1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
5 * Copyright (c) 2023, Linaro Limited
6 */
7
8 #include <linux/module.h>
9 #include <linux/slab.h>
10 #include <linux/platform_device.h>
11 #include <linux/device.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/kernel.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/component.h>
17 #include <sound/tlv.h>
18 #include <linux/of_graph.h>
19 #include <linux/of.h>
20 #include <sound/jack.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <linux/regmap.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/usb/typec_mux.h>
28 #include <linux/usb/typec_altmode.h>
29
30 #include "wcd-clsh-v2.h"
31 #include "wcd-mbhc-v2.h"
32 #include "wcd939x.h"
33
34 #define WCD939X_MAX_MICBIAS (4)
35 #define WCD939X_MBHC_MAX_BUTTONS (8)
36 #define TX_ADC_MAX (4)
37 #define WCD_MBHC_HS_V_MAX 1600
38
39 #define CHIPID_WCD9390 0x0
40 #define CHIPID_WCD9395 0x5
41
42 /* Version major: 1.x */
43 #define CHIPID_WCD939X_VER_MAJOR_1 0x0
44 /* Version minor: x.1 */
45 #define CHIPID_WCD939X_VER_MINOR_1 0x3
46
47 enum {
48 WCD939X_VERSION_1_0 = 0,
49 WCD939X_VERSION_1_1,
50 WCD939X_VERSION_2_0,
51 };
52
53 #define WCD939X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
54 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
55 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
56 SNDRV_PCM_RATE_384000)
57 /* Fractional Rates */
58 #define WCD939X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
59 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
60 #define WCD939X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
61 SNDRV_PCM_FMTBIT_S24_LE |\
62 SNDRV_PCM_FMTBIT_S24_3LE |\
63 SNDRV_PCM_FMTBIT_S32_LE)
64
65 /* Convert from vout ctl to micbias voltage in mV */
66 #define WCD_VOUT_CTL_TO_MICB(v) (1000 + (v) * 50)
67 #define SWR_CLK_RATE_0P6MHZ (600000)
68 #define SWR_CLK_RATE_1P2MHZ (1200000)
69 #define SWR_CLK_RATE_2P4MHZ (2400000)
70 #define SWR_CLK_RATE_4P8MHZ (4800000)
71 #define SWR_CLK_RATE_9P6MHZ (9600000)
72 #define SWR_CLK_RATE_11P2896MHZ (1128960)
73
74 #define ADC_MODE_VAL_HIFI 0x01
75 #define ADC_MODE_VAL_LO_HIF 0x02
76 #define ADC_MODE_VAL_NORMAL 0x03
77 #define ADC_MODE_VAL_LP 0x05
78 #define ADC_MODE_VAL_ULP1 0x09
79 #define ADC_MODE_VAL_ULP2 0x0B
80
81 /* Z value defined in milliohm */
82 #define WCD939X_ZDET_VAL_32 (32000)
83 #define WCD939X_ZDET_VAL_400 (400000)
84 #define WCD939X_ZDET_VAL_1200 (1200000)
85 #define WCD939X_ZDET_VAL_100K (100000000)
86
87 /* Z floating defined in ohms */
88 #define WCD939X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE)
89 #define WCD939X_ZDET_NUM_MEASUREMENTS (900)
90 #define WCD939X_MBHC_GET_C1(c) (((c) & 0xC000) >> 14)
91 #define WCD939X_MBHC_GET_X1(x) ((x) & 0x3FFF)
92
93 /* Z value compared in milliOhm */
94 #define WCD939X_ANA_MBHC_ZDET_CONST (1018 * 1024)
95
96 enum {
97 /* INTR_CTRL_INT_MASK_0 */
98 WCD939X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
99 WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET,
100 WCD939X_IRQ_MBHC_ELECT_INS_REM_DET,
101 WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
102 WCD939X_IRQ_MBHC_SW_DET,
103 WCD939X_IRQ_HPHR_OCP_INT,
104 WCD939X_IRQ_HPHR_CNP_INT,
105 WCD939X_IRQ_HPHL_OCP_INT,
106
107 /* INTR_CTRL_INT_MASK_1 */
108 WCD939X_IRQ_HPHL_CNP_INT,
109 WCD939X_IRQ_EAR_CNP_INT,
110 WCD939X_IRQ_EAR_SCD_INT,
111 WCD939X_IRQ_HPHL_PDM_WD_INT,
112 WCD939X_IRQ_HPHR_PDM_WD_INT,
113 WCD939X_IRQ_EAR_PDM_WD_INT,
114
115 /* INTR_CTRL_INT_MASK_2 */
116 WCD939X_IRQ_MBHC_MOISTURE_INT,
117 WCD939X_IRQ_HPHL_SURGE_DET_INT,
118 WCD939X_IRQ_HPHR_SURGE_DET_INT,
119 WCD939X_NUM_IRQS,
120 };
121
122 enum {
123 MICB_BIAS_DISABLE = 0,
124 MICB_BIAS_ENABLE,
125 MICB_BIAS_PULL_UP,
126 MICB_BIAS_PULL_DOWN,
127 };
128
129 enum {
130 WCD_ADC1 = 0,
131 WCD_ADC2,
132 WCD_ADC3,
133 WCD_ADC4,
134 HPH_PA_DELAY,
135 };
136
137 enum {
138 ADC_MODE_INVALID = 0,
139 ADC_MODE_HIFI,
140 ADC_MODE_LO_HIF,
141 ADC_MODE_NORMAL,
142 ADC_MODE_LP,
143 ADC_MODE_ULP1,
144 ADC_MODE_ULP2,
145 };
146
147 enum {
148 AIF1_PB = 0,
149 AIF1_CAP,
150 NUM_CODEC_DAIS,
151 };
152
153 static u8 tx_mode_bit[] = {
154 [ADC_MODE_INVALID] = 0x00,
155 [ADC_MODE_HIFI] = 0x01,
156 [ADC_MODE_LO_HIF] = 0x02,
157 [ADC_MODE_NORMAL] = 0x04,
158 [ADC_MODE_LP] = 0x08,
159 [ADC_MODE_ULP1] = 0x10,
160 [ADC_MODE_ULP2] = 0x20,
161 };
162
163 struct zdet_param {
164 u16 ldo_ctl;
165 u16 noff;
166 u16 nshift;
167 u16 btn5;
168 u16 btn6;
169 u16 btn7;
170 };
171
172 struct wcd939x_priv {
173 struct sdw_slave *tx_sdw_dev;
174 struct wcd939x_sdw_priv *sdw_priv[NUM_CODEC_DAIS];
175 struct device *txdev;
176 struct device *rxdev;
177 struct device_node *rxnode, *txnode;
178 struct regmap *regmap;
179 struct snd_soc_component *component;
180 /* micb setup lock */
181 struct mutex micb_lock;
182 /* typec handling */
183 bool typec_analog_mux;
184 #if IS_ENABLED(CONFIG_TYPEC)
185 enum typec_orientation typec_orientation;
186 unsigned long typec_mode;
187 struct typec_switch *typec_switch;
188 #endif /* CONFIG_TYPEC */
189 /* mbhc module */
190 struct wcd_mbhc *wcd_mbhc;
191 struct wcd_mbhc_config mbhc_cfg;
192 struct wcd_mbhc_intr intr_ids;
193 struct wcd_clsh_ctrl *clsh_info;
194 struct irq_domain *virq;
195 struct regmap_irq_chip_data *irq_chip;
196 struct snd_soc_jack *jack;
197 unsigned long status_mask;
198 s32 micb_ref[WCD939X_MAX_MICBIAS];
199 s32 pullup_ref[WCD939X_MAX_MICBIAS];
200 u32 hph_mode;
201 u32 tx_mode[TX_ADC_MAX];
202 int variant;
203 struct gpio_desc *reset_gpio;
204 u32 micb1_mv;
205 u32 micb2_mv;
206 u32 micb3_mv;
207 u32 micb4_mv;
208 int hphr_pdm_wd_int;
209 int hphl_pdm_wd_int;
210 int ear_pdm_wd_int;
211 bool comp1_enable;
212 bool comp2_enable;
213 bool ldoh;
214 };
215
216 static const char * const wcd939x_supplies[] = {
217 "vdd-rxtx", "vdd-io", "vdd-buck", "vdd-mic-bias", "vdd-px",
218 };
219
220 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
221 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
222 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
223
224 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
225 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD939X_ANA_MBHC_MECH, 0x80),
226 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD939X_ANA_MBHC_MECH, 0x40),
227 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD939X_ANA_MBHC_MECH, 0x20),
228 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD939X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
229 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD939X_ANA_MBHC_ELECT, 0x08),
230 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD939X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F),
231 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD939X_ANA_MBHC_MECH, 0x04),
232 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD939X_ANA_MBHC_MECH, 0x10),
233 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD939X_ANA_MBHC_MECH, 0x08),
234 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD939X_ANA_MBHC_MECH, 0x01),
235 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD939X_ANA_MBHC_ELECT, 0x06),
236 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD939X_ANA_MBHC_ELECT, 0x80),
237 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD939X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
238 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD939X_MBHC_NEW_CTL_1, 0x03),
239 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD939X_MBHC_NEW_CTL_2, 0x03),
240 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x08),
241 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD939X_ANA_MBHC_RESULT_3, 0x10),
242 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x20),
243 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x80),
244 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x40),
245 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD939X_HPH_OCP_CTL, 0x10),
246 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x07),
247 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD939X_ANA_MBHC_ELECT, 0x70),
248 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0xFF),
249 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD939X_ANA_MICB2, 0xC0),
250 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD939X_HPH_CNP_WG_TIME, 0xFF),
251 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD939X_ANA_HPH, 0x40),
252 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD939X_ANA_HPH, 0x80),
253 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD939X_ANA_HPH, 0xC0),
254 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD939X_ANA_MBHC_RESULT_3, 0x10),
255 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD939X_MBHC_CTL_BCS, 0x02),
256 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD939X_MBHC_NEW_FSM_STATUS, 0x01),
257 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD939X_MBHC_NEW_CTL_2, 0x70),
258 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD939X_MBHC_NEW_FSM_STATUS, 0x20),
259 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD939X_HPH_PA_CTL2, 0x40),
260 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD939X_HPH_PA_CTL2, 0x10),
261 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD939X_HPH_L_TEST, 0x01),
262 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD939X_HPH_R_TEST, 0x01),
263 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD939X_DIGITAL_INTR_STATUS_0, 0x80),
264 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD939X_DIGITAL_INTR_STATUS_0, 0x20),
265 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD939X_MBHC_NEW_CTL_1, 0x08),
266 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD939X_MBHC_NEW_FSM_STATUS, 0x40),
267 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD939X_MBHC_NEW_FSM_STATUS, 0x80),
268 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD939X_MBHC_NEW_ADC_RESULT, 0xFF),
269 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD939X_ANA_MICB2, 0x3F),
270 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD939X_MBHC_NEW_CTL_1, 0x10),
271 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD939X_MBHC_NEW_CTL_1, 0x04),
272 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD939X_ANA_MBHC_ZDET, 0x02),
273 };
274
275 static const struct regmap_irq wcd939x_irqs[WCD939X_NUM_IRQS] = {
276 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
277 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
278 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
279 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
280 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_SW_DET, 0, 0x10),
281 REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_OCP_INT, 0, 0x20),
282 REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_CNP_INT, 0, 0x40),
283 REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_OCP_INT, 0, 0x80),
284 REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_CNP_INT, 1, 0x01),
285 REGMAP_IRQ_REG(WCD939X_IRQ_EAR_CNP_INT, 1, 0x02),
286 REGMAP_IRQ_REG(WCD939X_IRQ_EAR_SCD_INT, 1, 0x04),
287 REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
288 REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
289 REGMAP_IRQ_REG(WCD939X_IRQ_EAR_PDM_WD_INT, 1, 0x80),
290 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
291 REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
292 REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
293 };
294
295 static const struct regmap_irq_chip wcd939x_regmap_irq_chip = {
296 .name = "wcd939x",
297 .irqs = wcd939x_irqs,
298 .num_irqs = ARRAY_SIZE(wcd939x_irqs),
299 .num_regs = 3,
300 .status_base = WCD939X_DIGITAL_INTR_STATUS_0,
301 .mask_base = WCD939X_DIGITAL_INTR_MASK_0,
302 .ack_base = WCD939X_DIGITAL_INTR_CLEAR_0,
303 .use_ack = 1,
304 .runtime_pm = true,
305 .irq_drv_data = NULL,
306 };
307
wcd939x_get_clk_rate(int mode)308 static int wcd939x_get_clk_rate(int mode)
309 {
310 int rate;
311
312 switch (mode) {
313 case ADC_MODE_ULP2:
314 rate = SWR_CLK_RATE_0P6MHZ;
315 break;
316 case ADC_MODE_ULP1:
317 rate = SWR_CLK_RATE_1P2MHZ;
318 break;
319 case ADC_MODE_LP:
320 rate = SWR_CLK_RATE_4P8MHZ;
321 break;
322 case ADC_MODE_NORMAL:
323 case ADC_MODE_LO_HIF:
324 case ADC_MODE_HIFI:
325 case ADC_MODE_INVALID:
326 default:
327 rate = SWR_CLK_RATE_9P6MHZ;
328 break;
329 }
330
331 return rate;
332 }
333
wcd939x_set_swr_clk_rate(struct snd_soc_component * component,int rate,int bank)334 static int wcd939x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank)
335 {
336 u8 mask = (bank ? 0xF0 : 0x0F);
337 u8 val = 0;
338
339 switch (rate) {
340 case SWR_CLK_RATE_0P6MHZ:
341 val = 6;
342 break;
343 case SWR_CLK_RATE_1P2MHZ:
344 val = 5;
345 break;
346 case SWR_CLK_RATE_2P4MHZ:
347 val = 3;
348 break;
349 case SWR_CLK_RATE_4P8MHZ:
350 val = 1;
351 break;
352 case SWR_CLK_RATE_9P6MHZ:
353 default:
354 val = 0;
355 break;
356 }
357
358 snd_soc_component_write_field(component, WCD939X_DIGITAL_SWR_TX_CLK_RATE, mask, val);
359
360 return 0;
361 }
362
wcd939x_io_init(struct snd_soc_component * component)363 static int wcd939x_io_init(struct snd_soc_component *component)
364 {
365 snd_soc_component_write_field(component, WCD939X_ANA_BIAS,
366 WCD939X_BIAS_ANALOG_BIAS_EN, true);
367 snd_soc_component_write_field(component, WCD939X_ANA_BIAS,
368 WCD939X_BIAS_PRECHRG_EN, true);
369
370 /* 10 msec delay as per HW requirement */
371 usleep_range(10000, 10010);
372 snd_soc_component_write_field(component, WCD939X_ANA_BIAS,
373 WCD939X_BIAS_PRECHRG_EN, false);
374
375 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L,
376 WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 0x15);
377 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R,
378 WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 0x15);
379 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL,
380 WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN, true);
381
382 snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2CASC_ULP,
383 WCD939X_FE_ICTRL_STG2CASC_ULP_ICTRL_SCBIAS_ULP0P6M, 1);
384 snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2CASC_ULP,
385 WCD939X_FE_ICTRL_STG2CASC_ULP_VALUE, 4);
386
387 snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2MAIN_ULP,
388 WCD939X_FE_ICTRL_STG2MAIN_ULP_VALUE, 8);
389
390 snd_soc_component_write_field(component, WCD939X_MICB1_TEST_CTL_1,
391 WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7);
392 snd_soc_component_write_field(component, WCD939X_MICB2_TEST_CTL_1,
393 WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7);
394 snd_soc_component_write_field(component, WCD939X_MICB3_TEST_CTL_1,
395 WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7);
396 snd_soc_component_write_field(component, WCD939X_MICB4_TEST_CTL_1,
397 WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7);
398 snd_soc_component_write_field(component, WCD939X_TX_3_4_TEST_BLK_EN2,
399 WCD939X_TEST_BLK_EN2_TXFE2_MBHC_CLKRST_EN, false);
400
401 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
402 WCD939X_EN_EN_SURGE_PROTECTION_HPHL, false);
403 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
404 WCD939X_EN_EN_SURGE_PROTECTION_HPHR, false);
405
406 snd_soc_component_write_field(component, WCD939X_HPH_OCP_CTL,
407 WCD939X_OCP_CTL_OCP_FSM_EN, true);
408 snd_soc_component_write_field(component, WCD939X_HPH_OCP_CTL,
409 WCD939X_OCP_CTL_SCD_OP_EN, true);
410
411 snd_soc_component_write(component, WCD939X_E_CFG0,
412 WCD939X_CFG0_IDLE_STEREO |
413 WCD939X_CFG0_AUTO_DISABLE_ANC);
414
415 return 0;
416 }
417
wcd939x_sdw_connect_port(const struct wcd939x_sdw_ch_info * ch_info,struct sdw_port_config * port_config,u8 enable)418 static int wcd939x_sdw_connect_port(const struct wcd939x_sdw_ch_info *ch_info,
419 struct sdw_port_config *port_config,
420 u8 enable)
421 {
422 u8 ch_mask, port_num;
423
424 port_num = ch_info->port_num;
425 ch_mask = ch_info->ch_mask;
426
427 port_config->num = port_num;
428
429 if (enable)
430 port_config->ch_mask |= ch_mask;
431 else
432 port_config->ch_mask &= ~ch_mask;
433
434 return 0;
435 }
436
wcd939x_connect_port(struct wcd939x_sdw_priv * wcd,u8 port_num,u8 ch_id,u8 enable)437 static int wcd939x_connect_port(struct wcd939x_sdw_priv *wcd, u8 port_num, u8 ch_id, u8 enable)
438 {
439 return wcd939x_sdw_connect_port(&wcd->ch_info[ch_id],
440 &wcd->port_config[port_num - 1],
441 enable);
442 }
443
wcd939x_codec_enable_rxclk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)444 static int wcd939x_codec_enable_rxclk(struct snd_soc_dapm_widget *w,
445 struct snd_kcontrol *kcontrol,
446 int event)
447 {
448 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
449
450 switch (event) {
451 case SND_SOC_DAPM_PRE_PMU:
452 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
453 WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE, true);
454
455 /* Analog path clock controls */
456 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
457 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN, true);
458 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
459 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN,
460 true);
461 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
462 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN,
463 true);
464
465 /* Digital path clock controls */
466 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
467 WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN, true);
468 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
469 WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN, true);
470 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
471 WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN, true);
472 break;
473 case SND_SOC_DAPM_POST_PMD:
474 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
475 WCD939X_RX_SUPPLIES_VNEG_EN, false);
476 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
477 WCD939X_RX_SUPPLIES_VPOS_EN, false);
478
479 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
480 WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN, false);
481 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
482 WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN, false);
483 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
484 WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN, false);
485
486 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
487 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN,
488 false);
489 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
490 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN,
491 false);
492 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
493 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN, false);
494
495 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
496 WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE, false);
497
498 break;
499 }
500
501 return 0;
502 }
503
wcd939x_codec_hphl_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)504 static int wcd939x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
505 struct snd_kcontrol *kcontrol,
506 int event)
507 {
508 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
509 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
510
511 switch (event) {
512 case SND_SOC_DAPM_PRE_PMU:
513 snd_soc_component_write_field(component, WCD939X_HPH_RDAC_CLK_CTL1,
514 WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN,
515 false);
516
517 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL,
518 WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN, true);
519 break;
520 case SND_SOC_DAPM_POST_PMU:
521 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L,
522 WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 0x1d);
523 if (wcd939x->comp1_enable) {
524 snd_soc_component_write_field(component,
525 WCD939X_DIGITAL_CDC_COMP_CTL_0,
526 WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN,
527 true);
528 /* 5msec compander delay as per HW requirement */
529 if (!wcd939x->comp2_enable ||
530 snd_soc_component_read_field(component,
531 WCD939X_DIGITAL_CDC_COMP_CTL_0,
532 WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN))
533 usleep_range(5000, 5010);
534
535 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1,
536 WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN,
537 false);
538 } else {
539 snd_soc_component_write_field(component,
540 WCD939X_DIGITAL_CDC_COMP_CTL_0,
541 WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN,
542 false);
543 snd_soc_component_write_field(component, WCD939X_HPH_L_EN,
544 WCD939X_L_EN_GAIN_SOURCE_SEL, true);
545 }
546 break;
547 case SND_SOC_DAPM_POST_PMD:
548 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L,
549 WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 1);
550 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL,
551 WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN, false);
552 break;
553 }
554
555 return 0;
556 }
557
wcd939x_codec_hphr_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)558 static int wcd939x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
559 struct snd_kcontrol *kcontrol,
560 int event)
561 {
562 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
563 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
564
565 dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
566 w->name, event);
567
568 switch (event) {
569 case SND_SOC_DAPM_PRE_PMU:
570 snd_soc_component_write_field(component, WCD939X_HPH_RDAC_CLK_CTL1,
571 WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN,
572 false);
573
574 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL,
575 WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN, true);
576 break;
577 case SND_SOC_DAPM_POST_PMU:
578 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R,
579 WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 0x1d);
580 if (wcd939x->comp2_enable) {
581 snd_soc_component_write_field(component,
582 WCD939X_DIGITAL_CDC_COMP_CTL_0,
583 WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN,
584 true);
585 /* 5msec compander delay as per HW requirement */
586 if (!wcd939x->comp1_enable ||
587 snd_soc_component_read_field(component,
588 WCD939X_DIGITAL_CDC_COMP_CTL_0,
589 WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN))
590 usleep_range(5000, 5010);
591 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1,
592 WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN,
593 false);
594 } else {
595 snd_soc_component_write_field(component,
596 WCD939X_DIGITAL_CDC_COMP_CTL_0,
597 WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN,
598 false);
599 snd_soc_component_write_field(component, WCD939X_HPH_R_EN,
600 WCD939X_R_EN_GAIN_SOURCE_SEL, true);
601 }
602 break;
603 case SND_SOC_DAPM_POST_PMD:
604 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R,
605 WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 1);
606 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL,
607 WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN, false);
608 break;
609 }
610
611 return 0;
612 }
613
wcd939x_codec_ear_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)614 static int wcd939x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
615 struct snd_kcontrol *kcontrol,
616 int event)
617 {
618 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
619 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
620
621 switch (event) {
622 case SND_SOC_DAPM_PRE_PMU:
623 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_EAR_GAIN_CTL,
624 WCD939X_CDC_EAR_GAIN_CTL_EAR_EN, true);
625
626 snd_soc_component_write_field(component, WCD939X_EAR_DAC_CON,
627 WCD939X_DAC_CON_DAC_SAMPLE_EDGE_SEL, false);
628
629 /* 5 msec delay as per HW requirement */
630 usleep_range(5000, 5010);
631 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
632 WCD_CLSH_STATE_EAR, CLS_AB_HIFI);
633
634 snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4,
635 WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd);
636 break;
637 case SND_SOC_DAPM_POST_PMD:
638 snd_soc_component_write_field(component, WCD939X_EAR_DAC_CON,
639 WCD939X_DAC_CON_DAC_SAMPLE_EDGE_SEL, true);
640 break;
641 }
642
643 return 0;
644 }
645
wcd939x_codec_enable_hphr_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)646 static int wcd939x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
647 struct snd_kcontrol *kcontrol,
648 int event)
649 {
650 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
651 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
652 int hph_mode = wcd939x->hph_mode;
653
654 switch (event) {
655 case SND_SOC_DAPM_PRE_PMU:
656 if (wcd939x->ldoh)
657 snd_soc_component_write_field(component, WCD939X_LDOH_MODE,
658 WCD939X_MODE_LDOH_EN, true);
659
660 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
661 WCD_CLSH_STATE_HPHR, hph_mode);
662 wcd_clsh_set_hph_mode(wcd939x->clsh_info, CLS_H_HIFI);
663
664 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || hph_mode == CLS_H_ULP)
665 snd_soc_component_write_field(component,
666 WCD939X_HPH_REFBUFF_LP_CTL,
667 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS, true);
668 if (hph_mode == CLS_H_LOHIFI)
669 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
670 WCD939X_HPH_PWR_LEVEL, 0);
671
672 snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4,
673 WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd);
674 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
675 WCD939X_HPH_HPHR_REF_ENABLE, true);
676
677 if (snd_soc_component_read_field(component, WCD939X_ANA_HPH,
678 WCD939X_HPH_HPHL_REF_ENABLE))
679 usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */
680
681 set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
682 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL1,
683 WCD939X_PDM_WD_CTL1_PDM_WD_EN, 3);
684 break;
685 case SND_SOC_DAPM_POST_PMU:
686 /*
687 * 7ms sleep is required if compander is enabled as per
688 * HW requirement. If compander is disabled, then
689 * 20ms delay is required.
690 */
691 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
692 if (!wcd939x->comp2_enable)
693 usleep_range(20000, 20100);
694 else
695 usleep_range(7000, 7100);
696
697 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
698 hph_mode == CLS_H_ULP)
699 snd_soc_component_write_field(component,
700 WCD939X_HPH_REFBUFF_LP_CTL,
701 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS,
702 false);
703 clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
704 }
705 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1,
706 WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN, true);
707 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
708 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
709 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
710 WCD939X_RX_SUPPLIES_REGULATOR_MODE,
711 true);
712
713 enable_irq(wcd939x->hphr_pdm_wd_int);
714 break;
715 case SND_SOC_DAPM_PRE_PMD:
716 disable_irq_nosync(wcd939x->hphr_pdm_wd_int);
717 /*
718 * 7ms sleep is required if compander is enabled as per
719 * HW requirement. If compander is disabled, then
720 * 20ms delay is required.
721 */
722 if (!wcd939x->comp2_enable)
723 usleep_range(20000, 20100);
724 else
725 usleep_range(7000, 7100);
726
727 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
728 WCD939X_HPH_HPHR_ENABLE, false);
729
730 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
731 WCD_EVENT_PRE_HPHR_PA_OFF);
732 set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
733 break;
734 case SND_SOC_DAPM_POST_PMD:
735 /*
736 * 7ms sleep is required if compander is enabled as per
737 * HW requirement. If compander is disabled, then
738 * 20ms delay is required.
739 */
740 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
741 if (!wcd939x->comp2_enable)
742 usleep_range(20000, 20100);
743 else
744 usleep_range(7000, 7100);
745 clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
746 }
747 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
748 WCD_EVENT_POST_HPHR_PA_OFF);
749
750 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
751 WCD939X_HPH_HPHR_REF_ENABLE, false);
752 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL1,
753 WCD939X_PDM_WD_CTL1_PDM_WD_EN, 0);
754
755 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA,
756 WCD_CLSH_STATE_HPHR, hph_mode);
757 if (wcd939x->ldoh)
758 snd_soc_component_write_field(component, WCD939X_LDOH_MODE,
759 WCD939X_MODE_LDOH_EN, false);
760 break;
761 }
762
763 return 0;
764 }
765
wcd939x_codec_enable_hphl_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)766 static int wcd939x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
767 struct snd_kcontrol *kcontrol,
768 int event)
769 {
770 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
771 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
772 int hph_mode = wcd939x->hph_mode;
773
774 dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
775 w->name, event);
776
777 switch (event) {
778 case SND_SOC_DAPM_PRE_PMU:
779 if (wcd939x->ldoh)
780 snd_soc_component_write_field(component, WCD939X_LDOH_MODE,
781 WCD939X_MODE_LDOH_EN, true);
782 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
783 WCD_CLSH_STATE_HPHL, hph_mode);
784 wcd_clsh_set_hph_mode(wcd939x->clsh_info, CLS_H_HIFI);
785
786 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || hph_mode == CLS_H_ULP)
787 snd_soc_component_write_field(component,
788 WCD939X_HPH_REFBUFF_LP_CTL,
789 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS,
790 true);
791 if (hph_mode == CLS_H_LOHIFI)
792 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
793 WCD939X_HPH_PWR_LEVEL, 0);
794
795 snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4,
796 WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd);
797 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
798 WCD939X_HPH_HPHL_REF_ENABLE, true);
799
800 if (snd_soc_component_read_field(component, WCD939X_ANA_HPH,
801 WCD939X_HPH_HPHR_REF_ENABLE))
802 usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */
803
804 set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
805 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0,
806 WCD939X_PDM_WD_CTL0_PDM_WD_EN, 3);
807 break;
808 case SND_SOC_DAPM_POST_PMU:
809 /*
810 * 7ms sleep is required if compander is enabled as per
811 * HW requirement. If compander is disabled, then
812 * 20ms delay is required.
813 */
814 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
815 if (!wcd939x->comp1_enable)
816 usleep_range(20000, 20100);
817 else
818 usleep_range(7000, 7100);
819 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
820 hph_mode == CLS_H_ULP)
821 snd_soc_component_write_field(component,
822 WCD939X_HPH_REFBUFF_LP_CTL,
823 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS,
824 false);
825 clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
826 }
827 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1,
828 WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN, true);
829 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
830 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
831 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
832 WCD939X_RX_SUPPLIES_REGULATOR_MODE,
833 true);
834 enable_irq(wcd939x->hphl_pdm_wd_int);
835 break;
836 case SND_SOC_DAPM_PRE_PMD:
837 disable_irq_nosync(wcd939x->hphl_pdm_wd_int);
838 /*
839 * 7ms sleep is required if compander is enabled as per
840 * HW requirement. If compander is disabled, then
841 * 20ms delay is required.
842 */
843 if (!wcd939x->comp1_enable)
844 usleep_range(20000, 20100);
845 else
846 usleep_range(7000, 7100);
847
848 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
849 WCD939X_HPH_HPHL_ENABLE, false);
850
851 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF);
852 set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
853 break;
854 case SND_SOC_DAPM_POST_PMD:
855 /*
856 * 7ms sleep is required if compander is enabled as per
857 * HW requirement. If compander is disabled, then
858 * 20ms delay is required.
859 */
860 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
861 if (!wcd939x->comp1_enable)
862 usleep_range(21000, 21100);
863 else
864 usleep_range(7000, 7100);
865 clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
866 }
867 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
868 WCD_EVENT_POST_HPHL_PA_OFF);
869 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
870 WCD939X_HPH_HPHL_REF_ENABLE, false);
871 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0,
872 WCD939X_PDM_WD_CTL0_PDM_WD_EN, 0);
873 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA,
874 WCD_CLSH_STATE_HPHL, hph_mode);
875 if (wcd939x->ldoh)
876 snd_soc_component_write_field(component, WCD939X_LDOH_MODE,
877 WCD939X_MODE_LDOH_EN, false);
878 break;
879 }
880
881 return 0;
882 }
883
wcd939x_codec_enable_ear_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)884 static int wcd939x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
885 struct snd_kcontrol *kcontrol, int event)
886 {
887 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
888 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
889
890 switch (event) {
891 case SND_SOC_DAPM_PRE_PMU:
892 /* Enable watchdog interrupt for HPHL */
893 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0,
894 WCD939X_PDM_WD_CTL0_PDM_WD_EN, 3);
895 /* For EAR, use CLASS_AB regulator mode */
896 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
897 WCD939X_RX_SUPPLIES_REGULATOR_MODE, true);
898 snd_soc_component_write_field(component, WCD939X_ANA_EAR_COMPANDER_CTL,
899 WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG, true);
900 break;
901 case SND_SOC_DAPM_POST_PMU:
902 /* 6 msec delay as per HW requirement */
903 usleep_range(6000, 6010);
904 enable_irq(wcd939x->ear_pdm_wd_int);
905 break;
906 case SND_SOC_DAPM_PRE_PMD:
907 disable_irq_nosync(wcd939x->ear_pdm_wd_int);
908 break;
909 case SND_SOC_DAPM_POST_PMD:
910 snd_soc_component_write_field(component, WCD939X_ANA_EAR_COMPANDER_CTL,
911 WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG,
912 false);
913 /* 7 msec delay as per HW requirement */
914 usleep_range(7000, 7010);
915 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0,
916 WCD939X_PDM_WD_CTL0_PDM_WD_EN, 0);
917 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA,
918 WCD_CLSH_STATE_EAR, CLS_AB_HIFI);
919 break;
920 }
921
922 return 0;
923 }
924
925 /* TX Controls */
926
wcd939x_codec_enable_dmic(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)927 static int wcd939x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
928 struct snd_kcontrol *kcontrol,
929 int event)
930 {
931 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
932 u16 dmic_clk_reg, dmic_clk_en_reg;
933 u8 dmic_clk_en_mask;
934 u8 dmic_ctl_mask;
935 u8 dmic_clk_mask;
936
937 switch (w->shift) {
938 case 0:
939 case 1:
940 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_1_2;
941 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC1_CTL;
942 dmic_clk_en_mask = WCD939X_CDC_DMIC1_CTL_DMIC_CLK_EN;
943 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_1_2_DMIC1_RATE;
944 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC1_IN_SEL;
945 break;
946 case 2:
947 case 3:
948 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_1_2;
949 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC2_CTL;
950 dmic_clk_en_mask = WCD939X_CDC_DMIC2_CTL_DMIC_CLK_EN;
951 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_1_2_DMIC2_RATE;
952 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC3_IN_SEL;
953 break;
954 case 4:
955 case 5:
956 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_3_4;
957 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC3_CTL;
958 dmic_clk_en_mask = WCD939X_CDC_DMIC3_CTL_DMIC_CLK_EN;
959 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_3_4_DMIC3_RATE;
960 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC4_IN_SEL;
961 break;
962 case 6:
963 case 7:
964 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_3_4;
965 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC4_CTL;
966 dmic_clk_en_mask = WCD939X_CDC_DMIC4_CTL_DMIC_CLK_EN;
967 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_3_4_DMIC4_RATE;
968 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC5_IN_SEL;
969 break;
970 default:
971 dev_err(component->dev, "%s: Invalid DMIC Selection\n", __func__);
972 return -EINVAL;
973 }
974
975 switch (event) {
976 case SND_SOC_DAPM_PRE_PMU:
977 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_AMIC_CTL,
978 dmic_ctl_mask, false);
979 /* 250us sleep as per HW requirement */
980 usleep_range(250, 260);
981 if (w->shift == 2)
982 snd_soc_component_write_field(component,
983 WCD939X_DIGITAL_CDC_DMIC2_CTL,
984 WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN,
985 true);
986 /* Setting DMIC clock rate to 2.4MHz */
987 snd_soc_component_write_field(component, dmic_clk_reg,
988 dmic_clk_mask, 3);
989 snd_soc_component_write_field(component, dmic_clk_en_reg,
990 dmic_clk_en_mask, true);
991 /* enable clock scaling */
992 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL,
993 WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN, true);
994 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL,
995 WCD939X_CDC_DMIC_CTL_DMIC_DIV_BAK_EN, true);
996 break;
997 case SND_SOC_DAPM_POST_PMD:
998 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_AMIC_CTL,
999 dmic_ctl_mask, 1);
1000 if (w->shift == 2)
1001 snd_soc_component_write_field(component,
1002 WCD939X_DIGITAL_CDC_DMIC2_CTL,
1003 WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN,
1004 false);
1005 snd_soc_component_write_field(component, dmic_clk_en_reg,
1006 dmic_clk_en_mask, 0);
1007 break;
1008 }
1009 return 0;
1010 }
1011
wcd939x_tx_swr_ctrl(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1012 static int wcd939x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
1013 struct snd_kcontrol *kcontrol, int event)
1014 {
1015 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1016 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1017 int bank;
1018 int rate;
1019
1020 bank = wcd939x_swr_get_current_bank(wcd939x->sdw_priv[AIF1_CAP]->sdev);
1021
1022 switch (event) {
1023 case SND_SOC_DAPM_PRE_PMU:
1024 if (strnstr(w->name, "ADC", sizeof("ADC"))) {
1025 int mode = 0;
1026
1027 if (test_bit(WCD_ADC1, &wcd939x->status_mask))
1028 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC1]];
1029 if (test_bit(WCD_ADC2, &wcd939x->status_mask))
1030 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC2]];
1031 if (test_bit(WCD_ADC3, &wcd939x->status_mask))
1032 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC3]];
1033 if (test_bit(WCD_ADC4, &wcd939x->status_mask))
1034 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC4]];
1035
1036 if (mode)
1037 rate = wcd939x_get_clk_rate(ffs(mode) - 1);
1038 else
1039 rate = wcd939x_get_clk_rate(ADC_MODE_INVALID);
1040 wcd939x_set_swr_clk_rate(component, rate, bank);
1041 wcd939x_set_swr_clk_rate(component, rate, !bank);
1042 }
1043 break;
1044 case SND_SOC_DAPM_POST_PMD:
1045 if (strnstr(w->name, "ADC", sizeof("ADC"))) {
1046 rate = wcd939x_get_clk_rate(ADC_MODE_INVALID);
1047 wcd939x_set_swr_clk_rate(component, rate, !bank);
1048 wcd939x_set_swr_clk_rate(component, rate, bank);
1049 }
1050 break;
1051 }
1052
1053 return 0;
1054 }
1055
wcd939x_get_adc_mode(int val)1056 static int wcd939x_get_adc_mode(int val)
1057 {
1058 int ret = 0;
1059
1060 switch (val) {
1061 case ADC_MODE_INVALID:
1062 ret = ADC_MODE_VAL_NORMAL;
1063 break;
1064 case ADC_MODE_HIFI:
1065 ret = ADC_MODE_VAL_HIFI;
1066 break;
1067 case ADC_MODE_LO_HIF:
1068 ret = ADC_MODE_VAL_LO_HIF;
1069 break;
1070 case ADC_MODE_NORMAL:
1071 ret = ADC_MODE_VAL_NORMAL;
1072 break;
1073 case ADC_MODE_LP:
1074 ret = ADC_MODE_VAL_LP;
1075 break;
1076 case ADC_MODE_ULP1:
1077 ret = ADC_MODE_VAL_ULP1;
1078 break;
1079 case ADC_MODE_ULP2:
1080 ret = ADC_MODE_VAL_ULP2;
1081 break;
1082 default:
1083 ret = -EINVAL;
1084 break;
1085 }
1086 return ret;
1087 }
1088
wcd939x_codec_enable_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1089 static int wcd939x_codec_enable_adc(struct snd_soc_dapm_widget *w,
1090 struct snd_kcontrol *kcontrol, int event)
1091 {
1092 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1093 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1094
1095 switch (event) {
1096 case SND_SOC_DAPM_PRE_PMU:
1097 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1098 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN, true);
1099 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1100 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN,
1101 true);
1102 set_bit(w->shift, &wcd939x->status_mask);
1103 break;
1104 case SND_SOC_DAPM_POST_PMD:
1105 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1106 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN,
1107 false);
1108 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1109 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN,
1110 false);
1111 clear_bit(w->shift, &wcd939x->status_mask);
1112 break;
1113 }
1114
1115 return 0;
1116 }
1117
wcd939x_tx_channel_config(struct snd_soc_component * component,int channel,bool init)1118 static void wcd939x_tx_channel_config(struct snd_soc_component *component,
1119 int channel, bool init)
1120 {
1121 int reg, mask;
1122
1123 switch (channel) {
1124 case 0:
1125 reg = WCD939X_ANA_TX_CH2;
1126 mask = WCD939X_TX_CH2_HPF1_INIT;
1127 break;
1128 case 1:
1129 reg = WCD939X_ANA_TX_CH2;
1130 mask = WCD939X_TX_CH2_HPF2_INIT;
1131 break;
1132 case 2:
1133 reg = WCD939X_ANA_TX_CH4;
1134 mask = WCD939X_TX_CH4_HPF3_INIT;
1135 break;
1136 case 3:
1137 reg = WCD939X_ANA_TX_CH4;
1138 mask = WCD939X_TX_CH4_HPF4_INIT;
1139 break;
1140 default:
1141 return;
1142 }
1143
1144 snd_soc_component_write_field(component, reg, mask, init);
1145 }
1146
wcd939x_adc_enable_req(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1147 static int wcd939x_adc_enable_req(struct snd_soc_dapm_widget *w,
1148 struct snd_kcontrol *kcontrol, int event)
1149 {
1150 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1151 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1152 int mode;
1153
1154 switch (event) {
1155 case SND_SOC_DAPM_PRE_PMU:
1156 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_REQ_CTL,
1157 WCD939X_CDC_REQ_CTL_FS_RATE_4P8, true);
1158 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_REQ_CTL,
1159 WCD939X_CDC_REQ_CTL_NO_NOTCH, false);
1160
1161 wcd939x_tx_channel_config(component, w->shift, true);
1162 mode = wcd939x_get_adc_mode(wcd939x->tx_mode[w->shift]);
1163 if (mode < 0) {
1164 dev_info(component->dev, "Invalid ADC mode\n");
1165 return -EINVAL;
1166 }
1167
1168 switch (w->shift) {
1169 case 0:
1170 snd_soc_component_write_field(component,
1171 WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1172 WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE,
1173 mode);
1174 snd_soc_component_write_field(component,
1175 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1176 WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN,
1177 true);
1178 break;
1179 case 1:
1180 snd_soc_component_write_field(component,
1181 WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1182 WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE,
1183 mode);
1184 snd_soc_component_write_field(component,
1185 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1186 WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN,
1187 true);
1188 break;
1189 case 2:
1190 snd_soc_component_write_field(component,
1191 WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1192 WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE,
1193 mode);
1194 snd_soc_component_write_field(component,
1195 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1196 WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN,
1197 true);
1198 break;
1199 case 3:
1200 snd_soc_component_write_field(component,
1201 WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1202 WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE,
1203 mode);
1204 snd_soc_component_write_field(component,
1205 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1206 WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN,
1207 true);
1208 break;
1209 default:
1210 break;
1211 }
1212
1213 wcd939x_tx_channel_config(component, w->shift, false);
1214 break;
1215 case SND_SOC_DAPM_POST_PMD:
1216 switch (w->shift) {
1217 case 0:
1218 snd_soc_component_write_field(component,
1219 WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1220 WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE,
1221 false);
1222 snd_soc_component_write_field(component,
1223 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1224 WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN,
1225 false);
1226 break;
1227 case 1:
1228 snd_soc_component_write_field(component,
1229 WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1230 WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE,
1231 false);
1232 snd_soc_component_write_field(component,
1233 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1234 WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN,
1235 false);
1236 break;
1237 case 2:
1238 snd_soc_component_write_field(component,
1239 WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1240 WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE,
1241 false);
1242 snd_soc_component_write_field(component,
1243 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1244 WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN,
1245 false);
1246 break;
1247 case 3:
1248 snd_soc_component_write_field(component,
1249 WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1250 WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE,
1251 false);
1252 snd_soc_component_write_field(component,
1253 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1254 WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN,
1255 false);
1256 break;
1257 default:
1258 break;
1259 }
1260 break;
1261 }
1262
1263 return 0;
1264 }
1265
wcd939x_micbias_control(struct snd_soc_component * component,int micb_num,int req,bool is_dapm)1266 static int wcd939x_micbias_control(struct snd_soc_component *component,
1267 int micb_num, int req, bool is_dapm)
1268 {
1269 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1270 int micb_index = micb_num - 1;
1271 u16 micb_reg;
1272
1273 switch (micb_num) {
1274 case MIC_BIAS_1:
1275 micb_reg = WCD939X_ANA_MICB1;
1276 break;
1277 case MIC_BIAS_2:
1278 micb_reg = WCD939X_ANA_MICB2;
1279 break;
1280 case MIC_BIAS_3:
1281 micb_reg = WCD939X_ANA_MICB3;
1282 break;
1283 case MIC_BIAS_4:
1284 micb_reg = WCD939X_ANA_MICB4;
1285 break;
1286 default:
1287 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
1288 __func__, micb_num);
1289 return -EINVAL;
1290 }
1291
1292 switch (req) {
1293 case MICB_PULLUP_ENABLE:
1294 wcd939x->pullup_ref[micb_index]++;
1295 if (wcd939x->pullup_ref[micb_index] == 1 &&
1296 wcd939x->micb_ref[micb_index] == 0)
1297 snd_soc_component_write_field(component, micb_reg,
1298 WCD939X_MICB_ENABLE,
1299 MICB_BIAS_PULL_UP);
1300 break;
1301 case MICB_PULLUP_DISABLE:
1302 if (wcd939x->pullup_ref[micb_index] > 0)
1303 wcd939x->pullup_ref[micb_index]--;
1304 if (wcd939x->pullup_ref[micb_index] == 0 &&
1305 wcd939x->micb_ref[micb_index] == 0)
1306 snd_soc_component_write_field(component, micb_reg,
1307 WCD939X_MICB_ENABLE,
1308 MICB_BIAS_DISABLE);
1309 break;
1310 case MICB_ENABLE:
1311 wcd939x->micb_ref[micb_index]++;
1312 if (wcd939x->micb_ref[micb_index] == 1) {
1313 snd_soc_component_write_field(component,
1314 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1315 WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN, true);
1316 snd_soc_component_write_field(component,
1317 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1318 WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN, true);
1319 snd_soc_component_write_field(component,
1320 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1321 WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN, true);
1322 snd_soc_component_write_field(component,
1323 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1324 WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN, true);
1325 snd_soc_component_write_field(component,
1326 WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1327 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN,
1328 true);
1329 snd_soc_component_write_field(component,
1330 WCD939X_DIGITAL_CDC_ANA_TX_CLK_CTL,
1331 WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TXSCBIAS_CLK_EN,
1332 true);
1333 snd_soc_component_write_field(component,
1334 WCD939X_MICB1_TEST_CTL_2,
1335 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true);
1336 snd_soc_component_write_field(component,
1337 WCD939X_MICB2_TEST_CTL_2,
1338 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true);
1339 snd_soc_component_write_field(component,
1340 WCD939X_MICB3_TEST_CTL_2,
1341 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true);
1342 snd_soc_component_write_field(component,
1343 WCD939X_MICB4_TEST_CTL_2,
1344 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true);
1345 snd_soc_component_write_field(component, micb_reg,
1346 WCD939X_MICB_ENABLE,
1347 MICB_BIAS_ENABLE);
1348 if (micb_num == MIC_BIAS_2)
1349 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1350 WCD_EVENT_POST_MICBIAS_2_ON);
1351 }
1352 if (micb_num == MIC_BIAS_2 && is_dapm)
1353 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1354 WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
1355 break;
1356 case MICB_DISABLE:
1357 if (wcd939x->micb_ref[micb_index] > 0)
1358 wcd939x->micb_ref[micb_index]--;
1359
1360 if (wcd939x->micb_ref[micb_index] == 0 &&
1361 wcd939x->pullup_ref[micb_index] > 0)
1362 snd_soc_component_write_field(component, micb_reg,
1363 WCD939X_MICB_ENABLE,
1364 MICB_BIAS_PULL_UP);
1365 else if (wcd939x->micb_ref[micb_index] == 0 &&
1366 wcd939x->pullup_ref[micb_index] == 0) {
1367 if (micb_num == MIC_BIAS_2)
1368 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1369 WCD_EVENT_PRE_MICBIAS_2_OFF);
1370
1371 snd_soc_component_write_field(component, micb_reg,
1372 WCD939X_MICB_ENABLE,
1373 MICB_BIAS_DISABLE);
1374 if (micb_num == MIC_BIAS_2)
1375 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1376 WCD_EVENT_POST_MICBIAS_2_OFF);
1377 }
1378 if (is_dapm && micb_num == MIC_BIAS_2)
1379 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1380 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
1381 break;
1382 }
1383
1384 return 0;
1385 }
1386
wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1387 static int wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
1388 struct snd_kcontrol *kcontrol,
1389 int event)
1390 {
1391 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1392 int micb_num = w->shift;
1393
1394 switch (event) {
1395 case SND_SOC_DAPM_PRE_PMU:
1396 wcd939x_micbias_control(component, micb_num, MICB_ENABLE, true);
1397 break;
1398 case SND_SOC_DAPM_POST_PMU:
1399 /* 1 msec delay as per HW requirement */
1400 usleep_range(1000, 1100);
1401 break;
1402 case SND_SOC_DAPM_POST_PMD:
1403 wcd939x_micbias_control(component, micb_num, MICB_DISABLE, true);
1404 break;
1405 }
1406
1407 return 0;
1408 }
1409
wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1410 static int wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
1411 struct snd_kcontrol *kcontrol,
1412 int event)
1413 {
1414 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1415 int micb_num = w->shift;
1416
1417 switch (event) {
1418 case SND_SOC_DAPM_PRE_PMU:
1419 wcd939x_micbias_control(component, micb_num,
1420 MICB_PULLUP_ENABLE, true);
1421 break;
1422 case SND_SOC_DAPM_POST_PMU:
1423 /* 1 msec delay as per HW requirement */
1424 usleep_range(1000, 1100);
1425 break;
1426 case SND_SOC_DAPM_POST_PMD:
1427 wcd939x_micbias_control(component, micb_num,
1428 MICB_PULLUP_DISABLE, true);
1429 break;
1430 }
1431
1432 return 0;
1433 }
1434
wcd939x_tx_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1435 static int wcd939x_tx_mode_get(struct snd_kcontrol *kcontrol,
1436 struct snd_ctl_elem_value *ucontrol)
1437 {
1438 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1439 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1440 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1441 int path = e->shift_l;
1442
1443 ucontrol->value.enumerated.item[0] = wcd939x->tx_mode[path];
1444
1445 return 0;
1446 }
1447
wcd939x_tx_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1448 static int wcd939x_tx_mode_put(struct snd_kcontrol *kcontrol,
1449 struct snd_ctl_elem_value *ucontrol)
1450 {
1451 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1452 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1453 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1454 int path = e->shift_l;
1455
1456 if (wcd939x->tx_mode[path] == ucontrol->value.enumerated.item[0])
1457 return 0;
1458
1459 wcd939x->tx_mode[path] = ucontrol->value.enumerated.item[0];
1460
1461 return 1;
1462 }
1463
1464 /* RX Controls */
1465
wcd939x_rx_hph_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1466 static int wcd939x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
1467 struct snd_ctl_elem_value *ucontrol)
1468 {
1469 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1470 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1471
1472 ucontrol->value.integer.value[0] = wcd939x->hph_mode;
1473
1474 return 0;
1475 }
1476
wcd939x_rx_hph_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1477 static int wcd939x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
1478 struct snd_ctl_elem_value *ucontrol)
1479 {
1480 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1481 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1482 u32 mode_val;
1483
1484 mode_val = ucontrol->value.enumerated.item[0];
1485
1486 if (mode_val == wcd939x->hph_mode)
1487 return 0;
1488
1489 if (wcd939x->variant == CHIPID_WCD9390) {
1490 switch (mode_val) {
1491 case CLS_H_NORMAL:
1492 case CLS_H_LP:
1493 case CLS_AB:
1494 case CLS_H_LOHIFI:
1495 case CLS_H_ULP:
1496 case CLS_AB_LP:
1497 case CLS_AB_LOHIFI:
1498 wcd939x->hph_mode = mode_val;
1499 return 1;
1500 }
1501 } else {
1502 switch (mode_val) {
1503 case CLS_H_NORMAL:
1504 case CLS_H_HIFI:
1505 case CLS_H_LP:
1506 case CLS_AB:
1507 case CLS_H_LOHIFI:
1508 case CLS_H_ULP:
1509 case CLS_AB_HIFI:
1510 case CLS_AB_LP:
1511 case CLS_AB_LOHIFI:
1512 wcd939x->hph_mode = mode_val;
1513 return 1;
1514 }
1515 }
1516
1517 dev_dbg(component->dev, "%s: Invalid HPH Mode\n", __func__);
1518 return -EINVAL;
1519 }
1520
wcd939x_get_compander(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1521 static int wcd939x_get_compander(struct snd_kcontrol *kcontrol,
1522 struct snd_ctl_elem_value *ucontrol)
1523 {
1524 struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value);
1525 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1526 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1527
1528 if (mc->shift)
1529 ucontrol->value.integer.value[0] = wcd939x->comp2_enable ? 1 : 0;
1530 else
1531 ucontrol->value.integer.value[0] = wcd939x->comp1_enable ? 1 : 0;
1532
1533 return 0;
1534 }
1535
wcd939x_set_compander(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1536 static int wcd939x_set_compander(struct snd_kcontrol *kcontrol,
1537 struct snd_ctl_elem_value *ucontrol)
1538 {
1539 struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value);
1540 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1541 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1542 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[AIF1_PB];
1543 bool value = !!ucontrol->value.integer.value[0];
1544 int portidx = wcd->ch_info[mc->reg].port_num;
1545
1546 if (mc->shift)
1547 wcd939x->comp2_enable = value;
1548 else
1549 wcd939x->comp1_enable = value;
1550
1551 if (value)
1552 wcd939x_connect_port(wcd, portidx, mc->reg, true);
1553 else
1554 wcd939x_connect_port(wcd, portidx, mc->reg, false);
1555
1556 return 1;
1557 }
1558
wcd939x_ldoh_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1559 static int wcd939x_ldoh_get(struct snd_kcontrol *kcontrol,
1560 struct snd_ctl_elem_value *ucontrol)
1561 {
1562 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1563 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1564
1565 ucontrol->value.integer.value[0] = wcd939x->ldoh ? 1 : 0;
1566
1567 return 0;
1568 }
1569
wcd939x_ldoh_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1570 static int wcd939x_ldoh_put(struct snd_kcontrol *kcontrol,
1571 struct snd_ctl_elem_value *ucontrol)
1572 {
1573 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1574 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1575
1576 if (wcd939x->ldoh == !!ucontrol->value.integer.value[0])
1577 return 0;
1578
1579 wcd939x->ldoh = !!ucontrol->value.integer.value[0];
1580
1581 return 1;
1582 }
1583
1584 static const char * const tx_mode_mux_text_wcd9390[] = {
1585 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
1586 };
1587
1588 static const struct soc_enum tx0_mode_mux_enum_wcd9390 =
1589 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9390),
1590 tx_mode_mux_text_wcd9390);
1591
1592 static const struct soc_enum tx1_mode_mux_enum_wcd9390 =
1593 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9390),
1594 tx_mode_mux_text_wcd9390);
1595
1596 static const struct soc_enum tx2_mode_mux_enum_wcd9390 =
1597 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9390),
1598 tx_mode_mux_text_wcd9390);
1599
1600 static const struct soc_enum tx3_mode_mux_enum_wcd9390 =
1601 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9390),
1602 tx_mode_mux_text_wcd9390);
1603
1604 static const char * const tx_mode_mux_text[] = {
1605 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
1606 "ADC_ULP1", "ADC_ULP2",
1607 };
1608
1609 static const struct soc_enum tx0_mode_mux_enum =
1610 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text),
1611 tx_mode_mux_text);
1612
1613 static const struct soc_enum tx1_mode_mux_enum =
1614 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text),
1615 tx_mode_mux_text);
1616
1617 static const struct soc_enum tx2_mode_mux_enum =
1618 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text),
1619 tx_mode_mux_text);
1620
1621 static const struct soc_enum tx3_mode_mux_enum =
1622 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text),
1623 tx_mode_mux_text);
1624
1625 static const char * const rx_hph_mode_mux_text_wcd9390[] = {
1626 "CLS_H_NORMAL", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
1627 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
1628 "CLS_AB_LOHIFI",
1629 };
1630
1631 static const struct soc_enum rx_hph_mode_mux_enum_wcd9390 =
1632 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9390),
1633 rx_hph_mode_mux_text_wcd9390);
1634
1635 static const char * const rx_hph_mode_mux_text[] = {
1636 "CLS_H_NORMAL", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
1637 "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
1638 };
1639
1640 static const struct soc_enum rx_hph_mode_mux_enum =
1641 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
1642 rx_hph_mode_mux_text);
1643
1644 static const struct snd_kcontrol_new wcd9390_snd_controls[] = {
1645 SOC_SINGLE_TLV("EAR_PA Volume", WCD939X_ANA_EAR_COMPANDER_CTL,
1646 2, 0x10, 0, ear_pa_gain),
1647
1648 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9390,
1649 wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
1650
1651 SOC_ENUM_EXT("TX0 MODE", tx0_mode_mux_enum_wcd9390,
1652 wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1653 SOC_ENUM_EXT("TX1 MODE", tx1_mode_mux_enum_wcd9390,
1654 wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1655 SOC_ENUM_EXT("TX2 MODE", tx2_mode_mux_enum_wcd9390,
1656 wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1657 SOC_ENUM_EXT("TX3 MODE", tx3_mode_mux_enum_wcd9390,
1658 wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1659 };
1660
1661 static const struct snd_kcontrol_new wcd9395_snd_controls[] = {
1662 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
1663 wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
1664
1665 SOC_ENUM_EXT("TX0 MODE", tx0_mode_mux_enum,
1666 wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1667 SOC_ENUM_EXT("TX1 MODE", tx1_mode_mux_enum,
1668 wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1669 SOC_ENUM_EXT("TX2 MODE", tx2_mode_mux_enum,
1670 wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1671 SOC_ENUM_EXT("TX3 MODE", tx3_mode_mux_enum,
1672 wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1673 };
1674
1675 static const struct snd_kcontrol_new adc1_switch[] = {
1676 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1677 };
1678
1679 static const struct snd_kcontrol_new adc2_switch[] = {
1680 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1681 };
1682
1683 static const struct snd_kcontrol_new adc3_switch[] = {
1684 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1685 };
1686
1687 static const struct snd_kcontrol_new adc4_switch[] = {
1688 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1689 };
1690
1691 static const struct snd_kcontrol_new dmic1_switch[] = {
1692 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1693 };
1694
1695 static const struct snd_kcontrol_new dmic2_switch[] = {
1696 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1697 };
1698
1699 static const struct snd_kcontrol_new dmic3_switch[] = {
1700 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1701 };
1702
1703 static const struct snd_kcontrol_new dmic4_switch[] = {
1704 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1705 };
1706
1707 static const struct snd_kcontrol_new dmic5_switch[] = {
1708 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1709 };
1710
1711 static const struct snd_kcontrol_new dmic6_switch[] = {
1712 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1713 };
1714
1715 static const struct snd_kcontrol_new dmic7_switch[] = {
1716 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1717 };
1718
1719 static const struct snd_kcontrol_new dmic8_switch[] = {
1720 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1721 };
1722
1723 static const struct snd_kcontrol_new ear_rdac_switch[] = {
1724 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1725 };
1726
1727 static const struct snd_kcontrol_new hphl_rdac_switch[] = {
1728 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1729 };
1730
1731 static const struct snd_kcontrol_new hphr_rdac_switch[] = {
1732 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1733 };
1734
1735 static const char * const adc1_mux_text[] = {
1736 "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4", "CH1_AMIC5"
1737 };
1738
1739 static const struct soc_enum adc1_enum =
1740 SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH12_MUX, 0,
1741 ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
1742
1743 static const struct snd_kcontrol_new tx_adc1_mux =
1744 SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
1745
1746 static const char * const adc2_mux_text[] = {
1747 "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4", "CH2_AMIC5"
1748 };
1749
1750 static const struct soc_enum adc2_enum =
1751 SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH12_MUX, 3,
1752 ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
1753
1754 static const struct snd_kcontrol_new tx_adc2_mux =
1755 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
1756
1757 static const char * const adc3_mux_text[] = {
1758 "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC3", "CH3_AMIC4", "CH3_AMIC5"
1759 };
1760
1761 static const struct soc_enum adc3_enum =
1762 SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH34_MUX, 0,
1763 ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
1764
1765 static const struct snd_kcontrol_new tx_adc3_mux =
1766 SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
1767
1768 static const char * const adc4_mux_text[] = {
1769 "CH4_AMIC_DISABLE", "CH4_AMIC1", "CH4_AMIC3", "CH4_AMIC4", "CH4_AMIC5"
1770 };
1771
1772 static const struct soc_enum adc4_enum =
1773 SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH34_MUX, 3,
1774 ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
1775
1776 static const struct snd_kcontrol_new tx_adc4_mux =
1777 SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
1778
1779 static const char * const rdac3_mux_text[] = {
1780 "RX3", "RX1"
1781 };
1782
1783 static const struct soc_enum rdac3_enum =
1784 SOC_ENUM_SINGLE(WCD939X_DIGITAL_CDC_EAR_PATH_CTL, 0,
1785 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
1786
1787 static const struct snd_kcontrol_new rx_rdac3_mux =
1788 SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
1789
wcd939x_get_swr_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1790 static int wcd939x_get_swr_port(struct snd_kcontrol *kcontrol,
1791 struct snd_ctl_elem_value *ucontrol)
1792 {
1793 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1794 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1795 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(comp);
1796 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[mixer->shift];
1797 unsigned int portidx = wcd->ch_info[mixer->reg].port_num;
1798
1799 ucontrol->value.integer.value[0] = wcd->port_enable[portidx] ? 1 : 0;
1800
1801 return 0;
1802 }
1803
version_to_str(u32 version)1804 static const char *version_to_str(u32 version)
1805 {
1806 switch (version) {
1807 case WCD939X_VERSION_1_0:
1808 return __stringify(WCD939X_1_0);
1809 case WCD939X_VERSION_1_1:
1810 return __stringify(WCD939X_1_1);
1811 case WCD939X_VERSION_2_0:
1812 return __stringify(WCD939X_2_0);
1813 }
1814 return NULL;
1815 }
1816
wcd939x_set_swr_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1817 static int wcd939x_set_swr_port(struct snd_kcontrol *kcontrol,
1818 struct snd_ctl_elem_value *ucontrol)
1819 {
1820 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1821 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1822 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(comp);
1823 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[mixer->shift];
1824 unsigned int portidx = wcd->ch_info[mixer->reg].port_num;
1825
1826 wcd->port_enable[portidx] = !!ucontrol->value.integer.value[0];
1827
1828 wcd939x_connect_port(wcd, portidx, mixer->reg, wcd->port_enable[portidx]);
1829
1830 return 1;
1831 }
1832
1833 /* MBHC Related */
1834
wcd939x_mbhc_clk_setup(struct snd_soc_component * component,bool enable)1835 static void wcd939x_mbhc_clk_setup(struct snd_soc_component *component,
1836 bool enable)
1837 {
1838 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_1,
1839 WCD939X_CTL_1_RCO_EN, enable);
1840 }
1841
wcd939x_mbhc_mbhc_bias_control(struct snd_soc_component * component,bool enable)1842 static void wcd939x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
1843 bool enable)
1844 {
1845 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT,
1846 WCD939X_MBHC_ELECT_BIAS_EN, enable);
1847 }
1848
wcd939x_mbhc_program_btn_thr(struct snd_soc_component * component,int * btn_low,int * btn_high,int num_btn,bool is_micbias)1849 static void wcd939x_mbhc_program_btn_thr(struct snd_soc_component *component,
1850 int *btn_low, int *btn_high,
1851 int num_btn, bool is_micbias)
1852 {
1853 int i, vth;
1854
1855 if (num_btn > WCD_MBHC_DEF_BUTTONS) {
1856 dev_err(component->dev, "%s: invalid number of buttons: %d\n",
1857 __func__, num_btn);
1858 return;
1859 }
1860
1861 for (i = 0; i < num_btn; i++) {
1862 vth = (btn_high[i] * 2) / 25;
1863 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_BTN0 + i,
1864 WCD939X_MBHC_BTN0_VTH, vth);
1865 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n",
1866 __func__, i, btn_high[i], vth);
1867 }
1868 }
1869
wcd939x_mbhc_micb_en_status(struct snd_soc_component * component,int micb_num)1870 static bool wcd939x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
1871 {
1872 if (micb_num == MIC_BIAS_2) {
1873 u8 val;
1874
1875 val = FIELD_GET(WCD939X_MICB_ENABLE,
1876 snd_soc_component_read(component, WCD939X_ANA_MICB2));
1877 if (val == MICB_BIAS_ENABLE)
1878 return true;
1879 }
1880
1881 return false;
1882 }
1883
wcd939x_mbhc_hph_l_pull_up_control(struct snd_soc_component * component,int pull_up_cur)1884 static void wcd939x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
1885 int pull_up_cur)
1886 {
1887 /* Default pull up current to 2uA */
1888 if (pull_up_cur > HS_PULLUP_I_OFF ||
1889 pull_up_cur < HS_PULLUP_I_3P0_UA ||
1890 pull_up_cur == HS_PULLUP_I_DEFAULT)
1891 pull_up_cur = HS_PULLUP_I_2P0_UA;
1892
1893 dev_dbg(component->dev, "%s: HS pull up current:%d\n",
1894 __func__, pull_up_cur);
1895
1896 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_INT_MECH_DET_CURRENT,
1897 WCD939X_MECH_DET_CURRENT_HSDET_PULLUP_CTL, pull_up_cur);
1898 }
1899
wcd939x_mbhc_request_micbias(struct snd_soc_component * component,int micb_num,int req)1900 static int wcd939x_mbhc_request_micbias(struct snd_soc_component *component,
1901 int micb_num, int req)
1902 {
1903 return wcd939x_micbias_control(component, micb_num, req, false);
1904 }
1905
wcd939x_mbhc_micb_ramp_control(struct snd_soc_component * component,bool enable)1906 static void wcd939x_mbhc_micb_ramp_control(struct snd_soc_component *component,
1907 bool enable)
1908 {
1909 if (enable) {
1910 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP,
1911 WCD939X_MICB2_RAMP_SHIFT_CTL, 3);
1912 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP,
1913 WCD939X_MICB2_RAMP_RAMP_ENABLE, true);
1914 } else {
1915 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP,
1916 WCD939X_MICB2_RAMP_RAMP_ENABLE, false);
1917 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP,
1918 WCD939X_MICB2_RAMP_SHIFT_CTL, 0);
1919 }
1920 }
1921
wcd939x_get_micb_vout_ctl_val(u32 micb_mv)1922 static int wcd939x_get_micb_vout_ctl_val(u32 micb_mv)
1923 {
1924 /* min micbias voltage is 1V and maximum is 2.85V */
1925 if (micb_mv < 1000 || micb_mv > 2850) {
1926 pr_err("%s: unsupported micbias voltage\n", __func__);
1927 return -EINVAL;
1928 }
1929
1930 return (micb_mv - 1000) / 50;
1931 }
1932
wcd939x_mbhc_micb_adjust_voltage(struct snd_soc_component * component,int req_volt,int micb_num)1933 static int wcd939x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
1934 int req_volt, int micb_num)
1935 {
1936 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1937 unsigned int micb_reg, cur_vout_ctl, micb_en;
1938 int req_vout_ctl;
1939 int ret = 0;
1940
1941 switch (micb_num) {
1942 case MIC_BIAS_1:
1943 micb_reg = WCD939X_ANA_MICB1;
1944 break;
1945 case MIC_BIAS_2:
1946 micb_reg = WCD939X_ANA_MICB2;
1947 break;
1948 case MIC_BIAS_3:
1949 micb_reg = WCD939X_ANA_MICB3;
1950 break;
1951 case MIC_BIAS_4:
1952 micb_reg = WCD939X_ANA_MICB4;
1953 break;
1954 default:
1955 return -EINVAL;
1956 }
1957 mutex_lock(&wcd939x->micb_lock);
1958
1959 /*
1960 * If requested micbias voltage is same as current micbias
1961 * voltage, then just return. Otherwise, adjust voltage as
1962 * per requested value. If micbias is already enabled, then
1963 * to avoid slow micbias ramp-up or down enable pull-up
1964 * momentarily, change the micbias value and then re-enable
1965 * micbias.
1966 */
1967 micb_en = snd_soc_component_read_field(component, micb_reg,
1968 WCD939X_MICB_ENABLE);
1969 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
1970 WCD939X_MICB_VOUT_CTL);
1971
1972 req_vout_ctl = wcd939x_get_micb_vout_ctl_val(req_volt);
1973 if (req_vout_ctl < 0) {
1974 ret = req_vout_ctl;
1975 goto exit;
1976 }
1977
1978 if (cur_vout_ctl == req_vout_ctl) {
1979 ret = 0;
1980 goto exit;
1981 }
1982
1983 dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
1984 __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
1985 req_volt, micb_en);
1986
1987 if (micb_en == MICB_BIAS_ENABLE)
1988 snd_soc_component_write_field(component, micb_reg,
1989 WCD939X_MICB_ENABLE,
1990 MICB_BIAS_PULL_DOWN);
1991
1992 snd_soc_component_write_field(component, micb_reg,
1993 WCD939X_MICB_VOUT_CTL, req_vout_ctl);
1994
1995 if (micb_en == MICB_BIAS_ENABLE) {
1996 snd_soc_component_write_field(component, micb_reg,
1997 WCD939X_MICB_ENABLE,
1998 MICB_BIAS_ENABLE);
1999 /*
2000 * Add 2ms delay as per HW requirement after enabling
2001 * micbias
2002 */
2003 usleep_range(2000, 2100);
2004 }
2005
2006 exit:
2007 mutex_unlock(&wcd939x->micb_lock);
2008 return ret;
2009 }
2010
wcd939x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component * component,int micb_num,bool req_en)2011 static int wcd939x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
2012 int micb_num, bool req_en)
2013 {
2014 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2015 int micb_mv;
2016
2017 if (micb_num != MIC_BIAS_2)
2018 return -EINVAL;
2019 /*
2020 * If device tree micbias level is already above the minimum
2021 * voltage needed to detect threshold microphone, then do
2022 * not change the micbias, just return.
2023 */
2024 if (wcd939x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
2025 return 0;
2026
2027 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd939x->micb2_mv;
2028
2029 return wcd939x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
2030 }
2031
2032 /* Selected by WCD939X_MBHC_GET_C1() */
2033 static const s16 wcd939x_wcd_mbhc_d1_a[4] = {
2034 0, 30, 30, 6
2035 };
2036
2037 /* Selected by zdet_param.noff */
2038 static const int wcd939x_mbhc_mincode_param[] = {
2039 3277, 1639, 820, 410, 205, 103, 52, 26
2040 };
2041
2042 static const struct zdet_param wcd939x_mbhc_zdet_param = {
2043 .ldo_ctl = 4,
2044 .noff = 0,
2045 .nshift = 6,
2046 .btn5 = 0x18,
2047 .btn6 = 0x60,
2048 .btn7 = 0x78,
2049 };
2050
wcd939x_mbhc_get_result_params(struct snd_soc_component * component,int32_t * zdet)2051 static void wcd939x_mbhc_get_result_params(struct snd_soc_component *component,
2052 int32_t *zdet)
2053 {
2054 const struct zdet_param *zdet_param = &wcd939x_mbhc_zdet_param;
2055 s32 x1, d1, denom;
2056 int val;
2057 s16 c1;
2058 int i;
2059
2060 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2061 WCD939X_MBHC_ZDET_ZDET_CHG_EN, true);
2062 for (i = 0; i < WCD939X_ZDET_NUM_MEASUREMENTS; i++) {
2063 val = snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_2,
2064 WCD939X_MBHC_RESULT_2_Z_RESULT_MSB);
2065 if (val & BIT(7))
2066 break;
2067 }
2068 val = val << 8;
2069 val |= snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_1,
2070 WCD939X_MBHC_RESULT_1_Z_RESULT_LSB);
2071 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2072 WCD939X_MBHC_ZDET_ZDET_CHG_EN, false);
2073 x1 = WCD939X_MBHC_GET_X1(val);
2074 c1 = WCD939X_MBHC_GET_C1(val);
2075
2076 /* If ramp is not complete, give additional 5ms */
2077 if (c1 < 2 && x1)
2078 mdelay(5);
2079
2080 if (!c1 || !x1) {
2081 dev_dbg(component->dev,
2082 "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
2083 __func__, c1, x1);
2084 goto ramp_down;
2085 }
2086
2087 d1 = wcd939x_wcd_mbhc_d1_a[c1];
2088 denom = (x1 * d1) - (1 << (14 - zdet_param->noff));
2089 if (denom > 0)
2090 *zdet = (WCD939X_ANA_MBHC_ZDET_CONST * 1000) / denom;
2091 else if (x1 < wcd939x_mbhc_mincode_param[zdet_param->noff])
2092 *zdet = WCD939X_ZDET_FLOATING_IMPEDANCE;
2093
2094 dev_dbg(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n",
2095 __func__, d1, c1, x1, *zdet);
2096 ramp_down:
2097 i = 0;
2098 while (x1) {
2099 val = snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_1,
2100 WCD939X_MBHC_RESULT_1_Z_RESULT_LSB) << 8;
2101 val |= snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_2,
2102 WCD939X_MBHC_RESULT_2_Z_RESULT_MSB);
2103 x1 = WCD939X_MBHC_GET_X1(val);
2104 i++;
2105 if (i == WCD939X_ZDET_NUM_MEASUREMENTS)
2106 break;
2107 }
2108 }
2109
wcd939x_mbhc_zdet_ramp(struct snd_soc_component * component,s32 * zl,int32_t * zr)2110 static void wcd939x_mbhc_zdet_ramp(struct snd_soc_component *component,
2111 s32 *zl, int32_t *zr)
2112 {
2113 const struct zdet_param *zdet_param = &wcd939x_mbhc_zdet_param;
2114 s32 zdet = 0;
2115
2116 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL,
2117 WCD939X_ZDET_ANA_CTL_MAXV_CTL, zdet_param->ldo_ctl);
2118 snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN5, WCD939X_MBHC_BTN5_VTH,
2119 zdet_param->btn5);
2120 snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN6, WCD939X_MBHC_BTN6_VTH,
2121 zdet_param->btn6);
2122 snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN7, WCD939X_MBHC_BTN7_VTH,
2123 zdet_param->btn7);
2124 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL,
2125 WCD939X_ZDET_ANA_CTL_RANGE_CTL, zdet_param->noff);
2126 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_RAMP_CTL,
2127 WCD939X_ZDET_RAMP_CTL_TIME_CTL, zdet_param->nshift);
2128 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_RAMP_CTL,
2129 WCD939X_ZDET_RAMP_CTL_ACC1_MIN_CTL, 6); /*acc1_min_63 */
2130
2131 if (!zl)
2132 goto z_right;
2133
2134 /* Start impedance measurement for HPH_L */
2135 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2136 WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN, true);
2137 dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n",
2138 __func__, zdet_param->noff);
2139 wcd939x_mbhc_get_result_params(component, &zdet);
2140 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2141 WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN, false);
2142
2143 *zl = zdet;
2144
2145 z_right:
2146 if (!zr)
2147 return;
2148
2149 /* Start impedance measurement for HPH_R */
2150 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2151 WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN, true);
2152 dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n",
2153 __func__, zdet_param->noff);
2154 wcd939x_mbhc_get_result_params(component, &zdet);
2155 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2156 WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN, false);
2157
2158 *zr = zdet;
2159 }
2160
wcd939x_wcd_mbhc_qfuse_cal(struct snd_soc_component * component,s32 * z_val,int flag_l_r)2161 static void wcd939x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
2162 s32 *z_val, int flag_l_r)
2163 {
2164 int q1_cal;
2165 s16 q1;
2166
2167 q1 = snd_soc_component_read(component, WCD939X_DIGITAL_EFUSE_REG_21 + flag_l_r);
2168 if (q1 & BIT(7))
2169 q1_cal = (10000 - ((q1 & GENMASK(6, 0)) * 10));
2170 else
2171 q1_cal = (10000 + (q1 * 10));
2172
2173 if (q1_cal > 0)
2174 *z_val = ((*z_val) * 10000) / q1_cal;
2175 }
2176
wcd939x_wcd_mbhc_calc_impedance(struct snd_soc_component * component,u32 * zl,uint32_t * zr)2177 static void wcd939x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
2178 u32 *zl, uint32_t *zr)
2179 {
2180 struct wcd939x_priv *wcd939x = dev_get_drvdata(component->dev);
2181 unsigned int reg0, reg1, reg2, reg3, reg4;
2182 int z_mono, z_diff1, z_diff2;
2183 bool is_fsm_disable = false;
2184 s32 z1l, z1r, z1ls;
2185
2186 reg0 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN5);
2187 reg1 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN6);
2188 reg2 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN7);
2189 reg3 = snd_soc_component_read(component, WCD939X_MBHC_CTL_CLK);
2190 reg4 = snd_soc_component_read(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL);
2191
2192 if (snd_soc_component_read_field(component, WCD939X_ANA_MBHC_ELECT,
2193 WCD939X_MBHC_ELECT_FSM_EN)) {
2194 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT,
2195 WCD939X_MBHC_ELECT_FSM_EN, false);
2196 is_fsm_disable = true;
2197 }
2198
2199 /* For NO-jack, disable L_DET_EN before Z-det measurements */
2200 if (wcd939x->mbhc_cfg.hphl_swh)
2201 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2202 WCD939X_MBHC_MECH_L_DET_EN, false);
2203
2204 /* Turn off 100k pull down on HPHL */
2205 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2206 WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND,
2207 false);
2208
2209 /*
2210 * Disable surge protection before impedance detection.
2211 * This is done to give correct value for high impedance.
2212 */
2213 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
2214 WCD939X_EN_EN_SURGE_PROTECTION_HPHR, false);
2215 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
2216 WCD939X_EN_EN_SURGE_PROTECTION_HPHL, false);
2217
2218 /* 1ms delay needed after disable surge protection */
2219 usleep_range(1000, 1010);
2220
2221 /* First get impedance on Left */
2222 wcd939x_mbhc_zdet_ramp(component, &z1l, NULL);
2223 if (z1l == WCD939X_ZDET_FLOATING_IMPEDANCE || z1l > WCD939X_ZDET_VAL_100K) {
2224 *zl = WCD939X_ZDET_FLOATING_IMPEDANCE;
2225 } else {
2226 *zl = z1l / 1000;
2227 wcd939x_wcd_mbhc_qfuse_cal(component, zl, 0);
2228 }
2229 dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
2230 __func__, *zl);
2231
2232 /* Start of right impedance ramp and calculation */
2233 wcd939x_mbhc_zdet_ramp(component, NULL, &z1r);
2234 if (z1r == WCD939X_ZDET_FLOATING_IMPEDANCE || z1r > WCD939X_ZDET_VAL_100K) {
2235 *zr = WCD939X_ZDET_FLOATING_IMPEDANCE;
2236 } else {
2237 *zr = z1r / 1000;
2238 wcd939x_wcd_mbhc_qfuse_cal(component, zr, 1);
2239 }
2240 dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
2241 __func__, *zr);
2242
2243 /* Mono/stereo detection */
2244 if (*zl == WCD939X_ZDET_FLOATING_IMPEDANCE &&
2245 *zr == WCD939X_ZDET_FLOATING_IMPEDANCE) {
2246 dev_dbg(component->dev,
2247 "%s: plug type is invalid or extension cable\n",
2248 __func__);
2249 goto zdet_complete;
2250 }
2251
2252 if (*zl == WCD939X_ZDET_FLOATING_IMPEDANCE ||
2253 *zr == WCD939X_ZDET_FLOATING_IMPEDANCE ||
2254 (*zl < WCD_MONO_HS_MIN_THR && *zr > WCD_MONO_HS_MIN_THR) ||
2255 (*zl > WCD_MONO_HS_MIN_THR && *zr < WCD_MONO_HS_MIN_THR)) {
2256 dev_dbg(component->dev,
2257 "%s: Mono plug type with one ch floating or shorted to GND\n",
2258 __func__);
2259 wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_MONO);
2260 goto zdet_complete;
2261 }
2262
2263 snd_soc_component_write_field(component, WCD939X_HPH_R_ATEST,
2264 WCD939X_R_ATEST_HPH_GND_OVR, true);
2265 snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2,
2266 WCD939X_PA_CTL2_HPHPA_GND_R, true);
2267 wcd939x_mbhc_zdet_ramp(component, &z1ls, NULL);
2268 snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2,
2269 WCD939X_PA_CTL2_HPHPA_GND_R, false);
2270 snd_soc_component_write_field(component, WCD939X_HPH_R_ATEST,
2271 WCD939X_R_ATEST_HPH_GND_OVR, false);
2272
2273 z1ls /= 1000;
2274 wcd939x_wcd_mbhc_qfuse_cal(component, &z1ls, 0);
2275
2276 /* Parallel of left Z and 9 ohm pull down resistor */
2277 z_mono = (*zl * 9) / (*zl + 9);
2278 z_diff1 = z1ls > z_mono ? z1ls - z_mono : z_mono - z1ls;
2279 z_diff2 = *zl > z1ls ? *zl - z1ls : z1ls - *zl;
2280 if ((z_diff1 * (*zl + z1ls)) > (z_diff2 * (z1ls + z_mono))) {
2281 dev_dbg(component->dev, "%s: stereo plug type detected\n",
2282 __func__);
2283 wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_STEREO);
2284 } else {
2285 dev_dbg(component->dev, "%s: MONO plug type detected\n",
2286 __func__);
2287 wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_MONO);
2288 }
2289
2290 /* Enable surge protection again after impedance detection */
2291 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
2292 WCD939X_EN_EN_SURGE_PROTECTION_HPHR, true);
2293 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
2294 WCD939X_EN_EN_SURGE_PROTECTION_HPHL, true);
2295
2296 zdet_complete:
2297 snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN5, reg0);
2298 snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN6, reg1);
2299 snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN7, reg2);
2300
2301 /* Turn on 100k pull down on HPHL */
2302 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2303 WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND, true);
2304
2305 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */
2306 if (wcd939x->mbhc_cfg.hphl_swh)
2307 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2308 WCD939X_MBHC_MECH_L_DET_EN, true);
2309
2310 snd_soc_component_write(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL, reg4);
2311 snd_soc_component_write(component, WCD939X_MBHC_CTL_CLK, reg3);
2312
2313 if (is_fsm_disable)
2314 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT,
2315 WCD939X_MBHC_ELECT_FSM_EN, true);
2316 }
2317
wcd939x_mbhc_gnd_det_ctrl(struct snd_soc_component * component,bool enable)2318 static void wcd939x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
2319 bool enable)
2320 {
2321 if (enable) {
2322 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2323 WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN,
2324 true);
2325 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2326 WCD939X_MBHC_MECH_GND_DET_EN, true);
2327 } else {
2328 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2329 WCD939X_MBHC_MECH_GND_DET_EN, false);
2330 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2331 WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN,
2332 false);
2333 }
2334 }
2335
wcd939x_mbhc_hph_pull_down_ctrl(struct snd_soc_component * component,bool enable)2336 static void wcd939x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
2337 bool enable)
2338 {
2339 snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2,
2340 WCD939X_PA_CTL2_HPHPA_GND_R, enable);
2341 snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2,
2342 WCD939X_PA_CTL2_HPHPA_GND_L, enable);
2343 }
2344
wcd939x_mbhc_moisture_config(struct snd_soc_component * component)2345 static void wcd939x_mbhc_moisture_config(struct snd_soc_component *component)
2346 {
2347 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2348
2349 if (wcd939x->mbhc_cfg.moist_rref == R_OFF || wcd939x->typec_analog_mux) {
2350 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2351 WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2352 return;
2353 }
2354
2355 /* Do not enable moisture detection if jack type is NC */
2356 if (!wcd939x->mbhc_cfg.hphl_swh) {
2357 dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
2358 __func__);
2359 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2360 WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2361 return;
2362 }
2363
2364 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2365 WCD939X_CTL_2_M_RTH_CTL, wcd939x->mbhc_cfg.moist_rref);
2366 }
2367
wcd939x_mbhc_moisture_detect_en(struct snd_soc_component * component,bool enable)2368 static void wcd939x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable)
2369 {
2370 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2371
2372 if (enable)
2373 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2374 WCD939X_CTL_2_M_RTH_CTL,
2375 wcd939x->mbhc_cfg.moist_rref);
2376 else
2377 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2378 WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2379 }
2380
wcd939x_mbhc_get_moisture_status(struct snd_soc_component * component)2381 static bool wcd939x_mbhc_get_moisture_status(struct snd_soc_component *component)
2382 {
2383 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2384 bool ret = false;
2385
2386 if (wcd939x->mbhc_cfg.moist_rref == R_OFF || wcd939x->typec_analog_mux) {
2387 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2388 WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2389 goto done;
2390 }
2391
2392 /* Do not enable moisture detection if jack type is NC */
2393 if (!wcd939x->mbhc_cfg.hphl_swh) {
2394 dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
2395 __func__);
2396 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2397 WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2398 goto done;
2399 }
2400
2401 /*
2402 * If moisture_en is already enabled, then skip to plug type
2403 * detection.
2404 */
2405 if (snd_soc_component_read_field(component, WCD939X_MBHC_NEW_CTL_2,
2406 WCD939X_CTL_2_M_RTH_CTL))
2407 goto done;
2408
2409 wcd939x_mbhc_moisture_detect_en(component, true);
2410
2411 /* Read moisture comparator status, invert of status bit */
2412 ret = !snd_soc_component_read_field(component, WCD939X_MBHC_NEW_FSM_STATUS,
2413 WCD939X_FSM_STATUS_HS_M_COMP_STATUS);
2414 done:
2415 return ret;
2416 }
2417
wcd939x_mbhc_moisture_polling_ctrl(struct snd_soc_component * component,bool enable)2418 static void wcd939x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component,
2419 bool enable)
2420 {
2421 snd_soc_component_write_field(component,
2422 WCD939X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,
2423 WCD939X_MOISTURE_DET_POLLING_CTRL_MOIST_EN_POLLING,
2424 enable);
2425 }
2426
2427 static const struct wcd_mbhc_cb mbhc_cb = {
2428 .clk_setup = wcd939x_mbhc_clk_setup,
2429 .mbhc_bias = wcd939x_mbhc_mbhc_bias_control,
2430 .set_btn_thr = wcd939x_mbhc_program_btn_thr,
2431 .micbias_enable_status = wcd939x_mbhc_micb_en_status,
2432 .hph_pull_up_control_v2 = wcd939x_mbhc_hph_l_pull_up_control,
2433 .mbhc_micbias_control = wcd939x_mbhc_request_micbias,
2434 .mbhc_micb_ramp_control = wcd939x_mbhc_micb_ramp_control,
2435 .mbhc_micb_ctrl_thr_mic = wcd939x_mbhc_micb_ctrl_threshold_mic,
2436 .compute_impedance = wcd939x_wcd_mbhc_calc_impedance,
2437 .mbhc_gnd_det_ctrl = wcd939x_mbhc_gnd_det_ctrl,
2438 .hph_pull_down_ctrl = wcd939x_mbhc_hph_pull_down_ctrl,
2439 .mbhc_moisture_config = wcd939x_mbhc_moisture_config,
2440 .mbhc_get_moisture_status = wcd939x_mbhc_get_moisture_status,
2441 .mbhc_moisture_polling_ctrl = wcd939x_mbhc_moisture_polling_ctrl,
2442 .mbhc_moisture_detect_en = wcd939x_mbhc_moisture_detect_en,
2443 };
2444
wcd939x_get_hph_type(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2445 static int wcd939x_get_hph_type(struct snd_kcontrol *kcontrol,
2446 struct snd_ctl_elem_value *ucontrol)
2447 {
2448 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2449 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2450
2451 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd939x->wcd_mbhc);
2452
2453 return 0;
2454 }
2455
wcd939x_hph_impedance_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2456 static int wcd939x_hph_impedance_get(struct snd_kcontrol *kcontrol,
2457 struct snd_ctl_elem_value *ucontrol)
2458 {
2459 struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value);
2460 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2461 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2462 bool hphr = mc->shift;
2463 u32 zl, zr;
2464
2465 wcd_mbhc_get_impedance(wcd939x->wcd_mbhc, &zl, &zr);
2466 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
2467 ucontrol->value.integer.value[0] = hphr ? zr : zl;
2468
2469 return 0;
2470 }
2471
2472 static const struct snd_kcontrol_new hph_type_detect_controls[] = {
2473 SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0,
2474 wcd939x_get_hph_type, NULL),
2475 };
2476
2477 static const struct snd_kcontrol_new impedance_detect_controls[] = {
2478 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0,
2479 wcd939x_hph_impedance_get, NULL),
2480 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0,
2481 wcd939x_hph_impedance_get, NULL),
2482 };
2483
wcd939x_mbhc_init(struct snd_soc_component * component)2484 static int wcd939x_mbhc_init(struct snd_soc_component *component)
2485 {
2486 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2487 struct wcd_mbhc_intr *intr_ids = &wcd939x->intr_ids;
2488
2489 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2490 WCD939X_IRQ_MBHC_SW_DET);
2491 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2492 WCD939X_IRQ_MBHC_BUTTON_PRESS_DET);
2493 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2494 WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET);
2495 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2496 WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
2497 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2498 WCD939X_IRQ_MBHC_ELECT_INS_REM_DET);
2499 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd939x->irq_chip,
2500 WCD939X_IRQ_HPHL_OCP_INT);
2501 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd939x->irq_chip,
2502 WCD939X_IRQ_HPHR_OCP_INT);
2503
2504 wcd939x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
2505 if (IS_ERR(wcd939x->wcd_mbhc))
2506 return PTR_ERR(wcd939x->wcd_mbhc);
2507
2508 snd_soc_add_component_controls(component, impedance_detect_controls,
2509 ARRAY_SIZE(impedance_detect_controls));
2510 snd_soc_add_component_controls(component, hph_type_detect_controls,
2511 ARRAY_SIZE(hph_type_detect_controls));
2512
2513 return 0;
2514 }
2515
wcd939x_mbhc_deinit(struct snd_soc_component * component)2516 static void wcd939x_mbhc_deinit(struct snd_soc_component *component)
2517 {
2518 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2519
2520 wcd_mbhc_deinit(wcd939x->wcd_mbhc);
2521 }
2522
2523 /* END MBHC */
2524
2525 static const struct snd_kcontrol_new wcd939x_snd_controls[] = {
2526 /* RX Path */
2527 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD939X_COMP_L, 0, 1, 0,
2528 wcd939x_get_compander, wcd939x_set_compander),
2529 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD939X_COMP_R, 1, 1, 0,
2530 wcd939x_get_compander, wcd939x_set_compander),
2531 SOC_SINGLE_EXT("HPHL Switch", WCD939X_HPH_L, 0, 1, 0,
2532 wcd939x_get_swr_port, wcd939x_set_swr_port),
2533 SOC_SINGLE_EXT("HPHR Switch", WCD939X_HPH_R, 0, 1, 0,
2534 wcd939x_get_swr_port, wcd939x_set_swr_port),
2535 SOC_SINGLE_EXT("CLSH Switch", WCD939X_CLSH, 0, 1, 0,
2536 wcd939x_get_swr_port, wcd939x_set_swr_port),
2537 SOC_SINGLE_EXT("LO Switch", WCD939X_LO, 0, 1, 0,
2538 wcd939x_get_swr_port, wcd939x_set_swr_port),
2539 SOC_SINGLE_EXT("DSD_L Switch", WCD939X_DSD_L, 0, 1, 0,
2540 wcd939x_get_swr_port, wcd939x_set_swr_port),
2541 SOC_SINGLE_EXT("DSD_R Switch", WCD939X_DSD_R, 0, 1, 0,
2542 wcd939x_get_swr_port, wcd939x_set_swr_port),
2543 SOC_SINGLE_TLV("HPHL Volume", WCD939X_HPH_L_EN, 0, 20, 1, line_gain),
2544 SOC_SINGLE_TLV("HPHR Volume", WCD939X_HPH_R_EN, 0, 20, 1, line_gain),
2545 SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0,
2546 wcd939x_ldoh_get, wcd939x_ldoh_put),
2547
2548 /* TX Path */
2549 SOC_SINGLE_EXT("ADC1 Switch", WCD939X_ADC1, 1, 1, 0,
2550 wcd939x_get_swr_port, wcd939x_set_swr_port),
2551 SOC_SINGLE_EXT("ADC2 Switch", WCD939X_ADC2, 1, 1, 0,
2552 wcd939x_get_swr_port, wcd939x_set_swr_port),
2553 SOC_SINGLE_EXT("ADC3 Switch", WCD939X_ADC3, 1, 1, 0,
2554 wcd939x_get_swr_port, wcd939x_set_swr_port),
2555 SOC_SINGLE_EXT("ADC4 Switch", WCD939X_ADC4, 1, 1, 0,
2556 wcd939x_get_swr_port, wcd939x_set_swr_port),
2557 SOC_SINGLE_EXT("DMIC0 Switch", WCD939X_DMIC0, 1, 1, 0,
2558 wcd939x_get_swr_port, wcd939x_set_swr_port),
2559 SOC_SINGLE_EXT("DMIC1 Switch", WCD939X_DMIC1, 1, 1, 0,
2560 wcd939x_get_swr_port, wcd939x_set_swr_port),
2561 SOC_SINGLE_EXT("MBHC Switch", WCD939X_MBHC, 1, 1, 0,
2562 wcd939x_get_swr_port, wcd939x_set_swr_port),
2563 SOC_SINGLE_EXT("DMIC2 Switch", WCD939X_DMIC2, 1, 1, 0,
2564 wcd939x_get_swr_port, wcd939x_set_swr_port),
2565 SOC_SINGLE_EXT("DMIC3 Switch", WCD939X_DMIC3, 1, 1, 0,
2566 wcd939x_get_swr_port, wcd939x_set_swr_port),
2567 SOC_SINGLE_EXT("DMIC4 Switch", WCD939X_DMIC4, 1, 1, 0,
2568 wcd939x_get_swr_port, wcd939x_set_swr_port),
2569 SOC_SINGLE_EXT("DMIC5 Switch", WCD939X_DMIC5, 1, 1, 0,
2570 wcd939x_get_swr_port, wcd939x_set_swr_port),
2571 SOC_SINGLE_EXT("DMIC6 Switch", WCD939X_DMIC6, 1, 1, 0,
2572 wcd939x_get_swr_port, wcd939x_set_swr_port),
2573 SOC_SINGLE_EXT("DMIC7 Switch", WCD939X_DMIC7, 1, 1, 0,
2574 wcd939x_get_swr_port, wcd939x_set_swr_port),
2575 SOC_SINGLE_TLV("ADC1 Volume", WCD939X_ANA_TX_CH1, 0, 20, 0,
2576 analog_gain),
2577 SOC_SINGLE_TLV("ADC2 Volume", WCD939X_ANA_TX_CH2, 0, 20, 0,
2578 analog_gain),
2579 SOC_SINGLE_TLV("ADC3 Volume", WCD939X_ANA_TX_CH3, 0, 20, 0,
2580 analog_gain),
2581 SOC_SINGLE_TLV("ADC4 Volume", WCD939X_ANA_TX_CH4, 0, 20, 0,
2582 analog_gain),
2583 };
2584
2585 static const struct snd_soc_dapm_widget wcd939x_dapm_widgets[] = {
2586 /*input widgets*/
2587 SND_SOC_DAPM_INPUT("AMIC1"),
2588 SND_SOC_DAPM_INPUT("AMIC2"),
2589 SND_SOC_DAPM_INPUT("AMIC3"),
2590 SND_SOC_DAPM_INPUT("AMIC4"),
2591 SND_SOC_DAPM_INPUT("AMIC5"),
2592
2593 SND_SOC_DAPM_MIC("Analog Mic1", NULL),
2594 SND_SOC_DAPM_MIC("Analog Mic2", NULL),
2595 SND_SOC_DAPM_MIC("Analog Mic3", NULL),
2596 SND_SOC_DAPM_MIC("Analog Mic4", NULL),
2597 SND_SOC_DAPM_MIC("Analog Mic5", NULL),
2598
2599 /* TX widgets */
2600 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
2601 wcd939x_codec_enable_adc,
2602 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2603 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
2604 wcd939x_codec_enable_adc,
2605 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2606 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
2607 wcd939x_codec_enable_adc,
2608 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2609 SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
2610 wcd939x_codec_enable_adc,
2611 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2612 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
2613 wcd939x_codec_enable_dmic,
2614 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2615 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
2616 wcd939x_codec_enable_dmic,
2617 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2618 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
2619 wcd939x_codec_enable_dmic,
2620 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2621 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
2622 wcd939x_codec_enable_dmic,
2623 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2624 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
2625 wcd939x_codec_enable_dmic,
2626 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2627 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
2628 wcd939x_codec_enable_dmic,
2629 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2630 SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
2631 wcd939x_codec_enable_dmic,
2632 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2633 SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
2634 wcd939x_codec_enable_dmic,
2635 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2636
2637 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, NULL, 0,
2638 wcd939x_adc_enable_req,
2639 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2640 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0, NULL, 0,
2641 wcd939x_adc_enable_req,
2642 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2643 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0, NULL, 0,
2644 wcd939x_adc_enable_req,
2645 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2646 SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0,
2647 wcd939x_adc_enable_req,
2648 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2649
2650 SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0, &tx_adc1_mux),
2651 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
2652 SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux),
2653 SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux),
2654
2655 /* tx mixers */
2656 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
2657 adc1_switch, ARRAY_SIZE(adc1_switch), wcd939x_tx_swr_ctrl,
2658 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2659 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
2660 adc2_switch, ARRAY_SIZE(adc2_switch), wcd939x_tx_swr_ctrl,
2661 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2662 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0,
2663 adc3_switch, ARRAY_SIZE(adc3_switch), wcd939x_tx_swr_ctrl,
2664 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2665 SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0,
2666 adc4_switch, ARRAY_SIZE(adc4_switch), wcd939x_tx_swr_ctrl,
2667 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2668 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0,
2669 dmic1_switch, ARRAY_SIZE(dmic1_switch), wcd939x_tx_swr_ctrl,
2670 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2671 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0,
2672 dmic2_switch, ARRAY_SIZE(dmic2_switch), wcd939x_tx_swr_ctrl,
2673 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2674 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0,
2675 dmic3_switch, ARRAY_SIZE(dmic3_switch), wcd939x_tx_swr_ctrl,
2676 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2677 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0,
2678 dmic4_switch, ARRAY_SIZE(dmic4_switch), wcd939x_tx_swr_ctrl,
2679 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2680 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0,
2681 dmic5_switch, ARRAY_SIZE(dmic5_switch), wcd939x_tx_swr_ctrl,
2682 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2683 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0,
2684 dmic6_switch, ARRAY_SIZE(dmic6_switch), wcd939x_tx_swr_ctrl,
2685 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2686 SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0,
2687 dmic7_switch, ARRAY_SIZE(dmic7_switch), wcd939x_tx_swr_ctrl,
2688 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2689 SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0,
2690 dmic8_switch, ARRAY_SIZE(dmic8_switch), wcd939x_tx_swr_ctrl,
2691 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2692
2693 /* micbias widgets */
2694 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
2695 wcd939x_codec_enable_micbias,
2696 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2697 SND_SOC_DAPM_POST_PMD),
2698 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
2699 wcd939x_codec_enable_micbias,
2700 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2701 SND_SOC_DAPM_POST_PMD),
2702 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
2703 wcd939x_codec_enable_micbias,
2704 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2705 SND_SOC_DAPM_POST_PMD),
2706 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
2707 wcd939x_codec_enable_micbias,
2708 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2709 SND_SOC_DAPM_POST_PMD),
2710
2711 /* micbias pull up widgets */
2712 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
2713 wcd939x_codec_enable_micbias_pullup,
2714 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2715 SND_SOC_DAPM_POST_PMD),
2716 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
2717 wcd939x_codec_enable_micbias_pullup,
2718 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2719 SND_SOC_DAPM_POST_PMD),
2720 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
2721 wcd939x_codec_enable_micbias_pullup,
2722 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2723 SND_SOC_DAPM_POST_PMD),
2724 SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
2725 wcd939x_codec_enable_micbias_pullup,
2726 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2727 SND_SOC_DAPM_POST_PMD),
2728
2729 /* output widgets tx */
2730 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
2731 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
2732 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
2733 SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
2734 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
2735 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
2736 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
2737 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
2738 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
2739 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
2740 SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
2741 SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
2742
2743 SND_SOC_DAPM_INPUT("IN1_HPHL"),
2744 SND_SOC_DAPM_INPUT("IN2_HPHR"),
2745 SND_SOC_DAPM_INPUT("IN3_EAR"),
2746
2747 /* rx widgets */
2748 SND_SOC_DAPM_PGA_E("EAR PGA", WCD939X_ANA_EAR, 7, 0, NULL, 0,
2749 wcd939x_codec_enable_ear_pa,
2750 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2751 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2752 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD939X_ANA_HPH, 7, 0, NULL, 0,
2753 wcd939x_codec_enable_hphl_pa,
2754 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2755 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2756 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD939X_ANA_HPH, 6, 0, NULL, 0,
2757 wcd939x_codec_enable_hphr_pa,
2758 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2759 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2760
2761 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
2762 wcd939x_codec_hphl_dac_event,
2763 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2764 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2765 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
2766 wcd939x_codec_hphr_dac_event,
2767 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2768 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2769 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
2770 wcd939x_codec_ear_dac_event,
2771 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2772 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2773
2774 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
2775
2776 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0),
2777 SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0,
2778 wcd939x_codec_enable_rxclk,
2779 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2780 SND_SOC_DAPM_POST_PMD),
2781
2782 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0),
2783
2784 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2785 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2786 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2787
2788 /* rx mixer widgets */
2789 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
2790 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
2791 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
2792 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
2793 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
2794 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
2795
2796 /* output widgets rx */
2797 SND_SOC_DAPM_OUTPUT("EAR"),
2798 SND_SOC_DAPM_OUTPUT("HPHL"),
2799 SND_SOC_DAPM_OUTPUT("HPHR"),
2800 };
2801
2802 static const struct snd_soc_dapm_route wcd939x_audio_map[] = {
2803 /* TX Path */
2804 {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
2805 {"ADC1_MIXER", "Switch", "ADC1 REQ"},
2806 {"ADC1 REQ", NULL, "ADC1"},
2807 {"ADC1", NULL, "ADC1 MUX"},
2808 {"ADC1 MUX", "CH1_AMIC1", "AMIC1"},
2809 {"ADC1 MUX", "CH1_AMIC2", "AMIC2"},
2810 {"ADC1 MUX", "CH1_AMIC3", "AMIC3"},
2811 {"ADC1 MUX", "CH1_AMIC4", "AMIC4"},
2812 {"ADC1 MUX", "CH1_AMIC5", "AMIC5"},
2813
2814 {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
2815 {"ADC2_MIXER", "Switch", "ADC2 REQ"},
2816 {"ADC2 REQ", NULL, "ADC2"},
2817 {"ADC2", NULL, "ADC2 MUX"},
2818 {"ADC2 MUX", "CH2_AMIC1", "AMIC1"},
2819 {"ADC2 MUX", "CH2_AMIC2", "AMIC2"},
2820 {"ADC2 MUX", "CH2_AMIC3", "AMIC3"},
2821 {"ADC2 MUX", "CH2_AMIC4", "AMIC4"},
2822 {"ADC2 MUX", "CH2_AMIC5", "AMIC5"},
2823
2824 {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
2825 {"ADC3_MIXER", "Switch", "ADC3 REQ"},
2826 {"ADC3 REQ", NULL, "ADC3"},
2827 {"ADC3", NULL, "ADC3 MUX"},
2828 {"ADC3 MUX", "CH3_AMIC1", "AMIC1"},
2829 {"ADC3 MUX", "CH3_AMIC3", "AMIC3"},
2830 {"ADC3 MUX", "CH3_AMIC4", "AMIC4"},
2831 {"ADC3 MUX", "CH3_AMIC5", "AMIC5"},
2832
2833 {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
2834 {"ADC4_MIXER", "Switch", "ADC4 REQ"},
2835 {"ADC4 REQ", NULL, "ADC4"},
2836 {"ADC4", NULL, "ADC4 MUX"},
2837 {"ADC4 MUX", "CH4_AMIC1", "AMIC1"},
2838 {"ADC4 MUX", "CH4_AMIC3", "AMIC3"},
2839 {"ADC4 MUX", "CH4_AMIC4", "AMIC4"},
2840 {"ADC4 MUX", "CH4_AMIC5", "AMIC5"},
2841
2842 {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
2843 {"DMIC1_MIXER", "Switch", "DMIC1"},
2844
2845 {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
2846 {"DMIC2_MIXER", "Switch", "DMIC2"},
2847
2848 {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
2849 {"DMIC3_MIXER", "Switch", "DMIC3"},
2850
2851 {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
2852 {"DMIC4_MIXER", "Switch", "DMIC4"},
2853
2854 {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
2855 {"DMIC5_MIXER", "Switch", "DMIC5"},
2856
2857 {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
2858 {"DMIC6_MIXER", "Switch", "DMIC6"},
2859
2860 {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
2861 {"DMIC7_MIXER", "Switch", "DMIC7"},
2862
2863 {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
2864 {"DMIC8_MIXER", "Switch", "DMIC8"},
2865
2866 /* RX Path */
2867 {"IN1_HPHL", NULL, "VDD_BUCK"},
2868 {"IN1_HPHL", NULL, "CLS_H_PORT"},
2869
2870 {"RX1", NULL, "IN1_HPHL"},
2871 {"RX1", NULL, "RXCLK"},
2872 {"RDAC1", NULL, "RX1"},
2873 {"HPHL_RDAC", "Switch", "RDAC1"},
2874 {"HPHL PGA", NULL, "HPHL_RDAC"},
2875 {"HPHL", NULL, "HPHL PGA"},
2876
2877 {"IN2_HPHR", NULL, "VDD_BUCK"},
2878 {"IN2_HPHR", NULL, "CLS_H_PORT"},
2879 {"RX2", NULL, "IN2_HPHR"},
2880 {"RDAC2", NULL, "RX2"},
2881 {"RX2", NULL, "RXCLK"},
2882 {"HPHR_RDAC", "Switch", "RDAC2"},
2883 {"HPHR PGA", NULL, "HPHR_RDAC"},
2884 {"HPHR", NULL, "HPHR PGA"},
2885
2886 {"IN3_EAR", NULL, "VDD_BUCK"},
2887 {"RX3", NULL, "IN3_EAR"},
2888 {"RX3", NULL, "RXCLK"},
2889
2890 {"RDAC3_MUX", "RX3", "RX3"},
2891 {"RDAC3_MUX", "RX1", "RX1"},
2892 {"RDAC3", NULL, "RDAC3_MUX"},
2893 {"EAR_RDAC", "Switch", "RDAC3"},
2894 {"EAR PGA", NULL, "EAR_RDAC"},
2895 {"EAR", NULL, "EAR PGA"},
2896 };
2897
wcd939x_set_micbias_data(struct wcd939x_priv * wcd939x)2898 static int wcd939x_set_micbias_data(struct wcd939x_priv *wcd939x)
2899 {
2900 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
2901
2902 /* set micbias voltage */
2903 vout_ctl_1 = wcd939x_get_micb_vout_ctl_val(wcd939x->micb1_mv);
2904 vout_ctl_2 = wcd939x_get_micb_vout_ctl_val(wcd939x->micb2_mv);
2905 vout_ctl_3 = wcd939x_get_micb_vout_ctl_val(wcd939x->micb3_mv);
2906 vout_ctl_4 = wcd939x_get_micb_vout_ctl_val(wcd939x->micb4_mv);
2907 if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0)
2908 return -EINVAL;
2909
2910 regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB1,
2911 WCD939X_MICB_VOUT_CTL, vout_ctl_1);
2912 regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB2,
2913 WCD939X_MICB_VOUT_CTL, vout_ctl_2);
2914 regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB3,
2915 WCD939X_MICB_VOUT_CTL, vout_ctl_3);
2916 regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB4,
2917 WCD939X_MICB_VOUT_CTL, vout_ctl_4);
2918
2919 return 0;
2920 }
2921
wcd939x_wd_handle_irq(int irq,void * data)2922 static irqreturn_t wcd939x_wd_handle_irq(int irq, void *data)
2923 {
2924 /*
2925 * HPHR/HPHL/EAR Watchdog interrupt threaded handler
2926 *
2927 * Watchdog interrupts are expected to be enabled when switching
2928 * on the HPHL/R and EAR RX PGA in order to make sure the interrupts
2929 * are acked by the regmap_irq handler to allow PDM sync.
2930 * We could leave those interrupts masked but we would not have
2931 * any valid way to enable/disable them without violating irq layers.
2932 *
2933 * The HPHR/HPHL/EAR Watchdog interrupts are handled
2934 * by regmap_irq, so requesting a threaded handler is the
2935 * safest way to be able to ack those interrupts without
2936 * colliding with the regmap_irq setup.
2937 */
2938
2939 return IRQ_HANDLED;
2940 }
2941
2942 /*
2943 * Setup a virtual interrupt domain to hook regmap_irq
2944 * The root domain will have a single interrupt which mapping
2945 * will trigger the regmap_irq handler.
2946 *
2947 * root:
2948 * wcd_irq_chip
2949 * [0] wcd939x_regmap_irq_chip
2950 * [0] MBHC_BUTTON_PRESS_DET
2951 * [1] MBHC_BUTTON_RELEASE_DET
2952 * ...
2953 * [16] HPHR_SURGE_DET_INT
2954 *
2955 * Interrupt trigger:
2956 * soundwire_interrupt_callback()
2957 * \-handle_nested_irq(0)
2958 * \- regmap_irq_thread()
2959 * \- handle_nested_irq(i)
2960 */
2961 static const struct irq_chip wcd_irq_chip = {
2962 .name = "WCD939x",
2963 };
2964
wcd_irq_chip_map(struct irq_domain * irqd,unsigned int virq,irq_hw_number_t hw)2965 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq,
2966 irq_hw_number_t hw)
2967 {
2968 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq);
2969 irq_set_nested_thread(virq, 1);
2970 irq_set_noprobe(virq);
2971
2972 return 0;
2973 }
2974
2975 static const struct irq_domain_ops wcd_domain_ops = {
2976 .map = wcd_irq_chip_map,
2977 };
2978
wcd939x_irq_init(struct wcd939x_priv * wcd,struct device * dev)2979 static int wcd939x_irq_init(struct wcd939x_priv *wcd, struct device *dev)
2980 {
2981 wcd->virq = irq_domain_create_linear(NULL, 1, &wcd_domain_ops, NULL);
2982 if (!(wcd->virq)) {
2983 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__);
2984 return -EINVAL;
2985 }
2986
2987 return devm_regmap_add_irq_chip(dev, wcd->regmap,
2988 irq_create_mapping(wcd->virq, 0),
2989 IRQF_ONESHOT, 0, &wcd939x_regmap_irq_chip,
2990 &wcd->irq_chip);
2991 }
2992
wcd939x_soc_codec_probe(struct snd_soc_component * component)2993 static int wcd939x_soc_codec_probe(struct snd_soc_component *component)
2994 {
2995 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2996 struct sdw_slave *tx_sdw_dev = wcd939x->tx_sdw_dev;
2997 struct device *dev = component->dev;
2998 unsigned long time_left;
2999 int ret, i;
3000
3001 time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete,
3002 msecs_to_jiffies(2000));
3003 if (!time_left) {
3004 dev_err(dev, "soundwire device init timeout\n");
3005 return -ETIMEDOUT;
3006 }
3007
3008 snd_soc_component_init_regmap(component, wcd939x->regmap);
3009
3010 ret = pm_runtime_resume_and_get(dev);
3011 if (ret < 0)
3012 return ret;
3013
3014 wcd939x->variant = snd_soc_component_read_field(component,
3015 WCD939X_DIGITAL_EFUSE_REG_0,
3016 WCD939X_EFUSE_REG_0_WCD939X_ID);
3017
3018 wcd939x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD939X);
3019 if (IS_ERR(wcd939x->clsh_info)) {
3020 pm_runtime_put(dev);
3021 return PTR_ERR(wcd939x->clsh_info);
3022 }
3023
3024 wcd939x_io_init(component);
3025
3026 /* Set all interrupts as edge triggered */
3027 for (i = 0; i < wcd939x_regmap_irq_chip.num_regs; i++)
3028 regmap_write(wcd939x->regmap,
3029 (WCD939X_DIGITAL_INTR_LEVEL_0 + i), 0);
3030
3031 pm_runtime_put(dev);
3032
3033 /* Request for watchdog interrupt */
3034 wcd939x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip,
3035 WCD939X_IRQ_HPHR_PDM_WD_INT);
3036 wcd939x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip,
3037 WCD939X_IRQ_HPHL_PDM_WD_INT);
3038 wcd939x->ear_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip,
3039 WCD939X_IRQ_EAR_PDM_WD_INT);
3040
3041 ret = request_threaded_irq(wcd939x->hphr_pdm_wd_int, NULL, wcd939x_wd_handle_irq,
3042 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3043 "HPHR PDM WD INT", wcd939x);
3044 if (ret) {
3045 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret);
3046 goto err_free_clsh_ctrl;
3047 }
3048
3049 ret = request_threaded_irq(wcd939x->hphl_pdm_wd_int, NULL, wcd939x_wd_handle_irq,
3050 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3051 "HPHL PDM WD INT", wcd939x);
3052 if (ret) {
3053 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret);
3054 goto err_free_hphr_pdm_wd_int;
3055 }
3056
3057 ret = request_threaded_irq(wcd939x->ear_pdm_wd_int, NULL, wcd939x_wd_handle_irq,
3058 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3059 "AUX PDM WD INT", wcd939x);
3060 if (ret) {
3061 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret);
3062 goto err_free_hphl_pdm_wd_int;
3063 }
3064
3065 /* Disable watchdog interrupt for HPH and AUX */
3066 disable_irq_nosync(wcd939x->hphr_pdm_wd_int);
3067 disable_irq_nosync(wcd939x->hphl_pdm_wd_int);
3068 disable_irq_nosync(wcd939x->ear_pdm_wd_int);
3069
3070 switch (wcd939x->variant) {
3071 case CHIPID_WCD9390:
3072 ret = snd_soc_add_component_controls(component, wcd9390_snd_controls,
3073 ARRAY_SIZE(wcd9390_snd_controls));
3074 if (ret < 0) {
3075 dev_err(component->dev,
3076 "%s: Failed to add snd ctrls for variant: %d\n",
3077 __func__, wcd939x->variant);
3078 goto err_free_ear_pdm_wd_int;
3079 }
3080 break;
3081 case CHIPID_WCD9395:
3082 ret = snd_soc_add_component_controls(component, wcd9395_snd_controls,
3083 ARRAY_SIZE(wcd9395_snd_controls));
3084 if (ret < 0) {
3085 dev_err(component->dev,
3086 "%s: Failed to add snd ctrls for variant: %d\n",
3087 __func__, wcd939x->variant);
3088 goto err_free_ear_pdm_wd_int;
3089 }
3090 break;
3091 default:
3092 break;
3093 }
3094
3095 ret = wcd939x_mbhc_init(component);
3096 if (ret) {
3097 dev_err(component->dev, "mbhc initialization failed\n");
3098 goto err_free_ear_pdm_wd_int;
3099 }
3100
3101 return 0;
3102
3103 err_free_ear_pdm_wd_int:
3104 free_irq(wcd939x->ear_pdm_wd_int, wcd939x);
3105 err_free_hphl_pdm_wd_int:
3106 free_irq(wcd939x->hphl_pdm_wd_int, wcd939x);
3107 err_free_hphr_pdm_wd_int:
3108 free_irq(wcd939x->hphr_pdm_wd_int, wcd939x);
3109 err_free_clsh_ctrl:
3110 wcd_clsh_ctrl_free(wcd939x->clsh_info);
3111
3112 return ret;
3113 }
3114
wcd939x_soc_codec_remove(struct snd_soc_component * component)3115 static void wcd939x_soc_codec_remove(struct snd_soc_component *component)
3116 {
3117 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
3118
3119 wcd939x_mbhc_deinit(component);
3120
3121 free_irq(wcd939x->ear_pdm_wd_int, wcd939x);
3122 free_irq(wcd939x->hphl_pdm_wd_int, wcd939x);
3123 free_irq(wcd939x->hphr_pdm_wd_int, wcd939x);
3124
3125 wcd_clsh_ctrl_free(wcd939x->clsh_info);
3126 }
3127
wcd939x_codec_set_jack(struct snd_soc_component * comp,struct snd_soc_jack * jack,void * data)3128 static int wcd939x_codec_set_jack(struct snd_soc_component *comp,
3129 struct snd_soc_jack *jack, void *data)
3130 {
3131 struct wcd939x_priv *wcd = dev_get_drvdata(comp->dev);
3132
3133 if (jack)
3134 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack);
3135
3136 wcd_mbhc_stop(wcd->wcd_mbhc);
3137
3138 return 0;
3139 }
3140
3141 static const struct snd_soc_component_driver soc_codec_dev_wcd939x = {
3142 .name = "wcd939x_codec",
3143 .probe = wcd939x_soc_codec_probe,
3144 .remove = wcd939x_soc_codec_remove,
3145 .controls = wcd939x_snd_controls,
3146 .num_controls = ARRAY_SIZE(wcd939x_snd_controls),
3147 .dapm_widgets = wcd939x_dapm_widgets,
3148 .num_dapm_widgets = ARRAY_SIZE(wcd939x_dapm_widgets),
3149 .dapm_routes = wcd939x_audio_map,
3150 .num_dapm_routes = ARRAY_SIZE(wcd939x_audio_map),
3151 .set_jack = wcd939x_codec_set_jack,
3152 .endianness = 1,
3153 };
3154
3155 #if IS_ENABLED(CONFIG_TYPEC)
3156 /* Get USB-C plug orientation to provide swap event for MBHC */
wcd939x_typec_switch_set(struct typec_switch_dev * sw,enum typec_orientation orientation)3157 static int wcd939x_typec_switch_set(struct typec_switch_dev *sw,
3158 enum typec_orientation orientation)
3159 {
3160 struct wcd939x_priv *wcd939x = typec_switch_get_drvdata(sw);
3161
3162 wcd939x->typec_orientation = orientation;
3163
3164 return 0;
3165 }
3166
wcd939x_typec_mux_set(struct typec_mux_dev * mux,struct typec_mux_state * state)3167 static int wcd939x_typec_mux_set(struct typec_mux_dev *mux,
3168 struct typec_mux_state *state)
3169 {
3170 struct wcd939x_priv *wcd939x = typec_mux_get_drvdata(mux);
3171 unsigned int previous_mode = wcd939x->typec_mode;
3172
3173 if (!wcd939x->wcd_mbhc)
3174 return -EINVAL;
3175
3176 if (wcd939x->typec_mode != state->mode) {
3177 wcd939x->typec_mode = state->mode;
3178
3179 if (wcd939x->typec_mode == TYPEC_MODE_AUDIO)
3180 return wcd_mbhc_typec_report_plug(wcd939x->wcd_mbhc);
3181 else if (previous_mode == TYPEC_MODE_AUDIO)
3182 return wcd_mbhc_typec_report_unplug(wcd939x->wcd_mbhc);
3183 }
3184
3185 return 0;
3186 }
3187 #endif /* CONFIG_TYPEC */
3188
wcd939x_dt_parse_micbias_info(struct device * dev,struct wcd939x_priv * wcd)3189 static void wcd939x_dt_parse_micbias_info(struct device *dev, struct wcd939x_priv *wcd)
3190 {
3191 struct device_node *np = dev->of_node;
3192 u32 prop_val = 0;
3193 int rc = 0;
3194
3195 rc = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val);
3196 if (!rc)
3197 wcd->micb1_mv = prop_val / 1000;
3198 else
3199 dev_info(dev, "%s: Micbias1 DT property not found\n", __func__);
3200
3201 rc = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val);
3202 if (!rc)
3203 wcd->micb2_mv = prop_val / 1000;
3204 else
3205 dev_info(dev, "%s: Micbias2 DT property not found\n", __func__);
3206
3207 rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val);
3208 if (!rc)
3209 wcd->micb3_mv = prop_val / 1000;
3210 else
3211 dev_info(dev, "%s: Micbias3 DT property not found\n", __func__);
3212
3213 rc = of_property_read_u32(np, "qcom,micbias4-microvolt", &prop_val);
3214 if (!rc)
3215 wcd->micb4_mv = prop_val / 1000;
3216 else
3217 dev_info(dev, "%s: Micbias4 DT property not found\n", __func__);
3218 }
3219
3220 #if IS_ENABLED(CONFIG_TYPEC)
wcd939x_swap_gnd_mic(struct snd_soc_component * component)3221 static bool wcd939x_swap_gnd_mic(struct snd_soc_component *component)
3222 {
3223 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
3224
3225 if (!wcd939x->typec_analog_mux || !wcd939x->typec_switch)
3226 return false;
3227
3228 /* Report inversion via Type Switch of USBSS */
3229 typec_switch_set(wcd939x->typec_switch,
3230 wcd939x->typec_orientation == TYPEC_ORIENTATION_REVERSE ?
3231 TYPEC_ORIENTATION_NORMAL : TYPEC_ORIENTATION_REVERSE);
3232
3233 return true;
3234 }
3235 #endif /* CONFIG_TYPEC */
3236
wcd939x_populate_dt_data(struct wcd939x_priv * wcd939x,struct device * dev)3237 static int wcd939x_populate_dt_data(struct wcd939x_priv *wcd939x, struct device *dev)
3238 {
3239 struct wcd_mbhc_config *cfg = &wcd939x->mbhc_cfg;
3240 #if IS_ENABLED(CONFIG_TYPEC)
3241 struct device_node *np;
3242 #endif /* CONFIG_TYPEC */
3243 int ret;
3244
3245 wcd939x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
3246 if (IS_ERR(wcd939x->reset_gpio))
3247 return dev_err_probe(dev, PTR_ERR(wcd939x->reset_gpio),
3248 "Failed to get reset gpio\n");
3249
3250 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(wcd939x_supplies),
3251 wcd939x_supplies);
3252 if (ret)
3253 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n");
3254
3255 wcd939x_dt_parse_micbias_info(dev, wcd939x);
3256
3257 cfg->mbhc_micbias = MIC_BIAS_2;
3258 cfg->anc_micbias = MIC_BIAS_2;
3259 cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
3260 cfg->num_btn = WCD939X_MBHC_MAX_BUTTONS;
3261 cfg->micb_mv = wcd939x->micb2_mv;
3262 cfg->linein_th = 5000;
3263 cfg->hs_thr = 1700;
3264 cfg->hph_thr = 50;
3265
3266 wcd_dt_parse_mbhc_data(dev, cfg);
3267
3268 #if IS_ENABLED(CONFIG_TYPEC)
3269 /*
3270 * Is node has a port and a valid remote endpoint
3271 * consider HP lines are connected to the USBSS part
3272 */
3273 np = of_graph_get_remote_node(dev->of_node, 0, 0);
3274 if (np) {
3275 wcd939x->typec_analog_mux = true;
3276 cfg->typec_analog_mux = true;
3277 cfg->swap_gnd_mic = wcd939x_swap_gnd_mic;
3278 }
3279 #endif /* CONFIG_TYPEC */
3280
3281 return 0;
3282 }
3283
wcd939x_reset(struct wcd939x_priv * wcd939x)3284 static int wcd939x_reset(struct wcd939x_priv *wcd939x)
3285 {
3286 gpiod_set_value(wcd939x->reset_gpio, 1);
3287 /* 20us sleep required after pulling the reset gpio to LOW */
3288 usleep_range(20, 30);
3289 gpiod_set_value(wcd939x->reset_gpio, 0);
3290 /* 20us sleep required after pulling the reset gpio to HIGH */
3291 usleep_range(20, 30);
3292
3293 return 0;
3294 }
3295
wcd939x_codec_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)3296 static int wcd939x_codec_hw_params(struct snd_pcm_substream *substream,
3297 struct snd_pcm_hw_params *params,
3298 struct snd_soc_dai *dai)
3299 {
3300 struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev);
3301 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id];
3302
3303 return wcd939x_sdw_hw_params(wcd, substream, params, dai);
3304 }
3305
wcd939x_codec_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)3306 static int wcd939x_codec_free(struct snd_pcm_substream *substream,
3307 struct snd_soc_dai *dai)
3308 {
3309 struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev);
3310 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id];
3311
3312 return wcd939x_sdw_free(wcd, substream, dai);
3313 }
3314
wcd939x_codec_set_sdw_stream(struct snd_soc_dai * dai,void * stream,int direction)3315 static int wcd939x_codec_set_sdw_stream(struct snd_soc_dai *dai,
3316 void *stream, int direction)
3317 {
3318 struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev);
3319 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id];
3320
3321 return wcd939x_sdw_set_sdw_stream(wcd, dai, stream, direction);
3322 }
3323
3324 static const struct snd_soc_dai_ops wcd939x_sdw_dai_ops = {
3325 .hw_params = wcd939x_codec_hw_params,
3326 .hw_free = wcd939x_codec_free,
3327 .set_stream = wcd939x_codec_set_sdw_stream,
3328 };
3329
3330 static struct snd_soc_dai_driver wcd939x_dais[] = {
3331 [0] = {
3332 .name = "wcd939x-sdw-rx",
3333 .playback = {
3334 .stream_name = "WCD AIF1 Playback",
3335 .rates = WCD939X_RATES_MASK | WCD939X_FRAC_RATES_MASK,
3336 .formats = WCD939X_FORMATS,
3337 .rate_max = 384000,
3338 .rate_min = 8000,
3339 .channels_min = 1,
3340 .channels_max = 2,
3341 },
3342 .ops = &wcd939x_sdw_dai_ops,
3343 },
3344 [1] = {
3345 .name = "wcd939x-sdw-tx",
3346 .capture = {
3347 .stream_name = "WCD AIF1 Capture",
3348 .rates = WCD939X_RATES_MASK | WCD939X_FRAC_RATES_MASK,
3349 .formats = WCD939X_FORMATS,
3350 .rate_min = 8000,
3351 .rate_max = 384000,
3352 .channels_min = 1,
3353 .channels_max = 4,
3354 },
3355 .ops = &wcd939x_sdw_dai_ops,
3356 },
3357 };
3358
wcd939x_bind(struct device * dev)3359 static int wcd939x_bind(struct device *dev)
3360 {
3361 struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
3362 unsigned int version, id1, status1;
3363 int ret;
3364
3365 #if IS_ENABLED(CONFIG_TYPEC)
3366 /*
3367 * Get USBSS type-c switch to send gnd/mic swap events
3368 * typec_switch is fetched now to avoid a probe deadlock since
3369 * the USBSS depends on the typec_mux register in wcd939x_probe()
3370 */
3371 if (wcd939x->typec_analog_mux) {
3372 wcd939x->typec_switch = fwnode_typec_switch_get(dev->fwnode);
3373 if (IS_ERR(wcd939x->typec_switch))
3374 return dev_err_probe(dev, PTR_ERR(wcd939x->typec_switch),
3375 "failed to acquire orientation-switch\n");
3376 }
3377 #endif /* CONFIG_TYPEC */
3378
3379 ret = component_bind_all(dev, wcd939x);
3380 if (ret) {
3381 dev_err(dev, "%s: Slave bind failed, ret = %d\n",
3382 __func__, ret);
3383 goto err_put_typec_switch;
3384 }
3385
3386 wcd939x->rxdev = wcd939x_sdw_device_get(wcd939x->rxnode);
3387 if (!wcd939x->rxdev) {
3388 dev_err(dev, "could not find slave with matching of node\n");
3389 ret = -EINVAL;
3390 goto err_unbind;
3391 }
3392 wcd939x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd939x->rxdev);
3393 wcd939x->sdw_priv[AIF1_PB]->wcd939x = wcd939x;
3394
3395 wcd939x->txdev = wcd939x_sdw_device_get(wcd939x->txnode);
3396 if (!wcd939x->txdev) {
3397 dev_err(dev, "could not find txslave with matching of node\n");
3398 ret = -EINVAL;
3399 goto err_put_rxdev;
3400 }
3401 wcd939x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd939x->txdev);
3402 wcd939x->sdw_priv[AIF1_CAP]->wcd939x = wcd939x;
3403 wcd939x->tx_sdw_dev = dev_to_sdw_dev(wcd939x->txdev);
3404
3405 /*
3406 * As TX is main CSR reg interface, which should not be suspended first.
3407 * explicitly add the dependency link
3408 */
3409 if (!device_link_add(wcd939x->rxdev, wcd939x->txdev, DL_FLAG_STATELESS |
3410 DL_FLAG_PM_RUNTIME)) {
3411 dev_err(dev, "could not devlink tx and rx\n");
3412 ret = -EINVAL;
3413 goto err_put_txdev;
3414 }
3415
3416 if (!device_link_add(dev, wcd939x->txdev, DL_FLAG_STATELESS |
3417 DL_FLAG_PM_RUNTIME)) {
3418 dev_err(dev, "could not devlink wcd and tx\n");
3419 ret = -EINVAL;
3420 goto err_remove_rxtx_link;
3421 }
3422
3423 if (!device_link_add(dev, wcd939x->rxdev, DL_FLAG_STATELESS |
3424 DL_FLAG_PM_RUNTIME)) {
3425 dev_err(dev, "could not devlink wcd and rx\n");
3426 ret = -EINVAL;
3427 goto err_remove_tx_link;
3428 }
3429
3430 /* Get regmap from TX SoundWire device */
3431 wcd939x->regmap = wcd939x_swr_get_regmap(wcd939x->sdw_priv[AIF1_CAP]);
3432 if (IS_ERR(wcd939x->regmap)) {
3433 dev_err(dev, "could not get TX device regmap\n");
3434 ret = PTR_ERR(wcd939x->regmap);
3435 goto err_remove_rx_link;
3436 }
3437
3438 ret = wcd939x_irq_init(wcd939x, dev);
3439 if (ret) {
3440 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret);
3441 goto err_remove_rx_link;
3442 }
3443
3444 wcd939x->sdw_priv[AIF1_PB]->slave_irq = wcd939x->virq;
3445 wcd939x->sdw_priv[AIF1_CAP]->slave_irq = wcd939x->virq;
3446
3447 ret = wcd939x_set_micbias_data(wcd939x);
3448 if (ret < 0) {
3449 dev_err(dev, "%s: bad micbias pdata\n", __func__);
3450 goto err_remove_rx_link;
3451 }
3452
3453 /* Check WCD9395 version */
3454 regmap_read(wcd939x->regmap, WCD939X_DIGITAL_CHIP_ID1, &id1);
3455 regmap_read(wcd939x->regmap, WCD939X_EAR_STATUS_REG_1, &status1);
3456
3457 if (id1 == CHIPID_WCD939X_VER_MAJOR_1)
3458 version = ((status1 & CHIPID_WCD939X_VER_MINOR_1) ? WCD939X_VERSION_1_1 : WCD939X_VERSION_1_0);
3459 else
3460 version = WCD939X_VERSION_2_0;
3461
3462 dev_dbg(dev, "wcd939x version: %s\n", version_to_str(version));
3463
3464 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd939x,
3465 wcd939x_dais, ARRAY_SIZE(wcd939x_dais));
3466 if (ret) {
3467 dev_err(dev, "%s: Codec registration failed\n",
3468 __func__);
3469 goto err_remove_rx_link;
3470 }
3471
3472 return 0;
3473
3474 err_remove_rx_link:
3475 device_link_remove(dev, wcd939x->rxdev);
3476 err_remove_tx_link:
3477 device_link_remove(dev, wcd939x->txdev);
3478 err_remove_rxtx_link:
3479 device_link_remove(wcd939x->rxdev, wcd939x->txdev);
3480 err_put_txdev:
3481 put_device(wcd939x->txdev);
3482 err_put_rxdev:
3483 put_device(wcd939x->rxdev);
3484 err_unbind:
3485 component_unbind_all(dev, wcd939x);
3486 err_put_typec_switch:
3487 #if IS_ENABLED(CONFIG_TYPEC)
3488 if (wcd939x->typec_analog_mux)
3489 typec_switch_put(wcd939x->typec_switch);
3490 #endif /* CONFIG_TYPEC */
3491
3492 return ret;
3493 }
3494
wcd939x_unbind(struct device * dev)3495 static void wcd939x_unbind(struct device *dev)
3496 {
3497 struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
3498
3499 snd_soc_unregister_component(dev);
3500 device_link_remove(dev, wcd939x->txdev);
3501 device_link_remove(dev, wcd939x->rxdev);
3502 device_link_remove(wcd939x->rxdev, wcd939x->txdev);
3503 put_device(wcd939x->txdev);
3504 put_device(wcd939x->rxdev);
3505 component_unbind_all(dev, wcd939x);
3506 }
3507
3508 static const struct component_master_ops wcd939x_comp_ops = {
3509 .bind = wcd939x_bind,
3510 .unbind = wcd939x_unbind,
3511 };
3512
wcd939x_typec_mux_unregister(void * data)3513 static void __maybe_unused wcd939x_typec_mux_unregister(void *data)
3514 {
3515 struct typec_mux_dev *typec_mux = data;
3516
3517 typec_mux_unregister(typec_mux);
3518 }
3519
wcd939x_typec_switch_unregister(void * data)3520 static void __maybe_unused wcd939x_typec_switch_unregister(void *data)
3521 {
3522 struct typec_switch_dev *typec_sw = data;
3523
3524 typec_switch_unregister(typec_sw);
3525 }
3526
wcd939x_add_typec(struct wcd939x_priv * wcd939x,struct device * dev)3527 static int wcd939x_add_typec(struct wcd939x_priv *wcd939x, struct device *dev)
3528 {
3529 #if IS_ENABLED(CONFIG_TYPEC)
3530 int ret;
3531 struct typec_mux_dev *typec_mux;
3532 struct typec_switch_dev *typec_sw;
3533 struct typec_mux_desc mux_desc = {
3534 .drvdata = wcd939x,
3535 .fwnode = dev_fwnode(dev),
3536 .set = wcd939x_typec_mux_set,
3537 };
3538 struct typec_switch_desc sw_desc = {
3539 .drvdata = wcd939x,
3540 .fwnode = dev_fwnode(dev),
3541 .set = wcd939x_typec_switch_set,
3542 };
3543
3544 /*
3545 * Is USBSS is used to mux analog lines,
3546 * register a typec mux/switch to get typec events
3547 */
3548 if (!wcd939x->typec_analog_mux)
3549 return 0;
3550
3551 typec_mux = typec_mux_register(dev, &mux_desc);
3552 if (IS_ERR(typec_mux))
3553 return dev_err_probe(dev, PTR_ERR(typec_mux),
3554 "failed to register typec mux\n");
3555
3556 ret = devm_add_action_or_reset(dev, wcd939x_typec_mux_unregister,
3557 typec_mux);
3558 if (ret)
3559 return ret;
3560
3561 typec_sw = typec_switch_register(dev, &sw_desc);
3562 if (IS_ERR(typec_sw))
3563 return dev_err_probe(dev, PTR_ERR(typec_sw),
3564 "failed to register typec switch\n");
3565
3566 ret = devm_add_action_or_reset(dev, wcd939x_typec_switch_unregister,
3567 typec_sw);
3568 if (ret)
3569 return ret;
3570 #endif
3571
3572 return 0;
3573 }
3574
wcd939x_add_slave_components(struct wcd939x_priv * wcd939x,struct device * dev,struct component_match ** matchptr)3575 static int wcd939x_add_slave_components(struct wcd939x_priv *wcd939x,
3576 struct device *dev,
3577 struct component_match **matchptr)
3578 {
3579 struct device_node *np = dev->of_node;
3580
3581 wcd939x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0);
3582 if (!wcd939x->rxnode) {
3583 dev_err(dev, "%s: Rx-device node not defined\n", __func__);
3584 return -ENODEV;
3585 }
3586
3587 of_node_get(wcd939x->rxnode);
3588 component_match_add_release(dev, matchptr, component_release_of,
3589 component_compare_of, wcd939x->rxnode);
3590
3591 wcd939x->txnode = of_parse_phandle(np, "qcom,tx-device", 0);
3592 if (!wcd939x->txnode) {
3593 dev_err(dev, "%s: Tx-device node not defined\n", __func__);
3594 return -ENODEV;
3595 }
3596 of_node_get(wcd939x->txnode);
3597 component_match_add_release(dev, matchptr, component_release_of,
3598 component_compare_of, wcd939x->txnode);
3599 return 0;
3600 }
3601
wcd939x_probe(struct platform_device * pdev)3602 static int wcd939x_probe(struct platform_device *pdev)
3603 {
3604 struct component_match *match = NULL;
3605 struct wcd939x_priv *wcd939x = NULL;
3606 struct device *dev = &pdev->dev;
3607 int ret;
3608
3609 wcd939x = devm_kzalloc(dev, sizeof(struct wcd939x_priv),
3610 GFP_KERNEL);
3611 if (!wcd939x)
3612 return -ENOMEM;
3613
3614 dev_set_drvdata(dev, wcd939x);
3615 mutex_init(&wcd939x->micb_lock);
3616
3617 ret = wcd939x_populate_dt_data(wcd939x, dev);
3618 if (ret) {
3619 dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
3620 return -EINVAL;
3621 }
3622
3623 ret = wcd939x_add_typec(wcd939x, dev);
3624 if (ret)
3625 return ret;
3626
3627 ret = wcd939x_add_slave_components(wcd939x, dev, &match);
3628 if (ret)
3629 return ret;
3630
3631 wcd939x_reset(wcd939x);
3632
3633 ret = component_master_add_with_match(dev, &wcd939x_comp_ops, match);
3634 if (ret)
3635 return ret;
3636
3637 pm_runtime_set_autosuspend_delay(dev, 1000);
3638 pm_runtime_use_autosuspend(dev);
3639 pm_runtime_mark_last_busy(dev);
3640 pm_runtime_set_active(dev);
3641 pm_runtime_enable(dev);
3642 pm_runtime_idle(dev);
3643
3644 return 0;
3645 }
3646
wcd939x_remove(struct platform_device * pdev)3647 static void wcd939x_remove(struct platform_device *pdev)
3648 {
3649 struct device *dev = &pdev->dev;
3650
3651 component_master_del(dev, &wcd939x_comp_ops);
3652
3653 pm_runtime_disable(dev);
3654 pm_runtime_set_suspended(dev);
3655 pm_runtime_dont_use_autosuspend(dev);
3656 }
3657
3658 #if defined(CONFIG_OF)
3659 static const struct of_device_id wcd939x_dt_match[] = {
3660 { .compatible = "qcom,wcd9390-codec" },
3661 { .compatible = "qcom,wcd9395-codec" },
3662 {}
3663 };
3664 MODULE_DEVICE_TABLE(of, wcd939x_dt_match);
3665 #endif
3666
3667 static struct platform_driver wcd939x_codec_driver = {
3668 .probe = wcd939x_probe,
3669 .remove = wcd939x_remove,
3670 .driver = {
3671 .name = "wcd939x_codec",
3672 .of_match_table = of_match_ptr(wcd939x_dt_match),
3673 .suppress_bind_attrs = true,
3674 },
3675 };
3676
3677 module_platform_driver(wcd939x_codec_driver);
3678 MODULE_DESCRIPTION("WCD939X Codec driver");
3679 MODULE_LICENSE("GPL");
3680