1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA driver for RME Hammerfall DSP MADI audio interface(s) 4 * 5 * Copyright (c) 2003 Winfried Ritsch (IEM) 6 * code based on hdsp.c Paul Davis 7 * Marcus Andersson 8 * Thomas Charbonnel 9 * Modified 2006-06-01 for AES32 support by Remy Bruno 10 * <remy.bruno@trinnov.com> 11 * 12 * Modified 2009-04-13 for proper metering by Florian Faber 13 * <faber@faberman.de> 14 * 15 * Modified 2009-04-14 for native float support by Florian Faber 16 * <faber@faberman.de> 17 * 18 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber 19 * <faber@faberman.de> 20 * 21 * Modified 2009-04-30 added hw serial number support by Florian Faber 22 * 23 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth 24 * 25 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth 26 * 27 * Modified 2019-05-23 fix AIO single speed ADAT capture and playback 28 * by Philippe.Bekaert@uhasselt.be 29 */ 30 31 /* ************* Register Documentation ******************************************************* 32 * 33 * Work in progress! Documentation is based on the code in this file. 34 * 35 * --------- HDSPM_controlRegister --------- 36 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte 37 * :||||.||||:||||.||||:||||.||||:||||.||||: 38 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number 39 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31 40 * :||||.||||:||||.||||:||||.||||:||||.||||: 41 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 42 * : . : . : . : x . : HDSPM_AudioInterruptEnable \_ setting both bits 43 * : . : . : . : . x: HDSPM_Start / enables audio IO 44 * : . : . : . : x. : HDSPM_ClockModeMaster - 1: Master, 0: Slave 45 * : . : . : . : .210 : HDSPM_LatencyMask - 3 Bit value for latency 46 * : . : . : . : . : 0:64, 1:128, 2:256, 3:512, 47 * : . : . : . : . : 4:1024, 5:2048, 6:4096, 7:8192 48 * :x . : . : . x:xx . : HDSPM_FrequencyMask 49 * : . : . : . :10 . : HDSPM_Frequency1|HDSPM_Frequency0: 1=32K,2=44.1K,3=48K,0=?? 50 * : . : . : . x: . : <MADI> HDSPM_DoubleSpeed 51 * :x . : . : . : . : <MADI> HDSPM_QuadSpeed 52 * : . 3 : . 10: 2 . : . : HDSPM_SyncRefMask : 53 * : . : . x: . : . : HDSPM_SyncRef0 54 * : . : . x : . : . : HDSPM_SyncRef1 55 * : . : . : x . : . : <AES32> HDSPM_SyncRef2 56 * : . x : . : . : . : <AES32> HDSPM_SyncRef3 57 * : . : . 10: . : . : <MADI> sync ref: 0:WC, 1:Madi, 2:TCO, 3:SyncIn 58 * : . 3 : . 10: 2 . : . : <AES32> 0:WC, 1:AES1 ... 8:AES8, 9: TCO, 10:SyncIn? 59 * : . x : . : . : . : <MADIe> HDSPe_FLOAT_FORMAT 60 * : . : . : x . : . : <MADI> HDSPM_InputSelect0 : 0=optical,1=coax 61 * : . : . :x . : . : <MADI> HDSPM_InputSelect1 62 * : . : .x : . : . : <MADI> HDSPM_clr_tms 63 * : . : . : . x : . : <MADI> HDSPM_TX_64ch 64 * : . : . : . x : . : <AES32> HDSPM_Emphasis 65 * : . : . : .x : . : <MADI> HDSPM_AutoInp 66 * : . : . x : . : . : <MADI> HDSPM_SMUX 67 * : . : .x : . : . : <MADI> HDSPM_clr_tms 68 * : . : x. : . : . : <MADI> HDSPM_taxi_reset 69 * : . x: . : . : . : <MADI> HDSPM_LineOut 70 * : . x: . : . : . : <AES32> ?????????????????? 71 * : . : x. : . : . : <AES32> HDSPM_WCK48 72 * : . : . : .x : . : <AES32> HDSPM_Dolby 73 * : . : x . : . : . : HDSPM_Midi0InterruptEnable 74 * : . :x . : . : . : HDSPM_Midi1InterruptEnable 75 * : . : x . : . : . : HDSPM_Midi2InterruptEnable 76 * : . x : . : . : . : <MADI> HDSPM_Midi3InterruptEnable 77 * : . x : . : . : . : <AES32> HDSPM_DS_DoubleWire 78 * : .x : . : . : . : <AES32> HDSPM_QS_DoubleWire 79 * : x. : . : . : . : <AES32> HDSPM_QS_QuadWire 80 * : . : . : . x : . : <AES32> HDSPM_Professional 81 * : x . : . : . : . : HDSPM_wclk_sel 82 * : . : . : . : . : 83 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte 84 * :||||.||||:||||.||||:||||.||||:||||.||||: 85 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number 86 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31 87 * :||||.||||:||||.||||:||||.||||:||||.||||: 88 * :8421.8421:8421.8421:8421.8421:8421.8421:hex digit 89 * 90 * 91 * 92 * AIO / RayDAT only 93 * 94 * ------------ HDSPM_WR_SETTINGS ---------- 95 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte 96 * :1098.7654:3210.9876:5432.1098:7654.3210: 97 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number 98 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31 99 * :||||.||||:||||.||||:||||.||||:||||.||||: 100 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 101 * : . : . : . : . x: HDSPM_c0Master 1: Master, 0: Slave 102 * : . : . : . : . x : HDSPM_c0_SyncRef0 103 * : . : . : . : . x : HDSPM_c0_SyncRef1 104 * : . : . : . : .x : HDSPM_c0_SyncRef2 105 * : . : . : . : x. : HDSPM_c0_SyncRef3 106 * : . : . : . : 3.210 : HDSPM_c0_SyncRefMask: 107 * : . : . : . : . : RayDat: 0:WC, 1:AES, 2:SPDIF, 3..6: ADAT1..4, 108 * : . : . : . : . : 9:TCO, 10:SyncIn 109 * : . : . : . : . : AIO: 0:WC, 1:AES, 2: SPDIF, 3: ATAT, 110 * : . : . : . : . : 9:TCO, 10:SyncIn 111 * : . : . : . : . : 112 * : . : . : . : . : 113 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte 114 * :1098.7654:3210.9876:5432.1098:7654.3210: 115 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number 116 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31 117 * :||||.||||:||||.||||:||||.||||:||||.||||: 118 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 119 * 120 */ 121 #include <linux/init.h> 122 #include <linux/delay.h> 123 #include <linux/interrupt.h> 124 #include <linux/module.h> 125 #include <linux/slab.h> 126 #include <linux/pci.h> 127 #include <linux/math64.h> 128 #include <linux/io.h> 129 #include <linux/nospec.h> 130 131 #include <sound/core.h> 132 #include <sound/control.h> 133 #include <sound/pcm.h> 134 #include <sound/pcm_params.h> 135 #include <sound/info.h> 136 #include <sound/asoundef.h> 137 #include <sound/rawmidi.h> 138 #include <sound/hwdep.h> 139 #include <sound/initval.h> 140 141 #include <sound/hdspm.h> 142 143 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 144 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 145 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ 146 147 module_param_array(index, int, NULL, 0444); 148 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); 149 150 module_param_array(id, charp, NULL, 0444); 151 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); 152 153 module_param_array(enable, bool, NULL, 0444); 154 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); 155 156 157 MODULE_AUTHOR 158 ( 159 "Winfried Ritsch <ritsch_AT_iem.at>, " 160 "Paul Davis <paul@linuxaudiosystems.com>, " 161 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " 162 "Remy Bruno <remy.bruno@trinnov.com>, " 163 "Florian Faber <faberman@linuxproaudio.org>, " 164 "Adrian Knoth <adi@drcomp.erfurt.thur.de>" 165 ); 166 MODULE_DESCRIPTION("RME HDSPM"); 167 MODULE_LICENSE("GPL"); 168 169 /* --- Write registers. --- 170 These are defined as byte-offsets from the iobase value. */ 171 172 #define HDSPM_WR_SETTINGS 0 173 #define HDSPM_outputBufferAddress 32 174 #define HDSPM_inputBufferAddress 36 175 #define HDSPM_controlRegister 64 176 #define HDSPM_interruptConfirmation 96 177 #define HDSPM_control2Reg 256 /* not in specs ???????? */ 178 #define HDSPM_freqReg 256 /* for setting arbitrary clock values (DDS feature) */ 179 #define HDSPM_midiDataOut0 352 /* just believe in old code */ 180 #define HDSPM_midiDataOut1 356 181 #define HDSPM_eeprom_wr 384 /* for AES32 */ 182 183 /* DMA enable for 64 channels, only Bit 0 is relevant */ 184 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ 185 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ 186 187 /* 16 page addresses for each of the 64 channels DMA buffer in and out 188 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ 189 #define HDSPM_pageAddressBufferOut 8192 190 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) 191 192 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ 193 194 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ 195 196 /* --- Read registers. --- 197 These are defined as byte-offsets from the iobase value */ 198 #define HDSPM_statusRegister 0 199 /*#define HDSPM_statusRegister2 96 */ 200 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at 201 * offset 192, for AES32 *and* MADI 202 * => need to check that offset 192 is working on MADI */ 203 #define HDSPM_statusRegister2 192 204 #define HDSPM_timecodeRegister 128 205 206 /* AIO, RayDAT */ 207 #define HDSPM_RD_STATUS_0 0 208 #define HDSPM_RD_STATUS_1 64 209 #define HDSPM_RD_STATUS_2 128 210 #define HDSPM_RD_STATUS_3 192 211 212 #define HDSPM_RD_TCO 256 213 #define HDSPM_RD_PLL_FREQ 512 214 #define HDSPM_WR_TCO 128 215 216 #define HDSPM_TCO1_TCO_lock 0x00000001 217 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 218 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 219 #define HDSPM_TCO1_LTC_Input_valid 0x00000008 220 #define HDSPM_TCO1_WCK_Input_valid 0x00000010 221 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 222 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 223 224 #define HDSPM_TCO1_set_TC 0x00000100 225 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 226 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 227 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 228 229 #define HDSPM_TCO2_TC_run 0x00010000 230 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 231 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 232 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 233 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 234 #define HDSPM_TCO2_set_jam_sync 0x00200000 235 #define HDSPM_TCO2_set_flywheel 0x00400000 236 237 #define HDSPM_TCO2_set_01_4 0x01000000 238 #define HDSPM_TCO2_set_pull_down 0x02000000 239 #define HDSPM_TCO2_set_pull_up 0x04000000 240 #define HDSPM_TCO2_set_freq 0x08000000 241 #define HDSPM_TCO2_set_term_75R 0x10000000 242 #define HDSPM_TCO2_set_input_LSB 0x20000000 243 #define HDSPM_TCO2_set_input_MSB 0x40000000 244 #define HDSPM_TCO2_set_freq_from_app 0x80000000 245 246 247 #define HDSPM_midiDataOut0 352 248 #define HDSPM_midiDataOut1 356 249 #define HDSPM_midiDataOut2 368 250 251 #define HDSPM_midiDataIn0 360 252 #define HDSPM_midiDataIn1 364 253 #define HDSPM_midiDataIn2 372 254 #define HDSPM_midiDataIn3 376 255 256 /* status is data bytes in MIDI-FIFO (0-128) */ 257 #define HDSPM_midiStatusOut0 384 258 #define HDSPM_midiStatusOut1 388 259 #define HDSPM_midiStatusOut2 400 260 261 #define HDSPM_midiStatusIn0 392 262 #define HDSPM_midiStatusIn1 396 263 #define HDSPM_midiStatusIn2 404 264 #define HDSPM_midiStatusIn3 408 265 266 267 /* the meters are regular i/o-mapped registers, but offset 268 considerably from the rest. the peak registers are reset 269 when read; the least-significant 4 bits are full-scale counters; 270 the actual peak value is in the most-significant 24 bits. 271 */ 272 273 #define HDSPM_MADI_INPUT_PEAK 4096 274 #define HDSPM_MADI_PLAYBACK_PEAK 4352 275 #define HDSPM_MADI_OUTPUT_PEAK 4608 276 277 #define HDSPM_MADI_INPUT_RMS_L 6144 278 #define HDSPM_MADI_PLAYBACK_RMS_L 6400 279 #define HDSPM_MADI_OUTPUT_RMS_L 6656 280 281 #define HDSPM_MADI_INPUT_RMS_H 7168 282 #define HDSPM_MADI_PLAYBACK_RMS_H 7424 283 #define HDSPM_MADI_OUTPUT_RMS_H 7680 284 285 /* --- Control Register bits --------- */ 286 #define HDSPM_Start (1<<0) /* start engine */ 287 288 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ 289 #define HDSPM_Latency1 (1<<2) /* where n is defined */ 290 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ 291 292 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ 293 #define HDSPM_c0Master 0x1 /* Master clock bit in settings 294 register [RayDAT, AIO] */ 295 296 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ 297 298 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ 299 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ 300 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 301 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ 302 303 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ 304 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, 305 56channelMODE=0 */ /* MADI ONLY*/ 306 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ 307 308 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, 309 0=off, 1=on */ /* MADI ONLY */ 310 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ 311 312 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax 313 * -- MADI ONLY 314 */ 315 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ 316 317 #define HDSPM_SyncRef2 (1<<13) 318 #define HDSPM_SyncRef3 (1<<25) 319 320 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ 321 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use 322 AES additional bits in 323 lower 5 Audiodatabits ??? */ 324 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ 325 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ 326 327 #define HDSPM_Midi0InterruptEnable 0x0400000 328 #define HDSPM_Midi1InterruptEnable 0x0800000 329 #define HDSPM_Midi2InterruptEnable 0x0200000 330 #define HDSPM_Midi3InterruptEnable 0x4000000 331 332 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ 333 #define HDSPe_FLOAT_FORMAT 0x2000000 334 335 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ 336 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ 337 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ 338 339 #define HDSPM_wclk_sel (1<<30) 340 341 /* additional control register bits for AIO*/ 342 #define HDSPM_c0_Wck48 0x20 /* also RayDAT */ 343 #define HDSPM_c0_Input0 0x1000 344 #define HDSPM_c0_Input1 0x2000 345 #define HDSPM_c0_Spdif_Opt 0x4000 346 #define HDSPM_c0_Pro 0x8000 347 #define HDSPM_c0_clr_tms 0x10000 348 #define HDSPM_c0_AEB1 0x20000 349 #define HDSPM_c0_AEB2 0x40000 350 #define HDSPM_c0_LineOut 0x80000 351 #define HDSPM_c0_AD_GAIN0 0x100000 352 #define HDSPM_c0_AD_GAIN1 0x200000 353 #define HDSPM_c0_DA_GAIN0 0x400000 354 #define HDSPM_c0_DA_GAIN1 0x800000 355 #define HDSPM_c0_PH_GAIN0 0x1000000 356 #define HDSPM_c0_PH_GAIN1 0x2000000 357 #define HDSPM_c0_Sym6db 0x4000000 358 359 360 /* --- bit helper defines */ 361 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) 362 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ 363 HDSPM_DoubleSpeed|HDSPM_QuadSpeed) 364 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) 365 #define HDSPM_InputOptical 0 366 #define HDSPM_InputCoaxial (HDSPM_InputSelect0) 367 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ 368 HDSPM_SyncRef2|HDSPM_SyncRef3) 369 370 #define HDSPM_c0_SyncRef0 0x2 371 #define HDSPM_c0_SyncRef1 0x4 372 #define HDSPM_c0_SyncRef2 0x8 373 #define HDSPM_c0_SyncRef3 0x10 374 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ 375 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) 376 377 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ 378 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ 379 #define HDSPM_SYNC_FROM_TCO 2 380 #define HDSPM_SYNC_FROM_SYNC_IN 3 381 382 #define HDSPM_Frequency32KHz HDSPM_Frequency0 383 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 384 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) 385 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) 386 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) 387 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ 388 HDSPM_Frequency0) 389 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) 390 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) 391 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ 392 HDSPM_Frequency0) 393 394 395 /* Synccheck Status */ 396 #define HDSPM_SYNC_CHECK_NO_LOCK 0 397 #define HDSPM_SYNC_CHECK_LOCK 1 398 #define HDSPM_SYNC_CHECK_SYNC 2 399 400 /* AutoSync References - used by "autosync_ref" control switch */ 401 #define HDSPM_AUTOSYNC_FROM_WORD 0 402 #define HDSPM_AUTOSYNC_FROM_MADI 1 403 #define HDSPM_AUTOSYNC_FROM_TCO 2 404 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 405 #define HDSPM_AUTOSYNC_FROM_NONE 4 406 407 /* Possible sources of MADI input */ 408 #define HDSPM_OPTICAL 0 /* optical */ 409 #define HDSPM_COAXIAL 1 /* BNC */ 410 411 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) 412 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) 413 414 #define hdspm_encode_in(x) (((x)&0x3)<<14) 415 #define hdspm_decode_in(x) (((x)>>14)&0x3) 416 417 /* --- control2 register bits --- */ 418 #define HDSPM_TMS (1<<0) 419 #define HDSPM_TCK (1<<1) 420 #define HDSPM_TDI (1<<2) 421 #define HDSPM_JTAG (1<<3) 422 #define HDSPM_PWDN (1<<4) 423 #define HDSPM_PROGRAM (1<<5) 424 #define HDSPM_CONFIG_MODE_0 (1<<6) 425 #define HDSPM_CONFIG_MODE_1 (1<<7) 426 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ 427 #define HDSPM_BIGENDIAN_MODE (1<<9) 428 #define HDSPM_RD_MULTIPLE (1<<10) 429 430 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and 431 that do not conflict with specific bits for AES32 seem to be valid also 432 for the AES32 433 */ 434 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ 435 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ 436 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 437 * (like inp0) 438 */ 439 440 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ 441 #define HDSPM_madiSync (1<<18) /* MADI is in sync */ 442 443 #define HDSPM_tcoLockMadi 0x00000020 /* Optional TCO locked status for HDSPe MADI*/ 444 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/ 445 446 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */ 447 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */ 448 449 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 450 /* since 64byte accurate, last 6 bits are not used */ 451 452 453 454 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ 455 456 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ 457 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ 458 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ 459 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ 460 461 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with 462 * Interrupt 463 */ 464 #define HDSPM_tco_detect 0x08000000 465 #define HDSPM_tcoLockAes 0x20000000 /* Optional TCO locked status for HDSPe AES */ 466 467 #define HDSPM_s2_tco_detect 0x00000040 468 #define HDSPM_s2_AEBO_D 0x00000080 469 #define HDSPM_s2_AEBI_D 0x00000100 470 471 472 #define HDSPM_midi0IRQPending 0x40000000 473 #define HDSPM_midi1IRQPending 0x80000000 474 #define HDSPM_midi2IRQPending 0x20000000 475 #define HDSPM_midi2IRQPendingAES 0x00000020 476 #define HDSPM_midi3IRQPending 0x00200000 477 478 /* --- status bit helpers */ 479 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ 480 HDSPM_madiFreq2|HDSPM_madiFreq3) 481 #define HDSPM_madiFreq32 (HDSPM_madiFreq0) 482 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) 483 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) 484 #define HDSPM_madiFreq64 (HDSPM_madiFreq2) 485 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) 486 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) 487 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) 488 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) 489 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) 490 491 /* Status2 Register bits */ /* MADI ONLY */ 492 493 #define HDSPM_version0 (1<<0) /* not really defined but I guess */ 494 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ 495 #define HDSPM_version2 (1<<2) 496 497 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ 498 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ 499 500 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ 501 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ 502 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, 111=128 */ 503 #define HDSPM_wc_freq3 0x800 /* 1000=176.4, 1001=192 */ 504 505 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ 506 #define HDSPM_SyncRef1 0x20000 507 508 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ 509 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ 510 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ 511 512 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) 513 514 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\ 515 HDSPM_wc_freq3) 516 #define HDSPM_wcFreq32 (HDSPM_wc_freq0) 517 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) 518 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) 519 #define HDSPM_wcFreq64 (HDSPM_wc_freq2) 520 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) 521 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) 522 #define HDSPM_wcFreq128 (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) 523 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3) 524 #define HDSPM_wcFreq192 (HDSPM_wc_freq0|HDSPM_wc_freq3) 525 526 #define HDSPM_status1_F_0 0x0400000 527 #define HDSPM_status1_F_1 0x0800000 528 #define HDSPM_status1_F_2 0x1000000 529 #define HDSPM_status1_F_3 0x2000000 530 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) 531 532 533 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 534 HDSPM_SelSyncRef2) 535 #define HDSPM_SelSyncRef_WORD 0 536 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) 537 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) 538 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) 539 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 540 HDSPM_SelSyncRef2) 541 542 /* 543 For AES32, bits for status, status2 and timecode are different 544 */ 545 /* status */ 546 #define HDSPM_AES32_wcLock 0x0200000 547 #define HDSPM_AES32_wcSync 0x0100000 548 #define HDSPM_AES32_wcFreq_bit 22 549 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function 550 HDSPM_bit2freq */ 551 #define HDSPM_AES32_syncref_bit 16 552 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ 553 554 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 555 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 556 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 557 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 558 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 559 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 560 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 561 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 562 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 563 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9 564 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10 565 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11 566 567 /* status2 */ 568 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ 569 #define HDSPM_LockAES 0x80 570 #define HDSPM_LockAES1 0x80 571 #define HDSPM_LockAES2 0x40 572 #define HDSPM_LockAES3 0x20 573 #define HDSPM_LockAES4 0x10 574 #define HDSPM_LockAES5 0x8 575 #define HDSPM_LockAES6 0x4 576 #define HDSPM_LockAES7 0x2 577 #define HDSPM_LockAES8 0x1 578 /* 579 Timecode 580 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on 581 AES i+1 582 bits 3210 583 0001 32kHz 584 0010 44.1kHz 585 0011 48kHz 586 0100 64kHz 587 0101 88.2kHz 588 0110 96kHz 589 0111 128kHz 590 1000 176.4kHz 591 1001 192kHz 592 NB: Timecode register doesn't seem to work on AES32 card revision 230 593 */ 594 595 /* Mixer Values */ 596 #define UNITY_GAIN 32768 /* = 65536/2 */ 597 #define MINUS_INFINITY_GAIN 0 598 599 /* Number of channels for different Speed Modes */ 600 #define MADI_SS_CHANNELS 64 601 #define MADI_DS_CHANNELS 32 602 #define MADI_QS_CHANNELS 16 603 604 #define RAYDAT_SS_CHANNELS 36 605 #define RAYDAT_DS_CHANNELS 20 606 #define RAYDAT_QS_CHANNELS 12 607 608 #define AIO_IN_SS_CHANNELS 14 609 #define AIO_IN_DS_CHANNELS 10 610 #define AIO_IN_QS_CHANNELS 8 611 #define AIO_OUT_SS_CHANNELS 16 612 #define AIO_OUT_DS_CHANNELS 12 613 #define AIO_OUT_QS_CHANNELS 10 614 615 #define AES32_CHANNELS 16 616 617 /* the size of a substream (1 mono data stream) */ 618 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) 619 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) 620 621 /* the size of the area we need to allocate for DMA transfers. the 622 size is the same regardless of the number of channels, and 623 also the latency to use. 624 for one direction !!! 625 */ 626 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) 627 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) 628 629 #define HDSPM_RAYDAT_REV 211 630 #define HDSPM_AIO_REV 212 631 #define HDSPM_MADIFACE_REV 213 632 633 /* speed factor modes */ 634 #define HDSPM_SPEED_SINGLE 0 635 #define HDSPM_SPEED_DOUBLE 1 636 #define HDSPM_SPEED_QUAD 2 637 638 /* names for speed modes */ 639 static const char * const hdspm_speed_names[] = { "single", "double", "quad" }; 640 641 static const char *const texts_autosync_aes_tco[] = { "Word Clock", 642 "AES1", "AES2", "AES3", "AES4", 643 "AES5", "AES6", "AES7", "AES8", 644 "TCO", "Sync In" 645 }; 646 static const char *const texts_autosync_aes[] = { "Word Clock", 647 "AES1", "AES2", "AES3", "AES4", 648 "AES5", "AES6", "AES7", "AES8", 649 "Sync In" 650 }; 651 static const char *const texts_autosync_madi_tco[] = { "Word Clock", 652 "MADI", "TCO", "Sync In" }; 653 static const char *const texts_autosync_madi[] = { "Word Clock", 654 "MADI", "Sync In" }; 655 656 static const char *const texts_autosync_raydat_tco[] = { 657 "Word Clock", 658 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 659 "AES", "SPDIF", "TCO", "Sync In" 660 }; 661 static const char *const texts_autosync_raydat[] = { 662 "Word Clock", 663 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 664 "AES", "SPDIF", "Sync In" 665 }; 666 static const char *const texts_autosync_aio_tco[] = { 667 "Word Clock", 668 "ADAT", "AES", "SPDIF", "TCO", "Sync In" 669 }; 670 static const char *const texts_autosync_aio[] = { "Word Clock", 671 "ADAT", "AES", "SPDIF", "Sync In" }; 672 673 static const char *const texts_freq[] = { 674 "No Lock", 675 "32 kHz", 676 "44.1 kHz", 677 "48 kHz", 678 "64 kHz", 679 "88.2 kHz", 680 "96 kHz", 681 "128 kHz", 682 "176.4 kHz", 683 "192 kHz" 684 }; 685 686 static const char * const texts_ports_madi[] = { 687 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", 688 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", 689 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", 690 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", 691 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", 692 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", 693 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", 694 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", 695 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", 696 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", 697 "MADI.61", "MADI.62", "MADI.63", "MADI.64", 698 }; 699 700 701 static const char * const texts_ports_raydat_ss[] = { 702 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", 703 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 704 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", 705 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", 706 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", 707 "ADAT4.7", "ADAT4.8", 708 "AES.L", "AES.R", 709 "SPDIF.L", "SPDIF.R" 710 }; 711 712 static const char * const texts_ports_raydat_ds[] = { 713 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", 714 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 715 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", 716 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", 717 "AES.L", "AES.R", 718 "SPDIF.L", "SPDIF.R" 719 }; 720 721 static const char * const texts_ports_raydat_qs[] = { 722 "ADAT1.1", "ADAT1.2", 723 "ADAT2.1", "ADAT2.2", 724 "ADAT3.1", "ADAT3.2", 725 "ADAT4.1", "ADAT4.2", 726 "AES.L", "AES.R", 727 "SPDIF.L", "SPDIF.R" 728 }; 729 730 731 static const char * const texts_ports_aio_in_ss[] = { 732 "Analogue.L", "Analogue.R", 733 "AES.L", "AES.R", 734 "SPDIF.L", "SPDIF.R", 735 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 736 "ADAT.7", "ADAT.8", 737 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 738 }; 739 740 static const char * const texts_ports_aio_out_ss[] = { 741 "Analogue.L", "Analogue.R", 742 "AES.L", "AES.R", 743 "SPDIF.L", "SPDIF.R", 744 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 745 "ADAT.7", "ADAT.8", 746 "Phone.L", "Phone.R", 747 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 748 }; 749 750 static const char * const texts_ports_aio_in_ds[] = { 751 "Analogue.L", "Analogue.R", 752 "AES.L", "AES.R", 753 "SPDIF.L", "SPDIF.R", 754 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 755 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 756 }; 757 758 static const char * const texts_ports_aio_out_ds[] = { 759 "Analogue.L", "Analogue.R", 760 "AES.L", "AES.R", 761 "SPDIF.L", "SPDIF.R", 762 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 763 "Phone.L", "Phone.R", 764 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 765 }; 766 767 static const char * const texts_ports_aio_in_qs[] = { 768 "Analogue.L", "Analogue.R", 769 "AES.L", "AES.R", 770 "SPDIF.L", "SPDIF.R", 771 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 772 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 773 }; 774 775 static const char * const texts_ports_aio_out_qs[] = { 776 "Analogue.L", "Analogue.R", 777 "AES.L", "AES.R", 778 "SPDIF.L", "SPDIF.R", 779 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 780 "Phone.L", "Phone.R", 781 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 782 }; 783 784 static const char * const texts_ports_aes32[] = { 785 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", 786 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", 787 "AES.15", "AES.16" 788 }; 789 790 /* These tables map the ALSA channels 1..N to the channels that we 791 need to use in order to find the relevant channel buffer. RME 792 refers to this kind of mapping as between "the ADAT channel and 793 the DMA channel." We index it using the logical audio channel, 794 and the value is the DMA channel (i.e. channel buffer number) 795 where the data for that channel can be read/written from/to. 796 */ 797 798 static const char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { 799 0, 1, 2, 3, 4, 5, 6, 7, 800 8, 9, 10, 11, 12, 13, 14, 15, 801 16, 17, 18, 19, 20, 21, 22, 23, 802 24, 25, 26, 27, 28, 29, 30, 31, 803 32, 33, 34, 35, 36, 37, 38, 39, 804 40, 41, 42, 43, 44, 45, 46, 47, 805 48, 49, 50, 51, 52, 53, 54, 55, 806 56, 57, 58, 59, 60, 61, 62, 63 807 }; 808 809 static const char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { 810 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ 811 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ 812 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ 813 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ 814 0, 1, /* AES */ 815 2, 3, /* SPDIF */ 816 -1, -1, -1, -1, 817 -1, -1, -1, -1, -1, -1, -1, -1, 818 -1, -1, -1, -1, -1, -1, -1, -1, 819 -1, -1, -1, -1, -1, -1, -1, -1, 820 }; 821 822 static const char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { 823 4, 5, 6, 7, /* ADAT 1 */ 824 8, 9, 10, 11, /* ADAT 2 */ 825 12, 13, 14, 15, /* ADAT 3 */ 826 16, 17, 18, 19, /* ADAT 4 */ 827 0, 1, /* AES */ 828 2, 3, /* SPDIF */ 829 -1, -1, -1, -1, 830 -1, -1, -1, -1, -1, -1, -1, -1, 831 -1, -1, -1, -1, -1, -1, -1, -1, 832 -1, -1, -1, -1, -1, -1, -1, -1, 833 -1, -1, -1, -1, -1, -1, -1, -1, 834 -1, -1, -1, -1, -1, -1, -1, -1, 835 }; 836 837 static const char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { 838 4, 5, /* ADAT 1 */ 839 6, 7, /* ADAT 2 */ 840 8, 9, /* ADAT 3 */ 841 10, 11, /* ADAT 4 */ 842 0, 1, /* AES */ 843 2, 3, /* SPDIF */ 844 -1, -1, -1, -1, 845 -1, -1, -1, -1, -1, -1, -1, -1, 846 -1, -1, -1, -1, -1, -1, -1, -1, 847 -1, -1, -1, -1, -1, -1, -1, -1, 848 -1, -1, -1, -1, -1, -1, -1, -1, 849 -1, -1, -1, -1, -1, -1, -1, -1, 850 -1, -1, -1, -1, -1, -1, -1, -1, 851 }; 852 853 static const char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { 854 0, 1, /* line in */ 855 8, 9, /* aes in, */ 856 10, 11, /* spdif in */ 857 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ 858 2, 3, 4, 5, /* AEB */ 859 -1, -1, -1, -1, -1, -1, 860 -1, -1, -1, -1, -1, -1, -1, -1, 861 -1, -1, -1, -1, -1, -1, -1, -1, 862 -1, -1, -1, -1, -1, -1, -1, -1, 863 -1, -1, -1, -1, -1, -1, -1, -1, 864 -1, -1, -1, -1, -1, -1, -1, -1, 865 }; 866 867 static const char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { 868 0, 1, /* line out */ 869 8, 9, /* aes out */ 870 10, 11, /* spdif out */ 871 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ 872 6, 7, /* phone out */ 873 2, 3, 4, 5, /* AEB */ 874 -1, -1, -1, -1, 875 -1, -1, -1, -1, -1, -1, -1, -1, 876 -1, -1, -1, -1, -1, -1, -1, -1, 877 -1, -1, -1, -1, -1, -1, -1, -1, 878 -1, -1, -1, -1, -1, -1, -1, -1, 879 -1, -1, -1, -1, -1, -1, -1, -1, 880 }; 881 882 static const char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { 883 0, 1, /* line in */ 884 8, 9, /* aes in */ 885 10, 11, /* spdif in */ 886 12, 14, 16, 18, /* adat in */ 887 2, 3, 4, 5, /* AEB */ 888 -1, -1, 889 -1, -1, -1, -1, -1, -1, -1, -1, 890 -1, -1, -1, -1, -1, -1, -1, -1, 891 -1, -1, -1, -1, -1, -1, -1, -1, 892 -1, -1, -1, -1, -1, -1, -1, -1, 893 -1, -1, -1, -1, -1, -1, -1, -1, 894 -1, -1, -1, -1, -1, -1, -1, -1 895 }; 896 897 static const char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { 898 0, 1, /* line out */ 899 8, 9, /* aes out */ 900 10, 11, /* spdif out */ 901 12, 14, 16, 18, /* adat out */ 902 6, 7, /* phone out */ 903 2, 3, 4, 5, /* AEB */ 904 -1, -1, -1, -1, -1, -1, -1, -1, 905 -1, -1, -1, -1, -1, -1, -1, -1, 906 -1, -1, -1, -1, -1, -1, -1, -1, 907 -1, -1, -1, -1, -1, -1, -1, -1, 908 -1, -1, -1, -1, -1, -1, -1, -1, 909 -1, -1, -1, -1, -1, -1, -1, -1 910 }; 911 912 static const char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { 913 0, 1, /* line in */ 914 8, 9, /* aes in */ 915 10, 11, /* spdif in */ 916 12, 16, /* adat in */ 917 2, 3, 4, 5, /* AEB */ 918 -1, -1, -1, -1, 919 -1, -1, -1, -1, -1, -1, -1, -1, 920 -1, -1, -1, -1, -1, -1, -1, -1, 921 -1, -1, -1, -1, -1, -1, -1, -1, 922 -1, -1, -1, -1, -1, -1, -1, -1, 923 -1, -1, -1, -1, -1, -1, -1, -1, 924 -1, -1, -1, -1, -1, -1, -1, -1 925 }; 926 927 static const char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { 928 0, 1, /* line out */ 929 8, 9, /* aes out */ 930 10, 11, /* spdif out */ 931 12, 16, /* adat out */ 932 6, 7, /* phone out */ 933 2, 3, 4, 5, /* AEB */ 934 -1, -1, 935 -1, -1, -1, -1, -1, -1, -1, -1, 936 -1, -1, -1, -1, -1, -1, -1, -1, 937 -1, -1, -1, -1, -1, -1, -1, -1, 938 -1, -1, -1, -1, -1, -1, -1, -1, 939 -1, -1, -1, -1, -1, -1, -1, -1, 940 -1, -1, -1, -1, -1, -1, -1, -1 941 }; 942 943 static const char channel_map_aes32[HDSPM_MAX_CHANNELS] = { 944 0, 1, 2, 3, 4, 5, 6, 7, 945 8, 9, 10, 11, 12, 13, 14, 15, 946 -1, -1, -1, -1, -1, -1, -1, -1, 947 -1, -1, -1, -1, -1, -1, -1, -1, 948 -1, -1, -1, -1, -1, -1, -1, -1, 949 -1, -1, -1, -1, -1, -1, -1, -1, 950 -1, -1, -1, -1, -1, -1, -1, -1, 951 -1, -1, -1, -1, -1, -1, -1, -1 952 }; 953 954 struct hdspm_midi { 955 struct hdspm *hdspm; 956 int id; 957 struct snd_rawmidi *rmidi; 958 struct snd_rawmidi_substream *input; 959 struct snd_rawmidi_substream *output; 960 char istimer; /* timer in use */ 961 struct timer_list timer; 962 spinlock_t lock; 963 int pending; 964 int dataIn; 965 int statusIn; 966 int dataOut; 967 int statusOut; 968 int ie; 969 int irq; 970 }; 971 972 struct hdspm_tco { 973 int input; /* 0: LTC, 1:Video, 2: WC*/ 974 int framerate; /* 0=24, 1=25, 2=29.97, 3=29.97d, 4=30, 5=30d */ 975 int wordclock; /* 0=1:1, 1=44.1->48, 2=48->44.1 */ 976 int samplerate; /* 0=44.1, 1=48, 2= freq from app */ 977 int pull; /* 0=0, 1=+0.1%, 2=-0.1%, 3=+4%, 4=-4%*/ 978 int term; /* 0 = off, 1 = on */ 979 }; 980 981 struct hdspm { 982 spinlock_t lock; 983 /* only one playback and/or capture stream */ 984 struct snd_pcm_substream *capture_substream; 985 struct snd_pcm_substream *playback_substream; 986 987 char *card_name; /* for procinfo */ 988 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ 989 990 uint8_t io_type; 991 992 int monitor_outs; /* set up monitoring outs init flag */ 993 994 u32 control_register; /* cached value */ 995 u32 control2_register; /* cached value */ 996 u32 settings_register; /* cached value for AIO / RayDat (sync reference, master/slave) */ 997 998 struct hdspm_midi midi[4]; 999 struct work_struct midi_work; 1000 1001 size_t period_bytes; 1002 unsigned char ss_in_channels; 1003 unsigned char ds_in_channels; 1004 unsigned char qs_in_channels; 1005 unsigned char ss_out_channels; 1006 unsigned char ds_out_channels; 1007 unsigned char qs_out_channels; 1008 1009 unsigned char max_channels_in; 1010 unsigned char max_channels_out; 1011 1012 const signed char *channel_map_in; 1013 const signed char *channel_map_out; 1014 1015 const signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; 1016 const signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; 1017 1018 const char * const *port_names_in; 1019 const char * const *port_names_out; 1020 1021 const char * const *port_names_in_ss; 1022 const char * const *port_names_in_ds; 1023 const char * const *port_names_in_qs; 1024 const char * const *port_names_out_ss; 1025 const char * const *port_names_out_ds; 1026 const char * const *port_names_out_qs; 1027 1028 unsigned char *playback_buffer; /* suitably aligned address */ 1029 unsigned char *capture_buffer; /* suitably aligned address */ 1030 1031 pid_t capture_pid; /* process id which uses capture */ 1032 pid_t playback_pid; /* process id which uses capture */ 1033 int running; /* running status */ 1034 1035 int last_external_sample_rate; /* samplerate mystic ... */ 1036 int last_internal_sample_rate; 1037 int system_sample_rate; 1038 1039 int dev; /* Hardware vars... */ 1040 int irq; 1041 unsigned long port; 1042 void __iomem *iobase; 1043 1044 int irq_count; /* for debug */ 1045 int midiPorts; 1046 1047 struct snd_card *card; /* one card */ 1048 struct snd_pcm *pcm; /* has one pcm */ 1049 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ 1050 struct pci_dev *pci; /* and an pci info */ 1051 1052 /* Mixer vars */ 1053 /* fast alsa mixer */ 1054 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; 1055 /* but input to much, so not used */ 1056 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; 1057 /* full mixer accessible over mixer ioctl or hwdep-device */ 1058 struct hdspm_mixer *mixer; 1059 1060 struct hdspm_tco *tco; /* NULL if no TCO detected */ 1061 1062 const char *const *texts_autosync; 1063 int texts_autosync_items; 1064 1065 cycles_t last_interrupt; 1066 1067 unsigned int serial; 1068 1069 struct hdspm_peak_rms peak_rms; 1070 }; 1071 1072 1073 static const struct pci_device_id snd_hdspm_ids[] = { 1074 { 1075 .vendor = PCI_VENDOR_ID_XILINX, 1076 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, 1077 .subvendor = PCI_ANY_ID, 1078 .subdevice = PCI_ANY_ID, 1079 .class = 0, 1080 .class_mask = 0, 1081 .driver_data = 0}, 1082 {0,} 1083 }; 1084 1085 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); 1086 1087 /* prototypes */ 1088 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 1089 struct hdspm *hdspm); 1090 static int snd_hdspm_create_pcm(struct snd_card *card, 1091 struct hdspm *hdspm); 1092 1093 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); 1094 static inline int hdspm_get_pll_freq(struct hdspm *hdspm); 1095 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); 1096 static int hdspm_autosync_ref(struct hdspm *hdspm); 1097 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out); 1098 static int snd_hdspm_set_defaults(struct hdspm *hdspm); 1099 static int hdspm_system_clock_mode(struct hdspm *hdspm); 1100 static void hdspm_set_channel_dma_addr(struct hdspm *hdspm, 1101 struct snd_pcm_substream *substream, 1102 unsigned int reg, int channels); 1103 1104 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx); 1105 static int hdspm_wc_sync_check(struct hdspm *hdspm); 1106 static int hdspm_tco_sync_check(struct hdspm *hdspm); 1107 static int hdspm_sync_in_sync_check(struct hdspm *hdspm); 1108 1109 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index); 1110 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm); 1111 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm); 1112 1113 1114 1115 static inline int HDSPM_bit2freq(int n) 1116 { 1117 static const int bit2freq_tab[] = { 1118 0, 32000, 44100, 48000, 64000, 88200, 1119 96000, 128000, 176400, 192000 }; 1120 if (n < 1 || n > 9) 1121 return 0; 1122 return bit2freq_tab[n]; 1123 } 1124 1125 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm) 1126 { 1127 return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type)); 1128 } 1129 1130 1131 /* Write/read to/from HDSPM with Adresses in Bytes 1132 not words but only 32Bit writes are allowed */ 1133 1134 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, 1135 unsigned int val) 1136 { 1137 writel(val, hdspm->iobase + reg); 1138 } 1139 1140 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) 1141 { 1142 return readl(hdspm->iobase + reg); 1143 } 1144 1145 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader 1146 mixer is write only on hardware so we have to cache him for read 1147 each fader is a u32, but uses only the first 16 bit */ 1148 1149 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, 1150 unsigned int in) 1151 { 1152 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1153 return 0; 1154 1155 return hdspm->mixer->ch[chan].in[in]; 1156 } 1157 1158 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, 1159 unsigned int pb) 1160 { 1161 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1162 return 0; 1163 return hdspm->mixer->ch[chan].pb[pb]; 1164 } 1165 1166 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, 1167 unsigned int in, unsigned short data) 1168 { 1169 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1170 return -1; 1171 1172 hdspm_write(hdspm, 1173 HDSPM_MADI_mixerBase + 1174 ((in + 128 * chan) * sizeof(u32)), 1175 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); 1176 return 0; 1177 } 1178 1179 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, 1180 unsigned int pb, unsigned short data) 1181 { 1182 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1183 return -1; 1184 1185 hdspm_write(hdspm, 1186 HDSPM_MADI_mixerBase + 1187 ((64 + pb + 128 * chan) * sizeof(u32)), 1188 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); 1189 return 0; 1190 } 1191 1192 1193 /* enable DMA for specific channels, now available for DSP-MADI */ 1194 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) 1195 { 1196 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); 1197 } 1198 1199 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) 1200 { 1201 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); 1202 } 1203 1204 /* check if same process is writing and reading */ 1205 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) 1206 { 1207 unsigned long flags; 1208 int ret = 1; 1209 1210 spin_lock_irqsave(&hdspm->lock, flags); 1211 if ((hdspm->playback_pid != hdspm->capture_pid) && 1212 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { 1213 ret = 0; 1214 } 1215 spin_unlock_irqrestore(&hdspm->lock, flags); 1216 return ret; 1217 } 1218 1219 /* round arbitrary sample rates to commonly known rates */ 1220 static int hdspm_round_frequency(int rate) 1221 { 1222 if (rate < 38050) 1223 return 32000; 1224 if (rate < 46008) 1225 return 44100; 1226 else 1227 return 48000; 1228 } 1229 1230 /* QS and DS rates normally can not be detected 1231 * automatically by the card. Only exception is MADI 1232 * in 96k frame mode. 1233 * 1234 * So if we read SS values (32 .. 48k), check for 1235 * user-provided DS/QS bits in the control register 1236 * and multiply the base frequency accordingly. 1237 */ 1238 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate) 1239 { 1240 if (rate <= 48000) { 1241 if (hdspm->control_register & HDSPM_QuadSpeed) 1242 return rate * 4; 1243 else if (hdspm->control_register & 1244 HDSPM_DoubleSpeed) 1245 return rate * 2; 1246 } 1247 return rate; 1248 } 1249 1250 /* check for external sample rate, returns the sample rate in Hz*/ 1251 static int hdspm_external_sample_rate(struct hdspm *hdspm) 1252 { 1253 unsigned int status, status2; 1254 int syncref, rate = 0, rate_bits; 1255 1256 switch (hdspm->io_type) { 1257 case AES32: 1258 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1259 status = hdspm_read(hdspm, HDSPM_statusRegister); 1260 1261 syncref = hdspm_autosync_ref(hdspm); 1262 switch (syncref) { 1263 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 1264 /* Check WC sync and get sample rate */ 1265 if (hdspm_wc_sync_check(hdspm)) 1266 return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm)); 1267 break; 1268 1269 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 1270 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 1271 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 1272 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 1273 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 1274 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 1275 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 1276 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 1277 /* Check AES sync and get sample rate */ 1278 if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)) 1279 return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm, 1280 syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)); 1281 break; 1282 1283 1284 case HDSPM_AES32_AUTOSYNC_FROM_TCO: 1285 /* Check TCO sync and get sample rate */ 1286 if (hdspm_tco_sync_check(hdspm)) 1287 return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm)); 1288 break; 1289 default: 1290 return 0; 1291 } /* end switch(syncref) */ 1292 break; 1293 1294 case MADIface: 1295 status = hdspm_read(hdspm, HDSPM_statusRegister); 1296 1297 if (!(status & HDSPM_madiLock)) { 1298 rate = 0; /* no lock */ 1299 } else { 1300 switch (status & (HDSPM_status1_freqMask)) { 1301 case HDSPM_status1_F_0*1: 1302 rate = 32000; break; 1303 case HDSPM_status1_F_0*2: 1304 rate = 44100; break; 1305 case HDSPM_status1_F_0*3: 1306 rate = 48000; break; 1307 case HDSPM_status1_F_0*4: 1308 rate = 64000; break; 1309 case HDSPM_status1_F_0*5: 1310 rate = 88200; break; 1311 case HDSPM_status1_F_0*6: 1312 rate = 96000; break; 1313 case HDSPM_status1_F_0*7: 1314 rate = 128000; break; 1315 case HDSPM_status1_F_0*8: 1316 rate = 176400; break; 1317 case HDSPM_status1_F_0*9: 1318 rate = 192000; break; 1319 default: 1320 rate = 0; break; 1321 } 1322 } 1323 1324 break; 1325 1326 case MADI: 1327 case AIO: 1328 case RayDAT: 1329 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1330 status = hdspm_read(hdspm, HDSPM_statusRegister); 1331 rate = 0; 1332 1333 /* if wordclock has synced freq and wordclock is valid */ 1334 if ((status2 & HDSPM_wcLock) != 0 && 1335 (status2 & HDSPM_SelSyncRef0) == 0) { 1336 1337 rate_bits = status2 & HDSPM_wcFreqMask; 1338 1339 1340 switch (rate_bits) { 1341 case HDSPM_wcFreq32: 1342 rate = 32000; 1343 break; 1344 case HDSPM_wcFreq44_1: 1345 rate = 44100; 1346 break; 1347 case HDSPM_wcFreq48: 1348 rate = 48000; 1349 break; 1350 case HDSPM_wcFreq64: 1351 rate = 64000; 1352 break; 1353 case HDSPM_wcFreq88_2: 1354 rate = 88200; 1355 break; 1356 case HDSPM_wcFreq96: 1357 rate = 96000; 1358 break; 1359 case HDSPM_wcFreq128: 1360 rate = 128000; 1361 break; 1362 case HDSPM_wcFreq176_4: 1363 rate = 176400; 1364 break; 1365 case HDSPM_wcFreq192: 1366 rate = 192000; 1367 break; 1368 default: 1369 rate = 0; 1370 break; 1371 } 1372 } 1373 1374 /* if rate detected and Syncref is Word than have it, 1375 * word has priority to MADI 1376 */ 1377 if (rate != 0 && 1378 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) 1379 return hdspm_rate_multiplier(hdspm, rate); 1380 1381 /* maybe a madi input (which is taken if sel sync is madi) */ 1382 if (status & HDSPM_madiLock) { 1383 rate_bits = status & HDSPM_madiFreqMask; 1384 1385 switch (rate_bits) { 1386 case HDSPM_madiFreq32: 1387 rate = 32000; 1388 break; 1389 case HDSPM_madiFreq44_1: 1390 rate = 44100; 1391 break; 1392 case HDSPM_madiFreq48: 1393 rate = 48000; 1394 break; 1395 case HDSPM_madiFreq64: 1396 rate = 64000; 1397 break; 1398 case HDSPM_madiFreq88_2: 1399 rate = 88200; 1400 break; 1401 case HDSPM_madiFreq96: 1402 rate = 96000; 1403 break; 1404 case HDSPM_madiFreq128: 1405 rate = 128000; 1406 break; 1407 case HDSPM_madiFreq176_4: 1408 rate = 176400; 1409 break; 1410 case HDSPM_madiFreq192: 1411 rate = 192000; 1412 break; 1413 default: 1414 rate = 0; 1415 break; 1416 } 1417 1418 } /* endif HDSPM_madiLock */ 1419 1420 /* check sample rate from TCO or SYNC_IN */ 1421 { 1422 bool is_valid_input = 0; 1423 bool has_sync = 0; 1424 1425 syncref = hdspm_autosync_ref(hdspm); 1426 if (HDSPM_AUTOSYNC_FROM_TCO == syncref) { 1427 is_valid_input = 1; 1428 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1429 hdspm_tco_sync_check(hdspm)); 1430 } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) { 1431 is_valid_input = 1; 1432 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1433 hdspm_sync_in_sync_check(hdspm)); 1434 } 1435 1436 if (is_valid_input && has_sync) { 1437 rate = hdspm_round_frequency( 1438 hdspm_get_pll_freq(hdspm)); 1439 } 1440 } 1441 1442 rate = hdspm_rate_multiplier(hdspm, rate); 1443 1444 break; 1445 } 1446 1447 return rate; 1448 } 1449 1450 /* return latency in samples per period */ 1451 static int hdspm_get_latency(struct hdspm *hdspm) 1452 { 1453 int n; 1454 1455 n = hdspm_decode_latency(hdspm->control_register); 1456 1457 /* Special case for new RME cards with 32 samples period size. 1458 * The three latency bits in the control register 1459 * (HDSP_LatencyMask) encode latency values of 64 samples as 1460 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7 1461 * denotes 8192 samples, but on new cards like RayDAT or AIO, 1462 * it corresponds to 32 samples. 1463 */ 1464 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type)) 1465 n = -1; 1466 1467 return 1 << (n + 6); 1468 } 1469 1470 /* Latency function */ 1471 static inline void hdspm_compute_period_size(struct hdspm *hdspm) 1472 { 1473 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm); 1474 } 1475 1476 1477 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) 1478 { 1479 int position; 1480 1481 position = hdspm_read(hdspm, HDSPM_statusRegister); 1482 1483 switch (hdspm->io_type) { 1484 case RayDAT: 1485 case AIO: 1486 position &= HDSPM_BufferPositionMask; 1487 position /= 4; /* Bytes per sample */ 1488 break; 1489 default: 1490 position = (position & HDSPM_BufferID) ? 1491 (hdspm->period_bytes / 4) : 0; 1492 } 1493 1494 return position; 1495 } 1496 1497 1498 static inline void hdspm_start_audio(struct hdspm * s) 1499 { 1500 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); 1501 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1502 } 1503 1504 static inline void hdspm_stop_audio(struct hdspm * s) 1505 { 1506 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); 1507 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1508 } 1509 1510 /* should I silence all or only opened ones ? doit all for first even is 4MB*/ 1511 static void hdspm_silence_playback(struct hdspm *hdspm) 1512 { 1513 int i; 1514 int n = hdspm->period_bytes; 1515 void *buf = hdspm->playback_buffer; 1516 1517 if (!buf) 1518 return; 1519 1520 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 1521 memset(buf, 0, n); 1522 buf += HDSPM_CHANNEL_BUFFER_BYTES; 1523 } 1524 } 1525 1526 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) 1527 { 1528 int n; 1529 1530 spin_lock_irq(&s->lock); 1531 1532 if (32 == frames) { 1533 /* Special case for new RME cards like RayDAT/AIO which 1534 * support period sizes of 32 samples. Since latency is 1535 * encoded in the three bits of HDSP_LatencyMask, we can only 1536 * have values from 0 .. 7. While 0 still means 64 samples and 1537 * 6 represents 4096 samples on all cards, 7 represents 8192 1538 * on older cards and 32 samples on new cards. 1539 * 1540 * In other words, period size in samples is calculated by 1541 * 2^(n+6) with n ranging from 0 .. 7. 1542 */ 1543 n = 7; 1544 } else { 1545 frames >>= 7; 1546 n = 0; 1547 while (frames) { 1548 n++; 1549 frames >>= 1; 1550 } 1551 } 1552 1553 s->control_register &= ~HDSPM_LatencyMask; 1554 s->control_register |= hdspm_encode_latency(n); 1555 1556 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1557 1558 hdspm_compute_period_size(s); 1559 1560 spin_unlock_irq(&s->lock); 1561 1562 return 0; 1563 } 1564 1565 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) 1566 { 1567 u64 freq_const; 1568 1569 if (period == 0) 1570 return 0; 1571 1572 switch (hdspm->io_type) { 1573 case MADI: 1574 case AES32: 1575 freq_const = 110069313433624ULL; 1576 break; 1577 case RayDAT: 1578 case AIO: 1579 freq_const = 104857600000000ULL; 1580 break; 1581 case MADIface: 1582 freq_const = 131072000000000ULL; 1583 break; 1584 default: 1585 snd_BUG(); 1586 return 0; 1587 } 1588 1589 return div_u64(freq_const, period); 1590 } 1591 1592 1593 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) 1594 { 1595 u64 n; 1596 1597 if (snd_BUG_ON(rate <= 0)) 1598 return; 1599 1600 if (rate >= 112000) 1601 rate /= 4; 1602 else if (rate >= 56000) 1603 rate /= 2; 1604 1605 switch (hdspm->io_type) { 1606 case MADIface: 1607 n = 131072000000000ULL; /* 125 MHz */ 1608 break; 1609 case MADI: 1610 case AES32: 1611 n = 110069313433624ULL; /* 105 MHz */ 1612 break; 1613 case RayDAT: 1614 case AIO: 1615 n = 104857600000000ULL; /* 100 MHz */ 1616 break; 1617 default: 1618 snd_BUG(); 1619 return; 1620 } 1621 1622 n = div_u64(n, rate); 1623 /* n should be less than 2^32 for being written to FREQ register */ 1624 snd_BUG_ON(n >> 32); 1625 hdspm_write(hdspm, HDSPM_freqReg, (u32)n); 1626 } 1627 1628 /* dummy set rate lets see what happens */ 1629 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) 1630 { 1631 int current_rate; 1632 int rate_bits; 1633 int not_set = 0; 1634 int current_speed, target_speed; 1635 1636 /* ASSUMPTION: hdspm->lock is either set, or there is no need for 1637 it (e.g. during module initialization). 1638 */ 1639 1640 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { 1641 1642 /* SLAVE --- */ 1643 if (called_internally) { 1644 1645 /* request from ctl or card initialization 1646 just make a warning an remember setting 1647 for future master mode switching */ 1648 1649 dev_warn(hdspm->card->dev, 1650 "Warning: device is not running as a clock master.\n"); 1651 not_set = 1; 1652 } else { 1653 1654 /* hw_param request while in AutoSync mode */ 1655 int external_freq = 1656 hdspm_external_sample_rate(hdspm); 1657 1658 if (hdspm_autosync_ref(hdspm) == 1659 HDSPM_AUTOSYNC_FROM_NONE) { 1660 1661 dev_warn(hdspm->card->dev, 1662 "Detected no External Sync\n"); 1663 not_set = 1; 1664 1665 } else if (rate != external_freq) { 1666 1667 dev_warn(hdspm->card->dev, 1668 "Warning: No AutoSync source for requested rate\n"); 1669 not_set = 1; 1670 } 1671 } 1672 } 1673 1674 current_rate = hdspm->system_sample_rate; 1675 1676 /* Changing between Singe, Double and Quad speed is not 1677 allowed if any substreams are open. This is because such a change 1678 causes a shift in the location of the DMA buffers and a reduction 1679 in the number of available buffers. 1680 1681 Note that a similar but essentially insoluble problem exists for 1682 externally-driven rate changes. All we can do is to flag rate 1683 changes in the read/write routines. 1684 */ 1685 1686 if (current_rate <= 48000) 1687 current_speed = HDSPM_SPEED_SINGLE; 1688 else if (current_rate <= 96000) 1689 current_speed = HDSPM_SPEED_DOUBLE; 1690 else 1691 current_speed = HDSPM_SPEED_QUAD; 1692 1693 if (rate <= 48000) 1694 target_speed = HDSPM_SPEED_SINGLE; 1695 else if (rate <= 96000) 1696 target_speed = HDSPM_SPEED_DOUBLE; 1697 else 1698 target_speed = HDSPM_SPEED_QUAD; 1699 1700 switch (rate) { 1701 case 32000: 1702 rate_bits = HDSPM_Frequency32KHz; 1703 break; 1704 case 44100: 1705 rate_bits = HDSPM_Frequency44_1KHz; 1706 break; 1707 case 48000: 1708 rate_bits = HDSPM_Frequency48KHz; 1709 break; 1710 case 64000: 1711 rate_bits = HDSPM_Frequency64KHz; 1712 break; 1713 case 88200: 1714 rate_bits = HDSPM_Frequency88_2KHz; 1715 break; 1716 case 96000: 1717 rate_bits = HDSPM_Frequency96KHz; 1718 break; 1719 case 128000: 1720 rate_bits = HDSPM_Frequency128KHz; 1721 break; 1722 case 176400: 1723 rate_bits = HDSPM_Frequency176_4KHz; 1724 break; 1725 case 192000: 1726 rate_bits = HDSPM_Frequency192KHz; 1727 break; 1728 default: 1729 return -EINVAL; 1730 } 1731 1732 if (current_speed != target_speed 1733 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { 1734 dev_err(hdspm->card->dev, 1735 "cannot change from %s speed to %s speed mode (capture PID = %d, playback PID = %d)\n", 1736 hdspm_speed_names[current_speed], 1737 hdspm_speed_names[target_speed], 1738 hdspm->capture_pid, hdspm->playback_pid); 1739 return -EBUSY; 1740 } 1741 1742 hdspm->control_register &= ~HDSPM_FrequencyMask; 1743 hdspm->control_register |= rate_bits; 1744 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1745 1746 /* For AES32, need to set DDS value in FREQ register 1747 For MADI, also apparently */ 1748 hdspm_set_dds_value(hdspm, rate); 1749 1750 if (AES32 == hdspm->io_type && rate != current_rate) 1751 hdspm_write(hdspm, HDSPM_eeprom_wr, 0); 1752 1753 hdspm->system_sample_rate = rate; 1754 1755 if (rate <= 48000) { 1756 hdspm->channel_map_in = hdspm->channel_map_in_ss; 1757 hdspm->channel_map_out = hdspm->channel_map_out_ss; 1758 hdspm->max_channels_in = hdspm->ss_in_channels; 1759 hdspm->max_channels_out = hdspm->ss_out_channels; 1760 hdspm->port_names_in = hdspm->port_names_in_ss; 1761 hdspm->port_names_out = hdspm->port_names_out_ss; 1762 } else if (rate <= 96000) { 1763 hdspm->channel_map_in = hdspm->channel_map_in_ds; 1764 hdspm->channel_map_out = hdspm->channel_map_out_ds; 1765 hdspm->max_channels_in = hdspm->ds_in_channels; 1766 hdspm->max_channels_out = hdspm->ds_out_channels; 1767 hdspm->port_names_in = hdspm->port_names_in_ds; 1768 hdspm->port_names_out = hdspm->port_names_out_ds; 1769 } else { 1770 hdspm->channel_map_in = hdspm->channel_map_in_qs; 1771 hdspm->channel_map_out = hdspm->channel_map_out_qs; 1772 hdspm->max_channels_in = hdspm->qs_in_channels; 1773 hdspm->max_channels_out = hdspm->qs_out_channels; 1774 hdspm->port_names_in = hdspm->port_names_in_qs; 1775 hdspm->port_names_out = hdspm->port_names_out_qs; 1776 } 1777 1778 if (not_set != 0) 1779 return -1; 1780 1781 return 0; 1782 } 1783 1784 /* mainly for init to 0 on load */ 1785 static void all_in_all_mixer(struct hdspm * hdspm, int sgain) 1786 { 1787 int i, j; 1788 unsigned int gain; 1789 1790 if (sgain > UNITY_GAIN) 1791 gain = UNITY_GAIN; 1792 else if (sgain < 0) 1793 gain = 0; 1794 else 1795 gain = sgain; 1796 1797 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) 1798 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { 1799 hdspm_write_in_gain(hdspm, i, j, gain); 1800 hdspm_write_pb_gain(hdspm, i, j, gain); 1801 } 1802 } 1803 1804 /*---------------------------------------------------------------------------- 1805 MIDI 1806 ----------------------------------------------------------------------------*/ 1807 1808 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, 1809 int id) 1810 { 1811 /* the hardware already does the relevant bit-mask with 0xff */ 1812 return hdspm_read(hdspm, hdspm->midi[id].dataIn); 1813 } 1814 1815 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, 1816 int val) 1817 { 1818 /* the hardware already does the relevant bit-mask with 0xff */ 1819 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); 1820 } 1821 1822 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) 1823 { 1824 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; 1825 } 1826 1827 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) 1828 { 1829 int fifo_bytes_used; 1830 1831 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; 1832 1833 if (fifo_bytes_used < 128) 1834 return 128 - fifo_bytes_used; 1835 else 1836 return 0; 1837 } 1838 1839 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) 1840 { 1841 int count = 256; 1842 1843 while (snd_hdspm_midi_input_available(hdspm, id) && --count) 1844 snd_hdspm_midi_read_byte(hdspm, id); 1845 } 1846 1847 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) 1848 { 1849 unsigned long flags; 1850 int n_pending; 1851 int to_write; 1852 int i; 1853 unsigned char buf[128]; 1854 1855 /* Output is not interrupt driven */ 1856 1857 spin_lock_irqsave (&hmidi->lock, flags); 1858 if (hmidi->output && 1859 !snd_rawmidi_transmit_empty (hmidi->output)) { 1860 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, 1861 hmidi->id); 1862 if (n_pending > 0) { 1863 if (n_pending > (int)sizeof (buf)) 1864 n_pending = sizeof (buf); 1865 1866 to_write = snd_rawmidi_transmit (hmidi->output, buf, 1867 n_pending); 1868 if (to_write > 0) { 1869 for (i = 0; i < to_write; ++i) 1870 snd_hdspm_midi_write_byte (hmidi->hdspm, 1871 hmidi->id, 1872 buf[i]); 1873 } 1874 } 1875 } 1876 spin_unlock_irqrestore (&hmidi->lock, flags); 1877 return 0; 1878 } 1879 1880 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) 1881 { 1882 unsigned char buf[128]; /* this buffer is designed to match the MIDI 1883 * input FIFO size 1884 */ 1885 unsigned long flags; 1886 int n_pending; 1887 int i; 1888 1889 spin_lock_irqsave (&hmidi->lock, flags); 1890 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); 1891 if (n_pending > 0) { 1892 if (hmidi->input) { 1893 if (n_pending > (int)sizeof (buf)) 1894 n_pending = sizeof (buf); 1895 for (i = 0; i < n_pending; ++i) 1896 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, 1897 hmidi->id); 1898 if (n_pending) 1899 snd_rawmidi_receive (hmidi->input, buf, 1900 n_pending); 1901 } else { 1902 /* flush the MIDI input FIFO */ 1903 while (n_pending--) 1904 snd_hdspm_midi_read_byte (hmidi->hdspm, 1905 hmidi->id); 1906 } 1907 } 1908 hmidi->pending = 0; 1909 spin_unlock_irqrestore(&hmidi->lock, flags); 1910 1911 spin_lock_irqsave(&hmidi->hdspm->lock, flags); 1912 hmidi->hdspm->control_register |= hmidi->ie; 1913 hdspm_write(hmidi->hdspm, HDSPM_controlRegister, 1914 hmidi->hdspm->control_register); 1915 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags); 1916 1917 return snd_hdspm_midi_output_write (hmidi); 1918 } 1919 1920 static void 1921 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1922 { 1923 struct hdspm *hdspm; 1924 struct hdspm_midi *hmidi; 1925 unsigned long flags; 1926 1927 hmidi = substream->rmidi->private_data; 1928 hdspm = hmidi->hdspm; 1929 1930 spin_lock_irqsave (&hdspm->lock, flags); 1931 if (up) { 1932 if (!(hdspm->control_register & hmidi->ie)) { 1933 snd_hdspm_flush_midi_input (hdspm, hmidi->id); 1934 hdspm->control_register |= hmidi->ie; 1935 } 1936 } else { 1937 hdspm->control_register &= ~hmidi->ie; 1938 } 1939 1940 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1941 spin_unlock_irqrestore (&hdspm->lock, flags); 1942 } 1943 1944 static void snd_hdspm_midi_output_timer(struct timer_list *t) 1945 { 1946 struct hdspm_midi *hmidi = from_timer(hmidi, t, timer); 1947 unsigned long flags; 1948 1949 snd_hdspm_midi_output_write(hmidi); 1950 spin_lock_irqsave (&hmidi->lock, flags); 1951 1952 /* this does not bump hmidi->istimer, because the 1953 kernel automatically removed the timer when it 1954 expired, and we are now adding it back, thus 1955 leaving istimer wherever it was set before. 1956 */ 1957 1958 if (hmidi->istimer) 1959 mod_timer(&hmidi->timer, 1 + jiffies); 1960 1961 spin_unlock_irqrestore (&hmidi->lock, flags); 1962 } 1963 1964 static void 1965 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1966 { 1967 struct hdspm_midi *hmidi; 1968 unsigned long flags; 1969 1970 hmidi = substream->rmidi->private_data; 1971 spin_lock_irqsave (&hmidi->lock, flags); 1972 if (up) { 1973 if (!hmidi->istimer) { 1974 timer_setup(&hmidi->timer, 1975 snd_hdspm_midi_output_timer, 0); 1976 mod_timer(&hmidi->timer, 1 + jiffies); 1977 hmidi->istimer++; 1978 } 1979 } else { 1980 if (hmidi->istimer && --hmidi->istimer <= 0) 1981 del_timer (&hmidi->timer); 1982 } 1983 spin_unlock_irqrestore (&hmidi->lock, flags); 1984 if (up) 1985 snd_hdspm_midi_output_write(hmidi); 1986 } 1987 1988 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) 1989 { 1990 struct hdspm_midi *hmidi; 1991 1992 hmidi = substream->rmidi->private_data; 1993 spin_lock_irq (&hmidi->lock); 1994 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); 1995 hmidi->input = substream; 1996 spin_unlock_irq (&hmidi->lock); 1997 1998 return 0; 1999 } 2000 2001 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) 2002 { 2003 struct hdspm_midi *hmidi; 2004 2005 hmidi = substream->rmidi->private_data; 2006 spin_lock_irq (&hmidi->lock); 2007 hmidi->output = substream; 2008 spin_unlock_irq (&hmidi->lock); 2009 2010 return 0; 2011 } 2012 2013 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) 2014 { 2015 struct hdspm_midi *hmidi; 2016 2017 snd_hdspm_midi_input_trigger (substream, 0); 2018 2019 hmidi = substream->rmidi->private_data; 2020 spin_lock_irq (&hmidi->lock); 2021 hmidi->input = NULL; 2022 spin_unlock_irq (&hmidi->lock); 2023 2024 return 0; 2025 } 2026 2027 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) 2028 { 2029 struct hdspm_midi *hmidi; 2030 2031 snd_hdspm_midi_output_trigger (substream, 0); 2032 2033 hmidi = substream->rmidi->private_data; 2034 spin_lock_irq (&hmidi->lock); 2035 hmidi->output = NULL; 2036 spin_unlock_irq (&hmidi->lock); 2037 2038 return 0; 2039 } 2040 2041 static const struct snd_rawmidi_ops snd_hdspm_midi_output = 2042 { 2043 .open = snd_hdspm_midi_output_open, 2044 .close = snd_hdspm_midi_output_close, 2045 .trigger = snd_hdspm_midi_output_trigger, 2046 }; 2047 2048 static const struct snd_rawmidi_ops snd_hdspm_midi_input = 2049 { 2050 .open = snd_hdspm_midi_input_open, 2051 .close = snd_hdspm_midi_input_close, 2052 .trigger = snd_hdspm_midi_input_trigger, 2053 }; 2054 2055 static int snd_hdspm_create_midi(struct snd_card *card, 2056 struct hdspm *hdspm, int id) 2057 { 2058 int err; 2059 char buf[64]; 2060 2061 hdspm->midi[id].id = id; 2062 hdspm->midi[id].hdspm = hdspm; 2063 spin_lock_init (&hdspm->midi[id].lock); 2064 2065 if (0 == id) { 2066 if (MADIface == hdspm->io_type) { 2067 /* MIDI-over-MADI on HDSPe MADIface */ 2068 hdspm->midi[0].dataIn = HDSPM_midiDataIn2; 2069 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; 2070 hdspm->midi[0].dataOut = HDSPM_midiDataOut2; 2071 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; 2072 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; 2073 hdspm->midi[0].irq = HDSPM_midi2IRQPending; 2074 } else { 2075 hdspm->midi[0].dataIn = HDSPM_midiDataIn0; 2076 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; 2077 hdspm->midi[0].dataOut = HDSPM_midiDataOut0; 2078 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; 2079 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; 2080 hdspm->midi[0].irq = HDSPM_midi0IRQPending; 2081 } 2082 } else if (1 == id) { 2083 hdspm->midi[1].dataIn = HDSPM_midiDataIn1; 2084 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; 2085 hdspm->midi[1].dataOut = HDSPM_midiDataOut1; 2086 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; 2087 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; 2088 hdspm->midi[1].irq = HDSPM_midi1IRQPending; 2089 } else if ((2 == id) && (MADI == hdspm->io_type)) { 2090 /* MIDI-over-MADI on HDSPe MADI */ 2091 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 2092 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 2093 hdspm->midi[2].dataOut = HDSPM_midiDataOut2; 2094 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; 2095 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 2096 hdspm->midi[2].irq = HDSPM_midi2IRQPending; 2097 } else if (2 == id) { 2098 /* TCO MTC, read only */ 2099 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 2100 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 2101 hdspm->midi[2].dataOut = -1; 2102 hdspm->midi[2].statusOut = -1; 2103 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 2104 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; 2105 } else if (3 == id) { 2106 /* TCO MTC on HDSPe MADI */ 2107 hdspm->midi[3].dataIn = HDSPM_midiDataIn3; 2108 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; 2109 hdspm->midi[3].dataOut = -1; 2110 hdspm->midi[3].statusOut = -1; 2111 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; 2112 hdspm->midi[3].irq = HDSPM_midi3IRQPending; 2113 } 2114 2115 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || 2116 (MADIface == hdspm->io_type)))) { 2117 if ((id == 0) && (MADIface == hdspm->io_type)) { 2118 snprintf(buf, sizeof(buf), "%s MIDIoverMADI", 2119 card->shortname); 2120 } else if ((id == 2) && (MADI == hdspm->io_type)) { 2121 snprintf(buf, sizeof(buf), "%s MIDIoverMADI", 2122 card->shortname); 2123 } else { 2124 snprintf(buf, sizeof(buf), "%s MIDI %d", 2125 card->shortname, id+1); 2126 } 2127 err = snd_rawmidi_new(card, buf, id, 1, 1, 2128 &hdspm->midi[id].rmidi); 2129 if (err < 0) 2130 return err; 2131 2132 snprintf(hdspm->midi[id].rmidi->name, 2133 sizeof(hdspm->midi[id].rmidi->name), 2134 "%s MIDI %d", card->id, id+1); 2135 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 2136 2137 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2138 SNDRV_RAWMIDI_STREAM_OUTPUT, 2139 &snd_hdspm_midi_output); 2140 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2141 SNDRV_RAWMIDI_STREAM_INPUT, 2142 &snd_hdspm_midi_input); 2143 2144 hdspm->midi[id].rmidi->info_flags |= 2145 SNDRV_RAWMIDI_INFO_OUTPUT | 2146 SNDRV_RAWMIDI_INFO_INPUT | 2147 SNDRV_RAWMIDI_INFO_DUPLEX; 2148 } else { 2149 /* TCO MTC, read only */ 2150 snprintf(buf, sizeof(buf), "%s MTC %d", 2151 card->shortname, id+1); 2152 err = snd_rawmidi_new(card, buf, id, 1, 1, 2153 &hdspm->midi[id].rmidi); 2154 if (err < 0) 2155 return err; 2156 2157 snprintf(hdspm->midi[id].rmidi->name, 2158 sizeof(hdspm->midi[id].rmidi->name), 2159 "%s MTC %d", card->id, id+1); 2160 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 2161 2162 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2163 SNDRV_RAWMIDI_STREAM_INPUT, 2164 &snd_hdspm_midi_input); 2165 2166 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; 2167 } 2168 2169 return 0; 2170 } 2171 2172 2173 static void hdspm_midi_work(struct work_struct *work) 2174 { 2175 struct hdspm *hdspm = container_of(work, struct hdspm, midi_work); 2176 int i = 0; 2177 2178 while (i < hdspm->midiPorts) { 2179 if (hdspm->midi[i].pending) 2180 snd_hdspm_midi_input_read(&hdspm->midi[i]); 2181 2182 i++; 2183 } 2184 } 2185 2186 2187 /*----------------------------------------------------------------------------- 2188 Status Interface 2189 ----------------------------------------------------------------------------*/ 2190 2191 /* get the system sample rate which is set */ 2192 2193 2194 static inline int hdspm_get_pll_freq(struct hdspm *hdspm) 2195 { 2196 unsigned int period, rate; 2197 2198 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 2199 rate = hdspm_calc_dds_value(hdspm, period); 2200 2201 return rate; 2202 } 2203 2204 /* 2205 * Calculate the real sample rate from the 2206 * current DDS value. 2207 */ 2208 static int hdspm_get_system_sample_rate(struct hdspm *hdspm) 2209 { 2210 unsigned int rate; 2211 2212 rate = hdspm_get_pll_freq(hdspm); 2213 2214 if (rate > 207000) { 2215 /* Unreasonable high sample rate as seen on PCI MADI cards. */ 2216 if (0 == hdspm_system_clock_mode(hdspm)) { 2217 /* master mode, return internal sample rate */ 2218 rate = hdspm->system_sample_rate; 2219 } else { 2220 /* slave mode, return external sample rate */ 2221 rate = hdspm_external_sample_rate(hdspm); 2222 if (!rate) 2223 rate = hdspm->system_sample_rate; 2224 } 2225 } 2226 2227 return rate; 2228 } 2229 2230 2231 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ 2232 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2233 .name = xname, \ 2234 .index = xindex, \ 2235 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2236 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2237 .info = snd_hdspm_info_system_sample_rate, \ 2238 .put = snd_hdspm_put_system_sample_rate, \ 2239 .get = snd_hdspm_get_system_sample_rate \ 2240 } 2241 2242 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, 2243 struct snd_ctl_elem_info *uinfo) 2244 { 2245 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2246 uinfo->count = 1; 2247 uinfo->value.integer.min = 27000; 2248 uinfo->value.integer.max = 207000; 2249 uinfo->value.integer.step = 1; 2250 return 0; 2251 } 2252 2253 2254 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, 2255 struct snd_ctl_elem_value * 2256 ucontrol) 2257 { 2258 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2259 2260 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); 2261 return 0; 2262 } 2263 2264 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol, 2265 struct snd_ctl_elem_value * 2266 ucontrol) 2267 { 2268 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2269 int rate = ucontrol->value.integer.value[0]; 2270 2271 if (rate < 27000 || rate > 207000) 2272 return -EINVAL; 2273 hdspm_set_dds_value(hdspm, ucontrol->value.integer.value[0]); 2274 return 0; 2275 } 2276 2277 2278 /* 2279 * Returns the WordClock sample rate class for the given card. 2280 */ 2281 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) 2282 { 2283 int status; 2284 2285 switch (hdspm->io_type) { 2286 case RayDAT: 2287 case AIO: 2288 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2289 return (status >> 16) & 0xF; 2290 case AES32: 2291 status = hdspm_read(hdspm, HDSPM_statusRegister); 2292 return (status >> HDSPM_AES32_wcFreq_bit) & 0xF; 2293 default: 2294 break; 2295 } 2296 2297 2298 return 0; 2299 } 2300 2301 2302 /* 2303 * Returns the TCO sample rate class for the given card. 2304 */ 2305 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) 2306 { 2307 int status; 2308 2309 if (hdspm->tco) { 2310 switch (hdspm->io_type) { 2311 case RayDAT: 2312 case AIO: 2313 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2314 return (status >> 20) & 0xF; 2315 case AES32: 2316 status = hdspm_read(hdspm, HDSPM_statusRegister); 2317 return (status >> 1) & 0xF; 2318 default: 2319 break; 2320 } 2321 } 2322 2323 return 0; 2324 } 2325 2326 2327 /* 2328 * Returns the SYNC_IN sample rate class for the given card. 2329 */ 2330 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) 2331 { 2332 int status; 2333 2334 if (hdspm->tco) { 2335 switch (hdspm->io_type) { 2336 case RayDAT: 2337 case AIO: 2338 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2339 return (status >> 12) & 0xF; 2340 default: 2341 break; 2342 } 2343 } 2344 2345 return 0; 2346 } 2347 2348 /* 2349 * Returns the AES sample rate class for the given card. 2350 */ 2351 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index) 2352 { 2353 int timecode; 2354 2355 switch (hdspm->io_type) { 2356 case AES32: 2357 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 2358 return (timecode >> (4*index)) & 0xF; 2359 default: 2360 break; 2361 } 2362 return 0; 2363 } 2364 2365 /* 2366 * Returns the sample rate class for input source <idx> for 2367 * 'new style' cards like the AIO and RayDAT. 2368 */ 2369 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) 2370 { 2371 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2372 2373 return (status >> (idx*4)) & 0xF; 2374 } 2375 2376 #define ENUMERATED_CTL_INFO(info, texts) \ 2377 snd_ctl_enum_info(info, 1, ARRAY_SIZE(texts), texts) 2378 2379 2380 /* Helper function to query the external sample rate and return the 2381 * corresponding enum to be returned to userspace. 2382 */ 2383 static int hdspm_external_rate_to_enum(struct hdspm *hdspm) 2384 { 2385 int rate = hdspm_external_sample_rate(hdspm); 2386 int i, selected_rate = 0; 2387 for (i = 1; i < 10; i++) 2388 if (HDSPM_bit2freq(i) == rate) { 2389 selected_rate = i; 2390 break; 2391 } 2392 return selected_rate; 2393 } 2394 2395 2396 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 2397 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2398 .name = xname, \ 2399 .private_value = xindex, \ 2400 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2401 .info = snd_hdspm_info_autosync_sample_rate, \ 2402 .get = snd_hdspm_get_autosync_sample_rate \ 2403 } 2404 2405 2406 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2407 struct snd_ctl_elem_info *uinfo) 2408 { 2409 ENUMERATED_CTL_INFO(uinfo, texts_freq); 2410 return 0; 2411 } 2412 2413 2414 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2415 struct snd_ctl_elem_value * 2416 ucontrol) 2417 { 2418 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2419 2420 switch (hdspm->io_type) { 2421 case RayDAT: 2422 switch (kcontrol->private_value) { 2423 case 0: 2424 ucontrol->value.enumerated.item[0] = 2425 hdspm_get_wc_sample_rate(hdspm); 2426 break; 2427 case 7: 2428 ucontrol->value.enumerated.item[0] = 2429 hdspm_get_tco_sample_rate(hdspm); 2430 break; 2431 case 8: 2432 ucontrol->value.enumerated.item[0] = 2433 hdspm_get_sync_in_sample_rate(hdspm); 2434 break; 2435 default: 2436 ucontrol->value.enumerated.item[0] = 2437 hdspm_get_s1_sample_rate(hdspm, 2438 kcontrol->private_value-1); 2439 } 2440 break; 2441 2442 case AIO: 2443 switch (kcontrol->private_value) { 2444 case 0: /* WC */ 2445 ucontrol->value.enumerated.item[0] = 2446 hdspm_get_wc_sample_rate(hdspm); 2447 break; 2448 case 4: /* TCO */ 2449 ucontrol->value.enumerated.item[0] = 2450 hdspm_get_tco_sample_rate(hdspm); 2451 break; 2452 case 5: /* SYNC_IN */ 2453 ucontrol->value.enumerated.item[0] = 2454 hdspm_get_sync_in_sample_rate(hdspm); 2455 break; 2456 default: 2457 ucontrol->value.enumerated.item[0] = 2458 hdspm_get_s1_sample_rate(hdspm, 2459 kcontrol->private_value-1); 2460 } 2461 break; 2462 2463 case AES32: 2464 2465 switch (kcontrol->private_value) { 2466 case 0: /* WC */ 2467 ucontrol->value.enumerated.item[0] = 2468 hdspm_get_wc_sample_rate(hdspm); 2469 break; 2470 case 9: /* TCO */ 2471 ucontrol->value.enumerated.item[0] = 2472 hdspm_get_tco_sample_rate(hdspm); 2473 break; 2474 case 10: /* SYNC_IN */ 2475 ucontrol->value.enumerated.item[0] = 2476 hdspm_get_sync_in_sample_rate(hdspm); 2477 break; 2478 case 11: /* External Rate */ 2479 ucontrol->value.enumerated.item[0] = 2480 hdspm_external_rate_to_enum(hdspm); 2481 break; 2482 default: /* AES1 to AES8 */ 2483 ucontrol->value.enumerated.item[0] = 2484 hdspm_get_aes_sample_rate(hdspm, 2485 kcontrol->private_value - 2486 HDSPM_AES32_AUTOSYNC_FROM_AES1); 2487 break; 2488 } 2489 break; 2490 2491 case MADI: 2492 case MADIface: 2493 ucontrol->value.enumerated.item[0] = 2494 hdspm_external_rate_to_enum(hdspm); 2495 break; 2496 default: 2497 break; 2498 } 2499 2500 return 0; 2501 } 2502 2503 2504 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ 2505 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2506 .name = xname, \ 2507 .index = xindex, \ 2508 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2509 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2510 .info = snd_hdspm_info_system_clock_mode, \ 2511 .get = snd_hdspm_get_system_clock_mode, \ 2512 .put = snd_hdspm_put_system_clock_mode, \ 2513 } 2514 2515 2516 /* 2517 * Returns the system clock mode for the given card. 2518 * @returns 0 - master, 1 - slave 2519 */ 2520 static int hdspm_system_clock_mode(struct hdspm *hdspm) 2521 { 2522 switch (hdspm->io_type) { 2523 case AIO: 2524 case RayDAT: 2525 if (hdspm->settings_register & HDSPM_c0Master) 2526 return 0; 2527 break; 2528 2529 default: 2530 if (hdspm->control_register & HDSPM_ClockModeMaster) 2531 return 0; 2532 } 2533 2534 return 1; 2535 } 2536 2537 2538 /* 2539 * Sets the system clock mode. 2540 * @param mode 0 - master, 1 - slave 2541 */ 2542 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) 2543 { 2544 hdspm_set_toggle_setting(hdspm, 2545 (hdspm_is_raydat_or_aio(hdspm)) ? 2546 HDSPM_c0Master : HDSPM_ClockModeMaster, 2547 (0 == mode)); 2548 } 2549 2550 2551 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, 2552 struct snd_ctl_elem_info *uinfo) 2553 { 2554 static const char *const texts[] = { "Master", "AutoSync" }; 2555 ENUMERATED_CTL_INFO(uinfo, texts); 2556 return 0; 2557 } 2558 2559 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, 2560 struct snd_ctl_elem_value *ucontrol) 2561 { 2562 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2563 2564 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); 2565 return 0; 2566 } 2567 2568 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, 2569 struct snd_ctl_elem_value *ucontrol) 2570 { 2571 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2572 int val; 2573 2574 if (!snd_hdspm_use_is_exclusive(hdspm)) 2575 return -EBUSY; 2576 2577 val = ucontrol->value.enumerated.item[0]; 2578 if (val < 0) 2579 val = 0; 2580 else if (val > 1) 2581 val = 1; 2582 2583 hdspm_set_system_clock_mode(hdspm, val); 2584 2585 return 0; 2586 } 2587 2588 2589 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ 2590 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2591 .name = xname, \ 2592 .index = xindex, \ 2593 .info = snd_hdspm_info_clock_source, \ 2594 .get = snd_hdspm_get_clock_source, \ 2595 .put = snd_hdspm_put_clock_source \ 2596 } 2597 2598 2599 static int hdspm_clock_source(struct hdspm * hdspm) 2600 { 2601 switch (hdspm->system_sample_rate) { 2602 case 32000: return 0; 2603 case 44100: return 1; 2604 case 48000: return 2; 2605 case 64000: return 3; 2606 case 88200: return 4; 2607 case 96000: return 5; 2608 case 128000: return 6; 2609 case 176400: return 7; 2610 case 192000: return 8; 2611 } 2612 2613 return -1; 2614 } 2615 2616 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) 2617 { 2618 int rate; 2619 switch (mode) { 2620 case 0: 2621 rate = 32000; break; 2622 case 1: 2623 rate = 44100; break; 2624 case 2: 2625 rate = 48000; break; 2626 case 3: 2627 rate = 64000; break; 2628 case 4: 2629 rate = 88200; break; 2630 case 5: 2631 rate = 96000; break; 2632 case 6: 2633 rate = 128000; break; 2634 case 7: 2635 rate = 176400; break; 2636 case 8: 2637 rate = 192000; break; 2638 default: 2639 rate = 48000; 2640 } 2641 hdspm_set_rate(hdspm, rate, 1); 2642 return 0; 2643 } 2644 2645 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, 2646 struct snd_ctl_elem_info *uinfo) 2647 { 2648 return snd_ctl_enum_info(uinfo, 1, 9, texts_freq + 1); 2649 } 2650 2651 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, 2652 struct snd_ctl_elem_value *ucontrol) 2653 { 2654 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2655 2656 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); 2657 return 0; 2658 } 2659 2660 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, 2661 struct snd_ctl_elem_value *ucontrol) 2662 { 2663 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2664 int change; 2665 int val; 2666 2667 if (!snd_hdspm_use_is_exclusive(hdspm)) 2668 return -EBUSY; 2669 val = ucontrol->value.enumerated.item[0]; 2670 if (val < 0) 2671 val = 0; 2672 if (val > 9) 2673 val = 9; 2674 spin_lock_irq(&hdspm->lock); 2675 if (val != hdspm_clock_source(hdspm)) 2676 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; 2677 else 2678 change = 0; 2679 spin_unlock_irq(&hdspm->lock); 2680 return change; 2681 } 2682 2683 2684 #define HDSPM_PREF_SYNC_REF(xname, xindex) \ 2685 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2686 .name = xname, \ 2687 .index = xindex, \ 2688 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2689 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2690 .info = snd_hdspm_info_pref_sync_ref, \ 2691 .get = snd_hdspm_get_pref_sync_ref, \ 2692 .put = snd_hdspm_put_pref_sync_ref \ 2693 } 2694 2695 2696 /* 2697 * Returns the current preferred sync reference setting. 2698 * The semantics of the return value are depending on the 2699 * card, please see the comments for clarification. 2700 */ 2701 static int hdspm_pref_sync_ref(struct hdspm * hdspm) 2702 { 2703 switch (hdspm->io_type) { 2704 case AES32: 2705 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2706 case 0: return 0; /* WC */ 2707 case HDSPM_SyncRef0: return 1; /* AES 1 */ 2708 case HDSPM_SyncRef1: return 2; /* AES 2 */ 2709 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ 2710 case HDSPM_SyncRef2: return 4; /* AES 4 */ 2711 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ 2712 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ 2713 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: 2714 return 7; /* AES 7 */ 2715 case HDSPM_SyncRef3: return 8; /* AES 8 */ 2716 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ 2717 } 2718 break; 2719 2720 case MADI: 2721 case MADIface: 2722 if (hdspm->tco) { 2723 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2724 case 0: return 0; /* WC */ 2725 case HDSPM_SyncRef0: return 1; /* MADI */ 2726 case HDSPM_SyncRef1: return 2; /* TCO */ 2727 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2728 return 3; /* SYNC_IN */ 2729 } 2730 } else { 2731 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2732 case 0: return 0; /* WC */ 2733 case HDSPM_SyncRef0: return 1; /* MADI */ 2734 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2735 return 2; /* SYNC_IN */ 2736 } 2737 } 2738 break; 2739 2740 case RayDAT: 2741 if (hdspm->tco) { 2742 switch ((hdspm->settings_register & 2743 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2744 case 0: return 0; /* WC */ 2745 case 3: return 1; /* ADAT 1 */ 2746 case 4: return 2; /* ADAT 2 */ 2747 case 5: return 3; /* ADAT 3 */ 2748 case 6: return 4; /* ADAT 4 */ 2749 case 1: return 5; /* AES */ 2750 case 2: return 6; /* SPDIF */ 2751 case 9: return 7; /* TCO */ 2752 case 10: return 8; /* SYNC_IN */ 2753 } 2754 } else { 2755 switch ((hdspm->settings_register & 2756 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2757 case 0: return 0; /* WC */ 2758 case 3: return 1; /* ADAT 1 */ 2759 case 4: return 2; /* ADAT 2 */ 2760 case 5: return 3; /* ADAT 3 */ 2761 case 6: return 4; /* ADAT 4 */ 2762 case 1: return 5; /* AES */ 2763 case 2: return 6; /* SPDIF */ 2764 case 10: return 7; /* SYNC_IN */ 2765 } 2766 } 2767 2768 break; 2769 2770 case AIO: 2771 if (hdspm->tco) { 2772 switch ((hdspm->settings_register & 2773 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2774 case 0: return 0; /* WC */ 2775 case 3: return 1; /* ADAT */ 2776 case 1: return 2; /* AES */ 2777 case 2: return 3; /* SPDIF */ 2778 case 9: return 4; /* TCO */ 2779 case 10: return 5; /* SYNC_IN */ 2780 } 2781 } else { 2782 switch ((hdspm->settings_register & 2783 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2784 case 0: return 0; /* WC */ 2785 case 3: return 1; /* ADAT */ 2786 case 1: return 2; /* AES */ 2787 case 2: return 3; /* SPDIF */ 2788 case 10: return 4; /* SYNC_IN */ 2789 } 2790 } 2791 2792 break; 2793 } 2794 2795 return -1; 2796 } 2797 2798 2799 /* 2800 * Set the preferred sync reference to <pref>. The semantics 2801 * of <pref> are depending on the card type, see the comments 2802 * for clarification. 2803 */ 2804 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) 2805 { 2806 int p = 0; 2807 2808 switch (hdspm->io_type) { 2809 case AES32: 2810 hdspm->control_register &= ~HDSPM_SyncRefMask; 2811 switch (pref) { 2812 case 0: /* WC */ 2813 break; 2814 case 1: /* AES 1 */ 2815 hdspm->control_register |= HDSPM_SyncRef0; 2816 break; 2817 case 2: /* AES 2 */ 2818 hdspm->control_register |= HDSPM_SyncRef1; 2819 break; 2820 case 3: /* AES 3 */ 2821 hdspm->control_register |= 2822 HDSPM_SyncRef1+HDSPM_SyncRef0; 2823 break; 2824 case 4: /* AES 4 */ 2825 hdspm->control_register |= HDSPM_SyncRef2; 2826 break; 2827 case 5: /* AES 5 */ 2828 hdspm->control_register |= 2829 HDSPM_SyncRef2+HDSPM_SyncRef0; 2830 break; 2831 case 6: /* AES 6 */ 2832 hdspm->control_register |= 2833 HDSPM_SyncRef2+HDSPM_SyncRef1; 2834 break; 2835 case 7: /* AES 7 */ 2836 hdspm->control_register |= 2837 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; 2838 break; 2839 case 8: /* AES 8 */ 2840 hdspm->control_register |= HDSPM_SyncRef3; 2841 break; 2842 case 9: /* TCO */ 2843 hdspm->control_register |= 2844 HDSPM_SyncRef3+HDSPM_SyncRef0; 2845 break; 2846 default: 2847 return -1; 2848 } 2849 2850 break; 2851 2852 case MADI: 2853 case MADIface: 2854 hdspm->control_register &= ~HDSPM_SyncRefMask; 2855 if (hdspm->tco) { 2856 switch (pref) { 2857 case 0: /* WC */ 2858 break; 2859 case 1: /* MADI */ 2860 hdspm->control_register |= HDSPM_SyncRef0; 2861 break; 2862 case 2: /* TCO */ 2863 hdspm->control_register |= HDSPM_SyncRef1; 2864 break; 2865 case 3: /* SYNC_IN */ 2866 hdspm->control_register |= 2867 HDSPM_SyncRef0+HDSPM_SyncRef1; 2868 break; 2869 default: 2870 return -1; 2871 } 2872 } else { 2873 switch (pref) { 2874 case 0: /* WC */ 2875 break; 2876 case 1: /* MADI */ 2877 hdspm->control_register |= HDSPM_SyncRef0; 2878 break; 2879 case 2: /* SYNC_IN */ 2880 hdspm->control_register |= 2881 HDSPM_SyncRef0+HDSPM_SyncRef1; 2882 break; 2883 default: 2884 return -1; 2885 } 2886 } 2887 2888 break; 2889 2890 case RayDAT: 2891 if (hdspm->tco) { 2892 switch (pref) { 2893 case 0: p = 0; break; /* WC */ 2894 case 1: p = 3; break; /* ADAT 1 */ 2895 case 2: p = 4; break; /* ADAT 2 */ 2896 case 3: p = 5; break; /* ADAT 3 */ 2897 case 4: p = 6; break; /* ADAT 4 */ 2898 case 5: p = 1; break; /* AES */ 2899 case 6: p = 2; break; /* SPDIF */ 2900 case 7: p = 9; break; /* TCO */ 2901 case 8: p = 10; break; /* SYNC_IN */ 2902 default: return -1; 2903 } 2904 } else { 2905 switch (pref) { 2906 case 0: p = 0; break; /* WC */ 2907 case 1: p = 3; break; /* ADAT 1 */ 2908 case 2: p = 4; break; /* ADAT 2 */ 2909 case 3: p = 5; break; /* ADAT 3 */ 2910 case 4: p = 6; break; /* ADAT 4 */ 2911 case 5: p = 1; break; /* AES */ 2912 case 6: p = 2; break; /* SPDIF */ 2913 case 7: p = 10; break; /* SYNC_IN */ 2914 default: return -1; 2915 } 2916 } 2917 break; 2918 2919 case AIO: 2920 if (hdspm->tco) { 2921 switch (pref) { 2922 case 0: p = 0; break; /* WC */ 2923 case 1: p = 3; break; /* ADAT */ 2924 case 2: p = 1; break; /* AES */ 2925 case 3: p = 2; break; /* SPDIF */ 2926 case 4: p = 9; break; /* TCO */ 2927 case 5: p = 10; break; /* SYNC_IN */ 2928 default: return -1; 2929 } 2930 } else { 2931 switch (pref) { 2932 case 0: p = 0; break; /* WC */ 2933 case 1: p = 3; break; /* ADAT */ 2934 case 2: p = 1; break; /* AES */ 2935 case 3: p = 2; break; /* SPDIF */ 2936 case 4: p = 10; break; /* SYNC_IN */ 2937 default: return -1; 2938 } 2939 } 2940 break; 2941 } 2942 2943 switch (hdspm->io_type) { 2944 case RayDAT: 2945 case AIO: 2946 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; 2947 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; 2948 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2949 break; 2950 2951 case MADI: 2952 case MADIface: 2953 case AES32: 2954 hdspm_write(hdspm, HDSPM_controlRegister, 2955 hdspm->control_register); 2956 } 2957 2958 return 0; 2959 } 2960 2961 2962 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, 2963 struct snd_ctl_elem_info *uinfo) 2964 { 2965 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2966 2967 snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync); 2968 2969 return 0; 2970 } 2971 2972 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, 2973 struct snd_ctl_elem_value *ucontrol) 2974 { 2975 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2976 int psf = hdspm_pref_sync_ref(hdspm); 2977 2978 if (psf >= 0) { 2979 ucontrol->value.enumerated.item[0] = psf; 2980 return 0; 2981 } 2982 2983 return -1; 2984 } 2985 2986 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, 2987 struct snd_ctl_elem_value *ucontrol) 2988 { 2989 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2990 int val, change = 0; 2991 2992 if (!snd_hdspm_use_is_exclusive(hdspm)) 2993 return -EBUSY; 2994 2995 val = ucontrol->value.enumerated.item[0]; 2996 2997 if (val < 0) 2998 val = 0; 2999 else if (val >= hdspm->texts_autosync_items) 3000 val = hdspm->texts_autosync_items-1; 3001 3002 spin_lock_irq(&hdspm->lock); 3003 if (val != hdspm_pref_sync_ref(hdspm)) 3004 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; 3005 3006 spin_unlock_irq(&hdspm->lock); 3007 return change; 3008 } 3009 3010 3011 #define HDSPM_AUTOSYNC_REF(xname, xindex) \ 3012 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3013 .name = xname, \ 3014 .index = xindex, \ 3015 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 3016 .info = snd_hdspm_info_autosync_ref, \ 3017 .get = snd_hdspm_get_autosync_ref, \ 3018 } 3019 3020 static int hdspm_autosync_ref(struct hdspm *hdspm) 3021 { 3022 /* This looks at the autosync selected sync reference */ 3023 if (AES32 == hdspm->io_type) { 3024 3025 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); 3026 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF; 3027 /* syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD is always true */ 3028 if (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN) { 3029 return syncref; 3030 } 3031 return HDSPM_AES32_AUTOSYNC_FROM_NONE; 3032 3033 } else if (MADI == hdspm->io_type) { 3034 3035 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3036 switch (status2 & HDSPM_SelSyncRefMask) { 3037 case HDSPM_SelSyncRef_WORD: 3038 return HDSPM_AUTOSYNC_FROM_WORD; 3039 case HDSPM_SelSyncRef_MADI: 3040 return HDSPM_AUTOSYNC_FROM_MADI; 3041 case HDSPM_SelSyncRef_TCO: 3042 return HDSPM_AUTOSYNC_FROM_TCO; 3043 case HDSPM_SelSyncRef_SyncIn: 3044 return HDSPM_AUTOSYNC_FROM_SYNC_IN; 3045 case HDSPM_SelSyncRef_NVALID: 3046 return HDSPM_AUTOSYNC_FROM_NONE; 3047 default: 3048 return HDSPM_AUTOSYNC_FROM_NONE; 3049 } 3050 3051 } 3052 return 0; 3053 } 3054 3055 3056 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, 3057 struct snd_ctl_elem_info *uinfo) 3058 { 3059 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3060 3061 if (AES32 == hdspm->io_type) { 3062 static const char *const texts[] = { "WordClock", "AES1", "AES2", "AES3", 3063 "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"}; 3064 3065 ENUMERATED_CTL_INFO(uinfo, texts); 3066 } else if (MADI == hdspm->io_type) { 3067 static const char *const texts[] = {"Word Clock", "MADI", "TCO", 3068 "Sync In", "None" }; 3069 3070 ENUMERATED_CTL_INFO(uinfo, texts); 3071 } 3072 return 0; 3073 } 3074 3075 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, 3076 struct snd_ctl_elem_value *ucontrol) 3077 { 3078 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3079 3080 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); 3081 return 0; 3082 } 3083 3084 3085 3086 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname) \ 3087 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3088 .name = xname, \ 3089 .access = SNDRV_CTL_ELEM_ACCESS_READ |\ 3090 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3091 .info = snd_hdspm_info_tco_video_input_format, \ 3092 .get = snd_hdspm_get_tco_video_input_format, \ 3093 } 3094 3095 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol, 3096 struct snd_ctl_elem_info *uinfo) 3097 { 3098 static const char *const texts[] = {"No video", "NTSC", "PAL"}; 3099 ENUMERATED_CTL_INFO(uinfo, texts); 3100 return 0; 3101 } 3102 3103 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol, 3104 struct snd_ctl_elem_value *ucontrol) 3105 { 3106 u32 status; 3107 int ret = 0; 3108 3109 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3110 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3111 switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC | 3112 HDSPM_TCO1_Video_Input_Format_PAL)) { 3113 case HDSPM_TCO1_Video_Input_Format_NTSC: 3114 /* ntsc */ 3115 ret = 1; 3116 break; 3117 case HDSPM_TCO1_Video_Input_Format_PAL: 3118 /* pal */ 3119 ret = 2; 3120 break; 3121 default: 3122 /* no video */ 3123 ret = 0; 3124 break; 3125 } 3126 ucontrol->value.enumerated.item[0] = ret; 3127 return 0; 3128 } 3129 3130 3131 3132 #define HDSPM_TCO_LTC_FRAMES(xname) \ 3133 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3134 .name = xname, \ 3135 .access = SNDRV_CTL_ELEM_ACCESS_READ |\ 3136 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3137 .info = snd_hdspm_info_tco_ltc_frames, \ 3138 .get = snd_hdspm_get_tco_ltc_frames, \ 3139 } 3140 3141 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol, 3142 struct snd_ctl_elem_info *uinfo) 3143 { 3144 static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps", 3145 "30 fps"}; 3146 ENUMERATED_CTL_INFO(uinfo, texts); 3147 return 0; 3148 } 3149 3150 static int hdspm_tco_ltc_frames(struct hdspm *hdspm) 3151 { 3152 u32 status; 3153 int ret = 0; 3154 3155 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3156 if (status & HDSPM_TCO1_LTC_Input_valid) { 3157 switch (status & (HDSPM_TCO1_LTC_Format_LSB | 3158 HDSPM_TCO1_LTC_Format_MSB)) { 3159 case 0: 3160 /* 24 fps */ 3161 ret = fps_24; 3162 break; 3163 case HDSPM_TCO1_LTC_Format_LSB: 3164 /* 25 fps */ 3165 ret = fps_25; 3166 break; 3167 case HDSPM_TCO1_LTC_Format_MSB: 3168 /* 29.97 fps */ 3169 ret = fps_2997; 3170 break; 3171 default: 3172 /* 30 fps */ 3173 ret = fps_30; 3174 break; 3175 } 3176 } 3177 3178 return ret; 3179 } 3180 3181 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol, 3182 struct snd_ctl_elem_value *ucontrol) 3183 { 3184 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3185 3186 ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm); 3187 return 0; 3188 } 3189 3190 #define HDSPM_TOGGLE_SETTING(xname, xindex) \ 3191 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3192 .name = xname, \ 3193 .private_value = xindex, \ 3194 .info = snd_hdspm_info_toggle_setting, \ 3195 .get = snd_hdspm_get_toggle_setting, \ 3196 .put = snd_hdspm_put_toggle_setting \ 3197 } 3198 3199 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask) 3200 { 3201 u32 reg; 3202 3203 if (hdspm_is_raydat_or_aio(hdspm)) 3204 reg = hdspm->settings_register; 3205 else 3206 reg = hdspm->control_register; 3207 3208 return (reg & regmask) ? 1 : 0; 3209 } 3210 3211 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out) 3212 { 3213 u32 *reg; 3214 u32 target_reg; 3215 3216 if (hdspm_is_raydat_or_aio(hdspm)) { 3217 reg = &(hdspm->settings_register); 3218 target_reg = HDSPM_WR_SETTINGS; 3219 } else { 3220 reg = &(hdspm->control_register); 3221 target_reg = HDSPM_controlRegister; 3222 } 3223 3224 if (out) 3225 *reg |= regmask; 3226 else 3227 *reg &= ~regmask; 3228 3229 hdspm_write(hdspm, target_reg, *reg); 3230 3231 return 0; 3232 } 3233 3234 #define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info 3235 3236 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol, 3237 struct snd_ctl_elem_value *ucontrol) 3238 { 3239 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3240 u32 regmask = kcontrol->private_value; 3241 3242 spin_lock_irq(&hdspm->lock); 3243 ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask); 3244 spin_unlock_irq(&hdspm->lock); 3245 return 0; 3246 } 3247 3248 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol, 3249 struct snd_ctl_elem_value *ucontrol) 3250 { 3251 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3252 u32 regmask = kcontrol->private_value; 3253 int change; 3254 unsigned int val; 3255 3256 if (!snd_hdspm_use_is_exclusive(hdspm)) 3257 return -EBUSY; 3258 val = ucontrol->value.integer.value[0] & 1; 3259 spin_lock_irq(&hdspm->lock); 3260 change = (int) val != hdspm_toggle_setting(hdspm, regmask); 3261 hdspm_set_toggle_setting(hdspm, regmask, val); 3262 spin_unlock_irq(&hdspm->lock); 3263 return change; 3264 } 3265 3266 #define HDSPM_INPUT_SELECT(xname, xindex) \ 3267 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3268 .name = xname, \ 3269 .index = xindex, \ 3270 .info = snd_hdspm_info_input_select, \ 3271 .get = snd_hdspm_get_input_select, \ 3272 .put = snd_hdspm_put_input_select \ 3273 } 3274 3275 static int hdspm_input_select(struct hdspm * hdspm) 3276 { 3277 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; 3278 } 3279 3280 static int hdspm_set_input_select(struct hdspm * hdspm, int out) 3281 { 3282 if (out) 3283 hdspm->control_register |= HDSPM_InputSelect0; 3284 else 3285 hdspm->control_register &= ~HDSPM_InputSelect0; 3286 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3287 3288 return 0; 3289 } 3290 3291 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, 3292 struct snd_ctl_elem_info *uinfo) 3293 { 3294 static const char *const texts[] = { "optical", "coaxial" }; 3295 ENUMERATED_CTL_INFO(uinfo, texts); 3296 return 0; 3297 } 3298 3299 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, 3300 struct snd_ctl_elem_value *ucontrol) 3301 { 3302 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3303 3304 spin_lock_irq(&hdspm->lock); 3305 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); 3306 spin_unlock_irq(&hdspm->lock); 3307 return 0; 3308 } 3309 3310 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, 3311 struct snd_ctl_elem_value *ucontrol) 3312 { 3313 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3314 int change; 3315 unsigned int val; 3316 3317 if (!snd_hdspm_use_is_exclusive(hdspm)) 3318 return -EBUSY; 3319 val = ucontrol->value.integer.value[0] & 1; 3320 spin_lock_irq(&hdspm->lock); 3321 change = (int) val != hdspm_input_select(hdspm); 3322 hdspm_set_input_select(hdspm, val); 3323 spin_unlock_irq(&hdspm->lock); 3324 return change; 3325 } 3326 3327 3328 #define HDSPM_DS_WIRE(xname, xindex) \ 3329 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3330 .name = xname, \ 3331 .index = xindex, \ 3332 .info = snd_hdspm_info_ds_wire, \ 3333 .get = snd_hdspm_get_ds_wire, \ 3334 .put = snd_hdspm_put_ds_wire \ 3335 } 3336 3337 static int hdspm_ds_wire(struct hdspm * hdspm) 3338 { 3339 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; 3340 } 3341 3342 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) 3343 { 3344 if (ds) 3345 hdspm->control_register |= HDSPM_DS_DoubleWire; 3346 else 3347 hdspm->control_register &= ~HDSPM_DS_DoubleWire; 3348 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3349 3350 return 0; 3351 } 3352 3353 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, 3354 struct snd_ctl_elem_info *uinfo) 3355 { 3356 static const char *const texts[] = { "Single", "Double" }; 3357 ENUMERATED_CTL_INFO(uinfo, texts); 3358 return 0; 3359 } 3360 3361 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, 3362 struct snd_ctl_elem_value *ucontrol) 3363 { 3364 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3365 3366 spin_lock_irq(&hdspm->lock); 3367 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); 3368 spin_unlock_irq(&hdspm->lock); 3369 return 0; 3370 } 3371 3372 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, 3373 struct snd_ctl_elem_value *ucontrol) 3374 { 3375 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3376 int change; 3377 unsigned int val; 3378 3379 if (!snd_hdspm_use_is_exclusive(hdspm)) 3380 return -EBUSY; 3381 val = ucontrol->value.integer.value[0] & 1; 3382 spin_lock_irq(&hdspm->lock); 3383 change = (int) val != hdspm_ds_wire(hdspm); 3384 hdspm_set_ds_wire(hdspm, val); 3385 spin_unlock_irq(&hdspm->lock); 3386 return change; 3387 } 3388 3389 3390 #define HDSPM_QS_WIRE(xname, xindex) \ 3391 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3392 .name = xname, \ 3393 .index = xindex, \ 3394 .info = snd_hdspm_info_qs_wire, \ 3395 .get = snd_hdspm_get_qs_wire, \ 3396 .put = snd_hdspm_put_qs_wire \ 3397 } 3398 3399 static int hdspm_qs_wire(struct hdspm * hdspm) 3400 { 3401 if (hdspm->control_register & HDSPM_QS_DoubleWire) 3402 return 1; 3403 if (hdspm->control_register & HDSPM_QS_QuadWire) 3404 return 2; 3405 return 0; 3406 } 3407 3408 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) 3409 { 3410 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); 3411 switch (mode) { 3412 case 0: 3413 break; 3414 case 1: 3415 hdspm->control_register |= HDSPM_QS_DoubleWire; 3416 break; 3417 case 2: 3418 hdspm->control_register |= HDSPM_QS_QuadWire; 3419 break; 3420 } 3421 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3422 3423 return 0; 3424 } 3425 3426 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, 3427 struct snd_ctl_elem_info *uinfo) 3428 { 3429 static const char *const texts[] = { "Single", "Double", "Quad" }; 3430 ENUMERATED_CTL_INFO(uinfo, texts); 3431 return 0; 3432 } 3433 3434 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, 3435 struct snd_ctl_elem_value *ucontrol) 3436 { 3437 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3438 3439 spin_lock_irq(&hdspm->lock); 3440 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); 3441 spin_unlock_irq(&hdspm->lock); 3442 return 0; 3443 } 3444 3445 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, 3446 struct snd_ctl_elem_value *ucontrol) 3447 { 3448 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3449 int change; 3450 int val; 3451 3452 if (!snd_hdspm_use_is_exclusive(hdspm)) 3453 return -EBUSY; 3454 val = ucontrol->value.integer.value[0]; 3455 if (val < 0) 3456 val = 0; 3457 if (val > 2) 3458 val = 2; 3459 spin_lock_irq(&hdspm->lock); 3460 change = val != hdspm_qs_wire(hdspm); 3461 hdspm_set_qs_wire(hdspm, val); 3462 spin_unlock_irq(&hdspm->lock); 3463 return change; 3464 } 3465 3466 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \ 3467 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3468 .name = xname, \ 3469 .private_value = xindex, \ 3470 .info = snd_hdspm_info_tristate, \ 3471 .get = snd_hdspm_get_tristate, \ 3472 .put = snd_hdspm_put_tristate \ 3473 } 3474 3475 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask) 3476 { 3477 u32 reg = hdspm->settings_register & (regmask * 3); 3478 return reg / regmask; 3479 } 3480 3481 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask) 3482 { 3483 hdspm->settings_register &= ~(regmask * 3); 3484 hdspm->settings_register |= (regmask * mode); 3485 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 3486 3487 return 0; 3488 } 3489 3490 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol, 3491 struct snd_ctl_elem_info *uinfo) 3492 { 3493 u32 regmask = kcontrol->private_value; 3494 3495 static const char *const texts_spdif[] = { "Optical", "Coaxial", "Internal" }; 3496 static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" }; 3497 3498 switch (regmask) { 3499 case HDSPM_c0_Input0: 3500 ENUMERATED_CTL_INFO(uinfo, texts_spdif); 3501 break; 3502 default: 3503 ENUMERATED_CTL_INFO(uinfo, texts_levels); 3504 break; 3505 } 3506 return 0; 3507 } 3508 3509 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol, 3510 struct snd_ctl_elem_value *ucontrol) 3511 { 3512 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3513 u32 regmask = kcontrol->private_value; 3514 3515 spin_lock_irq(&hdspm->lock); 3516 ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask); 3517 spin_unlock_irq(&hdspm->lock); 3518 return 0; 3519 } 3520 3521 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol, 3522 struct snd_ctl_elem_value *ucontrol) 3523 { 3524 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3525 u32 regmask = kcontrol->private_value; 3526 int change; 3527 int val; 3528 3529 if (!snd_hdspm_use_is_exclusive(hdspm)) 3530 return -EBUSY; 3531 val = ucontrol->value.integer.value[0]; 3532 if (val < 0) 3533 val = 0; 3534 if (val > 2) 3535 val = 2; 3536 3537 spin_lock_irq(&hdspm->lock); 3538 change = val != hdspm_tristate(hdspm, regmask); 3539 hdspm_set_tristate(hdspm, val, regmask); 3540 spin_unlock_irq(&hdspm->lock); 3541 return change; 3542 } 3543 3544 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \ 3545 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3546 .name = xname, \ 3547 .index = xindex, \ 3548 .info = snd_hdspm_info_madi_speedmode, \ 3549 .get = snd_hdspm_get_madi_speedmode, \ 3550 .put = snd_hdspm_put_madi_speedmode \ 3551 } 3552 3553 static int hdspm_madi_speedmode(struct hdspm *hdspm) 3554 { 3555 if (hdspm->control_register & HDSPM_QuadSpeed) 3556 return 2; 3557 if (hdspm->control_register & HDSPM_DoubleSpeed) 3558 return 1; 3559 return 0; 3560 } 3561 3562 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode) 3563 { 3564 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed); 3565 switch (mode) { 3566 case 0: 3567 break; 3568 case 1: 3569 hdspm->control_register |= HDSPM_DoubleSpeed; 3570 break; 3571 case 2: 3572 hdspm->control_register |= HDSPM_QuadSpeed; 3573 break; 3574 } 3575 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3576 3577 return 0; 3578 } 3579 3580 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol, 3581 struct snd_ctl_elem_info *uinfo) 3582 { 3583 static const char *const texts[] = { "Single", "Double", "Quad" }; 3584 ENUMERATED_CTL_INFO(uinfo, texts); 3585 return 0; 3586 } 3587 3588 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol, 3589 struct snd_ctl_elem_value *ucontrol) 3590 { 3591 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3592 3593 spin_lock_irq(&hdspm->lock); 3594 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm); 3595 spin_unlock_irq(&hdspm->lock); 3596 return 0; 3597 } 3598 3599 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol, 3600 struct snd_ctl_elem_value *ucontrol) 3601 { 3602 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3603 int change; 3604 int val; 3605 3606 if (!snd_hdspm_use_is_exclusive(hdspm)) 3607 return -EBUSY; 3608 val = ucontrol->value.integer.value[0]; 3609 if (val < 0) 3610 val = 0; 3611 if (val > 2) 3612 val = 2; 3613 spin_lock_irq(&hdspm->lock); 3614 change = val != hdspm_madi_speedmode(hdspm); 3615 hdspm_set_madi_speedmode(hdspm, val); 3616 spin_unlock_irq(&hdspm->lock); 3617 return change; 3618 } 3619 3620 #define HDSPM_MIXER(xname, xindex) \ 3621 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 3622 .name = xname, \ 3623 .index = xindex, \ 3624 .device = 0, \ 3625 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3626 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3627 .info = snd_hdspm_info_mixer, \ 3628 .get = snd_hdspm_get_mixer, \ 3629 .put = snd_hdspm_put_mixer \ 3630 } 3631 3632 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, 3633 struct snd_ctl_elem_info *uinfo) 3634 { 3635 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3636 uinfo->count = 3; 3637 uinfo->value.integer.min = 0; 3638 uinfo->value.integer.max = 65535; 3639 uinfo->value.integer.step = 1; 3640 return 0; 3641 } 3642 3643 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, 3644 struct snd_ctl_elem_value *ucontrol) 3645 { 3646 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3647 int source; 3648 int destination; 3649 3650 source = ucontrol->value.integer.value[0]; 3651 if (source < 0) 3652 source = 0; 3653 else if (source >= 2 * HDSPM_MAX_CHANNELS) 3654 source = 2 * HDSPM_MAX_CHANNELS - 1; 3655 3656 destination = ucontrol->value.integer.value[1]; 3657 if (destination < 0) 3658 destination = 0; 3659 else if (destination >= HDSPM_MAX_CHANNELS) 3660 destination = HDSPM_MAX_CHANNELS - 1; 3661 3662 spin_lock_irq(&hdspm->lock); 3663 if (source >= HDSPM_MAX_CHANNELS) 3664 ucontrol->value.integer.value[2] = 3665 hdspm_read_pb_gain(hdspm, destination, 3666 source - HDSPM_MAX_CHANNELS); 3667 else 3668 ucontrol->value.integer.value[2] = 3669 hdspm_read_in_gain(hdspm, destination, source); 3670 3671 spin_unlock_irq(&hdspm->lock); 3672 3673 return 0; 3674 } 3675 3676 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, 3677 struct snd_ctl_elem_value *ucontrol) 3678 { 3679 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3680 int change; 3681 int source; 3682 int destination; 3683 int gain; 3684 3685 if (!snd_hdspm_use_is_exclusive(hdspm)) 3686 return -EBUSY; 3687 3688 source = ucontrol->value.integer.value[0]; 3689 destination = ucontrol->value.integer.value[1]; 3690 3691 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) 3692 return -1; 3693 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) 3694 return -1; 3695 3696 gain = ucontrol->value.integer.value[2]; 3697 3698 spin_lock_irq(&hdspm->lock); 3699 3700 if (source >= HDSPM_MAX_CHANNELS) 3701 change = gain != hdspm_read_pb_gain(hdspm, destination, 3702 source - 3703 HDSPM_MAX_CHANNELS); 3704 else 3705 change = gain != hdspm_read_in_gain(hdspm, destination, 3706 source); 3707 3708 if (change) { 3709 if (source >= HDSPM_MAX_CHANNELS) 3710 hdspm_write_pb_gain(hdspm, destination, 3711 source - HDSPM_MAX_CHANNELS, 3712 gain); 3713 else 3714 hdspm_write_in_gain(hdspm, destination, source, 3715 gain); 3716 } 3717 spin_unlock_irq(&hdspm->lock); 3718 3719 return change; 3720 } 3721 3722 /* The simple mixer control(s) provide gain control for the 3723 basic 1:1 mappings of playback streams to output 3724 streams. 3725 */ 3726 3727 #define HDSPM_PLAYBACK_MIXER \ 3728 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3729 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ 3730 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3731 .info = snd_hdspm_info_playback_mixer, \ 3732 .get = snd_hdspm_get_playback_mixer, \ 3733 .put = snd_hdspm_put_playback_mixer \ 3734 } 3735 3736 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, 3737 struct snd_ctl_elem_info *uinfo) 3738 { 3739 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3740 uinfo->count = 1; 3741 uinfo->value.integer.min = 0; 3742 uinfo->value.integer.max = 64; 3743 uinfo->value.integer.step = 1; 3744 return 0; 3745 } 3746 3747 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, 3748 struct snd_ctl_elem_value *ucontrol) 3749 { 3750 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3751 int channel; 3752 3753 channel = ucontrol->id.index - 1; 3754 3755 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3756 return -EINVAL; 3757 3758 spin_lock_irq(&hdspm->lock); 3759 ucontrol->value.integer.value[0] = 3760 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN; 3761 spin_unlock_irq(&hdspm->lock); 3762 3763 return 0; 3764 } 3765 3766 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, 3767 struct snd_ctl_elem_value *ucontrol) 3768 { 3769 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3770 int change; 3771 int channel; 3772 int gain; 3773 3774 if (!snd_hdspm_use_is_exclusive(hdspm)) 3775 return -EBUSY; 3776 3777 channel = ucontrol->id.index - 1; 3778 3779 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3780 return -EINVAL; 3781 3782 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64; 3783 3784 spin_lock_irq(&hdspm->lock); 3785 change = 3786 gain != hdspm_read_pb_gain(hdspm, channel, 3787 channel); 3788 if (change) 3789 hdspm_write_pb_gain(hdspm, channel, channel, 3790 gain); 3791 spin_unlock_irq(&hdspm->lock); 3792 return change; 3793 } 3794 3795 #define HDSPM_SYNC_CHECK(xname, xindex) \ 3796 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3797 .name = xname, \ 3798 .private_value = xindex, \ 3799 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3800 .info = snd_hdspm_info_sync_check, \ 3801 .get = snd_hdspm_get_sync_check \ 3802 } 3803 3804 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \ 3805 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3806 .name = xname, \ 3807 .private_value = xindex, \ 3808 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3809 .info = snd_hdspm_tco_info_lock_check, \ 3810 .get = snd_hdspm_get_sync_check \ 3811 } 3812 3813 3814 3815 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, 3816 struct snd_ctl_elem_info *uinfo) 3817 { 3818 static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" }; 3819 ENUMERATED_CTL_INFO(uinfo, texts); 3820 return 0; 3821 } 3822 3823 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol, 3824 struct snd_ctl_elem_info *uinfo) 3825 { 3826 static const char *const texts[] = { "No Lock", "Lock" }; 3827 ENUMERATED_CTL_INFO(uinfo, texts); 3828 return 0; 3829 } 3830 3831 static int hdspm_wc_sync_check(struct hdspm *hdspm) 3832 { 3833 int status, status2; 3834 3835 switch (hdspm->io_type) { 3836 case AES32: 3837 status = hdspm_read(hdspm, HDSPM_statusRegister); 3838 if (status & HDSPM_AES32_wcLock) { 3839 if (status & HDSPM_AES32_wcSync) 3840 return 2; 3841 else 3842 return 1; 3843 } 3844 return 0; 3845 3846 case MADI: 3847 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3848 if (status2 & HDSPM_wcLock) { 3849 if (status2 & HDSPM_wcSync) 3850 return 2; 3851 else 3852 return 1; 3853 } 3854 return 0; 3855 3856 case RayDAT: 3857 case AIO: 3858 status = hdspm_read(hdspm, HDSPM_statusRegister); 3859 3860 if (status & 0x2000000) 3861 return 2; 3862 else if (status & 0x1000000) 3863 return 1; 3864 return 0; 3865 3866 case MADIface: 3867 break; 3868 } 3869 3870 3871 return 3; 3872 } 3873 3874 3875 static int hdspm_madi_sync_check(struct hdspm *hdspm) 3876 { 3877 int status = hdspm_read(hdspm, HDSPM_statusRegister); 3878 if (status & HDSPM_madiLock) { 3879 if (status & HDSPM_madiSync) 3880 return 2; 3881 else 3882 return 1; 3883 } 3884 return 0; 3885 } 3886 3887 3888 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx) 3889 { 3890 int status, lock, sync; 3891 3892 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3893 3894 lock = (status & (0x1<<idx)) ? 1 : 0; 3895 sync = (status & (0x100<<idx)) ? 1 : 0; 3896 3897 if (lock && sync) 3898 return 2; 3899 else if (lock) 3900 return 1; 3901 return 0; 3902 } 3903 3904 3905 static int hdspm_sync_in_sync_check(struct hdspm *hdspm) 3906 { 3907 int status, lock = 0, sync = 0; 3908 3909 switch (hdspm->io_type) { 3910 case RayDAT: 3911 case AIO: 3912 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3); 3913 lock = (status & 0x400) ? 1 : 0; 3914 sync = (status & 0x800) ? 1 : 0; 3915 break; 3916 3917 case MADI: 3918 status = hdspm_read(hdspm, HDSPM_statusRegister); 3919 lock = (status & HDSPM_syncInLock) ? 1 : 0; 3920 sync = (status & HDSPM_syncInSync) ? 1 : 0; 3921 break; 3922 3923 case AES32: 3924 status = hdspm_read(hdspm, HDSPM_statusRegister2); 3925 lock = (status & 0x100000) ? 1 : 0; 3926 sync = (status & 0x200000) ? 1 : 0; 3927 break; 3928 3929 case MADIface: 3930 break; 3931 } 3932 3933 if (lock && sync) 3934 return 2; 3935 else if (lock) 3936 return 1; 3937 3938 return 0; 3939 } 3940 3941 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx) 3942 { 3943 int status2, lock, sync; 3944 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3945 3946 lock = (status2 & (0x0080 >> idx)) ? 1 : 0; 3947 sync = (status2 & (0x8000 >> idx)) ? 1 : 0; 3948 3949 if (sync) 3950 return 2; 3951 else if (lock) 3952 return 1; 3953 return 0; 3954 } 3955 3956 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask) 3957 { 3958 u32 status; 3959 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3960 3961 return (status & mask) ? 1 : 0; 3962 } 3963 3964 3965 static int hdspm_tco_sync_check(struct hdspm *hdspm) 3966 { 3967 int status; 3968 3969 if (hdspm->tco) { 3970 switch (hdspm->io_type) { 3971 case MADI: 3972 status = hdspm_read(hdspm, HDSPM_statusRegister); 3973 if (status & HDSPM_tcoLockMadi) { 3974 if (status & HDSPM_tcoSync) 3975 return 2; 3976 else 3977 return 1; 3978 } 3979 return 0; 3980 case AES32: 3981 status = hdspm_read(hdspm, HDSPM_statusRegister); 3982 if (status & HDSPM_tcoLockAes) { 3983 if (status & HDSPM_tcoSync) 3984 return 2; 3985 else 3986 return 1; 3987 } 3988 return 0; 3989 case RayDAT: 3990 case AIO: 3991 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3992 3993 if (status & 0x8000000) 3994 return 2; /* Sync */ 3995 if (status & 0x4000000) 3996 return 1; /* Lock */ 3997 return 0; /* No signal */ 3998 3999 default: 4000 break; 4001 } 4002 } 4003 4004 return 3; /* N/A */ 4005 } 4006 4007 4008 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol, 4009 struct snd_ctl_elem_value *ucontrol) 4010 { 4011 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4012 int val = -1; 4013 4014 switch (hdspm->io_type) { 4015 case RayDAT: 4016 switch (kcontrol->private_value) { 4017 case 0: /* WC */ 4018 val = hdspm_wc_sync_check(hdspm); break; 4019 case 7: /* TCO */ 4020 val = hdspm_tco_sync_check(hdspm); break; 4021 case 8: /* SYNC IN */ 4022 val = hdspm_sync_in_sync_check(hdspm); break; 4023 default: 4024 val = hdspm_s1_sync_check(hdspm, 4025 kcontrol->private_value-1); 4026 } 4027 break; 4028 4029 case AIO: 4030 switch (kcontrol->private_value) { 4031 case 0: /* WC */ 4032 val = hdspm_wc_sync_check(hdspm); break; 4033 case 4: /* TCO */ 4034 val = hdspm_tco_sync_check(hdspm); break; 4035 case 5: /* SYNC IN */ 4036 val = hdspm_sync_in_sync_check(hdspm); break; 4037 default: 4038 val = hdspm_s1_sync_check(hdspm, 4039 kcontrol->private_value-1); 4040 } 4041 break; 4042 4043 case MADI: 4044 switch (kcontrol->private_value) { 4045 case 0: /* WC */ 4046 val = hdspm_wc_sync_check(hdspm); break; 4047 case 1: /* MADI */ 4048 val = hdspm_madi_sync_check(hdspm); break; 4049 case 2: /* TCO */ 4050 val = hdspm_tco_sync_check(hdspm); break; 4051 case 3: /* SYNC_IN */ 4052 val = hdspm_sync_in_sync_check(hdspm); break; 4053 } 4054 break; 4055 4056 case MADIface: 4057 val = hdspm_madi_sync_check(hdspm); /* MADI */ 4058 break; 4059 4060 case AES32: 4061 switch (kcontrol->private_value) { 4062 case 0: /* WC */ 4063 val = hdspm_wc_sync_check(hdspm); break; 4064 case 9: /* TCO */ 4065 val = hdspm_tco_sync_check(hdspm); break; 4066 case 10 /* SYNC IN */: 4067 val = hdspm_sync_in_sync_check(hdspm); break; 4068 default: /* AES1 to AES8 */ 4069 val = hdspm_aes_sync_check(hdspm, 4070 kcontrol->private_value-1); 4071 } 4072 break; 4073 4074 } 4075 4076 if (hdspm->tco) { 4077 switch (kcontrol->private_value) { 4078 case 11: 4079 /* Check TCO for lock state of its current input */ 4080 val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock); 4081 break; 4082 case 12: 4083 /* Check TCO for valid time code on LTC input. */ 4084 val = hdspm_tco_input_check(hdspm, 4085 HDSPM_TCO1_LTC_Input_valid); 4086 break; 4087 default: 4088 break; 4089 } 4090 } 4091 4092 if (-1 == val) 4093 val = 3; 4094 4095 ucontrol->value.enumerated.item[0] = val; 4096 return 0; 4097 } 4098 4099 4100 4101 /* 4102 * TCO controls 4103 */ 4104 static void hdspm_tco_write(struct hdspm *hdspm) 4105 { 4106 unsigned int tc[4] = { 0, 0, 0, 0}; 4107 4108 switch (hdspm->tco->input) { 4109 case 0: 4110 tc[2] |= HDSPM_TCO2_set_input_MSB; 4111 break; 4112 case 1: 4113 tc[2] |= HDSPM_TCO2_set_input_LSB; 4114 break; 4115 default: 4116 break; 4117 } 4118 4119 switch (hdspm->tco->framerate) { 4120 case 1: 4121 tc[1] |= HDSPM_TCO1_LTC_Format_LSB; 4122 break; 4123 case 2: 4124 tc[1] |= HDSPM_TCO1_LTC_Format_MSB; 4125 break; 4126 case 3: 4127 tc[1] |= HDSPM_TCO1_LTC_Format_MSB + 4128 HDSPM_TCO1_set_drop_frame_flag; 4129 break; 4130 case 4: 4131 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 4132 HDSPM_TCO1_LTC_Format_MSB; 4133 break; 4134 case 5: 4135 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 4136 HDSPM_TCO1_LTC_Format_MSB + 4137 HDSPM_TCO1_set_drop_frame_flag; 4138 break; 4139 default: 4140 break; 4141 } 4142 4143 switch (hdspm->tco->wordclock) { 4144 case 1: 4145 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB; 4146 break; 4147 case 2: 4148 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB; 4149 break; 4150 default: 4151 break; 4152 } 4153 4154 switch (hdspm->tco->samplerate) { 4155 case 1: 4156 tc[2] |= HDSPM_TCO2_set_freq; 4157 break; 4158 case 2: 4159 tc[2] |= HDSPM_TCO2_set_freq_from_app; 4160 break; 4161 default: 4162 break; 4163 } 4164 4165 switch (hdspm->tco->pull) { 4166 case 1: 4167 tc[2] |= HDSPM_TCO2_set_pull_up; 4168 break; 4169 case 2: 4170 tc[2] |= HDSPM_TCO2_set_pull_down; 4171 break; 4172 case 3: 4173 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4; 4174 break; 4175 case 4: 4176 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4; 4177 break; 4178 default: 4179 break; 4180 } 4181 4182 if (1 == hdspm->tco->term) { 4183 tc[2] |= HDSPM_TCO2_set_term_75R; 4184 } 4185 4186 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]); 4187 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]); 4188 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]); 4189 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]); 4190 } 4191 4192 4193 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \ 4194 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4195 .name = xname, \ 4196 .index = xindex, \ 4197 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4198 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4199 .info = snd_hdspm_info_tco_sample_rate, \ 4200 .get = snd_hdspm_get_tco_sample_rate, \ 4201 .put = snd_hdspm_put_tco_sample_rate \ 4202 } 4203 4204 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol, 4205 struct snd_ctl_elem_info *uinfo) 4206 { 4207 /* TODO freq from app could be supported here, see tco->samplerate */ 4208 static const char *const texts[] = { "44.1 kHz", "48 kHz" }; 4209 ENUMERATED_CTL_INFO(uinfo, texts); 4210 return 0; 4211 } 4212 4213 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol, 4214 struct snd_ctl_elem_value *ucontrol) 4215 { 4216 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4217 4218 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate; 4219 4220 return 0; 4221 } 4222 4223 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol, 4224 struct snd_ctl_elem_value *ucontrol) 4225 { 4226 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4227 4228 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) { 4229 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0]; 4230 4231 hdspm_tco_write(hdspm); 4232 4233 return 1; 4234 } 4235 4236 return 0; 4237 } 4238 4239 4240 #define HDSPM_TCO_PULL(xname, xindex) \ 4241 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4242 .name = xname, \ 4243 .index = xindex, \ 4244 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4245 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4246 .info = snd_hdspm_info_tco_pull, \ 4247 .get = snd_hdspm_get_tco_pull, \ 4248 .put = snd_hdspm_put_tco_pull \ 4249 } 4250 4251 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol, 4252 struct snd_ctl_elem_info *uinfo) 4253 { 4254 static const char *const texts[] = { "0", "+ 0.1 %", "- 0.1 %", 4255 "+ 4 %", "- 4 %" }; 4256 ENUMERATED_CTL_INFO(uinfo, texts); 4257 return 0; 4258 } 4259 4260 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol, 4261 struct snd_ctl_elem_value *ucontrol) 4262 { 4263 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4264 4265 ucontrol->value.enumerated.item[0] = hdspm->tco->pull; 4266 4267 return 0; 4268 } 4269 4270 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol, 4271 struct snd_ctl_elem_value *ucontrol) 4272 { 4273 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4274 4275 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) { 4276 hdspm->tco->pull = ucontrol->value.enumerated.item[0]; 4277 4278 hdspm_tco_write(hdspm); 4279 4280 return 1; 4281 } 4282 4283 return 0; 4284 } 4285 4286 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \ 4287 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4288 .name = xname, \ 4289 .index = xindex, \ 4290 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4291 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4292 .info = snd_hdspm_info_tco_wck_conversion, \ 4293 .get = snd_hdspm_get_tco_wck_conversion, \ 4294 .put = snd_hdspm_put_tco_wck_conversion \ 4295 } 4296 4297 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4298 struct snd_ctl_elem_info *uinfo) 4299 { 4300 static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" }; 4301 ENUMERATED_CTL_INFO(uinfo, texts); 4302 return 0; 4303 } 4304 4305 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4306 struct snd_ctl_elem_value *ucontrol) 4307 { 4308 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4309 4310 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock; 4311 4312 return 0; 4313 } 4314 4315 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4316 struct snd_ctl_elem_value *ucontrol) 4317 { 4318 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4319 4320 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) { 4321 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0]; 4322 4323 hdspm_tco_write(hdspm); 4324 4325 return 1; 4326 } 4327 4328 return 0; 4329 } 4330 4331 4332 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \ 4333 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4334 .name = xname, \ 4335 .index = xindex, \ 4336 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4337 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4338 .info = snd_hdspm_info_tco_frame_rate, \ 4339 .get = snd_hdspm_get_tco_frame_rate, \ 4340 .put = snd_hdspm_put_tco_frame_rate \ 4341 } 4342 4343 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol, 4344 struct snd_ctl_elem_info *uinfo) 4345 { 4346 static const char *const texts[] = { "24 fps", "25 fps", "29.97fps", 4347 "29.97 dfps", "30 fps", "30 dfps" }; 4348 ENUMERATED_CTL_INFO(uinfo, texts); 4349 return 0; 4350 } 4351 4352 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol, 4353 struct snd_ctl_elem_value *ucontrol) 4354 { 4355 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4356 4357 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate; 4358 4359 return 0; 4360 } 4361 4362 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol, 4363 struct snd_ctl_elem_value *ucontrol) 4364 { 4365 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4366 4367 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) { 4368 hdspm->tco->framerate = ucontrol->value.enumerated.item[0]; 4369 4370 hdspm_tco_write(hdspm); 4371 4372 return 1; 4373 } 4374 4375 return 0; 4376 } 4377 4378 4379 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \ 4380 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4381 .name = xname, \ 4382 .index = xindex, \ 4383 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4384 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4385 .info = snd_hdspm_info_tco_sync_source, \ 4386 .get = snd_hdspm_get_tco_sync_source, \ 4387 .put = snd_hdspm_put_tco_sync_source \ 4388 } 4389 4390 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol, 4391 struct snd_ctl_elem_info *uinfo) 4392 { 4393 static const char *const texts[] = { "LTC", "Video", "WCK" }; 4394 ENUMERATED_CTL_INFO(uinfo, texts); 4395 return 0; 4396 } 4397 4398 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol, 4399 struct snd_ctl_elem_value *ucontrol) 4400 { 4401 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4402 4403 ucontrol->value.enumerated.item[0] = hdspm->tco->input; 4404 4405 return 0; 4406 } 4407 4408 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol, 4409 struct snd_ctl_elem_value *ucontrol) 4410 { 4411 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4412 4413 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) { 4414 hdspm->tco->input = ucontrol->value.enumerated.item[0]; 4415 4416 hdspm_tco_write(hdspm); 4417 4418 return 1; 4419 } 4420 4421 return 0; 4422 } 4423 4424 4425 #define HDSPM_TCO_WORD_TERM(xname, xindex) \ 4426 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4427 .name = xname, \ 4428 .index = xindex, \ 4429 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4430 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4431 .info = snd_hdspm_info_tco_word_term, \ 4432 .get = snd_hdspm_get_tco_word_term, \ 4433 .put = snd_hdspm_put_tco_word_term \ 4434 } 4435 4436 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol, 4437 struct snd_ctl_elem_info *uinfo) 4438 { 4439 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 4440 uinfo->count = 1; 4441 uinfo->value.integer.min = 0; 4442 uinfo->value.integer.max = 1; 4443 4444 return 0; 4445 } 4446 4447 4448 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol, 4449 struct snd_ctl_elem_value *ucontrol) 4450 { 4451 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4452 4453 ucontrol->value.integer.value[0] = hdspm->tco->term; 4454 4455 return 0; 4456 } 4457 4458 4459 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol, 4460 struct snd_ctl_elem_value *ucontrol) 4461 { 4462 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4463 4464 if (hdspm->tco->term != ucontrol->value.integer.value[0]) { 4465 hdspm->tco->term = ucontrol->value.integer.value[0]; 4466 4467 hdspm_tco_write(hdspm); 4468 4469 return 1; 4470 } 4471 4472 return 0; 4473 } 4474 4475 4476 4477 4478 static const struct snd_kcontrol_new snd_hdspm_controls_madi[] = { 4479 HDSPM_MIXER("Mixer", 0), 4480 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4481 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4482 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4483 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4484 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4485 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4486 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4487 HDSPM_SYNC_CHECK("MADI SyncCheck", 1), 4488 HDSPM_SYNC_CHECK("TCO SyncCheck", 2), 4489 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3), 4490 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4491 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4492 HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX), 4493 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4494 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4495 HDSPM_INPUT_SELECT("Input Select", 0), 4496 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4497 }; 4498 4499 4500 static const struct snd_kcontrol_new snd_hdspm_controls_madiface[] = { 4501 HDSPM_MIXER("Mixer", 0), 4502 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4503 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4504 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4505 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4506 HDSPM_SYNC_CHECK("MADI SyncCheck", 0), 4507 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4508 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4509 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4510 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4511 }; 4512 4513 static const struct snd_kcontrol_new snd_hdspm_controls_aio[] = { 4514 HDSPM_MIXER("Mixer", 0), 4515 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4516 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4517 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4518 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4519 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4520 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4521 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4522 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4523 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3), 4524 HDSPM_SYNC_CHECK("TCO SyncCheck", 4), 4525 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5), 4526 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4527 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4528 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4529 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3), 4530 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4), 4531 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5), 4532 HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0), 4533 HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt), 4534 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro), 4535 HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1), 4536 HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db), 4537 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48), 4538 HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0), 4539 HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0), 4540 HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0) 4541 4542 /* 4543 HDSPM_INPUT_SELECT("Input Select", 0), 4544 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0), 4545 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0); 4546 HDSPM_SPDIF_IN("SPDIF In", 0); 4547 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0); 4548 HDSPM_INPUT_LEVEL("Input Level", 0); 4549 HDSPM_OUTPUT_LEVEL("Output Level", 0); 4550 HDSPM_PHONES("Phones", 0); 4551 */ 4552 }; 4553 4554 static const struct snd_kcontrol_new snd_hdspm_controls_raydat[] = { 4555 HDSPM_MIXER("Mixer", 0), 4556 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4557 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0), 4558 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0), 4559 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4560 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4561 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4562 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4563 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3), 4564 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4), 4565 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5), 4566 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6), 4567 HDSPM_SYNC_CHECK("TCO SyncCheck", 7), 4568 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8), 4569 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4570 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4571 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4572 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3), 4573 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4), 4574 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5), 4575 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6), 4576 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7), 4577 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8), 4578 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro), 4579 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48) 4580 }; 4581 4582 static const struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { 4583 HDSPM_MIXER("Mixer", 0), 4584 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4585 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4586 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4587 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4588 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4589 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 11), 4590 HDSPM_SYNC_CHECK("WC Sync Check", 0), 4591 HDSPM_SYNC_CHECK("AES1 Sync Check", 1), 4592 HDSPM_SYNC_CHECK("AES2 Sync Check", 2), 4593 HDSPM_SYNC_CHECK("AES3 Sync Check", 3), 4594 HDSPM_SYNC_CHECK("AES4 Sync Check", 4), 4595 HDSPM_SYNC_CHECK("AES5 Sync Check", 5), 4596 HDSPM_SYNC_CHECK("AES6 Sync Check", 6), 4597 HDSPM_SYNC_CHECK("AES7 Sync Check", 7), 4598 HDSPM_SYNC_CHECK("AES8 Sync Check", 8), 4599 HDSPM_SYNC_CHECK("TCO Sync Check", 9), 4600 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10), 4601 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4602 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1), 4603 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2), 4604 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3), 4605 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4), 4606 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5), 4607 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6), 4608 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7), 4609 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8), 4610 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9), 4611 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10), 4612 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4613 HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis), 4614 HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby), 4615 HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional), 4616 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4617 HDSPM_DS_WIRE("Double Speed Wire Mode", 0), 4618 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), 4619 }; 4620 4621 4622 4623 /* Control elements for the optional TCO module */ 4624 static const struct snd_kcontrol_new snd_hdspm_controls_tco[] = { 4625 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0), 4626 HDSPM_TCO_PULL("TCO Pull", 0), 4627 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0), 4628 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0), 4629 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0), 4630 HDSPM_TCO_WORD_TERM("TCO Word Term", 0), 4631 HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11), 4632 HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12), 4633 HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate"), 4634 HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format") 4635 }; 4636 4637 4638 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; 4639 4640 4641 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) 4642 { 4643 int i; 4644 4645 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) { 4646 if (hdspm->system_sample_rate > 48000) { 4647 hdspm->playback_mixer_ctls[i]->vd[0].access = 4648 SNDRV_CTL_ELEM_ACCESS_INACTIVE | 4649 SNDRV_CTL_ELEM_ACCESS_READ | 4650 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4651 } else { 4652 hdspm->playback_mixer_ctls[i]->vd[0].access = 4653 SNDRV_CTL_ELEM_ACCESS_READWRITE | 4654 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4655 } 4656 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | 4657 SNDRV_CTL_EVENT_MASK_INFO, 4658 &hdspm->playback_mixer_ctls[i]->id); 4659 } 4660 4661 return 0; 4662 } 4663 4664 4665 static int snd_hdspm_create_controls(struct snd_card *card, 4666 struct hdspm *hdspm) 4667 { 4668 unsigned int idx, limit; 4669 int err; 4670 struct snd_kcontrol *kctl; 4671 const struct snd_kcontrol_new *list = NULL; 4672 4673 switch (hdspm->io_type) { 4674 case MADI: 4675 list = snd_hdspm_controls_madi; 4676 limit = ARRAY_SIZE(snd_hdspm_controls_madi); 4677 break; 4678 case MADIface: 4679 list = snd_hdspm_controls_madiface; 4680 limit = ARRAY_SIZE(snd_hdspm_controls_madiface); 4681 break; 4682 case AIO: 4683 list = snd_hdspm_controls_aio; 4684 limit = ARRAY_SIZE(snd_hdspm_controls_aio); 4685 break; 4686 case RayDAT: 4687 list = snd_hdspm_controls_raydat; 4688 limit = ARRAY_SIZE(snd_hdspm_controls_raydat); 4689 break; 4690 case AES32: 4691 list = snd_hdspm_controls_aes32; 4692 limit = ARRAY_SIZE(snd_hdspm_controls_aes32); 4693 break; 4694 } 4695 4696 if (list) { 4697 for (idx = 0; idx < limit; idx++) { 4698 err = snd_ctl_add(card, 4699 snd_ctl_new1(&list[idx], hdspm)); 4700 if (err < 0) 4701 return err; 4702 } 4703 } 4704 4705 4706 /* create simple 1:1 playback mixer controls */ 4707 snd_hdspm_playback_mixer.name = "Chn"; 4708 if (hdspm->system_sample_rate >= 128000) { 4709 limit = hdspm->qs_out_channels; 4710 } else if (hdspm->system_sample_rate >= 64000) { 4711 limit = hdspm->ds_out_channels; 4712 } else { 4713 limit = hdspm->ss_out_channels; 4714 } 4715 for (idx = 0; idx < limit; ++idx) { 4716 snd_hdspm_playback_mixer.index = idx + 1; 4717 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); 4718 err = snd_ctl_add(card, kctl); 4719 if (err < 0) 4720 return err; 4721 hdspm->playback_mixer_ctls[idx] = kctl; 4722 } 4723 4724 4725 if (hdspm->tco) { 4726 /* add tco control elements */ 4727 list = snd_hdspm_controls_tco; 4728 limit = ARRAY_SIZE(snd_hdspm_controls_tco); 4729 for (idx = 0; idx < limit; idx++) { 4730 err = snd_ctl_add(card, 4731 snd_ctl_new1(&list[idx], hdspm)); 4732 if (err < 0) 4733 return err; 4734 } 4735 } 4736 4737 return 0; 4738 } 4739 4740 /*------------------------------------------------------------ 4741 /proc interface 4742 ------------------------------------------------------------*/ 4743 4744 static void 4745 snd_hdspm_proc_read_tco(struct snd_info_entry *entry, 4746 struct snd_info_buffer *buffer) 4747 { 4748 struct hdspm *hdspm = entry->private_data; 4749 unsigned int status, control; 4750 int a, ltc, frames, seconds, minutes, hours; 4751 unsigned int period; 4752 u64 freq_const = 0; 4753 u32 rate; 4754 4755 snd_iprintf(buffer, "--- TCO ---\n"); 4756 4757 status = hdspm_read(hdspm, HDSPM_statusRegister); 4758 control = hdspm->control_register; 4759 4760 4761 if (status & HDSPM_tco_detect) { 4762 snd_iprintf(buffer, "TCO module detected.\n"); 4763 a = hdspm_read(hdspm, HDSPM_RD_TCO+4); 4764 if (a & HDSPM_TCO1_LTC_Input_valid) { 4765 snd_iprintf(buffer, " LTC valid, "); 4766 switch (a & (HDSPM_TCO1_LTC_Format_LSB | 4767 HDSPM_TCO1_LTC_Format_MSB)) { 4768 case 0: 4769 snd_iprintf(buffer, "24 fps, "); 4770 break; 4771 case HDSPM_TCO1_LTC_Format_LSB: 4772 snd_iprintf(buffer, "25 fps, "); 4773 break; 4774 case HDSPM_TCO1_LTC_Format_MSB: 4775 snd_iprintf(buffer, "29.97 fps, "); 4776 break; 4777 default: 4778 snd_iprintf(buffer, "30 fps, "); 4779 break; 4780 } 4781 if (a & HDSPM_TCO1_set_drop_frame_flag) { 4782 snd_iprintf(buffer, "drop frame\n"); 4783 } else { 4784 snd_iprintf(buffer, "full frame\n"); 4785 } 4786 } else { 4787 snd_iprintf(buffer, " no LTC\n"); 4788 } 4789 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) { 4790 snd_iprintf(buffer, " Video: NTSC\n"); 4791 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) { 4792 snd_iprintf(buffer, " Video: PAL\n"); 4793 } else { 4794 snd_iprintf(buffer, " No video\n"); 4795 } 4796 if (a & HDSPM_TCO1_TCO_lock) { 4797 snd_iprintf(buffer, " Sync: lock\n"); 4798 } else { 4799 snd_iprintf(buffer, " Sync: no lock\n"); 4800 } 4801 4802 switch (hdspm->io_type) { 4803 case MADI: 4804 case AES32: 4805 freq_const = 110069313433624ULL; 4806 break; 4807 case RayDAT: 4808 case AIO: 4809 freq_const = 104857600000000ULL; 4810 break; 4811 case MADIface: 4812 break; /* no TCO possible */ 4813 } 4814 4815 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 4816 snd_iprintf(buffer, " period: %u\n", period); 4817 4818 4819 /* rate = freq_const/period; */ 4820 rate = div_u64(freq_const, period); 4821 4822 if (control & HDSPM_QuadSpeed) { 4823 rate *= 4; 4824 } else if (control & HDSPM_DoubleSpeed) { 4825 rate *= 2; 4826 } 4827 4828 snd_iprintf(buffer, " Frequency: %u Hz\n", 4829 (unsigned int) rate); 4830 4831 ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 4832 frames = ltc & 0xF; 4833 ltc >>= 4; 4834 frames += (ltc & 0x3) * 10; 4835 ltc >>= 4; 4836 seconds = ltc & 0xF; 4837 ltc >>= 4; 4838 seconds += (ltc & 0x7) * 10; 4839 ltc >>= 4; 4840 minutes = ltc & 0xF; 4841 ltc >>= 4; 4842 minutes += (ltc & 0x7) * 10; 4843 ltc >>= 4; 4844 hours = ltc & 0xF; 4845 ltc >>= 4; 4846 hours += (ltc & 0x3) * 10; 4847 snd_iprintf(buffer, 4848 " LTC In: %02d:%02d:%02d:%02d\n", 4849 hours, minutes, seconds, frames); 4850 4851 } else { 4852 snd_iprintf(buffer, "No TCO module detected.\n"); 4853 } 4854 } 4855 4856 static void 4857 snd_hdspm_proc_read_madi(struct snd_info_entry *entry, 4858 struct snd_info_buffer *buffer) 4859 { 4860 struct hdspm *hdspm = entry->private_data; 4861 unsigned int status, status2; 4862 4863 char *pref_sync_ref; 4864 char *autosync_ref; 4865 char *system_clock_mode; 4866 int x, x2; 4867 4868 status = hdspm_read(hdspm, HDSPM_statusRegister); 4869 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4870 4871 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", 4872 hdspm->card_name, hdspm->card->number + 1, 4873 hdspm->firmware_rev, 4874 (status2 & HDSPM_version0) | 4875 (status2 & HDSPM_version1) | (status2 & 4876 HDSPM_version2)); 4877 4878 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n", 4879 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF, 4880 hdspm->serial); 4881 4882 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4883 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4884 4885 snd_iprintf(buffer, "--- System ---\n"); 4886 4887 snd_iprintf(buffer, 4888 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4889 status & HDSPM_audioIRQPending, 4890 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4891 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4892 hdspm->irq_count); 4893 snd_iprintf(buffer, 4894 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4895 "estimated= %ld (bytes)\n", 4896 ((status & HDSPM_BufferID) ? 1 : 0), 4897 (status & HDSPM_BufferPositionMask), 4898 (status & HDSPM_BufferPositionMask) % 4899 (2 * (int)hdspm->period_bytes), 4900 ((status & HDSPM_BufferPositionMask) - 64) % 4901 (2 * (int)hdspm->period_bytes), 4902 (long) hdspm_hw_pointer(hdspm) * 4); 4903 4904 snd_iprintf(buffer, 4905 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4906 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4907 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4908 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4909 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4910 snd_iprintf(buffer, 4911 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4912 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4913 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4914 snd_iprintf(buffer, 4915 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4916 "status2=0x%x\n", 4917 hdspm->control_register, hdspm->control2_register, 4918 status, status2); 4919 4920 4921 snd_iprintf(buffer, "--- Settings ---\n"); 4922 4923 x = hdspm_get_latency(hdspm); 4924 4925 snd_iprintf(buffer, 4926 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4927 x, (unsigned long) hdspm->period_bytes); 4928 4929 snd_iprintf(buffer, "Line out: %s\n", 4930 str_on_off(hdspm->control_register & HDSPM_LineOut)); 4931 4932 snd_iprintf(buffer, 4933 "ClearTrackMarker = %s, Transmit in %s Channel Mode, " 4934 "Auto Input %s\n", 4935 str_on_off(hdspm->control_register & HDSPM_clr_tms), 4936 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", 4937 str_on_off(hdspm->control_register & HDSPM_AutoInp)); 4938 4939 4940 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) 4941 system_clock_mode = "AutoSync"; 4942 else 4943 system_clock_mode = "Master"; 4944 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode); 4945 4946 switch (hdspm_pref_sync_ref(hdspm)) { 4947 case HDSPM_SYNC_FROM_WORD: 4948 pref_sync_ref = "Word Clock"; 4949 break; 4950 case HDSPM_SYNC_FROM_MADI: 4951 pref_sync_ref = "MADI Sync"; 4952 break; 4953 case HDSPM_SYNC_FROM_TCO: 4954 pref_sync_ref = "TCO"; 4955 break; 4956 case HDSPM_SYNC_FROM_SYNC_IN: 4957 pref_sync_ref = "Sync In"; 4958 break; 4959 default: 4960 pref_sync_ref = "XXXX Clock"; 4961 break; 4962 } 4963 snd_iprintf(buffer, "Preferred Sync Reference: %s\n", 4964 pref_sync_ref); 4965 4966 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4967 hdspm->system_sample_rate); 4968 4969 4970 snd_iprintf(buffer, "--- Status:\n"); 4971 4972 x = status & HDSPM_madiSync; 4973 x2 = status2 & HDSPM_wcSync; 4974 4975 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", 4976 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : 4977 "NoLock", 4978 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : 4979 "NoLock"); 4980 4981 switch (hdspm_autosync_ref(hdspm)) { 4982 case HDSPM_AUTOSYNC_FROM_SYNC_IN: 4983 autosync_ref = "Sync In"; 4984 break; 4985 case HDSPM_AUTOSYNC_FROM_TCO: 4986 autosync_ref = "TCO"; 4987 break; 4988 case HDSPM_AUTOSYNC_FROM_WORD: 4989 autosync_ref = "Word Clock"; 4990 break; 4991 case HDSPM_AUTOSYNC_FROM_MADI: 4992 autosync_ref = "MADI Sync"; 4993 break; 4994 case HDSPM_AUTOSYNC_FROM_NONE: 4995 autosync_ref = "Input not valid"; 4996 break; 4997 default: 4998 autosync_ref = "---"; 4999 break; 5000 } 5001 snd_iprintf(buffer, 5002 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", 5003 autosync_ref, hdspm_external_sample_rate(hdspm), 5004 (status & HDSPM_madiFreqMask) >> 22, 5005 (status2 & HDSPM_wcFreqMask) >> 5); 5006 5007 snd_iprintf(buffer, "Input: %s, Mode=%s\n", 5008 (status & HDSPM_AB_int) ? "Coax" : "Optical", 5009 (status & HDSPM_RX_64ch) ? "64 channels" : 5010 "56 channels"); 5011 5012 /* call readout function for TCO specific status */ 5013 snd_hdspm_proc_read_tco(entry, buffer); 5014 5015 snd_iprintf(buffer, "\n"); 5016 } 5017 5018 static void 5019 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, 5020 struct snd_info_buffer *buffer) 5021 { 5022 struct hdspm *hdspm = entry->private_data; 5023 unsigned int status; 5024 unsigned int status2; 5025 unsigned int timecode; 5026 unsigned int wcLock, wcSync; 5027 int pref_syncref; 5028 char *autosync_ref; 5029 int x; 5030 5031 status = hdspm_read(hdspm, HDSPM_statusRegister); 5032 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 5033 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 5034 5035 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", 5036 hdspm->card_name, hdspm->card->number + 1, 5037 hdspm->firmware_rev); 5038 5039 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 5040 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 5041 5042 snd_iprintf(buffer, "--- System ---\n"); 5043 5044 snd_iprintf(buffer, 5045 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 5046 status & HDSPM_audioIRQPending, 5047 (status & HDSPM_midi0IRQPending) ? 1 : 0, 5048 (status & HDSPM_midi1IRQPending) ? 1 : 0, 5049 hdspm->irq_count); 5050 snd_iprintf(buffer, 5051 "HW pointer: id = %d, rawptr = %d (%d->%d) " 5052 "estimated= %ld (bytes)\n", 5053 ((status & HDSPM_BufferID) ? 1 : 0), 5054 (status & HDSPM_BufferPositionMask), 5055 (status & HDSPM_BufferPositionMask) % 5056 (2 * (int)hdspm->period_bytes), 5057 ((status & HDSPM_BufferPositionMask) - 64) % 5058 (2 * (int)hdspm->period_bytes), 5059 (long) hdspm_hw_pointer(hdspm) * 4); 5060 5061 snd_iprintf(buffer, 5062 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 5063 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 5064 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 5065 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 5066 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 5067 snd_iprintf(buffer, 5068 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 5069 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 5070 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 5071 snd_iprintf(buffer, 5072 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 5073 "status2=0x%x\n", 5074 hdspm->control_register, hdspm->control2_register, 5075 status, status2); 5076 5077 snd_iprintf(buffer, "--- Settings ---\n"); 5078 5079 x = hdspm_get_latency(hdspm); 5080 5081 snd_iprintf(buffer, 5082 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 5083 x, (unsigned long) hdspm->period_bytes); 5084 5085 snd_iprintf(buffer, "Line out: %s\n", 5086 (hdspm-> 5087 control_register & HDSPM_LineOut) ? "on " : "off"); 5088 5089 snd_iprintf(buffer, 5090 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", 5091 str_on_off(hdspm->control_register & HDSPM_clr_tms), 5092 str_on_off(hdspm->control_register & HDSPM_Emphasis), 5093 str_on_off(hdspm->control_register & HDSPM_Dolby)); 5094 5095 5096 pref_syncref = hdspm_pref_sync_ref(hdspm); 5097 if (pref_syncref == 0) 5098 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); 5099 else 5100 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", 5101 pref_syncref); 5102 5103 snd_iprintf(buffer, "System Clock Frequency: %d\n", 5104 hdspm->system_sample_rate); 5105 5106 snd_iprintf(buffer, "Double speed: %s\n", 5107 hdspm->control_register & HDSPM_DS_DoubleWire? 5108 "Double wire" : "Single wire"); 5109 snd_iprintf(buffer, "Quad speed: %s\n", 5110 hdspm->control_register & HDSPM_QS_DoubleWire? 5111 "Double wire" : 5112 hdspm->control_register & HDSPM_QS_QuadWire? 5113 "Quad wire" : "Single wire"); 5114 5115 snd_iprintf(buffer, "--- Status:\n"); 5116 5117 wcLock = status & HDSPM_AES32_wcLock; 5118 wcSync = wcLock && (status & HDSPM_AES32_wcSync); 5119 5120 snd_iprintf(buffer, "Word: %s Frequency: %d\n", 5121 (wcLock) ? (wcSync ? "Sync " : "Lock ") : "No Lock", 5122 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); 5123 5124 for (x = 0; x < 8; x++) { 5125 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", 5126 x+1, 5127 (status2 & (HDSPM_LockAES >> x)) ? 5128 "Sync " : "No Lock", 5129 HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); 5130 } 5131 5132 switch (hdspm_autosync_ref(hdspm)) { 5133 case HDSPM_AES32_AUTOSYNC_FROM_NONE: 5134 autosync_ref = "None"; break; 5135 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 5136 autosync_ref = "Word Clock"; break; 5137 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 5138 autosync_ref = "AES1"; break; 5139 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 5140 autosync_ref = "AES2"; break; 5141 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 5142 autosync_ref = "AES3"; break; 5143 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 5144 autosync_ref = "AES4"; break; 5145 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 5146 autosync_ref = "AES5"; break; 5147 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 5148 autosync_ref = "AES6"; break; 5149 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 5150 autosync_ref = "AES7"; break; 5151 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 5152 autosync_ref = "AES8"; break; 5153 case HDSPM_AES32_AUTOSYNC_FROM_TCO: 5154 autosync_ref = "TCO"; break; 5155 case HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN: 5156 autosync_ref = "Sync In"; break; 5157 default: 5158 autosync_ref = "---"; break; 5159 } 5160 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); 5161 5162 /* call readout function for TCO specific status */ 5163 snd_hdspm_proc_read_tco(entry, buffer); 5164 5165 snd_iprintf(buffer, "\n"); 5166 } 5167 5168 static void 5169 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry, 5170 struct snd_info_buffer *buffer) 5171 { 5172 struct hdspm *hdspm = entry->private_data; 5173 unsigned int status1, status2, status3, i; 5174 unsigned int lock, sync; 5175 5176 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */ 5177 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */ 5178 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */ 5179 5180 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1); 5181 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2); 5182 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3); 5183 5184 5185 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n"); 5186 5187 snd_iprintf(buffer, "Clock mode : %s\n", 5188 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave"); 5189 snd_iprintf(buffer, "System frequency: %d Hz\n", 5190 hdspm_get_system_sample_rate(hdspm)); 5191 5192 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n"); 5193 5194 lock = 0x1; 5195 sync = 0x100; 5196 5197 for (i = 0; i < 8; i++) { 5198 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n", 5199 i, 5200 (status1 & lock) ? 1 : 0, 5201 (status1 & sync) ? 1 : 0, 5202 texts_freq[(status2 >> (i * 4)) & 0xF]); 5203 5204 lock = lock<<1; 5205 sync = sync<<1; 5206 } 5207 5208 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n", 5209 (status1 & 0x1000000) ? 1 : 0, 5210 (status1 & 0x2000000) ? 1 : 0, 5211 texts_freq[(status1 >> 16) & 0xF]); 5212 5213 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n", 5214 (status1 & 0x4000000) ? 1 : 0, 5215 (status1 & 0x8000000) ? 1 : 0, 5216 texts_freq[(status1 >> 20) & 0xF]); 5217 5218 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n", 5219 (status3 & 0x400) ? 1 : 0, 5220 (status3 & 0x800) ? 1 : 0, 5221 texts_freq[(status2 >> 12) & 0xF]); 5222 5223 } 5224 5225 #ifdef CONFIG_SND_DEBUG 5226 static void 5227 snd_hdspm_proc_read_debug(struct snd_info_entry *entry, 5228 struct snd_info_buffer *buffer) 5229 { 5230 struct hdspm *hdspm = entry->private_data; 5231 5232 int j,i; 5233 5234 for (i = 0; i < 256 /* 1024*64 */; i += j) { 5235 snd_iprintf(buffer, "0x%08X: ", i); 5236 for (j = 0; j < 16; j += 4) 5237 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); 5238 snd_iprintf(buffer, "\n"); 5239 } 5240 } 5241 #endif 5242 5243 5244 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry, 5245 struct snd_info_buffer *buffer) 5246 { 5247 struct hdspm *hdspm = entry->private_data; 5248 int i; 5249 5250 snd_iprintf(buffer, "# generated by hdspm\n"); 5251 5252 for (i = 0; i < hdspm->max_channels_in; i++) { 5253 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]); 5254 } 5255 } 5256 5257 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry, 5258 struct snd_info_buffer *buffer) 5259 { 5260 struct hdspm *hdspm = entry->private_data; 5261 int i; 5262 5263 snd_iprintf(buffer, "# generated by hdspm\n"); 5264 5265 for (i = 0; i < hdspm->max_channels_out; i++) { 5266 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]); 5267 } 5268 } 5269 5270 5271 static void snd_hdspm_proc_init(struct hdspm *hdspm) 5272 { 5273 void (*read)(struct snd_info_entry *, struct snd_info_buffer *) = NULL; 5274 5275 switch (hdspm->io_type) { 5276 case AES32: 5277 read = snd_hdspm_proc_read_aes32; 5278 break; 5279 case MADI: 5280 read = snd_hdspm_proc_read_madi; 5281 break; 5282 case MADIface: 5283 /* read = snd_hdspm_proc_read_madiface; */ 5284 break; 5285 case RayDAT: 5286 read = snd_hdspm_proc_read_raydat; 5287 break; 5288 case AIO: 5289 break; 5290 } 5291 5292 snd_card_ro_proc_new(hdspm->card, "hdspm", hdspm, read); 5293 snd_card_ro_proc_new(hdspm->card, "ports.in", hdspm, 5294 snd_hdspm_proc_ports_in); 5295 snd_card_ro_proc_new(hdspm->card, "ports.out", hdspm, 5296 snd_hdspm_proc_ports_out); 5297 5298 #ifdef CONFIG_SND_DEBUG 5299 /* debug file to read all hdspm registers */ 5300 snd_card_ro_proc_new(hdspm->card, "debug", hdspm, 5301 snd_hdspm_proc_read_debug); 5302 #endif 5303 } 5304 5305 /*------------------------------------------------------------ 5306 hdspm intitialize 5307 ------------------------------------------------------------*/ 5308 5309 static int snd_hdspm_set_defaults(struct hdspm * hdspm) 5310 { 5311 /* ASSUMPTION: hdspm->lock is either held, or there is no need to 5312 hold it (e.g. during module initialization). 5313 */ 5314 5315 /* set defaults: */ 5316 5317 hdspm->settings_register = 0; 5318 5319 switch (hdspm->io_type) { 5320 case MADI: 5321 case MADIface: 5322 hdspm->control_register = 5323 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5324 break; 5325 5326 case RayDAT: 5327 case AIO: 5328 hdspm->settings_register = 0x1 + 0x1000; 5329 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0, 5330 * line_out */ 5331 hdspm->control_register = 5332 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5333 break; 5334 5335 case AES32: 5336 hdspm->control_register = 5337 HDSPM_ClockModeMaster | /* Master Clock Mode on */ 5338 hdspm_encode_latency(7) | /* latency max=8192samples */ 5339 HDSPM_SyncRef0 | /* AES1 is syncclock */ 5340 HDSPM_LineOut | /* Analog output in */ 5341 HDSPM_Professional; /* Professional mode */ 5342 break; 5343 } 5344 5345 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5346 5347 if (AES32 == hdspm->io_type) { 5348 /* No control2 register for AES32 */ 5349 #ifdef SNDRV_BIG_ENDIAN 5350 hdspm->control2_register = HDSPM_BIGENDIAN_MODE; 5351 #else 5352 hdspm->control2_register = 0; 5353 #endif 5354 5355 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); 5356 } 5357 hdspm_compute_period_size(hdspm); 5358 5359 /* silence everything */ 5360 5361 all_in_all_mixer(hdspm, 0 * UNITY_GAIN); 5362 5363 if (hdspm_is_raydat_or_aio(hdspm)) 5364 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 5365 5366 /* set a default rate so that the channel map is set up. */ 5367 hdspm_set_rate(hdspm, 48000, 1); 5368 5369 return 0; 5370 } 5371 5372 5373 /*------------------------------------------------------------ 5374 interrupt 5375 ------------------------------------------------------------*/ 5376 5377 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) 5378 { 5379 struct hdspm *hdspm = (struct hdspm *) dev_id; 5380 unsigned int status; 5381 int i, audio, midi, schedule = 0; 5382 /* cycles_t now; */ 5383 5384 status = hdspm_read(hdspm, HDSPM_statusRegister); 5385 5386 audio = status & HDSPM_audioIRQPending; 5387 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending | 5388 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending); 5389 5390 /* now = get_cycles(); */ 5391 /* 5392 * LAT_2..LAT_0 period counter (win) counter (mac) 5393 * 6 4096 ~256053425 ~514672358 5394 * 5 2048 ~128024983 ~257373821 5395 * 4 1024 ~64023706 ~128718089 5396 * 3 512 ~32005945 ~64385999 5397 * 2 256 ~16003039 ~32260176 5398 * 1 128 ~7998738 ~16194507 5399 * 0 64 ~3998231 ~8191558 5400 */ 5401 /* 5402 dev_info(hdspm->card->dev, "snd_hdspm_interrupt %llu @ %llx\n", 5403 now-hdspm->last_interrupt, status & 0xFFC0); 5404 hdspm->last_interrupt = now; 5405 */ 5406 5407 if (!audio && !midi) 5408 return IRQ_NONE; 5409 5410 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); 5411 hdspm->irq_count++; 5412 5413 5414 if (audio) { 5415 if (hdspm->capture_substream) 5416 snd_pcm_period_elapsed(hdspm->capture_substream); 5417 5418 if (hdspm->playback_substream) 5419 snd_pcm_period_elapsed(hdspm->playback_substream); 5420 } 5421 5422 if (midi) { 5423 i = 0; 5424 while (i < hdspm->midiPorts) { 5425 if ((hdspm_read(hdspm, 5426 hdspm->midi[i].statusIn) & 0xff) && 5427 (status & hdspm->midi[i].irq)) { 5428 /* we disable interrupts for this input until 5429 * processing is done 5430 */ 5431 hdspm->control_register &= ~hdspm->midi[i].ie; 5432 hdspm_write(hdspm, HDSPM_controlRegister, 5433 hdspm->control_register); 5434 hdspm->midi[i].pending = 1; 5435 schedule = 1; 5436 } 5437 5438 i++; 5439 } 5440 5441 if (schedule) 5442 queue_work(system_highpri_wq, &hdspm->midi_work); 5443 } 5444 5445 return IRQ_HANDLED; 5446 } 5447 5448 /*------------------------------------------------------------ 5449 pcm interface 5450 ------------------------------------------------------------*/ 5451 5452 5453 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream 5454 *substream) 5455 { 5456 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5457 return hdspm_hw_pointer(hdspm); 5458 } 5459 5460 5461 static int snd_hdspm_reset(struct snd_pcm_substream *substream) 5462 { 5463 struct snd_pcm_runtime *runtime = substream->runtime; 5464 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5465 struct snd_pcm_substream *other; 5466 5467 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5468 other = hdspm->capture_substream; 5469 else 5470 other = hdspm->playback_substream; 5471 5472 if (hdspm->running) 5473 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); 5474 else 5475 runtime->status->hw_ptr = 0; 5476 if (other) { 5477 struct snd_pcm_substream *s; 5478 struct snd_pcm_runtime *oruntime = other->runtime; 5479 snd_pcm_group_for_each_entry(s, substream) { 5480 if (s == other) { 5481 oruntime->status->hw_ptr = 5482 runtime->status->hw_ptr; 5483 break; 5484 } 5485 } 5486 } 5487 return 0; 5488 } 5489 5490 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, 5491 struct snd_pcm_hw_params *params) 5492 { 5493 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5494 int err; 5495 int i; 5496 pid_t this_pid; 5497 pid_t other_pid; 5498 5499 spin_lock_irq(&hdspm->lock); 5500 5501 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5502 this_pid = hdspm->playback_pid; 5503 other_pid = hdspm->capture_pid; 5504 } else { 5505 this_pid = hdspm->capture_pid; 5506 other_pid = hdspm->playback_pid; 5507 } 5508 5509 if (other_pid > 0 && this_pid != other_pid) { 5510 5511 /* The other stream is open, and not by the same 5512 task as this one. Make sure that the parameters 5513 that matter are the same. 5514 */ 5515 5516 if (params_rate(params) != hdspm->system_sample_rate) { 5517 spin_unlock_irq(&hdspm->lock); 5518 _snd_pcm_hw_param_setempty(params, 5519 SNDRV_PCM_HW_PARAM_RATE); 5520 return -EBUSY; 5521 } 5522 5523 if (params_period_size(params) != hdspm->period_bytes / 4) { 5524 spin_unlock_irq(&hdspm->lock); 5525 _snd_pcm_hw_param_setempty(params, 5526 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5527 return -EBUSY; 5528 } 5529 5530 } 5531 /* We're fine. */ 5532 spin_unlock_irq(&hdspm->lock); 5533 5534 /* how to make sure that the rate matches an externally-set one ? */ 5535 5536 spin_lock_irq(&hdspm->lock); 5537 err = hdspm_set_rate(hdspm, params_rate(params), 0); 5538 if (err < 0) { 5539 dev_info(hdspm->card->dev, "err on hdspm_set_rate: %d\n", err); 5540 spin_unlock_irq(&hdspm->lock); 5541 _snd_pcm_hw_param_setempty(params, 5542 SNDRV_PCM_HW_PARAM_RATE); 5543 return err; 5544 } 5545 spin_unlock_irq(&hdspm->lock); 5546 5547 err = hdspm_set_interrupt_interval(hdspm, 5548 params_period_size(params)); 5549 if (err < 0) { 5550 dev_info(hdspm->card->dev, 5551 "err on hdspm_set_interrupt_interval: %d\n", err); 5552 _snd_pcm_hw_param_setempty(params, 5553 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5554 return err; 5555 } 5556 5557 /* Memory allocation, takashi's method, dont know if we should 5558 * spinlock 5559 */ 5560 /* malloc all buffer even if not enabled to get sure */ 5561 /* Update for MADI rev 204: we need to allocate for all channels, 5562 * otherwise it doesn't work at 96kHz */ 5563 5564 err = 5565 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); 5566 if (err < 0) { 5567 dev_info(hdspm->card->dev, 5568 "err on snd_pcm_lib_malloc_pages: %d\n", err); 5569 return err; 5570 } 5571 5572 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5573 5574 for (i = 0; i < params_channels(params); ++i) { 5575 int c = hdspm->channel_map_out[i]; 5576 5577 if (c < 0) 5578 continue; /* just make sure */ 5579 hdspm_set_channel_dma_addr(hdspm, substream, 5580 HDSPM_pageAddressBufferOut, 5581 c); 5582 snd_hdspm_enable_out(hdspm, c, 1); 5583 } 5584 5585 hdspm->playback_buffer = 5586 (unsigned char *) substream->runtime->dma_area; 5587 dev_dbg(hdspm->card->dev, 5588 "Allocated sample buffer for playback at %p\n", 5589 hdspm->playback_buffer); 5590 } else { 5591 for (i = 0; i < params_channels(params); ++i) { 5592 int c = hdspm->channel_map_in[i]; 5593 5594 if (c < 0) 5595 continue; 5596 hdspm_set_channel_dma_addr(hdspm, substream, 5597 HDSPM_pageAddressBufferIn, 5598 c); 5599 snd_hdspm_enable_in(hdspm, c, 1); 5600 } 5601 5602 hdspm->capture_buffer = 5603 (unsigned char *) substream->runtime->dma_area; 5604 dev_dbg(hdspm->card->dev, 5605 "Allocated sample buffer for capture at %p\n", 5606 hdspm->capture_buffer); 5607 } 5608 5609 /* 5610 dev_dbg(hdspm->card->dev, 5611 "Allocated sample buffer for %s at 0x%08X\n", 5612 snd_pcm_direction_name(substream->stream), 5613 snd_pcm_sgbuf_get_addr(substream, 0)); 5614 */ 5615 /* 5616 dev_dbg(hdspm->card->dev, 5617 "set_hwparams: %s %d Hz, %d channels, bs = %d\n", 5618 snd_pcm_direction_name(substream->stream), 5619 params_rate(params), params_channels(params), 5620 params_buffer_size(params)); 5621 */ 5622 5623 5624 /* For AES cards, the float format bit is the same as the 5625 * preferred sync reference. Since we don't want to break 5626 * sync settings, we have to skip the remaining part of this 5627 * function. 5628 */ 5629 if (hdspm->io_type == AES32) { 5630 return 0; 5631 } 5632 5633 5634 /* Switch to native float format if requested */ 5635 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { 5636 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) 5637 dev_info(hdspm->card->dev, 5638 "Switching to native 32bit LE float format.\n"); 5639 5640 hdspm->control_register |= HDSPe_FLOAT_FORMAT; 5641 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { 5642 if (hdspm->control_register & HDSPe_FLOAT_FORMAT) 5643 dev_info(hdspm->card->dev, 5644 "Switching to native 32bit LE integer format.\n"); 5645 5646 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; 5647 } 5648 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5649 5650 return 0; 5651 } 5652 5653 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) 5654 { 5655 int i; 5656 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5657 5658 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5659 /* Just disable all channels. The saving when disabling a */ 5660 /* smaller set is not worth the trouble. */ 5661 for (i = 0; i < HDSPM_MAX_CHANNELS; ++i) 5662 snd_hdspm_enable_out(hdspm, i, 0); 5663 5664 hdspm->playback_buffer = NULL; 5665 } else { 5666 for (i = 0; i < HDSPM_MAX_CHANNELS; ++i) 5667 snd_hdspm_enable_in(hdspm, i, 0); 5668 5669 hdspm->capture_buffer = NULL; 5670 } 5671 5672 snd_pcm_lib_free_pages(substream); 5673 5674 return 0; 5675 } 5676 5677 5678 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, 5679 struct snd_pcm_channel_info *info) 5680 { 5681 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5682 unsigned int channel = info->channel; 5683 5684 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5685 if (snd_BUG_ON(channel >= hdspm->max_channels_out)) { 5686 dev_info(hdspm->card->dev, 5687 "snd_hdspm_channel_info: output channel out of range (%d)\n", 5688 channel); 5689 return -EINVAL; 5690 } 5691 5692 channel = array_index_nospec(channel, hdspm->max_channels_out); 5693 if (hdspm->channel_map_out[channel] < 0) { 5694 dev_info(hdspm->card->dev, 5695 "snd_hdspm_channel_info: output channel %d mapped out\n", 5696 channel); 5697 return -EINVAL; 5698 } 5699 5700 info->offset = hdspm->channel_map_out[channel] * 5701 HDSPM_CHANNEL_BUFFER_BYTES; 5702 } else { 5703 if (snd_BUG_ON(channel >= hdspm->max_channels_in)) { 5704 dev_info(hdspm->card->dev, 5705 "snd_hdspm_channel_info: input channel out of range (%d)\n", 5706 channel); 5707 return -EINVAL; 5708 } 5709 5710 channel = array_index_nospec(channel, hdspm->max_channels_in); 5711 if (hdspm->channel_map_in[channel] < 0) { 5712 dev_info(hdspm->card->dev, 5713 "snd_hdspm_channel_info: input channel %d mapped out\n", 5714 channel); 5715 return -EINVAL; 5716 } 5717 5718 info->offset = hdspm->channel_map_in[channel] * 5719 HDSPM_CHANNEL_BUFFER_BYTES; 5720 } 5721 5722 info->first = 0; 5723 info->step = 32; 5724 return 0; 5725 } 5726 5727 5728 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, 5729 unsigned int cmd, void *arg) 5730 { 5731 switch (cmd) { 5732 case SNDRV_PCM_IOCTL1_RESET: 5733 return snd_hdspm_reset(substream); 5734 5735 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 5736 { 5737 struct snd_pcm_channel_info *info = arg; 5738 return snd_hdspm_channel_info(substream, info); 5739 } 5740 default: 5741 break; 5742 } 5743 5744 return snd_pcm_lib_ioctl(substream, cmd, arg); 5745 } 5746 5747 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) 5748 { 5749 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5750 struct snd_pcm_substream *other; 5751 int running; 5752 5753 spin_lock(&hdspm->lock); 5754 running = hdspm->running; 5755 switch (cmd) { 5756 case SNDRV_PCM_TRIGGER_START: 5757 running |= 1 << substream->stream; 5758 break; 5759 case SNDRV_PCM_TRIGGER_STOP: 5760 running &= ~(1 << substream->stream); 5761 break; 5762 default: 5763 snd_BUG(); 5764 spin_unlock(&hdspm->lock); 5765 return -EINVAL; 5766 } 5767 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5768 other = hdspm->capture_substream; 5769 else 5770 other = hdspm->playback_substream; 5771 5772 if (other) { 5773 struct snd_pcm_substream *s; 5774 snd_pcm_group_for_each_entry(s, substream) { 5775 if (s == other) { 5776 snd_pcm_trigger_done(s, substream); 5777 if (cmd == SNDRV_PCM_TRIGGER_START) 5778 running |= 1 << s->stream; 5779 else 5780 running &= ~(1 << s->stream); 5781 goto _ok; 5782 } 5783 } 5784 if (cmd == SNDRV_PCM_TRIGGER_START) { 5785 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) 5786 && substream->stream == 5787 SNDRV_PCM_STREAM_CAPTURE) 5788 hdspm_silence_playback(hdspm); 5789 } else { 5790 if (running && 5791 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5792 hdspm_silence_playback(hdspm); 5793 } 5794 } else { 5795 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 5796 hdspm_silence_playback(hdspm); 5797 } 5798 _ok: 5799 snd_pcm_trigger_done(substream, substream); 5800 if (!hdspm->running && running) 5801 hdspm_start_audio(hdspm); 5802 else if (hdspm->running && !running) 5803 hdspm_stop_audio(hdspm); 5804 hdspm->running = running; 5805 spin_unlock(&hdspm->lock); 5806 5807 return 0; 5808 } 5809 5810 static int snd_hdspm_prepare(struct snd_pcm_substream *substream) 5811 { 5812 return 0; 5813 } 5814 5815 static const struct snd_pcm_hardware snd_hdspm_playback_subinfo = { 5816 .info = (SNDRV_PCM_INFO_MMAP | 5817 SNDRV_PCM_INFO_MMAP_VALID | 5818 SNDRV_PCM_INFO_NONINTERLEAVED | 5819 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), 5820 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5821 .rates = (SNDRV_PCM_RATE_32000 | 5822 SNDRV_PCM_RATE_44100 | 5823 SNDRV_PCM_RATE_48000 | 5824 SNDRV_PCM_RATE_64000 | 5825 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5826 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), 5827 .rate_min = 32000, 5828 .rate_max = 192000, 5829 .channels_min = 1, 5830 .channels_max = HDSPM_MAX_CHANNELS, 5831 .buffer_bytes_max = 5832 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5833 .period_bytes_min = (32 * 4), 5834 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5835 .periods_min = 2, 5836 .periods_max = 512, 5837 .fifo_size = 0 5838 }; 5839 5840 static const struct snd_pcm_hardware snd_hdspm_capture_subinfo = { 5841 .info = (SNDRV_PCM_INFO_MMAP | 5842 SNDRV_PCM_INFO_MMAP_VALID | 5843 SNDRV_PCM_INFO_NONINTERLEAVED | 5844 SNDRV_PCM_INFO_SYNC_START), 5845 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5846 .rates = (SNDRV_PCM_RATE_32000 | 5847 SNDRV_PCM_RATE_44100 | 5848 SNDRV_PCM_RATE_48000 | 5849 SNDRV_PCM_RATE_64000 | 5850 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5851 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), 5852 .rate_min = 32000, 5853 .rate_max = 192000, 5854 .channels_min = 1, 5855 .channels_max = HDSPM_MAX_CHANNELS, 5856 .buffer_bytes_max = 5857 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5858 .period_bytes_min = (32 * 4), 5859 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5860 .periods_min = 2, 5861 .periods_max = 512, 5862 .fifo_size = 0 5863 }; 5864 5865 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 5866 struct snd_pcm_hw_rule *rule) 5867 { 5868 struct hdspm *hdspm = rule->private; 5869 struct snd_interval *c = 5870 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5871 struct snd_interval *r = 5872 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5873 5874 if (r->min > 96000 && r->max <= 192000) { 5875 struct snd_interval t = { 5876 .min = hdspm->qs_in_channels, 5877 .max = hdspm->qs_in_channels, 5878 .integer = 1, 5879 }; 5880 return snd_interval_refine(c, &t); 5881 } else if (r->min > 48000 && r->max <= 96000) { 5882 struct snd_interval t = { 5883 .min = hdspm->ds_in_channels, 5884 .max = hdspm->ds_in_channels, 5885 .integer = 1, 5886 }; 5887 return snd_interval_refine(c, &t); 5888 } else if (r->max < 64000) { 5889 struct snd_interval t = { 5890 .min = hdspm->ss_in_channels, 5891 .max = hdspm->ss_in_channels, 5892 .integer = 1, 5893 }; 5894 return snd_interval_refine(c, &t); 5895 } 5896 5897 return 0; 5898 } 5899 5900 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 5901 struct snd_pcm_hw_rule * rule) 5902 { 5903 struct hdspm *hdspm = rule->private; 5904 struct snd_interval *c = 5905 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5906 struct snd_interval *r = 5907 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5908 5909 if (r->min > 96000 && r->max <= 192000) { 5910 struct snd_interval t = { 5911 .min = hdspm->qs_out_channels, 5912 .max = hdspm->qs_out_channels, 5913 .integer = 1, 5914 }; 5915 return snd_interval_refine(c, &t); 5916 } else if (r->min > 48000 && r->max <= 96000) { 5917 struct snd_interval t = { 5918 .min = hdspm->ds_out_channels, 5919 .max = hdspm->ds_out_channels, 5920 .integer = 1, 5921 }; 5922 return snd_interval_refine(c, &t); 5923 } else if (r->max < 64000) { 5924 struct snd_interval t = { 5925 .min = hdspm->ss_out_channels, 5926 .max = hdspm->ss_out_channels, 5927 .integer = 1, 5928 }; 5929 return snd_interval_refine(c, &t); 5930 } else { 5931 } 5932 return 0; 5933 } 5934 5935 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 5936 struct snd_pcm_hw_rule * rule) 5937 { 5938 struct hdspm *hdspm = rule->private; 5939 struct snd_interval *c = 5940 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5941 struct snd_interval *r = 5942 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5943 5944 if (c->min >= hdspm->ss_in_channels) { 5945 struct snd_interval t = { 5946 .min = 32000, 5947 .max = 48000, 5948 .integer = 1, 5949 }; 5950 return snd_interval_refine(r, &t); 5951 } else if (c->max <= hdspm->qs_in_channels) { 5952 struct snd_interval t = { 5953 .min = 128000, 5954 .max = 192000, 5955 .integer = 1, 5956 }; 5957 return snd_interval_refine(r, &t); 5958 } else if (c->max <= hdspm->ds_in_channels) { 5959 struct snd_interval t = { 5960 .min = 64000, 5961 .max = 96000, 5962 .integer = 1, 5963 }; 5964 return snd_interval_refine(r, &t); 5965 } 5966 5967 return 0; 5968 } 5969 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 5970 struct snd_pcm_hw_rule *rule) 5971 { 5972 struct hdspm *hdspm = rule->private; 5973 struct snd_interval *c = 5974 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5975 struct snd_interval *r = 5976 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5977 5978 if (c->min >= hdspm->ss_out_channels) { 5979 struct snd_interval t = { 5980 .min = 32000, 5981 .max = 48000, 5982 .integer = 1, 5983 }; 5984 return snd_interval_refine(r, &t); 5985 } else if (c->max <= hdspm->qs_out_channels) { 5986 struct snd_interval t = { 5987 .min = 128000, 5988 .max = 192000, 5989 .integer = 1, 5990 }; 5991 return snd_interval_refine(r, &t); 5992 } else if (c->max <= hdspm->ds_out_channels) { 5993 struct snd_interval t = { 5994 .min = 64000, 5995 .max = 96000, 5996 .integer = 1, 5997 }; 5998 return snd_interval_refine(r, &t); 5999 } 6000 6001 return 0; 6002 } 6003 6004 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params, 6005 struct snd_pcm_hw_rule *rule) 6006 { 6007 unsigned int list[3]; 6008 struct hdspm *hdspm = rule->private; 6009 struct snd_interval *c = hw_param_interval(params, 6010 SNDRV_PCM_HW_PARAM_CHANNELS); 6011 6012 list[0] = hdspm->qs_in_channels; 6013 list[1] = hdspm->ds_in_channels; 6014 list[2] = hdspm->ss_in_channels; 6015 return snd_interval_list(c, 3, list, 0); 6016 } 6017 6018 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params, 6019 struct snd_pcm_hw_rule *rule) 6020 { 6021 unsigned int list[3]; 6022 struct hdspm *hdspm = rule->private; 6023 struct snd_interval *c = hw_param_interval(params, 6024 SNDRV_PCM_HW_PARAM_CHANNELS); 6025 6026 list[0] = hdspm->qs_out_channels; 6027 list[1] = hdspm->ds_out_channels; 6028 list[2] = hdspm->ss_out_channels; 6029 return snd_interval_list(c, 3, list, 0); 6030 } 6031 6032 static int snd_hdspm_open(struct snd_pcm_substream *substream) 6033 { 6034 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6035 struct snd_pcm_runtime *runtime = substream->runtime; 6036 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 6037 6038 spin_lock_irq(&hdspm->lock); 6039 snd_pcm_set_sync(substream); 6040 runtime->hw = (playback) ? snd_hdspm_playback_subinfo : 6041 snd_hdspm_capture_subinfo; 6042 6043 if (playback) { 6044 if (!hdspm->capture_substream) 6045 hdspm_stop_audio(hdspm); 6046 6047 hdspm->playback_pid = current->pid; 6048 hdspm->playback_substream = substream; 6049 } else { 6050 if (!hdspm->playback_substream) 6051 hdspm_stop_audio(hdspm); 6052 6053 hdspm->capture_pid = current->pid; 6054 hdspm->capture_substream = substream; 6055 } 6056 6057 spin_unlock_irq(&hdspm->lock); 6058 6059 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 6060 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 6061 6062 switch (hdspm->io_type) { 6063 case AIO: 6064 case RayDAT: 6065 snd_pcm_hw_constraint_minmax(runtime, 6066 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6067 32, 4096); 6068 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */ 6069 snd_pcm_hw_constraint_single(runtime, 6070 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 6071 16384); 6072 break; 6073 6074 default: 6075 snd_pcm_hw_constraint_minmax(runtime, 6076 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6077 64, 8192); 6078 snd_pcm_hw_constraint_single(runtime, 6079 SNDRV_PCM_HW_PARAM_PERIODS, 2); 6080 break; 6081 } 6082 6083 if (AES32 == hdspm->io_type) { 6084 runtime->hw.rates |= SNDRV_PCM_RATE_128000; 6085 } else { 6086 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 6087 (playback ? 6088 snd_hdspm_hw_rule_rate_out_channels : 6089 snd_hdspm_hw_rule_rate_in_channels), hdspm, 6090 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6091 } 6092 6093 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6094 (playback ? snd_hdspm_hw_rule_out_channels : 6095 snd_hdspm_hw_rule_in_channels), hdspm, 6096 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6097 6098 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6099 (playback ? snd_hdspm_hw_rule_out_channels_rate : 6100 snd_hdspm_hw_rule_in_channels_rate), hdspm, 6101 SNDRV_PCM_HW_PARAM_RATE, -1); 6102 6103 return 0; 6104 } 6105 6106 static int snd_hdspm_release(struct snd_pcm_substream *substream) 6107 { 6108 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6109 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 6110 6111 spin_lock_irq(&hdspm->lock); 6112 6113 if (playback) { 6114 hdspm->playback_pid = -1; 6115 hdspm->playback_substream = NULL; 6116 } else { 6117 hdspm->capture_pid = -1; 6118 hdspm->capture_substream = NULL; 6119 } 6120 6121 spin_unlock_irq(&hdspm->lock); 6122 6123 return 0; 6124 } 6125 6126 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) 6127 { 6128 /* we have nothing to initialize but the call is required */ 6129 return 0; 6130 } 6131 6132 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, 6133 unsigned int cmd, unsigned long arg) 6134 { 6135 void __user *argp = (void __user *)arg; 6136 struct hdspm *hdspm = hw->private_data; 6137 struct hdspm_mixer_ioctl mixer; 6138 struct hdspm_config info; 6139 struct hdspm_status status; 6140 struct hdspm_version hdspm_version; 6141 struct hdspm_peak_rms *levels; 6142 struct hdspm_ltc ltc; 6143 unsigned int statusregister; 6144 long unsigned int s; 6145 int i = 0; 6146 6147 switch (cmd) { 6148 6149 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: 6150 levels = &hdspm->peak_rms; 6151 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 6152 levels->input_peaks[i] = 6153 readl(hdspm->iobase + 6154 HDSPM_MADI_INPUT_PEAK + i*4); 6155 levels->playback_peaks[i] = 6156 readl(hdspm->iobase + 6157 HDSPM_MADI_PLAYBACK_PEAK + i*4); 6158 levels->output_peaks[i] = 6159 readl(hdspm->iobase + 6160 HDSPM_MADI_OUTPUT_PEAK + i*4); 6161 6162 levels->input_rms[i] = 6163 ((uint64_t) readl(hdspm->iobase + 6164 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) | 6165 (uint64_t) readl(hdspm->iobase + 6166 HDSPM_MADI_INPUT_RMS_L + i*4); 6167 levels->playback_rms[i] = 6168 ((uint64_t)readl(hdspm->iobase + 6169 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) | 6170 (uint64_t)readl(hdspm->iobase + 6171 HDSPM_MADI_PLAYBACK_RMS_L + i*4); 6172 levels->output_rms[i] = 6173 ((uint64_t)readl(hdspm->iobase + 6174 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) | 6175 (uint64_t)readl(hdspm->iobase + 6176 HDSPM_MADI_OUTPUT_RMS_L + i*4); 6177 } 6178 6179 if (hdspm->system_sample_rate > 96000) { 6180 levels->speed = qs; 6181 } else if (hdspm->system_sample_rate > 48000) { 6182 levels->speed = ds; 6183 } else { 6184 levels->speed = ss; 6185 } 6186 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 6187 6188 s = copy_to_user(argp, levels, sizeof(*levels)); 6189 if (0 != s) { 6190 /* dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu 6191 [Levels]\n", sizeof(struct hdspm_peak_rms), s); 6192 */ 6193 return -EFAULT; 6194 } 6195 break; 6196 6197 case SNDRV_HDSPM_IOCTL_GET_LTC: 6198 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 6199 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 6200 if (i & HDSPM_TCO1_LTC_Input_valid) { 6201 switch (i & (HDSPM_TCO1_LTC_Format_LSB | 6202 HDSPM_TCO1_LTC_Format_MSB)) { 6203 case 0: 6204 ltc.format = fps_24; 6205 break; 6206 case HDSPM_TCO1_LTC_Format_LSB: 6207 ltc.format = fps_25; 6208 break; 6209 case HDSPM_TCO1_LTC_Format_MSB: 6210 ltc.format = fps_2997; 6211 break; 6212 default: 6213 ltc.format = fps_30; 6214 break; 6215 } 6216 if (i & HDSPM_TCO1_set_drop_frame_flag) { 6217 ltc.frame = drop_frame; 6218 } else { 6219 ltc.frame = full_frame; 6220 } 6221 } else { 6222 ltc.format = format_invalid; 6223 ltc.frame = frame_invalid; 6224 } 6225 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) { 6226 ltc.input_format = ntsc; 6227 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) { 6228 ltc.input_format = pal; 6229 } else { 6230 ltc.input_format = no_video; 6231 } 6232 6233 s = copy_to_user(argp, <c, sizeof(ltc)); 6234 if (0 != s) { 6235 /* 6236 dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */ 6237 return -EFAULT; 6238 } 6239 6240 break; 6241 6242 case SNDRV_HDSPM_IOCTL_GET_CONFIG: 6243 6244 memset(&info, 0, sizeof(info)); 6245 spin_lock_irq(&hdspm->lock); 6246 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); 6247 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); 6248 6249 info.system_sample_rate = hdspm->system_sample_rate; 6250 info.autosync_sample_rate = 6251 hdspm_external_sample_rate(hdspm); 6252 info.system_clock_mode = hdspm_system_clock_mode(hdspm); 6253 info.clock_source = hdspm_clock_source(hdspm); 6254 info.autosync_ref = hdspm_autosync_ref(hdspm); 6255 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut); 6256 info.passthru = 0; 6257 spin_unlock_irq(&hdspm->lock); 6258 if (copy_to_user(argp, &info, sizeof(info))) 6259 return -EFAULT; 6260 break; 6261 6262 case SNDRV_HDSPM_IOCTL_GET_STATUS: 6263 memset(&status, 0, sizeof(status)); 6264 6265 status.card_type = hdspm->io_type; 6266 6267 status.autosync_source = hdspm_autosync_ref(hdspm); 6268 6269 status.card_clock = 110069313433624ULL; 6270 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 6271 6272 switch (hdspm->io_type) { 6273 case MADI: 6274 case MADIface: 6275 status.card_specific.madi.sync_wc = 6276 hdspm_wc_sync_check(hdspm); 6277 status.card_specific.madi.sync_madi = 6278 hdspm_madi_sync_check(hdspm); 6279 status.card_specific.madi.sync_tco = 6280 hdspm_tco_sync_check(hdspm); 6281 status.card_specific.madi.sync_in = 6282 hdspm_sync_in_sync_check(hdspm); 6283 6284 statusregister = 6285 hdspm_read(hdspm, HDSPM_statusRegister); 6286 status.card_specific.madi.madi_input = 6287 (statusregister & HDSPM_AB_int) ? 1 : 0; 6288 status.card_specific.madi.channel_format = 6289 (statusregister & HDSPM_RX_64ch) ? 1 : 0; 6290 /* TODO: Mac driver sets it when f_s>48kHz */ 6291 status.card_specific.madi.frame_format = 0; 6292 break; 6293 6294 default: 6295 break; 6296 } 6297 6298 if (copy_to_user(argp, &status, sizeof(status))) 6299 return -EFAULT; 6300 6301 6302 break; 6303 6304 case SNDRV_HDSPM_IOCTL_GET_VERSION: 6305 memset(&hdspm_version, 0, sizeof(hdspm_version)); 6306 6307 hdspm_version.card_type = hdspm->io_type; 6308 strscpy(hdspm_version.cardname, hdspm->card_name, 6309 sizeof(hdspm_version.cardname)); 6310 hdspm_version.serial = hdspm->serial; 6311 hdspm_version.firmware_rev = hdspm->firmware_rev; 6312 hdspm_version.addons = 0; 6313 if (hdspm->tco) 6314 hdspm_version.addons |= HDSPM_ADDON_TCO; 6315 6316 if (copy_to_user(argp, &hdspm_version, 6317 sizeof(hdspm_version))) 6318 return -EFAULT; 6319 break; 6320 6321 case SNDRV_HDSPM_IOCTL_GET_MIXER: 6322 if (copy_from_user(&mixer, argp, sizeof(mixer))) 6323 return -EFAULT; 6324 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, 6325 sizeof(*mixer.mixer))) 6326 return -EFAULT; 6327 break; 6328 6329 default: 6330 return -EINVAL; 6331 } 6332 return 0; 6333 } 6334 6335 static const struct snd_pcm_ops snd_hdspm_ops = { 6336 .open = snd_hdspm_open, 6337 .close = snd_hdspm_release, 6338 .ioctl = snd_hdspm_ioctl, 6339 .hw_params = snd_hdspm_hw_params, 6340 .hw_free = snd_hdspm_hw_free, 6341 .prepare = snd_hdspm_prepare, 6342 .trigger = snd_hdspm_trigger, 6343 .pointer = snd_hdspm_hw_pointer, 6344 }; 6345 6346 static int snd_hdspm_create_hwdep(struct snd_card *card, 6347 struct hdspm *hdspm) 6348 { 6349 struct snd_hwdep *hw; 6350 int err; 6351 6352 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); 6353 if (err < 0) 6354 return err; 6355 6356 hdspm->hwdep = hw; 6357 hw->private_data = hdspm; 6358 strcpy(hw->name, "HDSPM hwdep interface"); 6359 6360 hw->ops.open = snd_hdspm_hwdep_dummy_op; 6361 hw->ops.ioctl = snd_hdspm_hwdep_ioctl; 6362 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl; 6363 hw->ops.release = snd_hdspm_hwdep_dummy_op; 6364 6365 return 0; 6366 } 6367 6368 6369 /*------------------------------------------------------------ 6370 memory interface 6371 ------------------------------------------------------------*/ 6372 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm) 6373 { 6374 struct snd_pcm *pcm; 6375 size_t wanted; 6376 6377 pcm = hdspm->pcm; 6378 6379 wanted = HDSPM_DMA_AREA_BYTES; 6380 6381 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, 6382 &hdspm->pci->dev, 6383 wanted, wanted); 6384 dev_dbg(hdspm->card->dev, " Preallocated %zd Bytes\n", wanted); 6385 return 0; 6386 } 6387 6388 /* Inform the card what DMA addresses to use for the indicated channel. */ 6389 /* Each channel got 16 4K pages allocated for DMA transfers. */ 6390 static void hdspm_set_channel_dma_addr(struct hdspm *hdspm, 6391 struct snd_pcm_substream *substream, 6392 unsigned int reg, int channel) 6393 { 6394 int i; 6395 6396 for (i = channel * 16; i < channel * 16 + 16; i++) 6397 hdspm_write(hdspm, reg + 4 * i, 6398 snd_pcm_sgbuf_get_addr(substream, 4096 * i)); 6399 } 6400 6401 6402 /* ------------- ALSA Devices ---------------------------- */ 6403 static int snd_hdspm_create_pcm(struct snd_card *card, 6404 struct hdspm *hdspm) 6405 { 6406 struct snd_pcm *pcm; 6407 int err; 6408 6409 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); 6410 if (err < 0) 6411 return err; 6412 6413 hdspm->pcm = pcm; 6414 pcm->private_data = hdspm; 6415 strcpy(pcm->name, hdspm->card_name); 6416 6417 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 6418 &snd_hdspm_ops); 6419 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 6420 &snd_hdspm_ops); 6421 6422 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 6423 6424 err = snd_hdspm_preallocate_memory(hdspm); 6425 if (err < 0) 6426 return err; 6427 6428 return 0; 6429 } 6430 6431 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) 6432 { 6433 int i; 6434 6435 for (i = 0; i < hdspm->midiPorts; i++) 6436 snd_hdspm_flush_midi_input(hdspm, i); 6437 } 6438 6439 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 6440 struct hdspm *hdspm) 6441 { 6442 int err, i; 6443 6444 dev_dbg(card->dev, "Create card...\n"); 6445 err = snd_hdspm_create_pcm(card, hdspm); 6446 if (err < 0) 6447 return err; 6448 6449 i = 0; 6450 while (i < hdspm->midiPorts) { 6451 err = snd_hdspm_create_midi(card, hdspm, i); 6452 if (err < 0) { 6453 return err; 6454 } 6455 i++; 6456 } 6457 6458 err = snd_hdspm_create_controls(card, hdspm); 6459 if (err < 0) 6460 return err; 6461 6462 err = snd_hdspm_create_hwdep(card, hdspm); 6463 if (err < 0) 6464 return err; 6465 6466 dev_dbg(card->dev, "proc init...\n"); 6467 snd_hdspm_proc_init(hdspm); 6468 6469 hdspm->system_sample_rate = -1; 6470 hdspm->last_external_sample_rate = -1; 6471 hdspm->last_internal_sample_rate = -1; 6472 hdspm->playback_pid = -1; 6473 hdspm->capture_pid = -1; 6474 hdspm->capture_substream = NULL; 6475 hdspm->playback_substream = NULL; 6476 6477 dev_dbg(card->dev, "Set defaults...\n"); 6478 err = snd_hdspm_set_defaults(hdspm); 6479 if (err < 0) 6480 return err; 6481 6482 dev_dbg(card->dev, "Update mixer controls...\n"); 6483 hdspm_update_simple_mixer_controls(hdspm); 6484 6485 dev_dbg(card->dev, "Initializing complete?\n"); 6486 6487 err = snd_card_register(card); 6488 if (err < 0) { 6489 dev_err(card->dev, "error registering card\n"); 6490 return err; 6491 } 6492 6493 dev_dbg(card->dev, "... yes now\n"); 6494 6495 return 0; 6496 } 6497 6498 static int snd_hdspm_create(struct snd_card *card, 6499 struct hdspm *hdspm) 6500 { 6501 6502 struct pci_dev *pci = hdspm->pci; 6503 int err; 6504 unsigned long io_extent; 6505 6506 hdspm->irq = -1; 6507 hdspm->card = card; 6508 6509 spin_lock_init(&hdspm->lock); 6510 INIT_WORK(&hdspm->midi_work, hdspm_midi_work); 6511 6512 pci_read_config_word(hdspm->pci, 6513 PCI_CLASS_REVISION, &hdspm->firmware_rev); 6514 6515 strcpy(card->mixername, "Xilinx FPGA"); 6516 strcpy(card->driver, "HDSPM"); 6517 6518 switch (hdspm->firmware_rev) { 6519 case HDSPM_RAYDAT_REV: 6520 hdspm->io_type = RayDAT; 6521 hdspm->card_name = "RME RayDAT"; 6522 hdspm->midiPorts = 2; 6523 break; 6524 case HDSPM_AIO_REV: 6525 hdspm->io_type = AIO; 6526 hdspm->card_name = "RME AIO"; 6527 hdspm->midiPorts = 1; 6528 break; 6529 case HDSPM_MADIFACE_REV: 6530 hdspm->io_type = MADIface; 6531 hdspm->card_name = "RME MADIface"; 6532 hdspm->midiPorts = 1; 6533 break; 6534 default: 6535 if ((hdspm->firmware_rev == 0xf0) || 6536 ((hdspm->firmware_rev >= 0xe6) && 6537 (hdspm->firmware_rev <= 0xea))) { 6538 hdspm->io_type = AES32; 6539 hdspm->card_name = "RME AES32"; 6540 hdspm->midiPorts = 2; 6541 } else if ((hdspm->firmware_rev == 0xd2) || 6542 ((hdspm->firmware_rev >= 0xc8) && 6543 (hdspm->firmware_rev <= 0xcf))) { 6544 hdspm->io_type = MADI; 6545 hdspm->card_name = "RME MADI"; 6546 hdspm->midiPorts = 3; 6547 } else { 6548 dev_err(card->dev, 6549 "unknown firmware revision %x\n", 6550 hdspm->firmware_rev); 6551 return -ENODEV; 6552 } 6553 } 6554 6555 err = pcim_enable_device(pci); 6556 if (err < 0) 6557 return err; 6558 6559 pci_set_master(hdspm->pci); 6560 6561 err = pcim_iomap_regions(pci, 1 << 0, "hdspm"); 6562 if (err < 0) 6563 return err; 6564 6565 hdspm->port = pci_resource_start(pci, 0); 6566 io_extent = pci_resource_len(pci, 0); 6567 hdspm->iobase = pcim_iomap_table(pci)[0]; 6568 dev_dbg(card->dev, "remapped region (0x%lx) 0x%lx-0x%lx\n", 6569 (unsigned long)hdspm->iobase, hdspm->port, 6570 hdspm->port + io_extent - 1); 6571 6572 if (devm_request_irq(&pci->dev, pci->irq, snd_hdspm_interrupt, 6573 IRQF_SHARED, KBUILD_MODNAME, hdspm)) { 6574 dev_err(card->dev, "unable to use IRQ %d\n", pci->irq); 6575 return -EBUSY; 6576 } 6577 6578 dev_dbg(card->dev, "use IRQ %d\n", pci->irq); 6579 6580 hdspm->irq = pci->irq; 6581 card->sync_irq = hdspm->irq; 6582 6583 dev_dbg(card->dev, "kmalloc Mixer memory of %zd Bytes\n", 6584 sizeof(*hdspm->mixer)); 6585 hdspm->mixer = devm_kzalloc(&pci->dev, sizeof(*hdspm->mixer), GFP_KERNEL); 6586 if (!hdspm->mixer) 6587 return -ENOMEM; 6588 6589 hdspm->port_names_in = NULL; 6590 hdspm->port_names_out = NULL; 6591 6592 switch (hdspm->io_type) { 6593 case AES32: 6594 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS; 6595 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS; 6596 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS; 6597 6598 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6599 channel_map_aes32; 6600 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6601 channel_map_aes32; 6602 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6603 channel_map_aes32; 6604 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6605 texts_ports_aes32; 6606 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6607 texts_ports_aes32; 6608 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6609 texts_ports_aes32; 6610 6611 hdspm->max_channels_out = hdspm->max_channels_in = 6612 AES32_CHANNELS; 6613 hdspm->port_names_in = hdspm->port_names_out = 6614 texts_ports_aes32; 6615 hdspm->channel_map_in = hdspm->channel_map_out = 6616 channel_map_aes32; 6617 6618 break; 6619 6620 case MADI: 6621 case MADIface: 6622 hdspm->ss_in_channels = hdspm->ss_out_channels = 6623 MADI_SS_CHANNELS; 6624 hdspm->ds_in_channels = hdspm->ds_out_channels = 6625 MADI_DS_CHANNELS; 6626 hdspm->qs_in_channels = hdspm->qs_out_channels = 6627 MADI_QS_CHANNELS; 6628 6629 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6630 channel_map_unity_ss; 6631 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6632 channel_map_unity_ss; 6633 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6634 channel_map_unity_ss; 6635 6636 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6637 texts_ports_madi; 6638 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6639 texts_ports_madi; 6640 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6641 texts_ports_madi; 6642 break; 6643 6644 case AIO: 6645 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS; 6646 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS; 6647 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS; 6648 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS; 6649 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS; 6650 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS; 6651 6652 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) { 6653 dev_info(card->dev, "AEB input board found\n"); 6654 hdspm->ss_in_channels += 4; 6655 hdspm->ds_in_channels += 4; 6656 hdspm->qs_in_channels += 4; 6657 } 6658 6659 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) { 6660 dev_info(card->dev, "AEB output board found\n"); 6661 hdspm->ss_out_channels += 4; 6662 hdspm->ds_out_channels += 4; 6663 hdspm->qs_out_channels += 4; 6664 } 6665 6666 hdspm->channel_map_out_ss = channel_map_aio_out_ss; 6667 hdspm->channel_map_out_ds = channel_map_aio_out_ds; 6668 hdspm->channel_map_out_qs = channel_map_aio_out_qs; 6669 6670 hdspm->channel_map_in_ss = channel_map_aio_in_ss; 6671 hdspm->channel_map_in_ds = channel_map_aio_in_ds; 6672 hdspm->channel_map_in_qs = channel_map_aio_in_qs; 6673 6674 hdspm->port_names_in_ss = texts_ports_aio_in_ss; 6675 hdspm->port_names_out_ss = texts_ports_aio_out_ss; 6676 hdspm->port_names_in_ds = texts_ports_aio_in_ds; 6677 hdspm->port_names_out_ds = texts_ports_aio_out_ds; 6678 hdspm->port_names_in_qs = texts_ports_aio_in_qs; 6679 hdspm->port_names_out_qs = texts_ports_aio_out_qs; 6680 6681 break; 6682 6683 case RayDAT: 6684 hdspm->ss_in_channels = hdspm->ss_out_channels = 6685 RAYDAT_SS_CHANNELS; 6686 hdspm->ds_in_channels = hdspm->ds_out_channels = 6687 RAYDAT_DS_CHANNELS; 6688 hdspm->qs_in_channels = hdspm->qs_out_channels = 6689 RAYDAT_QS_CHANNELS; 6690 6691 hdspm->max_channels_in = RAYDAT_SS_CHANNELS; 6692 hdspm->max_channels_out = RAYDAT_SS_CHANNELS; 6693 6694 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6695 channel_map_raydat_ss; 6696 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6697 channel_map_raydat_ds; 6698 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6699 channel_map_raydat_qs; 6700 hdspm->channel_map_in = hdspm->channel_map_out = 6701 channel_map_raydat_ss; 6702 6703 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6704 texts_ports_raydat_ss; 6705 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6706 texts_ports_raydat_ds; 6707 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6708 texts_ports_raydat_qs; 6709 6710 6711 break; 6712 6713 } 6714 6715 /* TCO detection */ 6716 switch (hdspm->io_type) { 6717 case AIO: 6718 case RayDAT: 6719 if (hdspm_read(hdspm, HDSPM_statusRegister2) & 6720 HDSPM_s2_tco_detect) { 6721 hdspm->midiPorts++; 6722 hdspm->tco = kzalloc(sizeof(*hdspm->tco), GFP_KERNEL); 6723 if (hdspm->tco) 6724 hdspm_tco_write(hdspm); 6725 6726 dev_info(card->dev, "AIO/RayDAT TCO module found\n"); 6727 } else { 6728 hdspm->tco = NULL; 6729 } 6730 break; 6731 6732 case MADI: 6733 case AES32: 6734 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) { 6735 hdspm->midiPorts++; 6736 hdspm->tco = kzalloc(sizeof(*hdspm->tco), GFP_KERNEL); 6737 if (hdspm->tco) 6738 hdspm_tco_write(hdspm); 6739 6740 dev_info(card->dev, "MADI/AES TCO module found\n"); 6741 } else { 6742 hdspm->tco = NULL; 6743 } 6744 break; 6745 6746 default: 6747 hdspm->tco = NULL; 6748 } 6749 6750 /* texts */ 6751 switch (hdspm->io_type) { 6752 case AES32: 6753 if (hdspm->tco) { 6754 hdspm->texts_autosync = texts_autosync_aes_tco; 6755 hdspm->texts_autosync_items = 6756 ARRAY_SIZE(texts_autosync_aes_tco); 6757 } else { 6758 hdspm->texts_autosync = texts_autosync_aes; 6759 hdspm->texts_autosync_items = 6760 ARRAY_SIZE(texts_autosync_aes); 6761 } 6762 break; 6763 6764 case MADI: 6765 if (hdspm->tco) { 6766 hdspm->texts_autosync = texts_autosync_madi_tco; 6767 hdspm->texts_autosync_items = 4; 6768 } else { 6769 hdspm->texts_autosync = texts_autosync_madi; 6770 hdspm->texts_autosync_items = 3; 6771 } 6772 break; 6773 6774 case MADIface: 6775 6776 break; 6777 6778 case RayDAT: 6779 if (hdspm->tco) { 6780 hdspm->texts_autosync = texts_autosync_raydat_tco; 6781 hdspm->texts_autosync_items = 9; 6782 } else { 6783 hdspm->texts_autosync = texts_autosync_raydat; 6784 hdspm->texts_autosync_items = 8; 6785 } 6786 break; 6787 6788 case AIO: 6789 if (hdspm->tco) { 6790 hdspm->texts_autosync = texts_autosync_aio_tco; 6791 hdspm->texts_autosync_items = 6; 6792 } else { 6793 hdspm->texts_autosync = texts_autosync_aio; 6794 hdspm->texts_autosync_items = 5; 6795 } 6796 break; 6797 6798 } 6799 6800 if (hdspm->io_type != MADIface) { 6801 hdspm->serial = (hdspm_read(hdspm, 6802 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF; 6803 /* id contains either a user-provided value or the default 6804 * NULL. If it's the default, we're safe to 6805 * fill card->id with the serial number. 6806 * 6807 * If the serial number is 0xFFFFFF, then we're dealing with 6808 * an old PCI revision that comes without a sane number. In 6809 * this case, we don't set card->id to avoid collisions 6810 * when running with multiple cards. 6811 */ 6812 if (!id[hdspm->dev] && hdspm->serial != 0xFFFFFF) { 6813 snprintf(card->id, sizeof(card->id), 6814 "HDSPMx%06x", hdspm->serial); 6815 snd_card_set_id(card, card->id); 6816 } 6817 } 6818 6819 dev_dbg(card->dev, "create alsa devices.\n"); 6820 err = snd_hdspm_create_alsa_devices(card, hdspm); 6821 if (err < 0) 6822 return err; 6823 6824 snd_hdspm_initialize_midi_flush(hdspm); 6825 6826 return 0; 6827 } 6828 6829 6830 static void snd_hdspm_card_free(struct snd_card *card) 6831 { 6832 struct hdspm *hdspm = card->private_data; 6833 6834 if (hdspm->port) { 6835 cancel_work_sync(&hdspm->midi_work); 6836 6837 /* stop th audio, and cancel all interrupts */ 6838 hdspm->control_register &= 6839 ~(HDSPM_Start | HDSPM_AudioInterruptEnable | 6840 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable | 6841 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable); 6842 hdspm_write(hdspm, HDSPM_controlRegister, 6843 hdspm->control_register); 6844 } 6845 } 6846 6847 6848 static int snd_hdspm_probe(struct pci_dev *pci, 6849 const struct pci_device_id *pci_id) 6850 { 6851 static int dev; 6852 struct hdspm *hdspm; 6853 struct snd_card *card; 6854 int err; 6855 6856 if (dev >= SNDRV_CARDS) 6857 return -ENODEV; 6858 if (!enable[dev]) { 6859 dev++; 6860 return -ENOENT; 6861 } 6862 6863 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], 6864 THIS_MODULE, sizeof(*hdspm), &card); 6865 if (err < 0) 6866 return err; 6867 6868 hdspm = card->private_data; 6869 card->private_free = snd_hdspm_card_free; 6870 hdspm->dev = dev; 6871 hdspm->pci = pci; 6872 6873 err = snd_hdspm_create(card, hdspm); 6874 if (err < 0) 6875 goto error; 6876 6877 if (hdspm->io_type != MADIface) { 6878 snprintf(card->shortname, sizeof(card->shortname), "%s_%x", 6879 hdspm->card_name, hdspm->serial); 6880 snprintf(card->longname, sizeof(card->longname), 6881 "%s S/N 0x%x at 0x%lx, irq %d", 6882 hdspm->card_name, hdspm->serial, 6883 hdspm->port, hdspm->irq); 6884 } else { 6885 snprintf(card->shortname, sizeof(card->shortname), "%s", 6886 hdspm->card_name); 6887 snprintf(card->longname, sizeof(card->longname), 6888 "%s at 0x%lx, irq %d", 6889 hdspm->card_name, hdspm->port, hdspm->irq); 6890 } 6891 6892 err = snd_card_register(card); 6893 if (err < 0) 6894 goto error; 6895 6896 pci_set_drvdata(pci, card); 6897 6898 dev++; 6899 return 0; 6900 6901 error: 6902 snd_card_free(card); 6903 return err; 6904 } 6905 6906 static struct pci_driver hdspm_driver = { 6907 .name = KBUILD_MODNAME, 6908 .id_table = snd_hdspm_ids, 6909 .probe = snd_hdspm_probe, 6910 }; 6911 6912 module_pci_driver(hdspm_driver); 6913