1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * Wave5 series multi-standard codec IP - encoder interface 4 * 5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC 6 */ 7 8 #include <linux/pm_runtime.h> 9 #include "wave5-helper.h" 10 11 #define VPU_ENC_DEV_NAME "C&M Wave5 VPU encoder" 12 #define VPU_ENC_DRV_NAME "wave5-enc" 13 14 static const struct v4l2_frmsize_stepwise enc_frmsize[FMT_TYPES] = { 15 [VPU_FMT_TYPE_CODEC] = { 16 .min_width = W5_MIN_ENC_PIC_WIDTH, 17 .max_width = W5_MAX_ENC_PIC_WIDTH, 18 .step_width = W5_ENC_CODEC_STEP_WIDTH, 19 .min_height = W5_MIN_ENC_PIC_HEIGHT, 20 .max_height = W5_MAX_ENC_PIC_HEIGHT, 21 .step_height = W5_ENC_CODEC_STEP_HEIGHT, 22 }, 23 [VPU_FMT_TYPE_RAW] = { 24 .min_width = W5_MIN_ENC_PIC_WIDTH, 25 .max_width = W5_MAX_ENC_PIC_WIDTH, 26 .step_width = W5_ENC_RAW_STEP_WIDTH, 27 .min_height = W5_MIN_ENC_PIC_HEIGHT, 28 .max_height = W5_MAX_ENC_PIC_HEIGHT, 29 .step_height = W5_ENC_RAW_STEP_HEIGHT, 30 }, 31 }; 32 33 static const struct vpu_format enc_fmt_list[FMT_TYPES][MAX_FMTS] = { 34 [VPU_FMT_TYPE_CODEC] = { 35 { 36 .v4l2_pix_fmt = V4L2_PIX_FMT_HEVC, 37 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_CODEC], 38 }, 39 { 40 .v4l2_pix_fmt = V4L2_PIX_FMT_H264, 41 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_CODEC], 42 }, 43 }, 44 [VPU_FMT_TYPE_RAW] = { 45 { 46 .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420, 47 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], 48 }, 49 { 50 .v4l2_pix_fmt = V4L2_PIX_FMT_NV12, 51 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], 52 }, 53 { 54 .v4l2_pix_fmt = V4L2_PIX_FMT_NV21, 55 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], 56 }, 57 { 58 .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420M, 59 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], 60 }, 61 { 62 .v4l2_pix_fmt = V4L2_PIX_FMT_NV12M, 63 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], 64 }, 65 { 66 .v4l2_pix_fmt = V4L2_PIX_FMT_NV21M, 67 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], 68 }, 69 { 70 .v4l2_pix_fmt = V4L2_PIX_FMT_YUV422P, 71 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], 72 }, 73 { 74 .v4l2_pix_fmt = V4L2_PIX_FMT_NV16, 75 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], 76 }, 77 { 78 .v4l2_pix_fmt = V4L2_PIX_FMT_NV61, 79 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], 80 }, 81 { 82 .v4l2_pix_fmt = V4L2_PIX_FMT_YUV422M, 83 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], 84 }, 85 { 86 .v4l2_pix_fmt = V4L2_PIX_FMT_NV16M, 87 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], 88 }, 89 { 90 .v4l2_pix_fmt = V4L2_PIX_FMT_NV61M, 91 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], 92 }, 93 { 94 .v4l2_pix_fmt = V4L2_PIX_FMT_YUYV, 95 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], 96 }, 97 { 98 .v4l2_pix_fmt = V4L2_PIX_FMT_YVYU, 99 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], 100 }, 101 { 102 .v4l2_pix_fmt = V4L2_PIX_FMT_UYVY, 103 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], 104 }, 105 { 106 .v4l2_pix_fmt = V4L2_PIX_FMT_VYUY, 107 .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], 108 }, 109 } 110 }; 111 112 static int switch_state(struct vpu_instance *inst, enum vpu_instance_state state) 113 { 114 switch (state) { 115 case VPU_INST_STATE_NONE: 116 goto invalid_state_switch; 117 case VPU_INST_STATE_OPEN: 118 if (inst->state != VPU_INST_STATE_NONE) 119 goto invalid_state_switch; 120 break; 121 case VPU_INST_STATE_INIT_SEQ: 122 if (inst->state != VPU_INST_STATE_OPEN && inst->state != VPU_INST_STATE_STOP) 123 goto invalid_state_switch; 124 break; 125 case VPU_INST_STATE_PIC_RUN: 126 if (inst->state != VPU_INST_STATE_INIT_SEQ) 127 goto invalid_state_switch; 128 break; 129 case VPU_INST_STATE_STOP: 130 break; 131 } 132 133 dev_dbg(inst->dev->dev, "Switch state from %s to %s.\n", 134 state_to_str(inst->state), state_to_str(state)); 135 inst->state = state; 136 return 0; 137 138 invalid_state_switch: 139 WARN(1, "Invalid state switch from %s to %s.\n", 140 state_to_str(inst->state), state_to_str(state)); 141 return -EINVAL; 142 } 143 144 static int start_encode(struct vpu_instance *inst, u32 *fail_res) 145 { 146 struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; 147 int ret; 148 struct vb2_v4l2_buffer *src_buf; 149 struct vb2_v4l2_buffer *dst_buf; 150 struct frame_buffer frame_buf; 151 struct enc_param pic_param; 152 const struct v4l2_format_info *info; 153 u32 stride = inst->src_fmt.plane_fmt[0].bytesperline; 154 u32 luma_size = 0; 155 u32 chroma_size = 0; 156 157 memset(&pic_param, 0, sizeof(struct enc_param)); 158 memset(&frame_buf, 0, sizeof(struct frame_buffer)); 159 160 info = v4l2_format_info(inst->src_fmt.pixelformat); 161 if (!info) 162 return -EINVAL; 163 164 if (info->mem_planes == 1) { 165 luma_size = stride * inst->dst_fmt.height; 166 chroma_size = luma_size / (info->hdiv * info->vdiv); 167 } else { 168 luma_size = inst->src_fmt.plane_fmt[0].sizeimage; 169 chroma_size = inst->src_fmt.plane_fmt[1].sizeimage; 170 } 171 172 dst_buf = v4l2_m2m_next_dst_buf(m2m_ctx); 173 if (!dst_buf) { 174 dev_dbg(inst->dev->dev, "%s: No destination buffer found\n", __func__); 175 return -EAGAIN; 176 } 177 178 pic_param.pic_stream_buffer_addr = 179 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); 180 pic_param.pic_stream_buffer_size = 181 vb2_plane_size(&dst_buf->vb2_buf, 0); 182 183 src_buf = v4l2_m2m_next_src_buf(m2m_ctx); 184 if (!src_buf) { 185 dev_dbg(inst->dev->dev, "%s: No source buffer found\n", __func__); 186 if (m2m_ctx->is_draining) 187 pic_param.src_end_flag = 1; 188 else 189 return -EAGAIN; 190 } else { 191 if (inst->src_fmt.num_planes == 1) { 192 frame_buf.buf_y = 193 vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); 194 frame_buf.buf_cb = frame_buf.buf_y + luma_size; 195 frame_buf.buf_cr = frame_buf.buf_cb + chroma_size; 196 } else if (inst->src_fmt.num_planes == 2) { 197 frame_buf.buf_y = 198 vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); 199 frame_buf.buf_cb = 200 vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 1); 201 frame_buf.buf_cr = frame_buf.buf_cb + chroma_size; 202 } else if (inst->src_fmt.num_planes == 3) { 203 frame_buf.buf_y = 204 vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); 205 frame_buf.buf_cb = 206 vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 1); 207 frame_buf.buf_cr = 208 vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 2); 209 } 210 frame_buf.stride = stride; 211 pic_param.src_idx = src_buf->vb2_buf.index; 212 } 213 214 pic_param.source_frame = &frame_buf; 215 pic_param.code_option.implicit_header_encode = 1; 216 pic_param.code_option.encode_aud = inst->encode_aud; 217 ret = wave5_vpu_enc_start_one_frame(inst, &pic_param, fail_res); 218 if (ret) { 219 if (*fail_res == WAVE5_SYSERR_QUEUEING_FAIL) 220 return -EINVAL; 221 222 dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_start_one_frame fail: %d\n", 223 __func__, ret); 224 src_buf = v4l2_m2m_src_buf_remove(m2m_ctx); 225 if (!src_buf) { 226 dev_dbg(inst->dev->dev, 227 "%s: Removing src buf failed, the queue is empty\n", 228 __func__); 229 return -EINVAL; 230 } 231 dst_buf = v4l2_m2m_dst_buf_remove(m2m_ctx); 232 if (!dst_buf) { 233 dev_dbg(inst->dev->dev, 234 "%s: Removing dst buf failed, the queue is empty\n", 235 __func__); 236 return -EINVAL; 237 } 238 switch_state(inst, VPU_INST_STATE_STOP); 239 dst_buf->vb2_buf.timestamp = src_buf->vb2_buf.timestamp; 240 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); 241 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR); 242 } else { 243 dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_start_one_frame success\n", 244 __func__); 245 } 246 247 return 0; 248 } 249 250 static void wave5_vpu_enc_finish_encode(struct vpu_instance *inst) 251 { 252 struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; 253 int ret; 254 struct enc_output_info enc_output_info; 255 struct vb2_v4l2_buffer *src_buf = NULL; 256 struct vb2_v4l2_buffer *dst_buf = NULL; 257 258 ret = wave5_vpu_enc_get_output_info(inst, &enc_output_info); 259 if (ret) { 260 dev_dbg(inst->dev->dev, 261 "%s: vpu_enc_get_output_info fail: %d reason: %u | info: %u\n", 262 __func__, ret, enc_output_info.error_reason, enc_output_info.warn_info); 263 return; 264 } 265 266 dev_dbg(inst->dev->dev, 267 "%s: pic_type %i recon_idx %i src_idx %i pic_byte %u pts %llu\n", 268 __func__, enc_output_info.pic_type, enc_output_info.recon_frame_index, 269 enc_output_info.enc_src_idx, enc_output_info.enc_pic_byte, enc_output_info.pts); 270 271 if (enc_output_info.enc_src_idx >= 0) { 272 src_buf = v4l2_m2m_src_buf_remove_by_idx(m2m_ctx, enc_output_info.enc_src_idx); 273 if (!src_buf) { 274 dev_warn(inst->dev->dev, "%s: no source buffer found\n", __func__); 275 } else { 276 inst->timestamp = src_buf->vb2_buf.timestamp; 277 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); 278 } 279 } 280 281 dst_buf = v4l2_m2m_dst_buf_remove(m2m_ctx); 282 if (enc_output_info.recon_frame_index == RECON_IDX_FLAG_ENC_END) { 283 static const struct v4l2_event vpu_event_eos = { 284 .type = V4L2_EVENT_EOS 285 }; 286 287 if (!WARN_ON(!dst_buf)) { 288 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, 0); 289 dst_buf->field = V4L2_FIELD_NONE; 290 v4l2_m2m_last_buffer_done(m2m_ctx, dst_buf); 291 } 292 293 v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_eos); 294 295 v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); 296 } else { 297 if (!dst_buf) { 298 dev_warn(inst->dev->dev, "No bitstream buffer."); 299 v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); 300 return; 301 } 302 303 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, enc_output_info.bitstream_size); 304 305 dst_buf->vb2_buf.timestamp = inst->timestamp; 306 dst_buf->field = V4L2_FIELD_NONE; 307 if (enc_output_info.pic_type == PIC_TYPE_I) { 308 if (enc_output_info.enc_vcl_nut == 19 || 309 enc_output_info.enc_vcl_nut == 20) 310 dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME; 311 else 312 dst_buf->flags |= V4L2_BUF_FLAG_PFRAME; 313 } else if (enc_output_info.pic_type == PIC_TYPE_P) { 314 dst_buf->flags |= V4L2_BUF_FLAG_PFRAME; 315 } else if (enc_output_info.pic_type == PIC_TYPE_B) { 316 dst_buf->flags |= V4L2_BUF_FLAG_BFRAME; 317 } 318 319 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); 320 321 dev_dbg(inst->dev->dev, "%s: frame_cycle %8u\n", 322 __func__, enc_output_info.frame_cycle); 323 324 v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); 325 } 326 } 327 328 static int wave5_vpu_enc_querycap(struct file *file, void *fh, struct v4l2_capability *cap) 329 { 330 strscpy(cap->driver, VPU_ENC_DRV_NAME, sizeof(cap->driver)); 331 strscpy(cap->card, VPU_ENC_DRV_NAME, sizeof(cap->card)); 332 333 return 0; 334 } 335 336 static int wave5_vpu_enc_enum_framesizes(struct file *f, void *fh, struct v4l2_frmsizeenum *fsize) 337 { 338 const struct vpu_format *vpu_fmt; 339 340 if (fsize->index) 341 return -EINVAL; 342 343 vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, enc_fmt_list[VPU_FMT_TYPE_CODEC]); 344 if (!vpu_fmt) { 345 vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, enc_fmt_list[VPU_FMT_TYPE_RAW]); 346 if (!vpu_fmt) 347 return -EINVAL; 348 } 349 350 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; 351 fsize->stepwise = enc_frmsize[VPU_FMT_TYPE_CODEC]; 352 353 return 0; 354 } 355 356 static int wave5_vpu_enc_enum_fmt_cap(struct file *file, void *fh, struct v4l2_fmtdesc *f) 357 { 358 struct vpu_instance *inst = file_to_vpu_inst(file); 359 const struct vpu_format *vpu_fmt; 360 361 dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index); 362 363 vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, enc_fmt_list[VPU_FMT_TYPE_CODEC]); 364 if (!vpu_fmt) 365 return -EINVAL; 366 367 f->pixelformat = vpu_fmt->v4l2_pix_fmt; 368 f->flags = 0; 369 370 return 0; 371 } 372 373 static int wave5_vpu_enc_try_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) 374 { 375 struct vpu_instance *inst = file_to_vpu_inst(file); 376 const struct v4l2_frmsize_stepwise *frmsize; 377 const struct vpu_format *vpu_fmt; 378 int width, height; 379 380 dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", 381 __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, 382 f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); 383 384 vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_CODEC]); 385 if (!vpu_fmt) { 386 width = inst->dst_fmt.width; 387 height = inst->dst_fmt.height; 388 f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; 389 frmsize = &enc_frmsize[VPU_FMT_TYPE_CODEC]; 390 } else { 391 width = f->fmt.pix_mp.width; 392 height = f->fmt.pix_mp.height; 393 f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; 394 frmsize = vpu_fmt->v4l2_frmsize; 395 } 396 397 wave5_update_pix_fmt(&f->fmt.pix_mp, VPU_FMT_TYPE_CODEC, 398 width, height, frmsize); 399 f->fmt.pix_mp.colorspace = inst->colorspace; 400 f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; 401 f->fmt.pix_mp.quantization = inst->quantization; 402 f->fmt.pix_mp.xfer_func = inst->xfer_func; 403 404 return 0; 405 } 406 407 static int wave5_vpu_enc_s_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) 408 { 409 struct vpu_instance *inst = file_to_vpu_inst(file); 410 int i, ret; 411 412 dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", 413 __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, 414 f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); 415 416 ret = wave5_vpu_enc_try_fmt_cap(file, fh, f); 417 if (ret) 418 return ret; 419 420 inst->std = wave5_to_vpu_std(f->fmt.pix_mp.pixelformat, inst->type); 421 if (inst->std == STD_UNKNOWN) { 422 dev_warn(inst->dev->dev, "unsupported pixelformat: %.4s\n", 423 (char *)&f->fmt.pix_mp.pixelformat); 424 return -EINVAL; 425 } 426 427 inst->dst_fmt.width = f->fmt.pix_mp.width; 428 inst->dst_fmt.height = f->fmt.pix_mp.height; 429 inst->dst_fmt.pixelformat = f->fmt.pix_mp.pixelformat; 430 inst->dst_fmt.field = f->fmt.pix_mp.field; 431 inst->dst_fmt.flags = f->fmt.pix_mp.flags; 432 inst->dst_fmt.num_planes = f->fmt.pix_mp.num_planes; 433 for (i = 0; i < inst->dst_fmt.num_planes; i++) { 434 inst->dst_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; 435 inst->dst_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; 436 } 437 438 return 0; 439 } 440 441 static int wave5_vpu_enc_g_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) 442 { 443 struct vpu_instance *inst = file_to_vpu_inst(file); 444 int i; 445 446 f->fmt.pix_mp.width = inst->dst_fmt.width; 447 f->fmt.pix_mp.height = inst->dst_fmt.height; 448 f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; 449 f->fmt.pix_mp.field = inst->dst_fmt.field; 450 f->fmt.pix_mp.flags = inst->dst_fmt.flags; 451 f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; 452 for (i = 0; i < f->fmt.pix_mp.num_planes; i++) { 453 f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->dst_fmt.plane_fmt[i].bytesperline; 454 f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->dst_fmt.plane_fmt[i].sizeimage; 455 } 456 457 f->fmt.pix_mp.colorspace = inst->colorspace; 458 f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; 459 f->fmt.pix_mp.quantization = inst->quantization; 460 f->fmt.pix_mp.xfer_func = inst->xfer_func; 461 462 return 0; 463 } 464 465 static int wave5_vpu_enc_enum_fmt_out(struct file *file, void *fh, struct v4l2_fmtdesc *f) 466 { 467 struct vpu_instance *inst = file_to_vpu_inst(file); 468 const struct vpu_format *vpu_fmt; 469 470 dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index); 471 472 vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, enc_fmt_list[VPU_FMT_TYPE_RAW]); 473 if (!vpu_fmt) 474 return -EINVAL; 475 476 f->pixelformat = vpu_fmt->v4l2_pix_fmt; 477 f->flags = 0; 478 479 return 0; 480 } 481 482 static int wave5_vpu_enc_try_fmt_out(struct file *file, void *fh, struct v4l2_format *f) 483 { 484 struct vpu_instance *inst = file_to_vpu_inst(file); 485 const struct v4l2_frmsize_stepwise *frmsize; 486 const struct vpu_format *vpu_fmt; 487 int width, height; 488 489 dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", 490 __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, 491 f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); 492 493 vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_RAW]); 494 if (!vpu_fmt) { 495 width = inst->src_fmt.width; 496 height = inst->src_fmt.height; 497 f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; 498 frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW]; 499 } else { 500 width = f->fmt.pix_mp.width; 501 height = f->fmt.pix_mp.height; 502 f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; 503 frmsize = vpu_fmt->v4l2_frmsize; 504 } 505 506 wave5_update_pix_fmt(&f->fmt.pix_mp, VPU_FMT_TYPE_RAW, 507 width, height, frmsize); 508 return 0; 509 } 510 511 static int wave5_vpu_enc_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f) 512 { 513 struct vpu_instance *inst = file_to_vpu_inst(file); 514 const struct vpu_format *vpu_fmt; 515 const struct v4l2_format_info *info; 516 int i, ret; 517 518 dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", 519 __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, 520 f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); 521 522 ret = wave5_vpu_enc_try_fmt_out(file, fh, f); 523 if (ret) 524 return ret; 525 526 inst->src_fmt.width = f->fmt.pix_mp.width; 527 inst->src_fmt.height = f->fmt.pix_mp.height; 528 inst->src_fmt.pixelformat = f->fmt.pix_mp.pixelformat; 529 inst->src_fmt.field = f->fmt.pix_mp.field; 530 inst->src_fmt.flags = f->fmt.pix_mp.flags; 531 inst->src_fmt.num_planes = f->fmt.pix_mp.num_planes; 532 for (i = 0; i < inst->src_fmt.num_planes; i++) { 533 inst->src_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; 534 inst->src_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; 535 } 536 537 info = v4l2_format_info(inst->src_fmt.pixelformat); 538 if (!info) 539 return -EINVAL; 540 541 inst->cbcr_interleave = info->comp_planes == 2; 542 543 switch (inst->src_fmt.pixelformat) { 544 case V4L2_PIX_FMT_NV21: 545 case V4L2_PIX_FMT_NV21M: 546 case V4L2_PIX_FMT_NV61: 547 case V4L2_PIX_FMT_NV61M: 548 inst->nv21 = true; 549 break; 550 default: 551 inst->nv21 = false; 552 } 553 554 inst->colorspace = f->fmt.pix_mp.colorspace; 555 inst->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; 556 inst->quantization = f->fmt.pix_mp.quantization; 557 inst->xfer_func = f->fmt.pix_mp.xfer_func; 558 559 vpu_fmt = wave5_find_vpu_fmt(inst->dst_fmt.pixelformat, enc_fmt_list[VPU_FMT_TYPE_CODEC]); 560 if (!vpu_fmt) 561 return -EINVAL; 562 563 wave5_update_pix_fmt(&inst->dst_fmt, VPU_FMT_TYPE_CODEC, 564 f->fmt.pix_mp.width, f->fmt.pix_mp.height, 565 vpu_fmt->v4l2_frmsize); 566 inst->conf_win.width = inst->dst_fmt.width; 567 inst->conf_win.height = inst->dst_fmt.height; 568 569 return 0; 570 } 571 572 static int wave5_vpu_enc_g_selection(struct file *file, void *fh, struct v4l2_selection *s) 573 { 574 struct vpu_instance *inst = file_to_vpu_inst(file); 575 576 dev_dbg(inst->dev->dev, "%s: type: %u | target: %u\n", __func__, s->type, s->target); 577 578 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) 579 return -EINVAL; 580 switch (s->target) { 581 case V4L2_SEL_TGT_CROP_DEFAULT: 582 case V4L2_SEL_TGT_CROP_BOUNDS: 583 s->r.left = 0; 584 s->r.top = 0; 585 s->r.width = inst->dst_fmt.width; 586 s->r.height = inst->dst_fmt.height; 587 break; 588 case V4L2_SEL_TGT_CROP: 589 s->r.left = 0; 590 s->r.top = 0; 591 s->r.width = inst->conf_win.width; 592 s->r.height = inst->conf_win.height; 593 break; 594 default: 595 return -EINVAL; 596 } 597 598 return 0; 599 } 600 601 static int wave5_vpu_enc_s_selection(struct file *file, void *fh, struct v4l2_selection *s) 602 { 603 struct vpu_instance *inst = file_to_vpu_inst(file); 604 605 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) 606 return -EINVAL; 607 608 if (s->target != V4L2_SEL_TGT_CROP) 609 return -EINVAL; 610 611 dev_dbg(inst->dev->dev, "%s: V4L2_SEL_TGT_CROP width: %u | height: %u\n", 612 __func__, s->r.width, s->r.height); 613 614 s->r.left = 0; 615 s->r.top = 0; 616 s->r.width = min(s->r.width, inst->dst_fmt.width); 617 s->r.height = min(s->r.height, inst->dst_fmt.height); 618 619 inst->conf_win = s->r; 620 621 return 0; 622 } 623 624 static int wave5_vpu_enc_encoder_cmd(struct file *file, void *fh, struct v4l2_encoder_cmd *ec) 625 { 626 struct vpu_instance *inst = file_to_vpu_inst(file); 627 struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; 628 int ret; 629 630 ret = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, ec); 631 if (ret) 632 return ret; 633 634 if (!wave5_vpu_both_queues_are_streaming(inst)) 635 return 0; 636 637 switch (ec->cmd) { 638 case V4L2_ENC_CMD_STOP: 639 if (m2m_ctx->is_draining) 640 return -EBUSY; 641 642 if (m2m_ctx->has_stopped) 643 return 0; 644 645 m2m_ctx->last_src_buf = v4l2_m2m_last_src_buf(m2m_ctx); 646 m2m_ctx->is_draining = true; 647 648 v4l2_m2m_try_schedule(m2m_ctx); 649 break; 650 case V4L2_ENC_CMD_START: 651 break; 652 default: 653 return -EINVAL; 654 } 655 656 return 0; 657 } 658 659 static int wave5_vpu_enc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a) 660 { 661 struct vpu_instance *inst = file_to_vpu_inst(file); 662 663 dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, a->type); 664 665 if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT && a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) 666 return -EINVAL; 667 668 a->parm.output.capability = V4L2_CAP_TIMEPERFRAME; 669 a->parm.output.timeperframe.numerator = 1; 670 a->parm.output.timeperframe.denominator = inst->frame_rate; 671 672 dev_dbg(inst->dev->dev, "%s: numerator: %u | denominator: %u\n", 673 __func__, a->parm.output.timeperframe.numerator, 674 a->parm.output.timeperframe.denominator); 675 676 return 0; 677 } 678 679 static int wave5_vpu_enc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a) 680 { 681 struct vpu_instance *inst = file_to_vpu_inst(file); 682 683 dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, a->type); 684 685 if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT && a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) 686 return -EINVAL; 687 688 a->parm.output.capability = V4L2_CAP_TIMEPERFRAME; 689 if (a->parm.output.timeperframe.denominator && a->parm.output.timeperframe.numerator) { 690 inst->frame_rate = a->parm.output.timeperframe.denominator / 691 a->parm.output.timeperframe.numerator; 692 } else { 693 a->parm.output.timeperframe.numerator = 1; 694 a->parm.output.timeperframe.denominator = inst->frame_rate; 695 } 696 697 dev_dbg(inst->dev->dev, "%s: numerator: %u | denominator: %u\n", 698 __func__, a->parm.output.timeperframe.numerator, 699 a->parm.output.timeperframe.denominator); 700 701 return 0; 702 } 703 704 static const struct v4l2_ioctl_ops wave5_vpu_enc_ioctl_ops = { 705 .vidioc_querycap = wave5_vpu_enc_querycap, 706 .vidioc_enum_framesizes = wave5_vpu_enc_enum_framesizes, 707 708 .vidioc_enum_fmt_vid_cap = wave5_vpu_enc_enum_fmt_cap, 709 .vidioc_s_fmt_vid_cap_mplane = wave5_vpu_enc_s_fmt_cap, 710 .vidioc_g_fmt_vid_cap_mplane = wave5_vpu_enc_g_fmt_cap, 711 .vidioc_try_fmt_vid_cap_mplane = wave5_vpu_enc_try_fmt_cap, 712 713 .vidioc_enum_fmt_vid_out = wave5_vpu_enc_enum_fmt_out, 714 .vidioc_s_fmt_vid_out_mplane = wave5_vpu_enc_s_fmt_out, 715 .vidioc_g_fmt_vid_out_mplane = wave5_vpu_g_fmt_out, 716 .vidioc_try_fmt_vid_out_mplane = wave5_vpu_enc_try_fmt_out, 717 718 .vidioc_g_selection = wave5_vpu_enc_g_selection, 719 .vidioc_s_selection = wave5_vpu_enc_s_selection, 720 721 .vidioc_g_parm = wave5_vpu_enc_g_parm, 722 .vidioc_s_parm = wave5_vpu_enc_s_parm, 723 724 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, 725 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, 726 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, 727 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, 728 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, 729 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, 730 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, 731 .vidioc_streamon = v4l2_m2m_ioctl_streamon, 732 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, 733 734 .vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd, 735 .vidioc_encoder_cmd = wave5_vpu_enc_encoder_cmd, 736 737 .vidioc_subscribe_event = wave5_vpu_subscribe_event, 738 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 739 }; 740 741 static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl) 742 { 743 struct vpu_instance *inst = wave5_ctrl_to_vpu_inst(ctrl); 744 745 dev_dbg(inst->dev->dev, "%s: name: %s | value: %d\n", __func__, ctrl->name, ctrl->val); 746 747 switch (ctrl->id) { 748 case V4L2_CID_MPEG_VIDEO_AU_DELIMITER: 749 inst->encode_aud = ctrl->val; 750 break; 751 case V4L2_CID_HFLIP: 752 inst->mirror_direction |= (ctrl->val << 1); 753 break; 754 case V4L2_CID_VFLIP: 755 inst->mirror_direction |= ctrl->val; 756 break; 757 case V4L2_CID_ROTATE: 758 inst->rot_angle = ctrl->val; 759 break; 760 case V4L2_CID_MPEG_VIDEO_VBV_SIZE: 761 inst->vbv_buf_size = ctrl->val; 762 break; 763 case V4L2_CID_MPEG_VIDEO_BITRATE_MODE: 764 switch (ctrl->val) { 765 case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR: 766 inst->rc_mode = 0; 767 break; 768 case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR: 769 inst->rc_mode = 1; 770 break; 771 default: 772 return -EINVAL; 773 } 774 break; 775 case V4L2_CID_MPEG_VIDEO_BITRATE: 776 inst->bit_rate = ctrl->val; 777 break; 778 case V4L2_CID_MPEG_VIDEO_BACKGROUND_DETECTION: 779 inst->enc_param.bg_detection = ctrl->val; 780 break; 781 case V4L2_CID_MPEG_VIDEO_GOP_SIZE: 782 inst->enc_param.avc_idr_period = ctrl->val; 783 break; 784 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE: 785 inst->enc_param.independ_slice_mode = ctrl->val; 786 inst->enc_param.avc_slice_mode = ctrl->val; 787 break; 788 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB: 789 inst->enc_param.independ_slice_mode_arg = ctrl->val; 790 inst->enc_param.avc_slice_arg = ctrl->val; 791 break; 792 case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE: 793 inst->rc_enable = ctrl->val; 794 break; 795 case V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE: 796 inst->enc_param.mb_level_rc_enable = ctrl->val; 797 inst->enc_param.cu_level_rc_enable = ctrl->val; 798 inst->enc_param.hvs_qp_enable = ctrl->val; 799 break; 800 case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE: 801 switch (ctrl->val) { 802 case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN: 803 inst->enc_param.profile = HEVC_PROFILE_MAIN; 804 inst->bit_depth = 8; 805 break; 806 case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE: 807 inst->enc_param.profile = HEVC_PROFILE_STILLPICTURE; 808 inst->enc_param.en_still_picture = 1; 809 inst->bit_depth = 8; 810 break; 811 case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10: 812 inst->enc_param.profile = HEVC_PROFILE_MAIN10; 813 inst->bit_depth = 10; 814 break; 815 default: 816 return -EINVAL; 817 } 818 break; 819 case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: 820 switch (ctrl->val) { 821 case V4L2_MPEG_VIDEO_HEVC_LEVEL_1: 822 inst->enc_param.level = 10 * 3; 823 break; 824 case V4L2_MPEG_VIDEO_HEVC_LEVEL_2: 825 inst->enc_param.level = 20 * 3; 826 break; 827 case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1: 828 inst->enc_param.level = 21 * 3; 829 break; 830 case V4L2_MPEG_VIDEO_HEVC_LEVEL_3: 831 inst->enc_param.level = 30 * 3; 832 break; 833 case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1: 834 inst->enc_param.level = 31 * 3; 835 break; 836 case V4L2_MPEG_VIDEO_HEVC_LEVEL_4: 837 inst->enc_param.level = 40 * 3; 838 break; 839 case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1: 840 inst->enc_param.level = 41 * 3; 841 break; 842 case V4L2_MPEG_VIDEO_HEVC_LEVEL_5: 843 inst->enc_param.level = 50 * 3; 844 break; 845 case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1: 846 inst->enc_param.level = 51 * 3; 847 break; 848 case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2: 849 inst->enc_param.level = 52 * 3; 850 break; 851 default: 852 return -EINVAL; 853 } 854 break; 855 case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: 856 inst->enc_param.min_qp_i = ctrl->val; 857 inst->enc_param.min_qp_p = ctrl->val; 858 inst->enc_param.min_qp_b = ctrl->val; 859 break; 860 case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: 861 inst->enc_param.max_qp_i = ctrl->val; 862 inst->enc_param.max_qp_p = ctrl->val; 863 inst->enc_param.max_qp_b = ctrl->val; 864 break; 865 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: 866 inst->enc_param.intra_qp = ctrl->val; 867 break; 868 case V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE: 869 switch (ctrl->val) { 870 case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED: 871 inst->enc_param.disable_deblk = 1; 872 inst->enc_param.sao_enable = 0; 873 inst->enc_param.lf_cross_slice_boundary_enable = 0; 874 break; 875 case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED: 876 inst->enc_param.disable_deblk = 0; 877 inst->enc_param.sao_enable = 1; 878 inst->enc_param.lf_cross_slice_boundary_enable = 1; 879 break; 880 case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY: 881 inst->enc_param.disable_deblk = 0; 882 inst->enc_param.sao_enable = 1; 883 inst->enc_param.lf_cross_slice_boundary_enable = 0; 884 break; 885 default: 886 return -EINVAL; 887 } 888 break; 889 case V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2: 890 inst->enc_param.beta_offset_div2 = ctrl->val; 891 break; 892 case V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2: 893 inst->enc_param.tc_offset_div2 = ctrl->val; 894 break; 895 case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE: 896 switch (ctrl->val) { 897 case V4L2_MPEG_VIDEO_HEVC_REFRESH_NONE: 898 inst->enc_param.decoding_refresh_type = 0; 899 break; 900 case V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA: 901 inst->enc_param.decoding_refresh_type = 1; 902 break; 903 case V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR: 904 inst->enc_param.decoding_refresh_type = 2; 905 break; 906 default: 907 return -EINVAL; 908 } 909 break; 910 case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD: 911 inst->enc_param.intra_period = ctrl->val; 912 break; 913 case V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU: 914 inst->enc_param.lossless_enable = ctrl->val; 915 break; 916 case V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED: 917 inst->enc_param.const_intra_pred_flag = ctrl->val; 918 break; 919 case V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT: 920 inst->enc_param.wpp_enable = ctrl->val; 921 break; 922 case V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING: 923 inst->enc_param.strong_intra_smooth_enable = ctrl->val; 924 break; 925 case V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1: 926 inst->enc_param.max_num_merge = ctrl->val; 927 break; 928 case V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION: 929 inst->enc_param.tmvp_enable = ctrl->val; 930 break; 931 case V4L2_CID_MPEG_VIDEO_H264_PROFILE: 932 switch (ctrl->val) { 933 case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE: 934 case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE: 935 inst->enc_param.profile = H264_PROFILE_BP; 936 inst->bit_depth = 8; 937 if (ctrl->val == V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) 938 inst->enc_param.constraint_set1_flag = 1; 939 break; 940 case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: 941 inst->enc_param.profile = H264_PROFILE_MP; 942 inst->bit_depth = 8; 943 break; 944 case V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED: 945 inst->enc_param.profile = H264_PROFILE_EXTENDED; 946 inst->bit_depth = 8; 947 break; 948 case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH: 949 inst->enc_param.profile = H264_PROFILE_HP; 950 inst->bit_depth = 8; 951 break; 952 case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10: 953 inst->enc_param.profile = H264_PROFILE_HIGH10; 954 inst->bit_depth = 10; 955 break; 956 case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422: 957 inst->enc_param.profile = H264_PROFILE_HIGH422; 958 inst->bit_depth = 10; 959 break; 960 case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE: 961 inst->enc_param.profile = H264_PROFILE_HIGH444; 962 inst->bit_depth = 10; 963 break; 964 default: 965 return -EINVAL; 966 } 967 break; 968 case V4L2_CID_MPEG_VIDEO_H264_LEVEL: 969 switch (ctrl->val) { 970 case V4L2_MPEG_VIDEO_H264_LEVEL_1_0: 971 inst->enc_param.level = 10; 972 break; 973 case V4L2_MPEG_VIDEO_H264_LEVEL_1B: 974 inst->enc_param.level = 9; 975 break; 976 case V4L2_MPEG_VIDEO_H264_LEVEL_1_1: 977 inst->enc_param.level = 11; 978 break; 979 case V4L2_MPEG_VIDEO_H264_LEVEL_1_2: 980 inst->enc_param.level = 12; 981 break; 982 case V4L2_MPEG_VIDEO_H264_LEVEL_1_3: 983 inst->enc_param.level = 13; 984 break; 985 case V4L2_MPEG_VIDEO_H264_LEVEL_2_0: 986 inst->enc_param.level = 20; 987 break; 988 case V4L2_MPEG_VIDEO_H264_LEVEL_2_1: 989 inst->enc_param.level = 21; 990 break; 991 case V4L2_MPEG_VIDEO_H264_LEVEL_2_2: 992 inst->enc_param.level = 22; 993 break; 994 case V4L2_MPEG_VIDEO_H264_LEVEL_3_0: 995 inst->enc_param.level = 30; 996 break; 997 case V4L2_MPEG_VIDEO_H264_LEVEL_3_1: 998 inst->enc_param.level = 31; 999 break; 1000 case V4L2_MPEG_VIDEO_H264_LEVEL_3_2: 1001 inst->enc_param.level = 32; 1002 break; 1003 case V4L2_MPEG_VIDEO_H264_LEVEL_4_0: 1004 inst->enc_param.level = 40; 1005 break; 1006 case V4L2_MPEG_VIDEO_H264_LEVEL_4_1: 1007 inst->enc_param.level = 41; 1008 break; 1009 case V4L2_MPEG_VIDEO_H264_LEVEL_4_2: 1010 inst->enc_param.level = 42; 1011 break; 1012 case V4L2_MPEG_VIDEO_H264_LEVEL_5_0: 1013 inst->enc_param.level = 50; 1014 break; 1015 case V4L2_MPEG_VIDEO_H264_LEVEL_5_1: 1016 inst->enc_param.level = 51; 1017 break; 1018 default: 1019 return -EINVAL; 1020 } 1021 break; 1022 case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: 1023 inst->enc_param.min_qp_i = ctrl->val; 1024 inst->enc_param.min_qp_p = ctrl->val; 1025 inst->enc_param.min_qp_b = ctrl->val; 1026 break; 1027 case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: 1028 inst->enc_param.max_qp_i = ctrl->val; 1029 inst->enc_param.max_qp_p = ctrl->val; 1030 inst->enc_param.max_qp_b = ctrl->val; 1031 break; 1032 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP: 1033 inst->enc_param.intra_qp = ctrl->val; 1034 break; 1035 case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE: 1036 switch (ctrl->val) { 1037 case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED: 1038 inst->enc_param.disable_deblk = 1; 1039 inst->enc_param.lf_cross_slice_boundary_enable = 1; 1040 break; 1041 case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED: 1042 inst->enc_param.disable_deblk = 0; 1043 inst->enc_param.lf_cross_slice_boundary_enable = 1; 1044 break; 1045 case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY: 1046 inst->enc_param.disable_deblk = 0; 1047 inst->enc_param.lf_cross_slice_boundary_enable = 0; 1048 break; 1049 default: 1050 return -EINVAL; 1051 } 1052 break; 1053 case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA: 1054 inst->enc_param.beta_offset_div2 = ctrl->val; 1055 break; 1056 case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA: 1057 inst->enc_param.tc_offset_div2 = ctrl->val; 1058 break; 1059 case V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM: 1060 inst->enc_param.transform8x8_enable = ctrl->val; 1061 break; 1062 case V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION: 1063 inst->enc_param.const_intra_pred_flag = ctrl->val; 1064 break; 1065 case V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET: 1066 inst->enc_param.chroma_cb_qp_offset = ctrl->val; 1067 inst->enc_param.chroma_cr_qp_offset = ctrl->val; 1068 break; 1069 case V4L2_CID_MPEG_VIDEO_H264_I_PERIOD: 1070 inst->enc_param.intra_period = ctrl->val; 1071 break; 1072 case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: 1073 inst->enc_param.entropy_coding_mode = ctrl->val; 1074 break; 1075 case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: 1076 inst->enc_param.forced_idr_header_enable = ctrl->val; 1077 break; 1078 case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT: 1079 break; 1080 default: 1081 return -EINVAL; 1082 } 1083 1084 return 0; 1085 } 1086 1087 static const struct v4l2_ctrl_ops wave5_vpu_enc_ctrl_ops = { 1088 .s_ctrl = wave5_vpu_enc_s_ctrl, 1089 }; 1090 1091 static int wave5_vpu_enc_queue_setup(struct vb2_queue *q, unsigned int *num_buffers, 1092 unsigned int *num_planes, unsigned int sizes[], 1093 struct device *alloc_devs[]) 1094 { 1095 struct vpu_instance *inst = vb2_get_drv_priv(q); 1096 struct v4l2_pix_format_mplane inst_format = 1097 (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt; 1098 unsigned int i; 1099 1100 dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__, 1101 *num_buffers, *num_planes, q->type); 1102 1103 if (*num_planes) { 1104 if (inst_format.num_planes != *num_planes) 1105 return -EINVAL; 1106 1107 for (i = 0; i < *num_planes; i++) { 1108 if (sizes[i] < inst_format.plane_fmt[i].sizeimage) 1109 return -EINVAL; 1110 } 1111 } else { 1112 *num_planes = inst_format.num_planes; 1113 for (i = 0; i < *num_planes; i++) { 1114 sizes[i] = inst_format.plane_fmt[i].sizeimage; 1115 dev_dbg(inst->dev->dev, "%s: size[%u]: %u\n", __func__, i, sizes[i]); 1116 } 1117 } 1118 1119 dev_dbg(inst->dev->dev, "%s: size: %u\n", __func__, sizes[0]); 1120 1121 return 0; 1122 } 1123 1124 static void wave5_vpu_enc_buf_queue(struct vb2_buffer *vb) 1125 { 1126 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 1127 struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); 1128 struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; 1129 1130 dev_dbg(inst->dev->dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n", 1131 __func__, vb->type, vb->index, vb2_plane_size(&vbuf->vb2_buf, 0), 1132 vb2_plane_size(&vbuf->vb2_buf, 1), vb2_plane_size(&vbuf->vb2_buf, 2)); 1133 1134 if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) 1135 vbuf->sequence = inst->queued_src_buf_num++; 1136 else 1137 vbuf->sequence = inst->queued_dst_buf_num++; 1138 1139 v4l2_m2m_buf_queue(m2m_ctx, vbuf); 1140 } 1141 1142 static int wave5_set_enc_openparam(struct enc_open_param *open_param, 1143 struct vpu_instance *inst) 1144 { 1145 struct enc_wave_param input = inst->enc_param; 1146 const struct v4l2_format_info *info; 1147 u32 num_ctu_row = ALIGN(inst->dst_fmt.height, 64) / 64; 1148 u32 num_mb_row = ALIGN(inst->dst_fmt.height, 16) / 16; 1149 1150 info = v4l2_format_info(inst->src_fmt.pixelformat); 1151 if (!info) 1152 return -EINVAL; 1153 1154 if (info->hdiv == 2 && info->vdiv == 1) 1155 open_param->src_format = FORMAT_422; 1156 else 1157 open_param->src_format = FORMAT_420; 1158 1159 switch (info->format) { 1160 case V4L2_PIX_FMT_YUYV: 1161 open_param->packed_format = PACKED_YUYV; 1162 break; 1163 case V4L2_PIX_FMT_YVYU: 1164 open_param->packed_format = PACKED_YVYU; 1165 break; 1166 case V4L2_PIX_FMT_UYVY: 1167 open_param->packed_format = PACKED_UYVY; 1168 break; 1169 case V4L2_PIX_FMT_VYUY: 1170 open_param->packed_format = PACKED_VYUY; 1171 break; 1172 default: 1173 break; 1174 } 1175 open_param->wave_param.gop_preset_idx = PRESET_IDX_IPP_SINGLE; 1176 open_param->wave_param.hvs_qp_scale = 2; 1177 open_param->wave_param.hvs_max_delta_qp = 10; 1178 open_param->wave_param.skip_intra_trans = 1; 1179 open_param->wave_param.intra_nx_n_enable = 1; 1180 open_param->wave_param.nr_intra_weight_y = 7; 1181 open_param->wave_param.nr_intra_weight_cb = 7; 1182 open_param->wave_param.nr_intra_weight_cr = 7; 1183 open_param->wave_param.nr_inter_weight_y = 4; 1184 open_param->wave_param.nr_inter_weight_cb = 4; 1185 open_param->wave_param.nr_inter_weight_cr = 4; 1186 open_param->wave_param.rdo_skip = 1; 1187 open_param->wave_param.lambda_scaling_enable = 1; 1188 1189 open_param->line_buf_int_en = true; 1190 open_param->pic_width = inst->conf_win.width; 1191 open_param->pic_height = inst->conf_win.height; 1192 open_param->frame_rate_info = inst->frame_rate; 1193 open_param->rc_enable = inst->rc_enable; 1194 if (inst->rc_enable) { 1195 open_param->wave_param.initial_rc_qp = -1; 1196 open_param->wave_param.rc_weight_param = 16; 1197 open_param->wave_param.rc_weight_buf = 128; 1198 } 1199 open_param->wave_param.mb_level_rc_enable = input.mb_level_rc_enable; 1200 open_param->wave_param.cu_level_rc_enable = input.cu_level_rc_enable; 1201 open_param->wave_param.hvs_qp_enable = input.hvs_qp_enable; 1202 open_param->bit_rate = inst->bit_rate; 1203 open_param->vbv_buffer_size = inst->vbv_buf_size; 1204 if (inst->rc_mode == 0) 1205 open_param->vbv_buffer_size = 3000; 1206 open_param->wave_param.profile = input.profile; 1207 open_param->wave_param.en_still_picture = input.en_still_picture; 1208 open_param->wave_param.level = input.level; 1209 open_param->wave_param.internal_bit_depth = inst->bit_depth; 1210 open_param->wave_param.intra_qp = input.intra_qp; 1211 open_param->wave_param.min_qp_i = input.min_qp_i; 1212 open_param->wave_param.max_qp_i = input.max_qp_i; 1213 open_param->wave_param.min_qp_p = input.min_qp_p; 1214 open_param->wave_param.max_qp_p = input.max_qp_p; 1215 open_param->wave_param.min_qp_b = input.min_qp_b; 1216 open_param->wave_param.max_qp_b = input.max_qp_b; 1217 open_param->wave_param.disable_deblk = input.disable_deblk; 1218 open_param->wave_param.lf_cross_slice_boundary_enable = 1219 input.lf_cross_slice_boundary_enable; 1220 open_param->wave_param.tc_offset_div2 = input.tc_offset_div2; 1221 open_param->wave_param.beta_offset_div2 = input.beta_offset_div2; 1222 open_param->wave_param.decoding_refresh_type = input.decoding_refresh_type; 1223 open_param->wave_param.intra_period = input.intra_period; 1224 open_param->wave_param.bg_detection = input.bg_detection; 1225 if (inst->std == W_HEVC_ENC) { 1226 if (input.intra_period == 0) { 1227 open_param->wave_param.decoding_refresh_type = DEC_REFRESH_TYPE_IDR; 1228 open_param->wave_param.intra_period = input.avc_idr_period; 1229 } 1230 } else { 1231 open_param->wave_param.constraint_set1_flag = input.constraint_set1_flag; 1232 open_param->wave_param.avc_idr_period = input.avc_idr_period; 1233 } 1234 open_param->wave_param.entropy_coding_mode = input.entropy_coding_mode; 1235 open_param->wave_param.lossless_enable = input.lossless_enable; 1236 open_param->wave_param.const_intra_pred_flag = input.const_intra_pred_flag; 1237 open_param->wave_param.wpp_enable = input.wpp_enable; 1238 open_param->wave_param.strong_intra_smooth_enable = input.strong_intra_smooth_enable; 1239 open_param->wave_param.max_num_merge = input.max_num_merge; 1240 open_param->wave_param.tmvp_enable = input.tmvp_enable; 1241 open_param->wave_param.transform8x8_enable = input.transform8x8_enable; 1242 open_param->wave_param.chroma_cb_qp_offset = input.chroma_cb_qp_offset; 1243 open_param->wave_param.chroma_cr_qp_offset = input.chroma_cr_qp_offset; 1244 open_param->wave_param.independ_slice_mode = input.independ_slice_mode; 1245 open_param->wave_param.independ_slice_mode_arg = input.independ_slice_mode_arg; 1246 open_param->wave_param.avc_slice_mode = input.avc_slice_mode; 1247 open_param->wave_param.avc_slice_arg = input.avc_slice_arg; 1248 open_param->wave_param.intra_mb_refresh_mode = input.intra_mb_refresh_mode; 1249 if (input.intra_mb_refresh_mode != REFRESH_MB_MODE_NONE) { 1250 if (num_mb_row >= input.intra_mb_refresh_arg) 1251 open_param->wave_param.intra_mb_refresh_arg = 1252 num_mb_row / input.intra_mb_refresh_arg; 1253 else 1254 open_param->wave_param.intra_mb_refresh_arg = num_mb_row; 1255 } 1256 open_param->wave_param.intra_refresh_mode = input.intra_refresh_mode; 1257 if (input.intra_refresh_mode != 0) { 1258 if (num_ctu_row >= input.intra_refresh_arg) 1259 open_param->wave_param.intra_refresh_arg = 1260 num_ctu_row / input.intra_refresh_arg; 1261 else 1262 open_param->wave_param.intra_refresh_arg = num_ctu_row; 1263 } 1264 open_param->wave_param.forced_idr_header_enable = input.forced_idr_header_enable; 1265 1266 return 0; 1267 } 1268 1269 static int initialize_sequence(struct vpu_instance *inst) 1270 { 1271 struct enc_initial_info initial_info; 1272 struct v4l2_ctrl *ctrl; 1273 int ret; 1274 1275 ret = wave5_vpu_enc_issue_seq_init(inst); 1276 if (ret) { 1277 dev_err(inst->dev->dev, "%s: wave5_vpu_enc_issue_seq_init, fail: %d\n", 1278 __func__, ret); 1279 return ret; 1280 } 1281 1282 if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) < 0) { 1283 dev_err(inst->dev->dev, "%s: wave5_vpu_wait_interrupt failed\n", __func__); 1284 return -EINVAL; 1285 } 1286 1287 ret = wave5_vpu_enc_complete_seq_init(inst, &initial_info); 1288 if (ret) 1289 return ret; 1290 1291 dev_dbg(inst->dev->dev, "%s: min_frame_buffer: %u | min_source_buffer: %u\n", 1292 __func__, initial_info.min_frame_buffer_count, 1293 initial_info.min_src_frame_count); 1294 inst->min_src_buf_count = initial_info.min_src_frame_count + 1295 WAVE521_COMMAND_QUEUE_DEPTH; 1296 1297 ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, 1298 V4L2_CID_MIN_BUFFERS_FOR_OUTPUT); 1299 if (ctrl) 1300 v4l2_ctrl_s_ctrl(ctrl, inst->min_src_buf_count); 1301 1302 inst->fbc_buf_count = initial_info.min_frame_buffer_count; 1303 1304 return 0; 1305 } 1306 1307 static int prepare_fb(struct vpu_instance *inst) 1308 { 1309 u32 fb_stride = ALIGN(inst->dst_fmt.width, 32); 1310 u32 fb_height = ALIGN(inst->dst_fmt.height, 32); 1311 int i, ret = 0; 1312 1313 for (i = 0; i < inst->fbc_buf_count; i++) { 1314 u32 luma_size = fb_stride * fb_height; 1315 u32 chroma_size = ALIGN(fb_stride / 2, 16) * fb_height; 1316 1317 inst->frame_vbuf[i].size = luma_size + chroma_size; 1318 ret = wave5_vdi_allocate_dma_memory(inst->dev, &inst->frame_vbuf[i]); 1319 if (ret < 0) { 1320 dev_err(inst->dev->dev, "%s: failed to allocate FBC buffer %zu\n", 1321 __func__, inst->frame_vbuf[i].size); 1322 goto free_buffers; 1323 } 1324 1325 inst->frame_buf[i].buf_y = inst->frame_vbuf[i].daddr; 1326 inst->frame_buf[i].buf_cb = (dma_addr_t)-1; 1327 inst->frame_buf[i].buf_cr = (dma_addr_t)-1; 1328 inst->frame_buf[i].update_fb_info = true; 1329 inst->frame_buf[i].size = inst->frame_vbuf[i].size; 1330 } 1331 1332 ret = wave5_vpu_enc_register_frame_buffer(inst, inst->fbc_buf_count, fb_stride, 1333 fb_height, COMPRESSED_FRAME_MAP); 1334 if (ret) { 1335 dev_err(inst->dev->dev, 1336 "%s: wave5_vpu_enc_register_frame_buffer, fail: %d\n", 1337 __func__, ret); 1338 goto free_buffers; 1339 } 1340 1341 return 0; 1342 free_buffers: 1343 for (i = 0; i < inst->fbc_buf_count; i++) 1344 wave5_vpu_dec_reset_framebuffer(inst, i); 1345 return ret; 1346 } 1347 1348 static int wave5_vpu_enc_start_streaming(struct vb2_queue *q, unsigned int count) 1349 { 1350 struct vpu_instance *inst = vb2_get_drv_priv(q); 1351 struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; 1352 int ret = 0; 1353 1354 pm_runtime_resume_and_get(inst->dev->dev); 1355 v4l2_m2m_update_start_streaming_state(m2m_ctx, q); 1356 1357 if (inst->state == VPU_INST_STATE_NONE && q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { 1358 struct enc_open_param open_param; 1359 1360 memset(&open_param, 0, sizeof(struct enc_open_param)); 1361 1362 ret = wave5_set_enc_openparam(&open_param, inst); 1363 if (ret) { 1364 dev_dbg(inst->dev->dev, "%s: wave5_set_enc_openparam, fail: %d\n", 1365 __func__, ret); 1366 goto return_buffers; 1367 } 1368 1369 ret = wave5_vpu_enc_open(inst, &open_param); 1370 if (ret) { 1371 dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_open, fail: %d\n", 1372 __func__, ret); 1373 goto return_buffers; 1374 } 1375 1376 if (inst->mirror_direction) { 1377 wave5_vpu_enc_give_command(inst, ENABLE_MIRRORING, NULL); 1378 wave5_vpu_enc_give_command(inst, SET_MIRROR_DIRECTION, 1379 &inst->mirror_direction); 1380 } 1381 if (inst->rot_angle) { 1382 wave5_vpu_enc_give_command(inst, ENABLE_ROTATION, NULL); 1383 wave5_vpu_enc_give_command(inst, SET_ROTATION_ANGLE, &inst->rot_angle); 1384 } 1385 1386 ret = switch_state(inst, VPU_INST_STATE_OPEN); 1387 if (ret) 1388 goto return_buffers; 1389 } 1390 if (inst->state == VPU_INST_STATE_OPEN && 1391 (m2m_ctx->cap_q_ctx.q.streaming || q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)) { 1392 ret = initialize_sequence(inst); 1393 if (ret) { 1394 dev_warn(inst->dev->dev, "Sequence not found: %d\n", ret); 1395 goto return_buffers; 1396 } 1397 ret = switch_state(inst, VPU_INST_STATE_INIT_SEQ); 1398 if (ret) 1399 goto return_buffers; 1400 /* 1401 * The sequence must be analyzed first to calculate the proper 1402 * size of the auxiliary buffers. 1403 */ 1404 ret = prepare_fb(inst); 1405 if (ret) { 1406 dev_warn(inst->dev->dev, "Framebuffer preparation, fail: %d\n", ret); 1407 goto return_buffers; 1408 } 1409 1410 ret = switch_state(inst, VPU_INST_STATE_PIC_RUN); 1411 } 1412 if (ret) 1413 goto return_buffers; 1414 1415 pm_runtime_put_autosuspend(inst->dev->dev); 1416 return 0; 1417 return_buffers: 1418 wave5_return_bufs(q, VB2_BUF_STATE_QUEUED); 1419 pm_runtime_put_autosuspend(inst->dev->dev); 1420 return ret; 1421 } 1422 1423 static void streamoff_output(struct vpu_instance *inst, struct vb2_queue *q) 1424 { 1425 struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; 1426 struct vb2_v4l2_buffer *buf; 1427 1428 while ((buf = v4l2_m2m_src_buf_remove(m2m_ctx))) { 1429 dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", 1430 __func__, buf->vb2_buf.type, buf->vb2_buf.index); 1431 v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); 1432 } 1433 } 1434 1435 static void streamoff_capture(struct vpu_instance *inst, struct vb2_queue *q) 1436 { 1437 struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; 1438 struct vb2_v4l2_buffer *buf; 1439 1440 while ((buf = v4l2_m2m_dst_buf_remove(m2m_ctx))) { 1441 dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", 1442 __func__, buf->vb2_buf.type, buf->vb2_buf.index); 1443 vb2_set_plane_payload(&buf->vb2_buf, 0, 0); 1444 v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); 1445 } 1446 1447 v4l2_m2m_clear_state(m2m_ctx); 1448 } 1449 1450 static void wave5_vpu_enc_stop_streaming(struct vb2_queue *q) 1451 { 1452 struct vpu_instance *inst = vb2_get_drv_priv(q); 1453 bool check_cmd = true; 1454 1455 /* 1456 * Note that we don't need m2m_ctx->next_buf_last for this driver, so we 1457 * don't call v4l2_m2m_update_stop_streaming_state(). 1458 */ 1459 1460 dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); 1461 pm_runtime_resume_and_get(inst->dev->dev); 1462 1463 if (wave5_vpu_both_queues_are_streaming(inst)) 1464 switch_state(inst, VPU_INST_STATE_STOP); 1465 1466 while (check_cmd) { 1467 struct queue_status_info q_status; 1468 struct enc_output_info enc_output_info; 1469 1470 wave5_vpu_enc_give_command(inst, ENC_GET_QUEUE_STATUS, &q_status); 1471 1472 if (q_status.report_queue_count == 0) 1473 break; 1474 1475 if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) < 0) 1476 break; 1477 1478 if (wave5_vpu_enc_get_output_info(inst, &enc_output_info)) 1479 dev_dbg(inst->dev->dev, "Getting encoding results from fw, fail\n"); 1480 } 1481 1482 if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) 1483 streamoff_output(inst, q); 1484 else 1485 streamoff_capture(inst, q); 1486 1487 pm_runtime_put_autosuspend(inst->dev->dev); 1488 } 1489 1490 static const struct vb2_ops wave5_vpu_enc_vb2_ops = { 1491 .queue_setup = wave5_vpu_enc_queue_setup, 1492 .buf_queue = wave5_vpu_enc_buf_queue, 1493 .start_streaming = wave5_vpu_enc_start_streaming, 1494 .stop_streaming = wave5_vpu_enc_stop_streaming, 1495 }; 1496 1497 static void wave5_set_default_format(struct v4l2_pix_format_mplane *src_fmt, 1498 struct v4l2_pix_format_mplane *dst_fmt) 1499 { 1500 src_fmt->pixelformat = enc_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; 1501 wave5_update_pix_fmt(src_fmt, VPU_FMT_TYPE_RAW, 1502 W5_DEF_ENC_PIC_WIDTH, W5_DEF_ENC_PIC_HEIGHT, 1503 &enc_frmsize[VPU_FMT_TYPE_RAW]); 1504 1505 dst_fmt->pixelformat = enc_fmt_list[VPU_FMT_TYPE_CODEC][0].v4l2_pix_fmt; 1506 wave5_update_pix_fmt(dst_fmt, VPU_FMT_TYPE_CODEC, 1507 W5_DEF_ENC_PIC_WIDTH, W5_DEF_ENC_PIC_HEIGHT, 1508 &enc_frmsize[VPU_FMT_TYPE_CODEC]); 1509 } 1510 1511 static int wave5_vpu_enc_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) 1512 { 1513 return wave5_vpu_queue_init(priv, src_vq, dst_vq, &wave5_vpu_enc_vb2_ops); 1514 } 1515 1516 static const struct vpu_instance_ops wave5_vpu_enc_inst_ops = { 1517 .finish_process = wave5_vpu_enc_finish_encode, 1518 }; 1519 1520 static void wave5_vpu_enc_device_run(void *priv) 1521 { 1522 struct vpu_instance *inst = priv; 1523 struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; 1524 u32 fail_res = 0; 1525 int ret = 0; 1526 1527 pm_runtime_resume_and_get(inst->dev->dev); 1528 switch (inst->state) { 1529 case VPU_INST_STATE_PIC_RUN: 1530 ret = start_encode(inst, &fail_res); 1531 if (ret) { 1532 if (ret == -EINVAL) 1533 dev_err(inst->dev->dev, 1534 "Frame encoding on m2m context (%p), fail: %d (res: %d)\n", 1535 m2m_ctx, ret, fail_res); 1536 else if (ret == -EAGAIN) 1537 dev_dbg(inst->dev->dev, "Missing buffers for encode, try again\n"); 1538 break; 1539 } 1540 dev_dbg(inst->dev->dev, "%s: leave with active job", __func__); 1541 pm_runtime_put_autosuspend(inst->dev->dev); 1542 return; 1543 default: 1544 WARN(1, "Execution of a job in state %s is invalid.\n", 1545 state_to_str(inst->state)); 1546 break; 1547 } 1548 dev_dbg(inst->dev->dev, "%s: leave and finish job", __func__); 1549 pm_runtime_put_autosuspend(inst->dev->dev); 1550 v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); 1551 } 1552 1553 static int wave5_vpu_enc_job_ready(void *priv) 1554 { 1555 struct vpu_instance *inst = priv; 1556 struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; 1557 1558 switch (inst->state) { 1559 case VPU_INST_STATE_NONE: 1560 dev_dbg(inst->dev->dev, "Encoder must be open to start queueing M2M jobs!\n"); 1561 return false; 1562 case VPU_INST_STATE_PIC_RUN: 1563 if (m2m_ctx->is_draining || v4l2_m2m_num_src_bufs_ready(m2m_ctx)) { 1564 dev_dbg(inst->dev->dev, "Encoder ready for a job, state: %s\n", 1565 state_to_str(inst->state)); 1566 return true; 1567 } 1568 fallthrough; 1569 default: 1570 dev_dbg(inst->dev->dev, 1571 "Encoder not ready for a job, state: %s, %s draining, %d src bufs ready\n", 1572 state_to_str(inst->state), m2m_ctx->is_draining ? "is" : "is not", 1573 v4l2_m2m_num_src_bufs_ready(m2m_ctx)); 1574 break; 1575 } 1576 return false; 1577 } 1578 1579 static const struct v4l2_m2m_ops wave5_vpu_enc_m2m_ops = { 1580 .device_run = wave5_vpu_enc_device_run, 1581 .job_ready = wave5_vpu_enc_job_ready, 1582 }; 1583 1584 static int wave5_vpu_open_enc(struct file *filp) 1585 { 1586 struct video_device *vdev = video_devdata(filp); 1587 struct vpu_device *dev = video_drvdata(filp); 1588 struct vpu_instance *inst = NULL; 1589 struct v4l2_ctrl_handler *v4l2_ctrl_hdl; 1590 int ret = 0; 1591 1592 inst = kzalloc_obj(*inst); 1593 if (!inst) 1594 return -ENOMEM; 1595 v4l2_ctrl_hdl = &inst->v4l2_ctrl_hdl; 1596 1597 inst->dev = dev; 1598 inst->type = VPU_INST_TYPE_ENC; 1599 inst->ops = &wave5_vpu_enc_inst_ops; 1600 1601 inst->codec_info = kzalloc_obj(*inst->codec_info); 1602 if (!inst->codec_info) { 1603 kfree(inst); 1604 return -ENOMEM; 1605 } 1606 1607 v4l2_fh_init(&inst->v4l2_fh, vdev); 1608 v4l2_fh_add(&inst->v4l2_fh, filp); 1609 1610 INIT_LIST_HEAD(&inst->list); 1611 1612 inst->v4l2_m2m_dev = inst->dev->v4l2_m2m_enc_dev; 1613 inst->v4l2_fh.m2m_ctx = 1614 v4l2_m2m_ctx_init(inst->v4l2_m2m_dev, inst, wave5_vpu_enc_queue_init); 1615 if (IS_ERR(inst->v4l2_fh.m2m_ctx)) { 1616 ret = PTR_ERR(inst->v4l2_fh.m2m_ctx); 1617 goto cleanup_inst; 1618 } 1619 v4l2_m2m_set_src_buffered(inst->v4l2_fh.m2m_ctx, true); 1620 1621 v4l2_ctrl_handler_init(v4l2_ctrl_hdl, 50); 1622 v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1623 V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, 1624 V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, 0, 1625 V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN); 1626 v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1627 V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, 1628 V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, 0, 1629 V4L2_MPEG_VIDEO_HEVC_LEVEL_1); 1630 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1631 V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP, 1632 0, 63, 1, 8); 1633 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1634 V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP, 1635 0, 63, 1, 51); 1636 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1637 V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP, 1638 0, 63, 1, 30); 1639 v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1640 V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE, 1641 V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY, 0, 1642 V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED); 1643 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1644 V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2, 1645 -6, 6, 1, 0); 1646 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1647 V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2, 1648 -6, 6, 1, 0); 1649 v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1650 V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE, 1651 V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR, 0, 1652 V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR); 1653 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1654 V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD, 1655 0, 2047, 1, 0); 1656 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1657 V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU, 1658 0, 1, 1, 0); 1659 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1660 V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED, 1661 0, 1, 1, 0); 1662 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1663 V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT, 1664 0, 1, 1, 0); 1665 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1666 V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING, 1667 0, 1, 1, 1); 1668 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1669 V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1, 1670 1, 2, 1, 2); 1671 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1672 V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION, 1673 0, 1, 1, 1); 1674 1675 v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1676 V4L2_CID_MPEG_VIDEO_H264_PROFILE, 1677 V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE, 0, 1678 V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE); 1679 v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1680 V4L2_CID_MPEG_VIDEO_H264_LEVEL, 1681 V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 0, 1682 V4L2_MPEG_VIDEO_H264_LEVEL_1_0); 1683 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1684 V4L2_CID_MPEG_VIDEO_H264_MIN_QP, 1685 0, 63, 1, 8); 1686 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1687 V4L2_CID_MPEG_VIDEO_H264_MAX_QP, 1688 0, 63, 1, 51); 1689 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1690 V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, 1691 0, 63, 1, 30); 1692 v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1693 V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE, 1694 V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY, 0, 1695 V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED); 1696 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1697 V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA, 1698 -6, 6, 1, 0); 1699 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1700 V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA, 1701 -6, 6, 1, 0); 1702 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1703 V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM, 1704 0, 1, 1, 0); 1705 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1706 V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION, 1707 0, 1, 1, 0); 1708 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1709 V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET, 1710 -12, 12, 1, 0); 1711 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1712 V4L2_CID_MPEG_VIDEO_H264_I_PERIOD, 1713 0, 2047, 1, 0); 1714 v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1715 V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE, 1716 V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, 0, 1717 V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC); 1718 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1719 V4L2_CID_MPEG_VIDEO_AU_DELIMITER, 1720 0, 1, 1, 1); 1721 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1722 V4L2_CID_MPEG_VIDEO_BACKGROUND_DETECTION, 1723 0, 1, 1, 0); 1724 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1725 V4L2_CID_HFLIP, 1726 0, 1, 1, 0); 1727 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1728 V4L2_CID_VFLIP, 1729 0, 1, 1, 0); 1730 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1731 V4L2_CID_ROTATE, 1732 0, 270, 90, 0); 1733 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1734 V4L2_CID_MPEG_VIDEO_VBV_SIZE, 1735 10, 3000, 1, 1000); 1736 v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1737 V4L2_CID_MPEG_VIDEO_BITRATE_MODE, 1738 V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, 0, 1739 V4L2_MPEG_VIDEO_BITRATE_MODE_CBR); 1740 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1741 V4L2_CID_MPEG_VIDEO_BITRATE, 1742 0, 700000000, 1, 0); 1743 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1744 V4L2_CID_MPEG_VIDEO_GOP_SIZE, 1745 0, 2047, 1, 0); 1746 v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1747 V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE, 1748 V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB, 0, 1749 V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE); 1750 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1751 V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, 1752 0, 0xFFFF, 1, 0); 1753 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1754 V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE, 1755 0, 1, 1, 0); 1756 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1757 V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE, 1758 0, 1, 1, 0); 1759 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1760 V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 1); 1761 v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, 1762 V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR, 1763 0, 1, 1, 0); 1764 1765 if (v4l2_ctrl_hdl->error) { 1766 ret = -ENODEV; 1767 goto cleanup_inst; 1768 } 1769 1770 inst->v4l2_fh.ctrl_handler = v4l2_ctrl_hdl; 1771 v4l2_ctrl_handler_setup(v4l2_ctrl_hdl); 1772 1773 wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt); 1774 inst->conf_win.width = inst->dst_fmt.width; 1775 inst->conf_win.height = inst->dst_fmt.height; 1776 inst->colorspace = V4L2_COLORSPACE_REC709; 1777 inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1778 inst->quantization = V4L2_QUANTIZATION_DEFAULT; 1779 inst->xfer_func = V4L2_XFER_FUNC_DEFAULT; 1780 inst->frame_rate = 30; 1781 1782 init_completion(&inst->irq_done); 1783 ret = wave5_kfifo_alloc(inst); 1784 if (ret) { 1785 dev_err(inst->dev->dev, "failed to allocate fifo\n"); 1786 goto cleanup_inst; 1787 } 1788 1789 inst->id = ida_alloc(&inst->dev->inst_ida, GFP_KERNEL); 1790 if (inst->id < 0) { 1791 dev_warn(inst->dev->dev, "Allocating instance ID, fail: %d\n", inst->id); 1792 ret = inst->id; 1793 goto cleanup_inst; 1794 } 1795 1796 wave5_vdi_allocate_sram(inst->dev); 1797 1798 ret = mutex_lock_interruptible(&dev->dev_lock); 1799 if (ret) 1800 goto cleanup_inst; 1801 1802 list_add_tail(&inst->list, &dev->instances); 1803 1804 mutex_unlock(&dev->dev_lock); 1805 1806 return 0; 1807 1808 cleanup_inst: 1809 wave5_cleanup_instance(inst, filp); 1810 return ret; 1811 } 1812 1813 static int wave5_vpu_enc_release(struct file *filp) 1814 { 1815 return wave5_vpu_release_device(filp, wave5_vpu_enc_close, "encoder"); 1816 } 1817 1818 static const struct v4l2_file_operations wave5_vpu_enc_fops = { 1819 .owner = THIS_MODULE, 1820 .open = wave5_vpu_open_enc, 1821 .release = wave5_vpu_enc_release, 1822 .unlocked_ioctl = video_ioctl2, 1823 .poll = v4l2_m2m_fop_poll, 1824 .mmap = v4l2_m2m_fop_mmap, 1825 }; 1826 1827 int wave5_vpu_enc_register_device(struct vpu_device *dev) 1828 { 1829 struct video_device *vdev_enc; 1830 int ret; 1831 1832 vdev_enc = devm_kzalloc(dev->v4l2_dev.dev, sizeof(*vdev_enc), GFP_KERNEL); 1833 if (!vdev_enc) 1834 return -ENOMEM; 1835 1836 dev->v4l2_m2m_enc_dev = v4l2_m2m_init(&wave5_vpu_enc_m2m_ops); 1837 if (IS_ERR(dev->v4l2_m2m_enc_dev)) { 1838 ret = PTR_ERR(dev->v4l2_m2m_enc_dev); 1839 dev_err(dev->dev, "v4l2_m2m_init, fail: %d\n", ret); 1840 return -EINVAL; 1841 } 1842 1843 dev->video_dev_enc = vdev_enc; 1844 1845 strscpy(vdev_enc->name, VPU_ENC_DEV_NAME, sizeof(vdev_enc->name)); 1846 vdev_enc->fops = &wave5_vpu_enc_fops; 1847 vdev_enc->ioctl_ops = &wave5_vpu_enc_ioctl_ops; 1848 vdev_enc->release = video_device_release_empty; 1849 vdev_enc->v4l2_dev = &dev->v4l2_dev; 1850 vdev_enc->vfl_dir = VFL_DIR_M2M; 1851 vdev_enc->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING; 1852 vdev_enc->lock = &dev->dev_lock; 1853 1854 ret = video_register_device(vdev_enc, VFL_TYPE_VIDEO, -1); 1855 if (ret) 1856 return ret; 1857 1858 video_set_drvdata(vdev_enc, dev); 1859 1860 return 0; 1861 } 1862 1863 void wave5_vpu_enc_unregister_device(struct vpu_device *dev) 1864 { 1865 video_unregister_device(dev->video_dev_enc); 1866 if (dev->v4l2_m2m_enc_dev) 1867 v4l2_m2m_release(dev->v4l2_m2m_enc_dev); 1868 } 1869