1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023-2024 Intel Corporation 4 */ 5 6 #ifndef _XE_GT_SRIOV_VF_TYPES_H_ 7 #define _XE_GT_SRIOV_VF_TYPES_H_ 8 9 #include <linux/types.h> 10 #include "xe_uc_fw_types.h" 11 12 /** 13 * struct xe_gt_sriov_vf_selfconfig - VF configuration data. 14 */ 15 struct xe_gt_sriov_vf_selfconfig { 16 /** @ggtt_base: assigned base offset of the GGTT region. */ 17 u64 ggtt_base; 18 /** @ggtt_size: assigned size of the GGTT region. */ 19 u64 ggtt_size; 20 /** @ggtt_shift: difference in ggtt_base on last migration */ 21 s64 ggtt_shift; 22 /** @lmem_size: assigned size of the LMEM. */ 23 u64 lmem_size; 24 /** @num_ctxs: assigned number of GuC submission context IDs. */ 25 u16 num_ctxs; 26 /** @num_dbs: assigned number of GuC doorbells IDs. */ 27 u16 num_dbs; 28 }; 29 30 /** 31 * struct xe_gt_sriov_vf_runtime - VF runtime data. 32 */ 33 struct xe_gt_sriov_vf_runtime { 34 /** @gmdid: cached value of the GDMID register. */ 35 u32 gmdid; 36 /** @regs_size: size of runtime register array. */ 37 u32 regs_size; 38 /** @num_regs: number of runtime registers in the array. */ 39 u32 num_regs; 40 /** @regs: pointer to array of register offset/value pairs. */ 41 struct vf_runtime_reg { 42 /** @regs.offset: register offset. */ 43 u32 offset; 44 /** @regs.value: register value. */ 45 u32 value; 46 } *regs; 47 }; 48 49 /** 50 * struct xe_gt_sriov_vf - GT level VF virtualization data. 51 */ 52 struct xe_gt_sriov_vf { 53 /** @wanted_guc_version: minimum wanted GuC ABI version. */ 54 struct xe_uc_fw_version wanted_guc_version; 55 /** @guc_version: negotiated GuC ABI version. */ 56 struct xe_uc_fw_version guc_version; 57 /** @self_config: resource configurations. */ 58 struct xe_gt_sriov_vf_selfconfig self_config; 59 /** @runtime: runtime data retrieved from the PF. */ 60 struct xe_gt_sriov_vf_runtime runtime; 61 }; 62 63 #endif 64