1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef DEBUG_HTT_STATS_H
8 #define DEBUG_HTT_STATS_H
9
10 #define ATH12K_HTT_STATS_BUF_SIZE (1024 * 512)
11 #define ATH12K_HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0)
12 #define ATH12K_HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32)
13 #define ATH12K_HTT_STATS_MAGIC_VALUE 0xF0F0F0F0
14 #define ATH12K_HTT_STATS_SUBTYPE_MAX 16
15 #define ATH12K_HTT_MAX_STRING_LEN 256
16
17 #define ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx) ((_idx) & 0x1f)
18 #define ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx) ((_idx) & 0x3f)
19 #define ATH12K_HTT_STATS_RESET_BITMAP32_BIT(_idx) (1 << \
20 ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx))
21 #define ATH12K_HTT_STATS_RESET_BITMAP64_BIT(_idx) (1 << \
22 ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx))
23
24 void ath12k_debugfs_htt_stats_register(struct ath12k *ar);
25
26 #ifdef CONFIG_ATH12K_DEBUGFS
27 void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab,
28 struct sk_buff *skb);
29 #else /* CONFIG_ATH12K_DEBUGFS */
ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base * ab,struct sk_buff * skb)30 static inline void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab,
31 struct sk_buff *skb)
32 {
33 }
34 #endif
35
36 /**
37 * DOC: target -> host extended statistics upload
38 *
39 * The following field definitions describe the format of the HTT
40 * target to host stats upload confirmation message.
41 * The message contains a cookie echoed from the HTT host->target stats
42 * upload request, which identifies which request the confirmation is
43 * for, and a single stats can span over multiple HTT stats indication
44 * due to the HTT message size limitation so every HTT ext stats
45 * indication will have tag-length-value stats information elements.
46 * The tag-length header for each HTT stats IND message also includes a
47 * status field, to indicate whether the request for the stat type in
48 * question was fully met, partially met, unable to be met, or invalid
49 * (if the stat type in question is disabled in the target).
50 * A Done bit 1's indicate the end of the of stats info elements.
51 *
52 *
53 * |31 16|15 12|11|10 8|7 5|4 0|
54 * |--------------------------------------------------------------|
55 * | reserved | msg type |
56 * |--------------------------------------------------------------|
57 * | cookie LSBs |
58 * |--------------------------------------------------------------|
59 * | cookie MSBs |
60 * |--------------------------------------------------------------|
61 * | stats entry length | rsvd | D| S | stat type |
62 * |--------------------------------------------------------------|
63 * | type-specific stats info |
64 * | (see debugfs_htt_stats.h) |
65 * |--------------------------------------------------------------|
66 * Header fields:
67 * - MSG_TYPE
68 * Bits 7:0
69 * Purpose: Identifies this is a extended statistics upload confirmation
70 * message.
71 * Value: 0x1c
72 * - COOKIE_LSBS
73 * Bits 31:0
74 * Purpose: Provide a mechanism to match a target->host stats confirmation
75 * message with its preceding host->target stats request message.
76 * Value: MSBs of the opaque cookie specified by the host-side requestor
77 * - COOKIE_MSBS
78 * Bits 31:0
79 * Purpose: Provide a mechanism to match a target->host stats confirmation
80 * message with its preceding host->target stats request message.
81 * Value: MSBs of the opaque cookie specified by the host-side requestor
82 *
83 * Stats Information Element tag-length header fields:
84 * - STAT_TYPE
85 * Bits 7:0
86 * Purpose: identifies the type of statistics info held in the
87 * following information element
88 * Value: ath12k_dbg_htt_ext_stats_type
89 * - STATUS
90 * Bits 10:8
91 * Purpose: indicate whether the requested stats are present
92 * Value:
93 * 0 -> The requested stats have been delivered in full
94 * 1 -> The requested stats have been delivered in part
95 * 2 -> The requested stats could not be delivered (error case)
96 * 3 -> The requested stat type is either not recognized (invalid)
97 * - DONE
98 * Bits 11
99 * Purpose:
100 * Indicates the completion of the stats entry, this will be the last
101 * stats conf HTT segment for the requested stats type.
102 * Value:
103 * 0 -> the stats retrieval is ongoing
104 * 1 -> the stats retrieval is complete
105 * - LENGTH
106 * Bits 31:16
107 * Purpose: indicate the stats information size
108 * Value: This field specifies the number of bytes of stats information
109 * that follows the element tag-length header.
110 * It is expected but not required that this length is a multiple of
111 * 4 bytes.
112 */
113
114 #define ATH12K_HTT_T2H_EXT_STATS_INFO1_DONE BIT(11)
115 #define ATH12K_HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16)
116
117 struct ath12k_htt_extd_stats_msg {
118 __le32 info0;
119 __le64 cookie;
120 __le32 info1;
121 u8 data[];
122 } __packed;
123
124 /* htt_dbg_ext_stats_type */
125 enum ath12k_dbg_htt_ext_stats_type {
126 ATH12K_DBG_HTT_EXT_STATS_RESET = 0,
127 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX = 1,
128 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_SCHED = 4,
129 ATH12K_DBG_HTT_EXT_STATS_PDEV_ERROR = 5,
130 ATH12K_DBG_HTT_EXT_STATS_PDEV_TQM = 6,
131 ATH12K_DBG_HTT_EXT_STATS_TX_DE_INFO = 8,
132 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_RATE = 9,
133 ATH12K_DBG_HTT_EXT_STATS_PDEV_RX_RATE = 10,
134 ATH12K_DBG_HTT_EXT_STATS_TX_SELFGEN_INFO = 12,
135 ATH12K_DBG_HTT_EXT_STATS_SRNG_INFO = 15,
136 ATH12K_DBG_HTT_EXT_STATS_SFM_INFO = 16,
137 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_MU = 17,
138 ATH12K_DBG_HTT_EXT_STATS_PDEV_CCA_STATS = 19,
139 ATH12K_DBG_HTT_EXT_STATS_TX_SOUNDING_INFO = 22,
140 ATH12K_DBG_HTT_EXT_STATS_PDEV_OBSS_PD_STATS = 23,
141 ATH12K_DBG_HTT_EXT_STATS_LATENCY_PROF_STATS = 25,
142 ATH12K_DBG_HTT_EXT_STATS_PDEV_UL_TRIG_STATS = 26,
143 ATH12K_DBG_HTT_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS = 27,
144 ATH12K_DBG_HTT_EXT_STATS_FSE_RX = 28,
145 ATH12K_DBG_HTT_EXT_STATS_PDEV_RX_RATE_EXT = 30,
146 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_RATE_TXBF = 31,
147 ATH12K_DBG_HTT_EXT_STATS_TXBF_OFDMA = 32,
148 ATH12K_DBG_HTT_EXT_STATS_DLPAGER_STATS = 36,
149 ATH12K_DBG_HTT_EXT_PHY_COUNTERS_AND_PHY_STATS = 37,
150 ATH12K_DBG_HTT_EXT_VDEVS_TXRX_STATS = 38,
151 ATH12K_DBG_HTT_EXT_PDEV_PER_STATS = 40,
152 ATH12K_DBG_HTT_EXT_AST_ENTRIES = 41,
153 ATH12K_DBG_HTT_EXT_STATS_SOC_ERROR = 45,
154 ATH12K_DBG_HTT_DBG_PDEV_PUNCTURE_STATS = 46,
155 ATH12K_DBG_HTT_EXT_STATS_PDEV_SCHED_ALGO = 49,
156 ATH12K_DBG_HTT_EXT_STATS_MANDATORY_MUOFDMA = 51,
157 ATH12K_DGB_HTT_EXT_STATS_PDEV_MBSSID_CTRL_FRAME = 54,
158
159 /* keep this last */
160 ATH12K_DBG_HTT_NUM_EXT_STATS,
161 };
162
163 enum ath12k_dbg_htt_tlv_tag {
164 HTT_STATS_TX_PDEV_CMN_TAG = 0,
165 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1,
166 HTT_STATS_TX_PDEV_SIFS_TAG = 2,
167 HTT_STATS_TX_PDEV_FLUSH_TAG = 3,
168 HTT_STATS_STRING_TAG = 5,
169 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11,
170 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12,
171 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13,
172 HTT_STATS_TX_TQM_CMN_TAG = 14,
173 HTT_STATS_TX_TQM_PDEV_TAG = 15,
174 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17,
175 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18,
176 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19,
177 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20,
178 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21,
179 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22,
180 HTT_STATS_TX_DE_CMN_TAG = 23,
181 HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25,
182 HTT_STATS_SFM_CMN_TAG = 26,
183 HTT_STATS_SRING_STATS_TAG = 27,
184 HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34,
185 HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35,
186 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36,
187 HTT_STATS_TX_SCHED_CMN_TAG = 37,
188 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39,
189 HTT_STATS_SFM_CLIENT_USER_TAG = 41,
190 HTT_STATS_SFM_CLIENT_TAG = 42,
191 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43,
192 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44,
193 HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46,
194 HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47,
195 HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48,
196 HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49,
197 HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50,
198 HTT_STATS_HW_INTR_MISC_TAG = 54,
199 HTT_STATS_HW_PDEV_ERRS_TAG = 56,
200 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65,
201 HTT_STATS_WHAL_TX_TAG = 66,
202 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67,
203 HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70,
204 HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71,
205 HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72,
206 HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73,
207 HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74,
208 HTT_STATS_TX_SOUNDING_STATS_TAG = 80,
209 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86,
210 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87,
211 HTT_STATS_PDEV_OBSS_PD_TAG = 88,
212 HTT_STATS_HW_WAR_TAG = 89,
213 HTT_STATS_LATENCY_PROF_STATS_TAG = 91,
214 HTT_STATS_LATENCY_CTX_TAG = 92,
215 HTT_STATS_LATENCY_CNT_TAG = 93,
216 HTT_STATS_RX_PDEV_UL_TRIG_STATS_TAG = 94,
217 HTT_STATS_RX_PDEV_UL_OFDMA_USER_STATS_TAG = 95,
218 HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG = 97,
219 HTT_STATS_RX_FSE_STATS_TAG = 98,
220 HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG = 100,
221 HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG = 102,
222 HTT_STATS_RX_PDEV_RATE_EXT_STATS_TAG = 103,
223 HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG = 108,
224 HTT_STATS_TX_SELFGEN_AC_SCHED_STATUS_STATS_TAG = 111,
225 HTT_STATS_TX_SELFGEN_AX_SCHED_STATUS_STATS_TAG = 112,
226 HTT_STATS_DLPAGER_STATS_TAG = 120,
227 HTT_STATS_PHY_COUNTERS_TAG = 121,
228 HTT_STATS_PHY_STATS_TAG = 122,
229 HTT_STATS_PHY_RESET_COUNTERS_TAG = 123,
230 HTT_STATS_PHY_RESET_STATS_TAG = 124,
231 HTT_STATS_SOC_TXRX_STATS_COMMON_TAG = 125,
232 HTT_STATS_PER_RATE_STATS_TAG = 128,
233 HTT_STATS_MU_PPDU_DIST_TAG = 129,
234 HTT_STATS_TX_PDEV_MUMIMO_GRP_STATS_TAG = 130,
235 HTT_STATS_AST_ENTRY_TAG = 132,
236 HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG = 135,
237 HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG = 137,
238 HTT_STATS_TX_SELFGEN_BE_STATS_TAG = 138,
239 HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG = 139,
240 HTT_STATS_TXBF_OFDMA_AX_NDPA_STATS_TAG = 147,
241 HTT_STATS_TXBF_OFDMA_AX_NDP_STATS_TAG = 148,
242 HTT_STATS_TXBF_OFDMA_AX_BRP_STATS_TAG = 149,
243 HTT_STATS_TXBF_OFDMA_AX_STEER_STATS_TAG = 150,
244 HTT_STATS_DMAC_RESET_STATS_TAG = 155,
245 HTT_STATS_PHY_TPC_STATS_TAG = 157,
246 HTT_STATS_PDEV_PUNCTURE_STATS_TAG = 158,
247 HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_TAG = 165,
248 HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG = 172,
249 HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176,
250
251 HTT_STATS_MAX_TAG,
252 };
253
254 #define ATH12K_HTT_STATS_MAC_ID GENMASK(7, 0)
255
256 #define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9
257 #define ATH12K_HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 150
258
259 /* MU MIMO distribution stats is a 2-dimensional array
260 * with dimension one denoting stats for nr4[0] or nr8[1]
261 */
262 #define ATH12K_HTT_STATS_NUM_NR_BINS 2
263 #define ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST 10
264 #define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10
265 #define ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS 9
266 #define ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS \
267 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS)
268 #define ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS \
269 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST)
270
271 enum ath12k_htt_tx_pdev_underrun_enum {
272 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0,
273 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1,
274 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2,
275 HTT_TX_PDEV_MAX_URRN_STATS = 3,
276 };
277
278 enum ath12k_htt_stats_reset_cfg_param_alloc_pos {
279 ATH12K_HTT_STATS_RESET_PARAM_CFG_32_BYTES = 1,
280 ATH12K_HTT_STATS_RESET_PARAM_CFG_64_BYTES,
281 ATH12K_HTT_STATS_RESET_PARAM_CFG_128_BYTES,
282 };
283
284 struct debug_htt_stats_req {
285 bool done;
286 bool override_cfg_param;
287 u8 pdev_id;
288 enum ath12k_dbg_htt_ext_stats_type type;
289 u32 cfg_param[4];
290 u8 peer_addr[ETH_ALEN];
291 struct completion htt_stats_rcvd;
292 u32 buf_len;
293 u8 buf[];
294 };
295
296 struct ath12k_htt_tx_pdev_stats_cmn_tlv {
297 __le32 mac_id__word;
298 __le32 hw_queued;
299 __le32 hw_reaped;
300 __le32 underrun;
301 __le32 hw_paused;
302 __le32 hw_flush;
303 __le32 hw_filt;
304 __le32 tx_abort;
305 __le32 mpdu_requed;
306 __le32 tx_xretry;
307 __le32 data_rc;
308 __le32 mpdu_dropped_xretry;
309 __le32 illgl_rate_phy_err;
310 __le32 cont_xretry;
311 __le32 tx_timeout;
312 __le32 pdev_resets;
313 __le32 phy_underrun;
314 __le32 txop_ovf;
315 __le32 seq_posted;
316 __le32 seq_failed_queueing;
317 __le32 seq_completed;
318 __le32 seq_restarted;
319 __le32 mu_seq_posted;
320 __le32 seq_switch_hw_paused;
321 __le32 next_seq_posted_dsr;
322 __le32 seq_posted_isr;
323 __le32 seq_ctrl_cached;
324 __le32 mpdu_count_tqm;
325 __le32 msdu_count_tqm;
326 __le32 mpdu_removed_tqm;
327 __le32 msdu_removed_tqm;
328 __le32 mpdus_sw_flush;
329 __le32 mpdus_hw_filter;
330 __le32 mpdus_truncated;
331 __le32 mpdus_ack_failed;
332 __le32 mpdus_expired;
333 __le32 mpdus_seq_hw_retry;
334 __le32 ack_tlv_proc;
335 __le32 coex_abort_mpdu_cnt_valid;
336 __le32 coex_abort_mpdu_cnt;
337 __le32 num_total_ppdus_tried_ota;
338 __le32 num_data_ppdus_tried_ota;
339 __le32 local_ctrl_mgmt_enqued;
340 __le32 local_ctrl_mgmt_freed;
341 __le32 local_data_enqued;
342 __le32 local_data_freed;
343 __le32 mpdu_tried;
344 __le32 isr_wait_seq_posted;
345
346 __le32 tx_active_dur_us_low;
347 __le32 tx_active_dur_us_high;
348 __le32 remove_mpdus_max_retries;
349 __le32 comp_delivered;
350 __le32 ppdu_ok;
351 __le32 self_triggers;
352 __le32 tx_time_dur_data;
353 __le32 seq_qdepth_repost_stop;
354 __le32 mu_seq_min_msdu_repost_stop;
355 __le32 seq_min_msdu_repost_stop;
356 __le32 seq_txop_repost_stop;
357 __le32 next_seq_cancel;
358 __le32 fes_offsets_err_cnt;
359 __le32 num_mu_peer_blacklisted;
360 __le32 mu_ofdma_seq_posted;
361 __le32 ul_mumimo_seq_posted;
362 __le32 ul_ofdma_seq_posted;
363
364 __le32 thermal_suspend_cnt;
365 __le32 dfs_suspend_cnt;
366 __le32 tx_abort_suspend_cnt;
367 __le32 tgt_specific_opaque_txq_suspend_info;
368 __le32 last_suspend_reason;
369 } __packed;
370
371 struct ath12k_htt_tx_pdev_stats_urrn_tlv {
372 DECLARE_FLEX_ARRAY(__le32, urrn_stats);
373 } __packed;
374
375 struct ath12k_htt_tx_pdev_stats_flush_tlv {
376 DECLARE_FLEX_ARRAY(__le32, flush_errs);
377 } __packed;
378
379 struct ath12k_htt_tx_pdev_stats_phy_err_tlv {
380 DECLARE_FLEX_ARRAY(__le32, phy_errs);
381 } __packed;
382
383 struct ath12k_htt_tx_pdev_stats_sifs_tlv {
384 DECLARE_FLEX_ARRAY(__le32, sifs_status);
385 } __packed;
386
387 struct ath12k_htt_pdev_ctrl_path_tx_stats_tlv {
388 __le32 fw_tx_mgmt_subtype[ATH12K_HTT_STATS_SUBTYPE_MAX];
389 } __packed;
390
391 struct ath12k_htt_tx_pdev_stats_sifs_hist_tlv {
392 DECLARE_FLEX_ARRAY(__le32, sifs_hist_status);
393 } __packed;
394
395 enum ath12k_htt_stats_hw_mode {
396 ATH12K_HTT_STATS_HWMODE_AC = 0,
397 ATH12K_HTT_STATS_HWMODE_AX = 1,
398 ATH12K_HTT_STATS_HWMODE_BE = 2,
399 };
400
401 struct ath12k_htt_tx_pdev_mu_ppdu_dist_stats_tlv {
402 __le32 hw_mode;
403 __le32 num_seq_term_status[ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS];
404 __le32 num_ppdu_cmpl_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS];
405 __le32 num_seq_posted[ATH12K_HTT_STATS_NUM_NR_BINS];
406 __le32 num_ppdu_posted_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS];
407 } __packed;
408
409 #define ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12
410 #define ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4
411 #define ATH12K_HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5
412 #define ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4
413 #define ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8
414 #define ATH12K_HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES 7
415 #define ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4
416 #define ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8
417 #define ATH12K_HTT_TX_PDEV_STATS_NUM_LTF 4
418 #define ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2
419 #define ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2
420 #define ATH12K_HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES 6
421
422 struct ath12k_htt_tx_pdev_rate_stats_tlv {
423 __le32 mac_id_word;
424 __le32 tx_ldpc;
425 __le32 rts_cnt;
426 __le32 ack_rssi;
427 __le32 tx_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
428 __le32 tx_su_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
429 __le32 tx_mu_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
430 __le32 tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
431 __le32 tx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
432 __le32 tx_stbc[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
433 __le32 tx_pream[ATH12K_HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES];
434 __le32 tx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
435 [ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
436 __le32 tx_dcm[ATH12K_HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS];
437 __le32 rts_success;
438 __le32 tx_legacy_cck_rate[ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS];
439 __le32 tx_legacy_ofdm_rate[ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS];
440 __le32 ac_mu_mimo_tx_ldpc;
441 __le32 ax_mu_mimo_tx_ldpc;
442 __le32 ofdma_tx_ldpc;
443 __le32 tx_he_ltf[ATH12K_HTT_TX_PDEV_STATS_NUM_LTF];
444 __le32 ac_mu_mimo_tx_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
445 __le32 ax_mu_mimo_tx_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
446 __le32 ofdma_tx_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
447 __le32 ac_mu_mimo_tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
448 __le32 ax_mu_mimo_tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
449 __le32 ofdma_tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
450 __le32 ac_mu_mimo_tx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
451 __le32 ax_mu_mimo_tx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
452 __le32 ofdma_tx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
453 __le32 ac_mu_mimo_tx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
454 [ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
455 __le32 ax_mimo_tx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
456 [ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
457 __le32 ofdma_tx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
458 [ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
459 __le32 trigger_type_11ax[ATH12K_HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES];
460 __le32 tx_11ax_su_ext;
461 __le32 tx_mcs_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
462 __le32 tx_stbc_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
463 __le32 tx_gi_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
464 [ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
465 __le32 ax_mu_mimo_tx_mcs_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
466 __le32 ofdma_tx_mcs_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
467 __le32 ax_tx_gi_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
468 [ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
469 __le32 ofd_tx_gi_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
470 [ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
471 __le32 tx_mcs_ext_2[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS];
472 __le32 tx_bw_320mhz;
473 };
474
475 #define ATH12K_HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4
476 #define ATH12K_HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8
477 #define ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12
478 #define ATH12K_HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4
479 #define ATH12K_HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5
480 #define ATH12K_HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4
481 #define ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS 8
482 #define ATH12K_HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES 7
483 #define ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER 8
484 #define ATH12K_HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_NSS 16
485 #define ATH12K_HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS 6
486 #define ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER 8
487 #define ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2
488
489 struct ath12k_htt_rx_pdev_rate_stats_tlv {
490 __le32 mac_id_word;
491 __le32 nsts;
492 __le32 rx_ldpc;
493 __le32 rts_cnt;
494 __le32 rssi_mgmt;
495 __le32 rssi_data;
496 __le32 rssi_comb;
497 __le32 rx_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
498 __le32 rx_nss[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS];
499 __le32 rx_dcm[ATH12K_HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS];
500 __le32 rx_stbc[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
501 __le32 rx_bw[ATH12K_HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
502 __le32 rx_pream[ATH12K_HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES];
503 u8 rssi_chain_in_db[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]
504 [ATH12K_HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
505 __le32 rx_gi[ATH12K_HTT_RX_PDEV_STATS_NUM_GI_COUNTERS]
506 [ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
507 __le32 rssi_in_dbm;
508 __le32 rx_11ax_su_ext;
509 __le32 rx_11ac_mumimo;
510 __le32 rx_11ax_mumimo;
511 __le32 rx_11ax_ofdma;
512 __le32 txbf;
513 __le32 rx_legacy_cck_rate[ATH12K_HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS];
514 __le32 rx_legacy_ofdm_rate[ATH12K_HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS];
515 __le32 rx_active_dur_us_low;
516 __le32 rx_active_dur_us_high;
517 __le32 rx_11ax_ul_ofdma;
518 __le32 ul_ofdma_rx_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
519 __le32 ul_ofdma_rx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
520 [ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
521 __le32 ul_ofdma_rx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
522 __le32 ul_ofdma_rx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
523 __le32 ul_ofdma_rx_stbc;
524 __le32 ul_ofdma_rx_ldpc;
525 __le32 rx_ulofdma_non_data_ppdu[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
526 __le32 rx_ulofdma_data_ppdu[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
527 __le32 rx_ulofdma_mpdu_ok[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
528 __le32 rx_ulofdma_mpdu_fail[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
529 __le32 nss_count;
530 __le32 pilot_count;
531 __le32 rx_pil_evm_db[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]
532 [ATH12K_HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_NSS];
533 __le32 rx_pilot_evm_db_mean[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS];
534 s8 rx_ul_fd_rssi[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]
535 [ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
536 __le32 per_chain_rssi_pkt_type;
537 s8 rx_per_chain_rssi_in_dbm[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]
538 [ATH12K_HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
539 __le32 rx_su_ndpa;
540 __le32 rx_11ax_su_txbf_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
541 __le32 rx_mu_ndpa;
542 __le32 rx_11ax_mu_txbf_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
543 __le32 rx_br_poll;
544 __le32 rx_11ax_dl_ofdma_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
545 __le32 rx_11ax_dl_ofdma_ru[ATH12K_HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS];
546 __le32 rx_ulmumimo_non_data_ppdu[ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER];
547 __le32 rx_ulmumimo_data_ppdu[ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER];
548 __le32 rx_ulmumimo_mpdu_ok[ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER];
549 __le32 rx_ulmumimo_mpdu_fail[ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER];
550 __le32 rx_ulofdma_non_data_nusers[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
551 __le32 rx_ulofdma_data_nusers[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
552 __le32 rx_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
553 };
554
555 #define ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS 4
556 #define ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT 14
557 #define ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2
558 #define ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT2_COUNTERS 5
559 #define ATH12K_HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS 5
560
561 struct ath12k_htt_rx_pdev_rate_ext_stats_tlv {
562 u8 rssi_chain_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]
563 [ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS];
564 s8 rx_per_chain_rssi_ext_in_dbm[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]
565 [ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS];
566 __le32 rssi_mcast_in_dbm;
567 __le32 rssi_mgmt_in_dbm;
568 __le32 rx_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT];
569 __le32 rx_stbc_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT];
570 __le32 rx_gi_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_GI_COUNTERS]
571 [ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT];
572 __le32 ul_ofdma_rx_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT];
573 __le32 ul_ofdma_rx_gi_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
574 [ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT];
575 __le32 rx_11ax_su_txbf_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT];
576 __le32 rx_11ax_mu_txbf_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT];
577 __le32 rx_11ax_dl_ofdma_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT];
578 __le32 rx_mcs_ext_2[ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS];
579 __le32 rx_bw_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT2_COUNTERS];
580 __le32 rx_gi_ext_2[ATH12K_HTT_RX_PDEV_STATS_NUM_GI_COUNTERS]
581 [ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS];
582 __le32 rx_su_punctured_mode[ATH12K_HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
583 };
584
585 #define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0)
586 #define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8)
587
588 #define ATH12K_HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20
589
590 struct ath12k_htt_stats_tx_sched_cmn_tlv {
591 __le32 mac_id__word;
592 __le32 current_timestamp;
593 } __packed;
594
595 struct ath12k_htt_tx_pdev_stats_sched_per_txq_tlv {
596 __le32 mac_id__word;
597 __le32 sched_policy;
598 __le32 last_sched_cmd_posted_timestamp;
599 __le32 last_sched_cmd_compl_timestamp;
600 __le32 sched_2_tac_lwm_count;
601 __le32 sched_2_tac_ring_full;
602 __le32 sched_cmd_post_failure;
603 __le32 num_active_tids;
604 __le32 num_ps_schedules;
605 __le32 sched_cmds_pending;
606 __le32 num_tid_register;
607 __le32 num_tid_unregister;
608 __le32 num_qstats_queried;
609 __le32 qstats_update_pending;
610 __le32 last_qstats_query_timestamp;
611 __le32 num_tqm_cmdq_full;
612 __le32 num_de_sched_algo_trigger;
613 __le32 num_rt_sched_algo_trigger;
614 __le32 num_tqm_sched_algo_trigger;
615 __le32 notify_sched;
616 __le32 dur_based_sendn_term;
617 __le32 su_notify2_sched;
618 __le32 su_optimal_queued_msdus_sched;
619 __le32 su_delay_timeout_sched;
620 __le32 su_min_txtime_sched_delay;
621 __le32 su_no_delay;
622 __le32 num_supercycles;
623 __le32 num_subcycles_with_sort;
624 __le32 num_subcycles_no_sort;
625 } __packed;
626
627 struct ath12k_htt_sched_txq_cmd_posted_tlv {
628 DECLARE_FLEX_ARRAY(__le32, sched_cmd_posted);
629 } __packed;
630
631 struct ath12k_htt_sched_txq_cmd_reaped_tlv {
632 DECLARE_FLEX_ARRAY(__le32, sched_cmd_reaped);
633 } __packed;
634
635 struct ath12k_htt_sched_txq_sched_order_su_tlv {
636 DECLARE_FLEX_ARRAY(__le32, sched_order_su);
637 } __packed;
638
639 struct ath12k_htt_sched_txq_sched_ineligibility_tlv {
640 DECLARE_FLEX_ARRAY(__le32, sched_ineligibility);
641 } __packed;
642
643 enum ath12k_htt_sched_txq_supercycle_triggers_tlv_enum {
644 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0,
645 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_FORCED,
646 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_TIDQ_ENTRIES,
647 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_ACTIVE_TIDS,
648 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX_ITR_REACHED,
649 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_DUR_THRESHOLD_REACHED,
650 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_TWT_TRIGGER,
651 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX,
652 };
653
654 struct ath12k_htt_sched_txq_supercycle_triggers_tlv {
655 DECLARE_FLEX_ARRAY(__le32, supercycle_triggers);
656 } __packed;
657
658 struct ath12k_htt_hw_stats_pdev_errs_tlv {
659 __le32 mac_id__word;
660 __le32 tx_abort;
661 __le32 tx_abort_fail_count;
662 __le32 rx_abort;
663 __le32 rx_abort_fail_count;
664 __le32 warm_reset;
665 __le32 cold_reset;
666 __le32 tx_flush;
667 __le32 tx_glb_reset;
668 __le32 tx_txq_reset;
669 __le32 rx_timeout_reset;
670 __le32 mac_cold_reset_restore_cal;
671 __le32 mac_cold_reset;
672 __le32 mac_warm_reset;
673 __le32 mac_only_reset;
674 __le32 phy_warm_reset;
675 __le32 phy_warm_reset_ucode_trig;
676 __le32 mac_warm_reset_restore_cal;
677 __le32 mac_sfm_reset;
678 __le32 phy_warm_reset_m3_ssr;
679 __le32 phy_warm_reset_reason_phy_m3;
680 __le32 phy_warm_reset_reason_tx_hw_stuck;
681 __le32 phy_warm_reset_reason_num_rx_frame_stuck;
682 __le32 phy_warm_reset_reason_wal_rx_rec_rx_busy;
683 __le32 phy_warm_reset_reason_wal_rx_rec_mac_hng;
684 __le32 phy_warm_reset_reason_mac_conv_phy_reset;
685 __le32 wal_rx_recovery_rst_mac_hang_cnt;
686 __le32 wal_rx_recovery_rst_known_sig_cnt;
687 __le32 wal_rx_recovery_rst_no_rx_cnt;
688 __le32 wal_rx_recovery_rst_no_rx_consec_cnt;
689 __le32 wal_rx_recovery_rst_rx_busy_cnt;
690 __le32 wal_rx_recovery_rst_phy_mac_hang_cnt;
691 __le32 rx_flush_cnt;
692 __le32 phy_warm_reset_reason_tx_exp_cca_stuck;
693 __le32 phy_warm_reset_reason_tx_consec_flsh_war;
694 __le32 phy_warm_reset_reason_tx_hwsch_reset_war;
695 __le32 phy_warm_reset_reason_hwsch_cca_wdog_war;
696 __le32 fw_rx_rings_reset;
697 __le32 rx_dest_drain_rx_descs_leak_prevented;
698 __le32 rx_dest_drain_rx_descs_saved_cnt;
699 __le32 rx_dest_drain_rxdma2reo_leak_detected;
700 __le32 rx_dest_drain_rxdma2fw_leak_detected;
701 __le32 rx_dest_drain_rxdma2wbm_leak_detected;
702 __le32 rx_dest_drain_rxdma1_2sw_leak_detected;
703 __le32 rx_dest_drain_rx_drain_ok_mac_idle;
704 __le32 rx_dest_drain_ok_mac_not_idle;
705 __le32 rx_dest_drain_prerequisite_invld;
706 __le32 rx_dest_drain_skip_non_lmac_reset;
707 __le32 rx_dest_drain_hw_fifo_notempty_post_wait;
708 } __packed;
709
710 #define ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN 8
711 struct ath12k_htt_hw_stats_intr_misc_tlv {
712 u8 hw_intr_name[ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN];
713 __le32 mask;
714 __le32 count;
715 } __packed;
716
717 struct ath12k_htt_hw_stats_whal_tx_tlv {
718 __le32 mac_id__word;
719 __le32 last_unpause_ppdu_id;
720 __le32 hwsch_unpause_wait_tqm_write;
721 __le32 hwsch_dummy_tlv_skipped;
722 __le32 hwsch_misaligned_offset_received;
723 __le32 hwsch_reset_count;
724 __le32 hwsch_dev_reset_war;
725 __le32 hwsch_delayed_pause;
726 __le32 hwsch_long_delayed_pause;
727 __le32 sch_rx_ppdu_no_response;
728 __le32 sch_selfgen_response;
729 __le32 sch_rx_sifs_resp_trigger;
730 } __packed;
731
732 struct ath12k_htt_hw_war_stats_tlv {
733 __le32 mac_id__word;
734 DECLARE_FLEX_ARRAY(__le32, hw_wars);
735 } __packed;
736
737 struct ath12k_htt_tx_tqm_cmn_stats_tlv {
738 __le32 mac_id__word;
739 __le32 max_cmdq_id;
740 __le32 list_mpdu_cnt_hist_intvl;
741 __le32 add_msdu;
742 __le32 q_empty;
743 __le32 q_not_empty;
744 __le32 drop_notification;
745 __le32 desc_threshold;
746 __le32 hwsch_tqm_invalid_status;
747 __le32 missed_tqm_gen_mpdus;
748 __le32 tqm_active_tids;
749 __le32 tqm_inactive_tids;
750 __le32 tqm_active_msduq_flows;
751 __le32 msduq_timestamp_updates;
752 __le32 msduq_updates_mpdu_head_info_cmd;
753 __le32 msduq_updates_emp_to_nonemp_status;
754 __le32 get_mpdu_head_info_cmds_by_query;
755 __le32 get_mpdu_head_info_cmds_by_tac;
756 __le32 gen_mpdu_cmds_by_query;
757 __le32 high_prio_q_not_empty;
758 } __packed;
759
760 struct ath12k_htt_tx_tqm_error_stats_tlv {
761 __le32 q_empty_failure;
762 __le32 q_not_empty_failure;
763 __le32 add_msdu_failure;
764 __le32 tqm_cache_ctl_err;
765 __le32 tqm_soft_reset;
766 __le32 tqm_reset_num_in_use_link_descs;
767 __le32 tqm_reset_num_lost_link_descs;
768 __le32 tqm_reset_num_lost_host_tx_buf_cnt;
769 __le32 tqm_reset_num_in_use_internal_tqm;
770 __le32 tqm_reset_num_in_use_idle_link_rng;
771 __le32 tqm_reset_time_to_tqm_hang_delta_ms;
772 __le32 tqm_reset_recovery_time_ms;
773 __le32 tqm_reset_num_peers_hdl;
774 __le32 tqm_reset_cumm_dirty_hw_mpduq_cnt;
775 __le32 tqm_reset_cumm_dirty_hw_msduq_proc;
776 __le32 tqm_reset_flush_cache_cmd_su_cnt;
777 __le32 tqm_reset_flush_cache_cmd_other_cnt;
778 __le32 tqm_reset_flush_cache_cmd_trig_type;
779 __le32 tqm_reset_flush_cache_cmd_trig_cfg;
780 __le32 tqm_reset_flush_cmd_skp_status_null;
781 } __packed;
782
783 struct ath12k_htt_tx_tqm_gen_mpdu_stats_tlv {
784 DECLARE_FLEX_ARRAY(__le32, gen_mpdu_end_reason);
785 } __packed;
786
787 #define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16
788 #define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16
789
790 struct ath12k_htt_tx_tqm_list_mpdu_stats_tlv {
791 DECLARE_FLEX_ARRAY(__le32, list_mpdu_end_reason);
792 } __packed;
793
794 struct ath12k_htt_tx_tqm_list_mpdu_cnt_tlv {
795 DECLARE_FLEX_ARRAY(__le32, list_mpdu_cnt_hist);
796 } __packed;
797
798 struct ath12k_htt_tx_tqm_pdev_stats_tlv {
799 __le32 msdu_count;
800 __le32 mpdu_count;
801 __le32 remove_msdu;
802 __le32 remove_mpdu;
803 __le32 remove_msdu_ttl;
804 __le32 send_bar;
805 __le32 bar_sync;
806 __le32 notify_mpdu;
807 __le32 sync_cmd;
808 __le32 write_cmd;
809 __le32 hwsch_trigger;
810 __le32 ack_tlv_proc;
811 __le32 gen_mpdu_cmd;
812 __le32 gen_list_cmd;
813 __le32 remove_mpdu_cmd;
814 __le32 remove_mpdu_tried_cmd;
815 __le32 mpdu_queue_stats_cmd;
816 __le32 mpdu_head_info_cmd;
817 __le32 msdu_flow_stats_cmd;
818 __le32 remove_msdu_cmd;
819 __le32 remove_msdu_ttl_cmd;
820 __le32 flush_cache_cmd;
821 __le32 update_mpduq_cmd;
822 __le32 enqueue;
823 __le32 enqueue_notify;
824 __le32 notify_mpdu_at_head;
825 __le32 notify_mpdu_state_valid;
826 __le32 sched_udp_notify1;
827 __le32 sched_udp_notify2;
828 __le32 sched_nonudp_notify1;
829 __le32 sched_nonudp_notify2;
830 } __packed;
831
832 struct ath12k_htt_tx_de_cmn_stats_tlv {
833 __le32 mac_id__word;
834 __le32 tcl2fw_entry_count;
835 __le32 not_to_fw;
836 __le32 invalid_pdev_vdev_peer;
837 __le32 tcl_res_invalid_addrx;
838 __le32 wbm2fw_entry_count;
839 __le32 invalid_pdev;
840 __le32 tcl_res_addrx_timeout;
841 __le32 invalid_vdev;
842 __le32 invalid_tcl_exp_frame_desc;
843 __le32 vdev_id_mismatch_cnt;
844 } __packed;
845
846 struct ath12k_htt_tx_de_eapol_packets_stats_tlv {
847 __le32 m1_packets;
848 __le32 m2_packets;
849 __le32 m3_packets;
850 __le32 m4_packets;
851 __le32 g1_packets;
852 __le32 g2_packets;
853 __le32 rc4_packets;
854 __le32 eap_packets;
855 __le32 eapol_start_packets;
856 __le32 eapol_logoff_packets;
857 __le32 eapol_encap_asf_packets;
858 } __packed;
859
860 struct ath12k_htt_tx_de_classify_stats_tlv {
861 __le32 arp_packets;
862 __le32 igmp_packets;
863 __le32 dhcp_packets;
864 __le32 host_inspected;
865 __le32 htt_included;
866 __le32 htt_valid_mcs;
867 __le32 htt_valid_nss;
868 __le32 htt_valid_preamble_type;
869 __le32 htt_valid_chainmask;
870 __le32 htt_valid_guard_interval;
871 __le32 htt_valid_retries;
872 __le32 htt_valid_bw_info;
873 __le32 htt_valid_power;
874 __le32 htt_valid_key_flags;
875 __le32 htt_valid_no_encryption;
876 __le32 fse_entry_count;
877 __le32 fse_priority_be;
878 __le32 fse_priority_high;
879 __le32 fse_priority_low;
880 __le32 fse_traffic_ptrn_be;
881 __le32 fse_traffic_ptrn_over_sub;
882 __le32 fse_traffic_ptrn_bursty;
883 __le32 fse_traffic_ptrn_interactive;
884 __le32 fse_traffic_ptrn_periodic;
885 __le32 fse_hwqueue_alloc;
886 __le32 fse_hwqueue_created;
887 __le32 fse_hwqueue_send_to_host;
888 __le32 mcast_entry;
889 __le32 bcast_entry;
890 __le32 htt_update_peer_cache;
891 __le32 htt_learning_frame;
892 __le32 fse_invalid_peer;
893 __le32 mec_notify;
894 } __packed;
895
896 struct ath12k_htt_tx_de_classify_failed_stats_tlv {
897 __le32 ap_bss_peer_not_found;
898 __le32 ap_bcast_mcast_no_peer;
899 __le32 sta_delete_in_progress;
900 __le32 ibss_no_bss_peer;
901 __le32 invalid_vdev_type;
902 __le32 invalid_ast_peer_entry;
903 __le32 peer_entry_invalid;
904 __le32 ethertype_not_ip;
905 __le32 eapol_lookup_failed;
906 __le32 qpeer_not_allow_data;
907 __le32 fse_tid_override;
908 __le32 ipv6_jumbogram_zero_length;
909 __le32 qos_to_non_qos_in_prog;
910 __le32 ap_bcast_mcast_eapol;
911 __le32 unicast_on_ap_bss_peer;
912 __le32 ap_vdev_invalid;
913 __le32 incomplete_llc;
914 __le32 eapol_duplicate_m3;
915 __le32 eapol_duplicate_m4;
916 } __packed;
917
918 struct ath12k_htt_tx_de_classify_status_stats_tlv {
919 __le32 eok;
920 __le32 classify_done;
921 __le32 lookup_failed;
922 __le32 send_host_dhcp;
923 __le32 send_host_mcast;
924 __le32 send_host_unknown_dest;
925 __le32 send_host;
926 __le32 status_invalid;
927 } __packed;
928
929 struct ath12k_htt_tx_de_enqueue_packets_stats_tlv {
930 __le32 enqueued_pkts;
931 __le32 to_tqm;
932 __le32 to_tqm_bypass;
933 } __packed;
934
935 struct ath12k_htt_tx_de_enqueue_discard_stats_tlv {
936 __le32 discarded_pkts;
937 __le32 local_frames;
938 __le32 is_ext_msdu;
939 } __packed;
940
941 struct ath12k_htt_tx_de_compl_stats_tlv {
942 __le32 tcl_dummy_frame;
943 __le32 tqm_dummy_frame;
944 __le32 tqm_notify_frame;
945 __le32 fw2wbm_enq;
946 __le32 tqm_bypass_frame;
947 } __packed;
948
949 enum ath12k_htt_tx_mumimo_grp_invalid_reason_code_stats {
950 ATH12K_HTT_TX_MUMIMO_GRP_VALID,
951 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_NUM_MU_USERS_EXCEEDED_MU_MAX_USERS,
952 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_SCHED_ALGO_NOT_MU_COMPATIBLE_GID,
953 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_NON_PRIMARY_GRP,
954 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_ZERO_CANDIDATES,
955 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MORE_CANDIDATES,
956 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_SIZE_EXCEED_NSS,
957 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_INELIGIBLE,
958 ATH12K_HTT_TX_MUMIMO_GRP_INVALID,
959 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_EFF_MU_TPUT_OMBPS,
960 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE,
961 };
962
963 #define ATH12K_HTT_NUM_AC_WMM 0x4
964 #define ATH12K_HTT_MAX_NUM_SBT_INTR 4
965 #define ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS 4
966 #define ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS 8
967 #define ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS 8
968 #define ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS 7
969 #define ATH12K_HTT_TX_NUM_OFDMA_USER_STATS 74
970 #define ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS 8
971 #define ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ 8
972 #define ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS 10
973
974 #define ATH12K_HTT_STATS_MAX_INVALID_REASON_CODE \
975 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE
976 #define ATH12K_HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS \
977 (ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ * ATH12K_HTT_STATS_MAX_INVALID_REASON_CODE)
978
979 struct ath12k_htt_tx_selfgen_cmn_stats_tlv {
980 __le32 mac_id__word;
981 __le32 su_bar;
982 __le32 rts;
983 __le32 cts2self;
984 __le32 qos_null;
985 __le32 delayed_bar_1;
986 __le32 delayed_bar_2;
987 __le32 delayed_bar_3;
988 __le32 delayed_bar_4;
989 __le32 delayed_bar_5;
990 __le32 delayed_bar_6;
991 __le32 delayed_bar_7;
992 } __packed;
993
994 struct ath12k_htt_tx_selfgen_ac_stats_tlv {
995 __le32 ac_su_ndpa;
996 __le32 ac_su_ndp;
997 __le32 ac_mu_mimo_ndpa;
998 __le32 ac_mu_mimo_ndp;
999 __le32 ac_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS - 1];
1000 } __packed;
1001
1002 struct ath12k_htt_tx_selfgen_ax_stats_tlv {
1003 __le32 ax_su_ndpa;
1004 __le32 ax_su_ndp;
1005 __le32 ax_mu_mimo_ndpa;
1006 __le32 ax_mu_mimo_ndp;
1007 __le32 ax_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS - 1];
1008 __le32 ax_basic_trigger;
1009 __le32 ax_bsr_trigger;
1010 __le32 ax_mu_bar_trigger;
1011 __le32 ax_mu_rts_trigger;
1012 __le32 ax_ulmumimo_trigger;
1013 } __packed;
1014
1015 struct ath12k_htt_tx_selfgen_be_stats_tlv {
1016 __le32 be_su_ndpa;
1017 __le32 be_su_ndp;
1018 __le32 be_mu_mimo_ndpa;
1019 __le32 be_mu_mimo_ndp;
1020 __le32 be_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1];
1021 __le32 be_basic_trigger;
1022 __le32 be_bsr_trigger;
1023 __le32 be_mu_bar_trigger;
1024 __le32 be_mu_rts_trigger;
1025 __le32 be_ulmumimo_trigger;
1026 __le32 be_su_ndpa_queued;
1027 __le32 be_su_ndp_queued;
1028 __le32 be_mu_mimo_ndpa_queued;
1029 __le32 be_mu_mimo_ndp_queued;
1030 __le32 be_mu_mimo_brpoll_queued[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1];
1031 __le32 be_ul_mumimo_trigger[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS];
1032 } __packed;
1033
1034 struct ath12k_htt_tx_selfgen_ac_err_stats_tlv {
1035 __le32 ac_su_ndp_err;
1036 __le32 ac_su_ndpa_err;
1037 __le32 ac_mu_mimo_ndpa_err;
1038 __le32 ac_mu_mimo_ndp_err;
1039 __le32 ac_mu_mimo_brp1_err;
1040 __le32 ac_mu_mimo_brp2_err;
1041 __le32 ac_mu_mimo_brp3_err;
1042 } __packed;
1043
1044 struct ath12k_htt_tx_selfgen_ax_err_stats_tlv {
1045 __le32 ax_su_ndp_err;
1046 __le32 ax_su_ndpa_err;
1047 __le32 ax_mu_mimo_ndpa_err;
1048 __le32 ax_mu_mimo_ndp_err;
1049 __le32 ax_mu_mimo_brp_err[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS - 1];
1050 __le32 ax_basic_trigger_err;
1051 __le32 ax_bsr_trigger_err;
1052 __le32 ax_mu_bar_trigger_err;
1053 __le32 ax_mu_rts_trigger_err;
1054 __le32 ax_ulmumimo_trigger_err;
1055 } __packed;
1056
1057 struct ath12k_htt_tx_selfgen_be_err_stats_tlv {
1058 __le32 be_su_ndp_err;
1059 __le32 be_su_ndpa_err;
1060 __le32 be_mu_mimo_ndpa_err;
1061 __le32 be_mu_mimo_ndp_err;
1062 __le32 be_mu_mimo_brp_err[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1];
1063 __le32 be_basic_trigger_err;
1064 __le32 be_bsr_trigger_err;
1065 __le32 be_mu_bar_trigger_err;
1066 __le32 be_mu_rts_trigger_err;
1067 __le32 be_ulmumimo_trigger_err;
1068 __le32 be_mu_mimo_brp_err_num_cbf_rxd[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS];
1069 __le32 be_su_ndpa_flushed;
1070 __le32 be_su_ndp_flushed;
1071 __le32 be_mu_mimo_ndpa_flushed;
1072 __le32 be_mu_mimo_ndp_flushed;
1073 __le32 be_mu_mimo_brpoll_flushed[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1];
1074 __le32 be_ul_mumimo_trigger_err[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS];
1075 } __packed;
1076
1077 enum ath12k_htt_tx_selfgen_sch_tsflag_error_stats {
1078 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_FLUSH_RCVD_ERR,
1079 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_FILT_SCHED_CMD_ERR,
1080 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_MISMATCH_ERR,
1081 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_MIMO_CTRL_MISMATCH_ERR,
1082 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_BW_MISMATCH_ERR,
1083 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RETRY_COUNT_FAIL_ERR,
1084 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_TOO_LATE_RECEIVED_ERR,
1085 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_SIFS_STALL_NO_NEXT_CMD_ERR,
1086
1087 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS
1088 };
1089
1090 struct ath12k_htt_tx_selfgen_ac_sched_status_stats_tlv {
1091 __le32 ac_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1092 __le32 ac_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1093 __le32 ac_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
1094 __le32 ac_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1095 __le32 ac_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1096 __le32 ac_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
1097 __le32 ac_mu_mimo_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1098 __le32 ac_mu_mimo_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
1099 } __packed;
1100
1101 struct ath12k_htt_tx_selfgen_ax_sched_status_stats_tlv {
1102 __le32 ax_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1103 __le32 ax_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1104 __le32 ax_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
1105 __le32 ax_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1106 __le32 ax_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1107 __le32 ax_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
1108 __le32 ax_mu_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1109 __le32 ax_mu_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
1110 __le32 ax_mu_bar_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1111 __le32 ax_mu_bar_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
1112 __le32 ax_basic_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1113 __le32 ax_basic_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
1114 __le32 ax_ulmumimo_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1115 __le32 ax_ulmumimo_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
1116 } __packed;
1117
1118 struct ath12k_htt_tx_selfgen_be_sched_status_stats_tlv {
1119 __le32 be_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1120 __le32 be_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1121 __le32 be_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
1122 __le32 be_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1123 __le32 be_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1124 __le32 be_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
1125 __le32 be_mu_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1126 __le32 be_mu_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
1127 __le32 be_mu_bar_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1128 __le32 be_mu_bar_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
1129 __le32 be_basic_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1130 __le32 be_basic_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
1131 __le32 be_ulmumimo_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
1132 __le32 be_ulmumimo_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
1133 } __packed;
1134
1135 struct ath12k_htt_stats_string_tlv {
1136 DECLARE_FLEX_ARRAY(__le32, data);
1137 } __packed;
1138
1139 #define ATH12K_HTT_SRING_STATS_MAC_ID GENMASK(7, 0)
1140 #define ATH12K_HTT_SRING_STATS_RING_ID GENMASK(15, 8)
1141 #define ATH12K_HTT_SRING_STATS_ARENA GENMASK(23, 16)
1142 #define ATH12K_HTT_SRING_STATS_EP BIT(24)
1143 #define ATH12K_HTT_SRING_STATS_NUM_AVAIL_WORDS GENMASK(15, 0)
1144 #define ATH12K_HTT_SRING_STATS_NUM_VALID_WORDS GENMASK(31, 16)
1145 #define ATH12K_HTT_SRING_STATS_HEAD_PTR GENMASK(15, 0)
1146 #define ATH12K_HTT_SRING_STATS_TAIL_PTR GENMASK(31, 16)
1147 #define ATH12K_HTT_SRING_STATS_CONSUMER_EMPTY GENMASK(15, 0)
1148 #define ATH12K_HTT_SRING_STATS_PRODUCER_FULL GENMASK(31, 16)
1149 #define ATH12K_HTT_SRING_STATS_PREFETCH_COUNT GENMASK(15, 0)
1150 #define ATH12K_HTT_SRING_STATS_INTERNAL_TAIL_PTR GENMASK(31, 16)
1151
1152 struct ath12k_htt_sring_stats_tlv {
1153 __le32 mac_id__ring_id__arena__ep;
1154 __le32 base_addr_lsb;
1155 __le32 base_addr_msb;
1156 __le32 ring_size;
1157 __le32 elem_size;
1158 __le32 num_avail_words__num_valid_words;
1159 __le32 head_ptr__tail_ptr;
1160 __le32 consumer_empty__producer_full;
1161 __le32 prefetch_count__internal_tail_ptr;
1162 } __packed;
1163
1164 struct ath12k_htt_sfm_cmn_tlv {
1165 __le32 mac_id__word;
1166 __le32 buf_total;
1167 __le32 mem_empty;
1168 __le32 deallocate_bufs;
1169 __le32 num_records;
1170 } __packed;
1171
1172 struct ath12k_htt_sfm_client_tlv {
1173 __le32 client_id;
1174 __le32 buf_min;
1175 __le32 buf_max;
1176 __le32 buf_busy;
1177 __le32 buf_alloc;
1178 __le32 buf_avail;
1179 __le32 num_users;
1180 } __packed;
1181
1182 struct ath12k_htt_sfm_client_user_tlv {
1183 DECLARE_FLEX_ARRAY(__le32, dwords_used_by_user_n);
1184 } __packed;
1185
1186 struct ath12k_htt_tx_pdev_mu_mimo_sch_stats_tlv {
1187 __le32 mu_mimo_sch_posted;
1188 __le32 mu_mimo_sch_failed;
1189 __le32 mu_mimo_ppdu_posted;
1190 __le32 ac_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS];
1191 __le32 ax_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS];
1192 __le32 ax_ofdma_sch_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS];
1193 __le32 ax_ul_ofdma_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS];
1194 __le32 ax_ul_ofdma_bsr_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS];
1195 __le32 ax_ul_ofdma_bar_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS];
1196 __le32 ax_ul_ofdma_brp_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS];
1197 __le32 ax_ul_mumimo_nusers[ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS];
1198 __le32 ax_ul_mumimo_brp_nusers[ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS];
1199 __le32 ac_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS];
1200 __le32 ax_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS];
1201 __le32 be_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS];
1202 __le32 be_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS];
1203 __le32 ac_mu_mimo_grp_sz_ext[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS];
1204 } __packed;
1205
1206 struct ath12k_htt_tx_pdev_mumimo_grp_stats_tlv {
1207 __le32 dl_mumimo_grp_best_grp_size[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ];
1208 __le32 dl_mumimo_grp_best_num_usrs[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS];
1209 __le32 dl_mumimo_grp_eligible[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ];
1210 __le32 dl_mumimo_grp_ineligible[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ];
1211 __le32 dl_mumimo_grp_invalid[ATH12K_HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS];
1212 __le32 dl_mumimo_grp_tputs[ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS];
1213 __le32 ul_mumimo_grp_best_grp_size[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ];
1214 __le32 ul_mumimo_grp_best_usrs[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS];
1215 __le32 ul_mumimo_grp_tputs[ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS];
1216 } __packed;
1217
1218 enum ath12k_htt_stats_tx_sched_modes {
1219 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC = 0,
1220 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX,
1221 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX,
1222 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_OFDMA_BE,
1223 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_BE
1224 };
1225
1226 struct ath12k_htt_tx_pdev_mpdu_stats_tlv {
1227 __le32 mpdus_queued_usr;
1228 __le32 mpdus_tried_usr;
1229 __le32 mpdus_failed_usr;
1230 __le32 mpdus_requeued_usr;
1231 __le32 err_no_ba_usr;
1232 __le32 mpdu_underrun_usr;
1233 __le32 ampdu_underrun_usr;
1234 __le32 user_index;
1235 __le32 tx_sched_mode;
1236 } __packed;
1237
1238 struct ath12k_htt_pdev_stats_cca_counters_tlv {
1239 __le32 tx_frame_usec;
1240 __le32 rx_frame_usec;
1241 __le32 rx_clear_usec;
1242 __le32 my_rx_frame_usec;
1243 __le32 usec_cnt;
1244 __le32 med_rx_idle_usec;
1245 __le32 med_tx_idle_global_usec;
1246 __le32 cca_obss_usec;
1247 } __packed;
1248
1249 struct ath12k_htt_pdev_cca_stats_hist_v1_tlv {
1250 __le32 chan_num;
1251 __le32 num_records;
1252 __le32 valid_cca_counters_bitmap;
1253 __le32 collection_interval;
1254 } __packed;
1255
1256 #define ATH12K_HTT_TX_CV_CORR_MAX_NUM_COLUMNS 8
1257 #define ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS 4
1258 #define ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS 8
1259 #define ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS 8
1260 #define ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4
1261 #define ATH12K_HTT_TX_NUM_MCS_CNTRS 12
1262 #define ATH12K_HTT_TX_NUM_EXTRA_MCS_CNTRS 2
1263
1264 #define ATH12K_HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \
1265 (ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \
1266 ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS)
1267
1268 enum ath12k_htt_txbf_sound_steer_modes {
1269 ATH12K_HTT_IMPL_STEER_STATS = 0,
1270 ATH12K_HTT_EXPL_SUSIFS_STEER_STATS = 1,
1271 ATH12K_HTT_EXPL_SURBO_STEER_STATS = 2,
1272 ATH12K_HTT_EXPL_MUSIFS_STEER_STATS = 3,
1273 ATH12K_HTT_EXPL_MURBO_STEER_STATS = 4,
1274 ATH12K_HTT_TXBF_MAX_NUM_OF_MODES = 5
1275 };
1276
1277 enum ath12k_htt_stats_sounding_tx_mode {
1278 ATH12K_HTT_TX_AC_SOUNDING_MODE = 0,
1279 ATH12K_HTT_TX_AX_SOUNDING_MODE = 1,
1280 ATH12K_HTT_TX_BE_SOUNDING_MODE = 2,
1281 ATH12K_HTT_TX_CMN_SOUNDING_MODE = 3,
1282 };
1283
1284 struct ath12k_htt_tx_sounding_stats_tlv {
1285 __le32 tx_sounding_mode;
1286 __le32 cbf_20[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES];
1287 __le32 cbf_40[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES];
1288 __le32 cbf_80[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES];
1289 __le32 cbf_160[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES];
1290 __le32 sounding[ATH12K_HTT_TX_NUM_OF_SOUNDING_STATS_WORDS];
1291 __le32 cv_nc_mismatch_err;
1292 __le32 cv_fcs_err;
1293 __le32 cv_frag_idx_mismatch;
1294 __le32 cv_invalid_peer_id;
1295 __le32 cv_no_txbf_setup;
1296 __le32 cv_expiry_in_update;
1297 __le32 cv_pkt_bw_exceed;
1298 __le32 cv_dma_not_done_err;
1299 __le32 cv_update_failed;
1300 __le32 cv_total_query;
1301 __le32 cv_total_pattern_query;
1302 __le32 cv_total_bw_query;
1303 __le32 cv_invalid_bw_coding;
1304 __le32 cv_forced_sounding;
1305 __le32 cv_standalone_sounding;
1306 __le32 cv_nc_mismatch;
1307 __le32 cv_fb_type_mismatch;
1308 __le32 cv_ofdma_bw_mismatch;
1309 __le32 cv_bw_mismatch;
1310 __le32 cv_pattern_mismatch;
1311 __le32 cv_preamble_mismatch;
1312 __le32 cv_nr_mismatch;
1313 __le32 cv_in_use_cnt_exceeded;
1314 __le32 cv_found;
1315 __le32 cv_not_found;
1316 __le32 sounding_320[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS];
1317 __le32 cbf_320[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES];
1318 __le32 cv_ntbr_sounding;
1319 __le32 cv_found_upload_in_progress;
1320 __le32 cv_expired_during_query;
1321 __le32 cv_dma_timeout_error;
1322 __le32 cv_buf_ibf_uploads;
1323 __le32 cv_buf_ebf_uploads;
1324 __le32 cv_buf_received;
1325 __le32 cv_buf_fed_back;
1326 __le32 cv_total_query_ibf;
1327 __le32 cv_found_ibf;
1328 __le32 cv_not_found_ibf;
1329 __le32 cv_expired_during_query_ibf;
1330 } __packed;
1331
1332 struct ath12k_htt_pdev_obss_pd_stats_tlv {
1333 __le32 num_obss_tx_ppdu_success;
1334 __le32 num_obss_tx_ppdu_failure;
1335 __le32 num_sr_tx_transmissions;
1336 __le32 num_spatial_reuse_opportunities;
1337 __le32 num_non_srg_opportunities;
1338 __le32 num_non_srg_ppdu_tried;
1339 __le32 num_non_srg_ppdu_success;
1340 __le32 num_srg_opportunities;
1341 __le32 num_srg_ppdu_tried;
1342 __le32 num_srg_ppdu_success;
1343 __le32 num_psr_opportunities;
1344 __le32 num_psr_ppdu_tried;
1345 __le32 num_psr_ppdu_success;
1346 __le32 num_non_srg_tried_per_ac[ATH12K_HTT_NUM_AC_WMM];
1347 __le32 num_non_srg_success_ac[ATH12K_HTT_NUM_AC_WMM];
1348 __le32 num_srg_tried_per_ac[ATH12K_HTT_NUM_AC_WMM];
1349 __le32 num_srg_success_per_ac[ATH12K_HTT_NUM_AC_WMM];
1350 __le32 num_obss_min_dur_check_flush_cnt;
1351 __le32 num_sr_ppdu_abort_flush_cnt;
1352 } __packed;
1353
1354 #define ATH12K_HTT_STATS_MAX_PROF_STATS_NAME_LEN 32
1355 #define ATH12K_HTT_LATENCY_PROFILE_NUM_MAX_HIST 3
1356 #define ATH12K_HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST 3
1357
1358 struct ath12k_htt_latency_prof_stats_tlv {
1359 __le32 print_header;
1360 s8 latency_prof_name[ATH12K_HTT_STATS_MAX_PROF_STATS_NAME_LEN];
1361 __le32 cnt;
1362 __le32 min;
1363 __le32 max;
1364 __le32 last;
1365 __le32 tot;
1366 __le32 avg;
1367 __le32 hist_intvl;
1368 __le32 hist[ATH12K_HTT_LATENCY_PROFILE_NUM_MAX_HIST];
1369 } __packed;
1370
1371 struct ath12k_htt_latency_prof_ctx_tlv {
1372 __le32 duration;
1373 __le32 tx_msdu_cnt;
1374 __le32 tx_mpdu_cnt;
1375 __le32 tx_ppdu_cnt;
1376 __le32 rx_msdu_cnt;
1377 __le32 rx_mpdu_cnt;
1378 } __packed;
1379
1380 struct ath12k_htt_latency_prof_cnt_tlv {
1381 __le32 prof_enable_cnt;
1382 } __packed;
1383
1384 #define ATH12K_HTT_RX_NUM_MCS_CNTRS 12
1385 #define ATH12K_HTT_RX_NUM_GI_CNTRS 4
1386 #define ATH12K_HTT_RX_NUM_SPATIAL_STREAMS 8
1387 #define ATH12K_HTT_RX_NUM_BW_CNTRS 4
1388 #define ATH12K_HTT_RX_NUM_RU_SIZE_CNTRS 6
1389 #define ATH12K_HTT_RX_NUM_RU_SIZE_160MHZ_CNTRS 7
1390 #define ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK 5
1391 #define ATH12K_HTT_RX_NUM_REDUCED_CHAN_TYPES 2
1392 #define ATH12K_HTT_RX_NUM_EXTRA_MCS_CNTRS 2
1393
1394 enum ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE {
1395 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_26,
1396 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_52,
1397 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_106,
1398 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_242,
1399 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_484,
1400 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_996,
1401 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_996x2,
1402 ATH12K_HTT_TX_RX_PDEV_STATS_NUM_AX_RU_SIZE_CNTRS,
1403 };
1404
1405 struct ath12k_htt_rx_pdev_ul_ofdma_user_stats_tlv {
1406 __le32 user_index;
1407 __le32 rx_ulofdma_non_data_ppdu;
1408 __le32 rx_ulofdma_data_ppdu;
1409 __le32 rx_ulofdma_mpdu_ok;
1410 __le32 rx_ulofdma_mpdu_fail;
1411 __le32 rx_ulofdma_non_data_nusers;
1412 __le32 rx_ulofdma_data_nusers;
1413 } __packed;
1414
1415 struct ath12k_htt_rx_pdev_ul_trigger_stats_tlv {
1416 __le32 mac_id__word;
1417 __le32 rx_11ax_ul_ofdma;
1418 __le32 ul_ofdma_rx_mcs[ATH12K_HTT_RX_NUM_MCS_CNTRS];
1419 __le32 ul_ofdma_rx_gi[ATH12K_HTT_RX_NUM_GI_CNTRS][ATH12K_HTT_RX_NUM_MCS_CNTRS];
1420 __le32 ul_ofdma_rx_nss[ATH12K_HTT_RX_NUM_SPATIAL_STREAMS];
1421 __le32 ul_ofdma_rx_bw[ATH12K_HTT_RX_NUM_BW_CNTRS];
1422 __le32 ul_ofdma_rx_stbc;
1423 __le32 ul_ofdma_rx_ldpc;
1424 __le32 data_ru_size_ppdu[ATH12K_HTT_RX_NUM_RU_SIZE_160MHZ_CNTRS];
1425 __le32 non_data_ru_size_ppdu[ATH12K_HTT_RX_NUM_RU_SIZE_160MHZ_CNTRS];
1426 __le32 uplink_sta_aid[ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK];
1427 __le32 uplink_sta_target_rssi[ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK];
1428 __le32 uplink_sta_fd_rssi[ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK];
1429 __le32 uplink_sta_power_headroom[ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK];
1430 __le32 red_bw[ATH12K_HTT_RX_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_RX_NUM_BW_CNTRS];
1431 __le32 ul_ofdma_bsc_trig_rx_qos_null_only;
1432 } __packed;
1433
1434 #define ATH12K_HTT_TX_UL_MUMIMO_USER_STATS 8
1435
1436 struct ath12k_htt_rx_ul_mumimo_trig_stats_tlv {
1437 __le32 mac_id__word;
1438 __le32 rx_11ax_ul_mumimo;
1439 __le32 ul_mumimo_rx_mcs[ATH12K_HTT_RX_NUM_MCS_CNTRS];
1440 __le32 ul_rx_gi[ATH12K_HTT_RX_NUM_GI_CNTRS][ATH12K_HTT_RX_NUM_MCS_CNTRS];
1441 __le32 ul_mumimo_rx_nss[ATH12K_HTT_RX_NUM_SPATIAL_STREAMS];
1442 __le32 ul_mumimo_rx_bw[ATH12K_HTT_RX_NUM_BW_CNTRS];
1443 __le32 ul_mumimo_rx_stbc;
1444 __le32 ul_mumimo_rx_ldpc;
1445 __le32 ul_mumimo_rx_mcs_ext[ATH12K_HTT_RX_NUM_EXTRA_MCS_CNTRS];
1446 __le32 ul_gi_ext[ATH12K_HTT_RX_NUM_GI_CNTRS][ATH12K_HTT_RX_NUM_EXTRA_MCS_CNTRS];
1447 s8 ul_rssi[ATH12K_HTT_RX_NUM_SPATIAL_STREAMS][ATH12K_HTT_RX_NUM_BW_CNTRS];
1448 s8 tgt_rssi[ATH12K_HTT_TX_UL_MUMIMO_USER_STATS][ATH12K_HTT_RX_NUM_BW_CNTRS];
1449 s8 fd[ATH12K_HTT_TX_UL_MUMIMO_USER_STATS][ATH12K_HTT_RX_NUM_SPATIAL_STREAMS];
1450 s8 db[ATH12K_HTT_TX_UL_MUMIMO_USER_STATS][ATH12K_HTT_RX_NUM_SPATIAL_STREAMS];
1451 __le32 red_bw[ATH12K_HTT_RX_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_RX_NUM_BW_CNTRS];
1452 __le32 mumimo_bsc_trig_rx_qos_null_only;
1453 } __packed;
1454
1455 #define ATH12K_HTT_RX_NUM_MAX_PEAK_OCCUPANCY_INDEX 10
1456 #define ATH12K_HTT_RX_NUM_MAX_CURR_OCCUPANCY_INDEX 10
1457 #define ATH12K_HTT_RX_NUM_SQUARE_INDEX 6
1458 #define ATH12K_HTT_RX_NUM_MAX_PEAK_SEARCH_INDEX 4
1459 #define ATH12K_HTT_RX_NUM_MAX_PENDING_SEARCH_INDEX 4
1460
1461 struct ath12k_htt_rx_fse_stats_tlv {
1462 __le32 fse_enable_cnt;
1463 __le32 fse_disable_cnt;
1464 __le32 fse_cache_invalidate_entry_cnt;
1465 __le32 fse_full_cache_invalidate_cnt;
1466 __le32 fse_num_cache_hits_cnt;
1467 __le32 fse_num_searches_cnt;
1468 __le32 fse_cache_occupancy_peak_cnt[ATH12K_HTT_RX_NUM_MAX_PEAK_OCCUPANCY_INDEX];
1469 __le32 fse_cache_occupancy_curr_cnt[ATH12K_HTT_RX_NUM_MAX_CURR_OCCUPANCY_INDEX];
1470 __le32 fse_search_stat_square_cnt[ATH12K_HTT_RX_NUM_SQUARE_INDEX];
1471 __le32 fse_search_stat_peak_cnt[ATH12K_HTT_RX_NUM_MAX_PEAK_SEARCH_INDEX];
1472 __le32 fse_search_stat_pending_cnt[ATH12K_HTT_RX_NUM_MAX_PENDING_SEARCH_INDEX];
1473 } __packed;
1474
1475 #define ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS 14
1476 #define ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8
1477 #define ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8
1478 #define ATH12K_HTT_TXBF_NUM_BW_CNTRS 5
1479 #define ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES 2
1480
1481 struct ath12k_htt_pdev_txrate_txbf_stats_tlv {
1482 __le32 tx_su_txbf_mcs[ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS];
1483 __le32 tx_su_ibf_mcs[ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS];
1484 __le32 tx_su_ol_mcs[ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS];
1485 __le32 tx_su_txbf_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1486 __le32 tx_su_ibf_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1487 __le32 tx_su_ol_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1488 __le32 tx_su_txbf_bw[ATH12K_HTT_TXBF_NUM_BW_CNTRS];
1489 __le32 tx_su_ibf_bw[ATH12K_HTT_TXBF_NUM_BW_CNTRS];
1490 __le32 tx_su_ol_bw[ATH12K_HTT_TXBF_NUM_BW_CNTRS];
1491 __le32 tx_legacy_ofdm_rate[ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS];
1492 __le32 txbf[ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_TXBF_NUM_BW_CNTRS];
1493 __le32 ibf[ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_TXBF_NUM_BW_CNTRS];
1494 __le32 ol[ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_TXBF_NUM_BW_CNTRS];
1495 __le32 txbf_flag_set_mu_mode;
1496 __le32 txbf_flag_set_final_status;
1497 __le32 txbf_flag_not_set_verified_txbf_mode;
1498 __le32 txbf_flag_not_set_disable_p2p_access;
1499 __le32 txbf_flag_not_set_max_nss_in_he160;
1500 __le32 txbf_flag_not_set_disable_uldlofdma;
1501 __le32 txbf_flag_not_set_mcs_threshold_val;
1502 __le32 txbf_flag_not_set_final_status;
1503 } __packed;
1504
1505 struct ath12k_htt_txbf_ofdma_ax_ndpa_stats_elem_t {
1506 __le32 ax_ofdma_ndpa_queued;
1507 __le32 ax_ofdma_ndpa_tried;
1508 __le32 ax_ofdma_ndpa_flush;
1509 __le32 ax_ofdma_ndpa_err;
1510 } __packed;
1511
1512 struct ath12k_htt_txbf_ofdma_ax_ndpa_stats_tlv {
1513 __le32 num_elems_ax_ndpa_arr;
1514 __le32 arr_elem_size_ax_ndpa;
1515 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_ndpa_stats_elem_t, ax_ndpa);
1516 } __packed;
1517
1518 struct ath12k_htt_txbf_ofdma_ax_ndp_stats_elem_t {
1519 __le32 ax_ofdma_ndp_queued;
1520 __le32 ax_ofdma_ndp_tried;
1521 __le32 ax_ofdma_ndp_flush;
1522 __le32 ax_ofdma_ndp_err;
1523 } __packed;
1524
1525 struct ath12k_htt_txbf_ofdma_ax_ndp_stats_tlv {
1526 __le32 num_elems_ax_ndp_arr;
1527 __le32 arr_elem_size_ax_ndp;
1528 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_ndp_stats_elem_t, ax_ndp);
1529 } __packed;
1530
1531 struct ath12k_htt_txbf_ofdma_ax_brp_stats_elem_t {
1532 __le32 ax_ofdma_brp_queued;
1533 __le32 ax_ofdma_brp_tried;
1534 __le32 ax_ofdma_brp_flushed;
1535 __le32 ax_ofdma_brp_err;
1536 __le32 ax_ofdma_num_cbf_rcvd;
1537 } __packed;
1538
1539 struct ath12k_htt_txbf_ofdma_ax_brp_stats_tlv {
1540 __le32 num_elems_ax_brp_arr;
1541 __le32 arr_elem_size_ax_brp;
1542 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_brp_stats_elem_t, ax_brp);
1543 } __packed;
1544
1545 struct ath12k_htt_txbf_ofdma_ax_steer_stats_elem_t {
1546 __le32 num_ppdu_steer;
1547 __le32 num_ppdu_ol;
1548 __le32 num_usr_prefetch;
1549 __le32 num_usr_sound;
1550 __le32 num_usr_force_sound;
1551 } __packed;
1552
1553 struct ath12k_htt_txbf_ofdma_ax_steer_stats_tlv {
1554 __le32 num_elems_ax_steer_arr;
1555 __le32 arr_elem_size_ax_steer;
1556 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_steer_stats_elem_t, ax_steer);
1557 } __packed;
1558
1559 struct ath12k_htt_txbf_ofdma_ax_steer_mpdu_stats_tlv {
1560 __le32 ax_ofdma_rbo_steer_mpdus_tried;
1561 __le32 ax_ofdma_rbo_steer_mpdus_failed;
1562 __le32 ax_ofdma_sifs_steer_mpdus_tried;
1563 __le32 ax_ofdma_sifs_steer_mpdus_failed;
1564 } __packed;
1565
1566 enum ath12k_htt_stats_page_lock_state {
1567 ATH12K_HTT_STATS_PAGE_LOCKED = 0,
1568 ATH12K_HTT_STATS_PAGE_UNLOCKED = 1,
1569 ATH12K_NUM_PG_LOCK_STATE
1570 };
1571
1572 #define ATH12K_PAGER_MAX 10
1573
1574 #define ATH12K_HTT_DLPAGER_ASYNC_LOCK_PG_CNT_INFO0 GENMASK(7, 0)
1575 #define ATH12K_HTT_DLPAGER_SYNC_LOCK_PG_CNT_INFO0 GENMASK(15, 8)
1576 #define ATH12K_HTT_DLPAGER_TOTAL_LOCK_PAGES_INFO1 GENMASK(15, 0)
1577 #define ATH12K_HTT_DLPAGER_TOTAL_FREE_PAGES_INFO1 GENMASK(31, 16)
1578 #define ATH12K_HTT_DLPAGER_TOTAL_LOCK_PAGES_INFO2 GENMASK(15, 0)
1579 #define ATH12K_HTT_DLPAGER_TOTAL_FREE_PAGES_INFO2 GENMASK(31, 16)
1580
1581 struct ath12k_htt_pgs_info {
1582 __le32 page_num;
1583 __le32 num_pgs;
1584 __le32 ts_lsb;
1585 __le32 ts_msb;
1586 } __packed;
1587
1588 struct ath12k_htt_dl_pager_stats_tlv {
1589 __le32 info0;
1590 __le32 info1;
1591 __le32 info2;
1592 struct ath12k_htt_pgs_info pgs_info[ATH12K_NUM_PG_LOCK_STATE][ATH12K_PAGER_MAX];
1593 } __packed;
1594
1595 #define ATH12K_HTT_STATS_MAX_CHAINS 8
1596 #define ATH12K_HTT_MAX_RX_PKT_CNT 8
1597 #define ATH12K_HTT_MAX_RX_PKT_CRC_PASS_CNT 8
1598 #define ATH12K_HTT_MAX_PER_BLK_ERR_CNT 20
1599 #define ATH12K_HTT_MAX_RX_OTA_ERR_CNT 14
1600 #define ATH12K_HTT_MAX_CH_PWR_INFO_SIZE 16
1601
1602 struct ath12k_htt_phy_stats_tlv {
1603 a_sle32 nf_chain[ATH12K_HTT_STATS_MAX_CHAINS];
1604 __le32 false_radar_cnt;
1605 __le32 radar_cs_cnt;
1606 a_sle32 ani_level;
1607 __le32 fw_run_time;
1608 a_sle32 runtime_nf_chain[ATH12K_HTT_STATS_MAX_CHAINS];
1609 } __packed;
1610
1611 struct ath12k_htt_phy_counters_tlv {
1612 __le32 rx_ofdma_timing_err_cnt;
1613 __le32 rx_cck_fail_cnt;
1614 __le32 mactx_abort_cnt;
1615 __le32 macrx_abort_cnt;
1616 __le32 phytx_abort_cnt;
1617 __le32 phyrx_abort_cnt;
1618 __le32 phyrx_defer_abort_cnt;
1619 __le32 rx_gain_adj_lstf_event_cnt;
1620 __le32 rx_gain_adj_non_legacy_cnt;
1621 __le32 rx_pkt_cnt[ATH12K_HTT_MAX_RX_PKT_CNT];
1622 __le32 rx_pkt_crc_pass_cnt[ATH12K_HTT_MAX_RX_PKT_CRC_PASS_CNT];
1623 __le32 per_blk_err_cnt[ATH12K_HTT_MAX_PER_BLK_ERR_CNT];
1624 __le32 rx_ota_err_cnt[ATH12K_HTT_MAX_RX_OTA_ERR_CNT];
1625 } __packed;
1626
1627 struct ath12k_htt_phy_reset_stats_tlv {
1628 __le32 pdev_id;
1629 __le32 chan_mhz;
1630 __le32 chan_band_center_freq1;
1631 __le32 chan_band_center_freq2;
1632 __le32 chan_phy_mode;
1633 __le32 chan_flags;
1634 __le32 chan_num;
1635 __le32 reset_cause;
1636 __le32 prev_reset_cause;
1637 __le32 phy_warm_reset_src;
1638 __le32 rx_gain_tbl_mode;
1639 __le32 xbar_val;
1640 __le32 force_calibration;
1641 __le32 phyrf_mode;
1642 __le32 phy_homechan;
1643 __le32 phy_tx_ch_mask;
1644 __le32 phy_rx_ch_mask;
1645 __le32 phybb_ini_mask;
1646 __le32 phyrf_ini_mask;
1647 __le32 phy_dfs_en_mask;
1648 __le32 phy_sscan_en_mask;
1649 __le32 phy_synth_sel_mask;
1650 __le32 phy_adfs_freq;
1651 __le32 cck_fir_settings;
1652 __le32 phy_dyn_pri_chan;
1653 __le32 cca_thresh;
1654 __le32 dyn_cca_status;
1655 __le32 rxdesense_thresh_hw;
1656 __le32 rxdesense_thresh_sw;
1657 } __packed;
1658
1659 struct ath12k_htt_phy_reset_counters_tlv {
1660 __le32 pdev_id;
1661 __le32 cf_active_low_fail_cnt;
1662 __le32 cf_active_low_pass_cnt;
1663 __le32 phy_off_through_vreg_cnt;
1664 __le32 force_calibration_cnt;
1665 __le32 rf_mode_switch_phy_off_cnt;
1666 __le32 temperature_recal_cnt;
1667 } __packed;
1668
1669 struct ath12k_htt_phy_tpc_stats_tlv {
1670 __le32 pdev_id;
1671 __le32 tx_power_scale;
1672 __le32 tx_power_scale_db;
1673 __le32 min_negative_tx_power;
1674 __le32 reg_ctl_domain;
1675 __le32 max_reg_allowed_power[ATH12K_HTT_STATS_MAX_CHAINS];
1676 __le32 max_reg_allowed_power_6ghz[ATH12K_HTT_STATS_MAX_CHAINS];
1677 __le32 twice_max_rd_power;
1678 __le32 max_tx_power;
1679 __le32 home_max_tx_power;
1680 __le32 psd_power;
1681 __le32 eirp_power;
1682 __le32 power_type_6ghz;
1683 __le32 sub_band_cfreq[ATH12K_HTT_MAX_CH_PWR_INFO_SIZE];
1684 __le32 sub_band_txpower[ATH12K_HTT_MAX_CH_PWR_INFO_SIZE];
1685 } __packed;
1686
1687 struct ath12k_htt_t2h_soc_txrx_stats_common_tlv {
1688 __le32 inv_peers_msdu_drop_count_hi;
1689 __le32 inv_peers_msdu_drop_count_lo;
1690 } __packed;
1691
1692 #define ATH12K_HTT_AST_PDEV_ID_INFO GENMASK(1, 0)
1693 #define ATH12K_HTT_AST_VDEV_ID_INFO GENMASK(9, 2)
1694 #define ATH12K_HTT_AST_NEXT_HOP_INFO BIT(10)
1695 #define ATH12K_HTT_AST_MCAST_INFO BIT(11)
1696 #define ATH12K_HTT_AST_MONITOR_DIRECT_INFO BIT(12)
1697 #define ATH12K_HTT_AST_MESH_STA_INFO BIT(13)
1698 #define ATH12K_HTT_AST_MEC_INFO BIT(14)
1699 #define ATH12K_HTT_AST_INTRA_BSS_INFO BIT(15)
1700
1701 struct ath12k_htt_ast_entry_tlv {
1702 __le32 sw_peer_id;
1703 __le32 ast_index;
1704 struct htt_mac_addr mac_addr;
1705 __le32 info;
1706 } __packed;
1707
1708 enum ath12k_htt_stats_direction {
1709 ATH12K_HTT_STATS_DIRECTION_TX,
1710 ATH12K_HTT_STATS_DIRECTION_RX
1711 };
1712
1713 enum ath12k_htt_stats_ppdu_type {
1714 ATH12K_HTT_STATS_PPDU_TYPE_MODE_SU,
1715 ATH12K_HTT_STATS_PPDU_TYPE_DL_MU_MIMO,
1716 ATH12K_HTT_STATS_PPDU_TYPE_UL_MU_MIMO,
1717 ATH12K_HTT_STATS_PPDU_TYPE_DL_MU_OFDMA,
1718 ATH12K_HTT_STATS_PPDU_TYPE_UL_MU_OFDMA
1719 };
1720
1721 enum ath12k_htt_stats_param_type {
1722 ATH12K_HTT_STATS_PREAM_OFDM,
1723 ATH12K_HTT_STATS_PREAM_CCK,
1724 ATH12K_HTT_STATS_PREAM_HT,
1725 ATH12K_HTT_STATS_PREAM_VHT,
1726 ATH12K_HTT_STATS_PREAM_HE,
1727 ATH12K_HTT_STATS_PREAM_EHT,
1728 ATH12K_HTT_STATS_PREAM_RSVD1,
1729 ATH12K_HTT_STATS_PREAM_COUNT,
1730 };
1731
1732 #define ATH12K_HTT_PUNCT_STATS_MAX_SUBBAND_CNT 32
1733
1734 struct ath12k_htt_pdev_puncture_stats_tlv {
1735 __le32 mac_id__word;
1736 __le32 direction;
1737 __le32 preamble;
1738 __le32 ppdu_type;
1739 __le32 subband_cnt;
1740 __le32 last_used_pattern_mask;
1741 __le32 num_subbands_used_cnt[ATH12K_HTT_PUNCT_STATS_MAX_SUBBAND_CNT];
1742 } __packed;
1743
1744 struct ath12k_htt_dmac_reset_stats_tlv {
1745 __le32 reset_count;
1746 __le32 reset_time_lo_ms;
1747 __le32 reset_time_hi_ms;
1748 __le32 disengage_time_lo_ms;
1749 __le32 disengage_time_hi_ms;
1750 __le32 engage_time_lo_ms;
1751 __le32 engage_time_hi_ms;
1752 __le32 disengage_count;
1753 __le32 engage_count;
1754 __le32 drain_dest_ring_mask;
1755 } __packed;
1756
1757 struct ath12k_htt_pdev_sched_algo_ofdma_stats_tlv {
1758 __le32 mac_id__word;
1759 __le32 rate_based_dlofdma_enabled_cnt[ATH12K_HTT_NUM_AC_WMM];
1760 __le32 rate_based_dlofdma_disabled_cnt[ATH12K_HTT_NUM_AC_WMM];
1761 __le32 rate_based_dlofdma_probing_cnt[ATH12K_HTT_NUM_AC_WMM];
1762 __le32 rate_based_dlofdma_monitor_cnt[ATH12K_HTT_NUM_AC_WMM];
1763 __le32 chan_acc_lat_based_dlofdma_enabled_cnt[ATH12K_HTT_NUM_AC_WMM];
1764 __le32 chan_acc_lat_based_dlofdma_disabled_cnt[ATH12K_HTT_NUM_AC_WMM];
1765 __le32 chan_acc_lat_based_dlofdma_monitor_cnt[ATH12K_HTT_NUM_AC_WMM];
1766 __le32 downgrade_to_dl_su_ru_alloc_fail[ATH12K_HTT_NUM_AC_WMM];
1767 __le32 candidate_list_single_user_disable_ofdma[ATH12K_HTT_NUM_AC_WMM];
1768 __le32 dl_cand_list_dropped_high_ul_qos_weight[ATH12K_HTT_NUM_AC_WMM];
1769 __le32 ax_dlofdma_disabled_due_to_pipelining[ATH12K_HTT_NUM_AC_WMM];
1770 __le32 dlofdma_disabled_su_only_eligible[ATH12K_HTT_NUM_AC_WMM];
1771 __le32 dlofdma_disabled_consec_no_mpdus_tried[ATH12K_HTT_NUM_AC_WMM];
1772 __le32 dlofdma_disabled_consec_no_mpdus_success[ATH12K_HTT_NUM_AC_WMM];
1773 } __packed;
1774
1775 #define ATH12K_HTT_TX_PDEV_STATS_NUM_BW_CNTRS 4
1776 #define ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS 8
1777 #define ATH12K_HTT_TXBF_RATE_STAT_NUM_MCS_CNTRS 14
1778
1779 enum ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE {
1780 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_26,
1781 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_52,
1782 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_52_26,
1783 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_106,
1784 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_106_26,
1785 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_242,
1786 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_484,
1787 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_484_242,
1788 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996,
1789 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996_484,
1790 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996_484_242,
1791 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x2,
1792 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x2_484,
1793 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x3,
1794 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x3_484,
1795 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x4,
1796 ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS,
1797 };
1798
1799 enum ATH12K_HTT_RC_MODE {
1800 ATH12K_HTT_RC_MODE_SU_OL,
1801 ATH12K_HTT_RC_MODE_SU_BF,
1802 ATH12K_HTT_RC_MODE_MU1_INTF,
1803 ATH12K_HTT_RC_MODE_MU2_INTF,
1804 ATH12K_HTT_RC_MODE_MU3_INTF,
1805 ATH12K_HTT_RC_MODE_MU4_INTF,
1806 ATH12K_HTT_RC_MODE_MU5_INTF,
1807 ATH12K_HTT_RC_MODE_MU6_INTF,
1808 ATH12K_HTT_RC_MODE_MU7_INTF,
1809 ATH12K_HTT_RC_MODE_2D_COUNT
1810 };
1811
1812 enum ath12k_htt_stats_rc_mode {
1813 ATH12K_HTT_STATS_RC_MODE_DLSU = 0,
1814 ATH12K_HTT_STATS_RC_MODE_DLMUMIMO = 1,
1815 ATH12K_HTT_STATS_RC_MODE_DLOFDMA = 2,
1816 ATH12K_HTT_STATS_RC_MODE_ULMUMIMO = 3,
1817 ATH12K_HTT_STATS_RC_MODE_ULOFDMA = 4,
1818 };
1819
1820 enum ath12k_htt_stats_ru_type {
1821 ATH12K_HTT_STATS_RU_TYPE_INVALID,
1822 ATH12K_HTT_STATS_RU_TYPE_SINGLE_RU_ONLY,
1823 ATH12K_HTT_STATS_RU_TYPE_SINGLE_AND_MULTI_RU,
1824 };
1825
1826 struct ath12k_htt_tx_rate_stats {
1827 __le32 ppdus_tried;
1828 __le32 ppdus_ack_failed;
1829 __le32 mpdus_tried;
1830 __le32 mpdus_failed;
1831 } __packed;
1832
1833 struct ath12k_htt_tx_per_rate_stats_tlv {
1834 __le32 rc_mode;
1835 __le32 last_probed_mcs;
1836 __le32 last_probed_nss;
1837 __le32 last_probed_bw;
1838 struct ath12k_htt_tx_rate_stats per_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_CNTRS];
1839 struct ath12k_htt_tx_rate_stats per_nss[ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS];
1840 struct ath12k_htt_tx_rate_stats per_mcs[ATH12K_HTT_TXBF_RATE_STAT_NUM_MCS_CNTRS];
1841 struct ath12k_htt_tx_rate_stats per_bw320;
1842 __le32 probe_cnt[ATH12K_HTT_RC_MODE_2D_COUNT];
1843 __le32 ru_type;
1844 struct ath12k_htt_tx_rate_stats ru[ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS];
1845 } __packed;
1846
1847 #define ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS 16
1848 #define ATH12K_HTT_TX_PDEV_NUM_BE_BW_CNTRS 5
1849 #define ATH12K_HTT_TX_PDEV_NUM_EHT_SIG_MCS_CNTRS 4
1850 #define ATH12K_HTT_TX_PDEV_NUM_GI_CNTRS 4
1851
1852 struct ath12k_htt_tx_pdev_rate_stats_be_ofdma_tlv {
1853 __le32 mac_id__word;
1854 __le32 be_ofdma_tx_ldpc;
1855 __le32 be_ofdma_tx_mcs[ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS];
1856 __le32 be_ofdma_tx_nss[ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS];
1857 __le32 be_ofdma_tx_bw[ATH12K_HTT_TX_PDEV_NUM_BE_BW_CNTRS];
1858 __le32 gi[ATH12K_HTT_TX_PDEV_NUM_GI_CNTRS][ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS];
1859 __le32 be_ofdma_tx_ru_size[ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS];
1860 __le32 be_ofdma_eht_sig_mcs[ATH12K_HTT_TX_PDEV_NUM_EHT_SIG_MCS_CNTRS];
1861 } __packed;
1862
1863 struct ath12k_htt_pdev_mbssid_ctrl_frame_tlv {
1864 __le32 mac_id__word;
1865 __le32 basic_trigger_across_bss;
1866 __le32 basic_trigger_within_bss;
1867 __le32 bsr_trigger_across_bss;
1868 __le32 bsr_trigger_within_bss;
1869 __le32 mu_rts_across_bss;
1870 __le32 mu_rts_within_bss;
1871 __le32 ul_mumimo_trigger_across_bss;
1872 __le32 ul_mumimo_trigger_within_bss;
1873 } __packed;
1874
1875 #endif
1876