1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6 #include "qla_def.h"
7
8 #include <linux/bitfield.h>
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <linux/refcount.h>
17 #include <linux/crash_dump.h>
18 #include <linux/trace_events.h>
19 #include <linux/trace.h>
20
21 #include <scsi/scsi_tcq.h>
22 #include <scsi/scsicam.h>
23 #include <scsi/scsi_transport.h>
24 #include <scsi/scsi_transport_fc.h>
25
26 #include "qla_target.h"
27
28 /*
29 * Driver version
30 */
31 char qla2x00_version_str[40];
32
33 static int apidev_major;
34
35 /*
36 * SRB allocation cache
37 */
38 struct kmem_cache *srb_cachep;
39
40 static struct trace_array *qla_trc_array;
41
42 int ql2xfulldump_on_mpifail;
43 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR);
44 MODULE_PARM_DESC(ql2xfulldump_on_mpifail,
45 "Set this to take full dump on MPI hang.");
46
47 int ql2xenforce_iocb_limit = 2;
48 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR);
49 MODULE_PARM_DESC(ql2xenforce_iocb_limit,
50 "Enforce IOCB throttling, to avoid FW congestion. (default: 2) "
51 "1: track usage per queue, 2: track usage per adapter");
52
53 /*
54 * CT6 CTX allocation cache
55 */
56 static struct kmem_cache *ctx_cachep;
57 /*
58 * error level for logging
59 */
60 uint ql_errlev = 0x8001;
61
62 int ql2xsecenable;
63 module_param(ql2xsecenable, int, S_IRUGO);
64 MODULE_PARM_DESC(ql2xsecenable,
65 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled.");
66
67 static int ql2xenableclass2;
68 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
69 MODULE_PARM_DESC(ql2xenableclass2,
70 "Specify if Class 2 operations are supported from the very "
71 "beginning. Default is 0 - class 2 not supported.");
72
73
74 int ql2xlogintimeout = 20;
75 module_param(ql2xlogintimeout, int, S_IRUGO);
76 MODULE_PARM_DESC(ql2xlogintimeout,
77 "Login timeout value in seconds.");
78
79 int qlport_down_retry;
80 module_param(qlport_down_retry, int, S_IRUGO);
81 MODULE_PARM_DESC(qlport_down_retry,
82 "Maximum number of command retries to a port that returns "
83 "a PORT-DOWN status.");
84
85 int ql2xplogiabsentdevice;
86 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
87 MODULE_PARM_DESC(ql2xplogiabsentdevice,
88 "Option to enable PLOGI to devices that are not present after "
89 "a Fabric scan. This is needed for several broken switches. "
90 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
91
92 int ql2xloginretrycount;
93 module_param(ql2xloginretrycount, int, S_IRUGO);
94 MODULE_PARM_DESC(ql2xloginretrycount,
95 "Specify an alternate value for the NVRAM login retry count.");
96
97 int ql2xallocfwdump = 1;
98 module_param(ql2xallocfwdump, int, S_IRUGO);
99 MODULE_PARM_DESC(ql2xallocfwdump,
100 "Option to enable allocation of memory for a firmware dump "
101 "during HBA initialization. Memory allocation requirements "
102 "vary by ISP type. Default is 1 - allocate memory.");
103
104 int ql2xextended_error_logging;
105 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
106 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
107 MODULE_PARM_DESC(ql2xextended_error_logging,
108 "Option to enable extended error logging,\n"
109 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
110 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
111 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
112 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
113 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
114 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
115 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
116 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
117 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
118 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
119 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
120 "\t\t0x1e400000 - Preferred value for capturing essential "
121 "debug information (equivalent to old "
122 "ql2xextended_error_logging=1).\n"
123 "\t\tDo LOGICAL OR of the value to enable more than one level");
124
125 int ql2xextended_error_logging_ktrace = 1;
126 module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR);
127 MODULE_PARM_DESC(ql2xextended_error_logging_ktrace,
128 "Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n");
129
130 int ql2xshiftctondsd = 6;
131 module_param(ql2xshiftctondsd, int, S_IRUGO);
132 MODULE_PARM_DESC(ql2xshiftctondsd,
133 "Set to control shifting of command type processing "
134 "based on total number of SG elements.");
135
136 int ql2xfdmienable = 1;
137 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
138 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
139 MODULE_PARM_DESC(ql2xfdmienable,
140 "Enables FDMI registrations. "
141 "0 - no FDMI registrations. "
142 "1 - provide FDMI registrations (default).");
143
144 #define MAX_Q_DEPTH 64
145 static int ql2xmaxqdepth = MAX_Q_DEPTH;
146 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
147 MODULE_PARM_DESC(ql2xmaxqdepth,
148 "Maximum queue depth to set for each LUN. "
149 "Default is 64.");
150
151 int ql2xenabledif = 2;
152 module_param(ql2xenabledif, int, S_IRUGO);
153 MODULE_PARM_DESC(ql2xenabledif,
154 " Enable T10-CRC-DIF:\n"
155 " Default is 2.\n"
156 " 0 -- No DIF Support\n"
157 " 1 -- Enable DIF for all types\n"
158 " 2 -- Enable DIF for all types, except Type 0.\n");
159
160 #if (IS_ENABLED(CONFIG_NVME_FC))
161 int ql2xnvmeenable = 1;
162 #else
163 int ql2xnvmeenable;
164 #endif
165 module_param(ql2xnvmeenable, int, 0644);
166 MODULE_PARM_DESC(ql2xnvmeenable,
167 "Enables NVME support. "
168 "0 - no NVMe. Default is Y");
169
170 int ql2xenablehba_err_chk = 2;
171 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
172 MODULE_PARM_DESC(ql2xenablehba_err_chk,
173 " Enable T10-CRC-DIF Error isolation by HBA:\n"
174 " Default is 2.\n"
175 " 0 -- Error isolation disabled\n"
176 " 1 -- Error isolation enabled only for DIX Type 0\n"
177 " 2 -- Error isolation enabled for all Types\n");
178
179 int ql2xmqsupport = 1;
180 module_param(ql2xmqsupport, int, S_IRUGO);
181 MODULE_PARM_DESC(ql2xmqsupport,
182 "Enable on demand multiple queue pairs support "
183 "Default is 1 for supported. "
184 "Set it to 0 to turn off mq qpair support.");
185
186 int ql2xfwloadbin;
187 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
188 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
189 MODULE_PARM_DESC(ql2xfwloadbin,
190 "Option to specify location from which to load ISP firmware:.\n"
191 " 2 -- load firmware via the request_firmware() (hotplug).\n"
192 " interface.\n"
193 " 1 -- load firmware from flash.\n"
194 " 0 -- use default semantics.\n");
195
196 int ql2xdbwr = 1;
197 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
198 MODULE_PARM_DESC(ql2xdbwr,
199 "Option to specify scheme for request queue posting.\n"
200 " 0 -- Regular doorbell.\n"
201 " 1 -- CAMRAM doorbell (faster).\n");
202
203 int ql2xgffidenable;
204 module_param(ql2xgffidenable, int, S_IRUGO);
205 MODULE_PARM_DESC(ql2xgffidenable,
206 "Enables GFF_ID checks of port type. "
207 "Default is 0 - Do not use GFF_ID information.");
208
209 int ql2xasynctmfenable = 1;
210 module_param(ql2xasynctmfenable, int, S_IRUGO);
211 MODULE_PARM_DESC(ql2xasynctmfenable,
212 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
213 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
214
215 int ql2xdontresethba;
216 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
217 MODULE_PARM_DESC(ql2xdontresethba,
218 "Option to specify reset behaviour.\n"
219 " 0 (Default) -- Reset on failure.\n"
220 " 1 -- Do not reset on failure.\n");
221
222 uint64_t ql2xmaxlun = MAX_LUNS;
223 module_param(ql2xmaxlun, ullong, S_IRUGO);
224 MODULE_PARM_DESC(ql2xmaxlun,
225 "Defines the maximum LU number to register with the SCSI "
226 "midlayer. Default is 65535.");
227
228 int ql2xmdcapmask = 0x1F;
229 module_param(ql2xmdcapmask, int, S_IRUGO);
230 MODULE_PARM_DESC(ql2xmdcapmask,
231 "Set the Minidump driver capture mask level. "
232 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
233
234 int ql2xmdenable = 1;
235 module_param(ql2xmdenable, int, S_IRUGO);
236 MODULE_PARM_DESC(ql2xmdenable,
237 "Enable/disable MiniDump. "
238 "0 - MiniDump disabled. "
239 "1 (Default) - MiniDump enabled.");
240
241 int ql2xexlogins;
242 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
243 MODULE_PARM_DESC(ql2xexlogins,
244 "Number of extended Logins. "
245 "0 (Default)- Disabled.");
246
247 int ql2xexchoffld = 1024;
248 module_param(ql2xexchoffld, uint, 0644);
249 MODULE_PARM_DESC(ql2xexchoffld,
250 "Number of target exchanges.");
251
252 int ql2xiniexchg = 1024;
253 module_param(ql2xiniexchg, uint, 0644);
254 MODULE_PARM_DESC(ql2xiniexchg,
255 "Number of initiator exchanges.");
256
257 int ql2xfwholdabts;
258 module_param(ql2xfwholdabts, int, S_IRUGO);
259 MODULE_PARM_DESC(ql2xfwholdabts,
260 "Allow FW to hold status IOCB until ABTS rsp received. "
261 "0 (Default) Do not set fw option. "
262 "1 - Set fw option to hold ABTS.");
263
264 int ql2xmvasynctoatio = 1;
265 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
266 MODULE_PARM_DESC(ql2xmvasynctoatio,
267 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
268 "0 (Default). Do not move IOCBs"
269 "1 - Move IOCBs.");
270
271 int ql2xautodetectsfp = 1;
272 module_param(ql2xautodetectsfp, int, 0444);
273 MODULE_PARM_DESC(ql2xautodetectsfp,
274 "Detect SFP range and set appropriate distance.\n"
275 "1 (Default): Enable\n");
276
277 int ql2xenablemsix = 1;
278 module_param(ql2xenablemsix, int, 0444);
279 MODULE_PARM_DESC(ql2xenablemsix,
280 "Set to enable MSI or MSI-X interrupt mechanism.\n"
281 " Default is 1, enable MSI-X interrupt mechanism.\n"
282 " 0 -- enable traditional pin-based mechanism.\n"
283 " 1 -- enable MSI-X interrupt mechanism.\n"
284 " 2 -- enable MSI interrupt mechanism.\n");
285
286 int qla2xuseresexchforels;
287 module_param(qla2xuseresexchforels, int, 0444);
288 MODULE_PARM_DESC(qla2xuseresexchforels,
289 "Reserve 1/2 of emergency exchanges for ELS.\n"
290 " 0 (default): disabled");
291
292 static int ql2xprotmask;
293 module_param(ql2xprotmask, int, 0644);
294 MODULE_PARM_DESC(ql2xprotmask,
295 "Override DIF/DIX protection capabilities mask\n"
296 "Default is 0 which sets protection mask based on "
297 "capabilities reported by HBA firmware.\n");
298
299 static int ql2xprotguard;
300 module_param(ql2xprotguard, int, 0644);
301 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
302 " 0 -- Let HBA firmware decide\n"
303 " 1 -- Force T10 CRC\n"
304 " 2 -- Force IP checksum\n");
305
306 int ql2xdifbundlinginternalbuffers;
307 module_param(ql2xdifbundlinginternalbuffers, int, 0644);
308 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
309 "Force using internal buffers for DIF information\n"
310 "0 (Default). Based on check.\n"
311 "1 Force using internal buffers\n");
312
313 int ql2xsmartsan;
314 module_param(ql2xsmartsan, int, 0444);
315 module_param_named(smartsan, ql2xsmartsan, int, 0444);
316 MODULE_PARM_DESC(ql2xsmartsan,
317 "Send SmartSAN Management Attributes for FDMI Registration."
318 " Default is 0 - No SmartSAN registration,"
319 " 1 - Register SmartSAN Management Attributes.");
320
321 int ql2xrdpenable;
322 module_param(ql2xrdpenable, int, 0444);
323 module_param_named(rdpenable, ql2xrdpenable, int, 0444);
324 MODULE_PARM_DESC(ql2xrdpenable,
325 "Enables RDP responses. "
326 "0 - no RDP responses (default). "
327 "1 - provide RDP responses.");
328 int ql2xabts_wait_nvme = 1;
329 module_param(ql2xabts_wait_nvme, int, 0444);
330 MODULE_PARM_DESC(ql2xabts_wait_nvme,
331 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)");
332
333
334 static u32 ql2xdelay_before_pci_error_handling = 5;
335 module_param(ql2xdelay_before_pci_error_handling, uint, 0644);
336 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling,
337 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n");
338
339 static void qla2x00_clear_drv_active(struct qla_hw_data *);
340 static void qla2x00_free_device(scsi_qla_host_t *);
341 static void qla2xxx_map_queues(struct Scsi_Host *shost);
342 static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
343
344 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES;
345 module_param(ql2xnvme_queues, uint, S_IRUGO);
346 MODULE_PARM_DESC(ql2xnvme_queues,
347 "Number of NVMe Queues that can be configured.\n"
348 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n"
349 "1 - Minimum number of queues supported\n"
350 "8 - Default value");
351
352 int ql2xfc2target = 1;
353 module_param(ql2xfc2target, int, 0444);
354 MODULE_PARM_DESC(qla2xfc2target,
355 "Enables FC2 Target support. "
356 "0 - FC2 Target support is disabled. "
357 "1 - FC2 Target support is enabled (default).");
358
359 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
360 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
361
362 /* TODO Convert to inlines
363 *
364 * Timer routines
365 */
366
367 __inline__ void
qla2x00_start_timer(scsi_qla_host_t * vha,unsigned long interval)368 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
369 {
370 timer_setup(&vha->timer, qla2x00_timer, 0);
371 vha->timer.expires = jiffies + interval * HZ;
372 add_timer(&vha->timer);
373 vha->timer_active = 1;
374 }
375
376 static inline void
qla2x00_restart_timer(scsi_qla_host_t * vha,unsigned long interval)377 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
378 {
379 /* Currently used for 82XX only. */
380 if (vha->device_flags & DFLG_DEV_FAILED) {
381 ql_dbg(ql_dbg_timer, vha, 0x600d,
382 "Device in a failed state, returning.\n");
383 return;
384 }
385
386 mod_timer(&vha->timer, jiffies + interval * HZ);
387 }
388
389 static __inline__ void
qla2x00_stop_timer(scsi_qla_host_t * vha)390 qla2x00_stop_timer(scsi_qla_host_t *vha)
391 {
392 timer_delete_sync(&vha->timer);
393 vha->timer_active = 0;
394 }
395
396 static int qla2x00_do_dpc(void *data);
397
398 static void qla2x00_rst_aen(scsi_qla_host_t *);
399
400 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
401 struct req_que **, struct rsp_que **);
402 static void qla2x00_free_fw_dump(struct qla_hw_data *);
403 static void qla2x00_mem_free(struct qla_hw_data *);
404 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
405 struct qla_qpair *qpair);
406
407 /* -------------------------------------------------------------------------- */
qla_init_base_qpair(struct scsi_qla_host * vha,struct req_que * req,struct rsp_que * rsp)408 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
409 struct rsp_que *rsp)
410 {
411 struct qla_hw_data *ha = vha->hw;
412
413 rsp->qpair = ha->base_qpair;
414 rsp->req = req;
415 ha->base_qpair->hw = ha;
416 ha->base_qpair->req = req;
417 ha->base_qpair->rsp = rsp;
418 ha->base_qpair->vha = vha;
419 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
420 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
421 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
422 ha->base_qpair->srb_mempool = ha->srb_mempool;
423 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
424 INIT_LIST_HEAD(&ha->base_qpair->dsd_list);
425 ha->base_qpair->enable_class_2 = ql2xenableclass2;
426 /* init qpair to this cpu. Will adjust at run time. */
427 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
428 ha->base_qpair->pdev = ha->pdev;
429
430 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
431 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
432 }
433
qla2x00_alloc_queues(struct qla_hw_data * ha,struct req_que * req,struct rsp_que * rsp)434 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
435 struct rsp_que *rsp)
436 {
437 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
438
439 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
440 GFP_KERNEL);
441 if (!ha->req_q_map) {
442 ql_log(ql_log_fatal, vha, 0x003b,
443 "Unable to allocate memory for request queue ptrs.\n");
444 goto fail_req_map;
445 }
446
447 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
448 GFP_KERNEL);
449 if (!ha->rsp_q_map) {
450 ql_log(ql_log_fatal, vha, 0x003c,
451 "Unable to allocate memory for response queue ptrs.\n");
452 goto fail_rsp_map;
453 }
454
455 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
456 if (ha->base_qpair == NULL) {
457 ql_log(ql_log_warn, vha, 0x00e0,
458 "Failed to allocate base queue pair memory.\n");
459 goto fail_base_qpair;
460 }
461
462 qla_init_base_qpair(vha, req, rsp);
463
464 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
465 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
466 GFP_KERNEL);
467 if (!ha->queue_pair_map) {
468 ql_log(ql_log_fatal, vha, 0x0180,
469 "Unable to allocate memory for queue pair ptrs.\n");
470 goto fail_qpair_map;
471 }
472 if (qla_mapq_alloc_qp_cpu_map(ha) != 0) {
473 kfree(ha->queue_pair_map);
474 ha->queue_pair_map = NULL;
475 goto fail_qpair_map;
476 }
477 }
478
479 /*
480 * Make sure we record at least the request and response queue zero in
481 * case we need to free them if part of the probe fails.
482 */
483 ha->rsp_q_map[0] = rsp;
484 ha->req_q_map[0] = req;
485 set_bit(0, ha->rsp_qid_map);
486 set_bit(0, ha->req_qid_map);
487 return 0;
488
489 fail_qpair_map:
490 kfree(ha->base_qpair);
491 ha->base_qpair = NULL;
492 fail_base_qpair:
493 kfree(ha->rsp_q_map);
494 ha->rsp_q_map = NULL;
495 fail_rsp_map:
496 kfree(ha->req_q_map);
497 ha->req_q_map = NULL;
498 fail_req_map:
499 return -ENOMEM;
500 }
501
qla2x00_free_req_que(struct qla_hw_data * ha,struct req_que * req)502 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
503 {
504 if (IS_QLAFX00(ha)) {
505 if (req && req->ring_fx00)
506 dma_free_coherent(&ha->pdev->dev,
507 (req->length_fx00 + 1) * sizeof(request_t),
508 req->ring_fx00, req->dma_fx00);
509 } else if (req && req->ring)
510 dma_free_coherent(&ha->pdev->dev,
511 (req->length + 1) * sizeof(request_t),
512 req->ring, req->dma);
513
514 if (req)
515 kfree(req->outstanding_cmds);
516
517 kfree(req);
518 }
519
qla2x00_free_rsp_que(struct qla_hw_data * ha,struct rsp_que * rsp)520 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
521 {
522 if (IS_QLAFX00(ha)) {
523 if (rsp && rsp->ring_fx00)
524 dma_free_coherent(&ha->pdev->dev,
525 (rsp->length_fx00 + 1) * sizeof(request_t),
526 rsp->ring_fx00, rsp->dma_fx00);
527 } else if (rsp && rsp->ring) {
528 dma_free_coherent(&ha->pdev->dev,
529 (rsp->length + 1) * sizeof(response_t),
530 rsp->ring, rsp->dma);
531 }
532 kfree(rsp);
533 }
534
qla2x00_free_queues(struct qla_hw_data * ha)535 static void qla2x00_free_queues(struct qla_hw_data *ha)
536 {
537 struct req_que *req;
538 struct rsp_que *rsp;
539 int cnt;
540 unsigned long flags;
541
542 if (ha->queue_pair_map) {
543 kfree(ha->queue_pair_map);
544 ha->queue_pair_map = NULL;
545 }
546 if (ha->base_qpair) {
547 kfree(ha->base_qpair);
548 ha->base_qpair = NULL;
549 }
550
551 qla_mapq_free_qp_cpu_map(ha);
552 spin_lock_irqsave(&ha->hardware_lock, flags);
553 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
554 if (!test_bit(cnt, ha->req_qid_map))
555 continue;
556
557 req = ha->req_q_map[cnt];
558 clear_bit(cnt, ha->req_qid_map);
559 ha->req_q_map[cnt] = NULL;
560
561 spin_unlock_irqrestore(&ha->hardware_lock, flags);
562 qla2x00_free_req_que(ha, req);
563 spin_lock_irqsave(&ha->hardware_lock, flags);
564 }
565 spin_unlock_irqrestore(&ha->hardware_lock, flags);
566
567 kfree(ha->req_q_map);
568 ha->req_q_map = NULL;
569
570
571 spin_lock_irqsave(&ha->hardware_lock, flags);
572 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
573 if (!test_bit(cnt, ha->rsp_qid_map))
574 continue;
575
576 rsp = ha->rsp_q_map[cnt];
577 clear_bit(cnt, ha->rsp_qid_map);
578 ha->rsp_q_map[cnt] = NULL;
579 spin_unlock_irqrestore(&ha->hardware_lock, flags);
580 qla2x00_free_rsp_que(ha, rsp);
581 spin_lock_irqsave(&ha->hardware_lock, flags);
582 }
583 spin_unlock_irqrestore(&ha->hardware_lock, flags);
584
585 kfree(ha->rsp_q_map);
586 ha->rsp_q_map = NULL;
587 }
588
589 static char *
qla2x00_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)590 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
591 {
592 struct qla_hw_data *ha = vha->hw;
593 static const char *const pci_bus_modes[] = {
594 "33", "66", "100", "133",
595 };
596 uint16_t pci_bus;
597
598 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
599 if (pci_bus) {
600 snprintf(str, str_len, "PCI-X (%s MHz)",
601 pci_bus_modes[pci_bus]);
602 } else {
603 pci_bus = (ha->pci_attr & BIT_8) >> 8;
604 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
605 }
606
607 return str;
608 }
609
610 static char *
qla24xx_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)611 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
612 {
613 static const char *const pci_bus_modes[] = {
614 "33", "66", "100", "133",
615 };
616 struct qla_hw_data *ha = vha->hw;
617 uint32_t pci_bus;
618
619 if (pci_is_pcie(ha->pdev)) {
620 uint32_t lstat, lspeed, lwidth;
621 const char *speed_str;
622
623 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
624 lspeed = FIELD_GET(PCI_EXP_LNKCAP_SLS, lstat);
625 lwidth = FIELD_GET(PCI_EXP_LNKCAP_MLW, lstat);
626
627 switch (lspeed) {
628 case 1:
629 speed_str = "2.5GT/s";
630 break;
631 case 2:
632 speed_str = "5.0GT/s";
633 break;
634 case 3:
635 speed_str = "8.0GT/s";
636 break;
637 case 4:
638 speed_str = "16.0GT/s";
639 break;
640 default:
641 speed_str = "<unknown>";
642 break;
643 }
644 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
645
646 return str;
647 }
648
649 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
650 if (pci_bus == 0 || pci_bus == 8)
651 snprintf(str, str_len, "PCI (%s MHz)",
652 pci_bus_modes[pci_bus >> 3]);
653 else
654 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
655 pci_bus & 4 ? 2 : 1,
656 pci_bus_modes[pci_bus & 3]);
657
658 return str;
659 }
660
661 static char *
qla2x00_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)662 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
663 {
664 char un_str[10];
665 struct qla_hw_data *ha = vha->hw;
666
667 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
668 ha->fw_minor_version, ha->fw_subminor_version);
669
670 if (ha->fw_attributes & BIT_9) {
671 strcat(str, "FLX");
672 return (str);
673 }
674
675 switch (ha->fw_attributes & 0xFF) {
676 case 0x7:
677 strcat(str, "EF");
678 break;
679 case 0x17:
680 strcat(str, "TP");
681 break;
682 case 0x37:
683 strcat(str, "IP");
684 break;
685 case 0x77:
686 strcat(str, "VI");
687 break;
688 default:
689 sprintf(un_str, "(%x)", ha->fw_attributes);
690 strcat(str, un_str);
691 break;
692 }
693 if (ha->fw_attributes & 0x100)
694 strcat(str, "X");
695
696 return (str);
697 }
698
699 static char *
qla24xx_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)700 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
701 {
702 struct qla_hw_data *ha = vha->hw;
703
704 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
705 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
706 return str;
707 }
708
qla2x00_sp_free_dma(srb_t * sp)709 void qla2x00_sp_free_dma(srb_t *sp)
710 {
711 struct qla_hw_data *ha = sp->vha->hw;
712 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
713
714 if (sp->flags & SRB_DMA_VALID) {
715 scsi_dma_unmap(cmd);
716 sp->flags &= ~SRB_DMA_VALID;
717 }
718
719 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
720 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
721 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
722 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
723 }
724
725 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
726 /* List assured to be having elements */
727 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
728 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
729 }
730
731 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
732 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
733
734 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
735 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
736 }
737
738 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
739 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
740
741 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
742 ctx1->fcp_cmnd_dma);
743 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
744 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
745 sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
746 }
747
748 if (sp->flags & SRB_GOT_BUF)
749 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
750 }
751
qla2x00_sp_compl(srb_t * sp,int res)752 void qla2x00_sp_compl(srb_t *sp, int res)
753 {
754 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
755 struct completion *comp = sp->comp;
756
757 /* kref: INIT */
758 kref_put(&sp->cmd_kref, qla2x00_sp_release);
759 cmd->result = res;
760 sp->type = 0;
761 scsi_done(cmd);
762 if (comp)
763 complete(comp);
764 }
765
qla2xxx_qpair_sp_free_dma(srb_t * sp)766 void qla2xxx_qpair_sp_free_dma(srb_t *sp)
767 {
768 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
769 struct qla_hw_data *ha = sp->fcport->vha->hw;
770
771 if (sp->flags & SRB_DMA_VALID) {
772 scsi_dma_unmap(cmd);
773 sp->flags &= ~SRB_DMA_VALID;
774 }
775
776 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
777 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
778 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
779 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
780 }
781
782 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
783 /* List assured to be having elements */
784 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
785 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
786 }
787
788 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
789 struct crc_context *difctx = sp->u.scmd.crc_ctx;
790 struct dsd_dma *dif_dsd, *nxt_dsd;
791
792 list_for_each_entry_safe(dif_dsd, nxt_dsd,
793 &difctx->ldif_dma_hndl_list, list) {
794 list_del(&dif_dsd->list);
795 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
796 dif_dsd->dsd_list_dma);
797 kfree(dif_dsd);
798 difctx->no_dif_bundl--;
799 }
800
801 list_for_each_entry_safe(dif_dsd, nxt_dsd,
802 &difctx->ldif_dsd_list, list) {
803 list_del(&dif_dsd->list);
804 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
805 dif_dsd->dsd_list_dma);
806 kfree(dif_dsd);
807 difctx->no_ldif_dsd--;
808 }
809
810 if (difctx->no_ldif_dsd) {
811 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
812 "%s: difctx->no_ldif_dsd=%x\n",
813 __func__, difctx->no_ldif_dsd);
814 }
815
816 if (difctx->no_dif_bundl) {
817 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
818 "%s: difctx->no_dif_bundl=%x\n",
819 __func__, difctx->no_dif_bundl);
820 }
821 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
822 }
823
824 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
825 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
826
827 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
828 ctx1->fcp_cmnd_dma);
829 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
830 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
831 sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
832 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
833 }
834
835 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
836 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
837
838 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
839 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
840 }
841
842 if (sp->flags & SRB_GOT_BUF)
843 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
844 }
845
qla2xxx_qpair_sp_compl(srb_t * sp,int res)846 void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
847 {
848 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
849 struct completion *comp = sp->comp;
850
851 /* ref: INIT */
852 kref_put(&sp->cmd_kref, qla2x00_sp_release);
853 cmd->result = res;
854 sp->type = 0;
855 scsi_done(cmd);
856 if (comp)
857 complete(comp);
858 }
859
860 static int
qla2xxx_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)861 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
862 {
863 scsi_qla_host_t *vha = shost_priv(host);
864 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
865 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
866 struct qla_hw_data *ha = vha->hw;
867 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
868 srb_t *sp;
869 int rval;
870
871 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
872 WARN_ON_ONCE(!rport)) {
873 cmd->result = DID_NO_CONNECT << 16;
874 goto qc24_fail_command;
875 }
876
877 if (ha->mqenable) {
878 uint32_t tag;
879 uint16_t hwq;
880 struct qla_qpair *qpair = NULL;
881
882 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd));
883 hwq = blk_mq_unique_tag_to_hwq(tag);
884 qpair = ha->queue_pair_map[hwq];
885
886 if (qpair)
887 return qla2xxx_mqueuecommand(host, cmd, qpair);
888 }
889
890 if (ha->flags.eeh_busy) {
891 if (ha->flags.pci_channel_io_perm_failure) {
892 ql_dbg(ql_dbg_aer, vha, 0x9010,
893 "PCI Channel IO permanent failure, exiting "
894 "cmd=%p.\n", cmd);
895 cmd->result = DID_NO_CONNECT << 16;
896 } else {
897 ql_dbg(ql_dbg_aer, vha, 0x9011,
898 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
899 cmd->result = DID_REQUEUE << 16;
900 }
901 goto qc24_fail_command;
902 }
903
904 rval = fc_remote_port_chkready(rport);
905 if (rval) {
906 cmd->result = rval;
907 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
908 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
909 cmd, rval);
910 goto qc24_fail_command;
911 }
912
913 if (!vha->flags.difdix_supported &&
914 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
915 ql_dbg(ql_dbg_io, vha, 0x3004,
916 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
917 cmd);
918 cmd->result = DID_NO_CONNECT << 16;
919 goto qc24_fail_command;
920 }
921
922 if (!fcport || fcport->deleted) {
923 cmd->result = DID_IMM_RETRY << 16;
924 goto qc24_fail_command;
925 }
926
927 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
928 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
929 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
930 ql_dbg(ql_dbg_io, vha, 0x3005,
931 "Returning DNC, fcport_state=%d loop_state=%d.\n",
932 atomic_read(&fcport->state),
933 atomic_read(&base_vha->loop_state));
934 cmd->result = DID_NO_CONNECT << 16;
935 goto qc24_fail_command;
936 }
937 goto qc24_target_busy;
938 }
939
940 /*
941 * Return target busy if we've received a non-zero retry_delay_timer
942 * in a FCP_RSP.
943 */
944 if (fcport->retry_delay_timestamp == 0) {
945 /* retry delay not set */
946 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
947 fcport->retry_delay_timestamp = 0;
948 else
949 goto qc24_target_busy;
950
951 sp = scsi_cmd_priv(cmd);
952 /* ref: INIT */
953 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
954
955 sp->u.scmd.cmd = cmd;
956 sp->type = SRB_SCSI_CMD;
957 sp->free = qla2x00_sp_free_dma;
958 sp->done = qla2x00_sp_compl;
959
960 rval = ha->isp_ops->start_scsi(sp);
961 if (rval != QLA_SUCCESS) {
962 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
963 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
964 goto qc24_host_busy_free_sp;
965 }
966
967 return 0;
968
969 qc24_host_busy_free_sp:
970 /* ref: INIT */
971 kref_put(&sp->cmd_kref, qla2x00_sp_release);
972
973 qc24_target_busy:
974 return SCSI_MLQUEUE_TARGET_BUSY;
975
976 qc24_fail_command:
977 scsi_done(cmd);
978
979 return 0;
980 }
981
982 /* For MQ supported I/O */
983 int
qla2xxx_mqueuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd,struct qla_qpair * qpair)984 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
985 struct qla_qpair *qpair)
986 {
987 scsi_qla_host_t *vha = shost_priv(host);
988 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
989 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
990 struct qla_hw_data *ha = vha->hw;
991 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
992 srb_t *sp;
993 int rval;
994
995 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16);
996 if (rval) {
997 cmd->result = rval;
998 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
999 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
1000 cmd, rval);
1001 goto qc24_fail_command;
1002 }
1003
1004 if (!qpair->online) {
1005 ql_dbg(ql_dbg_io, vha, 0x3077,
1006 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy);
1007 cmd->result = DID_NO_CONNECT << 16;
1008 goto qc24_fail_command;
1009 }
1010
1011 if (!fcport || fcport->deleted) {
1012 cmd->result = DID_IMM_RETRY << 16;
1013 goto qc24_fail_command;
1014 }
1015
1016 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
1017 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
1018 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
1019 ql_dbg(ql_dbg_io, vha, 0x3077,
1020 "Returning DNC, fcport_state=%d loop_state=%d.\n",
1021 atomic_read(&fcport->state),
1022 atomic_read(&base_vha->loop_state));
1023 cmd->result = DID_NO_CONNECT << 16;
1024 goto qc24_fail_command;
1025 }
1026 goto qc24_target_busy;
1027 }
1028
1029 /*
1030 * Return target busy if we've received a non-zero retry_delay_timer
1031 * in a FCP_RSP.
1032 */
1033 if (fcport->retry_delay_timestamp == 0) {
1034 /* retry delay not set */
1035 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1036 fcport->retry_delay_timestamp = 0;
1037 else
1038 goto qc24_target_busy;
1039
1040 sp = scsi_cmd_priv(cmd);
1041 /* ref: INIT */
1042 qla2xxx_init_sp(sp, vha, qpair, fcport);
1043
1044 sp->u.scmd.cmd = cmd;
1045 sp->type = SRB_SCSI_CMD;
1046 sp->free = qla2xxx_qpair_sp_free_dma;
1047 sp->done = qla2xxx_qpair_sp_compl;
1048
1049 rval = ha->isp_ops->start_scsi_mq(sp);
1050 if (rval != QLA_SUCCESS) {
1051 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1052 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1053 goto qc24_host_busy_free_sp;
1054 }
1055
1056 return 0;
1057
1058 qc24_host_busy_free_sp:
1059 /* ref: INIT */
1060 kref_put(&sp->cmd_kref, qla2x00_sp_release);
1061
1062 qc24_target_busy:
1063 return SCSI_MLQUEUE_TARGET_BUSY;
1064
1065 qc24_fail_command:
1066 scsi_done(cmd);
1067
1068 return 0;
1069 }
1070
1071 /*
1072 * qla2x00_wait_for_hba_online
1073 * Wait till the HBA is online after going through
1074 * <= MAX_RETRIES_OF_ISP_ABORT or
1075 * finally HBA is disabled ie marked offline
1076 *
1077 * Input:
1078 * ha - pointer to host adapter structure
1079 *
1080 * Note:
1081 * Does context switching-Release SPIN_LOCK
1082 * (if any) before calling this routine.
1083 *
1084 * Return:
1085 * Success (Adapter is online) : 0
1086 * Failed (Adapter is offline/disabled) : 1
1087 */
1088 int
qla2x00_wait_for_hba_online(scsi_qla_host_t * vha)1089 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1090 {
1091 int return_status;
1092 unsigned long wait_online;
1093 struct qla_hw_data *ha = vha->hw;
1094 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1095
1096 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1097 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1098 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1099 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1100 ha->dpc_active) && time_before(jiffies, wait_online)) {
1101
1102 msleep(1000);
1103 }
1104 if (base_vha->flags.online)
1105 return_status = QLA_SUCCESS;
1106 else
1107 return_status = QLA_FUNCTION_FAILED;
1108
1109 return (return_status);
1110 }
1111
test_fcport_count(scsi_qla_host_t * vha)1112 static inline int test_fcport_count(scsi_qla_host_t *vha)
1113 {
1114 struct qla_hw_data *ha = vha->hw;
1115 unsigned long flags;
1116 int res;
1117 /* Return 0 = sleep, x=wake */
1118
1119 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1120 ql_dbg(ql_dbg_init, vha, 0x00ec,
1121 "tgt %p, fcport_count=%d\n",
1122 vha, vha->fcport_count);
1123 res = (vha->fcport_count == 0);
1124 if (res) {
1125 struct fc_port *fcport;
1126
1127 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1128 if (fcport->deleted != QLA_SESS_DELETED) {
1129 /* session(s) may not be fully logged in
1130 * (ie fcport_count=0), but session
1131 * deletion thread(s) may be inflight.
1132 */
1133
1134 res = 0;
1135 break;
1136 }
1137 }
1138 }
1139 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1140
1141 return res;
1142 }
1143
1144 /*
1145 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1146 * it has dependency on UNLOADING flag to stop device discovery
1147 */
1148 void
qla2x00_wait_for_sess_deletion(scsi_qla_host_t * vha)1149 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1150 {
1151 u8 i;
1152
1153 qla2x00_mark_all_devices_lost(vha);
1154
1155 for (i = 0; i < 10; i++) {
1156 if (wait_event_timeout(vha->fcport_waitQ,
1157 test_fcport_count(vha), HZ) > 0)
1158 break;
1159 }
1160
1161 flush_workqueue(vha->hw->wq);
1162 }
1163
1164 /*
1165 * qla2x00_wait_for_hba_ready
1166 * Wait till the HBA is ready before doing driver unload
1167 *
1168 * Input:
1169 * ha - pointer to host adapter structure
1170 *
1171 * Note:
1172 * Does context switching-Release SPIN_LOCK
1173 * (if any) before calling this routine.
1174 *
1175 */
1176 static void
qla2x00_wait_for_hba_ready(scsi_qla_host_t * vha)1177 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1178 {
1179 struct qla_hw_data *ha = vha->hw;
1180 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1181
1182 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1183 ha->flags.mbox_busy) ||
1184 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1185 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1186 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1187 break;
1188 msleep(1000);
1189 }
1190 }
1191
1192 int
qla2x00_wait_for_chip_reset(scsi_qla_host_t * vha)1193 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1194 {
1195 int return_status;
1196 unsigned long wait_reset;
1197 struct qla_hw_data *ha = vha->hw;
1198 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1199
1200 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1201 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1202 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1203 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1204 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1205
1206 msleep(1000);
1207
1208 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1209 ha->flags.chip_reset_done)
1210 break;
1211 }
1212 if (ha->flags.chip_reset_done)
1213 return_status = QLA_SUCCESS;
1214 else
1215 return_status = QLA_FUNCTION_FAILED;
1216
1217 return return_status;
1218 }
1219
1220 /**************************************************************************
1221 * qla2xxx_eh_abort
1222 *
1223 * Description:
1224 * The abort function will abort the specified command.
1225 *
1226 * Input:
1227 * cmd = Linux SCSI command packet to be aborted.
1228 *
1229 * Returns:
1230 * Either SUCCESS or FAILED.
1231 *
1232 * Note:
1233 * Only return FAILED if command not returned by firmware.
1234 **************************************************************************/
1235 static int
qla2xxx_eh_abort(struct scsi_cmnd * cmd)1236 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1237 {
1238 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1239 DECLARE_COMPLETION_ONSTACK(comp);
1240 srb_t *sp;
1241 int ret;
1242 unsigned int id;
1243 uint64_t lun;
1244 int rval;
1245 struct qla_hw_data *ha = vha->hw;
1246 uint32_t ratov_j;
1247 struct qla_qpair *qpair;
1248 unsigned long flags;
1249 int fast_fail_status = SUCCESS;
1250
1251 if (qla2x00_isp_reg_stat(ha)) {
1252 ql_log(ql_log_info, vha, 0x8042,
1253 "PCI/Register disconnect, exiting.\n");
1254 qla_pci_set_eeh_busy(vha);
1255 return FAILED;
1256 }
1257
1258 /* Save any FAST_IO_FAIL value to return later if abort succeeds */
1259 ret = fc_block_scsi_eh(cmd);
1260 if (ret != 0)
1261 fast_fail_status = ret;
1262
1263 sp = scsi_cmd_priv(cmd);
1264 qpair = sp->qpair;
1265
1266 vha->cmd_timeout_cnt++;
1267
1268 if ((sp->fcport && sp->fcport->deleted) || !qpair)
1269 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED;
1270
1271 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1272 sp->comp = ∁
1273 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1274
1275
1276 id = cmd->device->id;
1277 lun = cmd->device->lun;
1278
1279 ql_dbg(ql_dbg_taskm, vha, 0x8002,
1280 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1281 vha->host_no, id, lun, sp, cmd, sp->handle);
1282
1283 /*
1284 * Abort will release the original Command/sp from FW. Let the
1285 * original command call scsi_done. In return, he will wakeup
1286 * this sleeping thread.
1287 */
1288 rval = ha->isp_ops->abort_command(sp);
1289
1290 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1291 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
1292
1293 /* Wait for the command completion. */
1294 ratov_j = ha->r_a_tov / 10 * 4;
1295 ratov_j = secs_to_jiffies(ratov_j);
1296 switch (rval) {
1297 case QLA_SUCCESS:
1298 if (!wait_for_completion_timeout(&comp, ratov_j)) {
1299 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1300 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1301 __func__, ha->r_a_tov/10);
1302 ret = FAILED;
1303 } else {
1304 ret = fast_fail_status;
1305 }
1306 break;
1307 default:
1308 ret = FAILED;
1309 break;
1310 }
1311
1312 sp->comp = NULL;
1313
1314 ql_log(ql_log_info, vha, 0x801c,
1315 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1316 vha->host_no, id, lun, ret);
1317
1318 return ret;
1319 }
1320
1321 #define ABORT_POLLING_PERIOD 1000
1322 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
1323
1324 /*
1325 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1326 */
1327 static int
__qla2x00_eh_wait_for_pending_commands(struct qla_qpair * qpair,unsigned int t,uint64_t l,enum nexus_wait_type type)1328 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t,
1329 uint64_t l, enum nexus_wait_type type)
1330 {
1331 int cnt, match, status;
1332 unsigned long flags;
1333 scsi_qla_host_t *vha = qpair->vha;
1334 struct req_que *req = qpair->req;
1335 srb_t *sp;
1336 struct scsi_cmnd *cmd;
1337 unsigned long wait_iter = ABORT_WAIT_ITER;
1338 bool found;
1339 struct qla_hw_data *ha = vha->hw;
1340
1341 status = QLA_SUCCESS;
1342
1343 while (wait_iter--) {
1344 found = false;
1345
1346 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1347 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1348 sp = req->outstanding_cmds[cnt];
1349 if (!sp)
1350 continue;
1351 if (sp->type != SRB_SCSI_CMD)
1352 continue;
1353 if (vha->vp_idx != sp->vha->vp_idx)
1354 continue;
1355 match = 0;
1356 cmd = GET_CMD_SP(sp);
1357 switch (type) {
1358 case WAIT_HOST:
1359 match = 1;
1360 break;
1361 case WAIT_TARGET:
1362 if (sp->fcport)
1363 match = sp->fcport->d_id.b24 == t;
1364 else
1365 match = 0;
1366 break;
1367 case WAIT_LUN:
1368 if (sp->fcport)
1369 match = (sp->fcport->d_id.b24 == t &&
1370 cmd->device->lun == l);
1371 else
1372 match = 0;
1373 break;
1374 }
1375 if (!match)
1376 continue;
1377
1378 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1379
1380 if (unlikely(pci_channel_offline(ha->pdev)) ||
1381 ha->flags.eeh_busy) {
1382 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1383 "Return:eh_wait.\n");
1384 return status;
1385 }
1386
1387 /*
1388 * SRB_SCSI_CMD is still in the outstanding_cmds array.
1389 * it means scsi_done has not called. Wait for it to
1390 * clear from outstanding_cmds.
1391 */
1392 msleep(ABORT_POLLING_PERIOD);
1393 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1394 found = true;
1395 }
1396 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1397
1398 if (!found)
1399 break;
1400 }
1401
1402 if (wait_iter == -1)
1403 status = QLA_FUNCTION_FAILED;
1404
1405 return status;
1406 }
1407
1408 int
qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t * vha,unsigned int t,uint64_t l,enum nexus_wait_type type)1409 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1410 uint64_t l, enum nexus_wait_type type)
1411 {
1412 struct qla_qpair *qpair;
1413 struct qla_hw_data *ha = vha->hw;
1414 int i, status = QLA_SUCCESS;
1415
1416 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l,
1417 type);
1418 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) {
1419 qpair = ha->queue_pair_map[i];
1420 if (!qpair)
1421 continue;
1422 status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l,
1423 type);
1424 }
1425 return status;
1426 }
1427
1428 static char *reset_errors[] = {
1429 "HBA not online",
1430 "HBA not ready",
1431 "Task management failed",
1432 "Waiting for command completions",
1433 };
1434
1435 static int
qla2xxx_eh_device_reset(struct scsi_cmnd * cmd)1436 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1437 {
1438 struct scsi_device *sdev = cmd->device;
1439 scsi_qla_host_t *vha = shost_priv(sdev->host);
1440 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1441 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1442 struct qla_hw_data *ha = vha->hw;
1443 int err;
1444
1445 if (qla2x00_isp_reg_stat(ha)) {
1446 ql_log(ql_log_info, vha, 0x803e,
1447 "PCI/Register disconnect, exiting.\n");
1448 qla_pci_set_eeh_busy(vha);
1449 return FAILED;
1450 }
1451
1452 if (!fcport) {
1453 return FAILED;
1454 }
1455
1456 err = fc_block_rport(rport);
1457 if (err != 0)
1458 return err;
1459
1460 if (fcport->deleted)
1461 return FAILED;
1462
1463 ql_log(ql_log_info, vha, 0x8009,
1464 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no,
1465 sdev->id, sdev->lun, cmd);
1466
1467 err = 0;
1468 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1469 ql_log(ql_log_warn, vha, 0x800a,
1470 "Wait for hba online failed for cmd=%p.\n", cmd);
1471 goto eh_reset_failed;
1472 }
1473 err = 2;
1474 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1)
1475 != QLA_SUCCESS) {
1476 ql_log(ql_log_warn, vha, 0x800c,
1477 "do_reset failed for cmd=%p.\n", cmd);
1478 goto eh_reset_failed;
1479 }
1480 err = 3;
1481 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24,
1482 cmd->device->lun,
1483 WAIT_LUN) != QLA_SUCCESS) {
1484 ql_log(ql_log_warn, vha, 0x800d,
1485 "wait for pending cmds failed for cmd=%p.\n", cmd);
1486 goto eh_reset_failed;
1487 }
1488
1489 ql_log(ql_log_info, vha, 0x800e,
1490 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n",
1491 vha->host_no, sdev->id, sdev->lun, cmd);
1492
1493 return SUCCESS;
1494
1495 eh_reset_failed:
1496 ql_log(ql_log_info, vha, 0x800f,
1497 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1498 reset_errors[err], vha->host_no, sdev->id, sdev->lun,
1499 cmd);
1500 vha->reset_cmd_err_cnt++;
1501 return FAILED;
1502 }
1503
1504 static int
qla2xxx_eh_target_reset(struct scsi_cmnd * cmd)1505 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1506 {
1507 struct scsi_device *sdev = cmd->device;
1508 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1509 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport));
1510 struct qla_hw_data *ha = vha->hw;
1511 fc_port_t *fcport = *(fc_port_t **)rport->dd_data;
1512 int err;
1513
1514 if (qla2x00_isp_reg_stat(ha)) {
1515 ql_log(ql_log_info, vha, 0x803f,
1516 "PCI/Register disconnect, exiting.\n");
1517 qla_pci_set_eeh_busy(vha);
1518 return FAILED;
1519 }
1520
1521 if (!fcport) {
1522 return FAILED;
1523 }
1524
1525 err = fc_block_rport(rport);
1526 if (err != 0)
1527 return err;
1528
1529 if (fcport->deleted)
1530 return FAILED;
1531
1532 ql_log(ql_log_info, vha, 0x8009,
1533 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no,
1534 sdev->id, cmd);
1535
1536 err = 0;
1537 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1538 ql_log(ql_log_warn, vha, 0x800a,
1539 "Wait for hba online failed for cmd=%p.\n", cmd);
1540 goto eh_reset_failed;
1541 }
1542 err = 2;
1543 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) {
1544 ql_log(ql_log_warn, vha, 0x800c,
1545 "target_reset failed for cmd=%p.\n", cmd);
1546 goto eh_reset_failed;
1547 }
1548 err = 3;
1549 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 0,
1550 WAIT_TARGET) != QLA_SUCCESS) {
1551 ql_log(ql_log_warn, vha, 0x800d,
1552 "wait for pending cmds failed for cmd=%p.\n", cmd);
1553 goto eh_reset_failed;
1554 }
1555
1556 ql_log(ql_log_info, vha, 0x800e,
1557 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n",
1558 vha->host_no, sdev->id, cmd);
1559
1560 return SUCCESS;
1561
1562 eh_reset_failed:
1563 ql_log(ql_log_info, vha, 0x800f,
1564 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1565 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1566 cmd);
1567 vha->reset_cmd_err_cnt++;
1568 return FAILED;
1569 }
1570
1571 /**************************************************************************
1572 * qla2xxx_eh_bus_reset
1573 *
1574 * Description:
1575 * The bus reset function will reset the bus and abort any executing
1576 * commands.
1577 *
1578 * Input:
1579 * cmd = Linux SCSI command packet of the command that cause the
1580 * bus reset.
1581 *
1582 * Returns:
1583 * SUCCESS/FAILURE (defined as macro in scsi.h).
1584 *
1585 **************************************************************************/
1586 static int
qla2xxx_eh_bus_reset(struct scsi_cmnd * cmd)1587 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1588 {
1589 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1590 int ret = FAILED;
1591 unsigned int id;
1592 uint64_t lun;
1593 struct qla_hw_data *ha = vha->hw;
1594
1595 if (qla2x00_isp_reg_stat(ha)) {
1596 ql_log(ql_log_info, vha, 0x8040,
1597 "PCI/Register disconnect, exiting.\n");
1598 qla_pci_set_eeh_busy(vha);
1599 return FAILED;
1600 }
1601
1602 id = cmd->device->id;
1603 lun = cmd->device->lun;
1604
1605 if (qla2x00_chip_is_down(vha))
1606 return ret;
1607
1608 ql_log(ql_log_info, vha, 0x8012,
1609 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1610
1611 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1612 ql_log(ql_log_fatal, vha, 0x8013,
1613 "Wait for hba online failed board disabled.\n");
1614 goto eh_bus_reset_done;
1615 }
1616
1617 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1618 ret = SUCCESS;
1619
1620 if (ret == FAILED)
1621 goto eh_bus_reset_done;
1622
1623 /* Flush outstanding commands. */
1624 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1625 QLA_SUCCESS) {
1626 ql_log(ql_log_warn, vha, 0x8014,
1627 "Wait for pending commands failed.\n");
1628 ret = FAILED;
1629 }
1630
1631 eh_bus_reset_done:
1632 ql_log(ql_log_warn, vha, 0x802b,
1633 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1634 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1635
1636 return ret;
1637 }
1638
1639 /**************************************************************************
1640 * qla2xxx_eh_host_reset
1641 *
1642 * Description:
1643 * The reset function will reset the Adapter.
1644 *
1645 * Input:
1646 * cmd = Linux SCSI command packet of the command that cause the
1647 * adapter reset.
1648 *
1649 * Returns:
1650 * Either SUCCESS or FAILED.
1651 *
1652 * Note:
1653 **************************************************************************/
1654 static int
qla2xxx_eh_host_reset(struct scsi_cmnd * cmd)1655 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1656 {
1657 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1658 struct qla_hw_data *ha = vha->hw;
1659 int ret = FAILED;
1660 unsigned int id;
1661 uint64_t lun;
1662 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1663
1664 if (qla2x00_isp_reg_stat(ha)) {
1665 ql_log(ql_log_info, vha, 0x8041,
1666 "PCI/Register disconnect, exiting.\n");
1667 qla_pci_set_eeh_busy(vha);
1668 return SUCCESS;
1669 }
1670
1671 id = cmd->device->id;
1672 lun = cmd->device->lun;
1673
1674 ql_log(ql_log_info, vha, 0x8018,
1675 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1676
1677 /*
1678 * No point in issuing another reset if one is active. Also do not
1679 * attempt a reset if we are updating flash.
1680 */
1681 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1682 goto eh_host_reset_lock;
1683
1684 if (vha != base_vha) {
1685 if (qla2x00_vp_abort_isp(vha))
1686 goto eh_host_reset_lock;
1687 } else {
1688 if (IS_P3P_TYPE(vha->hw)) {
1689 if (!qla82xx_fcoe_ctx_reset(vha)) {
1690 /* Ctx reset success */
1691 ret = SUCCESS;
1692 goto eh_host_reset_lock;
1693 }
1694 /* fall thru if ctx reset failed */
1695 }
1696 if (ha->wq)
1697 flush_workqueue(ha->wq);
1698
1699 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1700 if (ha->isp_ops->abort_isp(base_vha)) {
1701 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1702 /* failed. schedule dpc to try */
1703 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1704
1705 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1706 ql_log(ql_log_warn, vha, 0x802a,
1707 "wait for hba online failed.\n");
1708 goto eh_host_reset_lock;
1709 }
1710 }
1711 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1712 }
1713
1714 /* Waiting for command to be returned to OS.*/
1715 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1716 QLA_SUCCESS)
1717 ret = SUCCESS;
1718
1719 eh_host_reset_lock:
1720 ql_log(ql_log_info, vha, 0x8017,
1721 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1722 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1723
1724 return ret;
1725 }
1726
1727 /*
1728 * qla2x00_loop_reset
1729 * Issue loop reset.
1730 *
1731 * Input:
1732 * ha = adapter block pointer.
1733 *
1734 * Returns:
1735 * 0 = success
1736 */
1737 int
qla2x00_loop_reset(scsi_qla_host_t * vha)1738 qla2x00_loop_reset(scsi_qla_host_t *vha)
1739 {
1740 int ret;
1741 struct qla_hw_data *ha = vha->hw;
1742
1743 if (IS_QLAFX00(ha))
1744 return QLA_SUCCESS;
1745
1746 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1747 atomic_set(&vha->loop_state, LOOP_DOWN);
1748 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1749 qla2x00_mark_all_devices_lost(vha);
1750 ret = qla2x00_full_login_lip(vha);
1751 if (ret != QLA_SUCCESS) {
1752 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1753 "full_login_lip=%d.\n", ret);
1754 }
1755 }
1756
1757 if (ha->flags.enable_lip_reset) {
1758 ret = qla2x00_lip_reset(vha);
1759 if (ret != QLA_SUCCESS)
1760 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1761 "lip_reset failed (%d).\n", ret);
1762 }
1763
1764 /* Issue marker command only when we are going to start the I/O */
1765 vha->marker_needed = 1;
1766
1767 return QLA_SUCCESS;
1768 }
1769
1770 /*
1771 * The caller must ensure that no completion interrupts will happen
1772 * while this function is in progress.
1773 */
qla2x00_abort_srb(struct qla_qpair * qp,srb_t * sp,const int res,unsigned long * flags)1774 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1775 unsigned long *flags)
1776 __releases(qp->qp_lock_ptr)
1777 __acquires(qp->qp_lock_ptr)
1778 {
1779 DECLARE_COMPLETION_ONSTACK(comp);
1780 scsi_qla_host_t *vha = qp->vha;
1781 struct qla_hw_data *ha = vha->hw;
1782 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1783 int rval;
1784 bool ret_cmd;
1785 uint32_t ratov_j;
1786
1787 lockdep_assert_held(qp->qp_lock_ptr);
1788
1789 if (qla2x00_chip_is_down(vha)) {
1790 sp->done(sp, res);
1791 return;
1792 }
1793
1794 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1795 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1796 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1797 !qla2x00_isp_reg_stat(ha))) {
1798 if (sp->comp) {
1799 sp->done(sp, res);
1800 return;
1801 }
1802
1803 sp->comp = ∁
1804 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1805
1806 rval = ha->isp_ops->abort_command(sp);
1807 /* Wait for command completion. */
1808 ret_cmd = false;
1809 ratov_j = ha->r_a_tov / 10 * 4;
1810 ratov_j = secs_to_jiffies(ratov_j);
1811 switch (rval) {
1812 case QLA_SUCCESS:
1813 if (wait_for_completion_timeout(&comp, ratov_j)) {
1814 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1815 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1816 __func__, ha->r_a_tov/10);
1817 ret_cmd = true;
1818 }
1819 /* else FW return SP to driver */
1820 break;
1821 default:
1822 ret_cmd = true;
1823 break;
1824 }
1825
1826 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1827 switch (sp->type) {
1828 case SRB_SCSI_CMD:
1829 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd)))
1830 sp->done(sp, res);
1831 break;
1832 default:
1833 if (ret_cmd)
1834 sp->done(sp, res);
1835 break;
1836 }
1837 } else {
1838 sp->done(sp, res);
1839 }
1840 }
1841
1842 /*
1843 * The caller must ensure that no completion interrupts will happen
1844 * while this function is in progress.
1845 */
1846 static void
__qla2x00_abort_all_cmds(struct qla_qpair * qp,int res)1847 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
1848 {
1849 int cnt;
1850 unsigned long flags;
1851 srb_t *sp;
1852 scsi_qla_host_t *vha = qp->vha;
1853 struct qla_hw_data *ha = vha->hw;
1854 struct req_que *req;
1855 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1856 struct qla_tgt_cmd *cmd;
1857
1858 if (!ha->req_q_map)
1859 return;
1860 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1861 req = qp->req;
1862 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1863 sp = req->outstanding_cmds[cnt];
1864 if (sp) {
1865 switch (sp->cmd_type) {
1866 case TYPE_SRB:
1867 qla2x00_abort_srb(qp, sp, res, &flags);
1868 break;
1869 case TYPE_TGT_CMD:
1870 if (!vha->hw->tgt.tgt_ops || !tgt ||
1871 qla_ini_mode_enabled(vha)) {
1872 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1873 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1874 vha->dpc_flags);
1875 continue;
1876 }
1877 cmd = (struct qla_tgt_cmd *)sp;
1878
1879 if (cmd->sg_mapped)
1880 qlt_unmap_sg(vha, cmd);
1881
1882 if (cmd->state == QLA_TGT_STATE_NEED_DATA) {
1883 cmd->aborted = 1;
1884 cmd->write_data_transferred = 0;
1885 cmd->state = QLA_TGT_STATE_DATA_IN;
1886 ha->tgt.tgt_ops->handle_data(cmd);
1887 } else {
1888 ha->tgt.tgt_ops->free_cmd(cmd);
1889 }
1890 break;
1891 case TYPE_TGT_TMCMD:
1892 /*
1893 * Currently, only ABTS response gets on the
1894 * outstanding_cmds[]
1895 */
1896 qlt_free_ul_mcmd(ha,
1897 (struct qla_tgt_mgmt_cmd *) sp);
1898 break;
1899 default:
1900 break;
1901 }
1902 req->outstanding_cmds[cnt] = NULL;
1903 }
1904 }
1905 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1906 }
1907
1908 /*
1909 * The caller must ensure that no completion interrupts will happen
1910 * while this function is in progress.
1911 */
1912 void
qla2x00_abort_all_cmds(scsi_qla_host_t * vha,int res)1913 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1914 {
1915 int que;
1916 struct qla_hw_data *ha = vha->hw;
1917
1918 /* Continue only if initialization complete. */
1919 if (!ha->base_qpair)
1920 return;
1921 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1922
1923 if (!ha->queue_pair_map)
1924 return;
1925 for (que = 0; que < ha->max_qpairs; que++) {
1926 if (!ha->queue_pair_map[que])
1927 continue;
1928
1929 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1930 }
1931 }
1932
1933 static int
qla2xxx_sdev_init(struct scsi_device * sdev)1934 qla2xxx_sdev_init(struct scsi_device *sdev)
1935 {
1936 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1937
1938 if (!rport || fc_remote_port_chkready(rport))
1939 return -ENXIO;
1940
1941 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1942
1943 return 0;
1944 }
1945
1946 static int
qla2xxx_sdev_configure(struct scsi_device * sdev,struct queue_limits * lim)1947 qla2xxx_sdev_configure(struct scsi_device *sdev, struct queue_limits *lim)
1948 {
1949 scsi_qla_host_t *vha = shost_priv(sdev->host);
1950 struct req_que *req = vha->req;
1951
1952 scsi_change_queue_depth(sdev, req->max_q_depth);
1953 return 0;
1954 }
1955
1956 static void
qla2xxx_sdev_destroy(struct scsi_device * sdev)1957 qla2xxx_sdev_destroy(struct scsi_device *sdev)
1958 {
1959 sdev->hostdata = NULL;
1960 }
1961
1962 /**
1963 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1964 * @ha: HA context
1965 *
1966 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1967 * supported addressing method.
1968 */
1969 static void
qla2x00_config_dma_addressing(struct qla_hw_data * ha)1970 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1971 {
1972 /* Assume a 32bit DMA mask. */
1973 ha->flags.enable_64bit_addressing = 0;
1974
1975 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1976 /* Any upper-dword bits set? */
1977 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1978 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1979 /* Ok, a 64bit DMA mask is applicable. */
1980 ha->flags.enable_64bit_addressing = 1;
1981 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1982 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1983 return;
1984 }
1985 }
1986
1987 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1988 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1989 }
1990
1991 static void
qla2x00_enable_intrs(struct qla_hw_data * ha)1992 qla2x00_enable_intrs(struct qla_hw_data *ha)
1993 {
1994 unsigned long flags = 0;
1995 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1996
1997 spin_lock_irqsave(&ha->hardware_lock, flags);
1998 ha->interrupts_on = 1;
1999 /* enable risc and host interrupts */
2000 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC);
2001 rd_reg_word(®->ictrl);
2002 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2003
2004 }
2005
2006 static void
qla2x00_disable_intrs(struct qla_hw_data * ha)2007 qla2x00_disable_intrs(struct qla_hw_data *ha)
2008 {
2009 unsigned long flags = 0;
2010 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2011
2012 spin_lock_irqsave(&ha->hardware_lock, flags);
2013 ha->interrupts_on = 0;
2014 /* disable risc and host interrupts */
2015 wrt_reg_word(®->ictrl, 0);
2016 rd_reg_word(®->ictrl);
2017 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2018 }
2019
2020 static void
qla24xx_enable_intrs(struct qla_hw_data * ha)2021 qla24xx_enable_intrs(struct qla_hw_data *ha)
2022 {
2023 unsigned long flags = 0;
2024 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2025
2026 spin_lock_irqsave(&ha->hardware_lock, flags);
2027 ha->interrupts_on = 1;
2028 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT);
2029 rd_reg_dword(®->ictrl);
2030 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2031 }
2032
2033 static void
qla24xx_disable_intrs(struct qla_hw_data * ha)2034 qla24xx_disable_intrs(struct qla_hw_data *ha)
2035 {
2036 unsigned long flags = 0;
2037 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2038
2039 if (IS_NOPOLLING_TYPE(ha))
2040 return;
2041 spin_lock_irqsave(&ha->hardware_lock, flags);
2042 ha->interrupts_on = 0;
2043 wrt_reg_dword(®->ictrl, 0);
2044 rd_reg_dword(®->ictrl);
2045 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2046 }
2047
2048 static int
qla2x00_iospace_config(struct qla_hw_data * ha)2049 qla2x00_iospace_config(struct qla_hw_data *ha)
2050 {
2051 resource_size_t pio;
2052 uint16_t msix;
2053
2054 if (pci_request_selected_regions(ha->pdev, ha->bars,
2055 QLA2XXX_DRIVER_NAME)) {
2056 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
2057 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2058 pci_name(ha->pdev));
2059 goto iospace_error_exit;
2060 }
2061 if (!(ha->bars & 1))
2062 goto skip_pio;
2063
2064 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
2065 pio = pci_resource_start(ha->pdev, 0);
2066 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
2067 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2068 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
2069 "Invalid pci I/O region size (%s).\n",
2070 pci_name(ha->pdev));
2071 pio = 0;
2072 }
2073 } else {
2074 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
2075 "Region #0 no a PIO resource (%s).\n",
2076 pci_name(ha->pdev));
2077 pio = 0;
2078 }
2079 ha->pio_address = pio;
2080 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2081 "PIO address=%llu.\n",
2082 (unsigned long long)ha->pio_address);
2083
2084 skip_pio:
2085 /* Use MMIO operations for all accesses. */
2086 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2087 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2088 "Region #1 not an MMIO resource (%s), aborting.\n",
2089 pci_name(ha->pdev));
2090 goto iospace_error_exit;
2091 }
2092 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2093 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2094 "Invalid PCI mem region size (%s), aborting.\n",
2095 pci_name(ha->pdev));
2096 goto iospace_error_exit;
2097 }
2098
2099 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2100 if (!ha->iobase) {
2101 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2102 "Cannot remap MMIO (%s), aborting.\n",
2103 pci_name(ha->pdev));
2104 goto iospace_error_exit;
2105 }
2106
2107 /* Determine queue resources */
2108 ha->max_req_queues = ha->max_rsp_queues = 1;
2109 ha->msix_count = QLA_BASE_VECTORS;
2110
2111 /* Check if FW supports MQ or not */
2112 if (!(ha->fw_attributes & BIT_6))
2113 goto mqiobase_exit;
2114
2115 if (!ql2xmqsupport || !ql2xnvmeenable ||
2116 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
2117 goto mqiobase_exit;
2118
2119 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2120 pci_resource_len(ha->pdev, 3));
2121 if (ha->mqiobase) {
2122 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2123 "MQIO Base=%p.\n", ha->mqiobase);
2124 /* Read MSIX vector size of the board */
2125 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
2126 ha->msix_count = msix + 1;
2127 /* Max queues are bounded by available msix vectors */
2128 /* MB interrupt uses 1 vector */
2129 ha->max_req_queues = ha->msix_count - 1;
2130 ha->max_rsp_queues = ha->max_req_queues;
2131 /* Queue pairs is the max value minus the base queue pair */
2132 ha->max_qpairs = ha->max_rsp_queues - 1;
2133 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2134 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2135
2136 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2137 "MSI-X vector count: %d.\n", ha->msix_count);
2138 } else
2139 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2140 "BAR 3 not enabled.\n");
2141
2142 mqiobase_exit:
2143 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2144 "MSIX Count: %d.\n", ha->msix_count);
2145 return (0);
2146
2147 iospace_error_exit:
2148 return (-ENOMEM);
2149 }
2150
2151
2152 static int
qla83xx_iospace_config(struct qla_hw_data * ha)2153 qla83xx_iospace_config(struct qla_hw_data *ha)
2154 {
2155 uint16_t msix;
2156
2157 if (pci_request_selected_regions(ha->pdev, ha->bars,
2158 QLA2XXX_DRIVER_NAME)) {
2159 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2160 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2161 pci_name(ha->pdev));
2162
2163 goto iospace_error_exit;
2164 }
2165
2166 /* Use MMIO operations for all accesses. */
2167 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2168 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2169 "Invalid pci I/O region size (%s).\n",
2170 pci_name(ha->pdev));
2171 goto iospace_error_exit;
2172 }
2173 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2174 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2175 "Invalid PCI mem region size (%s), aborting\n",
2176 pci_name(ha->pdev));
2177 goto iospace_error_exit;
2178 }
2179
2180 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2181 if (!ha->iobase) {
2182 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2183 "Cannot remap MMIO (%s), aborting.\n",
2184 pci_name(ha->pdev));
2185 goto iospace_error_exit;
2186 }
2187
2188 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2189 /* 83XX 26XX always use MQ type access for queues
2190 * - mbar 2, a.k.a region 4 */
2191 ha->max_req_queues = ha->max_rsp_queues = 1;
2192 ha->msix_count = QLA_BASE_VECTORS;
2193 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2194 pci_resource_len(ha->pdev, 4));
2195
2196 if (!ha->mqiobase) {
2197 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2198 "BAR2/region4 not enabled\n");
2199 goto mqiobase_exit;
2200 }
2201
2202 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2203 pci_resource_len(ha->pdev, 2));
2204 if (ha->msixbase) {
2205 /* Read MSIX vector size of the board */
2206 pci_read_config_word(ha->pdev,
2207 QLA_83XX_PCI_MSIX_CONTROL, &msix);
2208 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
2209 /*
2210 * By default, driver uses at least two msix vectors
2211 * (default & rspq)
2212 */
2213 if (ql2xmqsupport || ql2xnvmeenable) {
2214 /* MB interrupt uses 1 vector */
2215 ha->max_req_queues = ha->msix_count - 1;
2216
2217 /* ATIOQ needs 1 vector. That's 1 less QPair */
2218 if (QLA_TGT_MODE_ENABLED())
2219 ha->max_req_queues--;
2220
2221 ha->max_rsp_queues = ha->max_req_queues;
2222
2223 /* Queue pairs is the max value minus
2224 * the base queue pair */
2225 ha->max_qpairs = ha->max_req_queues - 1;
2226 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2227 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2228 }
2229 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2230 "MSI-X vector count: %d.\n", ha->msix_count);
2231 } else
2232 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2233 "BAR 1 not enabled.\n");
2234
2235 mqiobase_exit:
2236 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2237 "MSIX Count: %d.\n", ha->msix_count);
2238 return 0;
2239
2240 iospace_error_exit:
2241 return -ENOMEM;
2242 }
2243
2244 static struct isp_operations qla2100_isp_ops = {
2245 .pci_config = qla2100_pci_config,
2246 .reset_chip = qla2x00_reset_chip,
2247 .chip_diag = qla2x00_chip_diag,
2248 .config_rings = qla2x00_config_rings,
2249 .reset_adapter = qla2x00_reset_adapter,
2250 .nvram_config = qla2x00_nvram_config,
2251 .update_fw_options = qla2x00_update_fw_options,
2252 .load_risc = qla2x00_load_risc,
2253 .pci_info_str = qla2x00_pci_info_str,
2254 .fw_version_str = qla2x00_fw_version_str,
2255 .intr_handler = qla2100_intr_handler,
2256 .enable_intrs = qla2x00_enable_intrs,
2257 .disable_intrs = qla2x00_disable_intrs,
2258 .abort_command = qla2x00_abort_command,
2259 .target_reset = qla2x00_abort_target,
2260 .lun_reset = qla2x00_lun_reset,
2261 .fabric_login = qla2x00_login_fabric,
2262 .fabric_logout = qla2x00_fabric_logout,
2263 .calc_req_entries = qla2x00_calc_iocbs_32,
2264 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2265 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2266 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2267 .read_nvram = qla2x00_read_nvram_data,
2268 .write_nvram = qla2x00_write_nvram_data,
2269 .fw_dump = qla2100_fw_dump,
2270 .beacon_on = NULL,
2271 .beacon_off = NULL,
2272 .beacon_blink = NULL,
2273 .read_optrom = qla2x00_read_optrom_data,
2274 .write_optrom = qla2x00_write_optrom_data,
2275 .get_flash_version = qla2x00_get_flash_version,
2276 .start_scsi = qla2x00_start_scsi,
2277 .start_scsi_mq = NULL,
2278 .abort_isp = qla2x00_abort_isp,
2279 .iospace_config = qla2x00_iospace_config,
2280 .initialize_adapter = qla2x00_initialize_adapter,
2281 };
2282
2283 static struct isp_operations qla2300_isp_ops = {
2284 .pci_config = qla2300_pci_config,
2285 .reset_chip = qla2x00_reset_chip,
2286 .chip_diag = qla2x00_chip_diag,
2287 .config_rings = qla2x00_config_rings,
2288 .reset_adapter = qla2x00_reset_adapter,
2289 .nvram_config = qla2x00_nvram_config,
2290 .update_fw_options = qla2x00_update_fw_options,
2291 .load_risc = qla2x00_load_risc,
2292 .pci_info_str = qla2x00_pci_info_str,
2293 .fw_version_str = qla2x00_fw_version_str,
2294 .intr_handler = qla2300_intr_handler,
2295 .enable_intrs = qla2x00_enable_intrs,
2296 .disable_intrs = qla2x00_disable_intrs,
2297 .abort_command = qla2x00_abort_command,
2298 .target_reset = qla2x00_abort_target,
2299 .lun_reset = qla2x00_lun_reset,
2300 .fabric_login = qla2x00_login_fabric,
2301 .fabric_logout = qla2x00_fabric_logout,
2302 .calc_req_entries = qla2x00_calc_iocbs_32,
2303 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2304 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2305 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2306 .read_nvram = qla2x00_read_nvram_data,
2307 .write_nvram = qla2x00_write_nvram_data,
2308 .fw_dump = qla2300_fw_dump,
2309 .beacon_on = qla2x00_beacon_on,
2310 .beacon_off = qla2x00_beacon_off,
2311 .beacon_blink = qla2x00_beacon_blink,
2312 .read_optrom = qla2x00_read_optrom_data,
2313 .write_optrom = qla2x00_write_optrom_data,
2314 .get_flash_version = qla2x00_get_flash_version,
2315 .start_scsi = qla2x00_start_scsi,
2316 .start_scsi_mq = NULL,
2317 .abort_isp = qla2x00_abort_isp,
2318 .iospace_config = qla2x00_iospace_config,
2319 .initialize_adapter = qla2x00_initialize_adapter,
2320 };
2321
2322 static struct isp_operations qla24xx_isp_ops = {
2323 .pci_config = qla24xx_pci_config,
2324 .reset_chip = qla24xx_reset_chip,
2325 .chip_diag = qla24xx_chip_diag,
2326 .config_rings = qla24xx_config_rings,
2327 .reset_adapter = qla24xx_reset_adapter,
2328 .nvram_config = qla24xx_nvram_config,
2329 .update_fw_options = qla24xx_update_fw_options,
2330 .load_risc = qla24xx_load_risc,
2331 .pci_info_str = qla24xx_pci_info_str,
2332 .fw_version_str = qla24xx_fw_version_str,
2333 .intr_handler = qla24xx_intr_handler,
2334 .enable_intrs = qla24xx_enable_intrs,
2335 .disable_intrs = qla24xx_disable_intrs,
2336 .abort_command = qla24xx_abort_command,
2337 .target_reset = qla24xx_abort_target,
2338 .lun_reset = qla24xx_lun_reset,
2339 .fabric_login = qla24xx_login_fabric,
2340 .fabric_logout = qla24xx_fabric_logout,
2341 .calc_req_entries = NULL,
2342 .build_iocbs = NULL,
2343 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2344 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2345 .read_nvram = qla24xx_read_nvram_data,
2346 .write_nvram = qla24xx_write_nvram_data,
2347 .fw_dump = qla24xx_fw_dump,
2348 .beacon_on = qla24xx_beacon_on,
2349 .beacon_off = qla24xx_beacon_off,
2350 .beacon_blink = qla24xx_beacon_blink,
2351 .read_optrom = qla24xx_read_optrom_data,
2352 .write_optrom = qla24xx_write_optrom_data,
2353 .get_flash_version = qla24xx_get_flash_version,
2354 .start_scsi = qla24xx_start_scsi,
2355 .start_scsi_mq = NULL,
2356 .abort_isp = qla2x00_abort_isp,
2357 .iospace_config = qla2x00_iospace_config,
2358 .initialize_adapter = qla2x00_initialize_adapter,
2359 };
2360
2361 static struct isp_operations qla25xx_isp_ops = {
2362 .pci_config = qla25xx_pci_config,
2363 .reset_chip = qla24xx_reset_chip,
2364 .chip_diag = qla24xx_chip_diag,
2365 .config_rings = qla24xx_config_rings,
2366 .reset_adapter = qla24xx_reset_adapter,
2367 .nvram_config = qla24xx_nvram_config,
2368 .update_fw_options = qla24xx_update_fw_options,
2369 .load_risc = qla24xx_load_risc,
2370 .pci_info_str = qla24xx_pci_info_str,
2371 .fw_version_str = qla24xx_fw_version_str,
2372 .intr_handler = qla24xx_intr_handler,
2373 .enable_intrs = qla24xx_enable_intrs,
2374 .disable_intrs = qla24xx_disable_intrs,
2375 .abort_command = qla24xx_abort_command,
2376 .target_reset = qla24xx_abort_target,
2377 .lun_reset = qla24xx_lun_reset,
2378 .fabric_login = qla24xx_login_fabric,
2379 .fabric_logout = qla24xx_fabric_logout,
2380 .calc_req_entries = NULL,
2381 .build_iocbs = NULL,
2382 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2383 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2384 .read_nvram = qla25xx_read_nvram_data,
2385 .write_nvram = qla25xx_write_nvram_data,
2386 .fw_dump = qla25xx_fw_dump,
2387 .beacon_on = qla24xx_beacon_on,
2388 .beacon_off = qla24xx_beacon_off,
2389 .beacon_blink = qla24xx_beacon_blink,
2390 .read_optrom = qla25xx_read_optrom_data,
2391 .write_optrom = qla24xx_write_optrom_data,
2392 .get_flash_version = qla24xx_get_flash_version,
2393 .start_scsi = qla24xx_dif_start_scsi,
2394 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2395 .abort_isp = qla2x00_abort_isp,
2396 .iospace_config = qla2x00_iospace_config,
2397 .initialize_adapter = qla2x00_initialize_adapter,
2398 };
2399
2400 static struct isp_operations qla81xx_isp_ops = {
2401 .pci_config = qla25xx_pci_config,
2402 .reset_chip = qla24xx_reset_chip,
2403 .chip_diag = qla24xx_chip_diag,
2404 .config_rings = qla24xx_config_rings,
2405 .reset_adapter = qla24xx_reset_adapter,
2406 .nvram_config = qla81xx_nvram_config,
2407 .update_fw_options = qla24xx_update_fw_options,
2408 .load_risc = qla81xx_load_risc,
2409 .pci_info_str = qla24xx_pci_info_str,
2410 .fw_version_str = qla24xx_fw_version_str,
2411 .intr_handler = qla24xx_intr_handler,
2412 .enable_intrs = qla24xx_enable_intrs,
2413 .disable_intrs = qla24xx_disable_intrs,
2414 .abort_command = qla24xx_abort_command,
2415 .target_reset = qla24xx_abort_target,
2416 .lun_reset = qla24xx_lun_reset,
2417 .fabric_login = qla24xx_login_fabric,
2418 .fabric_logout = qla24xx_fabric_logout,
2419 .calc_req_entries = NULL,
2420 .build_iocbs = NULL,
2421 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2422 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2423 .read_nvram = NULL,
2424 .write_nvram = NULL,
2425 .fw_dump = qla81xx_fw_dump,
2426 .beacon_on = qla24xx_beacon_on,
2427 .beacon_off = qla24xx_beacon_off,
2428 .beacon_blink = qla83xx_beacon_blink,
2429 .read_optrom = qla25xx_read_optrom_data,
2430 .write_optrom = qla24xx_write_optrom_data,
2431 .get_flash_version = qla24xx_get_flash_version,
2432 .start_scsi = qla24xx_dif_start_scsi,
2433 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2434 .abort_isp = qla2x00_abort_isp,
2435 .iospace_config = qla2x00_iospace_config,
2436 .initialize_adapter = qla2x00_initialize_adapter,
2437 };
2438
2439 static struct isp_operations qla82xx_isp_ops = {
2440 .pci_config = qla82xx_pci_config,
2441 .reset_chip = qla82xx_reset_chip,
2442 .chip_diag = qla24xx_chip_diag,
2443 .config_rings = qla82xx_config_rings,
2444 .reset_adapter = qla24xx_reset_adapter,
2445 .nvram_config = qla81xx_nvram_config,
2446 .update_fw_options = qla24xx_update_fw_options,
2447 .load_risc = qla82xx_load_risc,
2448 .pci_info_str = qla24xx_pci_info_str,
2449 .fw_version_str = qla24xx_fw_version_str,
2450 .intr_handler = qla82xx_intr_handler,
2451 .enable_intrs = qla82xx_enable_intrs,
2452 .disable_intrs = qla82xx_disable_intrs,
2453 .abort_command = qla24xx_abort_command,
2454 .target_reset = qla24xx_abort_target,
2455 .lun_reset = qla24xx_lun_reset,
2456 .fabric_login = qla24xx_login_fabric,
2457 .fabric_logout = qla24xx_fabric_logout,
2458 .calc_req_entries = NULL,
2459 .build_iocbs = NULL,
2460 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2461 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2462 .read_nvram = qla24xx_read_nvram_data,
2463 .write_nvram = qla24xx_write_nvram_data,
2464 .fw_dump = qla82xx_fw_dump,
2465 .beacon_on = qla82xx_beacon_on,
2466 .beacon_off = qla82xx_beacon_off,
2467 .beacon_blink = NULL,
2468 .read_optrom = qla82xx_read_optrom_data,
2469 .write_optrom = qla82xx_write_optrom_data,
2470 .get_flash_version = qla82xx_get_flash_version,
2471 .start_scsi = qla82xx_start_scsi,
2472 .start_scsi_mq = NULL,
2473 .abort_isp = qla82xx_abort_isp,
2474 .iospace_config = qla82xx_iospace_config,
2475 .initialize_adapter = qla2x00_initialize_adapter,
2476 };
2477
2478 static struct isp_operations qla8044_isp_ops = {
2479 .pci_config = qla82xx_pci_config,
2480 .reset_chip = qla82xx_reset_chip,
2481 .chip_diag = qla24xx_chip_diag,
2482 .config_rings = qla82xx_config_rings,
2483 .reset_adapter = qla24xx_reset_adapter,
2484 .nvram_config = qla81xx_nvram_config,
2485 .update_fw_options = qla24xx_update_fw_options,
2486 .load_risc = qla82xx_load_risc,
2487 .pci_info_str = qla24xx_pci_info_str,
2488 .fw_version_str = qla24xx_fw_version_str,
2489 .intr_handler = qla8044_intr_handler,
2490 .enable_intrs = qla82xx_enable_intrs,
2491 .disable_intrs = qla82xx_disable_intrs,
2492 .abort_command = qla24xx_abort_command,
2493 .target_reset = qla24xx_abort_target,
2494 .lun_reset = qla24xx_lun_reset,
2495 .fabric_login = qla24xx_login_fabric,
2496 .fabric_logout = qla24xx_fabric_logout,
2497 .calc_req_entries = NULL,
2498 .build_iocbs = NULL,
2499 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2500 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2501 .read_nvram = NULL,
2502 .write_nvram = NULL,
2503 .fw_dump = qla8044_fw_dump,
2504 .beacon_on = qla82xx_beacon_on,
2505 .beacon_off = qla82xx_beacon_off,
2506 .beacon_blink = NULL,
2507 .read_optrom = qla8044_read_optrom_data,
2508 .write_optrom = qla8044_write_optrom_data,
2509 .get_flash_version = qla82xx_get_flash_version,
2510 .start_scsi = qla82xx_start_scsi,
2511 .start_scsi_mq = NULL,
2512 .abort_isp = qla8044_abort_isp,
2513 .iospace_config = qla82xx_iospace_config,
2514 .initialize_adapter = qla2x00_initialize_adapter,
2515 };
2516
2517 static struct isp_operations qla83xx_isp_ops = {
2518 .pci_config = qla25xx_pci_config,
2519 .reset_chip = qla24xx_reset_chip,
2520 .chip_diag = qla24xx_chip_diag,
2521 .config_rings = qla24xx_config_rings,
2522 .reset_adapter = qla24xx_reset_adapter,
2523 .nvram_config = qla81xx_nvram_config,
2524 .update_fw_options = qla24xx_update_fw_options,
2525 .load_risc = qla81xx_load_risc,
2526 .pci_info_str = qla24xx_pci_info_str,
2527 .fw_version_str = qla24xx_fw_version_str,
2528 .intr_handler = qla24xx_intr_handler,
2529 .enable_intrs = qla24xx_enable_intrs,
2530 .disable_intrs = qla24xx_disable_intrs,
2531 .abort_command = qla24xx_abort_command,
2532 .target_reset = qla24xx_abort_target,
2533 .lun_reset = qla24xx_lun_reset,
2534 .fabric_login = qla24xx_login_fabric,
2535 .fabric_logout = qla24xx_fabric_logout,
2536 .calc_req_entries = NULL,
2537 .build_iocbs = NULL,
2538 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2539 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2540 .read_nvram = NULL,
2541 .write_nvram = NULL,
2542 .fw_dump = qla83xx_fw_dump,
2543 .beacon_on = qla24xx_beacon_on,
2544 .beacon_off = qla24xx_beacon_off,
2545 .beacon_blink = qla83xx_beacon_blink,
2546 .read_optrom = qla25xx_read_optrom_data,
2547 .write_optrom = qla24xx_write_optrom_data,
2548 .get_flash_version = qla24xx_get_flash_version,
2549 .start_scsi = qla24xx_dif_start_scsi,
2550 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2551 .abort_isp = qla2x00_abort_isp,
2552 .iospace_config = qla83xx_iospace_config,
2553 .initialize_adapter = qla2x00_initialize_adapter,
2554 };
2555
2556 static struct isp_operations qlafx00_isp_ops = {
2557 .pci_config = qlafx00_pci_config,
2558 .reset_chip = qlafx00_soft_reset,
2559 .chip_diag = qlafx00_chip_diag,
2560 .config_rings = qlafx00_config_rings,
2561 .reset_adapter = qlafx00_soft_reset,
2562 .nvram_config = NULL,
2563 .update_fw_options = NULL,
2564 .load_risc = NULL,
2565 .pci_info_str = qlafx00_pci_info_str,
2566 .fw_version_str = qlafx00_fw_version_str,
2567 .intr_handler = qlafx00_intr_handler,
2568 .enable_intrs = qlafx00_enable_intrs,
2569 .disable_intrs = qlafx00_disable_intrs,
2570 .abort_command = qla24xx_async_abort_command,
2571 .target_reset = qlafx00_abort_target,
2572 .lun_reset = qlafx00_lun_reset,
2573 .fabric_login = NULL,
2574 .fabric_logout = NULL,
2575 .calc_req_entries = NULL,
2576 .build_iocbs = NULL,
2577 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2578 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2579 .read_nvram = qla24xx_read_nvram_data,
2580 .write_nvram = qla24xx_write_nvram_data,
2581 .fw_dump = NULL,
2582 .beacon_on = qla24xx_beacon_on,
2583 .beacon_off = qla24xx_beacon_off,
2584 .beacon_blink = NULL,
2585 .read_optrom = qla24xx_read_optrom_data,
2586 .write_optrom = qla24xx_write_optrom_data,
2587 .get_flash_version = qla24xx_get_flash_version,
2588 .start_scsi = qlafx00_start_scsi,
2589 .start_scsi_mq = NULL,
2590 .abort_isp = qlafx00_abort_isp,
2591 .iospace_config = qlafx00_iospace_config,
2592 .initialize_adapter = qlafx00_initialize_adapter,
2593 };
2594
2595 static struct isp_operations qla27xx_isp_ops = {
2596 .pci_config = qla25xx_pci_config,
2597 .reset_chip = qla24xx_reset_chip,
2598 .chip_diag = qla24xx_chip_diag,
2599 .config_rings = qla24xx_config_rings,
2600 .reset_adapter = qla24xx_reset_adapter,
2601 .nvram_config = qla81xx_nvram_config,
2602 .update_fw_options = qla24xx_update_fw_options,
2603 .load_risc = qla81xx_load_risc,
2604 .pci_info_str = qla24xx_pci_info_str,
2605 .fw_version_str = qla24xx_fw_version_str,
2606 .intr_handler = qla24xx_intr_handler,
2607 .enable_intrs = qla24xx_enable_intrs,
2608 .disable_intrs = qla24xx_disable_intrs,
2609 .abort_command = qla24xx_abort_command,
2610 .target_reset = qla24xx_abort_target,
2611 .lun_reset = qla24xx_lun_reset,
2612 .fabric_login = qla24xx_login_fabric,
2613 .fabric_logout = qla24xx_fabric_logout,
2614 .calc_req_entries = NULL,
2615 .build_iocbs = NULL,
2616 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2617 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2618 .read_nvram = NULL,
2619 .write_nvram = NULL,
2620 .fw_dump = qla27xx_fwdump,
2621 .mpi_fw_dump = qla27xx_mpi_fwdump,
2622 .beacon_on = qla24xx_beacon_on,
2623 .beacon_off = qla24xx_beacon_off,
2624 .beacon_blink = qla83xx_beacon_blink,
2625 .read_optrom = qla25xx_read_optrom_data,
2626 .write_optrom = qla24xx_write_optrom_data,
2627 .get_flash_version = qla24xx_get_flash_version,
2628 .start_scsi = qla24xx_dif_start_scsi,
2629 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2630 .abort_isp = qla2x00_abort_isp,
2631 .iospace_config = qla83xx_iospace_config,
2632 .initialize_adapter = qla2x00_initialize_adapter,
2633 };
2634
2635 static inline void
qla2x00_set_isp_flags(struct qla_hw_data * ha)2636 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2637 {
2638 ha->device_type = DT_EXTENDED_IDS;
2639 switch (ha->pdev->device) {
2640 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2641 ha->isp_type |= DT_ISP2100;
2642 ha->device_type &= ~DT_EXTENDED_IDS;
2643 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2644 break;
2645 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2646 ha->isp_type |= DT_ISP2200;
2647 ha->device_type &= ~DT_EXTENDED_IDS;
2648 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2649 break;
2650 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2651 ha->isp_type |= DT_ISP2300;
2652 ha->device_type |= DT_ZIO_SUPPORTED;
2653 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2654 break;
2655 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2656 ha->isp_type |= DT_ISP2312;
2657 ha->device_type |= DT_ZIO_SUPPORTED;
2658 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2659 break;
2660 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2661 ha->isp_type |= DT_ISP2322;
2662 ha->device_type |= DT_ZIO_SUPPORTED;
2663 if (ha->pdev->subsystem_vendor == 0x1028 &&
2664 ha->pdev->subsystem_device == 0x0170)
2665 ha->device_type |= DT_OEM_001;
2666 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2667 break;
2668 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2669 ha->isp_type |= DT_ISP6312;
2670 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2671 break;
2672 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2673 ha->isp_type |= DT_ISP6322;
2674 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2675 break;
2676 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2677 ha->isp_type |= DT_ISP2422;
2678 ha->device_type |= DT_ZIO_SUPPORTED;
2679 ha->device_type |= DT_FWI2;
2680 ha->device_type |= DT_IIDMA;
2681 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2682 break;
2683 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2684 ha->isp_type |= DT_ISP2432;
2685 ha->device_type |= DT_ZIO_SUPPORTED;
2686 ha->device_type |= DT_FWI2;
2687 ha->device_type |= DT_IIDMA;
2688 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2689 break;
2690 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2691 ha->isp_type |= DT_ISP8432;
2692 ha->device_type |= DT_ZIO_SUPPORTED;
2693 ha->device_type |= DT_FWI2;
2694 ha->device_type |= DT_IIDMA;
2695 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2696 break;
2697 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2698 ha->isp_type |= DT_ISP5422;
2699 ha->device_type |= DT_FWI2;
2700 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2701 break;
2702 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2703 ha->isp_type |= DT_ISP5432;
2704 ha->device_type |= DT_FWI2;
2705 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2706 break;
2707 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2708 ha->isp_type |= DT_ISP2532;
2709 ha->device_type |= DT_ZIO_SUPPORTED;
2710 ha->device_type |= DT_FWI2;
2711 ha->device_type |= DT_IIDMA;
2712 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2713 break;
2714 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2715 ha->isp_type |= DT_ISP8001;
2716 ha->device_type |= DT_ZIO_SUPPORTED;
2717 ha->device_type |= DT_FWI2;
2718 ha->device_type |= DT_IIDMA;
2719 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2720 break;
2721 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2722 ha->isp_type |= DT_ISP8021;
2723 ha->device_type |= DT_ZIO_SUPPORTED;
2724 ha->device_type |= DT_FWI2;
2725 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2726 /* Initialize 82XX ISP flags */
2727 qla82xx_init_flags(ha);
2728 break;
2729 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2730 ha->isp_type |= DT_ISP8044;
2731 ha->device_type |= DT_ZIO_SUPPORTED;
2732 ha->device_type |= DT_FWI2;
2733 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2734 /* Initialize 82XX ISP flags */
2735 qla82xx_init_flags(ha);
2736 break;
2737 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2738 ha->isp_type |= DT_ISP2031;
2739 ha->device_type |= DT_ZIO_SUPPORTED;
2740 ha->device_type |= DT_FWI2;
2741 ha->device_type |= DT_IIDMA;
2742 ha->device_type |= DT_T10_PI;
2743 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2744 break;
2745 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2746 ha->isp_type |= DT_ISP8031;
2747 ha->device_type |= DT_ZIO_SUPPORTED;
2748 ha->device_type |= DT_FWI2;
2749 ha->device_type |= DT_IIDMA;
2750 ha->device_type |= DT_T10_PI;
2751 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2752 break;
2753 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2754 ha->isp_type |= DT_ISPFX00;
2755 break;
2756 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2757 ha->isp_type |= DT_ISP2071;
2758 ha->device_type |= DT_ZIO_SUPPORTED;
2759 ha->device_type |= DT_FWI2;
2760 ha->device_type |= DT_IIDMA;
2761 ha->device_type |= DT_T10_PI;
2762 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2763 break;
2764 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2765 ha->isp_type |= DT_ISP2271;
2766 ha->device_type |= DT_ZIO_SUPPORTED;
2767 ha->device_type |= DT_FWI2;
2768 ha->device_type |= DT_IIDMA;
2769 ha->device_type |= DT_T10_PI;
2770 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2771 break;
2772 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2773 ha->isp_type |= DT_ISP2261;
2774 ha->device_type |= DT_ZIO_SUPPORTED;
2775 ha->device_type |= DT_FWI2;
2776 ha->device_type |= DT_IIDMA;
2777 ha->device_type |= DT_T10_PI;
2778 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2779 break;
2780 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2781 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2782 ha->isp_type |= DT_ISP2081;
2783 ha->device_type |= DT_ZIO_SUPPORTED;
2784 ha->device_type |= DT_FWI2;
2785 ha->device_type |= DT_IIDMA;
2786 ha->device_type |= DT_T10_PI;
2787 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2788 break;
2789 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2790 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2791 ha->isp_type |= DT_ISP2281;
2792 ha->device_type |= DT_ZIO_SUPPORTED;
2793 ha->device_type |= DT_FWI2;
2794 ha->device_type |= DT_IIDMA;
2795 ha->device_type |= DT_T10_PI;
2796 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2797 break;
2798 }
2799
2800 if (IS_QLA82XX(ha))
2801 ha->port_no = ha->portnum & 1;
2802 else {
2803 /* Get adapter physical port no from interrupt pin register. */
2804 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2805 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2806 IS_QLA27XX(ha) || IS_QLA28XX(ha))
2807 ha->port_no--;
2808 else
2809 ha->port_no = !(ha->port_no & 1);
2810 }
2811
2812 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2813 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2814 ha->device_type, ha->port_no, ha->fw_srisc_address);
2815 }
2816
2817 static void
qla2xxx_scan_start(struct Scsi_Host * shost)2818 qla2xxx_scan_start(struct Scsi_Host *shost)
2819 {
2820 scsi_qla_host_t *vha = shost_priv(shost);
2821
2822 if (vha->hw->flags.running_gold_fw)
2823 return;
2824
2825 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2826 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2827 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2828 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2829 }
2830
2831 static int
qla2xxx_scan_finished(struct Scsi_Host * shost,unsigned long time)2832 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2833 {
2834 scsi_qla_host_t *vha = shost_priv(shost);
2835
2836 if (test_bit(UNLOADING, &vha->dpc_flags))
2837 return 1;
2838 if (!vha->host)
2839 return 1;
2840 if (time > vha->hw->loop_reset_delay * HZ)
2841 return 1;
2842
2843 return atomic_read(&vha->loop_state) == LOOP_READY;
2844 }
2845
qla_heartbeat_work_fn(struct work_struct * work)2846 static void qla_heartbeat_work_fn(struct work_struct *work)
2847 {
2848 struct qla_hw_data *ha = container_of(work,
2849 struct qla_hw_data, heartbeat_work);
2850 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2851
2852 if (!ha->flags.mbox_busy && base_vha->flags.init_done)
2853 qla_no_op_mb(base_vha);
2854 }
2855
qla2x00_iocb_work_fn(struct work_struct * work)2856 static void qla2x00_iocb_work_fn(struct work_struct *work)
2857 {
2858 struct scsi_qla_host *vha = container_of(work,
2859 struct scsi_qla_host, iocb_work);
2860 struct qla_hw_data *ha = vha->hw;
2861 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2862 int i = 2;
2863 unsigned long flags;
2864
2865 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2866 return;
2867
2868 while (!list_empty(&vha->work_list) && i > 0) {
2869 qla2x00_do_work(vha);
2870 i--;
2871 }
2872
2873 spin_lock_irqsave(&vha->work_lock, flags);
2874 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2875 spin_unlock_irqrestore(&vha->work_lock, flags);
2876 }
2877
2878 static void
qla_trace_init(void)2879 qla_trace_init(void)
2880 {
2881 qla_trc_array = trace_array_get_by_name("qla2xxx", NULL);
2882 if (!qla_trc_array) {
2883 ql_log(ql_log_fatal, NULL, 0x0001,
2884 "Unable to create qla2xxx trace instance, instance logging will be disabled.\n");
2885 return;
2886 }
2887
2888 QLA_TRACE_ENABLE(qla_trc_array);
2889 }
2890
2891 static void
qla_trace_uninit(void)2892 qla_trace_uninit(void)
2893 {
2894 if (!qla_trc_array)
2895 return;
2896 trace_array_put(qla_trc_array);
2897 }
2898
2899 /*
2900 * PCI driver interface
2901 */
2902 static int
qla2x00_probe_one(struct pci_dev * pdev,const struct pci_device_id * id)2903 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2904 {
2905 int ret = -ENODEV;
2906 struct Scsi_Host *host;
2907 scsi_qla_host_t *base_vha = NULL;
2908 struct qla_hw_data *ha;
2909 char pci_info[30];
2910 char fw_str[30], wq_name[30];
2911 struct scsi_host_template *sht;
2912 int bars, mem_only = 0;
2913 uint16_t req_length = 0, rsp_length = 0;
2914 struct req_que *req = NULL;
2915 struct rsp_que *rsp = NULL;
2916 int i;
2917
2918 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2919 sht = &qla2xxx_driver_template;
2920 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2921 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2922 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2923 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2924 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2925 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2926 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2927 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2928 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2929 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2930 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2931 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2932 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2933 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2934 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2935 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2936 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2937 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2938 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
2939 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2940 mem_only = 1;
2941 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2942 "Mem only adapter.\n");
2943 }
2944 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2945 "Bars=%d.\n", bars);
2946
2947 if (mem_only) {
2948 if (pci_enable_device_mem(pdev))
2949 return ret;
2950 } else {
2951 if (pci_enable_device(pdev))
2952 return ret;
2953 }
2954
2955 if (is_kdump_kernel()) {
2956 ql2xmqsupport = 0;
2957 ql2xallocfwdump = 0;
2958 }
2959
2960 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2961 if (!ha) {
2962 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2963 "Unable to allocate memory for ha.\n");
2964 goto disable_device;
2965 }
2966 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2967 "Memory allocated for ha=%p.\n", ha);
2968 ha->pdev = pdev;
2969 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2970 spin_lock_init(&ha->tgt.q_full_lock);
2971 spin_lock_init(&ha->tgt.sess_lock);
2972 spin_lock_init(&ha->tgt.atio_lock);
2973
2974 spin_lock_init(&ha->sadb_lock);
2975 INIT_LIST_HEAD(&ha->sadb_tx_index_list);
2976 INIT_LIST_HEAD(&ha->sadb_rx_index_list);
2977
2978 spin_lock_init(&ha->sadb_fp_lock);
2979
2980 if (qla_edif_sadb_build_free_pool(ha)) {
2981 kfree(ha);
2982 goto disable_device;
2983 }
2984
2985 atomic_set(&ha->nvme_active_aen_cnt, 0);
2986
2987 /* Clear our data area */
2988 ha->bars = bars;
2989 ha->mem_only = mem_only;
2990 spin_lock_init(&ha->hardware_lock);
2991 spin_lock_init(&ha->vport_slock);
2992 mutex_init(&ha->selflogin_lock);
2993 mutex_init(&ha->optrom_mutex);
2994
2995 /* Set ISP-type information. */
2996 qla2x00_set_isp_flags(ha);
2997
2998 /* Set EEH reset type to fundamental if required by hba */
2999 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
3000 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3001 pdev->needs_freset = 1;
3002
3003 ha->prev_topology = 0;
3004 ha->init_cb_size = sizeof(init_cb_t);
3005 ha->link_data_rate = PORT_SPEED_UNKNOWN;
3006 ha->optrom_size = OPTROM_SIZE_2300;
3007 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
3008 atomic_set(&ha->num_pend_mbx_stage1, 0);
3009 atomic_set(&ha->num_pend_mbx_stage2, 0);
3010 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
3011 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
3012 INIT_LIST_HEAD(&ha->tmf_pending);
3013 INIT_LIST_HEAD(&ha->tmf_active);
3014
3015 /* Assign ISP specific operations. */
3016 if (IS_QLA2100(ha)) {
3017 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3018 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
3019 req_length = REQUEST_ENTRY_CNT_2100;
3020 rsp_length = RESPONSE_ENTRY_CNT_2100;
3021 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3022 ha->gid_list_info_size = 4;
3023 ha->flash_conf_off = ~0;
3024 ha->flash_data_off = ~0;
3025 ha->nvram_conf_off = ~0;
3026 ha->nvram_data_off = ~0;
3027 ha->isp_ops = &qla2100_isp_ops;
3028 } else if (IS_QLA2200(ha)) {
3029 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3030 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
3031 req_length = REQUEST_ENTRY_CNT_2200;
3032 rsp_length = RESPONSE_ENTRY_CNT_2100;
3033 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3034 ha->gid_list_info_size = 4;
3035 ha->flash_conf_off = ~0;
3036 ha->flash_data_off = ~0;
3037 ha->nvram_conf_off = ~0;
3038 ha->nvram_data_off = ~0;
3039 ha->isp_ops = &qla2100_isp_ops;
3040 } else if (IS_QLA23XX(ha)) {
3041 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3042 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3043 req_length = REQUEST_ENTRY_CNT_2200;
3044 rsp_length = RESPONSE_ENTRY_CNT_2300;
3045 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3046 ha->gid_list_info_size = 6;
3047 if (IS_QLA2322(ha) || IS_QLA6322(ha))
3048 ha->optrom_size = OPTROM_SIZE_2322;
3049 ha->flash_conf_off = ~0;
3050 ha->flash_data_off = ~0;
3051 ha->nvram_conf_off = ~0;
3052 ha->nvram_data_off = ~0;
3053 ha->isp_ops = &qla2300_isp_ops;
3054 } else if (IS_QLA24XX_TYPE(ha)) {
3055 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3056 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3057 req_length = REQUEST_ENTRY_CNT_24XX;
3058 rsp_length = RESPONSE_ENTRY_CNT_2300;
3059 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3060 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3061 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3062 ha->gid_list_info_size = 8;
3063 ha->optrom_size = OPTROM_SIZE_24XX;
3064 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
3065 ha->isp_ops = &qla24xx_isp_ops;
3066 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3067 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3068 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3069 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3070 } else if (IS_QLA25XX(ha)) {
3071 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3072 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3073 req_length = REQUEST_ENTRY_CNT_24XX;
3074 rsp_length = RESPONSE_ENTRY_CNT_2300;
3075 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3076 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3077 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3078 ha->gid_list_info_size = 8;
3079 ha->optrom_size = OPTROM_SIZE_25XX;
3080 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3081 ha->isp_ops = &qla25xx_isp_ops;
3082 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3083 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3084 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3085 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3086 } else if (IS_QLA81XX(ha)) {
3087 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3088 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3089 req_length = REQUEST_ENTRY_CNT_24XX;
3090 rsp_length = RESPONSE_ENTRY_CNT_2300;
3091 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3092 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3093 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3094 ha->gid_list_info_size = 8;
3095 ha->optrom_size = OPTROM_SIZE_81XX;
3096 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3097 ha->isp_ops = &qla81xx_isp_ops;
3098 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3099 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3100 ha->nvram_conf_off = ~0;
3101 ha->nvram_data_off = ~0;
3102 } else if (IS_QLA82XX(ha)) {
3103 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3104 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3105 req_length = REQUEST_ENTRY_CNT_82XX;
3106 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3107 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3108 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3109 ha->gid_list_info_size = 8;
3110 ha->optrom_size = OPTROM_SIZE_82XX;
3111 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3112 ha->isp_ops = &qla82xx_isp_ops;
3113 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3114 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3115 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3116 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3117 } else if (IS_QLA8044(ha)) {
3118 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3119 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3120 req_length = REQUEST_ENTRY_CNT_82XX;
3121 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3122 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3123 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3124 ha->gid_list_info_size = 8;
3125 ha->optrom_size = OPTROM_SIZE_83XX;
3126 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3127 ha->isp_ops = &qla8044_isp_ops;
3128 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3129 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3130 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3131 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3132 } else if (IS_QLA83XX(ha)) {
3133 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3134 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3135 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3136 req_length = REQUEST_ENTRY_CNT_83XX;
3137 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3138 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3139 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3140 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3141 ha->gid_list_info_size = 8;
3142 ha->optrom_size = OPTROM_SIZE_83XX;
3143 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3144 ha->isp_ops = &qla83xx_isp_ops;
3145 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3146 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3147 ha->nvram_conf_off = ~0;
3148 ha->nvram_data_off = ~0;
3149 } else if (IS_QLAFX00(ha)) {
3150 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3151 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3152 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3153 req_length = REQUEST_ENTRY_CNT_FX00;
3154 rsp_length = RESPONSE_ENTRY_CNT_FX00;
3155 ha->isp_ops = &qlafx00_isp_ops;
3156 ha->port_down_retry_count = 30; /* default value */
3157 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3158 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
3159 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
3160 ha->mr.fw_hbt_en = 1;
3161 ha->mr.host_info_resend = false;
3162 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
3163 } else if (IS_QLA27XX(ha)) {
3164 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3165 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3166 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3167 req_length = REQUEST_ENTRY_CNT_83XX;
3168 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3169 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3170 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3171 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3172 ha->gid_list_info_size = 8;
3173 ha->optrom_size = OPTROM_SIZE_83XX;
3174 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3175 ha->isp_ops = &qla27xx_isp_ops;
3176 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3177 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3178 ha->nvram_conf_off = ~0;
3179 ha->nvram_data_off = ~0;
3180 } else if (IS_QLA28XX(ha)) {
3181 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3182 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3183 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3184 req_length = REQUEST_ENTRY_CNT_83XX;
3185 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3186 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3187 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3188 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3189 ha->gid_list_info_size = 8;
3190 ha->optrom_size = OPTROM_SIZE_28XX;
3191 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3192 ha->isp_ops = &qla27xx_isp_ops;
3193 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3194 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3195 ha->nvram_conf_off = ~0;
3196 ha->nvram_data_off = ~0;
3197 }
3198
3199 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3200 "mbx_count=%d, req_length=%d, "
3201 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
3202 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3203 "max_fibre_devices=%d.\n",
3204 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3205 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3206 ha->nvram_npiv_size, ha->max_fibre_devices);
3207 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3208 "isp_ops=%p, flash_conf_off=%d, "
3209 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3210 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3211 ha->nvram_conf_off, ha->nvram_data_off);
3212
3213 /* Configure PCI I/O space */
3214 ret = ha->isp_ops->iospace_config(ha);
3215 if (ret)
3216 goto iospace_config_failed;
3217
3218 ql_log_pci(ql_log_info, pdev, 0x001d,
3219 "Found an ISP%04X irq %d iobase 0x%p.\n",
3220 pdev->device, pdev->irq, ha->iobase);
3221 mutex_init(&ha->vport_lock);
3222 mutex_init(&ha->mq_lock);
3223 init_completion(&ha->mbx_cmd_comp);
3224 complete(&ha->mbx_cmd_comp);
3225 init_completion(&ha->mbx_intr_comp);
3226 init_completion(&ha->dcbx_comp);
3227 init_completion(&ha->lb_portup_comp);
3228
3229 set_bit(0, (unsigned long *) ha->vp_idx_map);
3230
3231 qla2x00_config_dma_addressing(ha);
3232 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3233 "64 Bit addressing is %s.\n",
3234 ha->flags.enable_64bit_addressing ? "enable" :
3235 "disable");
3236 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3237 if (ret) {
3238 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3239 "Failed to allocate memory for adapter, aborting.\n");
3240
3241 goto probe_hw_failed;
3242 }
3243
3244 req->max_q_depth = MAX_Q_DEPTH;
3245 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3246 req->max_q_depth = ql2xmaxqdepth;
3247
3248
3249 base_vha = qla2x00_create_host(sht, ha);
3250 if (!base_vha) {
3251 ret = -ENOMEM;
3252 goto probe_hw_failed;
3253 }
3254
3255 pci_set_drvdata(pdev, base_vha);
3256 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3257
3258 host = base_vha->host;
3259 base_vha->req = req;
3260 if (IS_QLA2XXX_MIDTYPE(ha))
3261 base_vha->mgmt_svr_loop_id =
3262 qla2x00_reserve_mgmt_server_loop_id(base_vha);
3263 else
3264 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3265 base_vha->vp_idx;
3266
3267 /* Setup fcport template structure. */
3268 ha->mr.fcport.vha = base_vha;
3269 ha->mr.fcport.port_type = FCT_UNKNOWN;
3270 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3271 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3272 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3273 ha->mr.fcport.scan_state = 1;
3274
3275 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN |
3276 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT |
3277 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN);
3278
3279 /* Set the SG table size based on ISP type */
3280 if (!IS_FWI2_CAPABLE(ha)) {
3281 if (IS_QLA2100(ha))
3282 host->sg_tablesize = 32;
3283 } else {
3284 if (!IS_QLA82XX(ha))
3285 host->sg_tablesize = QLA_SG_ALL;
3286 }
3287 host->max_id = ha->max_fibre_devices;
3288 host->cmd_per_lun = 3;
3289 host->unique_id = host->host_no;
3290
3291 if (ql2xenabledif && ql2xenabledif != 2) {
3292 ql_log(ql_log_warn, base_vha, 0x302d,
3293 "Invalid value for ql2xenabledif, resetting it to default (2)\n");
3294 ql2xenabledif = 2;
3295 }
3296
3297 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3298 host->max_cmd_len = 32;
3299 else
3300 host->max_cmd_len = MAX_CMDSZ;
3301 host->max_channel = MAX_BUSES - 1;
3302 /* Older HBAs support only 16-bit LUNs */
3303 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3304 ql2xmaxlun > 0xffff)
3305 host->max_lun = 0xffff;
3306 else
3307 host->max_lun = ql2xmaxlun;
3308 host->transportt = qla2xxx_transport_template;
3309 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3310
3311 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3312 "max_id=%d this_id=%d "
3313 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3314 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3315 host->this_id, host->cmd_per_lun, host->unique_id,
3316 host->max_cmd_len, host->max_channel, host->max_lun,
3317 host->transportt, sht->vendor_id);
3318
3319 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn);
3320
3321 /* Set up the irqs */
3322 ret = qla2x00_request_irqs(ha, rsp);
3323 if (ret)
3324 goto probe_failed;
3325
3326 /* Alloc arrays of request and response ring ptrs */
3327 ret = qla2x00_alloc_queues(ha, req, rsp);
3328 if (ret) {
3329 ql_log(ql_log_fatal, base_vha, 0x003d,
3330 "Failed to allocate memory for queue pointers..."
3331 "aborting.\n");
3332 ret = -ENODEV;
3333 goto probe_failed;
3334 }
3335
3336 if (ha->mqenable) {
3337 /* number of hardware queues supported by blk/scsi-mq*/
3338 host->nr_hw_queues = ha->max_qpairs;
3339
3340 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3341 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3342 } else {
3343 if (ql2xnvmeenable) {
3344 host->nr_hw_queues = ha->max_qpairs;
3345 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3346 "FC-NVMe support is enabled, HW queues=%d\n",
3347 host->nr_hw_queues);
3348 } else {
3349 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3350 "blk/scsi-mq disabled.\n");
3351 }
3352 }
3353
3354 qlt_probe_one_stage1(base_vha, ha);
3355
3356 pci_save_state(pdev);
3357
3358 /* Assign back pointers */
3359 rsp->req = req;
3360 req->rsp = rsp;
3361
3362 if (IS_QLAFX00(ha)) {
3363 ha->rsp_q_map[0] = rsp;
3364 ha->req_q_map[0] = req;
3365 set_bit(0, ha->req_qid_map);
3366 set_bit(0, ha->rsp_qid_map);
3367 }
3368
3369 /* FWI2-capable only. */
3370 req->req_q_in = &ha->iobase->isp24.req_q_in;
3371 req->req_q_out = &ha->iobase->isp24.req_q_out;
3372 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3373 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3374 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3375 IS_QLA28XX(ha)) {
3376 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3377 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3378 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3379 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
3380 }
3381
3382 if (IS_QLAFX00(ha)) {
3383 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3384 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3385 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3386 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3387 }
3388
3389 if (IS_P3P_TYPE(ha)) {
3390 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3391 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3392 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3393 }
3394
3395 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3396 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3397 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3398 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3399 "req->req_q_in=%p req->req_q_out=%p "
3400 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3401 req->req_q_in, req->req_q_out,
3402 rsp->rsp_q_in, rsp->rsp_q_out);
3403 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3404 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3405 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3406 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3407 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3408 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3409
3410 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM | WQ_PERCPU, 0);
3411 if (unlikely(!ha->wq)) {
3412 ret = -ENOMEM;
3413 goto probe_failed;
3414 }
3415
3416 if (ha->isp_ops->initialize_adapter(base_vha)) {
3417 ql_log(ql_log_fatal, base_vha, 0x00d6,
3418 "Failed to initialize adapter - Adapter flags %x.\n",
3419 base_vha->device_flags);
3420
3421 if (IS_QLA82XX(ha)) {
3422 qla82xx_idc_lock(ha);
3423 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3424 QLA8XXX_DEV_FAILED);
3425 qla82xx_idc_unlock(ha);
3426 ql_log(ql_log_fatal, base_vha, 0x00d7,
3427 "HW State: FAILED.\n");
3428 } else if (IS_QLA8044(ha)) {
3429 qla8044_idc_lock(ha);
3430 qla8044_wr_direct(base_vha,
3431 QLA8044_CRB_DEV_STATE_INDEX,
3432 QLA8XXX_DEV_FAILED);
3433 qla8044_idc_unlock(ha);
3434 ql_log(ql_log_fatal, base_vha, 0x0150,
3435 "HW State: FAILED.\n");
3436 }
3437
3438 ret = -ENODEV;
3439 goto probe_failed;
3440 }
3441
3442 if (IS_QLAFX00(ha))
3443 host->can_queue = QLAFX00_MAX_CANQUEUE;
3444 else
3445 host->can_queue = req->num_outstanding_cmds - 10;
3446
3447 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3448 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3449 host->can_queue, base_vha->req,
3450 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3451
3452 /* Check if FW supports MQ or not for ISP25xx */
3453 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6))
3454 ha->mqenable = 0;
3455
3456 if (ha->mqenable) {
3457 bool startit = !!(host->active_mode & MODE_INITIATOR);
3458
3459 /* Create start of day qpairs for Block MQ */
3460 for (i = 0; i < ha->max_qpairs; i++)
3461 qla2xxx_create_qpair(base_vha, 5, 0, startit);
3462 }
3463 qla_init_iocb_limit(base_vha);
3464
3465 if (ha->flags.running_gold_fw)
3466 goto skip_dpc;
3467
3468 /*
3469 * Startup the kernel thread for this host adapter
3470 */
3471 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3472 "%s_dpc", base_vha->host_str);
3473 if (IS_ERR(ha->dpc_thread)) {
3474 ql_log(ql_log_fatal, base_vha, 0x00ed,
3475 "Failed to start DPC thread.\n");
3476 ret = PTR_ERR(ha->dpc_thread);
3477 ha->dpc_thread = NULL;
3478 goto probe_failed;
3479 }
3480 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3481 "DPC thread started successfully.\n");
3482
3483 /*
3484 * If we're not coming up in initiator mode, we might sit for
3485 * a while without waking up the dpc thread, which leads to a
3486 * stuck process warning. So just kick the dpc once here and
3487 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3488 */
3489 qla2xxx_wake_dpc(base_vha);
3490
3491 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3492
3493 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3494 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3495 ha->dpc_lp_wq =
3496 alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, wq_name);
3497 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3498
3499 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3500 ha->dpc_hp_wq =
3501 alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, wq_name);
3502 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3503 INIT_WORK(&ha->idc_state_handler,
3504 qla83xx_idc_state_handler_work);
3505 INIT_WORK(&ha->nic_core_unrecoverable,
3506 qla83xx_nic_core_unrecoverable_work);
3507 }
3508
3509 skip_dpc:
3510 list_add_tail(&base_vha->list, &ha->vp_list);
3511 base_vha->host->irq = ha->pdev->irq;
3512
3513 /* Initialized the timer */
3514 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3515 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3516 "Started qla2x00_timer with "
3517 "interval=%d.\n", WATCH_INTERVAL);
3518 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3519 "Detected hba at address=%p.\n",
3520 ha);
3521
3522 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3523 if (ha->fw_attributes & BIT_4) {
3524 int prot = 0, guard;
3525
3526 base_vha->flags.difdix_supported = 1;
3527 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3528 "Registering for DIF/DIX type 1 and 3 protection.\n");
3529 if (ql2xprotmask)
3530 scsi_host_set_prot(host, ql2xprotmask);
3531 else
3532 scsi_host_set_prot(host,
3533 prot | SHOST_DIF_TYPE1_PROTECTION
3534 | SHOST_DIF_TYPE2_PROTECTION
3535 | SHOST_DIF_TYPE3_PROTECTION
3536 | SHOST_DIX_TYPE1_PROTECTION
3537 | SHOST_DIX_TYPE2_PROTECTION
3538 | SHOST_DIX_TYPE3_PROTECTION);
3539
3540 guard = SHOST_DIX_GUARD_CRC;
3541
3542 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3543 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3544 guard |= SHOST_DIX_GUARD_IP;
3545
3546 if (ql2xprotguard)
3547 scsi_host_set_guard(host, ql2xprotguard);
3548 else
3549 scsi_host_set_guard(host, guard);
3550 } else
3551 base_vha->flags.difdix_supported = 0;
3552 }
3553
3554 ha->isp_ops->enable_intrs(ha);
3555
3556 if (IS_QLAFX00(ha)) {
3557 ret = qlafx00_fx_disc(base_vha,
3558 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3559 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3560 QLA_SG_ALL : 128;
3561 }
3562
3563 if (IS_T10_PI_CAPABLE(base_vha->hw))
3564 host->dma_alignment = 0x7;
3565
3566 ret = scsi_add_host(host, &pdev->dev);
3567 if (ret)
3568 goto probe_failed;
3569
3570 base_vha->flags.init_done = 1;
3571 base_vha->flags.online = 1;
3572 ha->prev_minidump_failed = 0;
3573
3574 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3575 "Init done and hba is online.\n");
3576
3577 if (qla_ini_mode_enabled(base_vha) ||
3578 qla_dual_mode_enabled(base_vha))
3579 scsi_scan_host(host);
3580 else
3581 ql_log(ql_log_info, base_vha, 0x0122,
3582 "skipping scsi_scan_host() for non-initiator port\n");
3583
3584 qla2x00_alloc_sysfs_attr(base_vha);
3585
3586 if (IS_QLAFX00(ha)) {
3587 ret = qlafx00_fx_disc(base_vha,
3588 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3589
3590 /* Register system information */
3591 ret = qlafx00_fx_disc(base_vha,
3592 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3593 }
3594
3595 qla2x00_init_host_attr(base_vha);
3596
3597 qla2x00_dfs_setup(base_vha);
3598
3599 ql_log(ql_log_info, base_vha, 0x00fb,
3600 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3601 ql_log(ql_log_info, base_vha, 0x00fc,
3602 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3603 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3604 sizeof(pci_info)),
3605 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3606 base_vha->host_no,
3607 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3608
3609 qlt_add_target(ha, base_vha);
3610
3611 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3612
3613 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3614 return -ENODEV;
3615
3616 return 0;
3617
3618 probe_failed:
3619 qla_enode_stop(base_vha);
3620 qla_edb_stop(base_vha);
3621 vfree(base_vha->scan.l);
3622 if (base_vha->gnl.l) {
3623 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3624 base_vha->gnl.l, base_vha->gnl.ldma);
3625 base_vha->gnl.l = NULL;
3626 }
3627
3628 if (base_vha->timer_active)
3629 qla2x00_stop_timer(base_vha);
3630 base_vha->flags.online = 0;
3631 if (ha->dpc_thread) {
3632 struct task_struct *t = ha->dpc_thread;
3633
3634 ha->dpc_thread = NULL;
3635 kthread_stop(t);
3636 }
3637
3638 qla2x00_free_device(base_vha);
3639 scsi_host_put(base_vha->host);
3640 /*
3641 * Need to NULL out local req/rsp after
3642 * qla2x00_free_device => qla2x00_free_queues frees
3643 * what these are pointing to. Or else we'll
3644 * fall over below in qla2x00_free_req/rsp_que.
3645 */
3646 req = NULL;
3647 rsp = NULL;
3648
3649 probe_hw_failed:
3650 qla2x00_mem_free(ha);
3651 qla2x00_free_req_que(ha, req);
3652 qla2x00_free_rsp_que(ha, rsp);
3653 qla2x00_clear_drv_active(ha);
3654
3655 iospace_config_failed:
3656 if (IS_P3P_TYPE(ha)) {
3657 if (!ha->nx_pcibase)
3658 iounmap((device_reg_t *)ha->nx_pcibase);
3659 if (!ql2xdbwr)
3660 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3661 } else {
3662 if (ha->iobase)
3663 iounmap(ha->iobase);
3664 if (ha->cregbase)
3665 iounmap(ha->cregbase);
3666 }
3667 pci_release_selected_regions(ha->pdev, ha->bars);
3668 kfree(ha);
3669
3670 disable_device:
3671 pci_disable_device(pdev);
3672 return ret;
3673 }
3674
__qla_set_remove_flag(scsi_qla_host_t * base_vha)3675 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha)
3676 {
3677 scsi_qla_host_t *vp;
3678 unsigned long flags;
3679 struct qla_hw_data *ha;
3680
3681 if (!base_vha)
3682 return;
3683
3684 ha = base_vha->hw;
3685
3686 spin_lock_irqsave(&ha->vport_slock, flags);
3687 list_for_each_entry(vp, &ha->vp_list, list)
3688 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);
3689
3690 /*
3691 * Indicate device removal to prevent future board_disable
3692 * and wait until any pending board_disable has completed.
3693 */
3694 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3695 spin_unlock_irqrestore(&ha->vport_slock, flags);
3696 }
3697
3698 static void
qla2x00_shutdown(struct pci_dev * pdev)3699 qla2x00_shutdown(struct pci_dev *pdev)
3700 {
3701 scsi_qla_host_t *vha;
3702 struct qla_hw_data *ha;
3703
3704 vha = pci_get_drvdata(pdev);
3705 ha = vha->hw;
3706
3707 ql_log(ql_log_info, vha, 0xfffa,
3708 "Adapter shutdown\n");
3709
3710 /*
3711 * Prevent future board_disable and wait
3712 * until any pending board_disable has completed.
3713 */
3714 __qla_set_remove_flag(vha);
3715 cancel_work_sync(&ha->board_disable);
3716
3717 if (!atomic_read(&pdev->enable_cnt))
3718 return;
3719
3720 /* Notify ISPFX00 firmware */
3721 if (IS_QLAFX00(ha))
3722 qlafx00_driver_shutdown(vha, 20);
3723
3724 /* Turn-off FCE trace */
3725 if (ha->flags.fce_enabled) {
3726 qla2x00_disable_fce_trace(vha, NULL, NULL);
3727 ha->flags.fce_enabled = 0;
3728 }
3729
3730 /* Turn-off EFT trace */
3731 if (ha->eft)
3732 qla2x00_disable_eft_trace(vha);
3733
3734 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3735 IS_QLA28XX(ha)) {
3736 if (ha->flags.fw_started)
3737 qla2x00_abort_isp_cleanup(vha);
3738 } else {
3739 /* Stop currently executing firmware. */
3740 qla2x00_try_to_stop_firmware(vha);
3741 }
3742
3743 /* Disable timer */
3744 if (vha->timer_active)
3745 qla2x00_stop_timer(vha);
3746
3747 /* Turn adapter off line */
3748 vha->flags.online = 0;
3749
3750 /* turn-off interrupts on the card */
3751 if (ha->interrupts_on) {
3752 vha->flags.init_done = 0;
3753 ha->isp_ops->disable_intrs(ha);
3754 }
3755
3756 qla2x00_free_irqs(vha);
3757
3758 qla2x00_free_fw_dump(ha);
3759
3760 pci_disable_device(pdev);
3761 ql_log(ql_log_info, vha, 0xfffe,
3762 "Adapter shutdown successfully.\n");
3763 }
3764
3765 /* Deletes all the virtual ports for a given ha */
3766 static void
qla2x00_delete_all_vps(struct qla_hw_data * ha,scsi_qla_host_t * base_vha)3767 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3768 {
3769 scsi_qla_host_t *vha;
3770 unsigned long flags;
3771
3772 mutex_lock(&ha->vport_lock);
3773 while (ha->cur_vport_count) {
3774 spin_lock_irqsave(&ha->vport_slock, flags);
3775
3776 BUG_ON(base_vha->list.next == &ha->vp_list);
3777 /* This assumes first entry in ha->vp_list is always base vha */
3778 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3779 scsi_host_get(vha->host);
3780
3781 spin_unlock_irqrestore(&ha->vport_slock, flags);
3782 mutex_unlock(&ha->vport_lock);
3783
3784 qla_nvme_delete(vha);
3785
3786 fc_vport_terminate(vha->fc_vport);
3787 scsi_host_put(vha->host);
3788
3789 mutex_lock(&ha->vport_lock);
3790 }
3791 mutex_unlock(&ha->vport_lock);
3792 }
3793
3794 /* Stops all deferred work threads */
3795 static void
qla2x00_destroy_deferred_work(struct qla_hw_data * ha)3796 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3797 {
3798 /* Cancel all work and destroy DPC workqueues */
3799 if (ha->dpc_lp_wq) {
3800 cancel_work_sync(&ha->idc_aen);
3801 destroy_workqueue(ha->dpc_lp_wq);
3802 ha->dpc_lp_wq = NULL;
3803 }
3804
3805 if (ha->dpc_hp_wq) {
3806 cancel_work_sync(&ha->nic_core_reset);
3807 cancel_work_sync(&ha->idc_state_handler);
3808 cancel_work_sync(&ha->nic_core_unrecoverable);
3809 destroy_workqueue(ha->dpc_hp_wq);
3810 ha->dpc_hp_wq = NULL;
3811 }
3812
3813 /* Kill the kernel thread for this host */
3814 if (ha->dpc_thread) {
3815 struct task_struct *t = ha->dpc_thread;
3816
3817 /*
3818 * qla2xxx_wake_dpc checks for ->dpc_thread
3819 * so we need to zero it out.
3820 */
3821 ha->dpc_thread = NULL;
3822 kthread_stop(t);
3823 }
3824 }
3825
3826 static void
qla2x00_unmap_iobases(struct qla_hw_data * ha)3827 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3828 {
3829 if (IS_QLA82XX(ha)) {
3830
3831 iounmap((device_reg_t *)ha->nx_pcibase);
3832 if (!ql2xdbwr)
3833 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3834 } else {
3835 if (ha->iobase)
3836 iounmap(ha->iobase);
3837
3838 if (ha->cregbase)
3839 iounmap(ha->cregbase);
3840
3841 if (ha->mqiobase)
3842 iounmap(ha->mqiobase);
3843
3844 if (ha->msixbase)
3845 iounmap(ha->msixbase);
3846 }
3847 }
3848
3849 static void
qla2x00_clear_drv_active(struct qla_hw_data * ha)3850 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3851 {
3852 if (IS_QLA8044(ha)) {
3853 qla8044_idc_lock(ha);
3854 qla8044_clear_drv_active(ha);
3855 qla8044_idc_unlock(ha);
3856 } else if (IS_QLA82XX(ha)) {
3857 qla82xx_idc_lock(ha);
3858 qla82xx_clear_drv_active(ha);
3859 qla82xx_idc_unlock(ha);
3860 }
3861 }
3862
3863 static void
qla2x00_remove_one(struct pci_dev * pdev)3864 qla2x00_remove_one(struct pci_dev *pdev)
3865 {
3866 scsi_qla_host_t *base_vha;
3867 struct qla_hw_data *ha;
3868
3869 base_vha = pci_get_drvdata(pdev);
3870 ha = base_vha->hw;
3871 ql_log(ql_log_info, base_vha, 0xb079,
3872 "Removing driver\n");
3873 __qla_set_remove_flag(base_vha);
3874 cancel_work_sync(&ha->board_disable);
3875
3876 /*
3877 * If the PCI device is disabled then there was a PCI-disconnect and
3878 * qla2x00_disable_board_on_pci_error has taken care of most of the
3879 * resources.
3880 */
3881 if (!atomic_read(&pdev->enable_cnt)) {
3882 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3883 base_vha->gnl.l, base_vha->gnl.ldma);
3884 base_vha->gnl.l = NULL;
3885 scsi_host_put(base_vha->host);
3886 kfree(ha);
3887 pci_set_drvdata(pdev, NULL);
3888 return;
3889 }
3890 qla2x00_wait_for_hba_ready(base_vha);
3891
3892 /*
3893 * if UNLOADING flag is already set, then continue unload,
3894 * where it was set first.
3895 */
3896 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
3897 return;
3898
3899 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3900 IS_QLA28XX(ha)) {
3901 if (ha->flags.fw_started)
3902 qla2x00_abort_isp_cleanup(base_vha);
3903 } else if (!IS_QLAFX00(ha)) {
3904 if (IS_QLA8031(ha)) {
3905 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3906 "Clearing fcoe driver presence.\n");
3907 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3908 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3909 "Error while clearing DRV-Presence.\n");
3910 }
3911
3912 qla2x00_try_to_stop_firmware(base_vha);
3913 }
3914
3915 qla2x00_wait_for_sess_deletion(base_vha);
3916
3917 qla_nvme_delete(base_vha);
3918
3919 dma_free_coherent(&ha->pdev->dev,
3920 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3921
3922 base_vha->gnl.l = NULL;
3923 qla_enode_stop(base_vha);
3924 qla_edb_stop(base_vha);
3925
3926 vfree(base_vha->scan.l);
3927
3928 if (IS_QLAFX00(ha))
3929 qlafx00_driver_shutdown(base_vha, 20);
3930
3931 qla2x00_delete_all_vps(ha, base_vha);
3932
3933 qla2x00_dfs_remove(base_vha);
3934
3935 qla84xx_put_chip(base_vha);
3936
3937 /* Disable timer */
3938 if (base_vha->timer_active)
3939 qla2x00_stop_timer(base_vha);
3940
3941 base_vha->flags.online = 0;
3942
3943 /* free DMA memory */
3944 if (ha->exlogin_buf)
3945 qla2x00_free_exlogin_buffer(ha);
3946
3947 /* free DMA memory */
3948 if (ha->exchoffld_buf)
3949 qla2x00_free_exchoffld_buffer(ha);
3950
3951 qla2x00_destroy_deferred_work(ha);
3952
3953 qlt_remove_target(ha, base_vha);
3954
3955 qla2x00_free_sysfs_attr(base_vha, true);
3956
3957 fc_remove_host(base_vha->host);
3958
3959 scsi_remove_host(base_vha->host);
3960
3961 qla2x00_free_device(base_vha);
3962
3963 qla2x00_clear_drv_active(ha);
3964
3965 scsi_host_put(base_vha->host);
3966
3967 qla2x00_unmap_iobases(ha);
3968
3969 pci_release_selected_regions(ha->pdev, ha->bars);
3970 kfree(ha);
3971
3972 pci_disable_device(pdev);
3973 }
3974
3975 static inline void
qla24xx_free_purex_list(struct purex_list * list)3976 qla24xx_free_purex_list(struct purex_list *list)
3977 {
3978 struct purex_item *item, *next;
3979 ulong flags;
3980
3981 spin_lock_irqsave(&list->lock, flags);
3982 list_for_each_entry_safe(item, next, &list->head, list) {
3983 list_del(&item->list);
3984 if (item == &item->vha->default_item)
3985 continue;
3986 kfree(item);
3987 }
3988 spin_unlock_irqrestore(&list->lock, flags);
3989 }
3990
3991 static void
qla2x00_free_device(scsi_qla_host_t * vha)3992 qla2x00_free_device(scsi_qla_host_t *vha)
3993 {
3994 struct qla_hw_data *ha = vha->hw;
3995
3996 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3997
3998 /* Disable timer */
3999 if (vha->timer_active)
4000 qla2x00_stop_timer(vha);
4001
4002 qla25xx_delete_queues(vha);
4003 vha->flags.online = 0;
4004
4005 /* turn-off interrupts on the card */
4006 if (ha->interrupts_on) {
4007 vha->flags.init_done = 0;
4008 ha->isp_ops->disable_intrs(ha);
4009 }
4010
4011 qla2x00_free_fcports(vha);
4012
4013 qla2x00_free_irqs(vha);
4014
4015 /* Flush the work queue and remove it */
4016 if (ha->wq) {
4017 destroy_workqueue(ha->wq);
4018 ha->wq = NULL;
4019 }
4020
4021
4022 qla24xx_free_purex_list(&vha->purex_list);
4023
4024 qla2x00_mem_free(ha);
4025
4026 qla82xx_md_free(vha);
4027
4028 qla_edif_sadb_release_free_pool(ha);
4029 qla_edif_sadb_release(ha);
4030
4031 qla2x00_free_queues(ha);
4032 }
4033
qla2x00_free_fcports(struct scsi_qla_host * vha)4034 void qla2x00_free_fcports(struct scsi_qla_host *vha)
4035 {
4036 fc_port_t *fcport, *tfcport;
4037
4038 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
4039 qla2x00_free_fcport(fcport);
4040 }
4041
4042 static inline void
qla2x00_schedule_rport_del(struct scsi_qla_host * vha,fc_port_t * fcport)4043 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport)
4044 {
4045 int now;
4046
4047 if (!fcport->rport)
4048 return;
4049
4050 if (fcport->rport) {
4051 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
4052 "%s %8phN. rport %p roles %x\n",
4053 __func__, fcport->port_name, fcport->rport,
4054 fcport->rport->roles);
4055 fc_remote_port_delete(fcport->rport);
4056 }
4057 qlt_do_generation_tick(vha, &now);
4058 }
4059
4060 /*
4061 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
4062 *
4063 * Input: ha = adapter block pointer. fcport = port structure pointer.
4064 *
4065 * Return: None.
4066 *
4067 * Context:
4068 */
qla2x00_mark_device_lost(scsi_qla_host_t * vha,fc_port_t * fcport,int do_login)4069 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
4070 int do_login)
4071 {
4072 if (IS_QLAFX00(vha->hw)) {
4073 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4074 qla2x00_schedule_rport_del(vha, fcport);
4075 return;
4076 }
4077
4078 if (atomic_read(&fcport->state) == FCS_ONLINE &&
4079 vha->vp_idx == fcport->vha->vp_idx) {
4080 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4081 qla2x00_schedule_rport_del(vha, fcport);
4082 }
4083
4084 /*
4085 * We may need to retry the login, so don't change the state of the
4086 * port but do the retries.
4087 */
4088 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
4089 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4090
4091 if (!do_login)
4092 return;
4093
4094 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4095 }
4096
4097 void
qla2x00_mark_all_devices_lost(scsi_qla_host_t * vha)4098 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha)
4099 {
4100 fc_port_t *fcport;
4101
4102 ql_dbg(ql_dbg_disc, vha, 0x20f1,
4103 "Mark all dev lost\n");
4104
4105 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4106 if (ql2xfc2target &&
4107 fcport->loop_id != FC_NO_LOOP_ID &&
4108 (fcport->flags & FCF_FCP2_DEVICE) &&
4109 fcport->port_type == FCT_TARGET &&
4110 !qla2x00_reset_active(vha)) {
4111 ql_dbg(ql_dbg_disc, vha, 0x211a,
4112 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC",
4113 fcport->flags, fcport->port_type,
4114 fcport->d_id.b24, fcport->port_name);
4115 continue;
4116 }
4117 fcport->scan_state = 0;
4118 qlt_schedule_sess_for_deletion(fcport);
4119 }
4120 }
4121
qla2x00_set_reserved_loop_ids(struct qla_hw_data * ha)4122 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
4123 {
4124 int i;
4125
4126 if (IS_FWI2_CAPABLE(ha))
4127 return;
4128
4129 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
4130 set_bit(i, ha->loop_id_map);
4131 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
4132 set_bit(BROADCAST, ha->loop_id_map);
4133 }
4134
4135 /*
4136 * qla2x00_mem_alloc
4137 * Allocates adapter memory.
4138 *
4139 * Returns:
4140 * 0 = success.
4141 * !0 = failure.
4142 */
4143 static int
qla2x00_mem_alloc(struct qla_hw_data * ha,uint16_t req_len,uint16_t rsp_len,struct req_que ** req,struct rsp_que ** rsp)4144 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
4145 struct req_que **req, struct rsp_que **rsp)
4146 {
4147 char name[16];
4148 int rc;
4149
4150 if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) {
4151 ha->vp_map = kcalloc(MAX_MULTI_ID_FABRIC, sizeof(struct qla_vp_map), GFP_KERNEL);
4152 if (!ha->vp_map)
4153 goto fail;
4154 }
4155
4156 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
4157 &ha->init_cb_dma, GFP_KERNEL);
4158 if (!ha->init_cb)
4159 goto fail_free_vp_map;
4160
4161 rc = btree_init32(&ha->host_map);
4162 if (rc)
4163 goto fail_free_init_cb;
4164
4165 if (qlt_mem_alloc(ha) < 0)
4166 goto fail_free_btree;
4167
4168 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4169 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
4170 if (!ha->gid_list)
4171 goto fail_free_tgt_mem;
4172
4173 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4174 if (!ha->srb_mempool)
4175 goto fail_free_gid_list;
4176
4177 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) {
4178 /* Allocate cache for CT6 Ctx. */
4179 if (!ctx_cachep) {
4180 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4181 sizeof(struct ct6_dsd), 0,
4182 SLAB_HWCACHE_ALIGN, NULL);
4183 if (!ctx_cachep)
4184 goto fail_free_srb_mempool;
4185 }
4186 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4187 ctx_cachep);
4188 if (!ha->ctx_mempool)
4189 goto fail_free_srb_mempool;
4190 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4191 "ctx_cachep=%p ctx_mempool=%p.\n",
4192 ctx_cachep, ha->ctx_mempool);
4193 }
4194
4195 /* Get memory for cached NVRAM */
4196 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4197 if (!ha->nvram)
4198 goto fail_free_ctx_mempool;
4199
4200 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4201 ha->pdev->device);
4202 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4203 DMA_POOL_SIZE, 8, 0);
4204 if (!ha->s_dma_pool)
4205 goto fail_free_nvram;
4206
4207 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4208 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4209 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4210
4211 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) {
4212 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4213 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4214 if (!ha->dl_dma_pool) {
4215 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4216 "Failed to allocate memory for dl_dma_pool.\n");
4217 goto fail_s_dma_pool;
4218 }
4219
4220 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4221 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4222 if (!ha->fcp_cmnd_dma_pool) {
4223 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4224 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
4225 goto fail_dl_dma_pool;
4226 }
4227
4228 if (ql2xenabledif) {
4229 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4230 struct dsd_dma *dsd, *nxt;
4231 uint i;
4232 /* Creata a DMA pool of buffers for DIF bundling */
4233 ha->dif_bundl_pool = dma_pool_create(name,
4234 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4235 if (!ha->dif_bundl_pool) {
4236 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4237 "%s: failed create dif_bundl_pool\n",
4238 __func__);
4239 goto fail_dif_bundl_dma_pool;
4240 }
4241
4242 INIT_LIST_HEAD(&ha->pool.good.head);
4243 INIT_LIST_HEAD(&ha->pool.unusable.head);
4244 ha->pool.good.count = 0;
4245 ha->pool.unusable.count = 0;
4246 for (i = 0; i < 128; i++) {
4247 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4248 if (!dsd) {
4249 ql_dbg_pci(ql_dbg_init, ha->pdev,
4250 0xe0ee, "%s: failed alloc dsd\n",
4251 __func__);
4252 return -ENOMEM;
4253 }
4254 ha->dif_bundle_kallocs++;
4255
4256 dsd->dsd_addr = dma_pool_alloc(
4257 ha->dif_bundl_pool, GFP_ATOMIC,
4258 &dsd->dsd_list_dma);
4259 if (!dsd->dsd_addr) {
4260 ql_dbg_pci(ql_dbg_init, ha->pdev,
4261 0xe0ee,
4262 "%s: failed alloc ->dsd_addr\n",
4263 __func__);
4264 kfree(dsd);
4265 ha->dif_bundle_kallocs--;
4266 continue;
4267 }
4268 ha->dif_bundle_dma_allocs++;
4269
4270 /*
4271 * if DMA buffer crosses 4G boundary,
4272 * put it on bad list
4273 */
4274 if (MSD(dsd->dsd_list_dma) ^
4275 MSD(dsd->dsd_list_dma + bufsize)) {
4276 list_add_tail(&dsd->list,
4277 &ha->pool.unusable.head);
4278 ha->pool.unusable.count++;
4279 } else {
4280 list_add_tail(&dsd->list,
4281 &ha->pool.good.head);
4282 ha->pool.good.count++;
4283 }
4284 }
4285
4286 /* return the good ones back to the pool */
4287 list_for_each_entry_safe(dsd, nxt,
4288 &ha->pool.good.head, list) {
4289 list_del(&dsd->list);
4290 dma_pool_free(ha->dif_bundl_pool,
4291 dsd->dsd_addr, dsd->dsd_list_dma);
4292 ha->dif_bundle_dma_allocs--;
4293 kfree(dsd);
4294 ha->dif_bundle_kallocs--;
4295 }
4296
4297 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4298 "%s: dif dma pool (good=%u unusable=%u)\n",
4299 __func__, ha->pool.good.count,
4300 ha->pool.unusable.count);
4301 }
4302
4303 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4304 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4305 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4306 ha->dif_bundl_pool);
4307 }
4308
4309 /* Allocate memory for SNS commands */
4310 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4311 /* Get consistent memory allocated for SNS commands */
4312 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4313 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4314 if (!ha->sns_cmd)
4315 goto fail_dma_pool;
4316 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4317 "sns_cmd: %p.\n", ha->sns_cmd);
4318 } else {
4319 /* Get consistent memory allocated for MS IOCB */
4320 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4321 &ha->ms_iocb_dma);
4322 if (!ha->ms_iocb)
4323 goto fail_dma_pool;
4324 /* Get consistent memory allocated for CT SNS commands */
4325 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4326 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4327 if (!ha->ct_sns)
4328 goto fail_free_ms_iocb;
4329 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4330 "ms_iocb=%p ct_sns=%p.\n",
4331 ha->ms_iocb, ha->ct_sns);
4332 }
4333
4334 /* Allocate memory for request ring */
4335 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4336 if (!*req) {
4337 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4338 "Failed to allocate memory for req.\n");
4339 goto fail_req;
4340 }
4341 (*req)->length = req_len;
4342 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4343 ((*req)->length + 1) * sizeof(request_t),
4344 &(*req)->dma, GFP_KERNEL);
4345 if (!(*req)->ring) {
4346 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4347 "Failed to allocate memory for req_ring.\n");
4348 goto fail_req_ring;
4349 }
4350 /* Allocate memory for response ring */
4351 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4352 if (!*rsp) {
4353 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4354 "Failed to allocate memory for rsp.\n");
4355 goto fail_rsp;
4356 }
4357 (*rsp)->hw = ha;
4358 (*rsp)->length = rsp_len;
4359 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4360 ((*rsp)->length + 1) * sizeof(response_t),
4361 &(*rsp)->dma, GFP_KERNEL);
4362 if (!(*rsp)->ring) {
4363 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4364 "Failed to allocate memory for rsp_ring.\n");
4365 goto fail_rsp_ring;
4366 }
4367 (*req)->rsp = *rsp;
4368 (*rsp)->req = *req;
4369 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4370 "req=%p req->length=%d req->ring=%p rsp=%p "
4371 "rsp->length=%d rsp->ring=%p.\n",
4372 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4373 (*rsp)->ring);
4374 /* Allocate memory for NVRAM data for vports */
4375 if (ha->nvram_npiv_size) {
4376 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4377 sizeof(struct qla_npiv_entry),
4378 GFP_KERNEL);
4379 if (!ha->npiv_info) {
4380 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4381 "Failed to allocate memory for npiv_info.\n");
4382 goto fail_npiv_info;
4383 }
4384 } else
4385 ha->npiv_info = NULL;
4386
4387 /* Get consistent memory allocated for EX-INIT-CB. */
4388 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4389 IS_QLA28XX(ha)) {
4390 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4391 &ha->ex_init_cb_dma);
4392 if (!ha->ex_init_cb)
4393 goto fail_ex_init_cb;
4394 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4395 "ex_init_cb=%p.\n", ha->ex_init_cb);
4396 }
4397
4398 /* Get consistent memory allocated for Special Features-CB. */
4399 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4400 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL,
4401 &ha->sf_init_cb_dma);
4402 if (!ha->sf_init_cb)
4403 goto fail_sf_init_cb;
4404 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
4405 "sf_init_cb=%p.\n", ha->sf_init_cb);
4406 }
4407
4408
4409 /* Get consistent memory allocated for Async Port-Database. */
4410 if (!IS_FWI2_CAPABLE(ha)) {
4411 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4412 &ha->async_pd_dma);
4413 if (!ha->async_pd)
4414 goto fail_async_pd;
4415 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4416 "async_pd=%p.\n", ha->async_pd);
4417 }
4418
4419 INIT_LIST_HEAD(&ha->vp_list);
4420
4421 /* Allocate memory for our loop_id bitmap */
4422 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4423 sizeof(long),
4424 GFP_KERNEL);
4425 if (!ha->loop_id_map)
4426 goto fail_loop_id_map;
4427 else {
4428 qla2x00_set_reserved_loop_ids(ha);
4429 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4430 "loop_id_map=%p.\n", ha->loop_id_map);
4431 }
4432
4433 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4434 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4435 if (!ha->sfp_data) {
4436 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4437 "Unable to allocate memory for SFP read-data.\n");
4438 goto fail_sfp_data;
4439 }
4440
4441 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4442 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4443 GFP_KERNEL);
4444 if (!ha->flt) {
4445 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4446 "Unable to allocate memory for FLT.\n");
4447 goto fail_flt_buffer;
4448 }
4449
4450 /* allocate the purex dma pool */
4451 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4452 ELS_MAX_PAYLOAD, 8, 0);
4453
4454 if (!ha->purex_dma_pool) {
4455 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4456 "Unable to allocate purex_dma_pool.\n");
4457 goto fail_flt;
4458 }
4459
4460 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16;
4461 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev,
4462 ha->elsrej.size,
4463 &ha->elsrej.cdma,
4464 GFP_KERNEL);
4465 if (!ha->elsrej.c) {
4466 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4467 "Alloc failed for els reject cmd.\n");
4468 goto fail_elsrej;
4469 }
4470 ha->elsrej.c->er_cmd = ELS_LS_RJT;
4471 ha->elsrej.c->er_reason = ELS_RJT_LOGIC;
4472 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA;
4473
4474 ha->lsrjt.size = sizeof(struct fcnvme_ls_rjt);
4475 ha->lsrjt.c = dma_alloc_coherent(&ha->pdev->dev, ha->lsrjt.size,
4476 &ha->lsrjt.cdma, GFP_KERNEL);
4477 if (!ha->lsrjt.c) {
4478 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4479 "Alloc failed for nvme fc reject cmd.\n");
4480 goto fail_lsrjt;
4481 }
4482
4483 return 0;
4484
4485 fail_lsrjt:
4486 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
4487 ha->elsrej.c, ha->elsrej.cdma);
4488 fail_elsrej:
4489 dma_pool_destroy(ha->purex_dma_pool);
4490 fail_flt:
4491 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4492 ha->flt, ha->flt_dma);
4493
4494 fail_flt_buffer:
4495 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4496 ha->sfp_data, ha->sfp_data_dma);
4497 fail_sfp_data:
4498 kfree(ha->loop_id_map);
4499 fail_loop_id_map:
4500 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4501 fail_async_pd:
4502 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma);
4503 fail_sf_init_cb:
4504 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4505 fail_ex_init_cb:
4506 kfree(ha->npiv_info);
4507 fail_npiv_info:
4508 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4509 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4510 (*rsp)->ring = NULL;
4511 (*rsp)->dma = 0;
4512 fail_rsp_ring:
4513 kfree(*rsp);
4514 *rsp = NULL;
4515 fail_rsp:
4516 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4517 sizeof(request_t), (*req)->ring, (*req)->dma);
4518 (*req)->ring = NULL;
4519 (*req)->dma = 0;
4520 fail_req_ring:
4521 kfree(*req);
4522 *req = NULL;
4523 fail_req:
4524 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4525 ha->ct_sns, ha->ct_sns_dma);
4526 ha->ct_sns = NULL;
4527 ha->ct_sns_dma = 0;
4528 fail_free_ms_iocb:
4529 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4530 ha->ms_iocb = NULL;
4531 ha->ms_iocb_dma = 0;
4532
4533 if (ha->sns_cmd)
4534 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4535 ha->sns_cmd, ha->sns_cmd_dma);
4536 fail_dma_pool:
4537 if (ql2xenabledif) {
4538 struct dsd_dma *dsd, *nxt;
4539
4540 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4541 list) {
4542 list_del(&dsd->list);
4543 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4544 dsd->dsd_list_dma);
4545 ha->dif_bundle_dma_allocs--;
4546 kfree(dsd);
4547 ha->dif_bundle_kallocs--;
4548 ha->pool.unusable.count--;
4549 }
4550 dma_pool_destroy(ha->dif_bundl_pool);
4551 ha->dif_bundl_pool = NULL;
4552 }
4553
4554 fail_dif_bundl_dma_pool:
4555 if (IS_QLA82XX(ha) || ql2xenabledif) {
4556 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4557 ha->fcp_cmnd_dma_pool = NULL;
4558 }
4559 fail_dl_dma_pool:
4560 if (IS_QLA82XX(ha) || ql2xenabledif) {
4561 dma_pool_destroy(ha->dl_dma_pool);
4562 ha->dl_dma_pool = NULL;
4563 }
4564 fail_s_dma_pool:
4565 dma_pool_destroy(ha->s_dma_pool);
4566 ha->s_dma_pool = NULL;
4567 fail_free_nvram:
4568 kfree(ha->nvram);
4569 ha->nvram = NULL;
4570 fail_free_ctx_mempool:
4571 mempool_destroy(ha->ctx_mempool);
4572 ha->ctx_mempool = NULL;
4573 fail_free_srb_mempool:
4574 mempool_destroy(ha->srb_mempool);
4575 ha->srb_mempool = NULL;
4576 fail_free_gid_list:
4577 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4578 ha->gid_list,
4579 ha->gid_list_dma);
4580 ha->gid_list = NULL;
4581 ha->gid_list_dma = 0;
4582 fail_free_tgt_mem:
4583 qlt_mem_free(ha);
4584 fail_free_btree:
4585 btree_destroy32(&ha->host_map);
4586 fail_free_init_cb:
4587 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4588 ha->init_cb_dma);
4589 ha->init_cb = NULL;
4590 ha->init_cb_dma = 0;
4591 fail_free_vp_map:
4592 kfree(ha->vp_map);
4593 ha->vp_map = NULL;
4594 fail:
4595 ql_log(ql_log_fatal, NULL, 0x0030,
4596 "Memory allocation failure.\n");
4597 return -ENOMEM;
4598 }
4599
4600 int
qla2x00_set_exlogins_buffer(scsi_qla_host_t * vha)4601 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4602 {
4603 int rval;
4604 uint16_t size, max_cnt;
4605 uint32_t temp;
4606 struct qla_hw_data *ha = vha->hw;
4607
4608 /* Return if we don't need to alloacate any extended logins */
4609 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400)
4610 return QLA_SUCCESS;
4611
4612 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4613 return QLA_SUCCESS;
4614
4615 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4616 max_cnt = 0;
4617 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4618 if (rval != QLA_SUCCESS) {
4619 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4620 "Failed to get exlogin status.\n");
4621 return rval;
4622 }
4623
4624 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4625 temp *= size;
4626
4627 if (temp != ha->exlogin_size) {
4628 qla2x00_free_exlogin_buffer(ha);
4629 ha->exlogin_size = temp;
4630
4631 ql_log(ql_log_info, vha, 0xd024,
4632 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4633 max_cnt, size, temp);
4634
4635 ql_log(ql_log_info, vha, 0xd025,
4636 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4637
4638 /* Get consistent memory for extended logins */
4639 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4640 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4641 if (!ha->exlogin_buf) {
4642 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4643 "Failed to allocate memory for exlogin_buf_dma.\n");
4644 return -ENOMEM;
4645 }
4646 }
4647
4648 /* Now configure the dma buffer */
4649 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4650 if (rval) {
4651 ql_log(ql_log_fatal, vha, 0xd033,
4652 "Setup extended login buffer ****FAILED****.\n");
4653 qla2x00_free_exlogin_buffer(ha);
4654 }
4655
4656 return rval;
4657 }
4658
4659 /*
4660 * qla2x00_free_exlogin_buffer
4661 *
4662 * Input:
4663 * ha = adapter block pointer
4664 */
4665 void
qla2x00_free_exlogin_buffer(struct qla_hw_data * ha)4666 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4667 {
4668 if (ha->exlogin_buf) {
4669 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4670 ha->exlogin_buf, ha->exlogin_buf_dma);
4671 ha->exlogin_buf = NULL;
4672 ha->exlogin_size = 0;
4673 }
4674 }
4675
4676 static void
qla2x00_number_of_exch(scsi_qla_host_t * vha,u32 * ret_cnt,u16 max_cnt)4677 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4678 {
4679 u32 temp;
4680 struct init_cb_81xx *icb = (struct init_cb_81xx *)vha->hw->init_cb;
4681 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4682
4683 if (max_cnt > vha->hw->max_exchg)
4684 max_cnt = vha->hw->max_exchg;
4685
4686 if (qla_ini_mode_enabled(vha)) {
4687 if (vha->ql2xiniexchg > max_cnt)
4688 vha->ql2xiniexchg = max_cnt;
4689
4690 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4691 *ret_cnt = vha->ql2xiniexchg;
4692
4693 } else if (qla_tgt_mode_enabled(vha)) {
4694 if (vha->ql2xexchoffld > max_cnt) {
4695 vha->ql2xexchoffld = max_cnt;
4696 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4697 }
4698
4699 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4700 *ret_cnt = vha->ql2xexchoffld;
4701 } else if (qla_dual_mode_enabled(vha)) {
4702 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4703 if (temp > max_cnt) {
4704 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4705 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4706 temp = max_cnt;
4707 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4708 }
4709
4710 if (temp > FW_DEF_EXCHANGES_CNT)
4711 *ret_cnt = temp;
4712 }
4713 }
4714
4715 int
qla2x00_set_exchoffld_buffer(scsi_qla_host_t * vha)4716 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4717 {
4718 int rval;
4719 u16 size, max_cnt;
4720 u32 actual_cnt, totsz;
4721 struct qla_hw_data *ha = vha->hw;
4722
4723 if (!ha->flags.exchoffld_enabled)
4724 return QLA_SUCCESS;
4725
4726 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4727 return QLA_SUCCESS;
4728
4729 max_cnt = 0;
4730 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4731 if (rval != QLA_SUCCESS) {
4732 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4733 "Failed to get exlogin status.\n");
4734 return rval;
4735 }
4736
4737 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4738 ql_log(ql_log_info, vha, 0xd014,
4739 "Actual exchange offload count: %d.\n", actual_cnt);
4740
4741 totsz = actual_cnt * size;
4742
4743 if (totsz != ha->exchoffld_size) {
4744 qla2x00_free_exchoffld_buffer(ha);
4745 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4746 ha->exchoffld_size = 0;
4747 ha->flags.exchoffld_enabled = 0;
4748 return QLA_SUCCESS;
4749 }
4750
4751 ha->exchoffld_size = totsz;
4752
4753 ql_log(ql_log_info, vha, 0xd016,
4754 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4755 max_cnt, actual_cnt, size, totsz);
4756
4757 ql_log(ql_log_info, vha, 0xd017,
4758 "Exchange Buffers requested size = 0x%x\n",
4759 ha->exchoffld_size);
4760
4761 /* Get consistent memory for extended logins */
4762 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4763 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4764 if (!ha->exchoffld_buf) {
4765 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4766 "Failed to allocate memory for Exchange Offload.\n");
4767
4768 if (ha->max_exchg >
4769 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4770 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4771 } else if (ha->max_exchg >
4772 (FW_DEF_EXCHANGES_CNT + 512)) {
4773 ha->max_exchg -= 512;
4774 } else {
4775 ha->flags.exchoffld_enabled = 0;
4776 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4777 "Disabling Exchange offload due to lack of memory\n");
4778 }
4779 ha->exchoffld_size = 0;
4780
4781 return -ENOMEM;
4782 }
4783 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4784 /* pathological case */
4785 qla2x00_free_exchoffld_buffer(ha);
4786 ha->exchoffld_size = 0;
4787 ha->flags.exchoffld_enabled = 0;
4788 ql_log(ql_log_info, vha, 0xd016,
4789 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4790 ha->exchoffld_size, actual_cnt, size, totsz);
4791 return 0;
4792 }
4793
4794 /* Now configure the dma buffer */
4795 rval = qla_set_exchoffld_mem_cfg(vha);
4796 if (rval) {
4797 ql_log(ql_log_fatal, vha, 0xd02e,
4798 "Setup exchange offload buffer ****FAILED****.\n");
4799 qla2x00_free_exchoffld_buffer(ha);
4800 } else {
4801 /* re-adjust number of target exchange */
4802 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4803
4804 if (qla_ini_mode_enabled(vha))
4805 icb->exchange_count = 0;
4806 else
4807 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4808 }
4809
4810 return rval;
4811 }
4812
4813 /*
4814 * qla2x00_free_exchoffld_buffer
4815 *
4816 * Input:
4817 * ha = adapter block pointer
4818 */
4819 void
qla2x00_free_exchoffld_buffer(struct qla_hw_data * ha)4820 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4821 {
4822 if (ha->exchoffld_buf) {
4823 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4824 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4825 ha->exchoffld_buf = NULL;
4826 ha->exchoffld_size = 0;
4827 }
4828 }
4829
4830 /*
4831 * qla2x00_free_fw_dump
4832 * Frees fw dump stuff.
4833 *
4834 * Input:
4835 * ha = adapter block pointer
4836 */
4837 static void
qla2x00_free_fw_dump(struct qla_hw_data * ha)4838 qla2x00_free_fw_dump(struct qla_hw_data *ha)
4839 {
4840 struct fwdt *fwdt = ha->fwdt;
4841 uint j;
4842
4843 if (ha->fce)
4844 dma_free_coherent(&ha->pdev->dev,
4845 FCE_SIZE, ha->fce, ha->fce_dma);
4846
4847 if (ha->eft)
4848 dma_free_coherent(&ha->pdev->dev,
4849 EFT_SIZE, ha->eft, ha->eft_dma);
4850
4851 vfree(ha->fw_dump);
4852
4853 ha->fce = NULL;
4854 ha->fce_dma = 0;
4855 ha->flags.fce_enabled = 0;
4856 ha->eft = NULL;
4857 ha->eft_dma = 0;
4858 ha->fw_dumped = false;
4859 ha->fw_dump_cap_flags = 0;
4860 ha->fw_dump_reading = 0;
4861 ha->fw_dump = NULL;
4862 ha->fw_dump_len = 0;
4863
4864 for (j = 0; j < 2; j++, fwdt++) {
4865 vfree(fwdt->template);
4866 fwdt->template = NULL;
4867 fwdt->length = 0;
4868 }
4869 }
4870
4871 /*
4872 * qla2x00_mem_free
4873 * Frees all adapter allocated memory.
4874 *
4875 * Input:
4876 * ha = adapter block pointer.
4877 */
4878 static void
qla2x00_mem_free(struct qla_hw_data * ha)4879 qla2x00_mem_free(struct qla_hw_data *ha)
4880 {
4881 qla2x00_free_fw_dump(ha);
4882
4883 if (ha->mctp_dump)
4884 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4885 ha->mctp_dump_dma);
4886 ha->mctp_dump = NULL;
4887
4888 mempool_destroy(ha->srb_mempool);
4889 ha->srb_mempool = NULL;
4890
4891 if (ha->dcbx_tlv)
4892 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4893 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4894 ha->dcbx_tlv = NULL;
4895
4896 if (ha->xgmac_data)
4897 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4898 ha->xgmac_data, ha->xgmac_data_dma);
4899 ha->xgmac_data = NULL;
4900
4901 if (ha->sns_cmd)
4902 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4903 ha->sns_cmd, ha->sns_cmd_dma);
4904 ha->sns_cmd = NULL;
4905 ha->sns_cmd_dma = 0;
4906
4907 if (ha->ct_sns)
4908 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4909 ha->ct_sns, ha->ct_sns_dma);
4910 ha->ct_sns = NULL;
4911 ha->ct_sns_dma = 0;
4912
4913 if (ha->sfp_data)
4914 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4915 ha->sfp_data_dma);
4916 ha->sfp_data = NULL;
4917
4918 if (ha->flt)
4919 dma_free_coherent(&ha->pdev->dev,
4920 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4921 ha->flt, ha->flt_dma);
4922 ha->flt = NULL;
4923 ha->flt_dma = 0;
4924
4925 if (ha->ms_iocb)
4926 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4927 ha->ms_iocb = NULL;
4928 ha->ms_iocb_dma = 0;
4929
4930 if (ha->sf_init_cb)
4931 dma_pool_free(ha->s_dma_pool,
4932 ha->sf_init_cb, ha->sf_init_cb_dma);
4933
4934 if (ha->ex_init_cb)
4935 dma_pool_free(ha->s_dma_pool,
4936 ha->ex_init_cb, ha->ex_init_cb_dma);
4937 ha->ex_init_cb = NULL;
4938 ha->ex_init_cb_dma = 0;
4939
4940 if (ha->async_pd)
4941 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4942 ha->async_pd = NULL;
4943 ha->async_pd_dma = 0;
4944
4945 dma_pool_destroy(ha->s_dma_pool);
4946 ha->s_dma_pool = NULL;
4947
4948 if (ha->gid_list)
4949 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4950 ha->gid_list, ha->gid_list_dma);
4951 ha->gid_list = NULL;
4952 ha->gid_list_dma = 0;
4953
4954 if (ha->base_qpair && !list_empty(&ha->base_qpair->dsd_list)) {
4955 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4956
4957 /* clean up allocated prev pool */
4958 list_for_each_entry_safe(dsd_ptr, tdsd_ptr,
4959 &ha->base_qpair->dsd_list, list) {
4960 dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr,
4961 dsd_ptr->dsd_list_dma);
4962 list_del(&dsd_ptr->list);
4963 kfree(dsd_ptr);
4964 }
4965 }
4966
4967 dma_pool_destroy(ha->dl_dma_pool);
4968 ha->dl_dma_pool = NULL;
4969
4970 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4971 ha->fcp_cmnd_dma_pool = NULL;
4972
4973 mempool_destroy(ha->ctx_mempool);
4974 ha->ctx_mempool = NULL;
4975
4976 if (ql2xenabledif && ha->dif_bundl_pool) {
4977 struct dsd_dma *dsd, *nxt;
4978
4979 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4980 list) {
4981 list_del(&dsd->list);
4982 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4983 dsd->dsd_list_dma);
4984 ha->dif_bundle_dma_allocs--;
4985 kfree(dsd);
4986 ha->dif_bundle_kallocs--;
4987 ha->pool.unusable.count--;
4988 }
4989 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4990 list_del(&dsd->list);
4991 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4992 dsd->dsd_list_dma);
4993 ha->dif_bundle_dma_allocs--;
4994 kfree(dsd);
4995 ha->dif_bundle_kallocs--;
4996 }
4997 }
4998
4999 dma_pool_destroy(ha->dif_bundl_pool);
5000 ha->dif_bundl_pool = NULL;
5001
5002 qlt_mem_free(ha);
5003 qla_remove_hostmap(ha);
5004
5005 if (ha->init_cb)
5006 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
5007 ha->init_cb, ha->init_cb_dma);
5008
5009 dma_pool_destroy(ha->purex_dma_pool);
5010 ha->purex_dma_pool = NULL;
5011
5012 if (ha->elsrej.c) {
5013 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
5014 ha->elsrej.c, ha->elsrej.cdma);
5015 ha->elsrej.c = NULL;
5016 }
5017
5018 if (ha->lsrjt.c) {
5019 dma_free_coherent(&ha->pdev->dev, ha->lsrjt.size, ha->lsrjt.c,
5020 ha->lsrjt.cdma);
5021 ha->lsrjt.c = NULL;
5022 }
5023
5024 ha->init_cb = NULL;
5025 ha->init_cb_dma = 0;
5026
5027 vfree(ha->optrom_buffer);
5028 ha->optrom_buffer = NULL;
5029 kfree(ha->nvram);
5030 ha->nvram = NULL;
5031 kfree(ha->npiv_info);
5032 ha->npiv_info = NULL;
5033 kfree(ha->swl);
5034 ha->swl = NULL;
5035 kfree(ha->loop_id_map);
5036 ha->sf_init_cb = NULL;
5037 ha->sf_init_cb_dma = 0;
5038 ha->loop_id_map = NULL;
5039
5040 kfree(ha->vp_map);
5041 ha->vp_map = NULL;
5042 }
5043
qla2x00_create_host(const struct scsi_host_template * sht,struct qla_hw_data * ha)5044 struct scsi_qla_host *qla2x00_create_host(const struct scsi_host_template *sht,
5045 struct qla_hw_data *ha)
5046 {
5047 struct Scsi_Host *host;
5048 struct scsi_qla_host *vha = NULL;
5049
5050 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
5051 if (!host) {
5052 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
5053 "Failed to allocate host from the scsi layer, aborting.\n");
5054 return NULL;
5055 }
5056
5057 /* Clear our data area */
5058 vha = shost_priv(host);
5059 memset(vha, 0, sizeof(scsi_qla_host_t));
5060
5061 vha->host = host;
5062 vha->host_no = host->host_no;
5063 vha->hw = ha;
5064
5065 vha->qlini_mode = ql2x_ini_mode;
5066 vha->ql2xexchoffld = ql2xexchoffld;
5067 vha->ql2xiniexchg = ql2xiniexchg;
5068
5069 INIT_LIST_HEAD(&vha->vp_fcports);
5070 INIT_LIST_HEAD(&vha->work_list);
5071 INIT_LIST_HEAD(&vha->list);
5072 INIT_LIST_HEAD(&vha->qla_cmd_list);
5073 INIT_LIST_HEAD(&vha->logo_list);
5074 INIT_LIST_HEAD(&vha->plogi_ack_list);
5075 INIT_LIST_HEAD(&vha->qp_list);
5076 INIT_LIST_HEAD(&vha->gnl.fcports);
5077 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
5078
5079 INIT_LIST_HEAD(&vha->purex_list.head);
5080 spin_lock_init(&vha->purex_list.lock);
5081
5082 spin_lock_init(&vha->work_lock);
5083 spin_lock_init(&vha->cmd_list_lock);
5084 init_waitqueue_head(&vha->fcport_waitQ);
5085 init_waitqueue_head(&vha->vref_waitq);
5086 qla_enode_init(vha);
5087 qla_edb_init(vha);
5088
5089
5090 vha->gnl.size = sizeof(struct get_name_list_extended) *
5091 (ha->max_loop_id + 1);
5092 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
5093 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
5094 if (!vha->gnl.l) {
5095 ql_log(ql_log_fatal, vha, 0xd04a,
5096 "Alloc failed for name list.\n");
5097 scsi_host_put(vha->host);
5098 return NULL;
5099 }
5100
5101 /* todo: what about ext login? */
5102 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
5103 vha->scan.l = vmalloc(vha->scan.size);
5104 if (!vha->scan.l) {
5105 ql_log(ql_log_fatal, vha, 0xd04a,
5106 "Alloc failed for scan database.\n");
5107 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
5108 vha->gnl.l, vha->gnl.ldma);
5109 vha->gnl.l = NULL;
5110 scsi_host_put(vha->host);
5111 return NULL;
5112 }
5113 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
5114
5115 snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu",
5116 QLA2XXX_DRIVER_NAME, vha->host_no);
5117 ql_dbg(ql_dbg_init, vha, 0x0041,
5118 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
5119 vha->host, vha->hw, vha,
5120 dev_name(&(ha->pdev->dev)));
5121
5122 return vha;
5123 }
5124
5125 struct qla_work_evt *
qla2x00_alloc_work(struct scsi_qla_host * vha,enum qla_work_type type)5126 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
5127 {
5128 struct qla_work_evt *e;
5129
5130 if (test_bit(UNLOADING, &vha->dpc_flags))
5131 return NULL;
5132
5133 if (qla_vha_mark_busy(vha))
5134 return NULL;
5135
5136 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
5137 if (!e) {
5138 QLA_VHA_MARK_NOT_BUSY(vha);
5139 return NULL;
5140 }
5141
5142 INIT_LIST_HEAD(&e->list);
5143 e->type = type;
5144 e->flags = QLA_EVT_FLAG_FREE;
5145 return e;
5146 }
5147
5148 int
qla2x00_post_work(struct scsi_qla_host * vha,struct qla_work_evt * e)5149 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
5150 {
5151 unsigned long flags;
5152 bool q = false;
5153
5154 spin_lock_irqsave(&vha->work_lock, flags);
5155 list_add_tail(&e->list, &vha->work_list);
5156
5157 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
5158 q = true;
5159
5160 spin_unlock_irqrestore(&vha->work_lock, flags);
5161
5162 if (q)
5163 queue_work(vha->hw->wq, &vha->iocb_work);
5164
5165 return QLA_SUCCESS;
5166 }
5167
5168 int
qla2x00_post_aen_work(struct scsi_qla_host * vha,enum fc_host_event_code code,u32 data)5169 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
5170 u32 data)
5171 {
5172 struct qla_work_evt *e;
5173
5174 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
5175 if (!e)
5176 return QLA_FUNCTION_FAILED;
5177
5178 e->u.aen.code = code;
5179 e->u.aen.data = data;
5180 return qla2x00_post_work(vha, e);
5181 }
5182
5183 int
qla2x00_post_idc_ack_work(struct scsi_qla_host * vha,uint16_t * mb)5184 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
5185 {
5186 struct qla_work_evt *e;
5187
5188 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
5189 if (!e)
5190 return QLA_FUNCTION_FAILED;
5191
5192 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
5193 return qla2x00_post_work(vha, e);
5194 }
5195
5196 #define qla2x00_post_async_work(name, type) \
5197 int qla2x00_post_async_##name##_work( \
5198 struct scsi_qla_host *vha, \
5199 fc_port_t *fcport, uint16_t *data) \
5200 { \
5201 struct qla_work_evt *e; \
5202 \
5203 e = qla2x00_alloc_work(vha, type); \
5204 if (!e) \
5205 return QLA_FUNCTION_FAILED; \
5206 \
5207 e->u.logio.fcport = fcport; \
5208 if (data) { \
5209 e->u.logio.data[0] = data[0]; \
5210 e->u.logio.data[1] = data[1]; \
5211 } \
5212 fcport->flags |= FCF_ASYNC_ACTIVE; \
5213 return qla2x00_post_work(vha, e); \
5214 }
5215
5216 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
5217 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
5218 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
5219 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
5220 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
5221
5222 int
qla2x00_post_uevent_work(struct scsi_qla_host * vha,u32 code)5223 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
5224 {
5225 struct qla_work_evt *e;
5226
5227 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
5228 if (!e)
5229 return QLA_FUNCTION_FAILED;
5230
5231 e->u.uevent.code = code;
5232 return qla2x00_post_work(vha, e);
5233 }
5234
5235 static void
qla2x00_uevent_emit(struct scsi_qla_host * vha,u32 code)5236 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
5237 {
5238 char event_string[40];
5239 char *envp[] = { event_string, NULL };
5240
5241 switch (code) {
5242 case QLA_UEVENT_CODE_FW_DUMP:
5243 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
5244 vha->host_no);
5245 break;
5246 default:
5247 /* do nothing */
5248 break;
5249 }
5250 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5251 }
5252
5253 int
qlafx00_post_aenfx_work(struct scsi_qla_host * vha,uint32_t evtcode,uint32_t * data,int cnt)5254 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5255 uint32_t *data, int cnt)
5256 {
5257 struct qla_work_evt *e;
5258
5259 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5260 if (!e)
5261 return QLA_FUNCTION_FAILED;
5262
5263 e->u.aenfx.evtcode = evtcode;
5264 e->u.aenfx.count = cnt;
5265 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5266 return qla2x00_post_work(vha, e);
5267 }
5268
qla24xx_sched_upd_fcport(fc_port_t * fcport)5269 void qla24xx_sched_upd_fcport(fc_port_t *fcport)
5270 {
5271 unsigned long flags;
5272
5273 if (IS_SW_RESV_ADDR(fcport->d_id))
5274 return;
5275
5276 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5277 if (fcport->disc_state == DSC_UPD_FCPORT) {
5278 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5279 return;
5280 }
5281 fcport->jiffies_at_registration = jiffies;
5282 fcport->sec_since_registration = 0;
5283 fcport->next_disc_state = DSC_DELETED;
5284 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
5285 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5286
5287 queue_work(system_dfl_wq, &fcport->reg_work);
5288 }
5289
5290 static
qla24xx_create_new_sess(struct scsi_qla_host * vha,struct qla_work_evt * e)5291 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5292 {
5293 unsigned long flags;
5294 fc_port_t *fcport = NULL, *tfcp;
5295 struct qlt_plogi_ack_t *pla =
5296 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
5297 uint8_t free_fcport = 0;
5298
5299 ql_dbg(ql_dbg_disc, vha, 0xffff,
5300 "%s %d %8phC enter\n",
5301 __func__, __LINE__, e->u.new_sess.port_name);
5302
5303 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5304 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5305 if (fcport) {
5306 fcport->d_id = e->u.new_sess.id;
5307 if (pla) {
5308 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5309 memcpy(fcport->node_name,
5310 pla->iocb.u.isp24.u.plogi.node_name,
5311 WWN_SIZE);
5312 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5313 /* we took an extra ref_count to prevent PLOGI ACK when
5314 * fcport/sess has not been created.
5315 */
5316 pla->ref_count--;
5317 }
5318 } else {
5319 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5320 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5321 if (fcport) {
5322 fcport->d_id = e->u.new_sess.id;
5323 fcport->flags |= FCF_FABRIC_DEVICE;
5324 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5325 fcport->tgt_short_link_down_cnt = 0;
5326
5327 memcpy(fcport->port_name, e->u.new_sess.port_name,
5328 WWN_SIZE);
5329
5330 fcport->fc4_type = e->u.new_sess.fc4_type;
5331 if (NVME_PRIORITY(vha->hw, fcport))
5332 fcport->do_prli_nvme = 1;
5333 else
5334 fcport->do_prli_nvme = 0;
5335
5336 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
5337 fcport->dm_login_expire = jiffies +
5338 QLA_N2N_WAIT_TIME * HZ;
5339 fcport->fc4_type = FS_FC4TYPE_FCP;
5340 fcport->n2n_flag = 1;
5341 if (vha->flags.nvme_enabled)
5342 fcport->fc4_type |= FS_FC4TYPE_NVME;
5343 }
5344
5345 } else {
5346 ql_dbg(ql_dbg_disc, vha, 0xffff,
5347 "%s %8phC mem alloc fail.\n",
5348 __func__, e->u.new_sess.port_name);
5349
5350 if (pla) {
5351 list_del(&pla->list);
5352 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5353 }
5354 return;
5355 }
5356
5357 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5358 /* search again to make sure no one else got ahead */
5359 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5360 e->u.new_sess.port_name, 1);
5361 if (tfcp) {
5362 /* should rarily happen */
5363 ql_dbg(ql_dbg_disc, vha, 0xffff,
5364 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5365 __func__, tfcp->port_name, tfcp->disc_state,
5366 tfcp->fw_login_state);
5367
5368 free_fcport = 1;
5369 } else {
5370 list_add_tail(&fcport->list, &vha->vp_fcports);
5371
5372 }
5373 if (pla) {
5374 qlt_plogi_ack_link(vha, pla, fcport,
5375 QLT_PLOGI_LINK_SAME_WWN);
5376 pla->ref_count--;
5377 }
5378 }
5379 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5380
5381 if (fcport) {
5382 fcport->id_changed = 1;
5383 fcport->scan_state = QLA_FCPORT_FOUND;
5384 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5385 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5386
5387 if (pla) {
5388 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5389 u16 wd3_lo;
5390
5391 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5392 fcport->local = 0;
5393 fcport->loop_id =
5394 le16_to_cpu(
5395 pla->iocb.u.isp24.nport_handle);
5396 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5397 wd3_lo =
5398 le16_to_cpu(
5399 pla->iocb.u.isp24.u.prli.wd3_lo);
5400
5401 if (wd3_lo & BIT_7)
5402 fcport->conf_compl_supported = 1;
5403
5404 if ((wd3_lo & BIT_4) == 0)
5405 fcport->port_type = FCT_INITIATOR;
5406 else
5407 fcport->port_type = FCT_TARGET;
5408 }
5409 qlt_plogi_ack_unref(vha, pla);
5410 } else {
5411 fc_port_t *dfcp = NULL;
5412
5413 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5414 tfcp = qla2x00_find_fcport_by_nportid(vha,
5415 &e->u.new_sess.id, 1);
5416 if (tfcp && (tfcp != fcport)) {
5417 /*
5418 * We have a conflict fcport with same NportID.
5419 */
5420 ql_dbg(ql_dbg_disc, vha, 0xffff,
5421 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5422 __func__, tfcp->port_name, tfcp->disc_state,
5423 tfcp->fw_login_state);
5424
5425 switch (tfcp->disc_state) {
5426 case DSC_DELETED:
5427 break;
5428 case DSC_DELETE_PEND:
5429 fcport->login_pause = 1;
5430 tfcp->conflict = fcport;
5431 break;
5432 default:
5433 fcport->login_pause = 1;
5434 tfcp->conflict = fcport;
5435 dfcp = tfcp;
5436 break;
5437 }
5438 }
5439 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5440 if (dfcp)
5441 qlt_schedule_sess_for_deletion(tfcp);
5442
5443 if (N2N_TOPO(vha->hw)) {
5444 fcport->flags &= ~FCF_FABRIC_DEVICE;
5445 fcport->keep_nport_handle = 1;
5446 if (vha->flags.nvme_enabled) {
5447 fcport->fc4_type =
5448 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP);
5449 fcport->n2n_flag = 1;
5450 }
5451 fcport->fw_login_state = 0;
5452
5453 schedule_delayed_work(&vha->scan.scan_work, 5);
5454 } else {
5455 qla24xx_fcport_handle_login(vha, fcport);
5456 }
5457 }
5458 }
5459
5460 if (free_fcport) {
5461 qla2x00_free_fcport(fcport);
5462 if (pla) {
5463 list_del(&pla->list);
5464 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5465 }
5466 }
5467 }
5468
qla_sp_retry(struct scsi_qla_host * vha,struct qla_work_evt * e)5469 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5470 {
5471 struct srb *sp = e->u.iosb.sp;
5472 int rval;
5473
5474 rval = qla2x00_start_sp(sp);
5475 if (rval != QLA_SUCCESS) {
5476 ql_dbg(ql_dbg_disc, vha, 0x2043,
5477 "%s: %s: Re-issue IOCB failed (%d).\n",
5478 __func__, sp->name, rval);
5479 qla24xx_sp_unmap(vha, sp);
5480 }
5481 }
5482
5483 void
qla2x00_do_work(struct scsi_qla_host * vha)5484 qla2x00_do_work(struct scsi_qla_host *vha)
5485 {
5486 struct qla_work_evt *e, *tmp;
5487 unsigned long flags;
5488 LIST_HEAD(work);
5489 int rc;
5490
5491 spin_lock_irqsave(&vha->work_lock, flags);
5492 list_splice_init(&vha->work_list, &work);
5493 spin_unlock_irqrestore(&vha->work_lock, flags);
5494
5495 list_for_each_entry_safe(e, tmp, &work, list) {
5496 rc = QLA_SUCCESS;
5497 switch (e->type) {
5498 case QLA_EVT_AEN:
5499 fc_host_post_event(vha->host, fc_get_event_number(),
5500 e->u.aen.code, e->u.aen.data);
5501 break;
5502 case QLA_EVT_IDC_ACK:
5503 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5504 break;
5505 case QLA_EVT_ASYNC_LOGIN:
5506 qla2x00_async_login(vha, e->u.logio.fcport,
5507 e->u.logio.data);
5508 break;
5509 case QLA_EVT_ASYNC_LOGOUT:
5510 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
5511 break;
5512 case QLA_EVT_ASYNC_ADISC:
5513 qla2x00_async_adisc(vha, e->u.logio.fcport,
5514 e->u.logio.data);
5515 break;
5516 case QLA_EVT_UEVENT:
5517 qla2x00_uevent_emit(vha, e->u.uevent.code);
5518 break;
5519 case QLA_EVT_AENFX:
5520 qlafx00_process_aen(vha, e);
5521 break;
5522 case QLA_EVT_UNMAP:
5523 qla24xx_sp_unmap(vha, e->u.iosb.sp);
5524 break;
5525 case QLA_EVT_RELOGIN:
5526 qla2x00_relogin(vha);
5527 break;
5528 case QLA_EVT_NEW_SESS:
5529 qla24xx_create_new_sess(vha, e);
5530 break;
5531 case QLA_EVT_GPDB:
5532 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5533 e->u.fcport.opt);
5534 break;
5535 case QLA_EVT_PRLI:
5536 qla24xx_async_prli(vha, e->u.fcport.fcport);
5537 break;
5538 case QLA_EVT_GPSC:
5539 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5540 break;
5541 case QLA_EVT_GNL:
5542 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5543 break;
5544 case QLA_EVT_NACK:
5545 qla24xx_do_nack_work(vha, e);
5546 break;
5547 case QLA_EVT_ASYNC_PRLO:
5548 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
5549 break;
5550 case QLA_EVT_ASYNC_PRLO_DONE:
5551 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5552 e->u.logio.data);
5553 break;
5554 case QLA_EVT_SCAN_CMD:
5555 qla_fab_async_scan(vha, e->u.iosb.sp);
5556 break;
5557 case QLA_EVT_SCAN_FINISH:
5558 qla_fab_scan_finish(vha, e->u.iosb.sp);
5559 break;
5560 case QLA_EVT_GFPNID:
5561 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5562 break;
5563 case QLA_EVT_SP_RETRY:
5564 qla_sp_retry(vha, e);
5565 break;
5566 case QLA_EVT_IIDMA:
5567 qla_do_iidma_work(vha, e->u.fcport.fcport);
5568 break;
5569 case QLA_EVT_ELS_PLOGI:
5570 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5571 e->u.fcport.fcport);
5572 break;
5573 case QLA_EVT_SA_REPLACE:
5574 rc = qla24xx_issue_sa_replace_iocb(vha, e);
5575 break;
5576 }
5577
5578 if (rc == EAGAIN) {
5579 /* put 'work' at head of 'vha->work_list' */
5580 spin_lock_irqsave(&vha->work_lock, flags);
5581 list_splice(&work, &vha->work_list);
5582 spin_unlock_irqrestore(&vha->work_lock, flags);
5583 break;
5584 }
5585 list_del_init(&e->list);
5586 if (e->flags & QLA_EVT_FLAG_FREE)
5587 kfree(e);
5588
5589 /* For each work completed decrement vha ref count */
5590 QLA_VHA_MARK_NOT_BUSY(vha);
5591 }
5592 }
5593
qla24xx_post_relogin_work(struct scsi_qla_host * vha)5594 int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5595 {
5596 struct qla_work_evt *e;
5597
5598 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5599
5600 if (!e) {
5601 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5602 return QLA_FUNCTION_FAILED;
5603 }
5604
5605 return qla2x00_post_work(vha, e);
5606 }
5607
5608 /* Relogins all the fcports of a vport
5609 * Context: dpc thread
5610 */
qla2x00_relogin(struct scsi_qla_host * vha)5611 void qla2x00_relogin(struct scsi_qla_host *vha)
5612 {
5613 fc_port_t *fcport;
5614 int status, relogin_needed = 0;
5615 struct event_arg ea;
5616
5617 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5618 /*
5619 * If the port is not ONLINE then try to login
5620 * to it if we haven't run out of retries.
5621 */
5622 if (atomic_read(&fcport->state) != FCS_ONLINE &&
5623 fcport->login_retry) {
5624 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5625 fcport->disc_state == DSC_LOGIN_AUTH_PEND ||
5626 fcport->disc_state == DSC_LOGIN_COMPLETE)
5627 continue;
5628
5629 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5630 fcport->disc_state == DSC_DELETE_PEND) {
5631 relogin_needed = 1;
5632 } else {
5633 if (vha->hw->current_topology != ISP_CFG_NL) {
5634 memset(&ea, 0, sizeof(ea));
5635 ea.fcport = fcport;
5636 qla24xx_handle_relogin_event(vha, &ea);
5637 } else if (vha->hw->current_topology ==
5638 ISP_CFG_NL &&
5639 IS_QLA2XXX_MIDTYPE(vha->hw)) {
5640 (void)qla24xx_fcport_handle_login(vha,
5641 fcport);
5642 } else if (vha->hw->current_topology ==
5643 ISP_CFG_NL) {
5644 fcport->login_retry--;
5645 status =
5646 qla2x00_local_device_login(vha,
5647 fcport);
5648 if (status == QLA_SUCCESS) {
5649 fcport->old_loop_id =
5650 fcport->loop_id;
5651 ql_dbg(ql_dbg_disc, vha, 0x2003,
5652 "Port login OK: logged in ID 0x%x.\n",
5653 fcport->loop_id);
5654 qla2x00_update_fcport
5655 (vha, fcport);
5656 } else if (status == 1) {
5657 set_bit(RELOGIN_NEEDED,
5658 &vha->dpc_flags);
5659 /* retry the login again */
5660 ql_dbg(ql_dbg_disc, vha, 0x2007,
5661 "Retrying %d login again loop_id 0x%x.\n",
5662 fcport->login_retry,
5663 fcport->loop_id);
5664 } else {
5665 fcport->login_retry = 0;
5666 }
5667
5668 if (fcport->login_retry == 0 &&
5669 status != QLA_SUCCESS)
5670 qla2x00_clear_loop_id(fcport);
5671 }
5672 }
5673 }
5674 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5675 break;
5676 }
5677
5678 if (relogin_needed)
5679 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5680
5681 ql_dbg(ql_dbg_disc, vha, 0x400e,
5682 "Relogin end.\n");
5683 }
5684
5685 /* Schedule work on any of the dpc-workqueues */
5686 void
qla83xx_schedule_work(scsi_qla_host_t * base_vha,int work_code)5687 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5688 {
5689 struct qla_hw_data *ha = base_vha->hw;
5690
5691 switch (work_code) {
5692 case MBA_IDC_AEN: /* 0x8200 */
5693 if (ha->dpc_lp_wq)
5694 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5695 break;
5696
5697 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5698 if (!ha->flags.nic_core_reset_hdlr_active) {
5699 if (ha->dpc_hp_wq)
5700 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5701 } else
5702 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5703 "NIC Core reset is already active. Skip "
5704 "scheduling it again.\n");
5705 break;
5706 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5707 if (ha->dpc_hp_wq)
5708 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5709 break;
5710 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5711 if (ha->dpc_hp_wq)
5712 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5713 break;
5714 default:
5715 ql_log(ql_log_warn, base_vha, 0xb05f,
5716 "Unknown work-code=0x%x.\n", work_code);
5717 }
5718
5719 return;
5720 }
5721
5722 /* Work: Perform NIC Core Unrecoverable state handling */
5723 void
qla83xx_nic_core_unrecoverable_work(struct work_struct * work)5724 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5725 {
5726 struct qla_hw_data *ha =
5727 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
5728 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5729 uint32_t dev_state = 0;
5730
5731 qla83xx_idc_lock(base_vha, 0);
5732 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5733 qla83xx_reset_ownership(base_vha);
5734 if (ha->flags.nic_core_reset_owner) {
5735 ha->flags.nic_core_reset_owner = 0;
5736 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5737 QLA8XXX_DEV_FAILED);
5738 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5739 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5740 }
5741 qla83xx_idc_unlock(base_vha, 0);
5742 }
5743
5744 /* Work: Execute IDC state handler */
5745 void
qla83xx_idc_state_handler_work(struct work_struct * work)5746 qla83xx_idc_state_handler_work(struct work_struct *work)
5747 {
5748 struct qla_hw_data *ha =
5749 container_of(work, struct qla_hw_data, idc_state_handler);
5750 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5751 uint32_t dev_state = 0;
5752
5753 qla83xx_idc_lock(base_vha, 0);
5754 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5755 if (dev_state == QLA8XXX_DEV_FAILED ||
5756 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5757 qla83xx_idc_state_handler(base_vha);
5758 qla83xx_idc_unlock(base_vha, 0);
5759 }
5760
5761 static int
qla83xx_check_nic_core_fw_alive(scsi_qla_host_t * base_vha)5762 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5763 {
5764 int rval = QLA_SUCCESS;
5765 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5766 uint32_t heart_beat_counter1, heart_beat_counter2;
5767
5768 do {
5769 if (time_after(jiffies, heart_beat_wait)) {
5770 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5771 "Nic Core f/w is not alive.\n");
5772 rval = QLA_FUNCTION_FAILED;
5773 break;
5774 }
5775
5776 qla83xx_idc_lock(base_vha, 0);
5777 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5778 &heart_beat_counter1);
5779 qla83xx_idc_unlock(base_vha, 0);
5780 msleep(100);
5781 qla83xx_idc_lock(base_vha, 0);
5782 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5783 &heart_beat_counter2);
5784 qla83xx_idc_unlock(base_vha, 0);
5785 } while (heart_beat_counter1 == heart_beat_counter2);
5786
5787 return rval;
5788 }
5789
5790 /* Work: Perform NIC Core Reset handling */
5791 void
qla83xx_nic_core_reset_work(struct work_struct * work)5792 qla83xx_nic_core_reset_work(struct work_struct *work)
5793 {
5794 struct qla_hw_data *ha =
5795 container_of(work, struct qla_hw_data, nic_core_reset);
5796 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5797 uint32_t dev_state = 0;
5798
5799 if (IS_QLA2031(ha)) {
5800 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5801 ql_log(ql_log_warn, base_vha, 0xb081,
5802 "Failed to dump mctp\n");
5803 return;
5804 }
5805
5806 if (!ha->flags.nic_core_reset_hdlr_active) {
5807 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5808 qla83xx_idc_lock(base_vha, 0);
5809 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5810 &dev_state);
5811 qla83xx_idc_unlock(base_vha, 0);
5812 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5813 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5814 "Nic Core f/w is alive.\n");
5815 return;
5816 }
5817 }
5818
5819 ha->flags.nic_core_reset_hdlr_active = 1;
5820 if (qla83xx_nic_core_reset(base_vha)) {
5821 /* NIC Core reset failed. */
5822 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5823 "NIC Core reset failed.\n");
5824 }
5825 ha->flags.nic_core_reset_hdlr_active = 0;
5826 }
5827 }
5828
5829 /* Work: Handle 8200 IDC aens */
5830 void
qla83xx_service_idc_aen(struct work_struct * work)5831 qla83xx_service_idc_aen(struct work_struct *work)
5832 {
5833 struct qla_hw_data *ha =
5834 container_of(work, struct qla_hw_data, idc_aen);
5835 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5836 uint32_t dev_state, idc_control;
5837
5838 qla83xx_idc_lock(base_vha, 0);
5839 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5840 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5841 qla83xx_idc_unlock(base_vha, 0);
5842 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5843 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5844 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5845 "Application requested NIC Core Reset.\n");
5846 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5847 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5848 QLA_SUCCESS) {
5849 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5850 "Other protocol driver requested NIC Core Reset.\n");
5851 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5852 }
5853 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5854 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5855 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5856 }
5857 }
5858
5859 /*
5860 * Control the frequency of IDC lock retries
5861 */
5862 #define QLA83XX_WAIT_LOGIC_MS 100
5863
5864 static int
qla83xx_force_lock_recovery(scsi_qla_host_t * base_vha)5865 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5866 {
5867 int rval;
5868 uint32_t data;
5869 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5870 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5871 struct qla_hw_data *ha = base_vha->hw;
5872
5873 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5874 "Trying force recovery of the IDC lock.\n");
5875
5876 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5877 if (rval)
5878 return rval;
5879
5880 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5881 return QLA_SUCCESS;
5882 } else {
5883 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5884 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5885 data);
5886 if (rval)
5887 return rval;
5888
5889 msleep(200);
5890
5891 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5892 &data);
5893 if (rval)
5894 return rval;
5895
5896 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5897 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5898 ~(idc_lck_rcvry_stage_mask));
5899 rval = qla83xx_wr_reg(base_vha,
5900 QLA83XX_IDC_LOCK_RECOVERY, data);
5901 if (rval)
5902 return rval;
5903
5904 /* Forcefully perform IDC UnLock */
5905 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5906 &data);
5907 if (rval)
5908 return rval;
5909 /* Clear lock-id by setting 0xff */
5910 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5911 0xff);
5912 if (rval)
5913 return rval;
5914 /* Clear lock-recovery by setting 0x0 */
5915 rval = qla83xx_wr_reg(base_vha,
5916 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5917 if (rval)
5918 return rval;
5919 } else
5920 return QLA_SUCCESS;
5921 }
5922
5923 return rval;
5924 }
5925
5926 static int
qla83xx_idc_lock_recovery(scsi_qla_host_t * base_vha)5927 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5928 {
5929 int rval = QLA_SUCCESS;
5930 uint32_t o_drv_lockid, n_drv_lockid;
5931 unsigned long lock_recovery_timeout;
5932
5933 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5934 retry_lockid:
5935 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5936 if (rval)
5937 goto exit;
5938
5939 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5940 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5941 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5942 return QLA_SUCCESS;
5943 else
5944 return QLA_FUNCTION_FAILED;
5945 }
5946
5947 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5948 if (rval)
5949 goto exit;
5950
5951 if (o_drv_lockid == n_drv_lockid) {
5952 msleep(QLA83XX_WAIT_LOGIC_MS);
5953 goto retry_lockid;
5954 } else
5955 return QLA_SUCCESS;
5956
5957 exit:
5958 return rval;
5959 }
5960
5961 /*
5962 * Context: task, can sleep
5963 */
5964 void
qla83xx_idc_lock(scsi_qla_host_t * base_vha,uint16_t requester_id)5965 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5966 {
5967 uint32_t data;
5968 uint32_t lock_owner;
5969 struct qla_hw_data *ha = base_vha->hw;
5970
5971 might_sleep();
5972
5973 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5974 retry_lock:
5975 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5976 == QLA_SUCCESS) {
5977 if (data) {
5978 /* Setting lock-id to our function-number */
5979 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5980 ha->portnum);
5981 } else {
5982 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5983 &lock_owner);
5984 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
5985 "Failed to acquire IDC lock, acquired by %d, "
5986 "retrying...\n", lock_owner);
5987
5988 /* Retry/Perform IDC-Lock recovery */
5989 if (qla83xx_idc_lock_recovery(base_vha)
5990 == QLA_SUCCESS) {
5991 msleep(QLA83XX_WAIT_LOGIC_MS);
5992 goto retry_lock;
5993 } else
5994 ql_log(ql_log_warn, base_vha, 0xb075,
5995 "IDC Lock recovery FAILED.\n");
5996 }
5997
5998 }
5999
6000 return;
6001 }
6002
6003 static bool
qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host * vha,struct purex_entry_24xx * purex)6004 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha,
6005 struct purex_entry_24xx *purex)
6006 {
6007 char fwstr[16];
6008 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0];
6009 struct port_database_24xx *pdb;
6010
6011 /* Domain Controller is always logged-out. */
6012 /* if RDP request is not from Domain Controller: */
6013 if (sid != 0xfffc01)
6014 return false;
6015
6016 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid);
6017
6018 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL);
6019 if (!pdb) {
6020 ql_dbg(ql_dbg_init, vha, 0x0181,
6021 "%s: Failed allocate pdb\n", __func__);
6022 } else if (qla24xx_get_port_database(vha,
6023 le16_to_cpu(purex->nport_handle), pdb)) {
6024 ql_dbg(ql_dbg_init, vha, 0x0181,
6025 "%s: Failed get pdb sid=%x\n", __func__, sid);
6026 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE &&
6027 pdb->current_login_state != PDS_PRLI_COMPLETE) {
6028 ql_dbg(ql_dbg_init, vha, 0x0181,
6029 "%s: Port not logged in sid=%#x\n", __func__, sid);
6030 } else {
6031 /* RDP request is from logged in port */
6032 kfree(pdb);
6033 return false;
6034 }
6035 kfree(pdb);
6036
6037 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr));
6038 fwstr[strcspn(fwstr, " ")] = 0;
6039 /* if FW version allows RDP response length upto 2048 bytes: */
6040 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0)
6041 return false;
6042
6043 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr);
6044
6045 /* RDP response length is to be reduced to maximum 256 bytes */
6046 return true;
6047 }
6048
6049 /*
6050 * Function Name: qla24xx_process_purex_iocb
6051 *
6052 * Description:
6053 * Prepare a RDP response and send to Fabric switch
6054 *
6055 * PARAMETERS:
6056 * vha: SCSI qla host
6057 * purex: RDP request received by HBA
6058 */
qla24xx_process_purex_rdp(struct scsi_qla_host * vha,struct purex_item * item)6059 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha,
6060 struct purex_item *item)
6061 {
6062 struct qla_hw_data *ha = vha->hw;
6063 struct purex_entry_24xx *purex =
6064 (struct purex_entry_24xx *)&item->iocb;
6065 dma_addr_t rsp_els_dma;
6066 dma_addr_t rsp_payload_dma;
6067 dma_addr_t stat_dma;
6068 dma_addr_t sfp_dma;
6069 struct els_entry_24xx *rsp_els = NULL;
6070 struct rdp_rsp_payload *rsp_payload = NULL;
6071 struct link_statistics *stat = NULL;
6072 uint8_t *sfp = NULL;
6073 uint16_t sfp_flags = 0;
6074 uint rsp_payload_length = sizeof(*rsp_payload);
6075 int rval;
6076
6077 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180,
6078 "%s: Enter\n", __func__);
6079
6080 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181,
6081 "-------- ELS REQ -------\n");
6082 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182,
6083 purex, sizeof(*purex));
6084
6085 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) {
6086 rsp_payload_length =
6087 offsetof(typeof(*rsp_payload), optical_elmt_desc);
6088 ql_dbg(ql_dbg_init, vha, 0x0181,
6089 "Reducing RSP payload length to %u bytes...\n",
6090 rsp_payload_length);
6091 }
6092
6093 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6094 &rsp_els_dma, GFP_KERNEL);
6095 if (!rsp_els) {
6096 ql_log(ql_log_warn, vha, 0x0183,
6097 "Failed allocate dma buffer ELS RSP.\n");
6098 goto dealloc;
6099 }
6100
6101 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6102 &rsp_payload_dma, GFP_KERNEL);
6103 if (!rsp_payload) {
6104 ql_log(ql_log_warn, vha, 0x0184,
6105 "Failed allocate dma buffer ELS RSP payload.\n");
6106 goto dealloc;
6107 }
6108
6109 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6110 &sfp_dma, GFP_KERNEL);
6111
6112 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat),
6113 &stat_dma, GFP_KERNEL);
6114
6115 /* Prepare Response IOCB */
6116 rsp_els->entry_type = ELS_IOCB_TYPE;
6117 rsp_els->entry_count = 1;
6118 rsp_els->sys_define = 0;
6119 rsp_els->entry_status = 0;
6120 rsp_els->handle = 0;
6121 rsp_els->nport_handle = purex->nport_handle;
6122 rsp_els->tx_dsd_count = cpu_to_le16(1);
6123 rsp_els->vp_index = purex->vp_idx;
6124 rsp_els->sof_type = EST_SOFI3;
6125 rsp_els->rx_xchg_address = purex->rx_xchg_addr;
6126 rsp_els->rx_dsd_count = 0;
6127 rsp_els->opcode = purex->els_frame_payload[0];
6128
6129 rsp_els->d_id[0] = purex->s_id[0];
6130 rsp_els->d_id[1] = purex->s_id[1];
6131 rsp_els->d_id[2] = purex->s_id[2];
6132
6133 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC);
6134 rsp_els->rx_byte_count = 0;
6135 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length);
6136
6137 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address);
6138 rsp_els->tx_len = rsp_els->tx_byte_count;
6139
6140 rsp_els->rx_address = 0;
6141 rsp_els->rx_len = 0;
6142
6143 /* Prepare Response Payload */
6144 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */
6145 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) -
6146 sizeof(rsp_payload->hdr));
6147
6148 /* Link service Request Info Descriptor */
6149 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1);
6150 rsp_payload->ls_req_info_desc.desc_len =
6151 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc));
6152 rsp_payload->ls_req_info_desc.req_payload_word_0 =
6153 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6154
6155 /* Link service Request Info Descriptor 2 */
6156 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1);
6157 rsp_payload->ls_req_info_desc2.desc_len =
6158 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2));
6159 rsp_payload->ls_req_info_desc2.req_payload_word_0 =
6160 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6161
6162
6163 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000);
6164 rsp_payload->sfp_diag_desc.desc_len =
6165 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc));
6166
6167 if (sfp) {
6168 /* SFP Flags */
6169 memset(sfp, 0, SFP_RTDI_LEN);
6170 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0);
6171 if (!rval) {
6172 /* SFP Flags bits 3-0: Port Tx Laser Type */
6173 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
6174 sfp_flags |= BIT_0; /* short wave */
6175 else if (sfp[0] & BIT_1)
6176 sfp_flags |= BIT_1; /* long wave 1310nm */
6177 else if (sfp[1] & BIT_4)
6178 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */
6179 }
6180
6181 /* SFP Type */
6182 memset(sfp, 0, SFP_RTDI_LEN);
6183 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0);
6184 if (!rval) {
6185 sfp_flags |= BIT_4; /* optical */
6186 if (sfp[0] == 0x3)
6187 sfp_flags |= BIT_6; /* sfp+ */
6188 }
6189
6190 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags);
6191
6192 /* SFP Diagnostics */
6193 memset(sfp, 0, SFP_RTDI_LEN);
6194 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0);
6195 if (!rval) {
6196 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
6197 rsp_payload->sfp_diag_desc.temperature = trx[0];
6198 rsp_payload->sfp_diag_desc.vcc = trx[1];
6199 rsp_payload->sfp_diag_desc.tx_bias = trx[2];
6200 rsp_payload->sfp_diag_desc.tx_power = trx[3];
6201 rsp_payload->sfp_diag_desc.rx_power = trx[4];
6202 }
6203 }
6204
6205 /* Port Speed Descriptor */
6206 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001);
6207 rsp_payload->port_speed_desc.desc_len =
6208 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc));
6209 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16(
6210 qla25xx_fdmi_port_speed_capability(ha));
6211 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16(
6212 qla25xx_fdmi_port_speed_currently(ha));
6213
6214 /* Link Error Status Descriptor */
6215 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002);
6216 rsp_payload->ls_err_desc.desc_len =
6217 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc));
6218
6219 if (stat) {
6220 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0);
6221 if (!rval) {
6222 rsp_payload->ls_err_desc.link_fail_cnt =
6223 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt));
6224 rsp_payload->ls_err_desc.loss_sync_cnt =
6225 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt));
6226 rsp_payload->ls_err_desc.loss_sig_cnt =
6227 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt));
6228 rsp_payload->ls_err_desc.prim_seq_err_cnt =
6229 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt));
6230 rsp_payload->ls_err_desc.inval_xmit_word_cnt =
6231 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt));
6232 rsp_payload->ls_err_desc.inval_crc_cnt =
6233 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt));
6234 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
6235 }
6236 }
6237
6238 /* Portname Descriptor */
6239 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003);
6240 rsp_payload->port_name_diag_desc.desc_len =
6241 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc));
6242 memcpy(rsp_payload->port_name_diag_desc.WWNN,
6243 vha->node_name,
6244 sizeof(rsp_payload->port_name_diag_desc.WWNN));
6245 memcpy(rsp_payload->port_name_diag_desc.WWPN,
6246 vha->port_name,
6247 sizeof(rsp_payload->port_name_diag_desc.WWPN));
6248
6249 /* F-Port Portname Descriptor */
6250 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003);
6251 rsp_payload->port_name_direct_desc.desc_len =
6252 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc));
6253 memcpy(rsp_payload->port_name_direct_desc.WWNN,
6254 vha->fabric_node_name,
6255 sizeof(rsp_payload->port_name_direct_desc.WWNN));
6256 memcpy(rsp_payload->port_name_direct_desc.WWPN,
6257 vha->fabric_port_name,
6258 sizeof(rsp_payload->port_name_direct_desc.WWPN));
6259
6260 /* Bufer Credit Descriptor */
6261 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006);
6262 rsp_payload->buffer_credit_desc.desc_len =
6263 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc));
6264 rsp_payload->buffer_credit_desc.fcport_b2b = 0;
6265 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0);
6266 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0);
6267
6268 if (ha->flags.plogi_template_valid) {
6269 uint32_t tmp =
6270 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred);
6271 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp);
6272 }
6273
6274 if (rsp_payload_length < sizeof(*rsp_payload))
6275 goto send;
6276
6277 /* Optical Element Descriptor, Temperature */
6278 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007);
6279 rsp_payload->optical_elmt_desc[0].desc_len =
6280 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6281 /* Optical Element Descriptor, Voltage */
6282 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007);
6283 rsp_payload->optical_elmt_desc[1].desc_len =
6284 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6285 /* Optical Element Descriptor, Tx Bias Current */
6286 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007);
6287 rsp_payload->optical_elmt_desc[2].desc_len =
6288 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6289 /* Optical Element Descriptor, Tx Power */
6290 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007);
6291 rsp_payload->optical_elmt_desc[3].desc_len =
6292 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6293 /* Optical Element Descriptor, Rx Power */
6294 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007);
6295 rsp_payload->optical_elmt_desc[4].desc_len =
6296 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6297
6298 if (sfp) {
6299 memset(sfp, 0, SFP_RTDI_LEN);
6300 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0);
6301 if (!rval) {
6302 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
6303
6304 /* Optical Element Descriptor, Temperature */
6305 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0];
6306 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1];
6307 rsp_payload->optical_elmt_desc[0].high_warn = trx[2];
6308 rsp_payload->optical_elmt_desc[0].low_warn = trx[3];
6309 rsp_payload->optical_elmt_desc[0].element_flags =
6310 cpu_to_be32(1 << 28);
6311
6312 /* Optical Element Descriptor, Voltage */
6313 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4];
6314 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5];
6315 rsp_payload->optical_elmt_desc[1].high_warn = trx[6];
6316 rsp_payload->optical_elmt_desc[1].low_warn = trx[7];
6317 rsp_payload->optical_elmt_desc[1].element_flags =
6318 cpu_to_be32(2 << 28);
6319
6320 /* Optical Element Descriptor, Tx Bias Current */
6321 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8];
6322 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9];
6323 rsp_payload->optical_elmt_desc[2].high_warn = trx[10];
6324 rsp_payload->optical_elmt_desc[2].low_warn = trx[11];
6325 rsp_payload->optical_elmt_desc[2].element_flags =
6326 cpu_to_be32(3 << 28);
6327
6328 /* Optical Element Descriptor, Tx Power */
6329 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12];
6330 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13];
6331 rsp_payload->optical_elmt_desc[3].high_warn = trx[14];
6332 rsp_payload->optical_elmt_desc[3].low_warn = trx[15];
6333 rsp_payload->optical_elmt_desc[3].element_flags =
6334 cpu_to_be32(4 << 28);
6335
6336 /* Optical Element Descriptor, Rx Power */
6337 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16];
6338 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17];
6339 rsp_payload->optical_elmt_desc[4].high_warn = trx[18];
6340 rsp_payload->optical_elmt_desc[4].low_warn = trx[19];
6341 rsp_payload->optical_elmt_desc[4].element_flags =
6342 cpu_to_be32(5 << 28);
6343 }
6344
6345 memset(sfp, 0, SFP_RTDI_LEN);
6346 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0);
6347 if (!rval) {
6348 /* Temperature high/low alarm/warning */
6349 rsp_payload->optical_elmt_desc[0].element_flags |=
6350 cpu_to_be32(
6351 (sfp[0] >> 7 & 1) << 3 |
6352 (sfp[0] >> 6 & 1) << 2 |
6353 (sfp[4] >> 7 & 1) << 1 |
6354 (sfp[4] >> 6 & 1) << 0);
6355
6356 /* Voltage high/low alarm/warning */
6357 rsp_payload->optical_elmt_desc[1].element_flags |=
6358 cpu_to_be32(
6359 (sfp[0] >> 5 & 1) << 3 |
6360 (sfp[0] >> 4 & 1) << 2 |
6361 (sfp[4] >> 5 & 1) << 1 |
6362 (sfp[4] >> 4 & 1) << 0);
6363
6364 /* Tx Bias Current high/low alarm/warning */
6365 rsp_payload->optical_elmt_desc[2].element_flags |=
6366 cpu_to_be32(
6367 (sfp[0] >> 3 & 1) << 3 |
6368 (sfp[0] >> 2 & 1) << 2 |
6369 (sfp[4] >> 3 & 1) << 1 |
6370 (sfp[4] >> 2 & 1) << 0);
6371
6372 /* Tx Power high/low alarm/warning */
6373 rsp_payload->optical_elmt_desc[3].element_flags |=
6374 cpu_to_be32(
6375 (sfp[0] >> 1 & 1) << 3 |
6376 (sfp[0] >> 0 & 1) << 2 |
6377 (sfp[4] >> 1 & 1) << 1 |
6378 (sfp[4] >> 0 & 1) << 0);
6379
6380 /* Rx Power high/low alarm/warning */
6381 rsp_payload->optical_elmt_desc[4].element_flags |=
6382 cpu_to_be32(
6383 (sfp[1] >> 7 & 1) << 3 |
6384 (sfp[1] >> 6 & 1) << 2 |
6385 (sfp[5] >> 7 & 1) << 1 |
6386 (sfp[5] >> 6 & 1) << 0);
6387 }
6388 }
6389
6390 /* Optical Product Data Descriptor */
6391 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008);
6392 rsp_payload->optical_prod_desc.desc_len =
6393 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc));
6394
6395 if (sfp) {
6396 memset(sfp, 0, SFP_RTDI_LEN);
6397 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0);
6398 if (!rval) {
6399 memcpy(rsp_payload->optical_prod_desc.vendor_name,
6400 sfp + 0,
6401 sizeof(rsp_payload->optical_prod_desc.vendor_name));
6402 memcpy(rsp_payload->optical_prod_desc.part_number,
6403 sfp + 20,
6404 sizeof(rsp_payload->optical_prod_desc.part_number));
6405 memcpy(rsp_payload->optical_prod_desc.revision,
6406 sfp + 36,
6407 sizeof(rsp_payload->optical_prod_desc.revision));
6408 memcpy(rsp_payload->optical_prod_desc.serial_number,
6409 sfp + 48,
6410 sizeof(rsp_payload->optical_prod_desc.serial_number));
6411 }
6412
6413 memset(sfp, 0, SFP_RTDI_LEN);
6414 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0);
6415 if (!rval) {
6416 memcpy(rsp_payload->optical_prod_desc.date,
6417 sfp + 0,
6418 sizeof(rsp_payload->optical_prod_desc.date));
6419 }
6420 }
6421
6422 send:
6423 ql_dbg(ql_dbg_init, vha, 0x0183,
6424 "Sending ELS Response to RDP Request...\n");
6425 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184,
6426 "-------- ELS RSP -------\n");
6427 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185,
6428 rsp_els, sizeof(*rsp_els));
6429 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186,
6430 "-------- ELS RSP PAYLOAD -------\n");
6431 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187,
6432 rsp_payload, rsp_payload_length);
6433
6434 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0);
6435
6436 if (rval) {
6437 ql_log(ql_log_warn, vha, 0x0188,
6438 "%s: iocb failed to execute -> %x\n", __func__, rval);
6439 } else if (rsp_els->comp_status) {
6440 ql_log(ql_log_warn, vha, 0x0189,
6441 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n",
6442 __func__, rsp_els->comp_status,
6443 rsp_els->error_subcode_1, rsp_els->error_subcode_2);
6444 } else {
6445 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__);
6446 }
6447
6448 dealloc:
6449 if (stat)
6450 dma_free_coherent(&ha->pdev->dev, sizeof(*stat),
6451 stat, stat_dma);
6452 if (sfp)
6453 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6454 sfp, sfp_dma);
6455 if (rsp_payload)
6456 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6457 rsp_payload, rsp_payload_dma);
6458 if (rsp_els)
6459 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6460 rsp_els, rsp_els_dma);
6461 }
6462
6463 void
qla24xx_free_purex_item(struct purex_item * item)6464 qla24xx_free_purex_item(struct purex_item *item)
6465 {
6466 if (item == &item->vha->default_item)
6467 memset(&item->vha->default_item, 0, sizeof(struct purex_item));
6468 else
6469 kfree(item);
6470 }
6471
qla24xx_process_purex_list(struct purex_list * list)6472 void qla24xx_process_purex_list(struct purex_list *list)
6473 {
6474 struct list_head head = LIST_HEAD_INIT(head);
6475 struct purex_item *item, *next;
6476 ulong flags;
6477
6478 spin_lock_irqsave(&list->lock, flags);
6479 list_splice_init(&list->head, &head);
6480 spin_unlock_irqrestore(&list->lock, flags);
6481
6482 list_for_each_entry_safe(item, next, &head, list) {
6483 list_del(&item->list);
6484 item->process_item(item->vha, item);
6485 qla24xx_free_purex_item(item);
6486 }
6487 }
6488
6489 /*
6490 * Context: task, can sleep
6491 */
6492 void
qla83xx_idc_unlock(scsi_qla_host_t * base_vha,uint16_t requester_id)6493 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
6494 {
6495 #if 0
6496 uint16_t options = (requester_id << 15) | BIT_7;
6497 #endif
6498 uint16_t retry;
6499 uint32_t data;
6500 struct qla_hw_data *ha = base_vha->hw;
6501
6502 might_sleep();
6503
6504 /* IDC-unlock implementation using driver-unlock/lock-id
6505 * remote registers
6506 */
6507 retry = 0;
6508 retry_unlock:
6509 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
6510 == QLA_SUCCESS) {
6511 if (data == ha->portnum) {
6512 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
6513 /* Clearing lock-id by setting 0xff */
6514 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
6515 } else if (retry < 10) {
6516 /* SV: XXX: IDC unlock retrying needed here? */
6517
6518 /* Retry for IDC-unlock */
6519 msleep(QLA83XX_WAIT_LOGIC_MS);
6520 retry++;
6521 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
6522 "Failed to release IDC lock, retrying=%d\n", retry);
6523 goto retry_unlock;
6524 }
6525 } else if (retry < 10) {
6526 /* Retry for IDC-unlock */
6527 msleep(QLA83XX_WAIT_LOGIC_MS);
6528 retry++;
6529 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
6530 "Failed to read drv-lockid, retrying=%d\n", retry);
6531 goto retry_unlock;
6532 }
6533
6534 return;
6535
6536 #if 0
6537 /* XXX: IDC-unlock implementation using access-control mbx */
6538 retry = 0;
6539 retry_unlock2:
6540 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
6541 if (retry < 10) {
6542 /* Retry for IDC-unlock */
6543 msleep(QLA83XX_WAIT_LOGIC_MS);
6544 retry++;
6545 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
6546 "Failed to release IDC lock, retrying=%d\n", retry);
6547 goto retry_unlock2;
6548 }
6549 }
6550
6551 return;
6552 #endif
6553 }
6554
6555 int
__qla83xx_set_drv_presence(scsi_qla_host_t * vha)6556 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6557 {
6558 int rval = QLA_SUCCESS;
6559 struct qla_hw_data *ha = vha->hw;
6560 uint32_t drv_presence;
6561
6562 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6563 if (rval == QLA_SUCCESS) {
6564 drv_presence |= (1 << ha->portnum);
6565 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6566 drv_presence);
6567 }
6568
6569 return rval;
6570 }
6571
6572 int
qla83xx_set_drv_presence(scsi_qla_host_t * vha)6573 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6574 {
6575 int rval = QLA_SUCCESS;
6576
6577 qla83xx_idc_lock(vha, 0);
6578 rval = __qla83xx_set_drv_presence(vha);
6579 qla83xx_idc_unlock(vha, 0);
6580
6581 return rval;
6582 }
6583
6584 int
__qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6585 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6586 {
6587 int rval = QLA_SUCCESS;
6588 struct qla_hw_data *ha = vha->hw;
6589 uint32_t drv_presence;
6590
6591 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6592 if (rval == QLA_SUCCESS) {
6593 drv_presence &= ~(1 << ha->portnum);
6594 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6595 drv_presence);
6596 }
6597
6598 return rval;
6599 }
6600
6601 int
qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6602 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6603 {
6604 int rval = QLA_SUCCESS;
6605
6606 qla83xx_idc_lock(vha, 0);
6607 rval = __qla83xx_clear_drv_presence(vha);
6608 qla83xx_idc_unlock(vha, 0);
6609
6610 return rval;
6611 }
6612
6613 static void
qla83xx_need_reset_handler(scsi_qla_host_t * vha)6614 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
6615 {
6616 struct qla_hw_data *ha = vha->hw;
6617 uint32_t drv_ack, drv_presence;
6618 unsigned long ack_timeout;
6619
6620 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
6621 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
6622 while (1) {
6623 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6624 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6625 if ((drv_ack & drv_presence) == drv_presence)
6626 break;
6627
6628 if (time_after_eq(jiffies, ack_timeout)) {
6629 ql_log(ql_log_warn, vha, 0xb067,
6630 "RESET ACK TIMEOUT! drv_presence=0x%x "
6631 "drv_ack=0x%x\n", drv_presence, drv_ack);
6632 /*
6633 * The function(s) which did not ack in time are forced
6634 * to withdraw any further participation in the IDC
6635 * reset.
6636 */
6637 if (drv_ack != drv_presence)
6638 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6639 drv_ack);
6640 break;
6641 }
6642
6643 qla83xx_idc_unlock(vha, 0);
6644 msleep(1000);
6645 qla83xx_idc_lock(vha, 0);
6646 }
6647
6648 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
6649 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
6650 }
6651
6652 static int
qla83xx_device_bootstrap(scsi_qla_host_t * vha)6653 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
6654 {
6655 int rval = QLA_SUCCESS;
6656 uint32_t idc_control;
6657
6658 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
6659 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
6660
6661 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
6662 __qla83xx_get_idc_control(vha, &idc_control);
6663 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
6664 __qla83xx_set_idc_control(vha, 0);
6665
6666 qla83xx_idc_unlock(vha, 0);
6667 rval = qla83xx_restart_nic_firmware(vha);
6668 qla83xx_idc_lock(vha, 0);
6669
6670 if (rval != QLA_SUCCESS) {
6671 ql_log(ql_log_fatal, vha, 0xb06a,
6672 "Failed to restart NIC f/w.\n");
6673 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
6674 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
6675 } else {
6676 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
6677 "Success in restarting nic f/w.\n");
6678 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
6679 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
6680 }
6681
6682 return rval;
6683 }
6684
6685 /* Assumes idc_lock always held on entry */
6686 int
qla83xx_idc_state_handler(scsi_qla_host_t * base_vha)6687 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
6688 {
6689 struct qla_hw_data *ha = base_vha->hw;
6690 int rval = QLA_SUCCESS;
6691 unsigned long dev_init_timeout;
6692 uint32_t dev_state;
6693
6694 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
6695 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
6696
6697 while (1) {
6698
6699 if (time_after_eq(jiffies, dev_init_timeout)) {
6700 ql_log(ql_log_warn, base_vha, 0xb06e,
6701 "Initialization TIMEOUT!\n");
6702 /* Init timeout. Disable further NIC Core
6703 * communication.
6704 */
6705 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
6706 QLA8XXX_DEV_FAILED);
6707 ql_log(ql_log_info, base_vha, 0xb06f,
6708 "HW State: FAILED.\n");
6709 }
6710
6711 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6712 switch (dev_state) {
6713 case QLA8XXX_DEV_READY:
6714 if (ha->flags.nic_core_reset_owner)
6715 qla83xx_idc_audit(base_vha,
6716 IDC_AUDIT_COMPLETION);
6717 ha->flags.nic_core_reset_owner = 0;
6718 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6719 "Reset_owner reset by 0x%x.\n",
6720 ha->portnum);
6721 goto exit;
6722 case QLA8XXX_DEV_COLD:
6723 if (ha->flags.nic_core_reset_owner)
6724 rval = qla83xx_device_bootstrap(base_vha);
6725 else {
6726 /* Wait for AEN to change device-state */
6727 qla83xx_idc_unlock(base_vha, 0);
6728 msleep(1000);
6729 qla83xx_idc_lock(base_vha, 0);
6730 }
6731 break;
6732 case QLA8XXX_DEV_INITIALIZING:
6733 /* Wait for AEN to change device-state */
6734 qla83xx_idc_unlock(base_vha, 0);
6735 msleep(1000);
6736 qla83xx_idc_lock(base_vha, 0);
6737 break;
6738 case QLA8XXX_DEV_NEED_RESET:
6739 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6740 qla83xx_need_reset_handler(base_vha);
6741 else {
6742 /* Wait for AEN to change device-state */
6743 qla83xx_idc_unlock(base_vha, 0);
6744 msleep(1000);
6745 qla83xx_idc_lock(base_vha, 0);
6746 }
6747 /* reset timeout value after need reset handler */
6748 dev_init_timeout = jiffies +
6749 (ha->fcoe_dev_init_timeout * HZ);
6750 break;
6751 case QLA8XXX_DEV_NEED_QUIESCENT:
6752 /* XXX: DEBUG for now */
6753 qla83xx_idc_unlock(base_vha, 0);
6754 msleep(1000);
6755 qla83xx_idc_lock(base_vha, 0);
6756 break;
6757 case QLA8XXX_DEV_QUIESCENT:
6758 /* XXX: DEBUG for now */
6759 if (ha->flags.quiesce_owner)
6760 goto exit;
6761
6762 qla83xx_idc_unlock(base_vha, 0);
6763 msleep(1000);
6764 qla83xx_idc_lock(base_vha, 0);
6765 dev_init_timeout = jiffies +
6766 (ha->fcoe_dev_init_timeout * HZ);
6767 break;
6768 case QLA8XXX_DEV_FAILED:
6769 if (ha->flags.nic_core_reset_owner)
6770 qla83xx_idc_audit(base_vha,
6771 IDC_AUDIT_COMPLETION);
6772 ha->flags.nic_core_reset_owner = 0;
6773 __qla83xx_clear_drv_presence(base_vha);
6774 qla83xx_idc_unlock(base_vha, 0);
6775 qla8xxx_dev_failed_handler(base_vha);
6776 rval = QLA_FUNCTION_FAILED;
6777 qla83xx_idc_lock(base_vha, 0);
6778 goto exit;
6779 case QLA8XXX_BAD_VALUE:
6780 qla83xx_idc_unlock(base_vha, 0);
6781 msleep(1000);
6782 qla83xx_idc_lock(base_vha, 0);
6783 break;
6784 default:
6785 ql_log(ql_log_warn, base_vha, 0xb071,
6786 "Unknown Device State: %x.\n", dev_state);
6787 qla83xx_idc_unlock(base_vha, 0);
6788 qla8xxx_dev_failed_handler(base_vha);
6789 rval = QLA_FUNCTION_FAILED;
6790 qla83xx_idc_lock(base_vha, 0);
6791 goto exit;
6792 }
6793 }
6794
6795 exit:
6796 return rval;
6797 }
6798
6799 void
qla2x00_disable_board_on_pci_error(struct work_struct * work)6800 qla2x00_disable_board_on_pci_error(struct work_struct *work)
6801 {
6802 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6803 board_disable);
6804 struct pci_dev *pdev = ha->pdev;
6805 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6806
6807 ql_log(ql_log_warn, base_vha, 0x015b,
6808 "Disabling adapter.\n");
6809
6810 if (!atomic_read(&pdev->enable_cnt)) {
6811 ql_log(ql_log_info, base_vha, 0xfffc,
6812 "PCI device disabled, no action req for PCI error=%lx\n",
6813 base_vha->pci_flags);
6814 return;
6815 }
6816
6817 /*
6818 * if UNLOADING flag is already set, then continue unload,
6819 * where it was set first.
6820 */
6821 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
6822 return;
6823
6824 qla2x00_wait_for_sess_deletion(base_vha);
6825
6826 qla2x00_delete_all_vps(ha, base_vha);
6827
6828 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6829
6830 qla2x00_dfs_remove(base_vha);
6831
6832 qla84xx_put_chip(base_vha);
6833
6834 if (base_vha->timer_active)
6835 qla2x00_stop_timer(base_vha);
6836
6837 base_vha->flags.online = 0;
6838
6839 qla2x00_destroy_deferred_work(ha);
6840
6841 /*
6842 * Do not try to stop beacon blink as it will issue a mailbox
6843 * command.
6844 */
6845 qla2x00_free_sysfs_attr(base_vha, false);
6846
6847 fc_remove_host(base_vha->host);
6848
6849 scsi_remove_host(base_vha->host);
6850
6851 base_vha->flags.init_done = 0;
6852 qla25xx_delete_queues(base_vha);
6853 qla2x00_free_fcports(base_vha);
6854 qla2x00_free_irqs(base_vha);
6855 qla2x00_mem_free(ha);
6856 qla82xx_md_free(base_vha);
6857 qla2x00_free_queues(ha);
6858
6859 qla2x00_unmap_iobases(ha);
6860
6861 pci_release_selected_regions(ha->pdev, ha->bars);
6862 pci_disable_device(pdev);
6863
6864 /*
6865 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6866 */
6867 }
6868
6869 /**************************************************************************
6870 * qla2x00_do_dpc
6871 * This kernel thread is a task that is schedule by the interrupt handler
6872 * to perform the background processing for interrupts.
6873 *
6874 * Notes:
6875 * This task always run in the context of a kernel thread. It
6876 * is kick-off by the driver's detect code and starts up
6877 * up one per adapter. It immediately goes to sleep and waits for
6878 * some fibre event. When either the interrupt handler or
6879 * the timer routine detects a event it will one of the task
6880 * bits then wake us up.
6881 **************************************************************************/
6882 static int
qla2x00_do_dpc(void * data)6883 qla2x00_do_dpc(void *data)
6884 {
6885 scsi_qla_host_t *base_vha;
6886 struct qla_hw_data *ha;
6887 uint32_t online;
6888 struct qla_qpair *qpair;
6889
6890 ha = (struct qla_hw_data *)data;
6891 base_vha = pci_get_drvdata(ha->pdev);
6892
6893 set_user_nice(current, MIN_NICE);
6894
6895 set_current_state(TASK_INTERRUPTIBLE);
6896 while (1) {
6897 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6898 "DPC handler sleeping.\n");
6899
6900 schedule();
6901
6902 if (kthread_should_stop())
6903 break;
6904
6905 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags))
6906 qla_pci_set_eeh_busy(base_vha);
6907
6908 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6909 goto end_loop;
6910
6911 if (ha->flags.eeh_busy) {
6912 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6913 "eeh_busy=%d.\n", ha->flags.eeh_busy);
6914 goto end_loop;
6915 }
6916
6917 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6918 /* don't do any work. Wait to be terminated by kthread_stop */
6919 goto end_loop;
6920
6921 ha->dpc_active = 1;
6922
6923 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6924 "DPC handler waking up, dpc_flags=0x%lx.\n",
6925 base_vha->dpc_flags);
6926
6927 if (IS_P3P_TYPE(ha)) {
6928 if (IS_QLA8044(ha)) {
6929 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6930 &base_vha->dpc_flags)) {
6931 qla8044_idc_lock(ha);
6932 qla8044_wr_direct(base_vha,
6933 QLA8044_CRB_DEV_STATE_INDEX,
6934 QLA8XXX_DEV_FAILED);
6935 qla8044_idc_unlock(ha);
6936 ql_log(ql_log_info, base_vha, 0x4004,
6937 "HW State: FAILED.\n");
6938 qla8044_device_state_handler(base_vha);
6939 continue;
6940 }
6941
6942 } else {
6943 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6944 &base_vha->dpc_flags)) {
6945 qla82xx_idc_lock(ha);
6946 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6947 QLA8XXX_DEV_FAILED);
6948 qla82xx_idc_unlock(ha);
6949 ql_log(ql_log_info, base_vha, 0x0151,
6950 "HW State: FAILED.\n");
6951 qla82xx_device_state_handler(base_vha);
6952 continue;
6953 }
6954 }
6955
6956 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6957 &base_vha->dpc_flags)) {
6958
6959 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6960 "FCoE context reset scheduled.\n");
6961 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6962 &base_vha->dpc_flags))) {
6963 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6964 /* FCoE-ctx reset failed.
6965 * Escalate to chip-reset
6966 */
6967 set_bit(ISP_ABORT_NEEDED,
6968 &base_vha->dpc_flags);
6969 }
6970 clear_bit(ABORT_ISP_ACTIVE,
6971 &base_vha->dpc_flags);
6972 }
6973
6974 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6975 "FCoE context reset end.\n");
6976 }
6977 } else if (IS_QLAFX00(ha)) {
6978 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6979 &base_vha->dpc_flags)) {
6980 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6981 "Firmware Reset Recovery\n");
6982 if (qlafx00_reset_initialize(base_vha)) {
6983 /* Failed. Abort isp later. */
6984 if (!test_bit(UNLOADING,
6985 &base_vha->dpc_flags)) {
6986 set_bit(ISP_UNRECOVERABLE,
6987 &base_vha->dpc_flags);
6988 ql_dbg(ql_dbg_dpc, base_vha,
6989 0x4021,
6990 "Reset Recovery Failed\n");
6991 }
6992 }
6993 }
6994
6995 if (test_and_clear_bit(FX00_TARGET_SCAN,
6996 &base_vha->dpc_flags)) {
6997 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6998 "ISPFx00 Target Scan scheduled\n");
6999 if (qlafx00_rescan_isp(base_vha)) {
7000 if (!test_bit(UNLOADING,
7001 &base_vha->dpc_flags))
7002 set_bit(ISP_UNRECOVERABLE,
7003 &base_vha->dpc_flags);
7004 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
7005 "ISPFx00 Target Scan Failed\n");
7006 }
7007 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
7008 "ISPFx00 Target Scan End\n");
7009 }
7010 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
7011 &base_vha->dpc_flags)) {
7012 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
7013 "ISPFx00 Host Info resend scheduled\n");
7014 qlafx00_fx_disc(base_vha,
7015 &base_vha->hw->mr.fcport,
7016 FXDISC_REG_HOST_INFO);
7017 }
7018 }
7019
7020 if (test_and_clear_bit(DETECT_SFP_CHANGE,
7021 &base_vha->dpc_flags)) {
7022 /* Semantic:
7023 * - NO-OP -- await next ISP-ABORT. Preferred method
7024 * to minimize disruptions that will occur
7025 * when a forced chip-reset occurs.
7026 * - Force -- ISP-ABORT scheduled.
7027 */
7028 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */
7029 }
7030
7031 if (test_and_clear_bit
7032 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
7033 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
7034 bool do_reset = true;
7035
7036 switch (base_vha->qlini_mode) {
7037 case QLA2XXX_INI_MODE_ENABLED:
7038 break;
7039 case QLA2XXX_INI_MODE_DISABLED:
7040 if (!qla_tgt_mode_enabled(base_vha) &&
7041 !ha->flags.fw_started)
7042 do_reset = false;
7043 break;
7044 case QLA2XXX_INI_MODE_DUAL:
7045 if (!qla_dual_mode_enabled(base_vha) &&
7046 !ha->flags.fw_started)
7047 do_reset = false;
7048 break;
7049 default:
7050 break;
7051 }
7052
7053 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
7054 &base_vha->dpc_flags))) {
7055 base_vha->flags.online = 1;
7056 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
7057 "ISP abort scheduled.\n");
7058 if (ha->isp_ops->abort_isp(base_vha)) {
7059 /* failed. retry later */
7060 set_bit(ISP_ABORT_NEEDED,
7061 &base_vha->dpc_flags);
7062 }
7063 clear_bit(ABORT_ISP_ACTIVE,
7064 &base_vha->dpc_flags);
7065 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
7066 "ISP abort end.\n");
7067 }
7068 }
7069
7070 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) {
7071 if (atomic_read(&base_vha->loop_state) == LOOP_READY) {
7072 qla24xx_process_purex_list
7073 (&base_vha->purex_list);
7074 clear_bit(PROCESS_PUREX_IOCB,
7075 &base_vha->dpc_flags);
7076 }
7077 }
7078
7079 if (IS_QLAFX00(ha))
7080 goto loop_resync_check;
7081
7082 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7083 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
7084 "Quiescence mode scheduled.\n");
7085 if (IS_P3P_TYPE(ha)) {
7086 if (IS_QLA82XX(ha))
7087 qla82xx_device_state_handler(base_vha);
7088 if (IS_QLA8044(ha))
7089 qla8044_device_state_handler(base_vha);
7090 clear_bit(ISP_QUIESCE_NEEDED,
7091 &base_vha->dpc_flags);
7092 if (!ha->flags.quiesce_owner) {
7093 qla2x00_perform_loop_resync(base_vha);
7094 if (IS_QLA82XX(ha)) {
7095 qla82xx_idc_lock(ha);
7096 qla82xx_clear_qsnt_ready(
7097 base_vha);
7098 qla82xx_idc_unlock(ha);
7099 } else if (IS_QLA8044(ha)) {
7100 qla8044_idc_lock(ha);
7101 qla8044_clear_qsnt_ready(
7102 base_vha);
7103 qla8044_idc_unlock(ha);
7104 }
7105 }
7106 } else {
7107 clear_bit(ISP_QUIESCE_NEEDED,
7108 &base_vha->dpc_flags);
7109 qla2x00_quiesce_io(base_vha);
7110 }
7111 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
7112 "Quiescence mode end.\n");
7113 }
7114
7115 if (test_and_clear_bit(RESET_MARKER_NEEDED,
7116 &base_vha->dpc_flags) &&
7117 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
7118
7119 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
7120 "Reset marker scheduled.\n");
7121 qla2x00_rst_aen(base_vha);
7122 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7123 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
7124 "Reset marker end.\n");
7125 }
7126
7127 /* Retry each device up to login retry count */
7128 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
7129 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
7130 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
7131
7132 if (!base_vha->relogin_jif ||
7133 time_after_eq(jiffies, base_vha->relogin_jif)) {
7134 base_vha->relogin_jif = jiffies + HZ;
7135 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
7136
7137 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
7138 "Relogin scheduled.\n");
7139 qla24xx_post_relogin_work(base_vha);
7140 }
7141 }
7142 loop_resync_check:
7143 if (!qla2x00_reset_active(base_vha) &&
7144 test_and_clear_bit(LOOP_RESYNC_NEEDED,
7145 &base_vha->dpc_flags)) {
7146 /*
7147 * Allow abort_isp to complete before moving on to scanning.
7148 */
7149 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
7150 "Loop resync scheduled.\n");
7151
7152 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
7153 &base_vha->dpc_flags))) {
7154
7155 qla2x00_loop_resync(base_vha);
7156
7157 clear_bit(LOOP_RESYNC_ACTIVE,
7158 &base_vha->dpc_flags);
7159 }
7160
7161 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
7162 "Loop resync end.\n");
7163 }
7164
7165 if (IS_QLAFX00(ha))
7166 goto intr_on_check;
7167
7168 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
7169 atomic_read(&base_vha->loop_state) == LOOP_READY) {
7170 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
7171 qla2xxx_flash_npiv_conf(base_vha);
7172 }
7173
7174 intr_on_check:
7175 if (!ha->interrupts_on)
7176 ha->isp_ops->enable_intrs(ha);
7177
7178 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
7179 &base_vha->dpc_flags)) {
7180 if (ha->beacon_blink_led == 1)
7181 ha->isp_ops->beacon_blink(base_vha);
7182 }
7183
7184 /* qpair online check */
7185 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
7186 &base_vha->dpc_flags)) {
7187 if (ha->flags.eeh_busy ||
7188 ha->flags.pci_channel_io_perm_failure)
7189 online = 0;
7190 else
7191 online = 1;
7192
7193 mutex_lock(&ha->mq_lock);
7194 list_for_each_entry(qpair, &base_vha->qp_list,
7195 qp_list_elem)
7196 qpair->online = online;
7197 mutex_unlock(&ha->mq_lock);
7198 }
7199
7200 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
7201 &base_vha->dpc_flags)) {
7202 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold;
7203
7204 if (threshold > ha->orig_fw_xcb_count)
7205 threshold = ha->orig_fw_xcb_count;
7206
7207 ql_log(ql_log_info, base_vha, 0xffffff,
7208 "SET ZIO Activity exchange threshold to %d.\n",
7209 threshold);
7210 if (qla27xx_set_zio_threshold(base_vha, threshold)) {
7211 ql_log(ql_log_info, base_vha, 0xffffff,
7212 "Unable to SET ZIO Activity exchange threshold to %d.\n",
7213 threshold);
7214 }
7215 }
7216
7217 if (!IS_QLAFX00(ha))
7218 qla2x00_do_dpc_all_vps(base_vha);
7219
7220 if (test_and_clear_bit(N2N_LINK_RESET,
7221 &base_vha->dpc_flags)) {
7222 qla2x00_lip_reset(base_vha);
7223 }
7224
7225 ha->dpc_active = 0;
7226 end_loop:
7227 set_current_state(TASK_INTERRUPTIBLE);
7228 } /* End of while(1) */
7229 __set_current_state(TASK_RUNNING);
7230
7231 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
7232 "DPC handler exiting.\n");
7233
7234 /*
7235 * Make sure that nobody tries to wake us up again.
7236 */
7237 ha->dpc_active = 0;
7238
7239 return 0;
7240 }
7241
7242 void
qla2xxx_wake_dpc(struct scsi_qla_host * vha)7243 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
7244 {
7245 struct qla_hw_data *ha = vha->hw;
7246 struct task_struct *t = ha->dpc_thread;
7247
7248 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
7249 wake_up_process(t);
7250 }
7251 EXPORT_SYMBOL(qla2xxx_wake_dpc);
7252
7253 /*
7254 * qla2x00_rst_aen
7255 * Processes asynchronous reset.
7256 *
7257 * Input:
7258 * ha = adapter block pointer.
7259 */
7260 static void
qla2x00_rst_aen(scsi_qla_host_t * vha)7261 qla2x00_rst_aen(scsi_qla_host_t *vha)
7262 {
7263 if (vha->flags.online && !vha->flags.reset_active &&
7264 !atomic_read(&vha->loop_down_timer) &&
7265 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
7266 do {
7267 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7268
7269 /*
7270 * Issue marker command only when we are going to start
7271 * the I/O.
7272 */
7273 vha->marker_needed = 1;
7274 } while (!atomic_read(&vha->loop_down_timer) &&
7275 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
7276 }
7277 }
7278
qla_do_heartbeat(struct scsi_qla_host * vha)7279 static bool qla_do_heartbeat(struct scsi_qla_host *vha)
7280 {
7281 struct qla_hw_data *ha = vha->hw;
7282 u32 cmpl_cnt;
7283 u16 i;
7284 bool do_heartbeat = false;
7285
7286 /*
7287 * Allow do_heartbeat only if we don’t have any active interrupts,
7288 * but there are still IOs outstanding with firmware.
7289 */
7290 cmpl_cnt = ha->base_qpair->cmd_completion_cnt;
7291 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt &&
7292 cmpl_cnt != ha->base_qpair->cmd_cnt) {
7293 do_heartbeat = true;
7294 goto skip;
7295 }
7296 ha->base_qpair->prev_completion_cnt = cmpl_cnt;
7297
7298 for (i = 0; i < ha->max_qpairs; i++) {
7299 if (ha->queue_pair_map[i]) {
7300 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt;
7301 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt &&
7302 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) {
7303 do_heartbeat = true;
7304 break;
7305 }
7306 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt;
7307 }
7308 }
7309
7310 skip:
7311 return do_heartbeat;
7312 }
7313
qla_heart_beat(struct scsi_qla_host * vha,u16 dpc_started)7314 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started)
7315 {
7316 struct qla_hw_data *ha = vha->hw;
7317
7318 if (vha->vp_idx)
7319 return;
7320
7321 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha))
7322 return;
7323
7324 /*
7325 * dpc thread cannot run if heartbeat is running at the same time.
7326 * We also do not want to starve heartbeat task. Therefore, do
7327 * heartbeat task at least once every 5 seconds.
7328 */
7329 if (dpc_started &&
7330 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ))
7331 return;
7332
7333 if (qla_do_heartbeat(vha)) {
7334 ha->last_heartbeat_run_jiffies = jiffies;
7335 queue_work(ha->wq, &ha->heartbeat_work);
7336 }
7337 }
7338
qla_wind_down_chip(scsi_qla_host_t * vha)7339 static void qla_wind_down_chip(scsi_qla_host_t *vha)
7340 {
7341 struct qla_hw_data *ha = vha->hw;
7342
7343 if (!ha->flags.eeh_busy)
7344 return;
7345 if (ha->pci_error_state)
7346 /* system is trying to recover */
7347 return;
7348
7349 /*
7350 * Current system is not handling PCIE error. At this point, this is
7351 * best effort to wind down the adapter.
7352 */
7353 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) &&
7354 !ha->flags.eeh_flush) {
7355 ql_log(ql_log_info, vha, 0x9009,
7356 "PCI Error detected, attempting to reset hardware.\n");
7357
7358 ha->isp_ops->reset_chip(vha);
7359 ha->isp_ops->disable_intrs(ha);
7360
7361 ha->flags.eeh_flush = EEH_FLUSH_RDY;
7362 ha->eeh_jif = jiffies;
7363
7364 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY &&
7365 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) {
7366 pci_clear_master(ha->pdev);
7367
7368 /* flush all command */
7369 qla2x00_abort_isp_cleanup(vha);
7370 ha->flags.eeh_flush = EEH_FLUSH_DONE;
7371
7372 ql_log(ql_log_info, vha, 0x900a,
7373 "PCI Error handling complete, all IOs aborted.\n");
7374 }
7375 }
7376
7377 /**************************************************************************
7378 * qla2x00_timer
7379 *
7380 * Description:
7381 * One second timer
7382 *
7383 * Context: Interrupt
7384 ***************************************************************************/
7385 void
qla2x00_timer(struct timer_list * t)7386 qla2x00_timer(struct timer_list *t)
7387 {
7388 scsi_qla_host_t *vha = timer_container_of(vha, t, timer);
7389 unsigned long cpu_flags = 0;
7390 int start_dpc = 0;
7391 int index;
7392 srb_t *sp;
7393 uint16_t w;
7394 struct qla_hw_data *ha = vha->hw;
7395 struct req_que *req;
7396 unsigned long flags;
7397 fc_port_t *fcport = NULL;
7398
7399 if (ha->flags.eeh_busy) {
7400 qla_wind_down_chip(vha);
7401
7402 ql_dbg(ql_dbg_timer, vha, 0x6000,
7403 "EEH = %d, restarting timer.\n",
7404 ha->flags.eeh_busy);
7405 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7406 return;
7407 }
7408
7409 /*
7410 * Hardware read to raise pending EEH errors during mailbox waits. If
7411 * the read returns -1 then disable the board.
7412 */
7413 if (!pci_channel_offline(ha->pdev)) {
7414 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
7415 qla2x00_check_reg16_for_disconnect(vha, w);
7416 }
7417
7418 /* Make sure qla82xx_watchdog is run only for physical port */
7419 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
7420 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
7421 start_dpc++;
7422 if (IS_QLA82XX(ha))
7423 qla82xx_watchdog(vha);
7424 else if (IS_QLA8044(ha))
7425 qla8044_watchdog(vha);
7426 }
7427
7428 if (!vha->vp_idx && IS_QLAFX00(ha))
7429 qlafx00_timer_routine(vha);
7430
7431 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7432 vha->link_down_time++;
7433
7434 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
7435 list_for_each_entry(fcport, &vha->vp_fcports, list) {
7436 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7437 fcport->tgt_link_down_time++;
7438 }
7439 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
7440
7441 /* Loop down handler. */
7442 if (atomic_read(&vha->loop_down_timer) > 0 &&
7443 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
7444 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
7445 && vha->flags.online) {
7446
7447 if (atomic_read(&vha->loop_down_timer) ==
7448 vha->loop_down_abort_time) {
7449
7450 ql_log(ql_log_info, vha, 0x6008,
7451 "Loop down - aborting the queues before time expires.\n");
7452
7453 if (!IS_QLA2100(ha) && vha->link_down_timeout)
7454 atomic_set(&vha->loop_state, LOOP_DEAD);
7455
7456 /*
7457 * Schedule an ISP abort to return any FCP2-device
7458 * commands.
7459 */
7460 /* NPIV - scan physical port only */
7461 if (!vha->vp_idx) {
7462 spin_lock_irqsave(&ha->hardware_lock,
7463 cpu_flags);
7464 req = ha->req_q_map[0];
7465 for (index = 1;
7466 index < req->num_outstanding_cmds;
7467 index++) {
7468 fc_port_t *sfcp;
7469
7470 sp = req->outstanding_cmds[index];
7471 if (!sp)
7472 continue;
7473 if (sp->cmd_type != TYPE_SRB)
7474 continue;
7475 if (sp->type != SRB_SCSI_CMD)
7476 continue;
7477 sfcp = sp->fcport;
7478 if (!(sfcp->flags & FCF_FCP2_DEVICE))
7479 continue;
7480
7481 if (IS_QLA82XX(ha))
7482 set_bit(FCOE_CTX_RESET_NEEDED,
7483 &vha->dpc_flags);
7484 else
7485 set_bit(ISP_ABORT_NEEDED,
7486 &vha->dpc_flags);
7487 break;
7488 }
7489 spin_unlock_irqrestore(&ha->hardware_lock,
7490 cpu_flags);
7491 }
7492 start_dpc++;
7493 }
7494
7495 /* if the loop has been down for 4 minutes, reinit adapter */
7496 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
7497 if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) {
7498 ql_log(ql_log_warn, vha, 0x6009,
7499 "Loop down - aborting ISP.\n");
7500
7501 if (IS_QLA82XX(ha))
7502 set_bit(FCOE_CTX_RESET_NEEDED,
7503 &vha->dpc_flags);
7504 else
7505 set_bit(ISP_ABORT_NEEDED,
7506 &vha->dpc_flags);
7507 }
7508 }
7509 ql_dbg(ql_dbg_timer, vha, 0x600a,
7510 "Loop down - seconds remaining %d.\n",
7511 atomic_read(&vha->loop_down_timer));
7512 }
7513 /* Check if beacon LED needs to be blinked for physical host only */
7514 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
7515 /* There is no beacon_blink function for ISP82xx */
7516 if (!IS_P3P_TYPE(ha)) {
7517 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
7518 start_dpc++;
7519 }
7520 }
7521
7522 /* check if edif running */
7523 if (vha->hw->flags.edif_enabled)
7524 qla_edif_timer(vha);
7525
7526 /* Process any deferred work. */
7527 if (!list_empty(&vha->work_list)) {
7528 unsigned long flags;
7529 bool q = false;
7530
7531 spin_lock_irqsave(&vha->work_lock, flags);
7532 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
7533 q = true;
7534 spin_unlock_irqrestore(&vha->work_lock, flags);
7535 if (q)
7536 queue_work(vha->hw->wq, &vha->iocb_work);
7537 }
7538
7539 /*
7540 * FC-NVME
7541 * see if the active AEN count has changed from what was last reported.
7542 */
7543 index = atomic_read(&ha->nvme_active_aen_cnt);
7544 if (!vha->vp_idx &&
7545 (index != ha->nvme_last_rptd_aen) &&
7546 ha->zio_mode == QLA_ZIO_MODE_6 &&
7547 !ha->flags.host_shutting_down) {
7548 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
7549 ql_log(ql_log_info, vha, 0x3002,
7550 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
7551 ha->nvme_last_rptd_aen);
7552 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7553 start_dpc++;
7554 }
7555
7556 if (!vha->vp_idx &&
7557 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold &&
7558 IS_ZIO_THRESHOLD_CAPABLE(ha)) {
7559 ql_log(ql_log_info, vha, 0x3002,
7560 "Sched: Set ZIO exchange threshold to %d.\n",
7561 ha->last_zio_threshold);
7562 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
7563 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7564 start_dpc++;
7565 }
7566 qla_adjust_buf(vha);
7567
7568 /* borrowing w to signify dpc will run */
7569 w = 0;
7570 /* Schedule the DPC routine if needed */
7571 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
7572 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
7573 start_dpc ||
7574 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
7575 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
7576 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
7577 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
7578 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7579 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
7580 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) {
7581 ql_dbg(ql_dbg_timer, vha, 0x600b,
7582 "isp_abort_needed=%d loop_resync_needed=%d "
7583 "start_dpc=%d reset_marker_needed=%d",
7584 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
7585 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
7586 start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
7587 ql_dbg(ql_dbg_timer, vha, 0x600c,
7588 "beacon_blink_needed=%d isp_unrecoverable=%d "
7589 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
7590 "relogin_needed=%d, Process_purex_iocb=%d.\n",
7591 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
7592 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
7593 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
7594 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
7595 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
7596 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags));
7597 qla2xxx_wake_dpc(vha);
7598 w = 1;
7599 }
7600
7601 qla_heart_beat(vha, w);
7602
7603 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7604 }
7605
7606 /* Firmware interface routines. */
7607
7608 #define FW_ISP21XX 0
7609 #define FW_ISP22XX 1
7610 #define FW_ISP2300 2
7611 #define FW_ISP2322 3
7612 #define FW_ISP24XX 4
7613 #define FW_ISP25XX 5
7614 #define FW_ISP81XX 6
7615 #define FW_ISP82XX 7
7616 #define FW_ISP2031 8
7617 #define FW_ISP8031 9
7618 #define FW_ISP27XX 10
7619 #define FW_ISP28XX 11
7620
7621 #define FW_FILE_ISP21XX "ql2100_fw.bin"
7622 #define FW_FILE_ISP22XX "ql2200_fw.bin"
7623 #define FW_FILE_ISP2300 "ql2300_fw.bin"
7624 #define FW_FILE_ISP2322 "ql2322_fw.bin"
7625 #define FW_FILE_ISP24XX "ql2400_fw.bin"
7626 #define FW_FILE_ISP25XX "ql2500_fw.bin"
7627 #define FW_FILE_ISP81XX "ql8100_fw.bin"
7628 #define FW_FILE_ISP82XX "ql8200_fw.bin"
7629 #define FW_FILE_ISP2031 "ql2600_fw.bin"
7630 #define FW_FILE_ISP8031 "ql8300_fw.bin"
7631 #define FW_FILE_ISP27XX "ql2700_fw.bin"
7632 #define FW_FILE_ISP28XX "ql2800_fw.bin"
7633
7634
7635 static DEFINE_MUTEX(qla_fw_lock);
7636
7637 static struct fw_blob qla_fw_blobs[] = {
7638 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
7639 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
7640 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
7641 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
7642 { .name = FW_FILE_ISP24XX, },
7643 { .name = FW_FILE_ISP25XX, },
7644 { .name = FW_FILE_ISP81XX, },
7645 { .name = FW_FILE_ISP82XX, },
7646 { .name = FW_FILE_ISP2031, },
7647 { .name = FW_FILE_ISP8031, },
7648 { .name = FW_FILE_ISP27XX, },
7649 { .name = FW_FILE_ISP28XX, },
7650 { .name = NULL, },
7651 };
7652
7653 struct fw_blob *
qla2x00_request_firmware(scsi_qla_host_t * vha)7654 qla2x00_request_firmware(scsi_qla_host_t *vha)
7655 {
7656 struct qla_hw_data *ha = vha->hw;
7657 struct fw_blob *blob;
7658
7659 if (IS_QLA2100(ha)) {
7660 blob = &qla_fw_blobs[FW_ISP21XX];
7661 } else if (IS_QLA2200(ha)) {
7662 blob = &qla_fw_blobs[FW_ISP22XX];
7663 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
7664 blob = &qla_fw_blobs[FW_ISP2300];
7665 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
7666 blob = &qla_fw_blobs[FW_ISP2322];
7667 } else if (IS_QLA24XX_TYPE(ha)) {
7668 blob = &qla_fw_blobs[FW_ISP24XX];
7669 } else if (IS_QLA25XX(ha)) {
7670 blob = &qla_fw_blobs[FW_ISP25XX];
7671 } else if (IS_QLA81XX(ha)) {
7672 blob = &qla_fw_blobs[FW_ISP81XX];
7673 } else if (IS_QLA82XX(ha)) {
7674 blob = &qla_fw_blobs[FW_ISP82XX];
7675 } else if (IS_QLA2031(ha)) {
7676 blob = &qla_fw_blobs[FW_ISP2031];
7677 } else if (IS_QLA8031(ha)) {
7678 blob = &qla_fw_blobs[FW_ISP8031];
7679 } else if (IS_QLA27XX(ha)) {
7680 blob = &qla_fw_blobs[FW_ISP27XX];
7681 } else if (IS_QLA28XX(ha)) {
7682 blob = &qla_fw_blobs[FW_ISP28XX];
7683 } else {
7684 return NULL;
7685 }
7686
7687 if (!blob->name)
7688 return NULL;
7689
7690 mutex_lock(&qla_fw_lock);
7691 if (blob->fw)
7692 goto out;
7693
7694 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7695 ql_log(ql_log_warn, vha, 0x0063,
7696 "Failed to load firmware image (%s).\n", blob->name);
7697 blob->fw = NULL;
7698 blob = NULL;
7699 }
7700
7701 out:
7702 mutex_unlock(&qla_fw_lock);
7703 return blob;
7704 }
7705
7706 static void
qla2x00_release_firmware(void)7707 qla2x00_release_firmware(void)
7708 {
7709 struct fw_blob *blob;
7710
7711 mutex_lock(&qla_fw_lock);
7712 for (blob = qla_fw_blobs; blob->name; blob++)
7713 release_firmware(blob->fw);
7714 mutex_unlock(&qla_fw_lock);
7715 }
7716
qla_pci_error_cleanup(scsi_qla_host_t * vha)7717 static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
7718 {
7719 struct qla_hw_data *ha = vha->hw;
7720 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
7721 struct qla_qpair *qpair = NULL;
7722 struct scsi_qla_host *vp, *tvp;
7723 fc_port_t *fcport;
7724 int i;
7725 unsigned long flags;
7726
7727 ql_dbg(ql_dbg_aer, vha, 0x9000,
7728 "%s\n", __func__);
7729 ha->chip_reset++;
7730
7731 ha->base_qpair->chip_reset = ha->chip_reset;
7732 for (i = 0; i < ha->max_qpairs; i++) {
7733 if (ha->queue_pair_map[i])
7734 ha->queue_pair_map[i]->chip_reset =
7735 ha->base_qpair->chip_reset;
7736 }
7737
7738 /*
7739 * purge mailbox might take a while. Slot Reset/chip reset
7740 * will take care of the purge
7741 */
7742
7743 mutex_lock(&ha->mq_lock);
7744 ha->base_qpair->online = 0;
7745 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7746 qpair->online = 0;
7747 wmb();
7748 mutex_unlock(&ha->mq_lock);
7749
7750 qla2x00_mark_all_devices_lost(vha);
7751
7752 spin_lock_irqsave(&ha->vport_slock, flags);
7753 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7754 atomic_inc(&vp->vref_count);
7755 spin_unlock_irqrestore(&ha->vport_slock, flags);
7756 qla2x00_mark_all_devices_lost(vp);
7757 spin_lock_irqsave(&ha->vport_slock, flags);
7758 atomic_dec(&vp->vref_count);
7759 }
7760 spin_unlock_irqrestore(&ha->vport_slock, flags);
7761
7762 /* Clear all async request states across all VPs. */
7763 list_for_each_entry(fcport, &vha->vp_fcports, list)
7764 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7765
7766 spin_lock_irqsave(&ha->vport_slock, flags);
7767 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7768 atomic_inc(&vp->vref_count);
7769 spin_unlock_irqrestore(&ha->vport_slock, flags);
7770 list_for_each_entry(fcport, &vp->vp_fcports, list)
7771 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7772 spin_lock_irqsave(&ha->vport_slock, flags);
7773 atomic_dec(&vp->vref_count);
7774 }
7775 spin_unlock_irqrestore(&ha->vport_slock, flags);
7776 }
7777
7778
7779 static pci_ers_result_t
qla2xxx_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)7780 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
7781 {
7782 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
7783 struct qla_hw_data *ha = vha->hw;
7784 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET;
7785
7786 ql_log(ql_log_warn, vha, 0x9000,
7787 "PCI error detected, state %x.\n", state);
7788 ha->pci_error_state = QLA_PCI_ERR_DETECTED;
7789
7790 if (!atomic_read(&pdev->enable_cnt)) {
7791 ql_log(ql_log_info, vha, 0xffff,
7792 "PCI device is disabled,state %x\n", state);
7793 ret = PCI_ERS_RESULT_NEED_RESET;
7794 goto out;
7795 }
7796
7797 switch (state) {
7798 case pci_channel_io_normal:
7799 qla_pci_set_eeh_busy(vha);
7800 if (ql2xmqsupport || ql2xnvmeenable) {
7801 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7802 qla2xxx_wake_dpc(vha);
7803 }
7804 ret = PCI_ERS_RESULT_CAN_RECOVER;
7805 break;
7806 case pci_channel_io_frozen:
7807 qla_pci_set_eeh_busy(vha);
7808 ret = PCI_ERS_RESULT_NEED_RESET;
7809 break;
7810 case pci_channel_io_perm_failure:
7811 ha->flags.pci_channel_io_perm_failure = 1;
7812 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
7813 if (ql2xmqsupport || ql2xnvmeenable) {
7814 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7815 qla2xxx_wake_dpc(vha);
7816 }
7817 ret = PCI_ERS_RESULT_DISCONNECT;
7818 }
7819 out:
7820 ql_dbg(ql_dbg_aer, vha, 0x600d,
7821 "PCI error detected returning [%x].\n", ret);
7822 return ret;
7823 }
7824
7825 static pci_ers_result_t
qla2xxx_pci_mmio_enabled(struct pci_dev * pdev)7826 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
7827 {
7828 int risc_paused = 0;
7829 uint32_t stat;
7830 unsigned long flags;
7831 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7832 struct qla_hw_data *ha = base_vha->hw;
7833 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7834 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
7835
7836 ql_log(ql_log_warn, base_vha, 0x9000,
7837 "mmio enabled\n");
7838
7839 ha->pci_error_state = QLA_PCI_MMIO_ENABLED;
7840
7841 if (IS_QLA82XX(ha))
7842 return PCI_ERS_RESULT_RECOVERED;
7843
7844 if (qla2x00_isp_reg_stat(ha)) {
7845 ql_log(ql_log_info, base_vha, 0x803f,
7846 "During mmio enabled, PCI/Register disconnect still detected.\n");
7847 goto out;
7848 }
7849
7850 spin_lock_irqsave(&ha->hardware_lock, flags);
7851 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
7852 stat = rd_reg_word(®->hccr);
7853 if (stat & HCCR_RISC_PAUSE)
7854 risc_paused = 1;
7855 } else if (IS_QLA23XX(ha)) {
7856 stat = rd_reg_dword(®->u.isp2300.host_status);
7857 if (stat & HSR_RISC_PAUSED)
7858 risc_paused = 1;
7859 } else if (IS_FWI2_CAPABLE(ha)) {
7860 stat = rd_reg_dword(®24->host_status);
7861 if (stat & HSRX_RISC_PAUSED)
7862 risc_paused = 1;
7863 }
7864 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7865
7866 if (risc_paused) {
7867 ql_log(ql_log_info, base_vha, 0x9003,
7868 "RISC paused -- mmio_enabled, Dumping firmware.\n");
7869 qla2xxx_dump_fw(base_vha);
7870 }
7871 out:
7872 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */
7873 ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7874 "mmio enabled returning.\n");
7875 return PCI_ERS_RESULT_NEED_RESET;
7876 }
7877
7878 static pci_ers_result_t
qla2xxx_pci_slot_reset(struct pci_dev * pdev)7879 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7880 {
7881 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
7882 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7883 struct qla_hw_data *ha = base_vha->hw;
7884 int rc;
7885 struct qla_qpair *qpair = NULL;
7886
7887 ql_log(ql_log_warn, base_vha, 0x9004,
7888 "Slot Reset.\n");
7889
7890 ha->pci_error_state = QLA_PCI_SLOT_RESET;
7891
7892 pci_restore_state(pdev);
7893
7894 if (ha->mem_only)
7895 rc = pci_enable_device_mem(pdev);
7896 else
7897 rc = pci_enable_device(pdev);
7898
7899 if (rc) {
7900 ql_log(ql_log_warn, base_vha, 0x9005,
7901 "Can't re-enable PCI device after reset.\n");
7902 goto exit_slot_reset;
7903 }
7904
7905
7906 if (ha->isp_ops->pci_config(base_vha))
7907 goto exit_slot_reset;
7908
7909 mutex_lock(&ha->mq_lock);
7910 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7911 qpair->online = 1;
7912 mutex_unlock(&ha->mq_lock);
7913
7914 ha->flags.eeh_busy = 0;
7915 base_vha->flags.online = 1;
7916 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7917 ha->isp_ops->abort_isp(base_vha);
7918 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7919
7920 if (qla2x00_isp_reg_stat(ha)) {
7921 ha->flags.eeh_busy = 1;
7922 qla_pci_error_cleanup(base_vha);
7923 ql_log(ql_log_warn, base_vha, 0x9005,
7924 "Device unable to recover from PCI error.\n");
7925 } else {
7926 ret = PCI_ERS_RESULT_RECOVERED;
7927 }
7928
7929 exit_slot_reset:
7930 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7931 "Slot Reset returning %x.\n", ret);
7932
7933 return ret;
7934 }
7935
7936 static void
qla2xxx_pci_resume(struct pci_dev * pdev)7937 qla2xxx_pci_resume(struct pci_dev *pdev)
7938 {
7939 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7940 struct qla_hw_data *ha = base_vha->hw;
7941 int ret;
7942
7943 ql_log(ql_log_warn, base_vha, 0x900f,
7944 "Pci Resume.\n");
7945
7946
7947 ret = qla2x00_wait_for_hba_online(base_vha);
7948 if (ret != QLA_SUCCESS) {
7949 ql_log(ql_log_fatal, base_vha, 0x9002,
7950 "The device failed to resume I/O from slot/link_reset.\n");
7951 }
7952 ha->pci_error_state = QLA_PCI_RESUME;
7953 ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7954 "Pci Resume returning.\n");
7955 }
7956
qla_pci_set_eeh_busy(struct scsi_qla_host * vha)7957 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha)
7958 {
7959 struct qla_hw_data *ha = vha->hw;
7960 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7961 bool do_cleanup = false;
7962 unsigned long flags;
7963
7964 if (ha->flags.eeh_busy)
7965 return;
7966
7967 spin_lock_irqsave(&base_vha->work_lock, flags);
7968 if (!ha->flags.eeh_busy) {
7969 ha->eeh_jif = jiffies;
7970 ha->flags.eeh_flush = 0;
7971
7972 ha->flags.eeh_busy = 1;
7973 do_cleanup = true;
7974 }
7975 spin_unlock_irqrestore(&base_vha->work_lock, flags);
7976
7977 if (do_cleanup)
7978 qla_pci_error_cleanup(base_vha);
7979 }
7980
7981 /*
7982 * this routine will schedule a task to pause IO from interrupt context
7983 * if caller sees a PCIE error event (register read = 0xf's)
7984 */
qla_schedule_eeh_work(struct scsi_qla_host * vha)7985 void qla_schedule_eeh_work(struct scsi_qla_host *vha)
7986 {
7987 struct qla_hw_data *ha = vha->hw;
7988 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7989
7990 if (ha->flags.eeh_busy)
7991 return;
7992
7993 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags);
7994 qla2xxx_wake_dpc(base_vha);
7995 }
7996
7997 static void
qla_pci_reset_prepare(struct pci_dev * pdev)7998 qla_pci_reset_prepare(struct pci_dev *pdev)
7999 {
8000 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8001 struct qla_hw_data *ha = base_vha->hw;
8002 struct qla_qpair *qpair;
8003
8004 ql_log(ql_log_warn, base_vha, 0xffff,
8005 "%s.\n", __func__);
8006
8007 /*
8008 * PCI FLR/function reset is about to reset the
8009 * slot. Stop the chip to stop all DMA access.
8010 * It is assumed that pci_reset_done will be called
8011 * after FLR to resume Chip operation.
8012 */
8013 ha->flags.eeh_busy = 1;
8014 mutex_lock(&ha->mq_lock);
8015 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8016 qpair->online = 0;
8017 mutex_unlock(&ha->mq_lock);
8018
8019 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8020 qla2x00_abort_isp_cleanup(base_vha);
8021 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
8022 }
8023
8024 static void
qla_pci_reset_done(struct pci_dev * pdev)8025 qla_pci_reset_done(struct pci_dev *pdev)
8026 {
8027 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8028 struct qla_hw_data *ha = base_vha->hw;
8029 struct qla_qpair *qpair;
8030
8031 ql_log(ql_log_warn, base_vha, 0xffff,
8032 "%s.\n", __func__);
8033
8034 /*
8035 * FLR just completed by PCI layer. Resume adapter
8036 */
8037 ha->flags.eeh_busy = 0;
8038 mutex_lock(&ha->mq_lock);
8039 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8040 qpair->online = 1;
8041 mutex_unlock(&ha->mq_lock);
8042
8043 base_vha->flags.online = 1;
8044 ha->isp_ops->abort_isp(base_vha);
8045 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8046 }
8047
qla2xxx_map_queues(struct Scsi_Host * shost)8048 static void qla2xxx_map_queues(struct Scsi_Host *shost)
8049 {
8050 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
8051 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
8052
8053 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
8054 blk_mq_map_queues(qmap);
8055 else
8056 blk_mq_map_hw_queues(qmap, &vha->hw->pdev->dev,
8057 vha->irq_offset);
8058 }
8059
8060 struct scsi_host_template qla2xxx_driver_template = {
8061 .module = THIS_MODULE,
8062 .name = QLA2XXX_DRIVER_NAME,
8063 .queuecommand = qla2xxx_queuecommand,
8064
8065 .eh_timed_out = fc_eh_timed_out,
8066 .eh_abort_handler = qla2xxx_eh_abort,
8067 .eh_should_retry_cmd = fc_eh_should_retry_cmd,
8068 .eh_device_reset_handler = qla2xxx_eh_device_reset,
8069 .eh_target_reset_handler = qla2xxx_eh_target_reset,
8070 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
8071 .eh_host_reset_handler = qla2xxx_eh_host_reset,
8072
8073 .sdev_configure = qla2xxx_sdev_configure,
8074
8075 .sdev_init = qla2xxx_sdev_init,
8076 .sdev_destroy = qla2xxx_sdev_destroy,
8077 .scan_finished = qla2xxx_scan_finished,
8078 .scan_start = qla2xxx_scan_start,
8079 .change_queue_depth = scsi_change_queue_depth,
8080 .map_queues = qla2xxx_map_queues,
8081 .this_id = -1,
8082 .cmd_per_lun = 3,
8083 .sg_tablesize = SG_ALL,
8084
8085 .max_sectors = 0xFFFF,
8086 .shost_groups = qla2x00_host_groups,
8087
8088 .supported_mode = MODE_INITIATOR,
8089 .track_queue_depth = 1,
8090 .cmd_size = sizeof(srb_t),
8091 };
8092
8093 static const struct pci_error_handlers qla2xxx_err_handler = {
8094 .error_detected = qla2xxx_pci_error_detected,
8095 .mmio_enabled = qla2xxx_pci_mmio_enabled,
8096 .slot_reset = qla2xxx_pci_slot_reset,
8097 .resume = qla2xxx_pci_resume,
8098 .reset_prepare = qla_pci_reset_prepare,
8099 .reset_done = qla_pci_reset_done,
8100 };
8101
8102 static const struct pci_device_id qla2xxx_pci_tbl[] = {
8103 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
8104 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
8105 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
8106 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
8107 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
8108 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
8109 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
8110 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
8111 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
8112 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
8113 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
8114 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
8115 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
8116 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
8117 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
8118 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
8119 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8120 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
8121 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
8122 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
8123 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
8124 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
8125 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
8126 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
8127 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
8128 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
8129 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
8130 { 0 },
8131 };
8132 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
8133
8134 static struct pci_driver qla2xxx_pci_driver = {
8135 .name = QLA2XXX_DRIVER_NAME,
8136 .id_table = qla2xxx_pci_tbl,
8137 .probe = qla2x00_probe_one,
8138 .remove = qla2x00_remove_one,
8139 .shutdown = qla2x00_shutdown,
8140 .err_handler = &qla2xxx_err_handler,
8141 };
8142
8143 static const struct file_operations apidev_fops = {
8144 .owner = THIS_MODULE,
8145 .llseek = noop_llseek,
8146 };
8147
8148 /**
8149 * qla2x00_module_init - Module initialization.
8150 **/
8151 static int __init
qla2x00_module_init(void)8152 qla2x00_module_init(void)
8153 {
8154 int ret = 0;
8155
8156 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64);
8157 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
8158 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
8159 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
8160 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
8161 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64);
8162 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
8163 BUILD_BUG_ON(sizeof(request_t) != 64);
8164 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64);
8165 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64);
8166 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64);
8167 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
8168 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64);
8169 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
8170 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
8171 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
8172 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
8173 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
8174 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
8175 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
8176 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604);
8177 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424);
8178 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164);
8179 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260);
8180 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260);
8181 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16);
8182 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
8183 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256);
8184 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24);
8185 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256);
8186 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288);
8187 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216);
8188 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
8189 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64);
8190 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
8191 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64);
8192 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
8193 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
8194 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64);
8195 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64);
8196 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252);
8197 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64);
8198 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512);
8199 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512);
8200 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
8201 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64);
8202 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64);
8203 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634);
8204 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100);
8205 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976);
8206 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228);
8207 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52);
8208 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172);
8209 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524);
8210 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8);
8211 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12);
8212 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24);
8213 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420);
8214 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28);
8215 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32);
8216 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196);
8217 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE);
8218 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128);
8219 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8);
8220 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16);
8221 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24);
8222 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16);
8223 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336);
8224 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
8225 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64);
8226 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64);
8227 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64);
8228 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
8229 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52);
8230 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
8231 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64);
8232 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64);
8233 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64);
8234 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64);
8235 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64);
8236 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64);
8237 BUILD_BUG_ON(sizeof(sts_entry_t) != 64);
8238 BUILD_BUG_ON(sizeof(sw_info_t) != 32);
8239 BUILD_BUG_ON(sizeof(target_id_t) != 2);
8240
8241 qla_trace_init();
8242
8243 /* Allocate cache for SRBs. */
8244 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
8245 SLAB_HWCACHE_ALIGN, NULL);
8246 if (srb_cachep == NULL) {
8247 ql_log(ql_log_fatal, NULL, 0x0001,
8248 "Unable to allocate SRB cache...Failing load!.\n");
8249 return -ENOMEM;
8250 }
8251
8252 /* Initialize target kmem_cache and mem_pools */
8253 ret = qlt_init();
8254 if (ret < 0) {
8255 goto destroy_cache;
8256 } else if (ret > 0) {
8257 /*
8258 * If initiator mode is explictly disabled by qlt_init(),
8259 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
8260 * performing scsi_scan_target() during LOOP UP event.
8261 */
8262 qla2xxx_transport_functions.disable_target_scan = 1;
8263 qla2xxx_transport_vport_functions.disable_target_scan = 1;
8264 }
8265
8266 /* Derive version string. */
8267 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
8268 if (ql2xextended_error_logging)
8269 strcat(qla2x00_version_str, "-debug");
8270 if (ql2xextended_error_logging == 1)
8271 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
8272
8273 qla2xxx_transport_template =
8274 fc_attach_transport(&qla2xxx_transport_functions);
8275 if (!qla2xxx_transport_template) {
8276 ql_log(ql_log_fatal, NULL, 0x0002,
8277 "fc_attach_transport failed...Failing load!.\n");
8278 ret = -ENODEV;
8279 goto qlt_exit;
8280 }
8281
8282 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
8283 if (apidev_major < 0) {
8284 ql_log(ql_log_fatal, NULL, 0x0003,
8285 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
8286 }
8287
8288 qla2xxx_transport_vport_template =
8289 fc_attach_transport(&qla2xxx_transport_vport_functions);
8290 if (!qla2xxx_transport_vport_template) {
8291 ql_log(ql_log_fatal, NULL, 0x0004,
8292 "fc_attach_transport vport failed...Failing load!.\n");
8293 ret = -ENODEV;
8294 goto unreg_chrdev;
8295 }
8296 ql_log(ql_log_info, NULL, 0x0005,
8297 "QLogic Fibre Channel HBA Driver: %s.\n",
8298 qla2x00_version_str);
8299 ret = pci_register_driver(&qla2xxx_pci_driver);
8300 if (ret) {
8301 ql_log(ql_log_fatal, NULL, 0x0006,
8302 "pci_register_driver failed...ret=%d Failing load!.\n",
8303 ret);
8304 goto release_vport_transport;
8305 }
8306 return ret;
8307
8308 release_vport_transport:
8309 fc_release_transport(qla2xxx_transport_vport_template);
8310
8311 unreg_chrdev:
8312 if (apidev_major >= 0)
8313 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8314 fc_release_transport(qla2xxx_transport_template);
8315
8316 qlt_exit:
8317 qlt_exit();
8318
8319 destroy_cache:
8320 kmem_cache_destroy(srb_cachep);
8321
8322 qla_trace_uninit();
8323 return ret;
8324 }
8325
8326 /**
8327 * qla2x00_module_exit - Module cleanup.
8328 **/
8329 static void __exit
qla2x00_module_exit(void)8330 qla2x00_module_exit(void)
8331 {
8332 pci_unregister_driver(&qla2xxx_pci_driver);
8333 qla2x00_release_firmware();
8334 kmem_cache_destroy(ctx_cachep);
8335 fc_release_transport(qla2xxx_transport_vport_template);
8336 if (apidev_major >= 0)
8337 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8338 fc_release_transport(qla2xxx_transport_template);
8339 qlt_exit();
8340 kmem_cache_destroy(srb_cachep);
8341 qla_trace_uninit();
8342 }
8343
8344 module_init(qla2x00_module_init);
8345 module_exit(qla2x00_module_exit);
8346
8347 MODULE_AUTHOR("QLogic Corporation");
8348 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
8349 MODULE_LICENSE("GPL");
8350 MODULE_FIRMWARE(FW_FILE_ISP21XX);
8351 MODULE_FIRMWARE(FW_FILE_ISP22XX);
8352 MODULE_FIRMWARE(FW_FILE_ISP2300);
8353 MODULE_FIRMWARE(FW_FILE_ISP2322);
8354 MODULE_FIRMWARE(FW_FILE_ISP24XX);
8355 MODULE_FIRMWARE(FW_FILE_ISP25XX);
8356