1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Jie Qiu <jie.qiu@mediatek.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/debugfs.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel.h> 13 #include <linux/media-bus-format.h> 14 #include <linux/of.h> 15 #include <linux/of_graph.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/platform_device.h> 18 #include <linux/soc/mediatek/mtk-mmsys.h> 19 #include <linux/types.h> 20 21 #include <video/videomode.h> 22 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_bridge_connector.h> 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_edid.h> 28 #include <drm/drm_encoder.h> 29 #include <drm/drm_of.h> 30 31 #include "mtk_ddp_comp.h" 32 #include "mtk_disp_drv.h" 33 #include "mtk_dpi_regs.h" 34 #include "mtk_drm_drv.h" 35 36 enum mtk_dpi_out_bit_num { 37 MTK_DPI_OUT_BIT_NUM_8BITS, 38 MTK_DPI_OUT_BIT_NUM_10BITS, 39 MTK_DPI_OUT_BIT_NUM_12BITS, 40 MTK_DPI_OUT_BIT_NUM_16BITS 41 }; 42 43 enum mtk_dpi_out_yc_map { 44 MTK_DPI_OUT_YC_MAP_RGB, 45 MTK_DPI_OUT_YC_MAP_CYCY, 46 MTK_DPI_OUT_YC_MAP_YCYC, 47 MTK_DPI_OUT_YC_MAP_CY, 48 MTK_DPI_OUT_YC_MAP_YC 49 }; 50 51 enum mtk_dpi_out_channel_swap { 52 MTK_DPI_OUT_CHANNEL_SWAP_RGB, 53 MTK_DPI_OUT_CHANNEL_SWAP_GBR, 54 MTK_DPI_OUT_CHANNEL_SWAP_BRG, 55 MTK_DPI_OUT_CHANNEL_SWAP_RBG, 56 MTK_DPI_OUT_CHANNEL_SWAP_GRB, 57 MTK_DPI_OUT_CHANNEL_SWAP_BGR 58 }; 59 60 enum mtk_dpi_out_color_format { 61 MTK_DPI_COLOR_FORMAT_RGB, 62 MTK_DPI_COLOR_FORMAT_YCBCR_422, 63 MTK_DPI_COLOR_FORMAT_YCBCR_444 64 }; 65 66 struct mtk_dpi { 67 struct drm_encoder encoder; 68 struct drm_bridge bridge; 69 struct drm_bridge *next_bridge; 70 struct drm_connector *connector; 71 void __iomem *regs; 72 struct device *dev; 73 struct device *mmsys_dev; 74 struct clk *engine_clk; 75 struct clk *pixel_clk; 76 struct clk *tvd_clk; 77 int irq; 78 struct drm_display_mode mode; 79 const struct mtk_dpi_conf *conf; 80 enum mtk_dpi_out_color_format color_format; 81 enum mtk_dpi_out_yc_map yc_map; 82 enum mtk_dpi_out_bit_num bit_num; 83 enum mtk_dpi_out_channel_swap channel_swap; 84 struct pinctrl *pinctrl; 85 struct pinctrl_state *pins_gpio; 86 struct pinctrl_state *pins_dpi; 87 u32 output_fmt; 88 int refcount; 89 }; 90 91 static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b) 92 { 93 return container_of(b, struct mtk_dpi, bridge); 94 } 95 96 enum mtk_dpi_polarity { 97 MTK_DPI_POLARITY_RISING, 98 MTK_DPI_POLARITY_FALLING, 99 }; 100 101 struct mtk_dpi_polarities { 102 enum mtk_dpi_polarity de_pol; 103 enum mtk_dpi_polarity ck_pol; 104 enum mtk_dpi_polarity hsync_pol; 105 enum mtk_dpi_polarity vsync_pol; 106 }; 107 108 struct mtk_dpi_sync_param { 109 u32 sync_width; 110 u32 front_porch; 111 u32 back_porch; 112 bool shift_half_line; 113 }; 114 115 struct mtk_dpi_yc_limit { 116 u16 y_top; 117 u16 y_bottom; 118 u16 c_top; 119 u16 c_bottom; 120 }; 121 122 struct mtk_dpi_factor { 123 u32 clock; 124 u8 factor; 125 }; 126 127 /** 128 * struct mtk_dpi_conf - Configuration of mediatek dpi. 129 * @dpi_factor: SoC-specific pixel clock PLL factor values. 130 * @num_dpi_factor: Number of pixel clock PLL factor values. 131 * @reg_h_fre_con: Register address of frequency control. 132 * @max_clock_khz: Max clock frequency supported for this SoCs in khz units. 133 * @edge_sel_en: Enable of edge selection. 134 * @output_fmts: Array of supported output formats. 135 * @num_output_fmts: Quantity of supported output formats. 136 * @is_ck_de_pol: Support CK/DE polarity. 137 * @swap_input_support: Support input swap function. 138 * @support_direct_pin: IP supports direct connection to dpi panels. 139 * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH 140 * (no shift). 141 * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). 142 * @channel_swap_shift: Shift value of channel swap. 143 * @yuv422_en_bit: Enable bit of yuv422. 144 * @csc_enable_bit: Enable bit of CSC. 145 * @input_2p_en_bit: Enable bit for input two pixel per round feature. 146 * If present, implies that the feature must be enabled. 147 * @pixels_per_iter: Quantity of transferred pixels per iteration. 148 * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS. 149 * @clocked_by_hdmi: HDMI IP outputs clock to dpi_pixel_clk input clock, needed 150 * for DPI registers access. 151 * @output_1pixel: Enable outputting one pixel per round; if the input is two pixel per 152 * round, the DPI hardware will internally transform it to 1T1P. 153 */ 154 struct mtk_dpi_conf { 155 const struct mtk_dpi_factor *dpi_factor; 156 const u8 num_dpi_factor; 157 u32 reg_h_fre_con; 158 u32 max_clock_khz; 159 bool edge_sel_en; 160 const u32 *output_fmts; 161 u32 num_output_fmts; 162 bool is_ck_de_pol; 163 bool swap_input_support; 164 bool support_direct_pin; 165 u32 dimension_mask; 166 u32 hvsize_mask; 167 u32 channel_swap_shift; 168 u32 yuv422_en_bit; 169 u32 csc_enable_bit; 170 u32 input_2p_en_bit; 171 u32 pixels_per_iter; 172 bool edge_cfg_in_mmsys; 173 bool clocked_by_hdmi; 174 bool output_1pixel; 175 }; 176 177 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) 178 { 179 u32 tmp = readl(dpi->regs + offset) & ~mask; 180 181 tmp |= (val & mask); 182 writel(tmp, dpi->regs + offset); 183 } 184 185 static void mtk_dpi_test_pattern_en(struct mtk_dpi *dpi, u8 type, bool enable) 186 { 187 u32 val; 188 189 if (enable) 190 val = FIELD_PREP(DPI_PAT_SEL, type) | DPI_PAT_EN; 191 else 192 val = 0; 193 194 mtk_dpi_mask(dpi, DPI_PATTERN0, val, DPI_PAT_SEL | DPI_PAT_EN); 195 } 196 197 static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset) 198 { 199 mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST); 200 } 201 202 static void mtk_dpi_enable(struct mtk_dpi *dpi) 203 { 204 mtk_dpi_mask(dpi, DPI_EN, EN, EN); 205 } 206 207 static void mtk_dpi_disable(struct mtk_dpi *dpi) 208 { 209 mtk_dpi_mask(dpi, DPI_EN, 0, EN); 210 } 211 212 static void mtk_dpi_config_hsync(struct mtk_dpi *dpi, 213 struct mtk_dpi_sync_param *sync) 214 { 215 mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW, 216 dpi->conf->dimension_mask << HPW); 217 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->back_porch << HBP, 218 dpi->conf->dimension_mask << HBP); 219 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP, 220 dpi->conf->dimension_mask << HFP); 221 } 222 223 static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, 224 struct mtk_dpi_sync_param *sync, 225 u32 width_addr, u32 porch_addr) 226 { 227 mtk_dpi_mask(dpi, width_addr, 228 sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, 229 VSYNC_HALF_LINE_MASK); 230 mtk_dpi_mask(dpi, width_addr, 231 sync->sync_width << VSYNC_WIDTH_SHIFT, 232 dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT); 233 mtk_dpi_mask(dpi, porch_addr, 234 sync->back_porch << VSYNC_BACK_PORCH_SHIFT, 235 dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT); 236 mtk_dpi_mask(dpi, porch_addr, 237 sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, 238 dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT); 239 } 240 241 static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, 242 struct mtk_dpi_sync_param *sync) 243 { 244 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH); 245 } 246 247 static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi, 248 struct mtk_dpi_sync_param *sync) 249 { 250 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN, 251 DPI_TGEN_VPORCH_LEVEN); 252 } 253 254 static void mtk_dpi_config_vsync_rodd(struct mtk_dpi *dpi, 255 struct mtk_dpi_sync_param *sync) 256 { 257 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_RODD, 258 DPI_TGEN_VPORCH_RODD); 259 } 260 261 static void mtk_dpi_config_vsync_reven(struct mtk_dpi *dpi, 262 struct mtk_dpi_sync_param *sync) 263 { 264 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_REVEN, 265 DPI_TGEN_VPORCH_REVEN); 266 } 267 268 static void mtk_dpi_config_pol(struct mtk_dpi *dpi, 269 struct mtk_dpi_polarities *dpi_pol) 270 { 271 unsigned int pol; 272 unsigned int mask; 273 274 mask = HSYNC_POL | VSYNC_POL; 275 pol = (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) | 276 (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL); 277 if (dpi->conf->is_ck_de_pol) { 278 mask |= CK_POL | DE_POL; 279 pol |= (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 280 0 : CK_POL) | 281 (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 282 0 : DE_POL); 283 } 284 285 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask); 286 } 287 288 static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) 289 { 290 mtk_dpi_mask(dpi, DPI_CON, en_3d ? TDFP_EN : 0, TDFP_EN); 291 } 292 293 static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter) 294 { 295 mtk_dpi_mask(dpi, DPI_CON, inter ? INTL_EN : 0, INTL_EN); 296 } 297 298 static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) 299 { 300 mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, 301 dpi->conf->hvsize_mask << HSIZE); 302 mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, 303 dpi->conf->hvsize_mask << VSIZE); 304 } 305 306 static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) 307 { 308 struct mtk_dpi_yc_limit limit; 309 310 if (drm_default_rgb_quant_range(&dpi->mode) == 311 HDMI_QUANTIZATION_RANGE_LIMITED) { 312 limit.y_bottom = 0x10; 313 limit.y_top = 0xfe0; 314 limit.c_bottom = 0x10; 315 limit.c_top = 0xfe0; 316 } else { 317 limit.y_bottom = 0; 318 limit.y_top = 0xfff; 319 limit.c_bottom = 0; 320 limit.c_top = 0xfff; 321 } 322 323 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_bottom << Y_LIMINT_BOT, 324 Y_LIMINT_BOT_MASK); 325 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_top << Y_LIMINT_TOP, 326 Y_LIMINT_TOP_MASK); 327 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_bottom << C_LIMIT_BOT, 328 C_LIMIT_BOT_MASK); 329 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_top << C_LIMIT_TOP, 330 C_LIMIT_TOP_MASK); 331 } 332 333 static void mtk_dpi_config_bit_num(struct mtk_dpi *dpi, 334 enum mtk_dpi_out_bit_num num) 335 { 336 u32 val; 337 338 switch (num) { 339 case MTK_DPI_OUT_BIT_NUM_8BITS: 340 val = OUT_BIT_8; 341 break; 342 case MTK_DPI_OUT_BIT_NUM_10BITS: 343 val = OUT_BIT_10; 344 break; 345 case MTK_DPI_OUT_BIT_NUM_12BITS: 346 val = OUT_BIT_12; 347 break; 348 case MTK_DPI_OUT_BIT_NUM_16BITS: 349 val = OUT_BIT_16; 350 break; 351 default: 352 val = OUT_BIT_8; 353 break; 354 } 355 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << OUT_BIT, 356 OUT_BIT_MASK); 357 } 358 359 static void mtk_dpi_config_yc_map(struct mtk_dpi *dpi, 360 enum mtk_dpi_out_yc_map map) 361 { 362 u32 val; 363 364 switch (map) { 365 case MTK_DPI_OUT_YC_MAP_RGB: 366 val = YC_MAP_RGB; 367 break; 368 case MTK_DPI_OUT_YC_MAP_CYCY: 369 val = YC_MAP_CYCY; 370 break; 371 case MTK_DPI_OUT_YC_MAP_YCYC: 372 val = YC_MAP_YCYC; 373 break; 374 case MTK_DPI_OUT_YC_MAP_CY: 375 val = YC_MAP_CY; 376 break; 377 case MTK_DPI_OUT_YC_MAP_YC: 378 val = YC_MAP_YC; 379 break; 380 default: 381 val = YC_MAP_RGB; 382 break; 383 } 384 385 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << YC_MAP, YC_MAP_MASK); 386 } 387 388 static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi, 389 enum mtk_dpi_out_channel_swap swap) 390 { 391 u32 val; 392 393 switch (swap) { 394 case MTK_DPI_OUT_CHANNEL_SWAP_RGB: 395 val = SWAP_RGB; 396 break; 397 case MTK_DPI_OUT_CHANNEL_SWAP_GBR: 398 val = SWAP_GBR; 399 break; 400 case MTK_DPI_OUT_CHANNEL_SWAP_BRG: 401 val = SWAP_BRG; 402 break; 403 case MTK_DPI_OUT_CHANNEL_SWAP_RBG: 404 val = SWAP_RBG; 405 break; 406 case MTK_DPI_OUT_CHANNEL_SWAP_GRB: 407 val = SWAP_GRB; 408 break; 409 case MTK_DPI_OUT_CHANNEL_SWAP_BGR: 410 val = SWAP_BGR; 411 break; 412 default: 413 val = SWAP_RGB; 414 break; 415 } 416 417 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, 418 val << dpi->conf->channel_swap_shift, 419 CH_SWAP_MASK << dpi->conf->channel_swap_shift); 420 } 421 422 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) 423 { 424 mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0, 425 dpi->conf->yuv422_en_bit); 426 } 427 428 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) 429 { 430 mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->csc_enable_bit : 0, 431 dpi->conf->csc_enable_bit); 432 } 433 434 static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable) 435 { 436 mtk_dpi_mask(dpi, DPI_CON, enable ? IN_RB_SWAP : 0, IN_RB_SWAP); 437 } 438 439 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi) 440 { 441 if (dpi->conf->reg_h_fre_con) 442 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N); 443 } 444 445 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) 446 { 447 if (dpi->conf->edge_sel_en && dpi->conf->reg_h_fre_con) 448 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); 449 } 450 451 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, 452 enum mtk_dpi_out_color_format format) 453 { 454 mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); 455 456 switch (format) { 457 case MTK_DPI_COLOR_FORMAT_YCBCR_444: 458 mtk_dpi_config_yuv422_enable(dpi, false); 459 mtk_dpi_config_csc_enable(dpi, true); 460 if (dpi->conf->swap_input_support) 461 mtk_dpi_config_swap_input(dpi, false); 462 break; 463 case MTK_DPI_COLOR_FORMAT_YCBCR_422: 464 mtk_dpi_config_yuv422_enable(dpi, true); 465 mtk_dpi_config_csc_enable(dpi, true); 466 467 /* 468 * If height is smaller than 720, we need to use RGB_TO_BT601 469 * to transfer to yuv422. Otherwise, we use RGB_TO_JPEG. 470 */ 471 mtk_dpi_mask(dpi, DPI_MATRIX_SET, dpi->mode.hdisplay <= 720 ? 472 MATRIX_SEL_RGB_TO_BT601 : MATRIX_SEL_RGB_TO_JPEG, 473 INT_MATRIX_SEL_MASK); 474 break; 475 default: 476 case MTK_DPI_COLOR_FORMAT_RGB: 477 mtk_dpi_config_yuv422_enable(dpi, false); 478 mtk_dpi_config_csc_enable(dpi, false); 479 if (dpi->conf->swap_input_support) 480 mtk_dpi_config_swap_input(dpi, false); 481 break; 482 } 483 } 484 485 static void mtk_dpi_dual_edge(struct mtk_dpi *dpi) 486 { 487 if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || 488 (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) { 489 mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 490 DDR_EN | DDR_4PHASE); 491 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, 492 dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE ? 493 EDGE_SEL : 0, EDGE_SEL); 494 if (dpi->conf->edge_cfg_in_mmsys) 495 mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev, MTK_DPI_RGB888_DDR_CON); 496 } else { 497 mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 0); 498 if (dpi->conf->edge_cfg_in_mmsys) 499 mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev, MTK_DPI_RGB888_SDR_CON); 500 } 501 } 502 503 static void mtk_dpi_power_off(struct mtk_dpi *dpi) 504 { 505 if (WARN_ON(dpi->refcount == 0)) 506 return; 507 508 if (--dpi->refcount != 0) 509 return; 510 511 mtk_dpi_disable(dpi); 512 clk_disable_unprepare(dpi->pixel_clk); 513 clk_disable_unprepare(dpi->tvd_clk); 514 clk_disable_unprepare(dpi->engine_clk); 515 } 516 517 static int mtk_dpi_power_on(struct mtk_dpi *dpi) 518 { 519 int ret; 520 521 if (++dpi->refcount != 1) 522 return 0; 523 524 ret = clk_prepare_enable(dpi->engine_clk); 525 if (ret) { 526 dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); 527 goto err_refcount; 528 } 529 530 ret = clk_prepare_enable(dpi->tvd_clk); 531 if (ret) { 532 dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); 533 goto err_engine; 534 } 535 536 ret = clk_prepare_enable(dpi->pixel_clk); 537 if (ret) { 538 dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); 539 goto err_pixel; 540 } 541 542 return 0; 543 544 err_pixel: 545 clk_disable_unprepare(dpi->tvd_clk); 546 err_engine: 547 clk_disable_unprepare(dpi->engine_clk); 548 err_refcount: 549 dpi->refcount--; 550 return ret; 551 } 552 553 static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode_clk) 554 { 555 const struct mtk_dpi_factor *dpi_factor = dpi->conf->dpi_factor; 556 int i; 557 558 for (i = 0; i < dpi->conf->num_dpi_factor; i++) { 559 if (mode_clk <= dpi_factor[i].clock) 560 return dpi_factor[i].factor; 561 } 562 563 /* If no match try the lowest possible factor */ 564 return dpi_factor[dpi->conf->num_dpi_factor - 1].factor; 565 } 566 567 static void mtk_dpi_set_pixel_clk(struct mtk_dpi *dpi, struct videomode *vm, int mode_clk) 568 { 569 unsigned long pll_rate; 570 unsigned int factor; 571 572 /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ 573 factor = mtk_dpi_calculate_factor(dpi, mode_clk); 574 pll_rate = vm->pixelclock * factor; 575 576 dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", 577 pll_rate, vm->pixelclock); 578 579 clk_set_rate(dpi->tvd_clk, pll_rate); 580 pll_rate = clk_get_rate(dpi->tvd_clk); 581 582 /* 583 * Depending on the IP version, we may output a different amount of 584 * pixels for each iteration: divide the clock by this number and 585 * adjust the display porches accordingly. 586 */ 587 vm->pixelclock = pll_rate / factor; 588 vm->pixelclock /= dpi->conf->pixels_per_iter; 589 590 if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || 591 (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) 592 clk_set_rate(dpi->pixel_clk, vm->pixelclock * 2); 593 else 594 clk_set_rate(dpi->pixel_clk, vm->pixelclock); 595 596 vm->pixelclock = clk_get_rate(dpi->pixel_clk); 597 598 dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", 599 pll_rate, vm->pixelclock); 600 } 601 602 static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, 603 struct drm_display_mode *mode) 604 { 605 struct mtk_dpi_polarities dpi_pol; 606 struct mtk_dpi_sync_param hsync; 607 struct mtk_dpi_sync_param vsync_lodd = { 0 }; 608 struct mtk_dpi_sync_param vsync_leven = { 0 }; 609 struct mtk_dpi_sync_param vsync_rodd = { 0 }; 610 struct mtk_dpi_sync_param vsync_reven = { 0 }; 611 struct videomode vm = { 0 }; 612 613 drm_display_mode_to_videomode(mode, &vm); 614 615 if (!dpi->conf->clocked_by_hdmi) 616 mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock); 617 618 dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; 619 dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; 620 dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? 621 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; 622 dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? 623 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; 624 625 /* 626 * Depending on the IP version, we may output a different amount of 627 * pixels for each iteration: divide the clock by this number and 628 * adjust the display porches accordingly. 629 */ 630 hsync.sync_width = vm.hsync_len / dpi->conf->pixels_per_iter; 631 hsync.back_porch = vm.hback_porch / dpi->conf->pixels_per_iter; 632 hsync.front_porch = vm.hfront_porch / dpi->conf->pixels_per_iter; 633 634 hsync.shift_half_line = false; 635 vsync_lodd.sync_width = vm.vsync_len; 636 vsync_lodd.back_porch = vm.vback_porch; 637 vsync_lodd.front_porch = vm.vfront_porch; 638 vsync_lodd.shift_half_line = false; 639 640 if (vm.flags & DISPLAY_FLAGS_INTERLACED && 641 mode->flags & DRM_MODE_FLAG_3D_MASK) { 642 vsync_leven = vsync_lodd; 643 vsync_rodd = vsync_lodd; 644 vsync_reven = vsync_lodd; 645 vsync_leven.shift_half_line = true; 646 vsync_reven.shift_half_line = true; 647 } else if (vm.flags & DISPLAY_FLAGS_INTERLACED && 648 !(mode->flags & DRM_MODE_FLAG_3D_MASK)) { 649 vsync_leven = vsync_lodd; 650 vsync_leven.shift_half_line = true; 651 } else if (!(vm.flags & DISPLAY_FLAGS_INTERLACED) && 652 mode->flags & DRM_MODE_FLAG_3D_MASK) { 653 vsync_rodd = vsync_lodd; 654 } 655 mtk_dpi_sw_reset(dpi, true); 656 mtk_dpi_config_pol(dpi, &dpi_pol); 657 658 mtk_dpi_config_hsync(dpi, &hsync); 659 mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd); 660 mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd); 661 mtk_dpi_config_vsync_leven(dpi, &vsync_leven); 662 mtk_dpi_config_vsync_reven(dpi, &vsync_reven); 663 664 mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK)); 665 mtk_dpi_config_interface(dpi, !!(vm.flags & 666 DISPLAY_FLAGS_INTERLACED)); 667 if (vm.flags & DISPLAY_FLAGS_INTERLACED) 668 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive >> 1); 669 else 670 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); 671 672 mtk_dpi_config_channel_limit(dpi); 673 mtk_dpi_config_bit_num(dpi, dpi->bit_num); 674 mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); 675 mtk_dpi_config_color_format(dpi, dpi->color_format); 676 if (dpi->conf->support_direct_pin) { 677 mtk_dpi_config_yc_map(dpi, dpi->yc_map); 678 mtk_dpi_config_2n_h_fre(dpi); 679 680 /* DPI can connect to either an external bridge or the internal HDMI encoder */ 681 if (dpi->conf->output_1pixel) 682 mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN); 683 else 684 mtk_dpi_dual_edge(dpi); 685 686 mtk_dpi_config_disable_edge(dpi); 687 } 688 if (dpi->conf->input_2p_en_bit) { 689 mtk_dpi_mask(dpi, DPI_CON, dpi->conf->input_2p_en_bit, 690 dpi->conf->input_2p_en_bit); 691 } 692 mtk_dpi_sw_reset(dpi, false); 693 694 return 0; 695 } 696 697 static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 698 struct drm_bridge_state *bridge_state, 699 struct drm_crtc_state *crtc_state, 700 struct drm_connector_state *conn_state, 701 unsigned int *num_output_fmts) 702 { 703 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 704 u32 *output_fmts; 705 706 *num_output_fmts = 0; 707 708 if (!dpi->conf->output_fmts) { 709 dev_err(dpi->dev, "output_fmts should not be null\n"); 710 return NULL; 711 } 712 713 output_fmts = kcalloc(dpi->conf->num_output_fmts, sizeof(*output_fmts), 714 GFP_KERNEL); 715 if (!output_fmts) 716 return NULL; 717 718 *num_output_fmts = dpi->conf->num_output_fmts; 719 720 memcpy(output_fmts, dpi->conf->output_fmts, 721 sizeof(*output_fmts) * dpi->conf->num_output_fmts); 722 723 return output_fmts; 724 } 725 726 static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 727 struct drm_bridge_state *bridge_state, 728 struct drm_crtc_state *crtc_state, 729 struct drm_connector_state *conn_state, 730 u32 output_fmt, 731 unsigned int *num_input_fmts) 732 { 733 u32 *input_fmts; 734 735 *num_input_fmts = 0; 736 737 input_fmts = kcalloc(1, sizeof(*input_fmts), 738 GFP_KERNEL); 739 if (!input_fmts) 740 return NULL; 741 742 *num_input_fmts = 1; 743 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 744 745 return input_fmts; 746 } 747 748 static unsigned int mtk_dpi_bus_fmt_bit_num(unsigned int out_bus_format) 749 { 750 switch (out_bus_format) { 751 default: 752 case MEDIA_BUS_FMT_RGB888_1X24: 753 case MEDIA_BUS_FMT_BGR888_1X24: 754 case MEDIA_BUS_FMT_RGB888_2X12_LE: 755 case MEDIA_BUS_FMT_RGB888_2X12_BE: 756 case MEDIA_BUS_FMT_YUYV8_1X16: 757 case MEDIA_BUS_FMT_YUV8_1X24: 758 return MTK_DPI_OUT_BIT_NUM_8BITS; 759 case MEDIA_BUS_FMT_RGB101010_1X30: 760 case MEDIA_BUS_FMT_YUYV10_1X20: 761 case MEDIA_BUS_FMT_YUV10_1X30: 762 return MTK_DPI_OUT_BIT_NUM_10BITS; 763 case MEDIA_BUS_FMT_YUYV12_1X24: 764 return MTK_DPI_OUT_BIT_NUM_12BITS; 765 } 766 } 767 768 static unsigned int mtk_dpi_bus_fmt_channel_swap(unsigned int out_bus_format) 769 { 770 switch (out_bus_format) { 771 default: 772 case MEDIA_BUS_FMT_RGB888_1X24: 773 case MEDIA_BUS_FMT_RGB888_2X12_LE: 774 case MEDIA_BUS_FMT_RGB888_2X12_BE: 775 case MEDIA_BUS_FMT_RGB101010_1X30: 776 case MEDIA_BUS_FMT_YUYV8_1X16: 777 case MEDIA_BUS_FMT_YUYV10_1X20: 778 case MEDIA_BUS_FMT_YUYV12_1X24: 779 return MTK_DPI_OUT_CHANNEL_SWAP_RGB; 780 case MEDIA_BUS_FMT_BGR888_1X24: 781 case MEDIA_BUS_FMT_YUV8_1X24: 782 case MEDIA_BUS_FMT_YUV10_1X30: 783 return MTK_DPI_OUT_CHANNEL_SWAP_BGR; 784 } 785 } 786 787 static unsigned int mtk_dpi_bus_fmt_color_format(unsigned int out_bus_format) 788 { 789 switch (out_bus_format) { 790 default: 791 case MEDIA_BUS_FMT_RGB888_1X24: 792 case MEDIA_BUS_FMT_BGR888_1X24: 793 case MEDIA_BUS_FMT_RGB888_2X12_LE: 794 case MEDIA_BUS_FMT_RGB888_2X12_BE: 795 case MEDIA_BUS_FMT_RGB101010_1X30: 796 return MTK_DPI_COLOR_FORMAT_RGB; 797 case MEDIA_BUS_FMT_YUYV8_1X16: 798 case MEDIA_BUS_FMT_YUYV10_1X20: 799 case MEDIA_BUS_FMT_YUYV12_1X24: 800 return MTK_DPI_COLOR_FORMAT_YCBCR_422; 801 case MEDIA_BUS_FMT_YUV8_1X24: 802 case MEDIA_BUS_FMT_YUV10_1X30: 803 return MTK_DPI_COLOR_FORMAT_YCBCR_444; 804 } 805 } 806 807 static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge, 808 struct drm_bridge_state *bridge_state, 809 struct drm_crtc_state *crtc_state, 810 struct drm_connector_state *conn_state) 811 { 812 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 813 unsigned int out_bus_format; 814 815 out_bus_format = bridge_state->output_bus_cfg.format; 816 817 if (out_bus_format == MEDIA_BUS_FMT_FIXED) 818 if (dpi->conf->num_output_fmts) 819 out_bus_format = dpi->conf->output_fmts[0]; 820 821 dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n", 822 bridge_state->input_bus_cfg.format, 823 bridge_state->output_bus_cfg.format); 824 825 dpi->output_fmt = out_bus_format; 826 dpi->bit_num = mtk_dpi_bus_fmt_bit_num(out_bus_format); 827 dpi->channel_swap = mtk_dpi_bus_fmt_channel_swap(out_bus_format); 828 dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; 829 dpi->color_format = mtk_dpi_bus_fmt_color_format(out_bus_format); 830 831 return 0; 832 } 833 834 static int mtk_dpi_bridge_attach(struct drm_bridge *bridge, 835 struct drm_encoder *encoder, 836 enum drm_bridge_attach_flags flags) 837 { 838 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 839 840 return drm_bridge_attach(encoder, dpi->next_bridge, 841 &dpi->bridge, flags); 842 } 843 844 static void mtk_dpi_bridge_mode_set(struct drm_bridge *bridge, 845 const struct drm_display_mode *mode, 846 const struct drm_display_mode *adjusted_mode) 847 { 848 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 849 850 drm_mode_copy(&dpi->mode, adjusted_mode); 851 } 852 853 static void mtk_dpi_bridge_disable(struct drm_bridge *bridge) 854 { 855 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 856 857 mtk_dpi_power_off(dpi); 858 859 if (dpi->pinctrl && dpi->pins_gpio) 860 pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio); 861 } 862 863 static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) 864 { 865 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 866 867 if (dpi->pinctrl && dpi->pins_dpi) 868 pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi); 869 870 mtk_dpi_power_on(dpi); 871 mtk_dpi_set_display_mode(dpi, &dpi->mode); 872 mtk_dpi_enable(dpi); 873 } 874 875 static enum drm_mode_status 876 mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, 877 const struct drm_display_info *info, 878 const struct drm_display_mode *mode) 879 { 880 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 881 882 if (mode->clock > dpi->conf->max_clock_khz) 883 return MODE_CLOCK_HIGH; 884 885 return MODE_OK; 886 } 887 888 static int mtk_dpi_debug_tp_show(struct seq_file *m, void *arg) 889 { 890 struct mtk_dpi *dpi = m->private; 891 bool en; 892 u32 val; 893 894 if (!dpi) 895 return -EINVAL; 896 897 val = readl(dpi->regs + DPI_PATTERN0); 898 en = val & DPI_PAT_EN; 899 val = FIELD_GET(DPI_PAT_SEL, val); 900 901 seq_printf(m, "DPI Test Pattern: %s\n", en ? "Enabled" : "Disabled"); 902 903 if (en) { 904 seq_printf(m, "Internal pattern %d: ", val); 905 switch (val) { 906 case 0: 907 seq_puts(m, "256 Vertical Gray\n"); 908 break; 909 case 1: 910 seq_puts(m, "1024 Vertical Gray\n"); 911 break; 912 case 2: 913 seq_puts(m, "256 Horizontal Gray\n"); 914 break; 915 case 3: 916 seq_puts(m, "1024 Horizontal Gray\n"); 917 break; 918 case 4: 919 seq_puts(m, "Vertical Color bars\n"); 920 break; 921 case 6: 922 seq_puts(m, "Frame border\n"); 923 break; 924 case 7: 925 seq_puts(m, "Dot moire\n"); 926 break; 927 default: 928 seq_puts(m, "Invalid selection\n"); 929 break; 930 } 931 } 932 933 return 0; 934 } 935 936 static ssize_t mtk_dpi_debug_tp_write(struct file *file, const char __user *ubuf, 937 size_t len, loff_t *offp) 938 { 939 struct seq_file *m = file->private_data; 940 u32 en, type; 941 char buf[6]; 942 943 if (!m || !m->private || *offp || len > sizeof(buf) - 1) 944 return -EINVAL; 945 946 memset(buf, 0, sizeof(buf)); 947 if (copy_from_user(buf, ubuf, len)) 948 return -EFAULT; 949 950 if (sscanf(buf, "%u %u", &en, &type) != 2) 951 return -EINVAL; 952 953 if (en < 0 || en > 1 || type < 0 || type > 7) 954 return -EINVAL; 955 956 mtk_dpi_test_pattern_en((struct mtk_dpi *)m->private, type, en); 957 return len; 958 } 959 960 static int mtk_dpi_debug_tp_open(struct inode *inode, struct file *file) 961 { 962 return single_open(file, mtk_dpi_debug_tp_show, inode->i_private); 963 } 964 965 static const struct file_operations mtk_dpi_debug_tp_fops = { 966 .owner = THIS_MODULE, 967 .open = mtk_dpi_debug_tp_open, 968 .read = seq_read, 969 .write = mtk_dpi_debug_tp_write, 970 .llseek = seq_lseek, 971 .release = single_release, 972 }; 973 974 static void mtk_dpi_debugfs_init(struct drm_bridge *bridge, struct dentry *root) 975 { 976 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 977 978 debugfs_create_file("dpi_test_pattern", 0640, root, dpi, &mtk_dpi_debug_tp_fops); 979 } 980 981 static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { 982 .attach = mtk_dpi_bridge_attach, 983 .mode_set = mtk_dpi_bridge_mode_set, 984 .mode_valid = mtk_dpi_bridge_mode_valid, 985 .disable = mtk_dpi_bridge_disable, 986 .enable = mtk_dpi_bridge_enable, 987 .atomic_check = mtk_dpi_bridge_atomic_check, 988 .atomic_get_output_bus_fmts = mtk_dpi_bridge_atomic_get_output_bus_fmts, 989 .atomic_get_input_bus_fmts = mtk_dpi_bridge_atomic_get_input_bus_fmts, 990 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 991 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 992 .atomic_reset = drm_atomic_helper_bridge_reset, 993 .debugfs_init = mtk_dpi_debugfs_init, 994 }; 995 996 static const struct drm_encoder_funcs mtk_dpi_encoder_funcs = { 997 .destroy = drm_encoder_cleanup, 998 }; 999 1000 void mtk_dpi_start(struct device *dev) 1001 { 1002 struct mtk_dpi *dpi = dev_get_drvdata(dev); 1003 1004 if (!dpi->conf->clocked_by_hdmi) 1005 mtk_dpi_power_on(dpi); 1006 } 1007 1008 void mtk_dpi_stop(struct device *dev) 1009 { 1010 struct mtk_dpi *dpi = dev_get_drvdata(dev); 1011 1012 if (!dpi->conf->clocked_by_hdmi) 1013 mtk_dpi_power_off(dpi); 1014 } 1015 1016 unsigned int mtk_dpi_encoder_index(struct device *dev) 1017 { 1018 struct mtk_dpi *dpi = dev_get_drvdata(dev); 1019 unsigned int encoder_index = drm_encoder_index(&dpi->encoder); 1020 1021 dev_dbg(dev, "encoder index:%d\n", encoder_index); 1022 return encoder_index; 1023 } 1024 1025 static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) 1026 { 1027 struct mtk_dpi *dpi = dev_get_drvdata(dev); 1028 struct drm_device *drm_dev = data; 1029 struct mtk_drm_private *priv = drm_dev->dev_private; 1030 int ret; 1031 1032 dpi->mmsys_dev = priv->mmsys_dev; 1033 ret = drm_encoder_init(drm_dev, &dpi->encoder, &mtk_dpi_encoder_funcs, 1034 DRM_MODE_ENCODER_TMDS, NULL); 1035 if (ret) { 1036 dev_err(dev, "Failed to initialize decoder: %d\n", ret); 1037 return ret; 1038 } 1039 1040 ret = mtk_find_possible_crtcs(drm_dev, dpi->dev); 1041 if (ret < 0) 1042 goto err_cleanup; 1043 dpi->encoder.possible_crtcs = ret; 1044 1045 ret = drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL, 1046 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 1047 if (ret) 1048 goto err_cleanup; 1049 1050 dpi->connector = drm_bridge_connector_init(drm_dev, &dpi->encoder); 1051 if (IS_ERR(dpi->connector)) { 1052 dev_err(dev, "Unable to create bridge connector\n"); 1053 ret = PTR_ERR(dpi->connector); 1054 goto err_cleanup; 1055 } 1056 1057 return 0; 1058 1059 err_cleanup: 1060 drm_encoder_cleanup(&dpi->encoder); 1061 return ret; 1062 } 1063 1064 static void mtk_dpi_unbind(struct device *dev, struct device *master, 1065 void *data) 1066 { 1067 struct mtk_dpi *dpi = dev_get_drvdata(dev); 1068 1069 drm_encoder_cleanup(&dpi->encoder); 1070 } 1071 1072 static const struct component_ops mtk_dpi_component_ops = { 1073 .bind = mtk_dpi_bind, 1074 .unbind = mtk_dpi_unbind, 1075 }; 1076 1077 static const u32 mt8173_output_fmts[] = { 1078 MEDIA_BUS_FMT_RGB888_1X24, 1079 }; 1080 1081 static const u32 mt8183_output_fmts[] = { 1082 MEDIA_BUS_FMT_RGB888_2X12_LE, 1083 MEDIA_BUS_FMT_RGB888_2X12_BE, 1084 }; 1085 1086 static const u32 mt8195_dpi_output_fmts[] = { 1087 MEDIA_BUS_FMT_RGB888_1X24, 1088 MEDIA_BUS_FMT_RGB888_2X12_LE, 1089 MEDIA_BUS_FMT_RGB888_2X12_BE, 1090 MEDIA_BUS_FMT_RGB101010_1X30, 1091 MEDIA_BUS_FMT_YUYV8_1X16, 1092 MEDIA_BUS_FMT_YUYV10_1X20, 1093 MEDIA_BUS_FMT_YUYV12_1X24, 1094 MEDIA_BUS_FMT_BGR888_1X24, 1095 MEDIA_BUS_FMT_YUV8_1X24, 1096 MEDIA_BUS_FMT_YUV10_1X30, 1097 }; 1098 1099 static const u32 mt8195_dp_intf_output_fmts[] = { 1100 MEDIA_BUS_FMT_RGB888_1X24, 1101 MEDIA_BUS_FMT_RGB888_2X12_LE, 1102 MEDIA_BUS_FMT_RGB888_2X12_BE, 1103 MEDIA_BUS_FMT_RGB101010_1X30, 1104 MEDIA_BUS_FMT_YUYV8_1X16, 1105 MEDIA_BUS_FMT_YUYV10_1X20, 1106 MEDIA_BUS_FMT_BGR888_1X24, 1107 MEDIA_BUS_FMT_YUV8_1X24, 1108 MEDIA_BUS_FMT_YUV10_1X30, 1109 }; 1110 1111 static const struct mtk_dpi_factor dpi_factor_mt2701[] = { 1112 { 64000, 4 }, { 128000, 2 }, { U32_MAX, 1 } 1113 }; 1114 1115 static const struct mtk_dpi_factor dpi_factor_mt8173[] = { 1116 { 27000, 48 }, { 84000, 24 }, { 167000, 12 }, { U32_MAX, 6 } 1117 }; 1118 1119 static const struct mtk_dpi_factor dpi_factor_mt8183[] = { 1120 { 27000, 8 }, { 167000, 4 }, { U32_MAX, 2 } 1121 }; 1122 1123 static const struct mtk_dpi_factor dpi_factor_mt8195_dp_intf[] = { 1124 { 70000 - 1, 4 }, { 200000 - 1, 2 }, { U32_MAX, 1 } 1125 }; 1126 1127 static const struct mtk_dpi_conf mt8173_conf = { 1128 .dpi_factor = dpi_factor_mt8173, 1129 .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8173), 1130 .reg_h_fre_con = 0xe0, 1131 .max_clock_khz = 300000, 1132 .output_fmts = mt8173_output_fmts, 1133 .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), 1134 .pixels_per_iter = 1, 1135 .is_ck_de_pol = true, 1136 .swap_input_support = true, 1137 .support_direct_pin = true, 1138 .dimension_mask = HPW_MASK, 1139 .hvsize_mask = HSIZE_MASK, 1140 .channel_swap_shift = CH_SWAP, 1141 .yuv422_en_bit = YUV422_EN, 1142 .csc_enable_bit = CSC_ENABLE, 1143 }; 1144 1145 static const struct mtk_dpi_conf mt2701_conf = { 1146 .dpi_factor = dpi_factor_mt2701, 1147 .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt2701), 1148 .reg_h_fre_con = 0xb0, 1149 .edge_sel_en = true, 1150 .max_clock_khz = 150000, 1151 .output_fmts = mt8173_output_fmts, 1152 .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), 1153 .pixels_per_iter = 1, 1154 .is_ck_de_pol = true, 1155 .swap_input_support = true, 1156 .support_direct_pin = true, 1157 .dimension_mask = HPW_MASK, 1158 .hvsize_mask = HSIZE_MASK, 1159 .channel_swap_shift = CH_SWAP, 1160 .yuv422_en_bit = YUV422_EN, 1161 .csc_enable_bit = CSC_ENABLE, 1162 }; 1163 1164 static const struct mtk_dpi_conf mt8183_conf = { 1165 .dpi_factor = dpi_factor_mt8183, 1166 .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183), 1167 .reg_h_fre_con = 0xe0, 1168 .max_clock_khz = 100000, 1169 .output_fmts = mt8183_output_fmts, 1170 .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), 1171 .pixels_per_iter = 1, 1172 .is_ck_de_pol = true, 1173 .swap_input_support = true, 1174 .support_direct_pin = true, 1175 .dimension_mask = HPW_MASK, 1176 .hvsize_mask = HSIZE_MASK, 1177 .channel_swap_shift = CH_SWAP, 1178 .yuv422_en_bit = YUV422_EN, 1179 .csc_enable_bit = CSC_ENABLE, 1180 }; 1181 1182 static const struct mtk_dpi_conf mt8186_conf = { 1183 .dpi_factor = dpi_factor_mt8183, 1184 .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183), 1185 .reg_h_fre_con = 0xe0, 1186 .max_clock_khz = 150000, 1187 .output_fmts = mt8183_output_fmts, 1188 .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), 1189 .edge_cfg_in_mmsys = true, 1190 .pixels_per_iter = 1, 1191 .is_ck_de_pol = true, 1192 .swap_input_support = true, 1193 .support_direct_pin = true, 1194 .dimension_mask = HPW_MASK, 1195 .hvsize_mask = HSIZE_MASK, 1196 .channel_swap_shift = CH_SWAP, 1197 .yuv422_en_bit = YUV422_EN, 1198 .csc_enable_bit = CSC_ENABLE, 1199 }; 1200 1201 static const struct mtk_dpi_conf mt8192_conf = { 1202 .dpi_factor = dpi_factor_mt8183, 1203 .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183), 1204 .reg_h_fre_con = 0xe0, 1205 .max_clock_khz = 150000, 1206 .output_fmts = mt8183_output_fmts, 1207 .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), 1208 .pixels_per_iter = 1, 1209 .is_ck_de_pol = true, 1210 .swap_input_support = true, 1211 .support_direct_pin = true, 1212 .dimension_mask = HPW_MASK, 1213 .hvsize_mask = HSIZE_MASK, 1214 .channel_swap_shift = CH_SWAP, 1215 .yuv422_en_bit = YUV422_EN, 1216 .csc_enable_bit = CSC_ENABLE, 1217 }; 1218 1219 static const struct mtk_dpi_conf mt8195_conf = { 1220 .max_clock_khz = 594000, 1221 .output_fmts = mt8195_dpi_output_fmts, 1222 .num_output_fmts = ARRAY_SIZE(mt8195_dpi_output_fmts), 1223 .pixels_per_iter = 1, 1224 .is_ck_de_pol = true, 1225 .swap_input_support = true, 1226 .support_direct_pin = true, 1227 .dimension_mask = HPW_MASK, 1228 .hvsize_mask = HSIZE_MASK, 1229 .channel_swap_shift = CH_SWAP, 1230 .yuv422_en_bit = YUV422_EN, 1231 .csc_enable_bit = CSC_ENABLE, 1232 .input_2p_en_bit = DPI_INPUT_2P_EN, 1233 .clocked_by_hdmi = true, 1234 .output_1pixel = true, 1235 }; 1236 1237 static const struct mtk_dpi_conf mt8195_dpintf_conf = { 1238 .dpi_factor = dpi_factor_mt8195_dp_intf, 1239 .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf), 1240 .max_clock_khz = 600000, 1241 .output_fmts = mt8195_dp_intf_output_fmts, 1242 .num_output_fmts = ARRAY_SIZE(mt8195_dp_intf_output_fmts), 1243 .pixels_per_iter = 4, 1244 .dimension_mask = DPINTF_HPW_MASK, 1245 .hvsize_mask = DPINTF_HSIZE_MASK, 1246 .channel_swap_shift = DPINTF_CH_SWAP, 1247 .yuv422_en_bit = DPINTF_YUV422_EN, 1248 .csc_enable_bit = DPINTF_CSC_ENABLE, 1249 .input_2p_en_bit = DPINTF_INPUT_2P_EN, 1250 }; 1251 1252 static int mtk_dpi_probe(struct platform_device *pdev) 1253 { 1254 struct device *dev = &pdev->dev; 1255 struct mtk_dpi *dpi; 1256 int ret; 1257 1258 dpi = devm_drm_bridge_alloc(dev, struct mtk_dpi, bridge, 1259 &mtk_dpi_bridge_funcs); 1260 if (IS_ERR(dpi)) 1261 return PTR_ERR(dpi); 1262 1263 dpi->dev = dev; 1264 dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev); 1265 dpi->output_fmt = MEDIA_BUS_FMT_RGB888_1X24; 1266 1267 dpi->pinctrl = devm_pinctrl_get(&pdev->dev); 1268 if (IS_ERR(dpi->pinctrl)) { 1269 dpi->pinctrl = NULL; 1270 dev_dbg(&pdev->dev, "Cannot find pinctrl!\n"); 1271 } 1272 if (dpi->pinctrl) { 1273 dpi->pins_gpio = pinctrl_lookup_state(dpi->pinctrl, "sleep"); 1274 if (IS_ERR(dpi->pins_gpio)) { 1275 dpi->pins_gpio = NULL; 1276 dev_dbg(&pdev->dev, "Cannot find pinctrl idle!\n"); 1277 } 1278 if (dpi->pins_gpio) 1279 pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio); 1280 1281 dpi->pins_dpi = pinctrl_lookup_state(dpi->pinctrl, "default"); 1282 if (IS_ERR(dpi->pins_dpi)) { 1283 dpi->pins_dpi = NULL; 1284 dev_dbg(&pdev->dev, "Cannot find pinctrl active!\n"); 1285 } 1286 } 1287 dpi->regs = devm_platform_ioremap_resource(pdev, 0); 1288 if (IS_ERR(dpi->regs)) 1289 return dev_err_probe(dev, PTR_ERR(dpi->regs), 1290 "Failed to ioremap mem resource\n"); 1291 1292 dpi->engine_clk = devm_clk_get(dev, "engine"); 1293 if (IS_ERR(dpi->engine_clk)) 1294 return dev_err_probe(dev, PTR_ERR(dpi->engine_clk), 1295 "Failed to get engine clock\n"); 1296 1297 dpi->pixel_clk = devm_clk_get(dev, "pixel"); 1298 if (IS_ERR(dpi->pixel_clk)) 1299 return dev_err_probe(dev, PTR_ERR(dpi->pixel_clk), 1300 "Failed to get pixel clock\n"); 1301 1302 dpi->tvd_clk = devm_clk_get(dev, "pll"); 1303 if (IS_ERR(dpi->tvd_clk)) 1304 return dev_err_probe(dev, PTR_ERR(dpi->tvd_clk), 1305 "Failed to get tvdpll clock\n"); 1306 1307 dpi->irq = platform_get_irq(pdev, 0); 1308 if (dpi->irq < 0) 1309 return dpi->irq; 1310 1311 dpi->next_bridge = devm_drm_of_get_bridge(dpi->dev, dpi->dev->of_node, 1, -1); 1312 if (IS_ERR(dpi->next_bridge) && PTR_ERR(dpi->next_bridge) == -ENODEV) { 1313 /* Old devicetree has only one endpoint */ 1314 dpi->next_bridge = devm_drm_of_get_bridge(dpi->dev, dpi->dev->of_node, 0, 0); 1315 } 1316 if (IS_ERR(dpi->next_bridge)) 1317 return dev_err_probe(dpi->dev, PTR_ERR(dpi->next_bridge), 1318 "Failed to get bridge\n"); 1319 1320 platform_set_drvdata(pdev, dpi); 1321 1322 dpi->bridge.of_node = dev->of_node; 1323 dpi->bridge.type = DRM_MODE_CONNECTOR_DPI; 1324 1325 ret = devm_drm_bridge_add(dev, &dpi->bridge); 1326 if (ret) 1327 return ret; 1328 1329 ret = component_add(dev, &mtk_dpi_component_ops); 1330 if (ret) 1331 return dev_err_probe(dev, ret, "Failed to add component.\n"); 1332 1333 return 0; 1334 } 1335 1336 static void mtk_dpi_remove(struct platform_device *pdev) 1337 { 1338 component_del(&pdev->dev, &mtk_dpi_component_ops); 1339 } 1340 1341 static const struct of_device_id mtk_dpi_of_ids[] = { 1342 { .compatible = "mediatek,mt2701-dpi", .data = &mt2701_conf }, 1343 { .compatible = "mediatek,mt8173-dpi", .data = &mt8173_conf }, 1344 { .compatible = "mediatek,mt8183-dpi", .data = &mt8183_conf }, 1345 { .compatible = "mediatek,mt8186-dpi", .data = &mt8186_conf }, 1346 { .compatible = "mediatek,mt8188-dp-intf", .data = &mt8195_dpintf_conf }, 1347 { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf }, 1348 { .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf }, 1349 { .compatible = "mediatek,mt8195-dpi", .data = &mt8195_conf }, 1350 { /* sentinel */ }, 1351 }; 1352 MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); 1353 1354 struct platform_driver mtk_dpi_driver = { 1355 .probe = mtk_dpi_probe, 1356 .remove = mtk_dpi_remove, 1357 .driver = { 1358 .name = "mediatek-dpi", 1359 .of_match_table = mtk_dpi_of_ids, 1360 }, 1361 }; 1362