xref: /linux/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c (revision 76544811c850a1f4c055aa182b513b7a843868ea)
1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
28 
29 #include "dm_services_types.h"
30 #include "dc.h"
31 #include "link_enc_cfg.h"
32 #include "dc/inc/core_types.h"
33 #include "dal_asic_id.h"
34 #include "dmub/dmub_srv.h"
35 #include "dc/inc/hw/dmcu.h"
36 #include "dc/inc/hw/abm.h"
37 #include "dc/dc_dmub_srv.h"
38 #include "dc/dc_edid_parser.h"
39 #include "dc/dc_stat.h"
40 #include "dc/dc_state.h"
41 #include "amdgpu_dm_trace.h"
42 #include "dpcd_defs.h"
43 #include "link/protocols/link_dpcd.h"
44 #include "link_service_types.h"
45 #include "link/protocols/link_dp_capability.h"
46 #include "link/protocols/link_ddc.h"
47 
48 #include "vid.h"
49 #include "amdgpu.h"
50 #include "amdgpu_display.h"
51 #include "amdgpu_ucode.h"
52 #include "atom.h"
53 #include "amdgpu_dm.h"
54 #include "amdgpu_dm_plane.h"
55 #include "amdgpu_dm_crtc.h"
56 #include "amdgpu_dm_hdcp.h"
57 #include <drm/display/drm_hdcp_helper.h>
58 #include "amdgpu_dm_wb.h"
59 #include "amdgpu_pm.h"
60 #include "amdgpu_atombios.h"
61 
62 #include "amd_shared.h"
63 #include "amdgpu_dm_irq.h"
64 #include "dm_helpers.h"
65 #include "amdgpu_dm_mst_types.h"
66 #if defined(CONFIG_DEBUG_FS)
67 #include "amdgpu_dm_debugfs.h"
68 #endif
69 #include "amdgpu_dm_psr.h"
70 #include "amdgpu_dm_replay.h"
71 
72 #include "ivsrcid/ivsrcid_vislands30.h"
73 
74 #include <linux/backlight.h>
75 #include <linux/module.h>
76 #include <linux/moduleparam.h>
77 #include <linux/types.h>
78 #include <linux/pm_runtime.h>
79 #include <linux/pci.h>
80 #include <linux/power_supply.h>
81 #include <linux/firmware.h>
82 #include <linux/component.h>
83 #include <linux/dmi.h>
84 #include <linux/sort.h>
85 
86 #include <drm/display/drm_dp_mst_helper.h>
87 #include <drm/display/drm_hdmi_helper.h>
88 #include <drm/drm_atomic.h>
89 #include <drm/drm_atomic_uapi.h>
90 #include <drm/drm_atomic_helper.h>
91 #include <drm/drm_blend.h>
92 #include <drm/drm_fixed.h>
93 #include <drm/drm_fourcc.h>
94 #include <drm/drm_edid.h>
95 #include <drm/drm_eld.h>
96 #include <drm/drm_utils.h>
97 #include <drm/drm_vblank.h>
98 #include <drm/drm_audio_component.h>
99 #include <drm/drm_gem_atomic_helper.h>
100 
101 #include <media/cec-notifier.h>
102 #include <acpi/video.h>
103 
104 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
105 
106 #include "dcn/dcn_1_0_offset.h"
107 #include "dcn/dcn_1_0_sh_mask.h"
108 #include "soc15_hw_ip.h"
109 #include "soc15_common.h"
110 #include "vega10_ip_offset.h"
111 
112 #include "gc/gc_11_0_0_offset.h"
113 #include "gc/gc_11_0_0_sh_mask.h"
114 
115 #include "modules/inc/mod_freesync.h"
116 #include "modules/power/power_helpers.h"
117 
118 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
119 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
120 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
121 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
122 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
123 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
124 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
125 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
126 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
127 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
128 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
129 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
130 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
131 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
132 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
133 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
134 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
135 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
136 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
137 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
138 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
139 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
140 
141 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
142 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
143 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
144 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
145 
146 #define FIRMWARE_RAVEN_DMCU		"amdgpu/raven_dmcu.bin"
147 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
148 
149 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
150 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
151 
152 #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin"
153 MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB);
154 
155 #define FIRMWARE_DCN_351_DMUB "amdgpu/dcn_3_5_1_dmcub.bin"
156 MODULE_FIRMWARE(FIRMWARE_DCN_351_DMUB);
157 
158 #define FIRMWARE_DCN_401_DMUB "amdgpu/dcn_4_0_1_dmcub.bin"
159 MODULE_FIRMWARE(FIRMWARE_DCN_401_DMUB);
160 
161 /* Number of bytes in PSP header for firmware. */
162 #define PSP_HEADER_BYTES 0x100
163 
164 /* Number of bytes in PSP footer for firmware. */
165 #define PSP_FOOTER_BYTES 0x100
166 
167 /**
168  * DOC: overview
169  *
170  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
171  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
172  * requests into DC requests, and DC responses into DRM responses.
173  *
174  * The root control structure is &struct amdgpu_display_manager.
175  */
176 
177 /* basic init/fini API */
178 static int amdgpu_dm_init(struct amdgpu_device *adev);
179 static void amdgpu_dm_fini(struct amdgpu_device *adev);
180 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
181 static void reset_freesync_config_for_crtc(struct dm_crtc_state *new_crtc_state);
182 
get_subconnector_type(struct dc_link * link)183 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
184 {
185 	switch (link->dpcd_caps.dongle_type) {
186 	case DISPLAY_DONGLE_NONE:
187 		return DRM_MODE_SUBCONNECTOR_Native;
188 	case DISPLAY_DONGLE_DP_VGA_CONVERTER:
189 		return DRM_MODE_SUBCONNECTOR_VGA;
190 	case DISPLAY_DONGLE_DP_DVI_CONVERTER:
191 	case DISPLAY_DONGLE_DP_DVI_DONGLE:
192 		return DRM_MODE_SUBCONNECTOR_DVID;
193 	case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
194 	case DISPLAY_DONGLE_DP_HDMI_DONGLE:
195 		return DRM_MODE_SUBCONNECTOR_HDMIA;
196 	case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
197 	default:
198 		return DRM_MODE_SUBCONNECTOR_Unknown;
199 	}
200 }
201 
update_subconnector_property(struct amdgpu_dm_connector * aconnector)202 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
203 {
204 	struct dc_link *link = aconnector->dc_link;
205 	struct drm_connector *connector = &aconnector->base;
206 	enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
207 
208 	if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
209 		return;
210 
211 	if (aconnector->dc_sink)
212 		subconnector = get_subconnector_type(link);
213 
214 	drm_object_property_set_value(&connector->base,
215 			connector->dev->mode_config.dp_subconnector_property,
216 			subconnector);
217 }
218 
219 /*
220  * initializes drm_device display related structures, based on the information
221  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
222  * drm_encoder, drm_mode_config
223  *
224  * Returns 0 on success
225  */
226 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
227 /* removes and deallocates the drm structures, created by the above function */
228 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
229 
230 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
231 				    struct amdgpu_dm_connector *amdgpu_dm_connector,
232 				    u32 link_index,
233 				    struct amdgpu_encoder *amdgpu_encoder);
234 static int amdgpu_dm_encoder_init(struct drm_device *dev,
235 				  struct amdgpu_encoder *aencoder,
236 				  uint32_t link_index);
237 
238 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
239 
240 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
241 
242 static int amdgpu_dm_atomic_check(struct drm_device *dev,
243 				  struct drm_atomic_state *state);
244 
245 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
246 static void handle_hpd_rx_irq(void *param);
247 
248 static bool
249 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
250 				 struct drm_crtc_state *new_crtc_state);
251 /*
252  * dm_vblank_get_counter
253  *
254  * @brief
255  * Get counter for number of vertical blanks
256  *
257  * @param
258  * struct amdgpu_device *adev - [in] desired amdgpu device
259  * int disp_idx - [in] which CRTC to get the counter from
260  *
261  * @return
262  * Counter for vertical blanks
263  */
dm_vblank_get_counter(struct amdgpu_device * adev,int crtc)264 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
265 {
266 	struct amdgpu_crtc *acrtc = NULL;
267 
268 	if (crtc >= adev->mode_info.num_crtc)
269 		return 0;
270 
271 	acrtc = adev->mode_info.crtcs[crtc];
272 
273 	if (!acrtc->dm_irq_params.stream) {
274 		DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
275 			  crtc);
276 		return 0;
277 	}
278 
279 	return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
280 }
281 
dm_crtc_get_scanoutpos(struct amdgpu_device * adev,int crtc,u32 * vbl,u32 * position)282 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
283 				  u32 *vbl, u32 *position)
284 {
285 	u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0;
286 	struct amdgpu_crtc *acrtc = NULL;
287 	struct dc *dc = adev->dm.dc;
288 
289 	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
290 		return -EINVAL;
291 
292 	acrtc = adev->mode_info.crtcs[crtc];
293 
294 	if (!acrtc->dm_irq_params.stream) {
295 		DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
296 			  crtc);
297 		return 0;
298 	}
299 
300 	if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)
301 		dc_allow_idle_optimizations(dc, false);
302 
303 	/*
304 	 * TODO rework base driver to use values directly.
305 	 * for now parse it back into reg-format
306 	 */
307 	dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
308 				 &v_blank_start,
309 				 &v_blank_end,
310 				 &h_position,
311 				 &v_position);
312 
313 	*position = v_position | (h_position << 16);
314 	*vbl = v_blank_start | (v_blank_end << 16);
315 
316 	return 0;
317 }
318 
dm_is_idle(void * handle)319 static bool dm_is_idle(void *handle)
320 {
321 	/* XXX todo */
322 	return true;
323 }
324 
dm_wait_for_idle(struct amdgpu_ip_block * ip_block)325 static int dm_wait_for_idle(struct amdgpu_ip_block *ip_block)
326 {
327 	/* XXX todo */
328 	return 0;
329 }
330 
dm_check_soft_reset(struct amdgpu_ip_block * ip_block)331 static bool dm_check_soft_reset(struct amdgpu_ip_block *ip_block)
332 {
333 	return false;
334 }
335 
dm_soft_reset(struct amdgpu_ip_block * ip_block)336 static int dm_soft_reset(struct amdgpu_ip_block *ip_block)
337 {
338 	/* XXX todo */
339 	return 0;
340 }
341 
342 static struct amdgpu_crtc *
get_crtc_by_otg_inst(struct amdgpu_device * adev,int otg_inst)343 get_crtc_by_otg_inst(struct amdgpu_device *adev,
344 		     int otg_inst)
345 {
346 	struct drm_device *dev = adev_to_drm(adev);
347 	struct drm_crtc *crtc;
348 	struct amdgpu_crtc *amdgpu_crtc;
349 
350 	if (WARN_ON(otg_inst == -1))
351 		return adev->mode_info.crtcs[0];
352 
353 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
354 		amdgpu_crtc = to_amdgpu_crtc(crtc);
355 
356 		if (amdgpu_crtc->otg_inst == otg_inst)
357 			return amdgpu_crtc;
358 	}
359 
360 	return NULL;
361 }
362 
is_dc_timing_adjust_needed(struct dm_crtc_state * old_state,struct dm_crtc_state * new_state)363 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
364 					      struct dm_crtc_state *new_state)
365 {
366 	if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
367 		return true;
368 	else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
369 		return true;
370 	else
371 		return false;
372 }
373 
374 /*
375  * DC will program planes with their z-order determined by their ordering
376  * in the dc_surface_updates array. This comparator is used to sort them
377  * by descending zpos.
378  */
dm_plane_layer_index_cmp(const void * a,const void * b)379 static int dm_plane_layer_index_cmp(const void *a, const void *b)
380 {
381 	const struct dc_surface_update *sa = (struct dc_surface_update *)a;
382 	const struct dc_surface_update *sb = (struct dc_surface_update *)b;
383 
384 	/* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */
385 	return sb->surface->layer_index - sa->surface->layer_index;
386 }
387 
388 /**
389  * update_planes_and_stream_adapter() - Send planes to be updated in DC
390  *
391  * DC has a generic way to update planes and stream via
392  * dc_update_planes_and_stream function; however, DM might need some
393  * adjustments and preparation before calling it. This function is a wrapper
394  * for the dc_update_planes_and_stream that does any required configuration
395  * before passing control to DC.
396  *
397  * @dc: Display Core control structure
398  * @update_type: specify whether it is FULL/MEDIUM/FAST update
399  * @planes_count: planes count to update
400  * @stream: stream state
401  * @stream_update: stream update
402  * @array_of_surface_update: dc surface update pointer
403  *
404  */
update_planes_and_stream_adapter(struct dc * dc,int update_type,int planes_count,struct dc_stream_state * stream,struct dc_stream_update * stream_update,struct dc_surface_update * array_of_surface_update)405 static inline bool update_planes_and_stream_adapter(struct dc *dc,
406 						    int update_type,
407 						    int planes_count,
408 						    struct dc_stream_state *stream,
409 						    struct dc_stream_update *stream_update,
410 						    struct dc_surface_update *array_of_surface_update)
411 {
412 	sort(array_of_surface_update, planes_count,
413 	     sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL);
414 
415 	/*
416 	 * Previous frame finished and HW is ready for optimization.
417 	 */
418 	if (update_type == UPDATE_TYPE_FAST)
419 		dc_post_update_surfaces_to_stream(dc);
420 
421 	return dc_update_planes_and_stream(dc,
422 					   array_of_surface_update,
423 					   planes_count,
424 					   stream,
425 					   stream_update);
426 }
427 
428 /**
429  * dm_pflip_high_irq() - Handle pageflip interrupt
430  * @interrupt_params: ignored
431  *
432  * Handles the pageflip interrupt by notifying all interested parties
433  * that the pageflip has been completed.
434  */
dm_pflip_high_irq(void * interrupt_params)435 static void dm_pflip_high_irq(void *interrupt_params)
436 {
437 	struct amdgpu_crtc *amdgpu_crtc;
438 	struct common_irq_params *irq_params = interrupt_params;
439 	struct amdgpu_device *adev = irq_params->adev;
440 	struct drm_device *dev = adev_to_drm(adev);
441 	unsigned long flags;
442 	struct drm_pending_vblank_event *e;
443 	u32 vpos, hpos, v_blank_start, v_blank_end;
444 	bool vrr_active;
445 
446 	amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
447 
448 	/* IRQ could occur when in initial stage */
449 	/* TODO work and BO cleanup */
450 	if (amdgpu_crtc == NULL) {
451 		drm_dbg_state(dev, "CRTC is null, returning.\n");
452 		return;
453 	}
454 
455 	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
456 
457 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
458 		drm_dbg_state(dev,
459 			      "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",
460 			      amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED,
461 			      amdgpu_crtc->crtc_id, amdgpu_crtc);
462 		spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
463 		return;
464 	}
465 
466 	/* page flip completed. */
467 	e = amdgpu_crtc->event;
468 	amdgpu_crtc->event = NULL;
469 
470 	WARN_ON(!e);
471 
472 	vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
473 
474 	/* Fixed refresh rate, or VRR scanout position outside front-porch? */
475 	if (!vrr_active ||
476 	    !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
477 				      &v_blank_end, &hpos, &vpos) ||
478 	    (vpos < v_blank_start)) {
479 		/* Update to correct count and vblank timestamp if racing with
480 		 * vblank irq. This also updates to the correct vblank timestamp
481 		 * even in VRR mode, as scanout is past the front-porch atm.
482 		 */
483 		drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
484 
485 		/* Wake up userspace by sending the pageflip event with proper
486 		 * count and timestamp of vblank of flip completion.
487 		 */
488 		if (e) {
489 			drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
490 
491 			/* Event sent, so done with vblank for this flip */
492 			drm_crtc_vblank_put(&amdgpu_crtc->base);
493 		}
494 	} else if (e) {
495 		/* VRR active and inside front-porch: vblank count and
496 		 * timestamp for pageflip event will only be up to date after
497 		 * drm_crtc_handle_vblank() has been executed from late vblank
498 		 * irq handler after start of back-porch (vline 0). We queue the
499 		 * pageflip event for send-out by drm_crtc_handle_vblank() with
500 		 * updated timestamp and count, once it runs after us.
501 		 *
502 		 * We need to open-code this instead of using the helper
503 		 * drm_crtc_arm_vblank_event(), as that helper would
504 		 * call drm_crtc_accurate_vblank_count(), which we must
505 		 * not call in VRR mode while we are in front-porch!
506 		 */
507 
508 		/* sequence will be replaced by real count during send-out. */
509 		e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
510 		e->pipe = amdgpu_crtc->crtc_id;
511 
512 		list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
513 		e = NULL;
514 	}
515 
516 	/* Keep track of vblank of this flip for flip throttling. We use the
517 	 * cooked hw counter, as that one incremented at start of this vblank
518 	 * of pageflip completion, so last_flip_vblank is the forbidden count
519 	 * for queueing new pageflips if vsync + VRR is enabled.
520 	 */
521 	amdgpu_crtc->dm_irq_params.last_flip_vblank =
522 		amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
523 
524 	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
525 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
526 
527 	drm_dbg_state(dev,
528 		      "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
529 		      amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e);
530 }
531 
dm_vupdate_high_irq(void * interrupt_params)532 static void dm_vupdate_high_irq(void *interrupt_params)
533 {
534 	struct common_irq_params *irq_params = interrupt_params;
535 	struct amdgpu_device *adev = irq_params->adev;
536 	struct amdgpu_crtc *acrtc;
537 	struct drm_device *drm_dev;
538 	struct drm_vblank_crtc *vblank;
539 	ktime_t frame_duration_ns, previous_timestamp;
540 	unsigned long flags;
541 	int vrr_active;
542 
543 	acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
544 
545 	if (acrtc) {
546 		vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
547 		drm_dev = acrtc->base.dev;
548 		vblank = drm_crtc_vblank_crtc(&acrtc->base);
549 		previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
550 		frame_duration_ns = vblank->time - previous_timestamp;
551 
552 		if (frame_duration_ns > 0) {
553 			trace_amdgpu_refresh_rate_track(acrtc->base.index,
554 						frame_duration_ns,
555 						ktime_divns(NSEC_PER_SEC, frame_duration_ns));
556 			atomic64_set(&irq_params->previous_timestamp, vblank->time);
557 		}
558 
559 		drm_dbg_vbl(drm_dev,
560 			    "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
561 			    vrr_active);
562 
563 		/* Core vblank handling is done here after end of front-porch in
564 		 * vrr mode, as vblank timestamping will give valid results
565 		 * while now done after front-porch. This will also deliver
566 		 * page-flip completion events that have been queued to us
567 		 * if a pageflip happened inside front-porch.
568 		 */
569 		if (vrr_active) {
570 			amdgpu_dm_crtc_handle_vblank(acrtc);
571 
572 			/* BTR processing for pre-DCE12 ASICs */
573 			if (acrtc->dm_irq_params.stream &&
574 			    adev->family < AMDGPU_FAMILY_AI) {
575 				spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
576 				mod_freesync_handle_v_update(
577 				    adev->dm.freesync_module,
578 				    acrtc->dm_irq_params.stream,
579 				    &acrtc->dm_irq_params.vrr_params);
580 
581 				dc_stream_adjust_vmin_vmax(
582 				    adev->dm.dc,
583 				    acrtc->dm_irq_params.stream,
584 				    &acrtc->dm_irq_params.vrr_params.adjust);
585 				spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
586 			}
587 		}
588 	}
589 }
590 
591 /**
592  * dm_crtc_high_irq() - Handles CRTC interrupt
593  * @interrupt_params: used for determining the CRTC instance
594  *
595  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
596  * event handler.
597  */
dm_crtc_high_irq(void * interrupt_params)598 static void dm_crtc_high_irq(void *interrupt_params)
599 {
600 	struct common_irq_params *irq_params = interrupt_params;
601 	struct amdgpu_device *adev = irq_params->adev;
602 	struct drm_writeback_job *job;
603 	struct amdgpu_crtc *acrtc;
604 	unsigned long flags;
605 	int vrr_active;
606 
607 	acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
608 	if (!acrtc)
609 		return;
610 
611 	if (acrtc->wb_conn) {
612 		spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags);
613 
614 		if (acrtc->wb_pending) {
615 			job = list_first_entry_or_null(&acrtc->wb_conn->job_queue,
616 						       struct drm_writeback_job,
617 						       list_entry);
618 			acrtc->wb_pending = false;
619 			spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags);
620 
621 			if (job) {
622 				unsigned int v_total, refresh_hz;
623 				struct dc_stream_state *stream = acrtc->dm_irq_params.stream;
624 
625 				v_total = stream->adjust.v_total_max ?
626 					  stream->adjust.v_total_max : stream->timing.v_total;
627 				refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz *
628 					     100LL, (v_total * stream->timing.h_total));
629 				mdelay(1000 / refresh_hz);
630 
631 				drm_writeback_signal_completion(acrtc->wb_conn, 0);
632 				dc_stream_fc_disable_writeback(adev->dm.dc,
633 							       acrtc->dm_irq_params.stream, 0);
634 			}
635 		} else
636 			spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags);
637 	}
638 
639 	vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
640 
641 	drm_dbg_vbl(adev_to_drm(adev),
642 		    "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
643 		    vrr_active, acrtc->dm_irq_params.active_planes);
644 
645 	/**
646 	 * Core vblank handling at start of front-porch is only possible
647 	 * in non-vrr mode, as only there vblank timestamping will give
648 	 * valid results while done in front-porch. Otherwise defer it
649 	 * to dm_vupdate_high_irq after end of front-porch.
650 	 */
651 	if (!vrr_active)
652 		amdgpu_dm_crtc_handle_vblank(acrtc);
653 
654 	/**
655 	 * Following stuff must happen at start of vblank, for crc
656 	 * computation and below-the-range btr support in vrr mode.
657 	 */
658 	amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
659 
660 	/* BTR updates need to happen before VUPDATE on Vega and above. */
661 	if (adev->family < AMDGPU_FAMILY_AI)
662 		return;
663 
664 	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
665 
666 	if (acrtc->dm_irq_params.stream &&
667 	    acrtc->dm_irq_params.vrr_params.supported &&
668 	    acrtc->dm_irq_params.freesync_config.state ==
669 		    VRR_STATE_ACTIVE_VARIABLE) {
670 		mod_freesync_handle_v_update(adev->dm.freesync_module,
671 					     acrtc->dm_irq_params.stream,
672 					     &acrtc->dm_irq_params.vrr_params);
673 
674 		dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
675 					   &acrtc->dm_irq_params.vrr_params.adjust);
676 	}
677 
678 	/*
679 	 * If there aren't any active_planes then DCH HUBP may be clock-gated.
680 	 * In that case, pageflip completion interrupts won't fire and pageflip
681 	 * completion events won't get delivered. Prevent this by sending
682 	 * pending pageflip events from here if a flip is still pending.
683 	 *
684 	 * If any planes are enabled, use dm_pflip_high_irq() instead, to
685 	 * avoid race conditions between flip programming and completion,
686 	 * which could cause too early flip completion events.
687 	 */
688 	if (adev->family >= AMDGPU_FAMILY_RV &&
689 	    acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
690 	    acrtc->dm_irq_params.active_planes == 0) {
691 		if (acrtc->event) {
692 			drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
693 			acrtc->event = NULL;
694 			drm_crtc_vblank_put(&acrtc->base);
695 		}
696 		acrtc->pflip_status = AMDGPU_FLIP_NONE;
697 	}
698 
699 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
700 }
701 
702 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
703 /**
704  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
705  * DCN generation ASICs
706  * @interrupt_params: interrupt parameters
707  *
708  * Used to set crc window/read out crc value at vertical line 0 position
709  */
dm_dcn_vertical_interrupt0_high_irq(void * interrupt_params)710 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
711 {
712 	struct common_irq_params *irq_params = interrupt_params;
713 	struct amdgpu_device *adev = irq_params->adev;
714 	struct amdgpu_crtc *acrtc;
715 
716 	acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
717 
718 	if (!acrtc)
719 		return;
720 
721 	amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
722 }
723 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
724 
725 /**
726  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
727  * @adev: amdgpu_device pointer
728  * @notify: dmub notification structure
729  *
730  * Dmub AUX or SET_CONFIG command completion processing callback
731  * Copies dmub notification to DM which is to be read by AUX command.
732  * issuing thread and also signals the event to wake up the thread.
733  */
dmub_aux_setconfig_callback(struct amdgpu_device * adev,struct dmub_notification * notify)734 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
735 					struct dmub_notification *notify)
736 {
737 	if (adev->dm.dmub_notify)
738 		memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
739 	if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
740 		complete(&adev->dm.dmub_aux_transfer_done);
741 }
742 
743 /**
744  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
745  * @adev: amdgpu_device pointer
746  * @notify: dmub notification structure
747  *
748  * Dmub Hpd interrupt processing callback. Gets displayindex through the
749  * ink index and calls helper to do the processing.
750  */
dmub_hpd_callback(struct amdgpu_device * adev,struct dmub_notification * notify)751 static void dmub_hpd_callback(struct amdgpu_device *adev,
752 			      struct dmub_notification *notify)
753 {
754 	struct amdgpu_dm_connector *aconnector;
755 	struct amdgpu_dm_connector *hpd_aconnector = NULL;
756 	struct drm_connector *connector;
757 	struct drm_connector_list_iter iter;
758 	struct dc_link *link;
759 	u8 link_index = 0;
760 	struct drm_device *dev;
761 
762 	if (adev == NULL)
763 		return;
764 
765 	if (notify == NULL) {
766 		DRM_ERROR("DMUB HPD callback notification was NULL");
767 		return;
768 	}
769 
770 	if (notify->link_index > adev->dm.dc->link_count) {
771 		DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
772 		return;
773 	}
774 
775 	/* Skip DMUB HPD IRQ in suspend/resume. We will probe them later. */
776 	if (notify->type == DMUB_NOTIFICATION_HPD && adev->in_suspend) {
777 		DRM_INFO("Skip DMUB HPD IRQ callback in suspend/resume\n");
778 		return;
779 	}
780 
781 	link_index = notify->link_index;
782 	link = adev->dm.dc->links[link_index];
783 	dev = adev->dm.ddev;
784 
785 	drm_connector_list_iter_begin(dev, &iter);
786 	drm_for_each_connector_iter(connector, &iter) {
787 
788 		if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
789 			continue;
790 
791 		aconnector = to_amdgpu_dm_connector(connector);
792 		if (link && aconnector->dc_link == link) {
793 			if (notify->type == DMUB_NOTIFICATION_HPD)
794 				DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
795 			else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
796 				DRM_INFO("DMUB HPD RX IRQ callback: link_index=%u\n", link_index);
797 			else
798 				DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
799 						notify->type, link_index);
800 
801 			hpd_aconnector = aconnector;
802 			break;
803 		}
804 	}
805 	drm_connector_list_iter_end(&iter);
806 
807 	if (hpd_aconnector) {
808 		if (notify->type == DMUB_NOTIFICATION_HPD) {
809 			if (hpd_aconnector->dc_link->hpd_status == (notify->hpd_status == DP_HPD_PLUG))
810 				DRM_WARN("DMUB reported hpd status unchanged. link_index=%u\n", link_index);
811 			handle_hpd_irq_helper(hpd_aconnector);
812 		} else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) {
813 			handle_hpd_rx_irq(hpd_aconnector);
814 		}
815 	}
816 }
817 
818 /**
819  * dmub_hpd_sense_callback - DMUB HPD sense processing callback.
820  * @adev: amdgpu_device pointer
821  * @notify: dmub notification structure
822  *
823  * HPD sense changes can occur during low power states and need to be
824  * notified from firmware to driver.
825  */
dmub_hpd_sense_callback(struct amdgpu_device * adev,struct dmub_notification * notify)826 static void dmub_hpd_sense_callback(struct amdgpu_device *adev,
827 			      struct dmub_notification *notify)
828 {
829 	DRM_DEBUG_DRIVER("DMUB HPD SENSE callback.\n");
830 }
831 
832 /**
833  * register_dmub_notify_callback - Sets callback for DMUB notify
834  * @adev: amdgpu_device pointer
835  * @type: Type of dmub notification
836  * @callback: Dmub interrupt callback function
837  * @dmub_int_thread_offload: offload indicator
838  *
839  * API to register a dmub callback handler for a dmub notification
840  * Also sets indicator whether callback processing to be offloaded.
841  * to dmub interrupt handling thread
842  * Return: true if successfully registered, false if there is existing registration
843  */
register_dmub_notify_callback(struct amdgpu_device * adev,enum dmub_notification_type type,dmub_notify_interrupt_callback_t callback,bool dmub_int_thread_offload)844 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
845 					  enum dmub_notification_type type,
846 					  dmub_notify_interrupt_callback_t callback,
847 					  bool dmub_int_thread_offload)
848 {
849 	if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
850 		adev->dm.dmub_callback[type] = callback;
851 		adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
852 	} else
853 		return false;
854 
855 	return true;
856 }
857 
dm_handle_hpd_work(struct work_struct * work)858 static void dm_handle_hpd_work(struct work_struct *work)
859 {
860 	struct dmub_hpd_work *dmub_hpd_wrk;
861 
862 	dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
863 
864 	if (!dmub_hpd_wrk->dmub_notify) {
865 		DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
866 		return;
867 	}
868 
869 	if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
870 		dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
871 		dmub_hpd_wrk->dmub_notify);
872 	}
873 
874 	kfree(dmub_hpd_wrk->dmub_notify);
875 	kfree(dmub_hpd_wrk);
876 
877 }
878 
879 #define DMUB_TRACE_MAX_READ 64
880 /**
881  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
882  * @interrupt_params: used for determining the Outbox instance
883  *
884  * Handles the Outbox Interrupt
885  * event handler.
886  */
dm_dmub_outbox1_low_irq(void * interrupt_params)887 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
888 {
889 	struct dmub_notification notify = {0};
890 	struct common_irq_params *irq_params = interrupt_params;
891 	struct amdgpu_device *adev = irq_params->adev;
892 	struct amdgpu_display_manager *dm = &adev->dm;
893 	struct dmcub_trace_buf_entry entry = { 0 };
894 	u32 count = 0;
895 	struct dmub_hpd_work *dmub_hpd_wrk;
896 	static const char *const event_type[] = {
897 		"NO_DATA",
898 		"AUX_REPLY",
899 		"HPD",
900 		"HPD_IRQ",
901 		"SET_CONFIGC_REPLY",
902 		"DPIA_NOTIFICATION",
903 		"HPD_SENSE_NOTIFY",
904 	};
905 
906 	do {
907 		if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
908 			trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
909 							entry.param0, entry.param1);
910 
911 			DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
912 				 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
913 		} else
914 			break;
915 
916 		count++;
917 
918 	} while (count <= DMUB_TRACE_MAX_READ);
919 
920 	if (count > DMUB_TRACE_MAX_READ)
921 		DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
922 
923 	if (dc_enable_dmub_notifications(adev->dm.dc) &&
924 		irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
925 
926 		do {
927 			dc_stat_get_dmub_notification(adev->dm.dc, &notify);
928 			if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
929 				DRM_ERROR("DM: notify type %d invalid!", notify.type);
930 				continue;
931 			}
932 			if (!dm->dmub_callback[notify.type]) {
933 				DRM_WARN("DMUB notification skipped due to no handler: type=%s\n",
934 					event_type[notify.type]);
935 				continue;
936 			}
937 			if (dm->dmub_thread_offload[notify.type] == true) {
938 				dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
939 				if (!dmub_hpd_wrk) {
940 					DRM_ERROR("Failed to allocate dmub_hpd_wrk");
941 					return;
942 				}
943 				dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
944 								    GFP_ATOMIC);
945 				if (!dmub_hpd_wrk->dmub_notify) {
946 					kfree(dmub_hpd_wrk);
947 					DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
948 					return;
949 				}
950 				INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
951 				dmub_hpd_wrk->adev = adev;
952 				queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
953 			} else {
954 				dm->dmub_callback[notify.type](adev, &notify);
955 			}
956 		} while (notify.pending_notification);
957 	}
958 }
959 
dm_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)960 static int dm_set_clockgating_state(struct amdgpu_ip_block *ip_block,
961 		  enum amd_clockgating_state state)
962 {
963 	return 0;
964 }
965 
dm_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)966 static int dm_set_powergating_state(struct amdgpu_ip_block *ip_block,
967 		  enum amd_powergating_state state)
968 {
969 	return 0;
970 }
971 
972 /* Prototypes of private functions */
973 static int dm_early_init(struct amdgpu_ip_block *ip_block);
974 
975 /* Allocate memory for FBC compressed data  */
amdgpu_dm_fbc_init(struct drm_connector * connector)976 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
977 {
978 	struct amdgpu_device *adev = drm_to_adev(connector->dev);
979 	struct dm_compressor_info *compressor = &adev->dm.compressor;
980 	struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
981 	struct drm_display_mode *mode;
982 	unsigned long max_size = 0;
983 
984 	if (adev->dm.dc->fbc_compressor == NULL)
985 		return;
986 
987 	if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
988 		return;
989 
990 	if (compressor->bo_ptr)
991 		return;
992 
993 
994 	list_for_each_entry(mode, &connector->modes, head) {
995 		if (max_size < (unsigned long) mode->htotal * mode->vtotal)
996 			max_size = (unsigned long) mode->htotal * mode->vtotal;
997 	}
998 
999 	if (max_size) {
1000 		int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
1001 			    AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
1002 			    &compressor->gpu_addr, &compressor->cpu_addr);
1003 
1004 		if (r)
1005 			DRM_ERROR("DM: Failed to initialize FBC\n");
1006 		else {
1007 			adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
1008 			DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
1009 		}
1010 
1011 	}
1012 
1013 }
1014 
amdgpu_dm_audio_component_get_eld(struct device * kdev,int port,int pipe,bool * enabled,unsigned char * buf,int max_bytes)1015 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
1016 					  int pipe, bool *enabled,
1017 					  unsigned char *buf, int max_bytes)
1018 {
1019 	struct drm_device *dev = dev_get_drvdata(kdev);
1020 	struct amdgpu_device *adev = drm_to_adev(dev);
1021 	struct drm_connector *connector;
1022 	struct drm_connector_list_iter conn_iter;
1023 	struct amdgpu_dm_connector *aconnector;
1024 	int ret = 0;
1025 
1026 	*enabled = false;
1027 
1028 	mutex_lock(&adev->dm.audio_lock);
1029 
1030 	drm_connector_list_iter_begin(dev, &conn_iter);
1031 	drm_for_each_connector_iter(connector, &conn_iter) {
1032 
1033 		if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
1034 			continue;
1035 
1036 		aconnector = to_amdgpu_dm_connector(connector);
1037 		if (aconnector->audio_inst != port)
1038 			continue;
1039 
1040 		*enabled = true;
1041 		mutex_lock(&connector->eld_mutex);
1042 		ret = drm_eld_size(connector->eld);
1043 		memcpy(buf, connector->eld, min(max_bytes, ret));
1044 		mutex_unlock(&connector->eld_mutex);
1045 
1046 		break;
1047 	}
1048 	drm_connector_list_iter_end(&conn_iter);
1049 
1050 	mutex_unlock(&adev->dm.audio_lock);
1051 
1052 	DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
1053 
1054 	return ret;
1055 }
1056 
1057 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
1058 	.get_eld = amdgpu_dm_audio_component_get_eld,
1059 };
1060 
amdgpu_dm_audio_component_bind(struct device * kdev,struct device * hda_kdev,void * data)1061 static int amdgpu_dm_audio_component_bind(struct device *kdev,
1062 				       struct device *hda_kdev, void *data)
1063 {
1064 	struct drm_device *dev = dev_get_drvdata(kdev);
1065 	struct amdgpu_device *adev = drm_to_adev(dev);
1066 	struct drm_audio_component *acomp = data;
1067 
1068 	acomp->ops = &amdgpu_dm_audio_component_ops;
1069 	acomp->dev = kdev;
1070 	adev->dm.audio_component = acomp;
1071 
1072 	return 0;
1073 }
1074 
amdgpu_dm_audio_component_unbind(struct device * kdev,struct device * hda_kdev,void * data)1075 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
1076 					  struct device *hda_kdev, void *data)
1077 {
1078 	struct amdgpu_device *adev = drm_to_adev(dev_get_drvdata(kdev));
1079 	struct drm_audio_component *acomp = data;
1080 
1081 	acomp->ops = NULL;
1082 	acomp->dev = NULL;
1083 	adev->dm.audio_component = NULL;
1084 }
1085 
1086 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
1087 	.bind	= amdgpu_dm_audio_component_bind,
1088 	.unbind	= amdgpu_dm_audio_component_unbind,
1089 };
1090 
amdgpu_dm_audio_init(struct amdgpu_device * adev)1091 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1092 {
1093 	int i, ret;
1094 
1095 	if (!amdgpu_audio)
1096 		return 0;
1097 
1098 	adev->mode_info.audio.enabled = true;
1099 
1100 	adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1101 
1102 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1103 		adev->mode_info.audio.pin[i].channels = -1;
1104 		adev->mode_info.audio.pin[i].rate = -1;
1105 		adev->mode_info.audio.pin[i].bits_per_sample = -1;
1106 		adev->mode_info.audio.pin[i].status_bits = 0;
1107 		adev->mode_info.audio.pin[i].category_code = 0;
1108 		adev->mode_info.audio.pin[i].connected = false;
1109 		adev->mode_info.audio.pin[i].id =
1110 			adev->dm.dc->res_pool->audios[i]->inst;
1111 		adev->mode_info.audio.pin[i].offset = 0;
1112 	}
1113 
1114 	ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1115 	if (ret < 0)
1116 		return ret;
1117 
1118 	adev->dm.audio_registered = true;
1119 
1120 	return 0;
1121 }
1122 
amdgpu_dm_audio_fini(struct amdgpu_device * adev)1123 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1124 {
1125 	if (!amdgpu_audio)
1126 		return;
1127 
1128 	if (!adev->mode_info.audio.enabled)
1129 		return;
1130 
1131 	if (adev->dm.audio_registered) {
1132 		component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1133 		adev->dm.audio_registered = false;
1134 	}
1135 
1136 	/* TODO: Disable audio? */
1137 
1138 	adev->mode_info.audio.enabled = false;
1139 }
1140 
amdgpu_dm_audio_eld_notify(struct amdgpu_device * adev,int pin)1141 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1142 {
1143 	struct drm_audio_component *acomp = adev->dm.audio_component;
1144 
1145 	if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1146 		DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1147 
1148 		acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1149 						 pin, -1);
1150 	}
1151 }
1152 
dm_dmub_hw_init(struct amdgpu_device * adev)1153 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1154 {
1155 	const struct dmcub_firmware_header_v1_0 *hdr;
1156 	struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1157 	struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1158 	const struct firmware *dmub_fw = adev->dm.dmub_fw;
1159 	struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1160 	struct abm *abm = adev->dm.dc->res_pool->abm;
1161 	struct dc_context *ctx = adev->dm.dc->ctx;
1162 	struct dmub_srv_hw_params hw_params;
1163 	enum dmub_status status;
1164 	const unsigned char *fw_inst_const, *fw_bss_data;
1165 	u32 i, fw_inst_const_size, fw_bss_data_size;
1166 	bool has_hw_support;
1167 
1168 	if (!dmub_srv)
1169 		/* DMUB isn't supported on the ASIC. */
1170 		return 0;
1171 
1172 	if (!fb_info) {
1173 		DRM_ERROR("No framebuffer info for DMUB service.\n");
1174 		return -EINVAL;
1175 	}
1176 
1177 	if (!dmub_fw) {
1178 		/* Firmware required for DMUB support. */
1179 		DRM_ERROR("No firmware provided for DMUB.\n");
1180 		return -EINVAL;
1181 	}
1182 
1183 	/* initialize register offsets for ASICs with runtime initialization available */
1184 	if (dmub_srv->hw_funcs.init_reg_offsets)
1185 		dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);
1186 
1187 	status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1188 	if (status != DMUB_STATUS_OK) {
1189 		DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1190 		return -EINVAL;
1191 	}
1192 
1193 	if (!has_hw_support) {
1194 		DRM_INFO("DMUB unsupported on ASIC\n");
1195 		return 0;
1196 	}
1197 
1198 	/* Reset DMCUB if it was previously running - before we overwrite its memory. */
1199 	status = dmub_srv_hw_reset(dmub_srv);
1200 	if (status != DMUB_STATUS_OK)
1201 		DRM_WARN("Error resetting DMUB HW: %d\n", status);
1202 
1203 	hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1204 
1205 	fw_inst_const = dmub_fw->data +
1206 			le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1207 			PSP_HEADER_BYTES;
1208 
1209 	fw_bss_data = dmub_fw->data +
1210 		      le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1211 		      le32_to_cpu(hdr->inst_const_bytes);
1212 
1213 	/* Copy firmware and bios info into FB memory. */
1214 	fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1215 			     PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1216 
1217 	fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1218 
1219 	/* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1220 	 * amdgpu_ucode_init_single_fw will load dmub firmware
1221 	 * fw_inst_const part to cw0; otherwise, the firmware back door load
1222 	 * will be done by dm_dmub_hw_init
1223 	 */
1224 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1225 		memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1226 				fw_inst_const_size);
1227 	}
1228 
1229 	if (fw_bss_data_size)
1230 		memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1231 		       fw_bss_data, fw_bss_data_size);
1232 
1233 	/* Copy firmware bios info into FB memory. */
1234 	memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1235 	       adev->bios_size);
1236 
1237 	/* Reset regions that need to be reset. */
1238 	memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1239 	fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1240 
1241 	memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1242 	       fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1243 
1244 	memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1245 	       fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1246 
1247 	memset(fb_info->fb[DMUB_WINDOW_SHARED_STATE].cpu_addr, 0,
1248 	       fb_info->fb[DMUB_WINDOW_SHARED_STATE].size);
1249 
1250 	/* Initialize hardware. */
1251 	memset(&hw_params, 0, sizeof(hw_params));
1252 	hw_params.fb_base = adev->gmc.fb_start;
1253 	hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1254 
1255 	/* backdoor load firmware and trigger dmub running */
1256 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1257 		hw_params.load_inst_const = true;
1258 
1259 	if (dmcu)
1260 		hw_params.psp_version = dmcu->psp_version;
1261 
1262 	for (i = 0; i < fb_info->num_fb; ++i)
1263 		hw_params.fb[i] = &fb_info->fb[i];
1264 
1265 	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1266 	case IP_VERSION(3, 1, 3):
1267 	case IP_VERSION(3, 1, 4):
1268 	case IP_VERSION(3, 5, 0):
1269 	case IP_VERSION(3, 5, 1):
1270 	case IP_VERSION(4, 0, 1):
1271 		hw_params.dpia_supported = true;
1272 		hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1273 		break;
1274 	default:
1275 		break;
1276 	}
1277 
1278 	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1279 	case IP_VERSION(3, 5, 0):
1280 	case IP_VERSION(3, 5, 1):
1281 		hw_params.ips_sequential_ono = adev->external_rev_id > 0x10;
1282 		break;
1283 	default:
1284 		break;
1285 	}
1286 
1287 	status = dmub_srv_hw_init(dmub_srv, &hw_params);
1288 	if (status != DMUB_STATUS_OK) {
1289 		DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1290 		return -EINVAL;
1291 	}
1292 
1293 	/* Wait for firmware load to finish. */
1294 	status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1295 	if (status != DMUB_STATUS_OK)
1296 		DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1297 
1298 	/* Init DMCU and ABM if available. */
1299 	if (dmcu && abm) {
1300 		dmcu->funcs->dmcu_init(dmcu);
1301 		abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1302 	}
1303 
1304 	if (!adev->dm.dc->ctx->dmub_srv)
1305 		adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1306 	if (!adev->dm.dc->ctx->dmub_srv) {
1307 		DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1308 		return -ENOMEM;
1309 	}
1310 
1311 	DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1312 		 adev->dm.dmcub_fw_version);
1313 
1314 	/* Keeping sanity checks off if
1315 	 * DCN31 >= 4.0.59.0
1316 	 * DCN314 >= 8.0.16.0
1317 	 * Otherwise, turn on sanity checks
1318 	 */
1319 	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1320 	case IP_VERSION(3, 1, 2):
1321 	case IP_VERSION(3, 1, 3):
1322 		if (adev->dm.dmcub_fw_version &&
1323 			adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
1324 			adev->dm.dmcub_fw_version < DMUB_FW_VERSION(4, 0, 59))
1325 				adev->dm.dc->debug.sanity_checks = true;
1326 		break;
1327 	case IP_VERSION(3, 1, 4):
1328 		if (adev->dm.dmcub_fw_version &&
1329 			adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
1330 			adev->dm.dmcub_fw_version < DMUB_FW_VERSION(8, 0, 16))
1331 				adev->dm.dc->debug.sanity_checks = true;
1332 		break;
1333 	default:
1334 		break;
1335 	}
1336 
1337 	return 0;
1338 }
1339 
dm_dmub_hw_resume(struct amdgpu_device * adev)1340 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1341 {
1342 	struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1343 	enum dmub_status status;
1344 	bool init;
1345 	int r;
1346 
1347 	if (!dmub_srv) {
1348 		/* DMUB isn't supported on the ASIC. */
1349 		return;
1350 	}
1351 
1352 	status = dmub_srv_is_hw_init(dmub_srv, &init);
1353 	if (status != DMUB_STATUS_OK)
1354 		DRM_WARN("DMUB hardware init check failed: %d\n", status);
1355 
1356 	if (status == DMUB_STATUS_OK && init) {
1357 		/* Wait for firmware load to finish. */
1358 		status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1359 		if (status != DMUB_STATUS_OK)
1360 			DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1361 	} else {
1362 		/* Perform the full hardware initialization. */
1363 		r = dm_dmub_hw_init(adev);
1364 		if (r)
1365 			DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1366 	}
1367 }
1368 
mmhub_read_system_context(struct amdgpu_device * adev,struct dc_phy_addr_space_config * pa_config)1369 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1370 {
1371 	u64 pt_base;
1372 	u32 logical_addr_low;
1373 	u32 logical_addr_high;
1374 	u32 agp_base, agp_bot, agp_top;
1375 	PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1376 
1377 	memset(pa_config, 0, sizeof(*pa_config));
1378 
1379 	agp_base = 0;
1380 	agp_bot = adev->gmc.agp_start >> 24;
1381 	agp_top = adev->gmc.agp_end >> 24;
1382 
1383 	/* AGP aperture is disabled */
1384 	if (agp_bot > agp_top) {
1385 		logical_addr_low = adev->gmc.fb_start >> 18;
1386 		if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
1387 				       AMD_APU_IS_RENOIR |
1388 				       AMD_APU_IS_GREEN_SARDINE))
1389 			/*
1390 			 * Raven2 has a HW issue that it is unable to use the vram which
1391 			 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1392 			 * workaround that increase system aperture high address (add 1)
1393 			 * to get rid of the VM fault and hardware hang.
1394 			 */
1395 			logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1396 		else
1397 			logical_addr_high = adev->gmc.fb_end >> 18;
1398 	} else {
1399 		logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1400 		if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
1401 				       AMD_APU_IS_RENOIR |
1402 				       AMD_APU_IS_GREEN_SARDINE))
1403 			/*
1404 			 * Raven2 has a HW issue that it is unable to use the vram which
1405 			 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1406 			 * workaround that increase system aperture high address (add 1)
1407 			 * to get rid of the VM fault and hardware hang.
1408 			 */
1409 			logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1410 		else
1411 			logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1412 	}
1413 
1414 	pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1415 
1416 	page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
1417 						   AMDGPU_GPU_PAGE_SHIFT);
1418 	page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
1419 						  AMDGPU_GPU_PAGE_SHIFT);
1420 	page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
1421 						 AMDGPU_GPU_PAGE_SHIFT);
1422 	page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
1423 						AMDGPU_GPU_PAGE_SHIFT);
1424 	page_table_base.high_part = upper_32_bits(pt_base);
1425 	page_table_base.low_part = lower_32_bits(pt_base);
1426 
1427 	pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1428 	pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1429 
1430 	pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
1431 	pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1432 	pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1433 
1434 	pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1435 	pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1436 	pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1437 
1438 	pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1439 	pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1440 	pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1441 
1442 	pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1443 
1444 }
1445 
force_connector_state(struct amdgpu_dm_connector * aconnector,enum drm_connector_force force_state)1446 static void force_connector_state(
1447 	struct amdgpu_dm_connector *aconnector,
1448 	enum drm_connector_force force_state)
1449 {
1450 	struct drm_connector *connector = &aconnector->base;
1451 
1452 	mutex_lock(&connector->dev->mode_config.mutex);
1453 	aconnector->base.force = force_state;
1454 	mutex_unlock(&connector->dev->mode_config.mutex);
1455 
1456 	mutex_lock(&aconnector->hpd_lock);
1457 	drm_kms_helper_connector_hotplug_event(connector);
1458 	mutex_unlock(&aconnector->hpd_lock);
1459 }
1460 
dm_handle_hpd_rx_offload_work(struct work_struct * work)1461 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1462 {
1463 	struct hpd_rx_irq_offload_work *offload_work;
1464 	struct amdgpu_dm_connector *aconnector;
1465 	struct dc_link *dc_link;
1466 	struct amdgpu_device *adev;
1467 	enum dc_connection_type new_connection_type = dc_connection_none;
1468 	unsigned long flags;
1469 	union test_response test_response;
1470 
1471 	memset(&test_response, 0, sizeof(test_response));
1472 
1473 	offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1474 	aconnector = offload_work->offload_wq->aconnector;
1475 
1476 	if (!aconnector) {
1477 		DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1478 		goto skip;
1479 	}
1480 
1481 	adev = drm_to_adev(aconnector->base.dev);
1482 	dc_link = aconnector->dc_link;
1483 
1484 	mutex_lock(&aconnector->hpd_lock);
1485 	if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1486 		DRM_ERROR("KMS: Failed to detect connector\n");
1487 	mutex_unlock(&aconnector->hpd_lock);
1488 
1489 	if (new_connection_type == dc_connection_none)
1490 		goto skip;
1491 
1492 	if (amdgpu_in_reset(adev))
1493 		goto skip;
1494 
1495 	if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
1496 		offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
1497 		dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);
1498 		spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1499 		offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;
1500 		spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1501 		goto skip;
1502 	}
1503 
1504 	mutex_lock(&adev->dm.dc_lock);
1505 	if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1506 		dc_link_dp_handle_automated_test(dc_link);
1507 
1508 		if (aconnector->timing_changed) {
1509 			/* force connector disconnect and reconnect */
1510 			force_connector_state(aconnector, DRM_FORCE_OFF);
1511 			msleep(100);
1512 			force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1513 		}
1514 
1515 		test_response.bits.ACK = 1;
1516 
1517 		core_link_write_dpcd(
1518 		dc_link,
1519 		DP_TEST_RESPONSE,
1520 		&test_response.raw,
1521 		sizeof(test_response));
1522 	} else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1523 			dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1524 			dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1525 		/* offload_work->data is from handle_hpd_rx_irq->
1526 		 * schedule_hpd_rx_offload_work.this is defer handle
1527 		 * for hpd short pulse. upon here, link status may be
1528 		 * changed, need get latest link status from dpcd
1529 		 * registers. if link status is good, skip run link
1530 		 * training again.
1531 		 */
1532 		union hpd_irq_data irq_data;
1533 
1534 		memset(&irq_data, 0, sizeof(irq_data));
1535 
1536 		/* before dc_link_dp_handle_link_loss, allow new link lost handle
1537 		 * request be added to work queue if link lost at end of dc_link_
1538 		 * dp_handle_link_loss
1539 		 */
1540 		spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1541 		offload_work->offload_wq->is_handling_link_loss = false;
1542 		spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1543 
1544 		if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1545 			dc_link_check_link_loss_status(dc_link, &irq_data))
1546 			dc_link_dp_handle_link_loss(dc_link);
1547 	}
1548 	mutex_unlock(&adev->dm.dc_lock);
1549 
1550 skip:
1551 	kfree(offload_work);
1552 
1553 }
1554 
hpd_rx_irq_create_workqueue(struct dc * dc)1555 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1556 {
1557 	int max_caps = dc->caps.max_links;
1558 	int i = 0;
1559 	struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1560 
1561 	hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1562 
1563 	if (!hpd_rx_offload_wq)
1564 		return NULL;
1565 
1566 
1567 	for (i = 0; i < max_caps; i++) {
1568 		hpd_rx_offload_wq[i].wq =
1569 				    create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1570 
1571 		if (hpd_rx_offload_wq[i].wq == NULL) {
1572 			DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1573 			goto out_err;
1574 		}
1575 
1576 		spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1577 	}
1578 
1579 	return hpd_rx_offload_wq;
1580 
1581 out_err:
1582 	for (i = 0; i < max_caps; i++) {
1583 		if (hpd_rx_offload_wq[i].wq)
1584 			destroy_workqueue(hpd_rx_offload_wq[i].wq);
1585 	}
1586 	kfree(hpd_rx_offload_wq);
1587 	return NULL;
1588 }
1589 
1590 struct amdgpu_stutter_quirk {
1591 	u16 chip_vendor;
1592 	u16 chip_device;
1593 	u16 subsys_vendor;
1594 	u16 subsys_device;
1595 	u8 revision;
1596 };
1597 
1598 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1599 	/* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1600 	{ 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1601 	{ 0, 0, 0, 0, 0 },
1602 };
1603 
dm_should_disable_stutter(struct pci_dev * pdev)1604 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1605 {
1606 	const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1607 
1608 	while (p && p->chip_device != 0) {
1609 		if (pdev->vendor == p->chip_vendor &&
1610 		    pdev->device == p->chip_device &&
1611 		    pdev->subsystem_vendor == p->subsys_vendor &&
1612 		    pdev->subsystem_device == p->subsys_device &&
1613 		    pdev->revision == p->revision) {
1614 			return true;
1615 		}
1616 		++p;
1617 	}
1618 	return false;
1619 }
1620 
1621 struct amdgpu_dm_quirks {
1622 	bool aux_hpd_discon;
1623 	bool support_edp0_on_dp1;
1624 };
1625 
1626 static struct amdgpu_dm_quirks quirk_entries = {
1627 	.aux_hpd_discon = false,
1628 	.support_edp0_on_dp1 = false
1629 };
1630 
edp0_on_dp1_callback(const struct dmi_system_id * id)1631 static int edp0_on_dp1_callback(const struct dmi_system_id *id)
1632 {
1633 	quirk_entries.support_edp0_on_dp1 = true;
1634 	return 0;
1635 }
1636 
aux_hpd_discon_callback(const struct dmi_system_id * id)1637 static int aux_hpd_discon_callback(const struct dmi_system_id *id)
1638 {
1639 	quirk_entries.aux_hpd_discon = true;
1640 	return 0;
1641 }
1642 
1643 static const struct dmi_system_id dmi_quirk_table[] = {
1644 	{
1645 		.callback = aux_hpd_discon_callback,
1646 		.matches = {
1647 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1648 			DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1649 		},
1650 	},
1651 	{
1652 		.callback = aux_hpd_discon_callback,
1653 		.matches = {
1654 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1655 			DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1656 		},
1657 	},
1658 	{
1659 		.callback = aux_hpd_discon_callback,
1660 		.matches = {
1661 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1662 			DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1663 		},
1664 	},
1665 	{
1666 		.callback = aux_hpd_discon_callback,
1667 		.matches = {
1668 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1669 			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1670 		},
1671 	},
1672 	{
1673 		.callback = aux_hpd_discon_callback,
1674 		.matches = {
1675 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1676 			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1677 		},
1678 	},
1679 	{
1680 		.callback = aux_hpd_discon_callback,
1681 		.matches = {
1682 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1683 			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1684 		},
1685 	},
1686 	{
1687 		.callback = aux_hpd_discon_callback,
1688 		.matches = {
1689 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1690 			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1691 		},
1692 	},
1693 	{
1694 		.callback = aux_hpd_discon_callback,
1695 		.matches = {
1696 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1697 			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1698 		},
1699 	},
1700 	{
1701 		.callback = aux_hpd_discon_callback,
1702 		.matches = {
1703 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1704 			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1705 		},
1706 	},
1707 	{
1708 		.callback = edp0_on_dp1_callback,
1709 		.matches = {
1710 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1711 			DMI_MATCH(DMI_PRODUCT_NAME, "HP Elite mt645 G8 Mobile Thin Client"),
1712 		},
1713 	},
1714 	{
1715 		.callback = edp0_on_dp1_callback,
1716 		.matches = {
1717 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1718 			DMI_MATCH(DMI_PRODUCT_NAME, "HP EliteBook 665 16 inch G11 Notebook PC"),
1719 		},
1720 	},
1721 	{}
1722 	/* TODO: refactor this from a fixed table to a dynamic option */
1723 };
1724 
retrieve_dmi_info(struct amdgpu_display_manager * dm,struct dc_init_data * init_data)1725 static void retrieve_dmi_info(struct amdgpu_display_manager *dm, struct dc_init_data *init_data)
1726 {
1727 	int dmi_id;
1728 	struct drm_device *dev = dm->ddev;
1729 
1730 	dm->aux_hpd_discon_quirk = false;
1731 	init_data->flags.support_edp0_on_dp1 = false;
1732 
1733 	dmi_id = dmi_check_system(dmi_quirk_table);
1734 
1735 	if (!dmi_id)
1736 		return;
1737 
1738 	if (quirk_entries.aux_hpd_discon) {
1739 		dm->aux_hpd_discon_quirk = true;
1740 		drm_info(dev, "aux_hpd_discon_quirk attached\n");
1741 	}
1742 	if (quirk_entries.support_edp0_on_dp1) {
1743 		init_data->flags.support_edp0_on_dp1 = true;
1744 		drm_info(dev, "aux_hpd_discon_quirk attached\n");
1745 	}
1746 }
1747 
1748 void*
dm_allocate_gpu_mem(struct amdgpu_device * adev,enum dc_gpu_mem_alloc_type type,size_t size,long long * addr)1749 dm_allocate_gpu_mem(
1750 		struct amdgpu_device *adev,
1751 		enum dc_gpu_mem_alloc_type type,
1752 		size_t size,
1753 		long long *addr)
1754 {
1755 	struct dal_allocation *da;
1756 	u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ?
1757 		AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM;
1758 	int ret;
1759 
1760 	da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL);
1761 	if (!da)
1762 		return NULL;
1763 
1764 	ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
1765 				      domain, &da->bo,
1766 				      &da->gpu_addr, &da->cpu_ptr);
1767 
1768 	*addr = da->gpu_addr;
1769 
1770 	if (ret) {
1771 		kfree(da);
1772 		return NULL;
1773 	}
1774 
1775 	/* add da to list in dm */
1776 	list_add(&da->list, &adev->dm.da_list);
1777 
1778 	return da->cpu_ptr;
1779 }
1780 
1781 void
dm_free_gpu_mem(struct amdgpu_device * adev,enum dc_gpu_mem_alloc_type type,void * pvMem)1782 dm_free_gpu_mem(
1783 		struct amdgpu_device *adev,
1784 		enum dc_gpu_mem_alloc_type type,
1785 		void *pvMem)
1786 {
1787 	struct dal_allocation *da;
1788 
1789 	/* walk the da list in DM */
1790 	list_for_each_entry(da, &adev->dm.da_list, list) {
1791 		if (pvMem == da->cpu_ptr) {
1792 			amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr);
1793 			list_del(&da->list);
1794 			kfree(da);
1795 			break;
1796 		}
1797 	}
1798 
1799 }
1800 
1801 static enum dmub_status
dm_dmub_send_vbios_gpint_command(struct amdgpu_device * adev,enum dmub_gpint_command command_code,uint16_t param,uint32_t timeout_us)1802 dm_dmub_send_vbios_gpint_command(struct amdgpu_device *adev,
1803 				 enum dmub_gpint_command command_code,
1804 				 uint16_t param,
1805 				 uint32_t timeout_us)
1806 {
1807 	union dmub_gpint_data_register reg, test;
1808 	uint32_t i;
1809 
1810 	/* Assume that VBIOS DMUB is ready to take commands */
1811 
1812 	reg.bits.status = 1;
1813 	reg.bits.command_code = command_code;
1814 	reg.bits.param = param;
1815 
1816 	cgs_write_register(adev->dm.cgs_device, 0x34c0 + 0x01f8, reg.all);
1817 
1818 	for (i = 0; i < timeout_us; ++i) {
1819 		udelay(1);
1820 
1821 		/* Check if our GPINT got acked */
1822 		reg.bits.status = 0;
1823 		test = (union dmub_gpint_data_register)
1824 			cgs_read_register(adev->dm.cgs_device, 0x34c0 + 0x01f8);
1825 
1826 		if (test.all == reg.all)
1827 			return DMUB_STATUS_OK;
1828 	}
1829 
1830 	return DMUB_STATUS_TIMEOUT;
1831 }
1832 
dm_dmub_get_vbios_bounding_box(struct amdgpu_device * adev)1833 static struct dml2_soc_bb *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *adev)
1834 {
1835 	struct dml2_soc_bb *bb;
1836 	long long addr;
1837 	int i = 0;
1838 	uint16_t chunk;
1839 	enum dmub_gpint_command send_addrs[] = {
1840 		DMUB_GPINT__SET_BB_ADDR_WORD0,
1841 		DMUB_GPINT__SET_BB_ADDR_WORD1,
1842 		DMUB_GPINT__SET_BB_ADDR_WORD2,
1843 		DMUB_GPINT__SET_BB_ADDR_WORD3,
1844 	};
1845 	enum dmub_status ret;
1846 
1847 	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1848 	case IP_VERSION(4, 0, 1):
1849 		break;
1850 	default:
1851 		return NULL;
1852 	}
1853 
1854 	bb =  dm_allocate_gpu_mem(adev,
1855 				  DC_MEM_ALLOC_TYPE_GART,
1856 				  sizeof(struct dml2_soc_bb),
1857 				  &addr);
1858 	if (!bb)
1859 		return NULL;
1860 
1861 	for (i = 0; i < 4; i++) {
1862 		/* Extract 16-bit chunk */
1863 		chunk = ((uint64_t) addr >> (i * 16)) & 0xFFFF;
1864 		/* Send the chunk */
1865 		ret = dm_dmub_send_vbios_gpint_command(adev, send_addrs[i], chunk, 30000);
1866 		if (ret != DMUB_STATUS_OK)
1867 			goto free_bb;
1868 	}
1869 
1870 	/* Now ask DMUB to copy the bb */
1871 	ret = dm_dmub_send_vbios_gpint_command(adev, DMUB_GPINT__BB_COPY, 1, 200000);
1872 	if (ret != DMUB_STATUS_OK)
1873 		goto free_bb;
1874 
1875 	return bb;
1876 
1877 free_bb:
1878 	dm_free_gpu_mem(adev, DC_MEM_ALLOC_TYPE_GART, (void *) bb);
1879 	return NULL;
1880 
1881 }
1882 
dm_get_default_ips_mode(struct amdgpu_device * adev)1883 static enum dmub_ips_disable_type dm_get_default_ips_mode(
1884 	struct amdgpu_device *adev)
1885 {
1886 	enum dmub_ips_disable_type ret = DMUB_IPS_ENABLE;
1887 
1888 	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1889 	case IP_VERSION(3, 5, 0):
1890 		/*
1891 		 * On DCN35 systems with Z8 enabled, it's possible for IPS2 + Z8 to
1892 		 * cause a hard hang. A fix exists for newer PMFW.
1893 		 *
1894 		 * As a workaround, for non-fixed PMFW, force IPS1+RCG as the deepest
1895 		 * IPS state in all cases, except for s0ix and all displays off (DPMS),
1896 		 * where IPS2 is allowed.
1897 		 *
1898 		 * When checking pmfw version, use the major and minor only.
1899 		 */
1900 		if ((adev->pm.fw_version & 0x00FFFF00) < 0x005D6300)
1901 			ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
1902 		else if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(11, 5, 0))
1903 			/*
1904 			 * Other ASICs with DCN35 that have residency issues with
1905 			 * IPS2 in idle.
1906 			 * We want them to use IPS2 only in display off cases.
1907 			 */
1908 			ret =  DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
1909 		break;
1910 	case IP_VERSION(3, 5, 1):
1911 		ret =  DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
1912 		break;
1913 	default:
1914 		/* ASICs older than DCN35 do not have IPSs */
1915 		if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 5, 0))
1916 			ret = DMUB_IPS_DISABLE_ALL;
1917 		break;
1918 	}
1919 
1920 	return ret;
1921 }
1922 
amdgpu_dm_init(struct amdgpu_device * adev)1923 static int amdgpu_dm_init(struct amdgpu_device *adev)
1924 {
1925 	struct dc_init_data init_data;
1926 	struct dc_callback_init init_params;
1927 	int r;
1928 
1929 	adev->dm.ddev = adev_to_drm(adev);
1930 	adev->dm.adev = adev;
1931 
1932 	/* Zero all the fields */
1933 	memset(&init_data, 0, sizeof(init_data));
1934 	memset(&init_params, 0, sizeof(init_params));
1935 
1936 	mutex_init(&adev->dm.dpia_aux_lock);
1937 	mutex_init(&adev->dm.dc_lock);
1938 	mutex_init(&adev->dm.audio_lock);
1939 
1940 	if (amdgpu_dm_irq_init(adev)) {
1941 		DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1942 		goto error;
1943 	}
1944 
1945 	init_data.asic_id.chip_family = adev->family;
1946 
1947 	init_data.asic_id.pci_revision_id = adev->pdev->revision;
1948 	init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1949 	init_data.asic_id.chip_id = adev->pdev->device;
1950 
1951 	init_data.asic_id.vram_width = adev->gmc.vram_width;
1952 	/* TODO: initialize init_data.asic_id.vram_type here!!!! */
1953 	init_data.asic_id.atombios_base_address =
1954 		adev->mode_info.atom_context->bios;
1955 
1956 	init_data.driver = adev;
1957 
1958 	/* cgs_device was created in dm_sw_init() */
1959 	init_data.cgs_device = adev->dm.cgs_device;
1960 
1961 	init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1962 
1963 	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1964 	case IP_VERSION(2, 1, 0):
1965 		switch (adev->dm.dmcub_fw_version) {
1966 		case 0: /* development */
1967 		case 0x1: /* linux-firmware.git hash 6d9f399 */
1968 		case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1969 			init_data.flags.disable_dmcu = false;
1970 			break;
1971 		default:
1972 			init_data.flags.disable_dmcu = true;
1973 		}
1974 		break;
1975 	case IP_VERSION(2, 0, 3):
1976 		init_data.flags.disable_dmcu = true;
1977 		break;
1978 	default:
1979 		break;
1980 	}
1981 
1982 	/* APU support S/G display by default except:
1983 	 * ASICs before Carrizo,
1984 	 * RAVEN1 (Users reported stability issue)
1985 	 */
1986 
1987 	if (adev->asic_type < CHIP_CARRIZO) {
1988 		init_data.flags.gpu_vm_support = false;
1989 	} else if (adev->asic_type == CHIP_RAVEN) {
1990 		if (adev->apu_flags & AMD_APU_IS_RAVEN)
1991 			init_data.flags.gpu_vm_support = false;
1992 		else
1993 			init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0);
1994 	} else {
1995 		if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(2, 0, 3))
1996 			init_data.flags.gpu_vm_support = (amdgpu_sg_display == 1);
1997 		else
1998 			init_data.flags.gpu_vm_support =
1999 				(amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU);
2000 	}
2001 
2002 	adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support;
2003 
2004 	if (amdgpu_dc_feature_mask & DC_FBC_MASK)
2005 		init_data.flags.fbc_support = true;
2006 
2007 	if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
2008 		init_data.flags.multi_mon_pp_mclk_switch = true;
2009 
2010 	if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
2011 		init_data.flags.disable_fractional_pwm = true;
2012 
2013 	if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
2014 		init_data.flags.edp_no_power_sequencing = true;
2015 
2016 	if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
2017 		init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
2018 	if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
2019 		init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
2020 
2021 	init_data.flags.seamless_boot_edp_requested = false;
2022 
2023 	if (amdgpu_device_seamless_boot_supported(adev)) {
2024 		init_data.flags.seamless_boot_edp_requested = true;
2025 		init_data.flags.allow_seamless_boot_optimization = true;
2026 		DRM_INFO("Seamless boot condition check passed\n");
2027 	}
2028 
2029 	init_data.flags.enable_mipi_converter_optimization = true;
2030 
2031 	init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
2032 	init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
2033 	init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
2034 
2035 	if (amdgpu_dc_debug_mask & DC_DISABLE_IPS)
2036 		init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;
2037 	else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS_DYNAMIC)
2038 		init_data.flags.disable_ips = DMUB_IPS_DISABLE_DYNAMIC;
2039 	else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS2_DYNAMIC)
2040 		init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
2041 	else if (amdgpu_dc_debug_mask & DC_FORCE_IPS_ENABLE)
2042 		init_data.flags.disable_ips = DMUB_IPS_ENABLE;
2043 	else
2044 		init_data.flags.disable_ips = dm_get_default_ips_mode(adev);
2045 
2046 	init_data.flags.disable_ips_in_vpb = 0;
2047 
2048 	/* Enable DWB for tested platforms only */
2049 	if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0))
2050 		init_data.num_virtual_links = 1;
2051 
2052 	retrieve_dmi_info(&adev->dm, &init_data);
2053 
2054 	if (adev->dm.bb_from_dmub)
2055 		init_data.bb_from_dmub = adev->dm.bb_from_dmub;
2056 	else
2057 		init_data.bb_from_dmub = NULL;
2058 
2059 	/* Display Core create. */
2060 	adev->dm.dc = dc_create(&init_data);
2061 
2062 	if (adev->dm.dc) {
2063 		DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
2064 			 dce_version_to_string(adev->dm.dc->ctx->dce_version));
2065 	} else {
2066 		DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
2067 		goto error;
2068 	}
2069 
2070 	if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
2071 		adev->dm.dc->debug.force_single_disp_pipe_split = false;
2072 		adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
2073 	}
2074 
2075 	if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2076 		adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2077 	if (dm_should_disable_stutter(adev->pdev))
2078 		adev->dm.dc->debug.disable_stutter = true;
2079 
2080 	if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
2081 		adev->dm.dc->debug.disable_stutter = true;
2082 
2083 	if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
2084 		adev->dm.dc->debug.disable_dsc = true;
2085 
2086 	if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
2087 		adev->dm.dc->debug.disable_clock_gate = true;
2088 
2089 	if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
2090 		adev->dm.dc->debug.force_subvp_mclk_switch = true;
2091 
2092 	if (amdgpu_dc_debug_mask & DC_DISABLE_SUBVP)
2093 		adev->dm.dc->debug.force_disable_subvp = true;
2094 
2095 	if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) {
2096 		adev->dm.dc->debug.using_dml2 = true;
2097 		adev->dm.dc->debug.using_dml21 = true;
2098 	}
2099 
2100 	adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
2101 
2102 	/* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
2103 	adev->dm.dc->debug.ignore_cable_id = true;
2104 
2105 	if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
2106 		DRM_INFO("DP-HDMI FRL PCON supported\n");
2107 
2108 	r = dm_dmub_hw_init(adev);
2109 	if (r) {
2110 		DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2111 		goto error;
2112 	}
2113 
2114 	dc_hardware_init(adev->dm.dc);
2115 
2116 	adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
2117 	if (!adev->dm.hpd_rx_offload_wq) {
2118 		DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
2119 		goto error;
2120 	}
2121 
2122 	if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
2123 		struct dc_phy_addr_space_config pa_config;
2124 
2125 		mmhub_read_system_context(adev, &pa_config);
2126 
2127 		// Call the DC init_memory func
2128 		dc_setup_system_context(adev->dm.dc, &pa_config);
2129 	}
2130 
2131 	adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
2132 	if (!adev->dm.freesync_module) {
2133 		DRM_ERROR(
2134 		"amdgpu: failed to initialize freesync_module.\n");
2135 	} else
2136 		DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
2137 				adev->dm.freesync_module);
2138 
2139 	amdgpu_dm_init_color_mod();
2140 
2141 	if (adev->dm.dc->caps.max_links > 0) {
2142 		adev->dm.vblank_control_workqueue =
2143 			create_singlethread_workqueue("dm_vblank_control_workqueue");
2144 		if (!adev->dm.vblank_control_workqueue)
2145 			DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
2146 	}
2147 
2148 	if (adev->dm.dc->caps.ips_support &&
2149 	    adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL)
2150 		adev->dm.idle_workqueue = idle_create_workqueue(adev);
2151 
2152 	if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
2153 		adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
2154 
2155 		if (!adev->dm.hdcp_workqueue)
2156 			DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
2157 		else
2158 			DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
2159 
2160 		dc_init_callbacks(adev->dm.dc, &init_params);
2161 	}
2162 	if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2163 		init_completion(&adev->dm.dmub_aux_transfer_done);
2164 		adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
2165 		if (!adev->dm.dmub_notify) {
2166 			DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
2167 			goto error;
2168 		}
2169 
2170 		adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
2171 		if (!adev->dm.delayed_hpd_wq) {
2172 			DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
2173 			goto error;
2174 		}
2175 
2176 		amdgpu_dm_outbox_init(adev);
2177 		if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
2178 			dmub_aux_setconfig_callback, false)) {
2179 			DRM_ERROR("amdgpu: fail to register dmub aux callback");
2180 			goto error;
2181 		}
2182 		/* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
2183 		 * It is expected that DMUB will resend any pending notifications at this point. Note
2184 		 * that hpd and hpd_irq handler registration are deferred to register_hpd_handlers() to
2185 		 * align legacy interface initialization sequence. Connection status will be proactivly
2186 		 * detected once in the amdgpu_dm_initialize_drm_device.
2187 		 */
2188 		dc_enable_dmub_outbox(adev->dm.dc);
2189 
2190 		/* DPIA trace goes to dmesg logs only if outbox is enabled */
2191 		if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE)
2192 			dc_dmub_srv_enable_dpia_trace(adev->dm.dc);
2193 	}
2194 
2195 	if (amdgpu_dm_initialize_drm_device(adev)) {
2196 		DRM_ERROR(
2197 		"amdgpu: failed to initialize sw for display support.\n");
2198 		goto error;
2199 	}
2200 
2201 	/* create fake encoders for MST */
2202 	dm_dp_create_fake_mst_encoders(adev);
2203 
2204 	/* TODO: Add_display_info? */
2205 
2206 	/* TODO use dynamic cursor width */
2207 	adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
2208 	adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
2209 
2210 	if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
2211 		DRM_ERROR(
2212 		"amdgpu: failed to initialize sw for display support.\n");
2213 		goto error;
2214 	}
2215 
2216 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
2217 	amdgpu_dm_crtc_secure_display_create_contexts(adev);
2218 	if (!adev->dm.secure_display_ctx.crtc_ctx)
2219 		DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
2220 
2221 	if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 0, 1))
2222 		adev->dm.secure_display_ctx.support_mul_roi = true;
2223 
2224 #endif
2225 
2226 	DRM_DEBUG_DRIVER("KMS initialized.\n");
2227 
2228 	return 0;
2229 error:
2230 	amdgpu_dm_fini(adev);
2231 
2232 	return -EINVAL;
2233 }
2234 
amdgpu_dm_early_fini(struct amdgpu_ip_block * ip_block)2235 static int amdgpu_dm_early_fini(struct amdgpu_ip_block *ip_block)
2236 {
2237 	struct amdgpu_device *adev = ip_block->adev;
2238 
2239 	amdgpu_dm_audio_fini(adev);
2240 
2241 	return 0;
2242 }
2243 
amdgpu_dm_fini(struct amdgpu_device * adev)2244 static void amdgpu_dm_fini(struct amdgpu_device *adev)
2245 {
2246 	int i;
2247 
2248 	if (adev->dm.vblank_control_workqueue) {
2249 		destroy_workqueue(adev->dm.vblank_control_workqueue);
2250 		adev->dm.vblank_control_workqueue = NULL;
2251 	}
2252 
2253 	if (adev->dm.idle_workqueue) {
2254 		if (adev->dm.idle_workqueue->running) {
2255 			adev->dm.idle_workqueue->enable = false;
2256 			flush_work(&adev->dm.idle_workqueue->work);
2257 		}
2258 
2259 		kfree(adev->dm.idle_workqueue);
2260 		adev->dm.idle_workqueue = NULL;
2261 	}
2262 
2263 	amdgpu_dm_destroy_drm_device(&adev->dm);
2264 
2265 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
2266 	if (adev->dm.secure_display_ctx.crtc_ctx) {
2267 		for (i = 0; i < adev->mode_info.num_crtc; i++) {
2268 			if (adev->dm.secure_display_ctx.crtc_ctx[i].crtc) {
2269 				flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].notify_ta_work);
2270 				flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].forward_roi_work);
2271 			}
2272 		}
2273 		kfree(adev->dm.secure_display_ctx.crtc_ctx);
2274 		adev->dm.secure_display_ctx.crtc_ctx = NULL;
2275 	}
2276 #endif
2277 	if (adev->dm.hdcp_workqueue) {
2278 		hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
2279 		adev->dm.hdcp_workqueue = NULL;
2280 	}
2281 
2282 	if (adev->dm.dc) {
2283 		dc_deinit_callbacks(adev->dm.dc);
2284 		dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
2285 		if (dc_enable_dmub_notifications(adev->dm.dc)) {
2286 			kfree(adev->dm.dmub_notify);
2287 			adev->dm.dmub_notify = NULL;
2288 			destroy_workqueue(adev->dm.delayed_hpd_wq);
2289 			adev->dm.delayed_hpd_wq = NULL;
2290 		}
2291 	}
2292 
2293 	if (adev->dm.dmub_bo)
2294 		amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
2295 				      &adev->dm.dmub_bo_gpu_addr,
2296 				      &adev->dm.dmub_bo_cpu_addr);
2297 
2298 	if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) {
2299 		for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
2300 			if (adev->dm.hpd_rx_offload_wq[i].wq) {
2301 				destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
2302 				adev->dm.hpd_rx_offload_wq[i].wq = NULL;
2303 			}
2304 		}
2305 
2306 		kfree(adev->dm.hpd_rx_offload_wq);
2307 		adev->dm.hpd_rx_offload_wq = NULL;
2308 	}
2309 
2310 	/* DC Destroy TODO: Replace destroy DAL */
2311 	if (adev->dm.dc)
2312 		dc_destroy(&adev->dm.dc);
2313 	/*
2314 	 * TODO: pageflip, vlank interrupt
2315 	 *
2316 	 * amdgpu_dm_irq_fini(adev);
2317 	 */
2318 
2319 	if (adev->dm.cgs_device) {
2320 		amdgpu_cgs_destroy_device(adev->dm.cgs_device);
2321 		adev->dm.cgs_device = NULL;
2322 	}
2323 	if (adev->dm.freesync_module) {
2324 		mod_freesync_destroy(adev->dm.freesync_module);
2325 		adev->dm.freesync_module = NULL;
2326 	}
2327 
2328 	mutex_destroy(&adev->dm.audio_lock);
2329 	mutex_destroy(&adev->dm.dc_lock);
2330 	mutex_destroy(&adev->dm.dpia_aux_lock);
2331 }
2332 
load_dmcu_fw(struct amdgpu_device * adev)2333 static int load_dmcu_fw(struct amdgpu_device *adev)
2334 {
2335 	const char *fw_name_dmcu = NULL;
2336 	int r;
2337 	const struct dmcu_firmware_header_v1_0 *hdr;
2338 
2339 	switch (adev->asic_type) {
2340 #if defined(CONFIG_DRM_AMD_DC_SI)
2341 	case CHIP_TAHITI:
2342 	case CHIP_PITCAIRN:
2343 	case CHIP_VERDE:
2344 	case CHIP_OLAND:
2345 #endif
2346 	case CHIP_BONAIRE:
2347 	case CHIP_HAWAII:
2348 	case CHIP_KAVERI:
2349 	case CHIP_KABINI:
2350 	case CHIP_MULLINS:
2351 	case CHIP_TONGA:
2352 	case CHIP_FIJI:
2353 	case CHIP_CARRIZO:
2354 	case CHIP_STONEY:
2355 	case CHIP_POLARIS11:
2356 	case CHIP_POLARIS10:
2357 	case CHIP_POLARIS12:
2358 	case CHIP_VEGAM:
2359 	case CHIP_VEGA10:
2360 	case CHIP_VEGA12:
2361 	case CHIP_VEGA20:
2362 		return 0;
2363 	case CHIP_NAVI12:
2364 		fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
2365 		break;
2366 	case CHIP_RAVEN:
2367 		if (ASICREV_IS_PICASSO(adev->external_rev_id))
2368 			fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
2369 		else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
2370 			fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
2371 		else
2372 			return 0;
2373 		break;
2374 	default:
2375 		switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2376 		case IP_VERSION(2, 0, 2):
2377 		case IP_VERSION(2, 0, 3):
2378 		case IP_VERSION(2, 0, 0):
2379 		case IP_VERSION(2, 1, 0):
2380 		case IP_VERSION(3, 0, 0):
2381 		case IP_VERSION(3, 0, 2):
2382 		case IP_VERSION(3, 0, 3):
2383 		case IP_VERSION(3, 0, 1):
2384 		case IP_VERSION(3, 1, 2):
2385 		case IP_VERSION(3, 1, 3):
2386 		case IP_VERSION(3, 1, 4):
2387 		case IP_VERSION(3, 1, 5):
2388 		case IP_VERSION(3, 1, 6):
2389 		case IP_VERSION(3, 2, 0):
2390 		case IP_VERSION(3, 2, 1):
2391 		case IP_VERSION(3, 5, 0):
2392 		case IP_VERSION(3, 5, 1):
2393 		case IP_VERSION(4, 0, 1):
2394 			return 0;
2395 		default:
2396 			break;
2397 		}
2398 		DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2399 		return -EINVAL;
2400 	}
2401 
2402 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2403 		DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2404 		return 0;
2405 	}
2406 
2407 	r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, AMDGPU_UCODE_REQUIRED,
2408 				 "%s", fw_name_dmcu);
2409 	if (r == -ENODEV) {
2410 		/* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2411 		DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2412 		adev->dm.fw_dmcu = NULL;
2413 		return 0;
2414 	}
2415 	if (r) {
2416 		dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2417 			fw_name_dmcu);
2418 		amdgpu_ucode_release(&adev->dm.fw_dmcu);
2419 		return r;
2420 	}
2421 
2422 	hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2423 	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2424 	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2425 	adev->firmware.fw_size +=
2426 		ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2427 
2428 	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2429 	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2430 	adev->firmware.fw_size +=
2431 		ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2432 
2433 	adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2434 
2435 	DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2436 
2437 	return 0;
2438 }
2439 
amdgpu_dm_dmub_reg_read(void * ctx,uint32_t address)2440 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2441 {
2442 	struct amdgpu_device *adev = ctx;
2443 
2444 	return dm_read_reg(adev->dm.dc->ctx, address);
2445 }
2446 
amdgpu_dm_dmub_reg_write(void * ctx,uint32_t address,uint32_t value)2447 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2448 				     uint32_t value)
2449 {
2450 	struct amdgpu_device *adev = ctx;
2451 
2452 	return dm_write_reg(adev->dm.dc->ctx, address, value);
2453 }
2454 
dm_dmub_sw_init(struct amdgpu_device * adev)2455 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2456 {
2457 	struct dmub_srv_create_params create_params;
2458 	struct dmub_srv_region_params region_params;
2459 	struct dmub_srv_region_info region_info;
2460 	struct dmub_srv_memory_params memory_params;
2461 	struct dmub_srv_fb_info *fb_info;
2462 	struct dmub_srv *dmub_srv;
2463 	const struct dmcub_firmware_header_v1_0 *hdr;
2464 	enum dmub_asic dmub_asic;
2465 	enum dmub_status status;
2466 	static enum dmub_window_memory_type window_memory_type[DMUB_WINDOW_TOTAL] = {
2467 		DMUB_WINDOW_MEMORY_TYPE_FB,		//DMUB_WINDOW_0_INST_CONST
2468 		DMUB_WINDOW_MEMORY_TYPE_FB,		//DMUB_WINDOW_1_STACK
2469 		DMUB_WINDOW_MEMORY_TYPE_FB,		//DMUB_WINDOW_2_BSS_DATA
2470 		DMUB_WINDOW_MEMORY_TYPE_FB,		//DMUB_WINDOW_3_VBIOS
2471 		DMUB_WINDOW_MEMORY_TYPE_FB,		//DMUB_WINDOW_4_MAILBOX
2472 		DMUB_WINDOW_MEMORY_TYPE_FB,		//DMUB_WINDOW_5_TRACEBUFF
2473 		DMUB_WINDOW_MEMORY_TYPE_FB,		//DMUB_WINDOW_6_FW_STATE
2474 		DMUB_WINDOW_MEMORY_TYPE_FB,		//DMUB_WINDOW_7_SCRATCH_MEM
2475 		DMUB_WINDOW_MEMORY_TYPE_FB,		//DMUB_WINDOW_SHARED_STATE
2476 	};
2477 	int r;
2478 
2479 	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2480 	case IP_VERSION(2, 1, 0):
2481 		dmub_asic = DMUB_ASIC_DCN21;
2482 		break;
2483 	case IP_VERSION(3, 0, 0):
2484 		dmub_asic = DMUB_ASIC_DCN30;
2485 		break;
2486 	case IP_VERSION(3, 0, 1):
2487 		dmub_asic = DMUB_ASIC_DCN301;
2488 		break;
2489 	case IP_VERSION(3, 0, 2):
2490 		dmub_asic = DMUB_ASIC_DCN302;
2491 		break;
2492 	case IP_VERSION(3, 0, 3):
2493 		dmub_asic = DMUB_ASIC_DCN303;
2494 		break;
2495 	case IP_VERSION(3, 1, 2):
2496 	case IP_VERSION(3, 1, 3):
2497 		dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2498 		break;
2499 	case IP_VERSION(3, 1, 4):
2500 		dmub_asic = DMUB_ASIC_DCN314;
2501 		break;
2502 	case IP_VERSION(3, 1, 5):
2503 		dmub_asic = DMUB_ASIC_DCN315;
2504 		break;
2505 	case IP_VERSION(3, 1, 6):
2506 		dmub_asic = DMUB_ASIC_DCN316;
2507 		break;
2508 	case IP_VERSION(3, 2, 0):
2509 		dmub_asic = DMUB_ASIC_DCN32;
2510 		break;
2511 	case IP_VERSION(3, 2, 1):
2512 		dmub_asic = DMUB_ASIC_DCN321;
2513 		break;
2514 	case IP_VERSION(3, 5, 0):
2515 	case IP_VERSION(3, 5, 1):
2516 		dmub_asic = DMUB_ASIC_DCN35;
2517 		break;
2518 	case IP_VERSION(4, 0, 1):
2519 		dmub_asic = DMUB_ASIC_DCN401;
2520 		break;
2521 
2522 	default:
2523 		/* ASIC doesn't support DMUB. */
2524 		return 0;
2525 	}
2526 
2527 	hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2528 	adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2529 
2530 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2531 		adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2532 			AMDGPU_UCODE_ID_DMCUB;
2533 		adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2534 			adev->dm.dmub_fw;
2535 		adev->firmware.fw_size +=
2536 			ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2537 
2538 		DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2539 			 adev->dm.dmcub_fw_version);
2540 	}
2541 
2542 
2543 	adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2544 	dmub_srv = adev->dm.dmub_srv;
2545 
2546 	if (!dmub_srv) {
2547 		DRM_ERROR("Failed to allocate DMUB service!\n");
2548 		return -ENOMEM;
2549 	}
2550 
2551 	memset(&create_params, 0, sizeof(create_params));
2552 	create_params.user_ctx = adev;
2553 	create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2554 	create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2555 	create_params.asic = dmub_asic;
2556 
2557 	/* Create the DMUB service. */
2558 	status = dmub_srv_create(dmub_srv, &create_params);
2559 	if (status != DMUB_STATUS_OK) {
2560 		DRM_ERROR("Error creating DMUB service: %d\n", status);
2561 		return -EINVAL;
2562 	}
2563 
2564 	/* Calculate the size of all the regions for the DMUB service. */
2565 	memset(&region_params, 0, sizeof(region_params));
2566 
2567 	region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2568 					PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2569 	region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2570 	region_params.vbios_size = adev->bios_size;
2571 	region_params.fw_bss_data = region_params.bss_data_size ?
2572 		adev->dm.dmub_fw->data +
2573 		le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2574 		le32_to_cpu(hdr->inst_const_bytes) : NULL;
2575 	region_params.fw_inst_const =
2576 		adev->dm.dmub_fw->data +
2577 		le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2578 		PSP_HEADER_BYTES;
2579 	region_params.window_memory_type = window_memory_type;
2580 
2581 	status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2582 					   &region_info);
2583 
2584 	if (status != DMUB_STATUS_OK) {
2585 		DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2586 		return -EINVAL;
2587 	}
2588 
2589 	/*
2590 	 * Allocate a framebuffer based on the total size of all the regions.
2591 	 * TODO: Move this into GART.
2592 	 */
2593 	r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2594 				    AMDGPU_GEM_DOMAIN_VRAM |
2595 				    AMDGPU_GEM_DOMAIN_GTT,
2596 				    &adev->dm.dmub_bo,
2597 				    &adev->dm.dmub_bo_gpu_addr,
2598 				    &adev->dm.dmub_bo_cpu_addr);
2599 	if (r)
2600 		return r;
2601 
2602 	/* Rebase the regions on the framebuffer address. */
2603 	memset(&memory_params, 0, sizeof(memory_params));
2604 	memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr;
2605 	memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr;
2606 	memory_params.region_info = &region_info;
2607 	memory_params.window_memory_type = window_memory_type;
2608 
2609 	adev->dm.dmub_fb_info =
2610 		kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2611 	fb_info = adev->dm.dmub_fb_info;
2612 
2613 	if (!fb_info) {
2614 		DRM_ERROR(
2615 			"Failed to allocate framebuffer info for DMUB service!\n");
2616 		return -ENOMEM;
2617 	}
2618 
2619 	status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info);
2620 	if (status != DMUB_STATUS_OK) {
2621 		DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2622 		return -EINVAL;
2623 	}
2624 
2625 	adev->dm.bb_from_dmub = dm_dmub_get_vbios_bounding_box(adev);
2626 
2627 	return 0;
2628 }
2629 
dm_sw_init(struct amdgpu_ip_block * ip_block)2630 static int dm_sw_init(struct amdgpu_ip_block *ip_block)
2631 {
2632 	struct amdgpu_device *adev = ip_block->adev;
2633 	int r;
2634 
2635 	adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
2636 
2637 	if (!adev->dm.cgs_device) {
2638 		DRM_ERROR("amdgpu: failed to create cgs device.\n");
2639 		return -EINVAL;
2640 	}
2641 
2642 	/* Moved from dm init since we need to use allocations for storing bounding box data */
2643 	INIT_LIST_HEAD(&adev->dm.da_list);
2644 
2645 	r = dm_dmub_sw_init(adev);
2646 	if (r)
2647 		return r;
2648 
2649 	return load_dmcu_fw(adev);
2650 }
2651 
dm_sw_fini(struct amdgpu_ip_block * ip_block)2652 static int dm_sw_fini(struct amdgpu_ip_block *ip_block)
2653 {
2654 	struct amdgpu_device *adev = ip_block->adev;
2655 	struct dal_allocation *da;
2656 
2657 	list_for_each_entry(da, &adev->dm.da_list, list) {
2658 		if (adev->dm.bb_from_dmub == (void *) da->cpu_ptr) {
2659 			amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr);
2660 			list_del(&da->list);
2661 			kfree(da);
2662 			adev->dm.bb_from_dmub = NULL;
2663 			break;
2664 		}
2665 	}
2666 
2667 
2668 	kfree(adev->dm.dmub_fb_info);
2669 	adev->dm.dmub_fb_info = NULL;
2670 
2671 	if (adev->dm.dmub_srv) {
2672 		dmub_srv_destroy(adev->dm.dmub_srv);
2673 		kfree(adev->dm.dmub_srv);
2674 		adev->dm.dmub_srv = NULL;
2675 	}
2676 
2677 	amdgpu_ucode_release(&adev->dm.dmub_fw);
2678 	amdgpu_ucode_release(&adev->dm.fw_dmcu);
2679 
2680 	return 0;
2681 }
2682 
detect_mst_link_for_all_connectors(struct drm_device * dev)2683 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2684 {
2685 	struct amdgpu_dm_connector *aconnector;
2686 	struct drm_connector *connector;
2687 	struct drm_connector_list_iter iter;
2688 	int ret = 0;
2689 
2690 	drm_connector_list_iter_begin(dev, &iter);
2691 	drm_for_each_connector_iter(connector, &iter) {
2692 
2693 		if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2694 			continue;
2695 
2696 		aconnector = to_amdgpu_dm_connector(connector);
2697 		if (aconnector->dc_link->type == dc_connection_mst_branch &&
2698 		    aconnector->mst_mgr.aux) {
2699 			drm_dbg_kms(dev, "DM_MST: starting TM on aconnector: %p [id: %d]\n",
2700 					 aconnector,
2701 					 aconnector->base.base.id);
2702 
2703 			ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2704 			if (ret < 0) {
2705 				drm_err(dev, "DM_MST: Failed to start MST\n");
2706 				aconnector->dc_link->type =
2707 					dc_connection_single;
2708 				ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2709 								     aconnector->dc_link);
2710 				break;
2711 			}
2712 		}
2713 	}
2714 	drm_connector_list_iter_end(&iter);
2715 
2716 	return ret;
2717 }
2718 
dm_late_init(struct amdgpu_ip_block * ip_block)2719 static int dm_late_init(struct amdgpu_ip_block *ip_block)
2720 {
2721 	struct amdgpu_device *adev = ip_block->adev;
2722 
2723 	struct dmcu_iram_parameters params;
2724 	unsigned int linear_lut[16];
2725 	int i;
2726 	struct dmcu *dmcu = NULL;
2727 
2728 	dmcu = adev->dm.dc->res_pool->dmcu;
2729 
2730 	for (i = 0; i < 16; i++)
2731 		linear_lut[i] = 0xFFFF * i / 15;
2732 
2733 	params.set = 0;
2734 	params.backlight_ramping_override = false;
2735 	params.backlight_ramping_start = 0xCCCC;
2736 	params.backlight_ramping_reduction = 0xCCCCCCCC;
2737 	params.backlight_lut_array_size = 16;
2738 	params.backlight_lut_array = linear_lut;
2739 
2740 	/* Min backlight level after ABM reduction,  Don't allow below 1%
2741 	 * 0xFFFF x 0.01 = 0x28F
2742 	 */
2743 	params.min_abm_backlight = 0x28F;
2744 	/* In the case where abm is implemented on dmcub,
2745 	 * dmcu object will be null.
2746 	 * ABM 2.4 and up are implemented on dmcub.
2747 	 */
2748 	if (dmcu) {
2749 		if (!dmcu_load_iram(dmcu, params))
2750 			return -EINVAL;
2751 	} else if (adev->dm.dc->ctx->dmub_srv) {
2752 		struct dc_link *edp_links[MAX_NUM_EDP];
2753 		int edp_num;
2754 
2755 		dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2756 		for (i = 0; i < edp_num; i++) {
2757 			if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2758 				return -EINVAL;
2759 		}
2760 	}
2761 
2762 	return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2763 }
2764 
resume_mst_branch_status(struct drm_dp_mst_topology_mgr * mgr)2765 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
2766 {
2767 	u8 buf[UUID_SIZE];
2768 	guid_t guid;
2769 	int ret;
2770 
2771 	mutex_lock(&mgr->lock);
2772 	if (!mgr->mst_primary)
2773 		goto out_fail;
2774 
2775 	if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
2776 		drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2777 		goto out_fail;
2778 	}
2779 
2780 	ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
2781 				 DP_MST_EN |
2782 				 DP_UP_REQ_EN |
2783 				 DP_UPSTREAM_IS_SRC);
2784 	if (ret < 0) {
2785 		drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
2786 		goto out_fail;
2787 	}
2788 
2789 	/* Some hubs forget their guids after they resume */
2790 	ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf));
2791 	if (ret != sizeof(buf)) {
2792 		drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2793 		goto out_fail;
2794 	}
2795 
2796 	import_guid(&guid, buf);
2797 
2798 	if (guid_is_null(&guid)) {
2799 		guid_gen(&guid);
2800 		export_guid(buf, &guid);
2801 
2802 		ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf));
2803 
2804 		if (ret != sizeof(buf)) {
2805 			drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n");
2806 			goto out_fail;
2807 		}
2808 	}
2809 
2810 	guid_copy(&mgr->mst_primary->guid, &guid);
2811 
2812 out_fail:
2813 	mutex_unlock(&mgr->lock);
2814 }
2815 
hdmi_cec_unset_edid(struct amdgpu_dm_connector * aconnector)2816 void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector)
2817 {
2818 	struct cec_notifier *n = aconnector->notifier;
2819 
2820 	if (!n)
2821 		return;
2822 
2823 	cec_notifier_phys_addr_invalidate(n);
2824 }
2825 
hdmi_cec_set_edid(struct amdgpu_dm_connector * aconnector)2826 void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector)
2827 {
2828 	struct drm_connector *connector = &aconnector->base;
2829 	struct cec_notifier *n = aconnector->notifier;
2830 
2831 	if (!n)
2832 		return;
2833 
2834 	cec_notifier_set_phys_addr(n,
2835 				   connector->display_info.source_physical_address);
2836 }
2837 
s3_handle_hdmi_cec(struct drm_device * ddev,bool suspend)2838 static void s3_handle_hdmi_cec(struct drm_device *ddev, bool suspend)
2839 {
2840 	struct amdgpu_dm_connector *aconnector;
2841 	struct drm_connector *connector;
2842 	struct drm_connector_list_iter conn_iter;
2843 
2844 	drm_connector_list_iter_begin(ddev, &conn_iter);
2845 	drm_for_each_connector_iter(connector, &conn_iter) {
2846 		if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2847 			continue;
2848 
2849 		aconnector = to_amdgpu_dm_connector(connector);
2850 		if (suspend)
2851 			hdmi_cec_unset_edid(aconnector);
2852 		else
2853 			hdmi_cec_set_edid(aconnector);
2854 	}
2855 	drm_connector_list_iter_end(&conn_iter);
2856 }
2857 
s3_handle_mst(struct drm_device * dev,bool suspend)2858 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2859 {
2860 	struct amdgpu_dm_connector *aconnector;
2861 	struct drm_connector *connector;
2862 	struct drm_connector_list_iter iter;
2863 	struct drm_dp_mst_topology_mgr *mgr;
2864 
2865 	drm_connector_list_iter_begin(dev, &iter);
2866 	drm_for_each_connector_iter(connector, &iter) {
2867 
2868 		if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2869 			continue;
2870 
2871 		aconnector = to_amdgpu_dm_connector(connector);
2872 		if (aconnector->dc_link->type != dc_connection_mst_branch ||
2873 		    aconnector->mst_root)
2874 			continue;
2875 
2876 		mgr = &aconnector->mst_mgr;
2877 
2878 		if (suspend) {
2879 			drm_dp_mst_topology_mgr_suspend(mgr);
2880 		} else {
2881 			/* if extended timeout is supported in hardware,
2882 			 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2883 			 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2884 			 */
2885 			try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2886 			if (!dp_is_lttpr_present(aconnector->dc_link))
2887 				try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2888 
2889 			/* TODO: move resume_mst_branch_status() into drm mst resume again
2890 			 * once topology probing work is pulled out from mst resume into mst
2891 			 * resume 2nd step. mst resume 2nd step should be called after old
2892 			 * state getting restored (i.e. drm_atomic_helper_resume()).
2893 			 */
2894 			resume_mst_branch_status(mgr);
2895 		}
2896 	}
2897 	drm_connector_list_iter_end(&iter);
2898 }
2899 
amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device * adev)2900 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2901 {
2902 	int ret = 0;
2903 
2904 	/* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2905 	 * on window driver dc implementation.
2906 	 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2907 	 * should be passed to smu during boot up and resume from s3.
2908 	 * boot up: dc calculate dcn watermark clock settings within dc_create,
2909 	 * dcn20_resource_construct
2910 	 * then call pplib functions below to pass the settings to smu:
2911 	 * smu_set_watermarks_for_clock_ranges
2912 	 * smu_set_watermarks_table
2913 	 * navi10_set_watermarks_table
2914 	 * smu_write_watermarks_table
2915 	 *
2916 	 * For Renoir, clock settings of dcn watermark are also fixed values.
2917 	 * dc has implemented different flow for window driver:
2918 	 * dc_hardware_init / dc_set_power_state
2919 	 * dcn10_init_hw
2920 	 * notify_wm_ranges
2921 	 * set_wm_ranges
2922 	 * -- Linux
2923 	 * smu_set_watermarks_for_clock_ranges
2924 	 * renoir_set_watermarks_table
2925 	 * smu_write_watermarks_table
2926 	 *
2927 	 * For Linux,
2928 	 * dc_hardware_init -> amdgpu_dm_init
2929 	 * dc_set_power_state --> dm_resume
2930 	 *
2931 	 * therefore, this function apply to navi10/12/14 but not Renoir
2932 	 * *
2933 	 */
2934 	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2935 	case IP_VERSION(2, 0, 2):
2936 	case IP_VERSION(2, 0, 0):
2937 		break;
2938 	default:
2939 		return 0;
2940 	}
2941 
2942 	ret = amdgpu_dpm_write_watermarks_table(adev);
2943 	if (ret) {
2944 		DRM_ERROR("Failed to update WMTABLE!\n");
2945 		return ret;
2946 	}
2947 
2948 	return 0;
2949 }
2950 
2951 /**
2952  * dm_hw_init() - Initialize DC device
2953  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
2954  *
2955  * Initialize the &struct amdgpu_display_manager device. This involves calling
2956  * the initializers of each DM component, then populating the struct with them.
2957  *
2958  * Although the function implies hardware initialization, both hardware and
2959  * software are initialized here. Splitting them out to their relevant init
2960  * hooks is a future TODO item.
2961  *
2962  * Some notable things that are initialized here:
2963  *
2964  * - Display Core, both software and hardware
2965  * - DC modules that we need (freesync and color management)
2966  * - DRM software states
2967  * - Interrupt sources and handlers
2968  * - Vblank support
2969  * - Debug FS entries, if enabled
2970  */
dm_hw_init(struct amdgpu_ip_block * ip_block)2971 static int dm_hw_init(struct amdgpu_ip_block *ip_block)
2972 {
2973 	struct amdgpu_device *adev = ip_block->adev;
2974 	int r;
2975 
2976 	/* Create DAL display manager */
2977 	r = amdgpu_dm_init(adev);
2978 	if (r)
2979 		return r;
2980 	amdgpu_dm_hpd_init(adev);
2981 
2982 	return 0;
2983 }
2984 
2985 /**
2986  * dm_hw_fini() - Teardown DC device
2987  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
2988  *
2989  * Teardown components within &struct amdgpu_display_manager that require
2990  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2991  * were loaded. Also flush IRQ workqueues and disable them.
2992  */
dm_hw_fini(struct amdgpu_ip_block * ip_block)2993 static int dm_hw_fini(struct amdgpu_ip_block *ip_block)
2994 {
2995 	struct amdgpu_device *adev = ip_block->adev;
2996 
2997 	amdgpu_dm_hpd_fini(adev);
2998 
2999 	amdgpu_dm_irq_fini(adev);
3000 	amdgpu_dm_fini(adev);
3001 	return 0;
3002 }
3003 
3004 
dm_gpureset_toggle_interrupts(struct amdgpu_device * adev,struct dc_state * state,bool enable)3005 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
3006 				 struct dc_state *state, bool enable)
3007 {
3008 	enum dc_irq_source irq_source;
3009 	struct amdgpu_crtc *acrtc;
3010 	int rc = -EBUSY;
3011 	int i = 0;
3012 
3013 	for (i = 0; i < state->stream_count; i++) {
3014 		acrtc = get_crtc_by_otg_inst(
3015 				adev, state->stream_status[i].primary_otg_inst);
3016 
3017 		if (acrtc && state->stream_status[i].plane_count != 0) {
3018 			irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
3019 			rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3020 			if (rc)
3021 				DRM_WARN("Failed to %s pflip interrupts\n",
3022 					 enable ? "enable" : "disable");
3023 
3024 			if (enable) {
3025 				if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
3026 					rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
3027 			} else
3028 				rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
3029 
3030 			if (rc)
3031 				DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
3032 
3033 			irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
3034 			/* During gpu-reset we disable and then enable vblank irq, so
3035 			 * don't use amdgpu_irq_get/put() to avoid refcount change.
3036 			 */
3037 			if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
3038 				DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
3039 		}
3040 	}
3041 
3042 }
3043 
amdgpu_dm_commit_zero_streams(struct dc * dc)3044 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
3045 {
3046 	struct dc_state *context = NULL;
3047 	enum dc_status res = DC_ERROR_UNEXPECTED;
3048 	int i;
3049 	struct dc_stream_state *del_streams[MAX_PIPES];
3050 	int del_streams_count = 0;
3051 	struct dc_commit_streams_params params = {};
3052 
3053 	memset(del_streams, 0, sizeof(del_streams));
3054 
3055 	context = dc_state_create_current_copy(dc);
3056 	if (context == NULL)
3057 		goto context_alloc_fail;
3058 
3059 	/* First remove from context all streams */
3060 	for (i = 0; i < context->stream_count; i++) {
3061 		struct dc_stream_state *stream = context->streams[i];
3062 
3063 		del_streams[del_streams_count++] = stream;
3064 	}
3065 
3066 	/* Remove all planes for removed streams and then remove the streams */
3067 	for (i = 0; i < del_streams_count; i++) {
3068 		if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) {
3069 			res = DC_FAIL_DETACH_SURFACES;
3070 			goto fail;
3071 		}
3072 
3073 		res = dc_state_remove_stream(dc, context, del_streams[i]);
3074 		if (res != DC_OK)
3075 			goto fail;
3076 	}
3077 
3078 	params.streams = context->streams;
3079 	params.stream_count = context->stream_count;
3080 	res = dc_commit_streams(dc, &params);
3081 
3082 fail:
3083 	dc_state_release(context);
3084 
3085 context_alloc_fail:
3086 	return res;
3087 }
3088 
hpd_rx_irq_work_suspend(struct amdgpu_display_manager * dm)3089 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
3090 {
3091 	int i;
3092 
3093 	if (dm->hpd_rx_offload_wq) {
3094 		for (i = 0; i < dm->dc->caps.max_links; i++)
3095 			flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
3096 	}
3097 }
3098 
dm_suspend(struct amdgpu_ip_block * ip_block)3099 static int dm_suspend(struct amdgpu_ip_block *ip_block)
3100 {
3101 	struct amdgpu_device *adev = ip_block->adev;
3102 	struct amdgpu_display_manager *dm = &adev->dm;
3103 	int ret = 0;
3104 
3105 	if (amdgpu_in_reset(adev)) {
3106 		mutex_lock(&dm->dc_lock);
3107 
3108 		dc_allow_idle_optimizations(adev->dm.dc, false);
3109 
3110 		dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state);
3111 
3112 		if (dm->cached_dc_state)
3113 			dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
3114 
3115 		amdgpu_dm_commit_zero_streams(dm->dc);
3116 
3117 		amdgpu_dm_irq_suspend(adev);
3118 
3119 		hpd_rx_irq_work_suspend(dm);
3120 
3121 		return ret;
3122 	}
3123 
3124 	WARN_ON(adev->dm.cached_state);
3125 	adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
3126 	if (IS_ERR(adev->dm.cached_state))
3127 		return PTR_ERR(adev->dm.cached_state);
3128 
3129 	s3_handle_hdmi_cec(adev_to_drm(adev), true);
3130 
3131 	s3_handle_mst(adev_to_drm(adev), true);
3132 
3133 	amdgpu_dm_irq_suspend(adev);
3134 
3135 	hpd_rx_irq_work_suspend(dm);
3136 
3137 	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
3138 
3139 	if (dm->dc->caps.ips_support && adev->in_s0ix)
3140 		dc_allow_idle_optimizations(dm->dc, true);
3141 
3142 	dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);
3143 
3144 	return 0;
3145 }
3146 
3147 struct drm_connector *
amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state * state,struct drm_crtc * crtc)3148 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
3149 					     struct drm_crtc *crtc)
3150 {
3151 	u32 i;
3152 	struct drm_connector_state *new_con_state;
3153 	struct drm_connector *connector;
3154 	struct drm_crtc *crtc_from_state;
3155 
3156 	for_each_new_connector_in_state(state, connector, new_con_state, i) {
3157 		crtc_from_state = new_con_state->crtc;
3158 
3159 		if (crtc_from_state == crtc)
3160 			return connector;
3161 	}
3162 
3163 	return NULL;
3164 }
3165 
emulated_link_detect(struct dc_link * link)3166 static void emulated_link_detect(struct dc_link *link)
3167 {
3168 	struct dc_sink_init_data sink_init_data = { 0 };
3169 	struct display_sink_capability sink_caps = { 0 };
3170 	enum dc_edid_status edid_status;
3171 	struct dc_context *dc_ctx = link->ctx;
3172 	struct drm_device *dev = adev_to_drm(dc_ctx->driver_context);
3173 	struct dc_sink *sink = NULL;
3174 	struct dc_sink *prev_sink = NULL;
3175 
3176 	link->type = dc_connection_none;
3177 	prev_sink = link->local_sink;
3178 
3179 	if (prev_sink)
3180 		dc_sink_release(prev_sink);
3181 
3182 	switch (link->connector_signal) {
3183 	case SIGNAL_TYPE_HDMI_TYPE_A: {
3184 		sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
3185 		sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
3186 		break;
3187 	}
3188 
3189 	case SIGNAL_TYPE_DVI_SINGLE_LINK: {
3190 		sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
3191 		sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
3192 		break;
3193 	}
3194 
3195 	case SIGNAL_TYPE_DVI_DUAL_LINK: {
3196 		sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
3197 		sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
3198 		break;
3199 	}
3200 
3201 	case SIGNAL_TYPE_LVDS: {
3202 		sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
3203 		sink_caps.signal = SIGNAL_TYPE_LVDS;
3204 		break;
3205 	}
3206 
3207 	case SIGNAL_TYPE_EDP: {
3208 		sink_caps.transaction_type =
3209 			DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
3210 		sink_caps.signal = SIGNAL_TYPE_EDP;
3211 		break;
3212 	}
3213 
3214 	case SIGNAL_TYPE_DISPLAY_PORT: {
3215 		sink_caps.transaction_type =
3216 			DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
3217 		sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
3218 		break;
3219 	}
3220 
3221 	default:
3222 		drm_err(dev, "Invalid connector type! signal:%d\n",
3223 			link->connector_signal);
3224 		return;
3225 	}
3226 
3227 	sink_init_data.link = link;
3228 	sink_init_data.sink_signal = sink_caps.signal;
3229 
3230 	sink = dc_sink_create(&sink_init_data);
3231 	if (!sink) {
3232 		drm_err(dev, "Failed to create sink!\n");
3233 		return;
3234 	}
3235 
3236 	/* dc_sink_create returns a new reference */
3237 	link->local_sink = sink;
3238 
3239 	edid_status = dm_helpers_read_local_edid(
3240 			link->ctx,
3241 			link,
3242 			sink);
3243 
3244 	if (edid_status != EDID_OK)
3245 		drm_err(dev, "Failed to read EDID\n");
3246 
3247 }
3248 
dm_gpureset_commit_state(struct dc_state * dc_state,struct amdgpu_display_manager * dm)3249 static void dm_gpureset_commit_state(struct dc_state *dc_state,
3250 				     struct amdgpu_display_manager *dm)
3251 {
3252 	struct {
3253 		struct dc_surface_update surface_updates[MAX_SURFACES];
3254 		struct dc_plane_info plane_infos[MAX_SURFACES];
3255 		struct dc_scaling_info scaling_infos[MAX_SURFACES];
3256 		struct dc_flip_addrs flip_addrs[MAX_SURFACES];
3257 		struct dc_stream_update stream_update;
3258 	} *bundle;
3259 	int k, m;
3260 
3261 	bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
3262 
3263 	if (!bundle) {
3264 		drm_err(dm->ddev, "Failed to allocate update bundle\n");
3265 		goto cleanup;
3266 	}
3267 
3268 	for (k = 0; k < dc_state->stream_count; k++) {
3269 		bundle->stream_update.stream = dc_state->streams[k];
3270 
3271 		for (m = 0; m < dc_state->stream_status->plane_count; m++) {
3272 			bundle->surface_updates[m].surface =
3273 				dc_state->stream_status->plane_states[m];
3274 			bundle->surface_updates[m].surface->force_full_update =
3275 				true;
3276 		}
3277 
3278 		update_planes_and_stream_adapter(dm->dc,
3279 					 UPDATE_TYPE_FULL,
3280 					 dc_state->stream_status->plane_count,
3281 					 dc_state->streams[k],
3282 					 &bundle->stream_update,
3283 					 bundle->surface_updates);
3284 	}
3285 
3286 cleanup:
3287 	kfree(bundle);
3288 }
3289 
dm_resume(struct amdgpu_ip_block * ip_block)3290 static int dm_resume(struct amdgpu_ip_block *ip_block)
3291 {
3292 	struct amdgpu_device *adev = ip_block->adev;
3293 	struct drm_device *ddev = adev_to_drm(adev);
3294 	struct amdgpu_display_manager *dm = &adev->dm;
3295 	struct amdgpu_dm_connector *aconnector;
3296 	struct drm_connector *connector;
3297 	struct drm_connector_list_iter iter;
3298 	struct drm_crtc *crtc;
3299 	struct drm_crtc_state *new_crtc_state;
3300 	struct dm_crtc_state *dm_new_crtc_state;
3301 	struct drm_plane *plane;
3302 	struct drm_plane_state *new_plane_state;
3303 	struct dm_plane_state *dm_new_plane_state;
3304 	struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
3305 	enum dc_connection_type new_connection_type = dc_connection_none;
3306 	struct dc_state *dc_state;
3307 	int i, r, j;
3308 	struct dc_commit_streams_params commit_params = {};
3309 
3310 	if (dm->dc->caps.ips_support) {
3311 		dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);
3312 	}
3313 
3314 	if (amdgpu_in_reset(adev)) {
3315 		dc_state = dm->cached_dc_state;
3316 
3317 		/*
3318 		 * The dc->current_state is backed up into dm->cached_dc_state
3319 		 * before we commit 0 streams.
3320 		 *
3321 		 * DC will clear link encoder assignments on the real state
3322 		 * but the changes won't propagate over to the copy we made
3323 		 * before the 0 streams commit.
3324 		 *
3325 		 * DC expects that link encoder assignments are *not* valid
3326 		 * when committing a state, so as a workaround we can copy
3327 		 * off of the current state.
3328 		 *
3329 		 * We lose the previous assignments, but we had already
3330 		 * commit 0 streams anyway.
3331 		 */
3332 		link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
3333 
3334 		r = dm_dmub_hw_init(adev);
3335 		if (r)
3336 			DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
3337 
3338 		dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
3339 		dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
3340 
3341 		dc_resume(dm->dc);
3342 
3343 		amdgpu_dm_irq_resume_early(adev);
3344 
3345 		for (i = 0; i < dc_state->stream_count; i++) {
3346 			dc_state->streams[i]->mode_changed = true;
3347 			for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
3348 				dc_state->stream_status[i].plane_states[j]->update_flags.raw
3349 					= 0xffffffff;
3350 			}
3351 		}
3352 
3353 		if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
3354 			amdgpu_dm_outbox_init(adev);
3355 			dc_enable_dmub_outbox(adev->dm.dc);
3356 		}
3357 
3358 		commit_params.streams = dc_state->streams;
3359 		commit_params.stream_count = dc_state->stream_count;
3360 		dc_exit_ips_for_hw_access(dm->dc);
3361 		WARN_ON(!dc_commit_streams(dm->dc, &commit_params));
3362 
3363 		dm_gpureset_commit_state(dm->cached_dc_state, dm);
3364 
3365 		dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
3366 
3367 		dc_state_release(dm->cached_dc_state);
3368 		dm->cached_dc_state = NULL;
3369 
3370 		amdgpu_dm_irq_resume_late(adev);
3371 
3372 		mutex_unlock(&dm->dc_lock);
3373 
3374 		return 0;
3375 	}
3376 	/* Recreate dc_state - DC invalidates it when setting power state to S3. */
3377 	dc_state_release(dm_state->context);
3378 	dm_state->context = dc_state_create(dm->dc, NULL);
3379 	/* TODO: Remove dc_state->dccg, use dc->dccg directly. */
3380 
3381 	/* Before powering on DC we need to re-initialize DMUB. */
3382 	dm_dmub_hw_resume(adev);
3383 
3384 	/* Re-enable outbox interrupts for DPIA. */
3385 	if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
3386 		amdgpu_dm_outbox_init(adev);
3387 		dc_enable_dmub_outbox(adev->dm.dc);
3388 	}
3389 
3390 	/* power on hardware */
3391 	dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
3392 	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
3393 
3394 	/* program HPD filter */
3395 	dc_resume(dm->dc);
3396 
3397 	/*
3398 	 * early enable HPD Rx IRQ, should be done before set mode as short
3399 	 * pulse interrupts are used for MST
3400 	 */
3401 	amdgpu_dm_irq_resume_early(adev);
3402 
3403 	s3_handle_hdmi_cec(ddev, false);
3404 
3405 	/* On resume we need to rewrite the MSTM control bits to enable MST*/
3406 	s3_handle_mst(ddev, false);
3407 
3408 	/* Do detection*/
3409 	drm_connector_list_iter_begin(ddev, &iter);
3410 	drm_for_each_connector_iter(connector, &iter) {
3411 
3412 		if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
3413 			continue;
3414 
3415 		aconnector = to_amdgpu_dm_connector(connector);
3416 
3417 		if (!aconnector->dc_link)
3418 			continue;
3419 
3420 		/*
3421 		 * this is the case when traversing through already created end sink
3422 		 * MST connectors, should be skipped
3423 		 */
3424 		if (aconnector->mst_root)
3425 			continue;
3426 
3427 		mutex_lock(&aconnector->hpd_lock);
3428 		if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3429 			DRM_ERROR("KMS: Failed to detect connector\n");
3430 
3431 		if (aconnector->base.force && new_connection_type == dc_connection_none) {
3432 			emulated_link_detect(aconnector->dc_link);
3433 		} else {
3434 			mutex_lock(&dm->dc_lock);
3435 			dc_exit_ips_for_hw_access(dm->dc);
3436 			dc_link_detect(aconnector->dc_link, DETECT_REASON_RESUMEFROMS3S4);
3437 			mutex_unlock(&dm->dc_lock);
3438 		}
3439 
3440 		if (aconnector->fake_enable && aconnector->dc_link->local_sink)
3441 			aconnector->fake_enable = false;
3442 
3443 		if (aconnector->dc_sink)
3444 			dc_sink_release(aconnector->dc_sink);
3445 		aconnector->dc_sink = NULL;
3446 		amdgpu_dm_update_connector_after_detect(aconnector);
3447 		mutex_unlock(&aconnector->hpd_lock);
3448 	}
3449 	drm_connector_list_iter_end(&iter);
3450 
3451 	/* Force mode set in atomic commit */
3452 	for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
3453 		new_crtc_state->active_changed = true;
3454 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
3455 		reset_freesync_config_for_crtc(dm_new_crtc_state);
3456 	}
3457 
3458 	/*
3459 	 * atomic_check is expected to create the dc states. We need to release
3460 	 * them here, since they were duplicated as part of the suspend
3461 	 * procedure.
3462 	 */
3463 	for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
3464 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
3465 		if (dm_new_crtc_state->stream) {
3466 			WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
3467 			dc_stream_release(dm_new_crtc_state->stream);
3468 			dm_new_crtc_state->stream = NULL;
3469 		}
3470 		dm_new_crtc_state->base.color_mgmt_changed = true;
3471 	}
3472 
3473 	for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
3474 		dm_new_plane_state = to_dm_plane_state(new_plane_state);
3475 		if (dm_new_plane_state->dc_state) {
3476 			WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
3477 			dc_plane_state_release(dm_new_plane_state->dc_state);
3478 			dm_new_plane_state->dc_state = NULL;
3479 		}
3480 	}
3481 
3482 	drm_atomic_helper_resume(ddev, dm->cached_state);
3483 
3484 	dm->cached_state = NULL;
3485 
3486 	/* Do mst topology probing after resuming cached state*/
3487 	drm_connector_list_iter_begin(ddev, &iter);
3488 	drm_for_each_connector_iter(connector, &iter) {
3489 
3490 		if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
3491 			continue;
3492 
3493 		aconnector = to_amdgpu_dm_connector(connector);
3494 		if (aconnector->dc_link->type != dc_connection_mst_branch ||
3495 		    aconnector->mst_root)
3496 			continue;
3497 
3498 		drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr);
3499 	}
3500 	drm_connector_list_iter_end(&iter);
3501 
3502 	amdgpu_dm_irq_resume_late(adev);
3503 
3504 	amdgpu_dm_smu_write_watermarks_table(adev);
3505 
3506 	drm_kms_helper_hotplug_event(ddev);
3507 
3508 	return 0;
3509 }
3510 
3511 /**
3512  * DOC: DM Lifecycle
3513  *
3514  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
3515  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
3516  * the base driver's device list to be initialized and torn down accordingly.
3517  *
3518  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
3519  */
3520 
3521 static const struct amd_ip_funcs amdgpu_dm_funcs = {
3522 	.name = "dm",
3523 	.early_init = dm_early_init,
3524 	.late_init = dm_late_init,
3525 	.sw_init = dm_sw_init,
3526 	.sw_fini = dm_sw_fini,
3527 	.early_fini = amdgpu_dm_early_fini,
3528 	.hw_init = dm_hw_init,
3529 	.hw_fini = dm_hw_fini,
3530 	.suspend = dm_suspend,
3531 	.resume = dm_resume,
3532 	.is_idle = dm_is_idle,
3533 	.wait_for_idle = dm_wait_for_idle,
3534 	.check_soft_reset = dm_check_soft_reset,
3535 	.soft_reset = dm_soft_reset,
3536 	.set_clockgating_state = dm_set_clockgating_state,
3537 	.set_powergating_state = dm_set_powergating_state,
3538 };
3539 
3540 const struct amdgpu_ip_block_version dm_ip_block = {
3541 	.type = AMD_IP_BLOCK_TYPE_DCE,
3542 	.major = 1,
3543 	.minor = 0,
3544 	.rev = 0,
3545 	.funcs = &amdgpu_dm_funcs,
3546 };
3547 
3548 
3549 /**
3550  * DOC: atomic
3551  *
3552  * *WIP*
3553  */
3554 
3555 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
3556 	.fb_create = amdgpu_display_user_framebuffer_create,
3557 	.get_format_info = amdgpu_dm_plane_get_format_info,
3558 	.atomic_check = amdgpu_dm_atomic_check,
3559 	.atomic_commit = drm_atomic_helper_commit,
3560 };
3561 
3562 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
3563 	.atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
3564 	.atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
3565 };
3566 
update_connector_ext_caps(struct amdgpu_dm_connector * aconnector)3567 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
3568 {
3569 	struct amdgpu_dm_backlight_caps *caps;
3570 	struct drm_connector *conn_base;
3571 	struct amdgpu_device *adev;
3572 	struct drm_luminance_range_info *luminance_range;
3573 	int min_input_signal_override;
3574 
3575 	if (aconnector->bl_idx == -1 ||
3576 	    aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
3577 		return;
3578 
3579 	conn_base = &aconnector->base;
3580 	adev = drm_to_adev(conn_base->dev);
3581 
3582 	caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3583 	caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3584 	caps->aux_support = false;
3585 
3586 	if (caps->ext_caps->bits.oled == 1
3587 	    /*
3588 	     * ||
3589 	     * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3590 	     * caps->ext_caps->bits.hdr_aux_backlight_control == 1
3591 	     */)
3592 		caps->aux_support = true;
3593 
3594 	if (amdgpu_backlight == 0)
3595 		caps->aux_support = false;
3596 	else if (amdgpu_backlight == 1)
3597 		caps->aux_support = true;
3598 	if (caps->aux_support)
3599 		aconnector->dc_link->backlight_control_type = BACKLIGHT_CONTROL_AMD_AUX;
3600 
3601 	luminance_range = &conn_base->display_info.luminance_range;
3602 
3603 	if (luminance_range->max_luminance) {
3604 		caps->aux_min_input_signal = luminance_range->min_luminance;
3605 		caps->aux_max_input_signal = luminance_range->max_luminance;
3606 	} else {
3607 		caps->aux_min_input_signal = 0;
3608 		caps->aux_max_input_signal = 512;
3609 	}
3610 
3611 	min_input_signal_override = drm_get_panel_min_brightness_quirk(aconnector->drm_edid);
3612 	if (min_input_signal_override >= 0)
3613 		caps->min_input_signal = min_input_signal_override;
3614 }
3615 
amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector * aconnector)3616 void amdgpu_dm_update_connector_after_detect(
3617 		struct amdgpu_dm_connector *aconnector)
3618 {
3619 	struct drm_connector *connector = &aconnector->base;
3620 	struct drm_device *dev = connector->dev;
3621 	struct dc_sink *sink;
3622 
3623 	/* MST handled by drm_mst framework */
3624 	if (aconnector->mst_mgr.mst_state == true)
3625 		return;
3626 
3627 	sink = aconnector->dc_link->local_sink;
3628 	if (sink)
3629 		dc_sink_retain(sink);
3630 
3631 	/*
3632 	 * Edid mgmt connector gets first update only in mode_valid hook and then
3633 	 * the connector sink is set to either fake or physical sink depends on link status.
3634 	 * Skip if already done during boot.
3635 	 */
3636 	if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3637 			&& aconnector->dc_em_sink) {
3638 
3639 		/*
3640 		 * For S3 resume with headless use eml_sink to fake stream
3641 		 * because on resume connector->sink is set to NULL
3642 		 */
3643 		mutex_lock(&dev->mode_config.mutex);
3644 
3645 		if (sink) {
3646 			if (aconnector->dc_sink) {
3647 				amdgpu_dm_update_freesync_caps(connector, NULL);
3648 				/*
3649 				 * retain and release below are used to
3650 				 * bump up refcount for sink because the link doesn't point
3651 				 * to it anymore after disconnect, so on next crtc to connector
3652 				 * reshuffle by UMD we will get into unwanted dc_sink release
3653 				 */
3654 				dc_sink_release(aconnector->dc_sink);
3655 			}
3656 			aconnector->dc_sink = sink;
3657 			dc_sink_retain(aconnector->dc_sink);
3658 			amdgpu_dm_update_freesync_caps(connector,
3659 					aconnector->drm_edid);
3660 		} else {
3661 			amdgpu_dm_update_freesync_caps(connector, NULL);
3662 			if (!aconnector->dc_sink) {
3663 				aconnector->dc_sink = aconnector->dc_em_sink;
3664 				dc_sink_retain(aconnector->dc_sink);
3665 			}
3666 		}
3667 
3668 		mutex_unlock(&dev->mode_config.mutex);
3669 
3670 		if (sink)
3671 			dc_sink_release(sink);
3672 		return;
3673 	}
3674 
3675 	/*
3676 	 * TODO: temporary guard to look for proper fix
3677 	 * if this sink is MST sink, we should not do anything
3678 	 */
3679 	if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3680 		dc_sink_release(sink);
3681 		return;
3682 	}
3683 
3684 	if (aconnector->dc_sink == sink) {
3685 		/*
3686 		 * We got a DP short pulse (Link Loss, DP CTS, etc...).
3687 		 * Do nothing!!
3688 		 */
3689 		drm_dbg_kms(dev, "DCHPD: connector_id=%d: dc_sink didn't change.\n",
3690 				 aconnector->connector_id);
3691 		if (sink)
3692 			dc_sink_release(sink);
3693 		return;
3694 	}
3695 
3696 	drm_dbg_kms(dev, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3697 		    aconnector->connector_id, aconnector->dc_sink, sink);
3698 
3699 	mutex_lock(&dev->mode_config.mutex);
3700 
3701 	/*
3702 	 * 1. Update status of the drm connector
3703 	 * 2. Send an event and let userspace tell us what to do
3704 	 */
3705 	if (sink) {
3706 		/*
3707 		 * TODO: check if we still need the S3 mode update workaround.
3708 		 * If yes, put it here.
3709 		 */
3710 		if (aconnector->dc_sink) {
3711 			amdgpu_dm_update_freesync_caps(connector, NULL);
3712 			dc_sink_release(aconnector->dc_sink);
3713 		}
3714 
3715 		aconnector->dc_sink = sink;
3716 		dc_sink_retain(aconnector->dc_sink);
3717 		if (sink->dc_edid.length == 0) {
3718 			aconnector->drm_edid = NULL;
3719 			hdmi_cec_unset_edid(aconnector);
3720 			if (aconnector->dc_link->aux_mode) {
3721 				drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3722 			}
3723 		} else {
3724 			const struct edid *edid = (const struct edid *)sink->dc_edid.raw_edid;
3725 
3726 			aconnector->drm_edid = drm_edid_alloc(edid, sink->dc_edid.length);
3727 			drm_edid_connector_update(connector, aconnector->drm_edid);
3728 
3729 			hdmi_cec_set_edid(aconnector);
3730 			if (aconnector->dc_link->aux_mode)
3731 				drm_dp_cec_attach(&aconnector->dm_dp_aux.aux,
3732 						  connector->display_info.source_physical_address);
3733 		}
3734 
3735 		if (!aconnector->timing_requested) {
3736 			aconnector->timing_requested =
3737 				kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3738 			if (!aconnector->timing_requested)
3739 				drm_err(dev,
3740 					"failed to create aconnector->requested_timing\n");
3741 		}
3742 
3743 		amdgpu_dm_update_freesync_caps(connector, aconnector->drm_edid);
3744 		update_connector_ext_caps(aconnector);
3745 	} else {
3746 		hdmi_cec_unset_edid(aconnector);
3747 		drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3748 		amdgpu_dm_update_freesync_caps(connector, NULL);
3749 		aconnector->num_modes = 0;
3750 		dc_sink_release(aconnector->dc_sink);
3751 		aconnector->dc_sink = NULL;
3752 		drm_edid_free(aconnector->drm_edid);
3753 		aconnector->drm_edid = NULL;
3754 		kfree(aconnector->timing_requested);
3755 		aconnector->timing_requested = NULL;
3756 		/* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3757 		if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3758 			connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3759 	}
3760 
3761 	mutex_unlock(&dev->mode_config.mutex);
3762 
3763 	update_subconnector_property(aconnector);
3764 
3765 	if (sink)
3766 		dc_sink_release(sink);
3767 }
3768 
handle_hpd_irq_helper(struct amdgpu_dm_connector * aconnector)3769 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3770 {
3771 	struct drm_connector *connector = &aconnector->base;
3772 	struct drm_device *dev = connector->dev;
3773 	enum dc_connection_type new_connection_type = dc_connection_none;
3774 	struct amdgpu_device *adev = drm_to_adev(dev);
3775 	struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3776 	struct dc *dc = aconnector->dc_link->ctx->dc;
3777 	bool ret = false;
3778 
3779 	if (adev->dm.disable_hpd_irq)
3780 		return;
3781 
3782 	/*
3783 	 * In case of failure or MST no need to update connector status or notify the OS
3784 	 * since (for MST case) MST does this in its own context.
3785 	 */
3786 	mutex_lock(&aconnector->hpd_lock);
3787 
3788 	if (adev->dm.hdcp_workqueue) {
3789 		hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3790 		dm_con_state->update_hdcp = true;
3791 	}
3792 	if (aconnector->fake_enable)
3793 		aconnector->fake_enable = false;
3794 
3795 	aconnector->timing_changed = false;
3796 
3797 	if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3798 		DRM_ERROR("KMS: Failed to detect connector\n");
3799 
3800 	if (aconnector->base.force && new_connection_type == dc_connection_none) {
3801 		emulated_link_detect(aconnector->dc_link);
3802 
3803 		drm_modeset_lock_all(dev);
3804 		dm_restore_drm_connector_state(dev, connector);
3805 		drm_modeset_unlock_all(dev);
3806 
3807 		if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3808 			drm_kms_helper_connector_hotplug_event(connector);
3809 	} else {
3810 		mutex_lock(&adev->dm.dc_lock);
3811 		dc_exit_ips_for_hw_access(dc);
3812 		ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3813 		mutex_unlock(&adev->dm.dc_lock);
3814 		if (ret) {
3815 			amdgpu_dm_update_connector_after_detect(aconnector);
3816 
3817 			drm_modeset_lock_all(dev);
3818 			dm_restore_drm_connector_state(dev, connector);
3819 			drm_modeset_unlock_all(dev);
3820 
3821 			if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3822 				drm_kms_helper_connector_hotplug_event(connector);
3823 		}
3824 	}
3825 	mutex_unlock(&aconnector->hpd_lock);
3826 
3827 }
3828 
handle_hpd_irq(void * param)3829 static void handle_hpd_irq(void *param)
3830 {
3831 	struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3832 
3833 	handle_hpd_irq_helper(aconnector);
3834 
3835 }
3836 
schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue * offload_wq,union hpd_irq_data hpd_irq_data)3837 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3838 							union hpd_irq_data hpd_irq_data)
3839 {
3840 	struct hpd_rx_irq_offload_work *offload_work =
3841 				kzalloc(sizeof(*offload_work), GFP_KERNEL);
3842 
3843 	if (!offload_work) {
3844 		DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3845 		return;
3846 	}
3847 
3848 	INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3849 	offload_work->data = hpd_irq_data;
3850 	offload_work->offload_wq = offload_wq;
3851 
3852 	queue_work(offload_wq->wq, &offload_work->work);
3853 	DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3854 }
3855 
handle_hpd_rx_irq(void * param)3856 static void handle_hpd_rx_irq(void *param)
3857 {
3858 	struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3859 	struct drm_connector *connector = &aconnector->base;
3860 	struct drm_device *dev = connector->dev;
3861 	struct dc_link *dc_link = aconnector->dc_link;
3862 	bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3863 	bool result = false;
3864 	enum dc_connection_type new_connection_type = dc_connection_none;
3865 	struct amdgpu_device *adev = drm_to_adev(dev);
3866 	union hpd_irq_data hpd_irq_data;
3867 	bool link_loss = false;
3868 	bool has_left_work = false;
3869 	int idx = dc_link->link_index;
3870 	struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3871 	struct dc *dc = aconnector->dc_link->ctx->dc;
3872 
3873 	memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3874 
3875 	if (adev->dm.disable_hpd_irq)
3876 		return;
3877 
3878 	/*
3879 	 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3880 	 * conflict, after implement i2c helper, this mutex should be
3881 	 * retired.
3882 	 */
3883 	mutex_lock(&aconnector->hpd_lock);
3884 
3885 	result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3886 						&link_loss, true, &has_left_work);
3887 
3888 	if (!has_left_work)
3889 		goto out;
3890 
3891 	if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3892 		schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3893 		goto out;
3894 	}
3895 
3896 	if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3897 		if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3898 			hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3899 			bool skip = false;
3900 
3901 			/*
3902 			 * DOWN_REP_MSG_RDY is also handled by polling method
3903 			 * mgr->cbs->poll_hpd_irq()
3904 			 */
3905 			spin_lock(&offload_wq->offload_lock);
3906 			skip = offload_wq->is_handling_mst_msg_rdy_event;
3907 
3908 			if (!skip)
3909 				offload_wq->is_handling_mst_msg_rdy_event = true;
3910 
3911 			spin_unlock(&offload_wq->offload_lock);
3912 
3913 			if (!skip)
3914 				schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3915 
3916 			goto out;
3917 		}
3918 
3919 		if (link_loss) {
3920 			bool skip = false;
3921 
3922 			spin_lock(&offload_wq->offload_lock);
3923 			skip = offload_wq->is_handling_link_loss;
3924 
3925 			if (!skip)
3926 				offload_wq->is_handling_link_loss = true;
3927 
3928 			spin_unlock(&offload_wq->offload_lock);
3929 
3930 			if (!skip)
3931 				schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3932 
3933 			goto out;
3934 		}
3935 	}
3936 
3937 out:
3938 	if (result && !is_mst_root_connector) {
3939 		/* Downstream Port status changed. */
3940 		if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3941 			DRM_ERROR("KMS: Failed to detect connector\n");
3942 
3943 		if (aconnector->base.force && new_connection_type == dc_connection_none) {
3944 			emulated_link_detect(dc_link);
3945 
3946 			if (aconnector->fake_enable)
3947 				aconnector->fake_enable = false;
3948 
3949 			amdgpu_dm_update_connector_after_detect(aconnector);
3950 
3951 
3952 			drm_modeset_lock_all(dev);
3953 			dm_restore_drm_connector_state(dev, connector);
3954 			drm_modeset_unlock_all(dev);
3955 
3956 			drm_kms_helper_connector_hotplug_event(connector);
3957 		} else {
3958 			bool ret = false;
3959 
3960 			mutex_lock(&adev->dm.dc_lock);
3961 			dc_exit_ips_for_hw_access(dc);
3962 			ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3963 			mutex_unlock(&adev->dm.dc_lock);
3964 
3965 			if (ret) {
3966 				if (aconnector->fake_enable)
3967 					aconnector->fake_enable = false;
3968 
3969 				amdgpu_dm_update_connector_after_detect(aconnector);
3970 
3971 				drm_modeset_lock_all(dev);
3972 				dm_restore_drm_connector_state(dev, connector);
3973 				drm_modeset_unlock_all(dev);
3974 
3975 				drm_kms_helper_connector_hotplug_event(connector);
3976 			}
3977 		}
3978 	}
3979 	if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3980 		if (adev->dm.hdcp_workqueue)
3981 			hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3982 	}
3983 
3984 	if (dc_link->type != dc_connection_mst_branch)
3985 		drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3986 
3987 	mutex_unlock(&aconnector->hpd_lock);
3988 }
3989 
register_hpd_handlers(struct amdgpu_device * adev)3990 static int register_hpd_handlers(struct amdgpu_device *adev)
3991 {
3992 	struct drm_device *dev = adev_to_drm(adev);
3993 	struct drm_connector *connector;
3994 	struct amdgpu_dm_connector *aconnector;
3995 	const struct dc_link *dc_link;
3996 	struct dc_interrupt_params int_params = {0};
3997 
3998 	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3999 	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
4000 
4001 	if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
4002 		if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD,
4003 			dmub_hpd_callback, true)) {
4004 			DRM_ERROR("amdgpu: fail to register dmub hpd callback");
4005 			return -EINVAL;
4006 		}
4007 
4008 		if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ,
4009 			dmub_hpd_callback, true)) {
4010 			DRM_ERROR("amdgpu: fail to register dmub hpd callback");
4011 			return -EINVAL;
4012 		}
4013 
4014 		if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_SENSE_NOTIFY,
4015 			dmub_hpd_sense_callback, true)) {
4016 			DRM_ERROR("amdgpu: fail to register dmub hpd sense callback");
4017 			return -EINVAL;
4018 		}
4019 	}
4020 
4021 	list_for_each_entry(connector,
4022 			&dev->mode_config.connector_list, head)	{
4023 
4024 		if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
4025 			continue;
4026 
4027 		aconnector = to_amdgpu_dm_connector(connector);
4028 		dc_link = aconnector->dc_link;
4029 
4030 		if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
4031 			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
4032 			int_params.irq_source = dc_link->irq_source_hpd;
4033 
4034 			if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4035 				int_params.irq_source  < DC_IRQ_SOURCE_HPD1 ||
4036 				int_params.irq_source  > DC_IRQ_SOURCE_HPD6) {
4037 				DRM_ERROR("Failed to register hpd irq!\n");
4038 				return -EINVAL;
4039 			}
4040 
4041 			if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4042 				handle_hpd_irq, (void *) aconnector))
4043 				return -ENOMEM;
4044 		}
4045 
4046 		if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
4047 
4048 			/* Also register for DP short pulse (hpd_rx). */
4049 			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
4050 			int_params.irq_source =	dc_link->irq_source_hpd_rx;
4051 
4052 			if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4053 				int_params.irq_source  < DC_IRQ_SOURCE_HPD1RX ||
4054 				int_params.irq_source  > DC_IRQ_SOURCE_HPD6RX) {
4055 				DRM_ERROR("Failed to register hpd rx irq!\n");
4056 				return -EINVAL;
4057 			}
4058 
4059 			if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4060 				handle_hpd_rx_irq, (void *) aconnector))
4061 				return -ENOMEM;
4062 		}
4063 	}
4064 	return 0;
4065 }
4066 
4067 #if defined(CONFIG_DRM_AMD_DC_SI)
4068 /* Register IRQ sources and initialize IRQ callbacks */
dce60_register_irq_handlers(struct amdgpu_device * adev)4069 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
4070 {
4071 	struct dc *dc = adev->dm.dc;
4072 	struct common_irq_params *c_irq_params;
4073 	struct dc_interrupt_params int_params = {0};
4074 	int r;
4075 	int i;
4076 	unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
4077 
4078 	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
4079 	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
4080 
4081 	/*
4082 	 * Actions of amdgpu_irq_add_id():
4083 	 * 1. Register a set() function with base driver.
4084 	 *    Base driver will call set() function to enable/disable an
4085 	 *    interrupt in DC hardware.
4086 	 * 2. Register amdgpu_dm_irq_handler().
4087 	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
4088 	 *    coming from DC hardware.
4089 	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
4090 	 *    for acknowledging and handling.
4091 	 */
4092 
4093 	/* Use VBLANK interrupt */
4094 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
4095 		r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
4096 		if (r) {
4097 			DRM_ERROR("Failed to add crtc irq id!\n");
4098 			return r;
4099 		}
4100 
4101 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4102 		int_params.irq_source =
4103 			dc_interrupt_to_irq_source(dc, i + 1, 0);
4104 
4105 		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4106 			int_params.irq_source  < DC_IRQ_SOURCE_VBLANK1 ||
4107 			int_params.irq_source  > DC_IRQ_SOURCE_VBLANK6) {
4108 			DRM_ERROR("Failed to register vblank irq!\n");
4109 			return -EINVAL;
4110 		}
4111 
4112 		c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4113 
4114 		c_irq_params->adev = adev;
4115 		c_irq_params->irq_src = int_params.irq_source;
4116 
4117 		if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4118 			dm_crtc_high_irq, c_irq_params))
4119 			return -ENOMEM;
4120 	}
4121 
4122 	/* Use GRPH_PFLIP interrupt */
4123 	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
4124 			i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
4125 		r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4126 		if (r) {
4127 			DRM_ERROR("Failed to add page flip irq id!\n");
4128 			return r;
4129 		}
4130 
4131 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4132 		int_params.irq_source =
4133 			dc_interrupt_to_irq_source(dc, i, 0);
4134 
4135 		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4136 			int_params.irq_source  < DC_IRQ_SOURCE_PFLIP_FIRST ||
4137 			int_params.irq_source  > DC_IRQ_SOURCE_PFLIP_LAST) {
4138 			DRM_ERROR("Failed to register pflip irq!\n");
4139 			return -EINVAL;
4140 		}
4141 
4142 		c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
4143 
4144 		c_irq_params->adev = adev;
4145 		c_irq_params->irq_src = int_params.irq_source;
4146 
4147 		if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4148 			dm_pflip_high_irq, c_irq_params))
4149 			return -ENOMEM;
4150 	}
4151 
4152 	/* HPD */
4153 	r = amdgpu_irq_add_id(adev, client_id,
4154 			VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4155 	if (r) {
4156 		DRM_ERROR("Failed to add hpd irq id!\n");
4157 		return r;
4158 	}
4159 
4160 	r = register_hpd_handlers(adev);
4161 
4162 	return r;
4163 }
4164 #endif
4165 
4166 /* Register IRQ sources and initialize IRQ callbacks */
dce110_register_irq_handlers(struct amdgpu_device * adev)4167 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
4168 {
4169 	struct dc *dc = adev->dm.dc;
4170 	struct common_irq_params *c_irq_params;
4171 	struct dc_interrupt_params int_params = {0};
4172 	int r;
4173 	int i;
4174 	unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
4175 
4176 	if (adev->family >= AMDGPU_FAMILY_AI)
4177 		client_id = SOC15_IH_CLIENTID_DCE;
4178 
4179 	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
4180 	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
4181 
4182 	/*
4183 	 * Actions of amdgpu_irq_add_id():
4184 	 * 1. Register a set() function with base driver.
4185 	 *    Base driver will call set() function to enable/disable an
4186 	 *    interrupt in DC hardware.
4187 	 * 2. Register amdgpu_dm_irq_handler().
4188 	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
4189 	 *    coming from DC hardware.
4190 	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
4191 	 *    for acknowledging and handling.
4192 	 */
4193 
4194 	/* Use VBLANK interrupt */
4195 	for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
4196 		r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4197 		if (r) {
4198 			DRM_ERROR("Failed to add crtc irq id!\n");
4199 			return r;
4200 		}
4201 
4202 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4203 		int_params.irq_source =
4204 			dc_interrupt_to_irq_source(dc, i, 0);
4205 
4206 		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4207 			int_params.irq_source  < DC_IRQ_SOURCE_VBLANK1 ||
4208 			int_params.irq_source  > DC_IRQ_SOURCE_VBLANK6) {
4209 			DRM_ERROR("Failed to register vblank irq!\n");
4210 			return -EINVAL;
4211 		}
4212 
4213 		c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4214 
4215 		c_irq_params->adev = adev;
4216 		c_irq_params->irq_src = int_params.irq_source;
4217 
4218 		if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4219 			dm_crtc_high_irq, c_irq_params))
4220 			return -ENOMEM;
4221 	}
4222 
4223 	/* Use VUPDATE interrupt */
4224 	for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
4225 		r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
4226 		if (r) {
4227 			DRM_ERROR("Failed to add vupdate irq id!\n");
4228 			return r;
4229 		}
4230 
4231 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4232 		int_params.irq_source =
4233 			dc_interrupt_to_irq_source(dc, i, 0);
4234 
4235 		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4236 			int_params.irq_source  < DC_IRQ_SOURCE_VUPDATE1 ||
4237 			int_params.irq_source  > DC_IRQ_SOURCE_VUPDATE6) {
4238 			DRM_ERROR("Failed to register vupdate irq!\n");
4239 			return -EINVAL;
4240 		}
4241 
4242 		c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
4243 
4244 		c_irq_params->adev = adev;
4245 		c_irq_params->irq_src = int_params.irq_source;
4246 
4247 		if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4248 			dm_vupdate_high_irq, c_irq_params))
4249 			return -ENOMEM;
4250 	}
4251 
4252 	/* Use GRPH_PFLIP interrupt */
4253 	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
4254 			i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
4255 		r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4256 		if (r) {
4257 			DRM_ERROR("Failed to add page flip irq id!\n");
4258 			return r;
4259 		}
4260 
4261 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4262 		int_params.irq_source =
4263 			dc_interrupt_to_irq_source(dc, i, 0);
4264 
4265 		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4266 			int_params.irq_source  < DC_IRQ_SOURCE_PFLIP_FIRST ||
4267 			int_params.irq_source  > DC_IRQ_SOURCE_PFLIP_LAST) {
4268 			DRM_ERROR("Failed to register pflip irq!\n");
4269 			return -EINVAL;
4270 		}
4271 
4272 		c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
4273 
4274 		c_irq_params->adev = adev;
4275 		c_irq_params->irq_src = int_params.irq_source;
4276 
4277 		if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4278 			dm_pflip_high_irq, c_irq_params))
4279 			return -ENOMEM;
4280 	}
4281 
4282 	/* HPD */
4283 	r = amdgpu_irq_add_id(adev, client_id,
4284 			VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4285 	if (r) {
4286 		DRM_ERROR("Failed to add hpd irq id!\n");
4287 		return r;
4288 	}
4289 
4290 	r = register_hpd_handlers(adev);
4291 
4292 	return r;
4293 }
4294 
4295 /* Register IRQ sources and initialize IRQ callbacks */
dcn10_register_irq_handlers(struct amdgpu_device * adev)4296 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
4297 {
4298 	struct dc *dc = adev->dm.dc;
4299 	struct common_irq_params *c_irq_params;
4300 	struct dc_interrupt_params int_params = {0};
4301 	int r;
4302 	int i;
4303 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
4304 	static const unsigned int vrtl_int_srcid[] = {
4305 		DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
4306 		DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
4307 		DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
4308 		DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
4309 		DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
4310 		DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
4311 	};
4312 #endif
4313 
4314 	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
4315 	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
4316 
4317 	/*
4318 	 * Actions of amdgpu_irq_add_id():
4319 	 * 1. Register a set() function with base driver.
4320 	 *    Base driver will call set() function to enable/disable an
4321 	 *    interrupt in DC hardware.
4322 	 * 2. Register amdgpu_dm_irq_handler().
4323 	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
4324 	 *    coming from DC hardware.
4325 	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
4326 	 *    for acknowledging and handling.
4327 	 */
4328 
4329 	/* Use VSTARTUP interrupt */
4330 	for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
4331 			i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
4332 			i++) {
4333 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
4334 
4335 		if (r) {
4336 			DRM_ERROR("Failed to add crtc irq id!\n");
4337 			return r;
4338 		}
4339 
4340 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4341 		int_params.irq_source =
4342 			dc_interrupt_to_irq_source(dc, i, 0);
4343 
4344 		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4345 			int_params.irq_source  < DC_IRQ_SOURCE_VBLANK1 ||
4346 			int_params.irq_source  > DC_IRQ_SOURCE_VBLANK6) {
4347 			DRM_ERROR("Failed to register vblank irq!\n");
4348 			return -EINVAL;
4349 		}
4350 
4351 		c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4352 
4353 		c_irq_params->adev = adev;
4354 		c_irq_params->irq_src = int_params.irq_source;
4355 
4356 		if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4357 			dm_crtc_high_irq, c_irq_params))
4358 			return -ENOMEM;
4359 	}
4360 
4361 	/* Use otg vertical line interrupt */
4362 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
4363 	for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
4364 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
4365 				vrtl_int_srcid[i], &adev->vline0_irq);
4366 
4367 		if (r) {
4368 			DRM_ERROR("Failed to add vline0 irq id!\n");
4369 			return r;
4370 		}
4371 
4372 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4373 		int_params.irq_source =
4374 			dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
4375 
4376 		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4377 			int_params.irq_source < DC_IRQ_SOURCE_DC1_VLINE0 ||
4378 			int_params.irq_source > DC_IRQ_SOURCE_DC6_VLINE0) {
4379 			DRM_ERROR("Failed to register vline0 irq!\n");
4380 			return -EINVAL;
4381 		}
4382 
4383 		c_irq_params = &adev->dm.vline0_params[int_params.irq_source
4384 					- DC_IRQ_SOURCE_DC1_VLINE0];
4385 
4386 		c_irq_params->adev = adev;
4387 		c_irq_params->irq_src = int_params.irq_source;
4388 
4389 		if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4390 			dm_dcn_vertical_interrupt0_high_irq,
4391 			c_irq_params))
4392 			return -ENOMEM;
4393 	}
4394 #endif
4395 
4396 	/* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
4397 	 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
4398 	 * to trigger at end of each vblank, regardless of state of the lock,
4399 	 * matching DCE behaviour.
4400 	 */
4401 	for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
4402 	     i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
4403 	     i++) {
4404 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
4405 
4406 		if (r) {
4407 			DRM_ERROR("Failed to add vupdate irq id!\n");
4408 			return r;
4409 		}
4410 
4411 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4412 		int_params.irq_source =
4413 			dc_interrupt_to_irq_source(dc, i, 0);
4414 
4415 		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4416 			int_params.irq_source  < DC_IRQ_SOURCE_VUPDATE1 ||
4417 			int_params.irq_source  > DC_IRQ_SOURCE_VUPDATE6) {
4418 			DRM_ERROR("Failed to register vupdate irq!\n");
4419 			return -EINVAL;
4420 		}
4421 
4422 		c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
4423 
4424 		c_irq_params->adev = adev;
4425 		c_irq_params->irq_src = int_params.irq_source;
4426 
4427 		if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4428 			dm_vupdate_high_irq, c_irq_params))
4429 			return -ENOMEM;
4430 	}
4431 
4432 	/* Use GRPH_PFLIP interrupt */
4433 	for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
4434 			i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
4435 			i++) {
4436 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
4437 		if (r) {
4438 			DRM_ERROR("Failed to add page flip irq id!\n");
4439 			return r;
4440 		}
4441 
4442 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
4443 		int_params.irq_source =
4444 			dc_interrupt_to_irq_source(dc, i, 0);
4445 
4446 		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
4447 			int_params.irq_source  < DC_IRQ_SOURCE_PFLIP_FIRST ||
4448 			int_params.irq_source  > DC_IRQ_SOURCE_PFLIP_LAST) {
4449 			DRM_ERROR("Failed to register pflip irq!\n");
4450 			return -EINVAL;
4451 		}
4452 
4453 		c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
4454 
4455 		c_irq_params->adev = adev;
4456 		c_irq_params->irq_src = int_params.irq_source;
4457 
4458 		if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4459 			dm_pflip_high_irq, c_irq_params))
4460 			return -ENOMEM;
4461 	}
4462 
4463 	/* HPD */
4464 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
4465 			&adev->hpd_irq);
4466 	if (r) {
4467 		DRM_ERROR("Failed to add hpd irq id!\n");
4468 		return r;
4469 	}
4470 
4471 	r = register_hpd_handlers(adev);
4472 
4473 	return r;
4474 }
4475 /* Register Outbox IRQ sources and initialize IRQ callbacks */
register_outbox_irq_handlers(struct amdgpu_device * adev)4476 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
4477 {
4478 	struct dc *dc = adev->dm.dc;
4479 	struct common_irq_params *c_irq_params;
4480 	struct dc_interrupt_params int_params = {0};
4481 	int r, i;
4482 
4483 	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
4484 	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
4485 
4486 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
4487 			&adev->dmub_outbox_irq);
4488 	if (r) {
4489 		DRM_ERROR("Failed to add outbox irq id!\n");
4490 		return r;
4491 	}
4492 
4493 	if (dc->ctx->dmub_srv) {
4494 		i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
4495 		int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
4496 		int_params.irq_source =
4497 		dc_interrupt_to_irq_source(dc, i, 0);
4498 
4499 		c_irq_params = &adev->dm.dmub_outbox_params[0];
4500 
4501 		c_irq_params->adev = adev;
4502 		c_irq_params->irq_src = int_params.irq_source;
4503 
4504 		if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
4505 			dm_dmub_outbox1_low_irq, c_irq_params))
4506 			return -ENOMEM;
4507 	}
4508 
4509 	return 0;
4510 }
4511 
4512 /*
4513  * Acquires the lock for the atomic state object and returns
4514  * the new atomic state.
4515  *
4516  * This should only be called during atomic check.
4517  */
dm_atomic_get_state(struct drm_atomic_state * state,struct dm_atomic_state ** dm_state)4518 int dm_atomic_get_state(struct drm_atomic_state *state,
4519 			struct dm_atomic_state **dm_state)
4520 {
4521 	struct drm_device *dev = state->dev;
4522 	struct amdgpu_device *adev = drm_to_adev(dev);
4523 	struct amdgpu_display_manager *dm = &adev->dm;
4524 	struct drm_private_state *priv_state;
4525 
4526 	if (*dm_state)
4527 		return 0;
4528 
4529 	priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
4530 	if (IS_ERR(priv_state))
4531 		return PTR_ERR(priv_state);
4532 
4533 	*dm_state = to_dm_atomic_state(priv_state);
4534 
4535 	return 0;
4536 }
4537 
4538 static struct dm_atomic_state *
dm_atomic_get_new_state(struct drm_atomic_state * state)4539 dm_atomic_get_new_state(struct drm_atomic_state *state)
4540 {
4541 	struct drm_device *dev = state->dev;
4542 	struct amdgpu_device *adev = drm_to_adev(dev);
4543 	struct amdgpu_display_manager *dm = &adev->dm;
4544 	struct drm_private_obj *obj;
4545 	struct drm_private_state *new_obj_state;
4546 	int i;
4547 
4548 	for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
4549 		if (obj->funcs == dm->atomic_obj.funcs)
4550 			return to_dm_atomic_state(new_obj_state);
4551 	}
4552 
4553 	return NULL;
4554 }
4555 
4556 static struct drm_private_state *
dm_atomic_duplicate_state(struct drm_private_obj * obj)4557 dm_atomic_duplicate_state(struct drm_private_obj *obj)
4558 {
4559 	struct dm_atomic_state *old_state, *new_state;
4560 
4561 	new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
4562 	if (!new_state)
4563 		return NULL;
4564 
4565 	__drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
4566 
4567 	old_state = to_dm_atomic_state(obj->state);
4568 
4569 	if (old_state && old_state->context)
4570 		new_state->context = dc_state_create_copy(old_state->context);
4571 
4572 	if (!new_state->context) {
4573 		kfree(new_state);
4574 		return NULL;
4575 	}
4576 
4577 	return &new_state->base;
4578 }
4579 
dm_atomic_destroy_state(struct drm_private_obj * obj,struct drm_private_state * state)4580 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
4581 				    struct drm_private_state *state)
4582 {
4583 	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4584 
4585 	if (dm_state && dm_state->context)
4586 		dc_state_release(dm_state->context);
4587 
4588 	kfree(dm_state);
4589 }
4590 
4591 static struct drm_private_state_funcs dm_atomic_state_funcs = {
4592 	.atomic_duplicate_state = dm_atomic_duplicate_state,
4593 	.atomic_destroy_state = dm_atomic_destroy_state,
4594 };
4595 
amdgpu_dm_mode_config_init(struct amdgpu_device * adev)4596 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
4597 {
4598 	struct dm_atomic_state *state;
4599 	int r;
4600 
4601 	adev->mode_info.mode_config_initialized = true;
4602 
4603 	adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
4604 	adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4605 
4606 	adev_to_drm(adev)->mode_config.max_width = 16384;
4607 	adev_to_drm(adev)->mode_config.max_height = 16384;
4608 
4609 	adev_to_drm(adev)->mode_config.preferred_depth = 24;
4610 	if (adev->asic_type == CHIP_HAWAII)
4611 		/* disable prefer shadow for now due to hibernation issues */
4612 		adev_to_drm(adev)->mode_config.prefer_shadow = 0;
4613 	else
4614 		adev_to_drm(adev)->mode_config.prefer_shadow = 1;
4615 	/* indicates support for immediate flip */
4616 	adev_to_drm(adev)->mode_config.async_page_flip = true;
4617 
4618 	state = kzalloc(sizeof(*state), GFP_KERNEL);
4619 	if (!state)
4620 		return -ENOMEM;
4621 
4622 	state->context = dc_state_create_current_copy(adev->dm.dc);
4623 	if (!state->context) {
4624 		kfree(state);
4625 		return -ENOMEM;
4626 	}
4627 
4628 	drm_atomic_private_obj_init(adev_to_drm(adev),
4629 				    &adev->dm.atomic_obj,
4630 				    &state->base,
4631 				    &dm_atomic_state_funcs);
4632 
4633 	r = amdgpu_display_modeset_create_props(adev);
4634 	if (r) {
4635 		dc_state_release(state->context);
4636 		kfree(state);
4637 		return r;
4638 	}
4639 
4640 #ifdef AMD_PRIVATE_COLOR
4641 	if (amdgpu_dm_create_color_properties(adev)) {
4642 		dc_state_release(state->context);
4643 		kfree(state);
4644 		return -ENOMEM;
4645 	}
4646 #endif
4647 
4648 	r = amdgpu_dm_audio_init(adev);
4649 	if (r) {
4650 		dc_state_release(state->context);
4651 		kfree(state);
4652 		return r;
4653 	}
4654 
4655 	return 0;
4656 }
4657 
4658 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4659 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4660 #define AMDGPU_DM_MIN_SPREAD ((AMDGPU_DM_DEFAULT_MAX_BACKLIGHT - AMDGPU_DM_DEFAULT_MIN_BACKLIGHT) / 2)
4661 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4662 
amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager * dm,int bl_idx)4663 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4664 					    int bl_idx)
4665 {
4666 #if defined(CONFIG_ACPI)
4667 	struct amdgpu_dm_backlight_caps caps;
4668 
4669 	memset(&caps, 0, sizeof(caps));
4670 
4671 	if (dm->backlight_caps[bl_idx].caps_valid)
4672 		return;
4673 
4674 	amdgpu_acpi_get_backlight_caps(&caps);
4675 
4676 	/* validate the firmware value is sane */
4677 	if (caps.caps_valid) {
4678 		int spread = caps.max_input_signal - caps.min_input_signal;
4679 
4680 		if (caps.max_input_signal > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT ||
4681 		    caps.min_input_signal < 0 ||
4682 		    spread > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT ||
4683 		    spread < AMDGPU_DM_MIN_SPREAD) {
4684 			DRM_DEBUG_KMS("DM: Invalid backlight caps: min=%d, max=%d\n",
4685 				      caps.min_input_signal, caps.max_input_signal);
4686 			caps.caps_valid = false;
4687 		}
4688 	}
4689 
4690 	if (caps.caps_valid) {
4691 		dm->backlight_caps[bl_idx].caps_valid = true;
4692 		if (caps.aux_support)
4693 			return;
4694 		dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4695 		dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4696 	} else {
4697 		dm->backlight_caps[bl_idx].min_input_signal =
4698 				AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4699 		dm->backlight_caps[bl_idx].max_input_signal =
4700 				AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4701 	}
4702 #else
4703 	if (dm->backlight_caps[bl_idx].aux_support)
4704 		return;
4705 
4706 	dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4707 	dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4708 #endif
4709 }
4710 
get_brightness_range(const struct amdgpu_dm_backlight_caps * caps,unsigned int * min,unsigned int * max)4711 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4712 				unsigned int *min, unsigned int *max)
4713 {
4714 	if (!caps)
4715 		return 0;
4716 
4717 	if (caps->aux_support) {
4718 		// Firmware limits are in nits, DC API wants millinits.
4719 		*max = 1000 * caps->aux_max_input_signal;
4720 		*min = 1000 * caps->aux_min_input_signal;
4721 	} else {
4722 		// Firmware limits are 8-bit, PWM control is 16-bit.
4723 		*max = 0x101 * caps->max_input_signal;
4724 		*min = 0x101 * caps->min_input_signal;
4725 	}
4726 	return 1;
4727 }
4728 
convert_brightness_from_user(const struct amdgpu_dm_backlight_caps * caps,uint32_t brightness)4729 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4730 					uint32_t brightness)
4731 {
4732 	unsigned int min, max;
4733 
4734 	if (!get_brightness_range(caps, &min, &max))
4735 		return brightness;
4736 
4737 	// Rescale 0..255 to min..max
4738 	return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4739 				       AMDGPU_MAX_BL_LEVEL);
4740 }
4741 
convert_brightness_to_user(const struct amdgpu_dm_backlight_caps * caps,uint32_t brightness)4742 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4743 				      uint32_t brightness)
4744 {
4745 	unsigned int min, max;
4746 
4747 	if (!get_brightness_range(caps, &min, &max))
4748 		return brightness;
4749 
4750 	if (brightness < min)
4751 		return 0;
4752 	// Rescale min..max to 0..255
4753 	return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4754 				 max - min);
4755 }
4756 
amdgpu_dm_backlight_set_level(struct amdgpu_display_manager * dm,int bl_idx,u32 user_brightness)4757 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4758 					 int bl_idx,
4759 					 u32 user_brightness)
4760 {
4761 	struct amdgpu_dm_backlight_caps caps;
4762 	struct dc_link *link;
4763 	u32 brightness;
4764 	bool rc, reallow_idle = false;
4765 
4766 	amdgpu_dm_update_backlight_caps(dm, bl_idx);
4767 	caps = dm->backlight_caps[bl_idx];
4768 
4769 	dm->brightness[bl_idx] = user_brightness;
4770 	/* update scratch register */
4771 	if (bl_idx == 0)
4772 		amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4773 	brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4774 	link = (struct dc_link *)dm->backlight_link[bl_idx];
4775 
4776 	/* Change brightness based on AUX property */
4777 	mutex_lock(&dm->dc_lock);
4778 	if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) {
4779 		dc_allow_idle_optimizations(dm->dc, false);
4780 		reallow_idle = true;
4781 	}
4782 
4783 	if (caps.aux_support) {
4784 		rc = dc_link_set_backlight_level_nits(link, true, brightness,
4785 						      AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4786 		if (!rc)
4787 			DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4788 	} else {
4789 		struct set_backlight_level_params backlight_level_params = { 0 };
4790 
4791 		backlight_level_params.backlight_pwm_u16_16 = brightness;
4792 		backlight_level_params.transition_time_in_ms = 0;
4793 
4794 		rc = dc_link_set_backlight_level(link, &backlight_level_params);
4795 		if (!rc)
4796 			DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4797 	}
4798 
4799 	if (dm->dc->caps.ips_support && reallow_idle)
4800 		dc_allow_idle_optimizations(dm->dc, true);
4801 
4802 	mutex_unlock(&dm->dc_lock);
4803 
4804 	if (rc)
4805 		dm->actual_brightness[bl_idx] = user_brightness;
4806 }
4807 
amdgpu_dm_backlight_update_status(struct backlight_device * bd)4808 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4809 {
4810 	struct amdgpu_display_manager *dm = bl_get_data(bd);
4811 	int i;
4812 
4813 	for (i = 0; i < dm->num_of_edps; i++) {
4814 		if (bd == dm->backlight_dev[i])
4815 			break;
4816 	}
4817 	if (i >= AMDGPU_DM_MAX_NUM_EDP)
4818 		i = 0;
4819 	amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4820 
4821 	return 0;
4822 }
4823 
amdgpu_dm_backlight_get_level(struct amdgpu_display_manager * dm,int bl_idx)4824 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4825 					 int bl_idx)
4826 {
4827 	int ret;
4828 	struct amdgpu_dm_backlight_caps caps;
4829 	struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4830 
4831 	amdgpu_dm_update_backlight_caps(dm, bl_idx);
4832 	caps = dm->backlight_caps[bl_idx];
4833 
4834 	if (caps.aux_support) {
4835 		u32 avg, peak;
4836 		bool rc;
4837 
4838 		rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4839 		if (!rc)
4840 			return dm->brightness[bl_idx];
4841 		return convert_brightness_to_user(&caps, avg);
4842 	}
4843 
4844 	ret = dc_link_get_backlight_level(link);
4845 
4846 	if (ret == DC_ERROR_UNEXPECTED)
4847 		return dm->brightness[bl_idx];
4848 
4849 	return convert_brightness_to_user(&caps, ret);
4850 }
4851 
amdgpu_dm_backlight_get_brightness(struct backlight_device * bd)4852 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4853 {
4854 	struct amdgpu_display_manager *dm = bl_get_data(bd);
4855 	int i;
4856 
4857 	for (i = 0; i < dm->num_of_edps; i++) {
4858 		if (bd == dm->backlight_dev[i])
4859 			break;
4860 	}
4861 	if (i >= AMDGPU_DM_MAX_NUM_EDP)
4862 		i = 0;
4863 	return amdgpu_dm_backlight_get_level(dm, i);
4864 }
4865 
4866 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4867 	.options = BL_CORE_SUSPENDRESUME,
4868 	.get_brightness = amdgpu_dm_backlight_get_brightness,
4869 	.update_status	= amdgpu_dm_backlight_update_status,
4870 };
4871 
4872 static void
amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector * aconnector)4873 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4874 {
4875 	struct drm_device *drm = aconnector->base.dev;
4876 	struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4877 	struct backlight_properties props = { 0 };
4878 	struct amdgpu_dm_backlight_caps caps = { 0 };
4879 	char bl_name[16];
4880 
4881 	if (aconnector->bl_idx == -1)
4882 		return;
4883 
4884 	if (!acpi_video_backlight_use_native()) {
4885 		drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4886 		/* Try registering an ACPI video backlight device instead. */
4887 		acpi_video_register_backlight();
4888 		return;
4889 	}
4890 
4891 	amdgpu_acpi_get_backlight_caps(&caps);
4892 	if (caps.caps_valid) {
4893 		if (power_supply_is_system_supplied() > 0)
4894 			props.brightness = caps.ac_level;
4895 		else
4896 			props.brightness = caps.dc_level;
4897 	} else
4898 		props.brightness = AMDGPU_MAX_BL_LEVEL;
4899 
4900 	props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4901 	props.type = BACKLIGHT_RAW;
4902 
4903 	snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4904 		 drm->primary->index + aconnector->bl_idx);
4905 
4906 	dm->backlight_dev[aconnector->bl_idx] =
4907 		backlight_device_register(bl_name, aconnector->base.kdev, dm,
4908 					  &amdgpu_dm_backlight_ops, &props);
4909 
4910 	if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4911 		DRM_ERROR("DM: Backlight registration failed!\n");
4912 		dm->backlight_dev[aconnector->bl_idx] = NULL;
4913 	} else
4914 		DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4915 }
4916 
initialize_plane(struct amdgpu_display_manager * dm,struct amdgpu_mode_info * mode_info,int plane_id,enum drm_plane_type plane_type,const struct dc_plane_cap * plane_cap)4917 static int initialize_plane(struct amdgpu_display_manager *dm,
4918 			    struct amdgpu_mode_info *mode_info, int plane_id,
4919 			    enum drm_plane_type plane_type,
4920 			    const struct dc_plane_cap *plane_cap)
4921 {
4922 	struct drm_plane *plane;
4923 	unsigned long possible_crtcs;
4924 	int ret = 0;
4925 
4926 	plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4927 	if (!plane) {
4928 		DRM_ERROR("KMS: Failed to allocate plane\n");
4929 		return -ENOMEM;
4930 	}
4931 	plane->type = plane_type;
4932 
4933 	/*
4934 	 * HACK: IGT tests expect that the primary plane for a CRTC
4935 	 * can only have one possible CRTC. Only expose support for
4936 	 * any CRTC if they're not going to be used as a primary plane
4937 	 * for a CRTC - like overlay or underlay planes.
4938 	 */
4939 	possible_crtcs = 1 << plane_id;
4940 	if (plane_id >= dm->dc->caps.max_streams)
4941 		possible_crtcs = 0xff;
4942 
4943 	ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4944 
4945 	if (ret) {
4946 		DRM_ERROR("KMS: Failed to initialize plane\n");
4947 		kfree(plane);
4948 		return ret;
4949 	}
4950 
4951 	if (mode_info)
4952 		mode_info->planes[plane_id] = plane;
4953 
4954 	return ret;
4955 }
4956 
4957 
setup_backlight_device(struct amdgpu_display_manager * dm,struct amdgpu_dm_connector * aconnector)4958 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4959 				   struct amdgpu_dm_connector *aconnector)
4960 {
4961 	struct dc_link *link = aconnector->dc_link;
4962 	int bl_idx = dm->num_of_edps;
4963 
4964 	if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4965 	    link->type == dc_connection_none)
4966 		return;
4967 
4968 	if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4969 		drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4970 		return;
4971 	}
4972 
4973 	aconnector->bl_idx = bl_idx;
4974 
4975 	amdgpu_dm_update_backlight_caps(dm, bl_idx);
4976 	dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4977 	dm->backlight_link[bl_idx] = link;
4978 	dm->num_of_edps++;
4979 
4980 	update_connector_ext_caps(aconnector);
4981 }
4982 
4983 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4984 
4985 /*
4986  * In this architecture, the association
4987  * connector -> encoder -> crtc
4988  * id not really requried. The crtc and connector will hold the
4989  * display_index as an abstraction to use with DAL component
4990  *
4991  * Returns 0 on success
4992  */
amdgpu_dm_initialize_drm_device(struct amdgpu_device * adev)4993 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4994 {
4995 	struct amdgpu_display_manager *dm = &adev->dm;
4996 	s32 i;
4997 	struct amdgpu_dm_connector *aconnector = NULL;
4998 	struct amdgpu_encoder *aencoder = NULL;
4999 	struct amdgpu_mode_info *mode_info = &adev->mode_info;
5000 	u32 link_cnt;
5001 	s32 primary_planes;
5002 	enum dc_connection_type new_connection_type = dc_connection_none;
5003 	const struct dc_plane_cap *plane;
5004 	bool psr_feature_enabled = false;
5005 	bool replay_feature_enabled = false;
5006 	int max_overlay = dm->dc->caps.max_slave_planes;
5007 
5008 	dm->display_indexes_num = dm->dc->caps.max_streams;
5009 	/* Update the actual used number of crtc */
5010 	adev->mode_info.num_crtc = adev->dm.display_indexes_num;
5011 
5012 	amdgpu_dm_set_irq_funcs(adev);
5013 
5014 	link_cnt = dm->dc->caps.max_links;
5015 	if (amdgpu_dm_mode_config_init(dm->adev)) {
5016 		DRM_ERROR("DM: Failed to initialize mode config\n");
5017 		return -EINVAL;
5018 	}
5019 
5020 	/* There is one primary plane per CRTC */
5021 	primary_planes = dm->dc->caps.max_streams;
5022 	if (primary_planes > AMDGPU_MAX_PLANES) {
5023 		DRM_ERROR("DM: Plane nums out of 6 planes\n");
5024 		return -EINVAL;
5025 	}
5026 
5027 	/*
5028 	 * Initialize primary planes, implicit planes for legacy IOCTLS.
5029 	 * Order is reversed to match iteration order in atomic check.
5030 	 */
5031 	for (i = (primary_planes - 1); i >= 0; i--) {
5032 		plane = &dm->dc->caps.planes[i];
5033 
5034 		if (initialize_plane(dm, mode_info, i,
5035 				     DRM_PLANE_TYPE_PRIMARY, plane)) {
5036 			DRM_ERROR("KMS: Failed to initialize primary plane\n");
5037 			goto fail;
5038 		}
5039 	}
5040 
5041 	/*
5042 	 * Initialize overlay planes, index starting after primary planes.
5043 	 * These planes have a higher DRM index than the primary planes since
5044 	 * they should be considered as having a higher z-order.
5045 	 * Order is reversed to match iteration order in atomic check.
5046 	 *
5047 	 * Only support DCN for now, and only expose one so we don't encourage
5048 	 * userspace to use up all the pipes.
5049 	 */
5050 	for (i = 0; i < dm->dc->caps.max_planes; ++i) {
5051 		struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
5052 
5053 		/* Do not create overlay if MPO disabled */
5054 		if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
5055 			break;
5056 
5057 		if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
5058 			continue;
5059 
5060 		if (!plane->pixel_format_support.argb8888)
5061 			continue;
5062 
5063 		if (max_overlay-- == 0)
5064 			break;
5065 
5066 		if (initialize_plane(dm, NULL, primary_planes + i,
5067 				     DRM_PLANE_TYPE_OVERLAY, plane)) {
5068 			DRM_ERROR("KMS: Failed to initialize overlay plane\n");
5069 			goto fail;
5070 		}
5071 	}
5072 
5073 	for (i = 0; i < dm->dc->caps.max_streams; i++)
5074 		if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
5075 			DRM_ERROR("KMS: Failed to initialize crtc\n");
5076 			goto fail;
5077 		}
5078 
5079 	/* Use Outbox interrupt */
5080 	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
5081 	case IP_VERSION(3, 0, 0):
5082 	case IP_VERSION(3, 1, 2):
5083 	case IP_VERSION(3, 1, 3):
5084 	case IP_VERSION(3, 1, 4):
5085 	case IP_VERSION(3, 1, 5):
5086 	case IP_VERSION(3, 1, 6):
5087 	case IP_VERSION(3, 2, 0):
5088 	case IP_VERSION(3, 2, 1):
5089 	case IP_VERSION(2, 1, 0):
5090 	case IP_VERSION(3, 5, 0):
5091 	case IP_VERSION(3, 5, 1):
5092 	case IP_VERSION(4, 0, 1):
5093 		if (register_outbox_irq_handlers(dm->adev)) {
5094 			DRM_ERROR("DM: Failed to initialize IRQ\n");
5095 			goto fail;
5096 		}
5097 		break;
5098 	default:
5099 		DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
5100 			      amdgpu_ip_version(adev, DCE_HWIP, 0));
5101 	}
5102 
5103 	/* Determine whether to enable PSR support by default. */
5104 	if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
5105 		switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
5106 		case IP_VERSION(3, 1, 2):
5107 		case IP_VERSION(3, 1, 3):
5108 		case IP_VERSION(3, 1, 4):
5109 		case IP_VERSION(3, 1, 5):
5110 		case IP_VERSION(3, 1, 6):
5111 		case IP_VERSION(3, 2, 0):
5112 		case IP_VERSION(3, 2, 1):
5113 		case IP_VERSION(3, 5, 0):
5114 		case IP_VERSION(3, 5, 1):
5115 		case IP_VERSION(4, 0, 1):
5116 			psr_feature_enabled = true;
5117 			break;
5118 		default:
5119 			psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
5120 			break;
5121 		}
5122 	}
5123 
5124 	/* Determine whether to enable Replay support by default. */
5125 	if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
5126 		switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
5127 		case IP_VERSION(3, 1, 4):
5128 		case IP_VERSION(3, 2, 0):
5129 		case IP_VERSION(3, 2, 1):
5130 		case IP_VERSION(3, 5, 0):
5131 		case IP_VERSION(3, 5, 1):
5132 			replay_feature_enabled = true;
5133 			break;
5134 
5135 		default:
5136 			replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK;
5137 			break;
5138 		}
5139 	}
5140 
5141 	if (link_cnt > MAX_LINKS) {
5142 		DRM_ERROR(
5143 			"KMS: Cannot support more than %d display indexes\n",
5144 				MAX_LINKS);
5145 		goto fail;
5146 	}
5147 
5148 	/* loops over all connectors on the board */
5149 	for (i = 0; i < link_cnt; i++) {
5150 		struct dc_link *link = NULL;
5151 
5152 		link = dc_get_link_at_index(dm->dc, i);
5153 
5154 		if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) {
5155 			struct amdgpu_dm_wb_connector *wbcon = kzalloc(sizeof(*wbcon), GFP_KERNEL);
5156 
5157 			if (!wbcon) {
5158 				DRM_ERROR("KMS: Failed to allocate writeback connector\n");
5159 				continue;
5160 			}
5161 
5162 			if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) {
5163 				DRM_ERROR("KMS: Failed to initialize writeback connector\n");
5164 				kfree(wbcon);
5165 				continue;
5166 			}
5167 
5168 			link->psr_settings.psr_feature_enabled = false;
5169 			link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
5170 
5171 			continue;
5172 		}
5173 
5174 		aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
5175 		if (!aconnector)
5176 			goto fail;
5177 
5178 		aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
5179 		if (!aencoder)
5180 			goto fail;
5181 
5182 		if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
5183 			DRM_ERROR("KMS: Failed to initialize encoder\n");
5184 			goto fail;
5185 		}
5186 
5187 		if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
5188 			DRM_ERROR("KMS: Failed to initialize connector\n");
5189 			goto fail;
5190 		}
5191 
5192 		if (dm->hpd_rx_offload_wq)
5193 			dm->hpd_rx_offload_wq[aconnector->base.index].aconnector =
5194 				aconnector;
5195 
5196 		if (!dc_link_detect_connection_type(link, &new_connection_type))
5197 			DRM_ERROR("KMS: Failed to detect connector\n");
5198 
5199 		if (aconnector->base.force && new_connection_type == dc_connection_none) {
5200 			emulated_link_detect(link);
5201 			amdgpu_dm_update_connector_after_detect(aconnector);
5202 		} else {
5203 			bool ret = false;
5204 
5205 			mutex_lock(&dm->dc_lock);
5206 			dc_exit_ips_for_hw_access(dm->dc);
5207 			ret = dc_link_detect(link, DETECT_REASON_BOOT);
5208 			mutex_unlock(&dm->dc_lock);
5209 
5210 			if (ret) {
5211 				amdgpu_dm_update_connector_after_detect(aconnector);
5212 				setup_backlight_device(dm, aconnector);
5213 
5214 				/* Disable PSR if Replay can be enabled */
5215 				if (replay_feature_enabled)
5216 					if (amdgpu_dm_set_replay_caps(link, aconnector))
5217 						psr_feature_enabled = false;
5218 
5219 				if (psr_feature_enabled)
5220 					amdgpu_dm_set_psr_caps(link);
5221 			}
5222 		}
5223 		amdgpu_set_panel_orientation(&aconnector->base);
5224 	}
5225 
5226 	/* Software is initialized. Now we can register interrupt handlers. */
5227 	switch (adev->asic_type) {
5228 #if defined(CONFIG_DRM_AMD_DC_SI)
5229 	case CHIP_TAHITI:
5230 	case CHIP_PITCAIRN:
5231 	case CHIP_VERDE:
5232 	case CHIP_OLAND:
5233 		if (dce60_register_irq_handlers(dm->adev)) {
5234 			DRM_ERROR("DM: Failed to initialize IRQ\n");
5235 			goto fail;
5236 		}
5237 		break;
5238 #endif
5239 	case CHIP_BONAIRE:
5240 	case CHIP_HAWAII:
5241 	case CHIP_KAVERI:
5242 	case CHIP_KABINI:
5243 	case CHIP_MULLINS:
5244 	case CHIP_TONGA:
5245 	case CHIP_FIJI:
5246 	case CHIP_CARRIZO:
5247 	case CHIP_STONEY:
5248 	case CHIP_POLARIS11:
5249 	case CHIP_POLARIS10:
5250 	case CHIP_POLARIS12:
5251 	case CHIP_VEGAM:
5252 	case CHIP_VEGA10:
5253 	case CHIP_VEGA12:
5254 	case CHIP_VEGA20:
5255 		if (dce110_register_irq_handlers(dm->adev)) {
5256 			DRM_ERROR("DM: Failed to initialize IRQ\n");
5257 			goto fail;
5258 		}
5259 		break;
5260 	default:
5261 		switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
5262 		case IP_VERSION(1, 0, 0):
5263 		case IP_VERSION(1, 0, 1):
5264 		case IP_VERSION(2, 0, 2):
5265 		case IP_VERSION(2, 0, 3):
5266 		case IP_VERSION(2, 0, 0):
5267 		case IP_VERSION(2, 1, 0):
5268 		case IP_VERSION(3, 0, 0):
5269 		case IP_VERSION(3, 0, 2):
5270 		case IP_VERSION(3, 0, 3):
5271 		case IP_VERSION(3, 0, 1):
5272 		case IP_VERSION(3, 1, 2):
5273 		case IP_VERSION(3, 1, 3):
5274 		case IP_VERSION(3, 1, 4):
5275 		case IP_VERSION(3, 1, 5):
5276 		case IP_VERSION(3, 1, 6):
5277 		case IP_VERSION(3, 2, 0):
5278 		case IP_VERSION(3, 2, 1):
5279 		case IP_VERSION(3, 5, 0):
5280 		case IP_VERSION(3, 5, 1):
5281 		case IP_VERSION(4, 0, 1):
5282 			if (dcn10_register_irq_handlers(dm->adev)) {
5283 				DRM_ERROR("DM: Failed to initialize IRQ\n");
5284 				goto fail;
5285 			}
5286 			break;
5287 		default:
5288 			DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
5289 					amdgpu_ip_version(adev, DCE_HWIP, 0));
5290 			goto fail;
5291 		}
5292 		break;
5293 	}
5294 
5295 	return 0;
5296 fail:
5297 	kfree(aencoder);
5298 	kfree(aconnector);
5299 
5300 	return -EINVAL;
5301 }
5302 
amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager * dm)5303 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
5304 {
5305 	drm_atomic_private_obj_fini(&dm->atomic_obj);
5306 }
5307 
5308 /******************************************************************************
5309  * amdgpu_display_funcs functions
5310  *****************************************************************************/
5311 
5312 /*
5313  * dm_bandwidth_update - program display watermarks
5314  *
5315  * @adev: amdgpu_device pointer
5316  *
5317  * Calculate and program the display watermarks and line buffer allocation.
5318  */
dm_bandwidth_update(struct amdgpu_device * adev)5319 static void dm_bandwidth_update(struct amdgpu_device *adev)
5320 {
5321 	/* TODO: implement later */
5322 }
5323 
5324 static const struct amdgpu_display_funcs dm_display_funcs = {
5325 	.bandwidth_update = dm_bandwidth_update, /* called unconditionally */
5326 	.vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
5327 	.backlight_set_level = NULL, /* never called for DC */
5328 	.backlight_get_level = NULL, /* never called for DC */
5329 	.hpd_sense = NULL,/* called unconditionally */
5330 	.hpd_set_polarity = NULL, /* called unconditionally */
5331 	.hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
5332 	.page_flip_get_scanoutpos =
5333 		dm_crtc_get_scanoutpos,/* called unconditionally */
5334 	.add_encoder = NULL, /* VBIOS parsing. DAL does it. */
5335 	.add_connector = NULL, /* VBIOS parsing. DAL does it. */
5336 };
5337 
5338 #if defined(CONFIG_DEBUG_KERNEL_DC)
5339 
s3_debug_store(struct device * device,struct device_attribute * attr,const char * buf,size_t count)5340 static ssize_t s3_debug_store(struct device *device,
5341 			      struct device_attribute *attr,
5342 			      const char *buf,
5343 			      size_t count)
5344 {
5345 	int ret;
5346 	int s3_state;
5347 	struct drm_device *drm_dev = dev_get_drvdata(device);
5348 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
5349 	struct amdgpu_ip_block *ip_block;
5350 
5351 	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE);
5352 	if (!ip_block)
5353 		return -EINVAL;
5354 
5355 	ret = kstrtoint(buf, 0, &s3_state);
5356 
5357 	if (ret == 0) {
5358 		if (s3_state) {
5359 			dm_resume(ip_block);
5360 			drm_kms_helper_hotplug_event(adev_to_drm(adev));
5361 		} else
5362 			dm_suspend(ip_block);
5363 	}
5364 
5365 	return ret == 0 ? count : 0;
5366 }
5367 
5368 DEVICE_ATTR_WO(s3_debug);
5369 
5370 #endif
5371 
dm_init_microcode(struct amdgpu_device * adev)5372 static int dm_init_microcode(struct amdgpu_device *adev)
5373 {
5374 	char *fw_name_dmub;
5375 	int r;
5376 
5377 	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
5378 	case IP_VERSION(2, 1, 0):
5379 		fw_name_dmub = FIRMWARE_RENOIR_DMUB;
5380 		if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
5381 			fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
5382 		break;
5383 	case IP_VERSION(3, 0, 0):
5384 		if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
5385 			fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
5386 		else
5387 			fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
5388 		break;
5389 	case IP_VERSION(3, 0, 1):
5390 		fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
5391 		break;
5392 	case IP_VERSION(3, 0, 2):
5393 		fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
5394 		break;
5395 	case IP_VERSION(3, 0, 3):
5396 		fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
5397 		break;
5398 	case IP_VERSION(3, 1, 2):
5399 	case IP_VERSION(3, 1, 3):
5400 		fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
5401 		break;
5402 	case IP_VERSION(3, 1, 4):
5403 		fw_name_dmub = FIRMWARE_DCN_314_DMUB;
5404 		break;
5405 	case IP_VERSION(3, 1, 5):
5406 		fw_name_dmub = FIRMWARE_DCN_315_DMUB;
5407 		break;
5408 	case IP_VERSION(3, 1, 6):
5409 		fw_name_dmub = FIRMWARE_DCN316_DMUB;
5410 		break;
5411 	case IP_VERSION(3, 2, 0):
5412 		fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
5413 		break;
5414 	case IP_VERSION(3, 2, 1):
5415 		fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
5416 		break;
5417 	case IP_VERSION(3, 5, 0):
5418 		fw_name_dmub = FIRMWARE_DCN_35_DMUB;
5419 		break;
5420 	case IP_VERSION(3, 5, 1):
5421 		fw_name_dmub = FIRMWARE_DCN_351_DMUB;
5422 		break;
5423 	case IP_VERSION(4, 0, 1):
5424 		fw_name_dmub = FIRMWARE_DCN_401_DMUB;
5425 		break;
5426 	default:
5427 		/* ASIC doesn't support DMUB. */
5428 		return 0;
5429 	}
5430 	r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, AMDGPU_UCODE_REQUIRED,
5431 				 "%s", fw_name_dmub);
5432 	return r;
5433 }
5434 
dm_early_init(struct amdgpu_ip_block * ip_block)5435 static int dm_early_init(struct amdgpu_ip_block *ip_block)
5436 {
5437 	struct amdgpu_device *adev = ip_block->adev;
5438 	struct amdgpu_mode_info *mode_info = &adev->mode_info;
5439 	struct atom_context *ctx = mode_info->atom_context;
5440 	int index = GetIndexIntoMasterTable(DATA, Object_Header);
5441 	u16 data_offset;
5442 
5443 	/* if there is no object header, skip DM */
5444 	if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
5445 		adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
5446 		dev_info(adev->dev, "No object header, skipping DM\n");
5447 		return -ENOENT;
5448 	}
5449 
5450 	switch (adev->asic_type) {
5451 #if defined(CONFIG_DRM_AMD_DC_SI)
5452 	case CHIP_TAHITI:
5453 	case CHIP_PITCAIRN:
5454 	case CHIP_VERDE:
5455 		adev->mode_info.num_crtc = 6;
5456 		adev->mode_info.num_hpd = 6;
5457 		adev->mode_info.num_dig = 6;
5458 		break;
5459 	case CHIP_OLAND:
5460 		adev->mode_info.num_crtc = 2;
5461 		adev->mode_info.num_hpd = 2;
5462 		adev->mode_info.num_dig = 2;
5463 		break;
5464 #endif
5465 	case CHIP_BONAIRE:
5466 	case CHIP_HAWAII:
5467 		adev->mode_info.num_crtc = 6;
5468 		adev->mode_info.num_hpd = 6;
5469 		adev->mode_info.num_dig = 6;
5470 		break;
5471 	case CHIP_KAVERI:
5472 		adev->mode_info.num_crtc = 4;
5473 		adev->mode_info.num_hpd = 6;
5474 		adev->mode_info.num_dig = 7;
5475 		break;
5476 	case CHIP_KABINI:
5477 	case CHIP_MULLINS:
5478 		adev->mode_info.num_crtc = 2;
5479 		adev->mode_info.num_hpd = 6;
5480 		adev->mode_info.num_dig = 6;
5481 		break;
5482 	case CHIP_FIJI:
5483 	case CHIP_TONGA:
5484 		adev->mode_info.num_crtc = 6;
5485 		adev->mode_info.num_hpd = 6;
5486 		adev->mode_info.num_dig = 7;
5487 		break;
5488 	case CHIP_CARRIZO:
5489 		adev->mode_info.num_crtc = 3;
5490 		adev->mode_info.num_hpd = 6;
5491 		adev->mode_info.num_dig = 9;
5492 		break;
5493 	case CHIP_STONEY:
5494 		adev->mode_info.num_crtc = 2;
5495 		adev->mode_info.num_hpd = 6;
5496 		adev->mode_info.num_dig = 9;
5497 		break;
5498 	case CHIP_POLARIS11:
5499 	case CHIP_POLARIS12:
5500 		adev->mode_info.num_crtc = 5;
5501 		adev->mode_info.num_hpd = 5;
5502 		adev->mode_info.num_dig = 5;
5503 		break;
5504 	case CHIP_POLARIS10:
5505 	case CHIP_VEGAM:
5506 		adev->mode_info.num_crtc = 6;
5507 		adev->mode_info.num_hpd = 6;
5508 		adev->mode_info.num_dig = 6;
5509 		break;
5510 	case CHIP_VEGA10:
5511 	case CHIP_VEGA12:
5512 	case CHIP_VEGA20:
5513 		adev->mode_info.num_crtc = 6;
5514 		adev->mode_info.num_hpd = 6;
5515 		adev->mode_info.num_dig = 6;
5516 		break;
5517 	default:
5518 
5519 		switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
5520 		case IP_VERSION(2, 0, 2):
5521 		case IP_VERSION(3, 0, 0):
5522 			adev->mode_info.num_crtc = 6;
5523 			adev->mode_info.num_hpd = 6;
5524 			adev->mode_info.num_dig = 6;
5525 			break;
5526 		case IP_VERSION(2, 0, 0):
5527 		case IP_VERSION(3, 0, 2):
5528 			adev->mode_info.num_crtc = 5;
5529 			adev->mode_info.num_hpd = 5;
5530 			adev->mode_info.num_dig = 5;
5531 			break;
5532 		case IP_VERSION(2, 0, 3):
5533 		case IP_VERSION(3, 0, 3):
5534 			adev->mode_info.num_crtc = 2;
5535 			adev->mode_info.num_hpd = 2;
5536 			adev->mode_info.num_dig = 2;
5537 			break;
5538 		case IP_VERSION(1, 0, 0):
5539 		case IP_VERSION(1, 0, 1):
5540 		case IP_VERSION(3, 0, 1):
5541 		case IP_VERSION(2, 1, 0):
5542 		case IP_VERSION(3, 1, 2):
5543 		case IP_VERSION(3, 1, 3):
5544 		case IP_VERSION(3, 1, 4):
5545 		case IP_VERSION(3, 1, 5):
5546 		case IP_VERSION(3, 1, 6):
5547 		case IP_VERSION(3, 2, 0):
5548 		case IP_VERSION(3, 2, 1):
5549 		case IP_VERSION(3, 5, 0):
5550 		case IP_VERSION(3, 5, 1):
5551 		case IP_VERSION(4, 0, 1):
5552 			adev->mode_info.num_crtc = 4;
5553 			adev->mode_info.num_hpd = 4;
5554 			adev->mode_info.num_dig = 4;
5555 			break;
5556 		default:
5557 			DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
5558 					amdgpu_ip_version(adev, DCE_HWIP, 0));
5559 			return -EINVAL;
5560 		}
5561 		break;
5562 	}
5563 
5564 	if (adev->mode_info.funcs == NULL)
5565 		adev->mode_info.funcs = &dm_display_funcs;
5566 
5567 	/*
5568 	 * Note: Do NOT change adev->audio_endpt_rreg and
5569 	 * adev->audio_endpt_wreg because they are initialised in
5570 	 * amdgpu_device_init()
5571 	 */
5572 #if defined(CONFIG_DEBUG_KERNEL_DC)
5573 	device_create_file(
5574 		adev_to_drm(adev)->dev,
5575 		&dev_attr_s3_debug);
5576 #endif
5577 	adev->dc_enabled = true;
5578 
5579 	return dm_init_microcode(adev);
5580 }
5581 
modereset_required(struct drm_crtc_state * crtc_state)5582 static bool modereset_required(struct drm_crtc_state *crtc_state)
5583 {
5584 	return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
5585 }
5586 
amdgpu_dm_encoder_destroy(struct drm_encoder * encoder)5587 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
5588 {
5589 	drm_encoder_cleanup(encoder);
5590 	kfree(encoder);
5591 }
5592 
5593 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
5594 	.destroy = amdgpu_dm_encoder_destroy,
5595 };
5596 
5597 static int
fill_plane_color_attributes(const struct drm_plane_state * plane_state,const enum surface_pixel_format format,enum dc_color_space * color_space)5598 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
5599 			    const enum surface_pixel_format format,
5600 			    enum dc_color_space *color_space)
5601 {
5602 	bool full_range;
5603 
5604 	*color_space = COLOR_SPACE_SRGB;
5605 
5606 	/* DRM color properties only affect non-RGB formats. */
5607 	if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
5608 		return 0;
5609 
5610 	full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
5611 
5612 	switch (plane_state->color_encoding) {
5613 	case DRM_COLOR_YCBCR_BT601:
5614 		if (full_range)
5615 			*color_space = COLOR_SPACE_YCBCR601;
5616 		else
5617 			*color_space = COLOR_SPACE_YCBCR601_LIMITED;
5618 		break;
5619 
5620 	case DRM_COLOR_YCBCR_BT709:
5621 		if (full_range)
5622 			*color_space = COLOR_SPACE_YCBCR709;
5623 		else
5624 			*color_space = COLOR_SPACE_YCBCR709_LIMITED;
5625 		break;
5626 
5627 	case DRM_COLOR_YCBCR_BT2020:
5628 		if (full_range)
5629 			*color_space = COLOR_SPACE_2020_YCBCR;
5630 		else
5631 			return -EINVAL;
5632 		break;
5633 
5634 	default:
5635 		return -EINVAL;
5636 	}
5637 
5638 	return 0;
5639 }
5640 
5641 static int
fill_dc_plane_info_and_addr(struct amdgpu_device * adev,const struct drm_plane_state * plane_state,const u64 tiling_flags,struct dc_plane_info * plane_info,struct dc_plane_address * address,bool tmz_surface)5642 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
5643 			    const struct drm_plane_state *plane_state,
5644 			    const u64 tiling_flags,
5645 			    struct dc_plane_info *plane_info,
5646 			    struct dc_plane_address *address,
5647 			    bool tmz_surface)
5648 {
5649 	const struct drm_framebuffer *fb = plane_state->fb;
5650 	const struct amdgpu_framebuffer *afb =
5651 		to_amdgpu_framebuffer(plane_state->fb);
5652 	int ret;
5653 
5654 	memset(plane_info, 0, sizeof(*plane_info));
5655 
5656 	switch (fb->format->format) {
5657 	case DRM_FORMAT_C8:
5658 		plane_info->format =
5659 			SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
5660 		break;
5661 	case DRM_FORMAT_RGB565:
5662 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
5663 		break;
5664 	case DRM_FORMAT_XRGB8888:
5665 	case DRM_FORMAT_ARGB8888:
5666 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
5667 		break;
5668 	case DRM_FORMAT_XRGB2101010:
5669 	case DRM_FORMAT_ARGB2101010:
5670 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
5671 		break;
5672 	case DRM_FORMAT_XBGR2101010:
5673 	case DRM_FORMAT_ABGR2101010:
5674 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
5675 		break;
5676 	case DRM_FORMAT_XBGR8888:
5677 	case DRM_FORMAT_ABGR8888:
5678 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
5679 		break;
5680 	case DRM_FORMAT_NV21:
5681 		plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
5682 		break;
5683 	case DRM_FORMAT_NV12:
5684 		plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
5685 		break;
5686 	case DRM_FORMAT_P010:
5687 		plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
5688 		break;
5689 	case DRM_FORMAT_XRGB16161616F:
5690 	case DRM_FORMAT_ARGB16161616F:
5691 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
5692 		break;
5693 	case DRM_FORMAT_XBGR16161616F:
5694 	case DRM_FORMAT_ABGR16161616F:
5695 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
5696 		break;
5697 	case DRM_FORMAT_XRGB16161616:
5698 	case DRM_FORMAT_ARGB16161616:
5699 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
5700 		break;
5701 	case DRM_FORMAT_XBGR16161616:
5702 	case DRM_FORMAT_ABGR16161616:
5703 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
5704 		break;
5705 	default:
5706 		DRM_ERROR(
5707 			"Unsupported screen format %p4cc\n",
5708 			&fb->format->format);
5709 		return -EINVAL;
5710 	}
5711 
5712 	switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
5713 	case DRM_MODE_ROTATE_0:
5714 		plane_info->rotation = ROTATION_ANGLE_0;
5715 		break;
5716 	case DRM_MODE_ROTATE_90:
5717 		plane_info->rotation = ROTATION_ANGLE_90;
5718 		break;
5719 	case DRM_MODE_ROTATE_180:
5720 		plane_info->rotation = ROTATION_ANGLE_180;
5721 		break;
5722 	case DRM_MODE_ROTATE_270:
5723 		plane_info->rotation = ROTATION_ANGLE_270;
5724 		break;
5725 	default:
5726 		plane_info->rotation = ROTATION_ANGLE_0;
5727 		break;
5728 	}
5729 
5730 
5731 	plane_info->visible = true;
5732 	plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
5733 
5734 	plane_info->layer_index = plane_state->normalized_zpos;
5735 
5736 	ret = fill_plane_color_attributes(plane_state, plane_info->format,
5737 					  &plane_info->color_space);
5738 	if (ret)
5739 		return ret;
5740 
5741 	ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
5742 					   plane_info->rotation, tiling_flags,
5743 					   &plane_info->tiling_info,
5744 					   &plane_info->plane_size,
5745 					   &plane_info->dcc, address,
5746 					   tmz_surface);
5747 	if (ret)
5748 		return ret;
5749 
5750 	amdgpu_dm_plane_fill_blending_from_plane_state(
5751 		plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
5752 		&plane_info->global_alpha, &plane_info->global_alpha_value);
5753 
5754 	return 0;
5755 }
5756 
fill_dc_plane_attributes(struct amdgpu_device * adev,struct dc_plane_state * dc_plane_state,struct drm_plane_state * plane_state,struct drm_crtc_state * crtc_state)5757 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5758 				    struct dc_plane_state *dc_plane_state,
5759 				    struct drm_plane_state *plane_state,
5760 				    struct drm_crtc_state *crtc_state)
5761 {
5762 	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5763 	struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5764 	struct dc_scaling_info scaling_info;
5765 	struct dc_plane_info plane_info;
5766 	int ret;
5767 
5768 	ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5769 	if (ret)
5770 		return ret;
5771 
5772 	dc_plane_state->src_rect = scaling_info.src_rect;
5773 	dc_plane_state->dst_rect = scaling_info.dst_rect;
5774 	dc_plane_state->clip_rect = scaling_info.clip_rect;
5775 	dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5776 
5777 	ret = fill_dc_plane_info_and_addr(adev, plane_state,
5778 					  afb->tiling_flags,
5779 					  &plane_info,
5780 					  &dc_plane_state->address,
5781 					  afb->tmz_surface);
5782 	if (ret)
5783 		return ret;
5784 
5785 	dc_plane_state->format = plane_info.format;
5786 	dc_plane_state->color_space = plane_info.color_space;
5787 	dc_plane_state->format = plane_info.format;
5788 	dc_plane_state->plane_size = plane_info.plane_size;
5789 	dc_plane_state->rotation = plane_info.rotation;
5790 	dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5791 	dc_plane_state->stereo_format = plane_info.stereo_format;
5792 	dc_plane_state->tiling_info = plane_info.tiling_info;
5793 	dc_plane_state->visible = plane_info.visible;
5794 	dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5795 	dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5796 	dc_plane_state->global_alpha = plane_info.global_alpha;
5797 	dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5798 	dc_plane_state->dcc = plane_info.dcc;
5799 	dc_plane_state->layer_index = plane_info.layer_index;
5800 	dc_plane_state->flip_int_enabled = true;
5801 
5802 	/*
5803 	 * Always set input transfer function, since plane state is refreshed
5804 	 * every time.
5805 	 */
5806 	ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state,
5807 						plane_state,
5808 						dc_plane_state);
5809 	if (ret)
5810 		return ret;
5811 
5812 	return 0;
5813 }
5814 
fill_dc_dirty_rect(struct drm_plane * plane,struct rect * dirty_rect,int32_t x,s32 y,s32 width,s32 height,int * i,bool ffu)5815 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5816 				      struct rect *dirty_rect, int32_t x,
5817 				      s32 y, s32 width, s32 height,
5818 				      int *i, bool ffu)
5819 {
5820 	WARN_ON(*i >= DC_MAX_DIRTY_RECTS);
5821 
5822 	dirty_rect->x = x;
5823 	dirty_rect->y = y;
5824 	dirty_rect->width = width;
5825 	dirty_rect->height = height;
5826 
5827 	if (ffu)
5828 		drm_dbg(plane->dev,
5829 			"[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5830 			plane->base.id, width, height);
5831 	else
5832 		drm_dbg(plane->dev,
5833 			"[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5834 			plane->base.id, x, y, width, height);
5835 
5836 	(*i)++;
5837 }
5838 
5839 /**
5840  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5841  *
5842  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5843  *         remote fb
5844  * @old_plane_state: Old state of @plane
5845  * @new_plane_state: New state of @plane
5846  * @crtc_state: New state of CRTC connected to the @plane
5847  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5848  * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled.
5849  *             If PSR SU is enabled and damage clips are available, only the regions of the screen
5850  *             that have changed will be updated. If PSR SU is not enabled,
5851  *             or if damage clips are not available, the entire screen will be updated.
5852  * @dirty_regions_changed: dirty regions changed
5853  *
5854  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5855  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5856  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5857  * amdgpu_dm's.
5858  *
5859  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5860  * plane with regions that require flushing to the eDP remote buffer. In
5861  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5862  * implicitly provide damage clips without any client support via the plane
5863  * bounds.
5864  */
fill_dc_dirty_rects(struct drm_plane * plane,struct drm_plane_state * old_plane_state,struct drm_plane_state * new_plane_state,struct drm_crtc_state * crtc_state,struct dc_flip_addrs * flip_addrs,bool is_psr_su,bool * dirty_regions_changed)5865 static void fill_dc_dirty_rects(struct drm_plane *plane,
5866 				struct drm_plane_state *old_plane_state,
5867 				struct drm_plane_state *new_plane_state,
5868 				struct drm_crtc_state *crtc_state,
5869 				struct dc_flip_addrs *flip_addrs,
5870 				bool is_psr_su,
5871 				bool *dirty_regions_changed)
5872 {
5873 	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5874 	struct rect *dirty_rects = flip_addrs->dirty_rects;
5875 	u32 num_clips;
5876 	struct drm_mode_rect *clips;
5877 	bool bb_changed;
5878 	bool fb_changed;
5879 	u32 i = 0;
5880 	*dirty_regions_changed = false;
5881 
5882 	/*
5883 	 * Cursor plane has it's own dirty rect update interface. See
5884 	 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5885 	 */
5886 	if (plane->type == DRM_PLANE_TYPE_CURSOR)
5887 		return;
5888 
5889 	if (new_plane_state->rotation != DRM_MODE_ROTATE_0)
5890 		goto ffu;
5891 
5892 	num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5893 	clips = drm_plane_get_damage_clips(new_plane_state);
5894 
5895 	if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 &&
5896 						   is_psr_su)))
5897 		goto ffu;
5898 
5899 	if (!dm_crtc_state->mpo_requested) {
5900 		if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5901 			goto ffu;
5902 
5903 		for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5904 			fill_dc_dirty_rect(new_plane_state->plane,
5905 					   &dirty_rects[flip_addrs->dirty_rect_count],
5906 					   clips->x1, clips->y1,
5907 					   clips->x2 - clips->x1, clips->y2 - clips->y1,
5908 					   &flip_addrs->dirty_rect_count,
5909 					   false);
5910 		return;
5911 	}
5912 
5913 	/*
5914 	 * MPO is requested. Add entire plane bounding box to dirty rects if
5915 	 * flipped to or damaged.
5916 	 *
5917 	 * If plane is moved or resized, also add old bounding box to dirty
5918 	 * rects.
5919 	 */
5920 	fb_changed = old_plane_state->fb->base.id !=
5921 		     new_plane_state->fb->base.id;
5922 	bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5923 		      old_plane_state->crtc_y != new_plane_state->crtc_y ||
5924 		      old_plane_state->crtc_w != new_plane_state->crtc_w ||
5925 		      old_plane_state->crtc_h != new_plane_state->crtc_h);
5926 
5927 	drm_dbg(plane->dev,
5928 		"[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5929 		new_plane_state->plane->base.id,
5930 		bb_changed, fb_changed, num_clips);
5931 
5932 	*dirty_regions_changed = bb_changed;
5933 
5934 	if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS)
5935 		goto ffu;
5936 
5937 	if (bb_changed) {
5938 		fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5939 				   new_plane_state->crtc_x,
5940 				   new_plane_state->crtc_y,
5941 				   new_plane_state->crtc_w,
5942 				   new_plane_state->crtc_h, &i, false);
5943 
5944 		/* Add old plane bounding-box if plane is moved or resized */
5945 		fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5946 				   old_plane_state->crtc_x,
5947 				   old_plane_state->crtc_y,
5948 				   old_plane_state->crtc_w,
5949 				   old_plane_state->crtc_h, &i, false);
5950 	}
5951 
5952 	if (num_clips) {
5953 		for (; i < num_clips; clips++)
5954 			fill_dc_dirty_rect(new_plane_state->plane,
5955 					   &dirty_rects[i], clips->x1,
5956 					   clips->y1, clips->x2 - clips->x1,
5957 					   clips->y2 - clips->y1, &i, false);
5958 	} else if (fb_changed && !bb_changed) {
5959 		fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5960 				   new_plane_state->crtc_x,
5961 				   new_plane_state->crtc_y,
5962 				   new_plane_state->crtc_w,
5963 				   new_plane_state->crtc_h, &i, false);
5964 	}
5965 
5966 	flip_addrs->dirty_rect_count = i;
5967 	return;
5968 
5969 ffu:
5970 	fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5971 			   dm_crtc_state->base.mode.crtc_hdisplay,
5972 			   dm_crtc_state->base.mode.crtc_vdisplay,
5973 			   &flip_addrs->dirty_rect_count, true);
5974 }
5975 
update_stream_scaling_settings(const struct drm_display_mode * mode,const struct dm_connector_state * dm_state,struct dc_stream_state * stream)5976 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5977 					   const struct dm_connector_state *dm_state,
5978 					   struct dc_stream_state *stream)
5979 {
5980 	enum amdgpu_rmx_type rmx_type;
5981 
5982 	struct rect src = { 0 }; /* viewport in composition space*/
5983 	struct rect dst = { 0 }; /* stream addressable area */
5984 
5985 	/* no mode. nothing to be done */
5986 	if (!mode)
5987 		return;
5988 
5989 	/* Full screen scaling by default */
5990 	src.width = mode->hdisplay;
5991 	src.height = mode->vdisplay;
5992 	dst.width = stream->timing.h_addressable;
5993 	dst.height = stream->timing.v_addressable;
5994 
5995 	if (dm_state) {
5996 		rmx_type = dm_state->scaling;
5997 		if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5998 			if (src.width * dst.height <
5999 					src.height * dst.width) {
6000 				/* height needs less upscaling/more downscaling */
6001 				dst.width = src.width *
6002 						dst.height / src.height;
6003 			} else {
6004 				/* width needs less upscaling/more downscaling */
6005 				dst.height = src.height *
6006 						dst.width / src.width;
6007 			}
6008 		} else if (rmx_type == RMX_CENTER) {
6009 			dst = src;
6010 		}
6011 
6012 		dst.x = (stream->timing.h_addressable - dst.width) / 2;
6013 		dst.y = (stream->timing.v_addressable - dst.height) / 2;
6014 
6015 		if (dm_state->underscan_enable) {
6016 			dst.x += dm_state->underscan_hborder / 2;
6017 			dst.y += dm_state->underscan_vborder / 2;
6018 			dst.width -= dm_state->underscan_hborder;
6019 			dst.height -= dm_state->underscan_vborder;
6020 		}
6021 	}
6022 
6023 	stream->src = src;
6024 	stream->dst = dst;
6025 
6026 	DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
6027 		      dst.x, dst.y, dst.width, dst.height);
6028 
6029 }
6030 
6031 static enum dc_color_depth
convert_color_depth_from_display_info(const struct drm_connector * connector,bool is_y420,int requested_bpc)6032 convert_color_depth_from_display_info(const struct drm_connector *connector,
6033 				      bool is_y420, int requested_bpc)
6034 {
6035 	u8 bpc;
6036 
6037 	if (is_y420) {
6038 		bpc = 8;
6039 
6040 		/* Cap display bpc based on HDMI 2.0 HF-VSDB */
6041 		if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
6042 			bpc = 16;
6043 		else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
6044 			bpc = 12;
6045 		else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
6046 			bpc = 10;
6047 	} else {
6048 		bpc = (uint8_t)connector->display_info.bpc;
6049 		/* Assume 8 bpc by default if no bpc is specified. */
6050 		bpc = bpc ? bpc : 8;
6051 	}
6052 
6053 	if (requested_bpc > 0) {
6054 		/*
6055 		 * Cap display bpc based on the user requested value.
6056 		 *
6057 		 * The value for state->max_bpc may not correctly updated
6058 		 * depending on when the connector gets added to the state
6059 		 * or if this was called outside of atomic check, so it
6060 		 * can't be used directly.
6061 		 */
6062 		bpc = min_t(u8, bpc, requested_bpc);
6063 
6064 		/* Round down to the nearest even number. */
6065 		bpc = bpc - (bpc & 1);
6066 	}
6067 
6068 	switch (bpc) {
6069 	case 0:
6070 		/*
6071 		 * Temporary Work around, DRM doesn't parse color depth for
6072 		 * EDID revision before 1.4
6073 		 * TODO: Fix edid parsing
6074 		 */
6075 		return COLOR_DEPTH_888;
6076 	case 6:
6077 		return COLOR_DEPTH_666;
6078 	case 8:
6079 		return COLOR_DEPTH_888;
6080 	case 10:
6081 		return COLOR_DEPTH_101010;
6082 	case 12:
6083 		return COLOR_DEPTH_121212;
6084 	case 14:
6085 		return COLOR_DEPTH_141414;
6086 	case 16:
6087 		return COLOR_DEPTH_161616;
6088 	default:
6089 		return COLOR_DEPTH_UNDEFINED;
6090 	}
6091 }
6092 
6093 static enum dc_aspect_ratio
get_aspect_ratio(const struct drm_display_mode * mode_in)6094 get_aspect_ratio(const struct drm_display_mode *mode_in)
6095 {
6096 	/* 1-1 mapping, since both enums follow the HDMI spec. */
6097 	return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
6098 }
6099 
6100 static enum dc_color_space
get_output_color_space(const struct dc_crtc_timing * dc_crtc_timing,const struct drm_connector_state * connector_state)6101 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
6102 		       const struct drm_connector_state *connector_state)
6103 {
6104 	enum dc_color_space color_space = COLOR_SPACE_SRGB;
6105 
6106 	switch (connector_state->colorspace) {
6107 	case DRM_MODE_COLORIMETRY_BT601_YCC:
6108 		if (dc_crtc_timing->flags.Y_ONLY)
6109 			color_space = COLOR_SPACE_YCBCR601_LIMITED;
6110 		else
6111 			color_space = COLOR_SPACE_YCBCR601;
6112 		break;
6113 	case DRM_MODE_COLORIMETRY_BT709_YCC:
6114 		if (dc_crtc_timing->flags.Y_ONLY)
6115 			color_space = COLOR_SPACE_YCBCR709_LIMITED;
6116 		else
6117 			color_space = COLOR_SPACE_YCBCR709;
6118 		break;
6119 	case DRM_MODE_COLORIMETRY_OPRGB:
6120 		color_space = COLOR_SPACE_ADOBERGB;
6121 		break;
6122 	case DRM_MODE_COLORIMETRY_BT2020_RGB:
6123 	case DRM_MODE_COLORIMETRY_BT2020_YCC:
6124 		if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
6125 			color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
6126 		else
6127 			color_space = COLOR_SPACE_2020_YCBCR;
6128 		break;
6129 	case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
6130 	default:
6131 		if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
6132 			color_space = COLOR_SPACE_SRGB;
6133 		/*
6134 		 * 27030khz is the separation point between HDTV and SDTV
6135 		 * according to HDMI spec, we use YCbCr709 and YCbCr601
6136 		 * respectively
6137 		 */
6138 		} else if (dc_crtc_timing->pix_clk_100hz > 270300) {
6139 			if (dc_crtc_timing->flags.Y_ONLY)
6140 				color_space =
6141 					COLOR_SPACE_YCBCR709_LIMITED;
6142 			else
6143 				color_space = COLOR_SPACE_YCBCR709;
6144 		} else {
6145 			if (dc_crtc_timing->flags.Y_ONLY)
6146 				color_space =
6147 					COLOR_SPACE_YCBCR601_LIMITED;
6148 			else
6149 				color_space = COLOR_SPACE_YCBCR601;
6150 		}
6151 		break;
6152 	}
6153 
6154 	return color_space;
6155 }
6156 
6157 static enum display_content_type
get_output_content_type(const struct drm_connector_state * connector_state)6158 get_output_content_type(const struct drm_connector_state *connector_state)
6159 {
6160 	switch (connector_state->content_type) {
6161 	default:
6162 	case DRM_MODE_CONTENT_TYPE_NO_DATA:
6163 		return DISPLAY_CONTENT_TYPE_NO_DATA;
6164 	case DRM_MODE_CONTENT_TYPE_GRAPHICS:
6165 		return DISPLAY_CONTENT_TYPE_GRAPHICS;
6166 	case DRM_MODE_CONTENT_TYPE_PHOTO:
6167 		return DISPLAY_CONTENT_TYPE_PHOTO;
6168 	case DRM_MODE_CONTENT_TYPE_CINEMA:
6169 		return DISPLAY_CONTENT_TYPE_CINEMA;
6170 	case DRM_MODE_CONTENT_TYPE_GAME:
6171 		return DISPLAY_CONTENT_TYPE_GAME;
6172 	}
6173 }
6174 
adjust_colour_depth_from_display_info(struct dc_crtc_timing * timing_out,const struct drm_display_info * info)6175 static bool adjust_colour_depth_from_display_info(
6176 	struct dc_crtc_timing *timing_out,
6177 	const struct drm_display_info *info)
6178 {
6179 	enum dc_color_depth depth = timing_out->display_color_depth;
6180 	int normalized_clk;
6181 
6182 	do {
6183 		normalized_clk = timing_out->pix_clk_100hz / 10;
6184 		/* YCbCr 4:2:0 requires additional adjustment of 1/2 */
6185 		if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
6186 			normalized_clk /= 2;
6187 		/* Adjusting pix clock following on HDMI spec based on colour depth */
6188 		switch (depth) {
6189 		case COLOR_DEPTH_888:
6190 			break;
6191 		case COLOR_DEPTH_101010:
6192 			normalized_clk = (normalized_clk * 30) / 24;
6193 			break;
6194 		case COLOR_DEPTH_121212:
6195 			normalized_clk = (normalized_clk * 36) / 24;
6196 			break;
6197 		case COLOR_DEPTH_161616:
6198 			normalized_clk = (normalized_clk * 48) / 24;
6199 			break;
6200 		default:
6201 			/* The above depths are the only ones valid for HDMI. */
6202 			return false;
6203 		}
6204 		if (normalized_clk <= info->max_tmds_clock) {
6205 			timing_out->display_color_depth = depth;
6206 			return true;
6207 		}
6208 	} while (--depth > COLOR_DEPTH_666);
6209 	return false;
6210 }
6211 
fill_stream_properties_from_drm_display_mode(struct dc_stream_state * stream,const struct drm_display_mode * mode_in,const struct drm_connector * connector,const struct drm_connector_state * connector_state,const struct dc_stream_state * old_stream,int requested_bpc)6212 static void fill_stream_properties_from_drm_display_mode(
6213 	struct dc_stream_state *stream,
6214 	const struct drm_display_mode *mode_in,
6215 	const struct drm_connector *connector,
6216 	const struct drm_connector_state *connector_state,
6217 	const struct dc_stream_state *old_stream,
6218 	int requested_bpc)
6219 {
6220 	struct dc_crtc_timing *timing_out = &stream->timing;
6221 	const struct drm_display_info *info = &connector->display_info;
6222 	struct amdgpu_dm_connector *aconnector = NULL;
6223 	struct hdmi_vendor_infoframe hv_frame;
6224 	struct hdmi_avi_infoframe avi_frame;
6225 
6226 	if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
6227 		aconnector = to_amdgpu_dm_connector(connector);
6228 
6229 	memset(&hv_frame, 0, sizeof(hv_frame));
6230 	memset(&avi_frame, 0, sizeof(avi_frame));
6231 
6232 	timing_out->h_border_left = 0;
6233 	timing_out->h_border_right = 0;
6234 	timing_out->v_border_top = 0;
6235 	timing_out->v_border_bottom = 0;
6236 	/* TODO: un-hardcode */
6237 	if (drm_mode_is_420_only(info, mode_in)
6238 			&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6239 		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
6240 	else if (drm_mode_is_420_also(info, mode_in)
6241 			&& aconnector
6242 			&& aconnector->force_yuv420_output)
6243 		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
6244 	else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
6245 			&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6246 		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
6247 	else
6248 		timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
6249 
6250 	timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
6251 	timing_out->display_color_depth = convert_color_depth_from_display_info(
6252 		connector,
6253 		(timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
6254 		requested_bpc);
6255 	timing_out->scan_type = SCANNING_TYPE_NODATA;
6256 	timing_out->hdmi_vic = 0;
6257 
6258 	if (old_stream) {
6259 		timing_out->vic = old_stream->timing.vic;
6260 		timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
6261 		timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
6262 	} else {
6263 		timing_out->vic = drm_match_cea_mode(mode_in);
6264 		if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
6265 			timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
6266 		if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
6267 			timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
6268 	}
6269 
6270 	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
6271 		drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
6272 		timing_out->vic = avi_frame.video_code;
6273 		drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
6274 		timing_out->hdmi_vic = hv_frame.vic;
6275 	}
6276 
6277 	if (aconnector && is_freesync_video_mode(mode_in, aconnector)) {
6278 		timing_out->h_addressable = mode_in->hdisplay;
6279 		timing_out->h_total = mode_in->htotal;
6280 		timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
6281 		timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
6282 		timing_out->v_total = mode_in->vtotal;
6283 		timing_out->v_addressable = mode_in->vdisplay;
6284 		timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
6285 		timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
6286 		timing_out->pix_clk_100hz = mode_in->clock * 10;
6287 	} else {
6288 		timing_out->h_addressable = mode_in->crtc_hdisplay;
6289 		timing_out->h_total = mode_in->crtc_htotal;
6290 		timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
6291 		timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
6292 		timing_out->v_total = mode_in->crtc_vtotal;
6293 		timing_out->v_addressable = mode_in->crtc_vdisplay;
6294 		timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
6295 		timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
6296 		timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
6297 	}
6298 
6299 	timing_out->aspect_ratio = get_aspect_ratio(mode_in);
6300 
6301 	stream->out_transfer_func.type = TF_TYPE_PREDEFINED;
6302 	stream->out_transfer_func.tf = TRANSFER_FUNCTION_SRGB;
6303 	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
6304 		if (!adjust_colour_depth_from_display_info(timing_out, info) &&
6305 		    drm_mode_is_420_also(info, mode_in) &&
6306 		    timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
6307 			timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
6308 			adjust_colour_depth_from_display_info(timing_out, info);
6309 		}
6310 	}
6311 
6312 	stream->output_color_space = get_output_color_space(timing_out, connector_state);
6313 	stream->content_type = get_output_content_type(connector_state);
6314 }
6315 
fill_audio_info(struct audio_info * audio_info,const struct drm_connector * drm_connector,const struct dc_sink * dc_sink)6316 static void fill_audio_info(struct audio_info *audio_info,
6317 			    const struct drm_connector *drm_connector,
6318 			    const struct dc_sink *dc_sink)
6319 {
6320 	int i = 0;
6321 	int cea_revision = 0;
6322 	const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
6323 
6324 	audio_info->manufacture_id = edid_caps->manufacturer_id;
6325 	audio_info->product_id = edid_caps->product_id;
6326 
6327 	cea_revision = drm_connector->display_info.cea_rev;
6328 
6329 	strscpy(audio_info->display_name,
6330 		edid_caps->display_name,
6331 		AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
6332 
6333 	if (cea_revision >= 3) {
6334 		audio_info->mode_count = edid_caps->audio_mode_count;
6335 
6336 		for (i = 0; i < audio_info->mode_count; ++i) {
6337 			audio_info->modes[i].format_code =
6338 					(enum audio_format_code)
6339 					(edid_caps->audio_modes[i].format_code);
6340 			audio_info->modes[i].channel_count =
6341 					edid_caps->audio_modes[i].channel_count;
6342 			audio_info->modes[i].sample_rates.all =
6343 					edid_caps->audio_modes[i].sample_rate;
6344 			audio_info->modes[i].sample_size =
6345 					edid_caps->audio_modes[i].sample_size;
6346 		}
6347 	}
6348 
6349 	audio_info->flags.all = edid_caps->speaker_flags;
6350 
6351 	/* TODO: We only check for the progressive mode, check for interlace mode too */
6352 	if (drm_connector->latency_present[0]) {
6353 		audio_info->video_latency = drm_connector->video_latency[0];
6354 		audio_info->audio_latency = drm_connector->audio_latency[0];
6355 	}
6356 
6357 	/* TODO: For DP, video and audio latency should be calculated from DPCD caps */
6358 
6359 }
6360 
6361 static void
copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode * src_mode,struct drm_display_mode * dst_mode)6362 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
6363 				      struct drm_display_mode *dst_mode)
6364 {
6365 	dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
6366 	dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
6367 	dst_mode->crtc_clock = src_mode->crtc_clock;
6368 	dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
6369 	dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
6370 	dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
6371 	dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
6372 	dst_mode->crtc_htotal = src_mode->crtc_htotal;
6373 	dst_mode->crtc_hskew = src_mode->crtc_hskew;
6374 	dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
6375 	dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
6376 	dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
6377 	dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
6378 	dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
6379 }
6380 
6381 static void
decide_crtc_timing_for_drm_display_mode(struct drm_display_mode * drm_mode,const struct drm_display_mode * native_mode,bool scale_enabled)6382 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
6383 					const struct drm_display_mode *native_mode,
6384 					bool scale_enabled)
6385 {
6386 	if (scale_enabled) {
6387 		copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
6388 	} else if (native_mode->clock == drm_mode->clock &&
6389 			native_mode->htotal == drm_mode->htotal &&
6390 			native_mode->vtotal == drm_mode->vtotal) {
6391 		copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
6392 	} else {
6393 		/* no scaling nor amdgpu inserted, no need to patch */
6394 	}
6395 }
6396 
6397 static struct dc_sink *
create_fake_sink(struct dc_link * link)6398 create_fake_sink(struct dc_link *link)
6399 {
6400 	struct dc_sink_init_data sink_init_data = { 0 };
6401 	struct dc_sink *sink = NULL;
6402 
6403 	sink_init_data.link = link;
6404 	sink_init_data.sink_signal = link->connector_signal;
6405 
6406 	sink = dc_sink_create(&sink_init_data);
6407 	if (!sink) {
6408 		DRM_ERROR("Failed to create sink!\n");
6409 		return NULL;
6410 	}
6411 	sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
6412 
6413 	return sink;
6414 }
6415 
set_multisync_trigger_params(struct dc_stream_state * stream)6416 static void set_multisync_trigger_params(
6417 		struct dc_stream_state *stream)
6418 {
6419 	struct dc_stream_state *master = NULL;
6420 
6421 	if (stream->triggered_crtc_reset.enabled) {
6422 		master = stream->triggered_crtc_reset.event_source;
6423 		stream->triggered_crtc_reset.event =
6424 			master->timing.flags.VSYNC_POSITIVE_POLARITY ?
6425 			CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
6426 		stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
6427 	}
6428 }
6429 
set_master_stream(struct dc_stream_state * stream_set[],int stream_count)6430 static void set_master_stream(struct dc_stream_state *stream_set[],
6431 			      int stream_count)
6432 {
6433 	int j, highest_rfr = 0, master_stream = 0;
6434 
6435 	for (j = 0;  j < stream_count; j++) {
6436 		if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
6437 			int refresh_rate = 0;
6438 
6439 			refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
6440 				(stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
6441 			if (refresh_rate > highest_rfr) {
6442 				highest_rfr = refresh_rate;
6443 				master_stream = j;
6444 			}
6445 		}
6446 	}
6447 	for (j = 0;  j < stream_count; j++) {
6448 		if (stream_set[j])
6449 			stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
6450 	}
6451 }
6452 
dm_enable_per_frame_crtc_master_sync(struct dc_state * context)6453 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
6454 {
6455 	int i = 0;
6456 	struct dc_stream_state *stream;
6457 
6458 	if (context->stream_count < 2)
6459 		return;
6460 	for (i = 0; i < context->stream_count ; i++) {
6461 		if (!context->streams[i])
6462 			continue;
6463 		/*
6464 		 * TODO: add a function to read AMD VSDB bits and set
6465 		 * crtc_sync_master.multi_sync_enabled flag
6466 		 * For now it's set to false
6467 		 */
6468 	}
6469 
6470 	set_master_stream(context->streams, context->stream_count);
6471 
6472 	for (i = 0; i < context->stream_count ; i++) {
6473 		stream = context->streams[i];
6474 
6475 		if (!stream)
6476 			continue;
6477 
6478 		set_multisync_trigger_params(stream);
6479 	}
6480 }
6481 
6482 /**
6483  * DOC: FreeSync Video
6484  *
6485  * When a userspace application wants to play a video, the content follows a
6486  * standard format definition that usually specifies the FPS for that format.
6487  * The below list illustrates some video format and the expected FPS,
6488  * respectively:
6489  *
6490  * - TV/NTSC (23.976 FPS)
6491  * - Cinema (24 FPS)
6492  * - TV/PAL (25 FPS)
6493  * - TV/NTSC (29.97 FPS)
6494  * - TV/NTSC (30 FPS)
6495  * - Cinema HFR (48 FPS)
6496  * - TV/PAL (50 FPS)
6497  * - Commonly used (60 FPS)
6498  * - Multiples of 24 (48,72,96 FPS)
6499  *
6500  * The list of standards video format is not huge and can be added to the
6501  * connector modeset list beforehand. With that, userspace can leverage
6502  * FreeSync to extends the front porch in order to attain the target refresh
6503  * rate. Such a switch will happen seamlessly, without screen blanking or
6504  * reprogramming of the output in any other way. If the userspace requests a
6505  * modesetting change compatible with FreeSync modes that only differ in the
6506  * refresh rate, DC will skip the full update and avoid blink during the
6507  * transition. For example, the video player can change the modesetting from
6508  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
6509  * causing any display blink. This same concept can be applied to a mode
6510  * setting change.
6511  */
6512 static struct drm_display_mode *
get_highest_refresh_rate_mode(struct amdgpu_dm_connector * aconnector,bool use_probed_modes)6513 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
6514 		bool use_probed_modes)
6515 {
6516 	struct drm_display_mode *m, *m_pref = NULL;
6517 	u16 current_refresh, highest_refresh;
6518 	struct list_head *list_head = use_probed_modes ?
6519 		&aconnector->base.probed_modes :
6520 		&aconnector->base.modes;
6521 
6522 	if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
6523 		return NULL;
6524 
6525 	if (aconnector->freesync_vid_base.clock != 0)
6526 		return &aconnector->freesync_vid_base;
6527 
6528 	/* Find the preferred mode */
6529 	list_for_each_entry(m, list_head, head) {
6530 		if (m->type & DRM_MODE_TYPE_PREFERRED) {
6531 			m_pref = m;
6532 			break;
6533 		}
6534 	}
6535 
6536 	if (!m_pref) {
6537 		/* Probably an EDID with no preferred mode. Fallback to first entry */
6538 		m_pref = list_first_entry_or_null(
6539 				&aconnector->base.modes, struct drm_display_mode, head);
6540 		if (!m_pref) {
6541 			DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
6542 			return NULL;
6543 		}
6544 	}
6545 
6546 	highest_refresh = drm_mode_vrefresh(m_pref);
6547 
6548 	/*
6549 	 * Find the mode with highest refresh rate with same resolution.
6550 	 * For some monitors, preferred mode is not the mode with highest
6551 	 * supported refresh rate.
6552 	 */
6553 	list_for_each_entry(m, list_head, head) {
6554 		current_refresh  = drm_mode_vrefresh(m);
6555 
6556 		if (m->hdisplay == m_pref->hdisplay &&
6557 		    m->vdisplay == m_pref->vdisplay &&
6558 		    highest_refresh < current_refresh) {
6559 			highest_refresh = current_refresh;
6560 			m_pref = m;
6561 		}
6562 	}
6563 
6564 	drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
6565 	return m_pref;
6566 }
6567 
is_freesync_video_mode(const struct drm_display_mode * mode,struct amdgpu_dm_connector * aconnector)6568 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
6569 		struct amdgpu_dm_connector *aconnector)
6570 {
6571 	struct drm_display_mode *high_mode;
6572 	int timing_diff;
6573 
6574 	high_mode = get_highest_refresh_rate_mode(aconnector, false);
6575 	if (!high_mode || !mode)
6576 		return false;
6577 
6578 	timing_diff = high_mode->vtotal - mode->vtotal;
6579 
6580 	if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
6581 	    high_mode->hdisplay != mode->hdisplay ||
6582 	    high_mode->vdisplay != mode->vdisplay ||
6583 	    high_mode->hsync_start != mode->hsync_start ||
6584 	    high_mode->hsync_end != mode->hsync_end ||
6585 	    high_mode->htotal != mode->htotal ||
6586 	    high_mode->hskew != mode->hskew ||
6587 	    high_mode->vscan != mode->vscan ||
6588 	    high_mode->vsync_start - mode->vsync_start != timing_diff ||
6589 	    high_mode->vsync_end - mode->vsync_end != timing_diff)
6590 		return false;
6591 	else
6592 		return true;
6593 }
6594 
6595 #if defined(CONFIG_DRM_AMD_DC_FP)
update_dsc_caps(struct amdgpu_dm_connector * aconnector,struct dc_sink * sink,struct dc_stream_state * stream,struct dsc_dec_dpcd_caps * dsc_caps)6596 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
6597 			    struct dc_sink *sink, struct dc_stream_state *stream,
6598 			    struct dsc_dec_dpcd_caps *dsc_caps)
6599 {
6600 	stream->timing.flags.DSC = 0;
6601 	dsc_caps->is_dsc_supported = false;
6602 
6603 	if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
6604 	    sink->sink_signal == SIGNAL_TYPE_EDP)) {
6605 		if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
6606 			sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
6607 			dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
6608 				aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
6609 				aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
6610 				dsc_caps);
6611 	}
6612 }
6613 
apply_dsc_policy_for_edp(struct amdgpu_dm_connector * aconnector,struct dc_sink * sink,struct dc_stream_state * stream,struct dsc_dec_dpcd_caps * dsc_caps,uint32_t max_dsc_target_bpp_limit_override)6614 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
6615 				    struct dc_sink *sink, struct dc_stream_state *stream,
6616 				    struct dsc_dec_dpcd_caps *dsc_caps,
6617 				    uint32_t max_dsc_target_bpp_limit_override)
6618 {
6619 	const struct dc_link_settings *verified_link_cap = NULL;
6620 	u32 link_bw_in_kbps;
6621 	u32 edp_min_bpp_x16, edp_max_bpp_x16;
6622 	struct dc *dc = sink->ctx->dc;
6623 	struct dc_dsc_bw_range bw_range = {0};
6624 	struct dc_dsc_config dsc_cfg = {0};
6625 	struct dc_dsc_config_options dsc_options = {0};
6626 
6627 	dc_dsc_get_default_config_option(dc, &dsc_options);
6628 	dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
6629 
6630 	verified_link_cap = dc_link_get_link_cap(stream->link);
6631 	link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
6632 	edp_min_bpp_x16 = 8 * 16;
6633 	edp_max_bpp_x16 = 8 * 16;
6634 
6635 	if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
6636 		edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
6637 
6638 	if (edp_max_bpp_x16 < edp_min_bpp_x16)
6639 		edp_min_bpp_x16 = edp_max_bpp_x16;
6640 
6641 	if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
6642 				dc->debug.dsc_min_slice_height_override,
6643 				edp_min_bpp_x16, edp_max_bpp_x16,
6644 				dsc_caps,
6645 				&stream->timing,
6646 				dc_link_get_highest_encoding_format(aconnector->dc_link),
6647 				&bw_range)) {
6648 
6649 		if (bw_range.max_kbps < link_bw_in_kbps) {
6650 			if (dc_dsc_compute_config(dc->res_pool->dscs[0],
6651 					dsc_caps,
6652 					&dsc_options,
6653 					0,
6654 					&stream->timing,
6655 					dc_link_get_highest_encoding_format(aconnector->dc_link),
6656 					&dsc_cfg)) {
6657 				stream->timing.dsc_cfg = dsc_cfg;
6658 				stream->timing.flags.DSC = 1;
6659 				stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
6660 			}
6661 			return;
6662 		}
6663 	}
6664 
6665 	if (dc_dsc_compute_config(dc->res_pool->dscs[0],
6666 				dsc_caps,
6667 				&dsc_options,
6668 				link_bw_in_kbps,
6669 				&stream->timing,
6670 				dc_link_get_highest_encoding_format(aconnector->dc_link),
6671 				&dsc_cfg)) {
6672 		stream->timing.dsc_cfg = dsc_cfg;
6673 		stream->timing.flags.DSC = 1;
6674 	}
6675 }
6676 
apply_dsc_policy_for_stream(struct amdgpu_dm_connector * aconnector,struct dc_sink * sink,struct dc_stream_state * stream,struct dsc_dec_dpcd_caps * dsc_caps)6677 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
6678 					struct dc_sink *sink, struct dc_stream_state *stream,
6679 					struct dsc_dec_dpcd_caps *dsc_caps)
6680 {
6681 	struct drm_connector *drm_connector = &aconnector->base;
6682 	u32 link_bandwidth_kbps;
6683 	struct dc *dc = sink->ctx->dc;
6684 	u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
6685 	u32 dsc_max_supported_bw_in_kbps;
6686 	u32 max_dsc_target_bpp_limit_override =
6687 		drm_connector->display_info.max_dsc_bpp;
6688 	struct dc_dsc_config_options dsc_options = {0};
6689 
6690 	dc_dsc_get_default_config_option(dc, &dsc_options);
6691 	dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
6692 
6693 	link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
6694 							dc_link_get_link_cap(aconnector->dc_link));
6695 
6696 	/* Set DSC policy according to dsc_clock_en */
6697 	dc_dsc_policy_set_enable_dsc_when_not_needed(
6698 		aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
6699 
6700 	if (sink->sink_signal == SIGNAL_TYPE_EDP &&
6701 	    !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
6702 	    dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
6703 
6704 		apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
6705 
6706 	} else if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6707 		if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
6708 			if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6709 						dsc_caps,
6710 						&dsc_options,
6711 						link_bandwidth_kbps,
6712 						&stream->timing,
6713 						dc_link_get_highest_encoding_format(aconnector->dc_link),
6714 						&stream->timing.dsc_cfg)) {
6715 				stream->timing.flags.DSC = 1;
6716 				DRM_DEBUG_DRIVER("%s: SST_DSC [%s] DSC is selected from SST RX\n",
6717 							__func__, drm_connector->name);
6718 			}
6719 		} else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
6720 			timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
6721 					dc_link_get_highest_encoding_format(aconnector->dc_link));
6722 			max_supported_bw_in_kbps = link_bandwidth_kbps;
6723 			dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
6724 
6725 			if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
6726 					max_supported_bw_in_kbps > 0 &&
6727 					dsc_max_supported_bw_in_kbps > 0)
6728 				if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6729 						dsc_caps,
6730 						&dsc_options,
6731 						dsc_max_supported_bw_in_kbps,
6732 						&stream->timing,
6733 						dc_link_get_highest_encoding_format(aconnector->dc_link),
6734 						&stream->timing.dsc_cfg)) {
6735 					stream->timing.flags.DSC = 1;
6736 					DRM_DEBUG_DRIVER("%s: SST_DSC [%s] DSC is selected from DP-HDMI PCON\n",
6737 									 __func__, drm_connector->name);
6738 				}
6739 		}
6740 	}
6741 
6742 	/* Overwrite the stream flag if DSC is enabled through debugfs */
6743 	if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
6744 		stream->timing.flags.DSC = 1;
6745 
6746 	if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
6747 		stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
6748 
6749 	if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
6750 		stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
6751 
6752 	if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
6753 		stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
6754 }
6755 #endif
6756 
6757 static struct dc_stream_state *
create_stream_for_sink(struct drm_connector * connector,const struct drm_display_mode * drm_mode,const struct dm_connector_state * dm_state,const struct dc_stream_state * old_stream,int requested_bpc)6758 create_stream_for_sink(struct drm_connector *connector,
6759 		       const struct drm_display_mode *drm_mode,
6760 		       const struct dm_connector_state *dm_state,
6761 		       const struct dc_stream_state *old_stream,
6762 		       int requested_bpc)
6763 {
6764 	struct amdgpu_dm_connector *aconnector = NULL;
6765 	struct drm_display_mode *preferred_mode = NULL;
6766 	const struct drm_connector_state *con_state = &dm_state->base;
6767 	struct dc_stream_state *stream = NULL;
6768 	struct drm_display_mode mode;
6769 	struct drm_display_mode saved_mode;
6770 	struct drm_display_mode *freesync_mode = NULL;
6771 	bool native_mode_found = false;
6772 	bool recalculate_timing = false;
6773 	bool scale = dm_state->scaling != RMX_OFF;
6774 	int mode_refresh;
6775 	int preferred_refresh = 0;
6776 	enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
6777 #if defined(CONFIG_DRM_AMD_DC_FP)
6778 	struct dsc_dec_dpcd_caps dsc_caps;
6779 #endif
6780 	struct dc_link *link = NULL;
6781 	struct dc_sink *sink = NULL;
6782 
6783 	drm_mode_init(&mode, drm_mode);
6784 	memset(&saved_mode, 0, sizeof(saved_mode));
6785 
6786 	if (connector == NULL) {
6787 		DRM_ERROR("connector is NULL!\n");
6788 		return stream;
6789 	}
6790 
6791 	if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) {
6792 		aconnector = NULL;
6793 		aconnector = to_amdgpu_dm_connector(connector);
6794 		link = aconnector->dc_link;
6795 	} else {
6796 		struct drm_writeback_connector *wbcon = NULL;
6797 		struct amdgpu_dm_wb_connector *dm_wbcon = NULL;
6798 
6799 		wbcon = drm_connector_to_writeback(connector);
6800 		dm_wbcon = to_amdgpu_dm_wb_connector(wbcon);
6801 		link = dm_wbcon->link;
6802 	}
6803 
6804 	if (!aconnector || !aconnector->dc_sink) {
6805 		sink = create_fake_sink(link);
6806 		if (!sink)
6807 			return stream;
6808 
6809 	} else {
6810 		sink = aconnector->dc_sink;
6811 		dc_sink_retain(sink);
6812 	}
6813 
6814 	stream = dc_create_stream_for_sink(sink);
6815 
6816 	if (stream == NULL) {
6817 		DRM_ERROR("Failed to create stream for sink!\n");
6818 		goto finish;
6819 	}
6820 
6821 	/* We leave this NULL for writeback connectors */
6822 	stream->dm_stream_context = aconnector;
6823 
6824 	stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6825 		connector->display_info.hdmi.scdc.scrambling.low_rates;
6826 
6827 	list_for_each_entry(preferred_mode, &connector->modes, head) {
6828 		/* Search for preferred mode */
6829 		if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6830 			native_mode_found = true;
6831 			break;
6832 		}
6833 	}
6834 	if (!native_mode_found)
6835 		preferred_mode = list_first_entry_or_null(
6836 				&connector->modes,
6837 				struct drm_display_mode,
6838 				head);
6839 
6840 	mode_refresh = drm_mode_vrefresh(&mode);
6841 
6842 	if (preferred_mode == NULL) {
6843 		/*
6844 		 * This may not be an error, the use case is when we have no
6845 		 * usermode calls to reset and set mode upon hotplug. In this
6846 		 * case, we call set mode ourselves to restore the previous mode
6847 		 * and the modelist may not be filled in time.
6848 		 */
6849 		DRM_DEBUG_DRIVER("No preferred mode found\n");
6850 	} else if (aconnector) {
6851 		recalculate_timing = amdgpu_freesync_vid_mode &&
6852 				 is_freesync_video_mode(&mode, aconnector);
6853 		if (recalculate_timing) {
6854 			freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6855 			drm_mode_copy(&saved_mode, &mode);
6856 			saved_mode.picture_aspect_ratio = mode.picture_aspect_ratio;
6857 			drm_mode_copy(&mode, freesync_mode);
6858 			mode.picture_aspect_ratio = saved_mode.picture_aspect_ratio;
6859 		} else {
6860 			decide_crtc_timing_for_drm_display_mode(
6861 					&mode, preferred_mode, scale);
6862 
6863 			preferred_refresh = drm_mode_vrefresh(preferred_mode);
6864 		}
6865 	}
6866 
6867 	if (recalculate_timing)
6868 		drm_mode_set_crtcinfo(&saved_mode, 0);
6869 
6870 	/*
6871 	 * If scaling is enabled and refresh rate didn't change
6872 	 * we copy the vic and polarities of the old timings
6873 	 */
6874 	if (!scale || mode_refresh != preferred_refresh)
6875 		fill_stream_properties_from_drm_display_mode(
6876 			stream, &mode, connector, con_state, NULL,
6877 			requested_bpc);
6878 	else
6879 		fill_stream_properties_from_drm_display_mode(
6880 			stream, &mode, connector, con_state, old_stream,
6881 			requested_bpc);
6882 
6883 	/* The rest isn't needed for writeback connectors */
6884 	if (!aconnector)
6885 		goto finish;
6886 
6887 	if (aconnector->timing_changed) {
6888 		drm_dbg(aconnector->base.dev,
6889 			"overriding timing for automated test, bpc %d, changing to %d\n",
6890 			stream->timing.display_color_depth,
6891 			aconnector->timing_requested->display_color_depth);
6892 		stream->timing = *aconnector->timing_requested;
6893 	}
6894 
6895 #if defined(CONFIG_DRM_AMD_DC_FP)
6896 	/* SST DSC determination policy */
6897 	update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6898 	if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6899 		apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6900 #endif
6901 
6902 	update_stream_scaling_settings(&mode, dm_state, stream);
6903 
6904 	fill_audio_info(
6905 		&stream->audio_info,
6906 		connector,
6907 		sink);
6908 
6909 	update_stream_signal(stream, sink);
6910 
6911 	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6912 		mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6913 
6914 	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
6915 	    stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
6916 	    stream->signal == SIGNAL_TYPE_EDP) {
6917 		const struct dc_edid_caps *edid_caps;
6918 		unsigned int disable_colorimetry = 0;
6919 
6920 		if (aconnector->dc_sink) {
6921 			edid_caps = &aconnector->dc_sink->edid_caps;
6922 			disable_colorimetry = edid_caps->panel_patch.disable_colorimetry;
6923 		}
6924 
6925 		//
6926 		// should decide stream support vsc sdp colorimetry capability
6927 		// before building vsc info packet
6928 		//
6929 		stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 &&
6930 						      stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
6931 						      !disable_colorimetry;
6932 
6933 		if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22)
6934 			tf = TRANSFER_FUNC_GAMMA_22;
6935 		mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6936 		aconnector->sr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6937 
6938 	}
6939 finish:
6940 	dc_sink_release(sink);
6941 
6942 	return stream;
6943 }
6944 
6945 static enum drm_connector_status
amdgpu_dm_connector_detect(struct drm_connector * connector,bool force)6946 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6947 {
6948 	bool connected;
6949 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6950 
6951 	/*
6952 	 * Notes:
6953 	 * 1. This interface is NOT called in context of HPD irq.
6954 	 * 2. This interface *is called* in context of user-mode ioctl. Which
6955 	 * makes it a bad place for *any* MST-related activity.
6956 	 */
6957 
6958 	if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6959 	    !aconnector->fake_enable)
6960 		connected = (aconnector->dc_sink != NULL);
6961 	else
6962 		connected = (aconnector->base.force == DRM_FORCE_ON ||
6963 				aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6964 
6965 	update_subconnector_property(aconnector);
6966 
6967 	return (connected ? connector_status_connected :
6968 			connector_status_disconnected);
6969 }
6970 
amdgpu_dm_connector_atomic_set_property(struct drm_connector * connector,struct drm_connector_state * connector_state,struct drm_property * property,uint64_t val)6971 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6972 					    struct drm_connector_state *connector_state,
6973 					    struct drm_property *property,
6974 					    uint64_t val)
6975 {
6976 	struct drm_device *dev = connector->dev;
6977 	struct amdgpu_device *adev = drm_to_adev(dev);
6978 	struct dm_connector_state *dm_old_state =
6979 		to_dm_connector_state(connector->state);
6980 	struct dm_connector_state *dm_new_state =
6981 		to_dm_connector_state(connector_state);
6982 
6983 	int ret = -EINVAL;
6984 
6985 	if (property == dev->mode_config.scaling_mode_property) {
6986 		enum amdgpu_rmx_type rmx_type;
6987 
6988 		switch (val) {
6989 		case DRM_MODE_SCALE_CENTER:
6990 			rmx_type = RMX_CENTER;
6991 			break;
6992 		case DRM_MODE_SCALE_ASPECT:
6993 			rmx_type = RMX_ASPECT;
6994 			break;
6995 		case DRM_MODE_SCALE_FULLSCREEN:
6996 			rmx_type = RMX_FULL;
6997 			break;
6998 		case DRM_MODE_SCALE_NONE:
6999 		default:
7000 			rmx_type = RMX_OFF;
7001 			break;
7002 		}
7003 
7004 		if (dm_old_state->scaling == rmx_type)
7005 			return 0;
7006 
7007 		dm_new_state->scaling = rmx_type;
7008 		ret = 0;
7009 	} else if (property == adev->mode_info.underscan_hborder_property) {
7010 		dm_new_state->underscan_hborder = val;
7011 		ret = 0;
7012 	} else if (property == adev->mode_info.underscan_vborder_property) {
7013 		dm_new_state->underscan_vborder = val;
7014 		ret = 0;
7015 	} else if (property == adev->mode_info.underscan_property) {
7016 		dm_new_state->underscan_enable = val;
7017 		ret = 0;
7018 	}
7019 
7020 	return ret;
7021 }
7022 
amdgpu_dm_connector_atomic_get_property(struct drm_connector * connector,const struct drm_connector_state * state,struct drm_property * property,uint64_t * val)7023 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
7024 					    const struct drm_connector_state *state,
7025 					    struct drm_property *property,
7026 					    uint64_t *val)
7027 {
7028 	struct drm_device *dev = connector->dev;
7029 	struct amdgpu_device *adev = drm_to_adev(dev);
7030 	struct dm_connector_state *dm_state =
7031 		to_dm_connector_state(state);
7032 	int ret = -EINVAL;
7033 
7034 	if (property == dev->mode_config.scaling_mode_property) {
7035 		switch (dm_state->scaling) {
7036 		case RMX_CENTER:
7037 			*val = DRM_MODE_SCALE_CENTER;
7038 			break;
7039 		case RMX_ASPECT:
7040 			*val = DRM_MODE_SCALE_ASPECT;
7041 			break;
7042 		case RMX_FULL:
7043 			*val = DRM_MODE_SCALE_FULLSCREEN;
7044 			break;
7045 		case RMX_OFF:
7046 		default:
7047 			*val = DRM_MODE_SCALE_NONE;
7048 			break;
7049 		}
7050 		ret = 0;
7051 	} else if (property == adev->mode_info.underscan_hborder_property) {
7052 		*val = dm_state->underscan_hborder;
7053 		ret = 0;
7054 	} else if (property == adev->mode_info.underscan_vborder_property) {
7055 		*val = dm_state->underscan_vborder;
7056 		ret = 0;
7057 	} else if (property == adev->mode_info.underscan_property) {
7058 		*val = dm_state->underscan_enable;
7059 		ret = 0;
7060 	}
7061 
7062 	return ret;
7063 }
7064 
7065 /**
7066  * DOC: panel power savings
7067  *
7068  * The display manager allows you to set your desired **panel power savings**
7069  * level (between 0-4, with 0 representing off), e.g. using the following::
7070  *
7071  *   # echo 3 > /sys/class/drm/card0-eDP-1/amdgpu/panel_power_savings
7072  *
7073  * Modifying this value can have implications on color accuracy, so tread
7074  * carefully.
7075  */
7076 
panel_power_savings_show(struct device * device,struct device_attribute * attr,char * buf)7077 static ssize_t panel_power_savings_show(struct device *device,
7078 					struct device_attribute *attr,
7079 					char *buf)
7080 {
7081 	struct drm_connector *connector = dev_get_drvdata(device);
7082 	struct drm_device *dev = connector->dev;
7083 	u8 val;
7084 
7085 	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
7086 	val = to_dm_connector_state(connector->state)->abm_level ==
7087 		ABM_LEVEL_IMMEDIATE_DISABLE ? 0 :
7088 		to_dm_connector_state(connector->state)->abm_level;
7089 	drm_modeset_unlock(&dev->mode_config.connection_mutex);
7090 
7091 	return sysfs_emit(buf, "%u\n", val);
7092 }
7093 
panel_power_savings_store(struct device * device,struct device_attribute * attr,const char * buf,size_t count)7094 static ssize_t panel_power_savings_store(struct device *device,
7095 					 struct device_attribute *attr,
7096 					 const char *buf, size_t count)
7097 {
7098 	struct drm_connector *connector = dev_get_drvdata(device);
7099 	struct drm_device *dev = connector->dev;
7100 	long val;
7101 	int ret;
7102 
7103 	ret = kstrtol(buf, 0, &val);
7104 
7105 	if (ret)
7106 		return ret;
7107 
7108 	if (val < 0 || val > 4)
7109 		return -EINVAL;
7110 
7111 	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
7112 	to_dm_connector_state(connector->state)->abm_level = val ?:
7113 		ABM_LEVEL_IMMEDIATE_DISABLE;
7114 	drm_modeset_unlock(&dev->mode_config.connection_mutex);
7115 
7116 	drm_kms_helper_hotplug_event(dev);
7117 
7118 	return count;
7119 }
7120 
7121 static DEVICE_ATTR_RW(panel_power_savings);
7122 
7123 static struct attribute *amdgpu_attrs[] = {
7124 	&dev_attr_panel_power_savings.attr,
7125 	NULL
7126 };
7127 
7128 static const struct attribute_group amdgpu_group = {
7129 	.name = "amdgpu",
7130 	.attrs = amdgpu_attrs
7131 };
7132 
7133 static bool
amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector * amdgpu_dm_connector)7134 amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector)
7135 {
7136 	if (amdgpu_dm_abm_level >= 0)
7137 		return false;
7138 
7139 	if (amdgpu_dm_connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
7140 		return false;
7141 
7142 	/* check for OLED panels */
7143 	if (amdgpu_dm_connector->bl_idx >= 0) {
7144 		struct drm_device *drm = amdgpu_dm_connector->base.dev;
7145 		struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
7146 		struct amdgpu_dm_backlight_caps *caps;
7147 
7148 		caps = &dm->backlight_caps[amdgpu_dm_connector->bl_idx];
7149 		if (caps->aux_support)
7150 			return false;
7151 	}
7152 
7153 	return true;
7154 }
7155 
amdgpu_dm_connector_unregister(struct drm_connector * connector)7156 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
7157 {
7158 	struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
7159 
7160 	if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector))
7161 		sysfs_remove_group(&connector->kdev->kobj, &amdgpu_group);
7162 
7163 	cec_notifier_conn_unregister(amdgpu_dm_connector->notifier);
7164 	drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
7165 }
7166 
amdgpu_dm_connector_destroy(struct drm_connector * connector)7167 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
7168 {
7169 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7170 	struct amdgpu_device *adev = drm_to_adev(connector->dev);
7171 	struct amdgpu_display_manager *dm = &adev->dm;
7172 
7173 	/*
7174 	 * Call only if mst_mgr was initialized before since it's not done
7175 	 * for all connector types.
7176 	 */
7177 	if (aconnector->mst_mgr.dev)
7178 		drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
7179 
7180 	if (aconnector->bl_idx != -1) {
7181 		backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
7182 		dm->backlight_dev[aconnector->bl_idx] = NULL;
7183 	}
7184 
7185 	if (aconnector->dc_em_sink)
7186 		dc_sink_release(aconnector->dc_em_sink);
7187 	aconnector->dc_em_sink = NULL;
7188 	if (aconnector->dc_sink)
7189 		dc_sink_release(aconnector->dc_sink);
7190 	aconnector->dc_sink = NULL;
7191 
7192 	drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
7193 	drm_connector_unregister(connector);
7194 	drm_connector_cleanup(connector);
7195 	if (aconnector->i2c) {
7196 		i2c_del_adapter(&aconnector->i2c->base);
7197 		kfree(aconnector->i2c);
7198 	}
7199 	kfree(aconnector->dm_dp_aux.aux.name);
7200 
7201 	kfree(connector);
7202 }
7203 
amdgpu_dm_connector_funcs_reset(struct drm_connector * connector)7204 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
7205 {
7206 	struct dm_connector_state *state =
7207 		to_dm_connector_state(connector->state);
7208 
7209 	if (connector->state)
7210 		__drm_atomic_helper_connector_destroy_state(connector->state);
7211 
7212 	kfree(state);
7213 
7214 	state = kzalloc(sizeof(*state), GFP_KERNEL);
7215 
7216 	if (state) {
7217 		state->scaling = RMX_OFF;
7218 		state->underscan_enable = false;
7219 		state->underscan_hborder = 0;
7220 		state->underscan_vborder = 0;
7221 		state->base.max_requested_bpc = 8;
7222 		state->vcpi_slots = 0;
7223 		state->pbn = 0;
7224 
7225 		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
7226 			if (amdgpu_dm_abm_level <= 0)
7227 				state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE;
7228 			else
7229 				state->abm_level = amdgpu_dm_abm_level;
7230 		}
7231 
7232 		__drm_atomic_helper_connector_reset(connector, &state->base);
7233 	}
7234 }
7235 
7236 struct drm_connector_state *
amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector * connector)7237 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
7238 {
7239 	struct dm_connector_state *state =
7240 		to_dm_connector_state(connector->state);
7241 
7242 	struct dm_connector_state *new_state =
7243 			kmemdup(state, sizeof(*state), GFP_KERNEL);
7244 
7245 	if (!new_state)
7246 		return NULL;
7247 
7248 	__drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
7249 
7250 	new_state->freesync_capable = state->freesync_capable;
7251 	new_state->abm_level = state->abm_level;
7252 	new_state->scaling = state->scaling;
7253 	new_state->underscan_enable = state->underscan_enable;
7254 	new_state->underscan_hborder = state->underscan_hborder;
7255 	new_state->underscan_vborder = state->underscan_vborder;
7256 	new_state->vcpi_slots = state->vcpi_slots;
7257 	new_state->pbn = state->pbn;
7258 	return &new_state->base;
7259 }
7260 
7261 static int
amdgpu_dm_connector_late_register(struct drm_connector * connector)7262 amdgpu_dm_connector_late_register(struct drm_connector *connector)
7263 {
7264 	struct amdgpu_dm_connector *amdgpu_dm_connector =
7265 		to_amdgpu_dm_connector(connector);
7266 	int r;
7267 
7268 	if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) {
7269 		r = sysfs_create_group(&connector->kdev->kobj,
7270 				       &amdgpu_group);
7271 		if (r)
7272 			return r;
7273 	}
7274 
7275 	amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
7276 
7277 	if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
7278 	    (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
7279 		amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
7280 		r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
7281 		if (r)
7282 			return r;
7283 	}
7284 
7285 #if defined(CONFIG_DEBUG_FS)
7286 	connector_debugfs_init(amdgpu_dm_connector);
7287 #endif
7288 
7289 	return 0;
7290 }
7291 
amdgpu_dm_connector_funcs_force(struct drm_connector * connector)7292 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
7293 {
7294 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7295 	struct dc_link *dc_link = aconnector->dc_link;
7296 	struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
7297 	const struct drm_edid *drm_edid;
7298 	struct i2c_adapter *ddc;
7299 
7300 	if (dc_link && dc_link->aux_mode)
7301 		ddc = &aconnector->dm_dp_aux.aux.ddc;
7302 	else
7303 		ddc = &aconnector->i2c->base;
7304 
7305 	drm_edid = drm_edid_read_ddc(connector, ddc);
7306 	drm_edid_connector_update(connector, drm_edid);
7307 	if (!drm_edid) {
7308 		DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
7309 		return;
7310 	}
7311 
7312 	aconnector->drm_edid = drm_edid;
7313 	/* Update emulated (virtual) sink's EDID */
7314 	if (dc_em_sink && dc_link) {
7315 		// FIXME: Get rid of drm_edid_raw()
7316 		const struct edid *edid = drm_edid_raw(drm_edid);
7317 
7318 		memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
7319 		memmove(dc_em_sink->dc_edid.raw_edid, edid,
7320 			(edid->extensions + 1) * EDID_LENGTH);
7321 		dm_helpers_parse_edid_caps(
7322 			dc_link,
7323 			&dc_em_sink->dc_edid,
7324 			&dc_em_sink->edid_caps);
7325 	}
7326 }
7327 
7328 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
7329 	.reset = amdgpu_dm_connector_funcs_reset,
7330 	.detect = amdgpu_dm_connector_detect,
7331 	.fill_modes = drm_helper_probe_single_connector_modes,
7332 	.destroy = amdgpu_dm_connector_destroy,
7333 	.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
7334 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
7335 	.atomic_set_property = amdgpu_dm_connector_atomic_set_property,
7336 	.atomic_get_property = amdgpu_dm_connector_atomic_get_property,
7337 	.late_register = amdgpu_dm_connector_late_register,
7338 	.early_unregister = amdgpu_dm_connector_unregister,
7339 	.force = amdgpu_dm_connector_funcs_force
7340 };
7341 
get_modes(struct drm_connector * connector)7342 static int get_modes(struct drm_connector *connector)
7343 {
7344 	return amdgpu_dm_connector_get_modes(connector);
7345 }
7346 
create_eml_sink(struct amdgpu_dm_connector * aconnector)7347 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
7348 {
7349 	struct drm_connector *connector = &aconnector->base;
7350 	struct dc_link *dc_link = aconnector->dc_link;
7351 	struct dc_sink_init_data init_params = {
7352 			.link = aconnector->dc_link,
7353 			.sink_signal = SIGNAL_TYPE_VIRTUAL
7354 	};
7355 	const struct drm_edid *drm_edid;
7356 	const struct edid *edid;
7357 	struct i2c_adapter *ddc;
7358 
7359 	if (dc_link && dc_link->aux_mode)
7360 		ddc = &aconnector->dm_dp_aux.aux.ddc;
7361 	else
7362 		ddc = &aconnector->i2c->base;
7363 
7364 	drm_edid = drm_edid_read_ddc(connector, ddc);
7365 	drm_edid_connector_update(connector, drm_edid);
7366 	if (!drm_edid) {
7367 		DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
7368 		return;
7369 	}
7370 
7371 	if (connector->display_info.is_hdmi)
7372 		init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
7373 
7374 	aconnector->drm_edid = drm_edid;
7375 
7376 	edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()
7377 	aconnector->dc_em_sink = dc_link_add_remote_sink(
7378 		aconnector->dc_link,
7379 		(uint8_t *)edid,
7380 		(edid->extensions + 1) * EDID_LENGTH,
7381 		&init_params);
7382 
7383 	if (aconnector->base.force == DRM_FORCE_ON) {
7384 		aconnector->dc_sink = aconnector->dc_link->local_sink ?
7385 		aconnector->dc_link->local_sink :
7386 		aconnector->dc_em_sink;
7387 		if (aconnector->dc_sink)
7388 			dc_sink_retain(aconnector->dc_sink);
7389 	}
7390 }
7391 
handle_edid_mgmt(struct amdgpu_dm_connector * aconnector)7392 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
7393 {
7394 	struct dc_link *link = (struct dc_link *)aconnector->dc_link;
7395 
7396 	/*
7397 	 * In case of headless boot with force on for DP managed connector
7398 	 * Those settings have to be != 0 to get initial modeset
7399 	 */
7400 	if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
7401 		link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
7402 		link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
7403 	}
7404 
7405 	create_eml_sink(aconnector);
7406 }
7407 
dm_validate_stream_and_context(struct dc * dc,struct dc_stream_state * stream)7408 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
7409 						struct dc_stream_state *stream)
7410 {
7411 	enum dc_status dc_result = DC_ERROR_UNEXPECTED;
7412 	struct dc_plane_state *dc_plane_state = NULL;
7413 	struct dc_state *dc_state = NULL;
7414 
7415 	if (!stream)
7416 		goto cleanup;
7417 
7418 	dc_plane_state = dc_create_plane_state(dc);
7419 	if (!dc_plane_state)
7420 		goto cleanup;
7421 
7422 	dc_state = dc_state_create(dc, NULL);
7423 	if (!dc_state)
7424 		goto cleanup;
7425 
7426 	/* populate stream to plane */
7427 	dc_plane_state->src_rect.height  = stream->src.height;
7428 	dc_plane_state->src_rect.width   = stream->src.width;
7429 	dc_plane_state->dst_rect.height  = stream->src.height;
7430 	dc_plane_state->dst_rect.width   = stream->src.width;
7431 	dc_plane_state->clip_rect.height = stream->src.height;
7432 	dc_plane_state->clip_rect.width  = stream->src.width;
7433 	dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
7434 	dc_plane_state->plane_size.surface_size.height = stream->src.height;
7435 	dc_plane_state->plane_size.surface_size.width  = stream->src.width;
7436 	dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
7437 	dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
7438 	dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
7439 	dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
7440 	dc_plane_state->rotation = ROTATION_ANGLE_0;
7441 	dc_plane_state->is_tiling_rotated = false;
7442 	dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
7443 
7444 	dc_result = dc_validate_stream(dc, stream);
7445 	if (dc_result == DC_OK)
7446 		dc_result = dc_validate_plane(dc, dc_plane_state);
7447 
7448 	if (dc_result == DC_OK)
7449 		dc_result = dc_state_add_stream(dc, dc_state, stream);
7450 
7451 	if (dc_result == DC_OK && !dc_state_add_plane(
7452 						dc,
7453 						stream,
7454 						dc_plane_state,
7455 						dc_state))
7456 		dc_result = DC_FAIL_ATTACH_SURFACES;
7457 
7458 	if (dc_result == DC_OK)
7459 		dc_result = dc_validate_global_state(dc, dc_state, true);
7460 
7461 cleanup:
7462 	if (dc_state)
7463 		dc_state_release(dc_state);
7464 
7465 	if (dc_plane_state)
7466 		dc_plane_state_release(dc_plane_state);
7467 
7468 	return dc_result;
7469 }
7470 
7471 struct dc_stream_state *
create_validate_stream_for_sink(struct amdgpu_dm_connector * aconnector,const struct drm_display_mode * drm_mode,const struct dm_connector_state * dm_state,const struct dc_stream_state * old_stream)7472 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
7473 				const struct drm_display_mode *drm_mode,
7474 				const struct dm_connector_state *dm_state,
7475 				const struct dc_stream_state *old_stream)
7476 {
7477 	struct drm_connector *connector = &aconnector->base;
7478 	struct amdgpu_device *adev = drm_to_adev(connector->dev);
7479 	struct dc_stream_state *stream;
7480 	const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
7481 	int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
7482 	enum dc_status dc_result = DC_OK;
7483 	uint8_t bpc_limit = 6;
7484 
7485 	if (!dm_state)
7486 		return NULL;
7487 
7488 	if (aconnector->dc_link->connector_signal == SIGNAL_TYPE_HDMI_TYPE_A ||
7489 	    aconnector->dc_link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
7490 		bpc_limit = 8;
7491 
7492 	do {
7493 		stream = create_stream_for_sink(connector, drm_mode,
7494 						dm_state, old_stream,
7495 						requested_bpc);
7496 		if (stream == NULL) {
7497 			DRM_ERROR("Failed to create stream for sink!\n");
7498 			break;
7499 		}
7500 
7501 		if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
7502 			return stream;
7503 
7504 		dc_result = dc_validate_stream(adev->dm.dc, stream);
7505 		if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
7506 			dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
7507 
7508 		if (dc_result == DC_OK)
7509 			dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
7510 
7511 		if (dc_result != DC_OK) {
7512 			DRM_DEBUG_KMS("Mode %dx%d (clk %d) pixel_encoding:%s color_depth:%s failed validation -- %s\n",
7513 				      drm_mode->hdisplay,
7514 				      drm_mode->vdisplay,
7515 				      drm_mode->clock,
7516 				      dc_pixel_encoding_to_str(stream->timing.pixel_encoding),
7517 				      dc_color_depth_to_str(stream->timing.display_color_depth),
7518 				      dc_status_to_str(dc_result));
7519 
7520 			dc_stream_release(stream);
7521 			stream = NULL;
7522 			requested_bpc -= 2; /* lower bpc to retry validation */
7523 		}
7524 
7525 	} while (stream == NULL && requested_bpc >= bpc_limit);
7526 
7527 	if ((dc_result == DC_FAIL_ENC_VALIDATE ||
7528 	     dc_result == DC_EXCEED_DONGLE_CAP) &&
7529 	     !aconnector->force_yuv420_output) {
7530 		DRM_DEBUG_KMS("%s:%d Retry forcing yuv420 encoding\n",
7531 				     __func__, __LINE__);
7532 
7533 		aconnector->force_yuv420_output = true;
7534 		stream = create_validate_stream_for_sink(aconnector, drm_mode,
7535 						dm_state, old_stream);
7536 		aconnector->force_yuv420_output = false;
7537 	}
7538 
7539 	return stream;
7540 }
7541 
amdgpu_dm_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)7542 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
7543 				   struct drm_display_mode *mode)
7544 {
7545 	int result = MODE_ERROR;
7546 	struct dc_sink *dc_sink;
7547 	/* TODO: Unhardcode stream count */
7548 	struct dc_stream_state *stream;
7549 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7550 
7551 	if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
7552 			(mode->flags & DRM_MODE_FLAG_DBLSCAN))
7553 		return result;
7554 
7555 	/*
7556 	 * Only run this the first time mode_valid is called to initilialize
7557 	 * EDID mgmt
7558 	 */
7559 	if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
7560 		!aconnector->dc_em_sink)
7561 		handle_edid_mgmt(aconnector);
7562 
7563 	dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
7564 
7565 	if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
7566 				aconnector->base.force != DRM_FORCE_ON) {
7567 		DRM_ERROR("dc_sink is NULL!\n");
7568 		goto fail;
7569 	}
7570 
7571 	drm_mode_set_crtcinfo(mode, 0);
7572 
7573 	stream = create_validate_stream_for_sink(aconnector, mode,
7574 						 to_dm_connector_state(connector->state),
7575 						 NULL);
7576 	if (stream) {
7577 		dc_stream_release(stream);
7578 		result = MODE_OK;
7579 	}
7580 
7581 fail:
7582 	/* TODO: error handling*/
7583 	return result;
7584 }
7585 
fill_hdr_info_packet(const struct drm_connector_state * state,struct dc_info_packet * out)7586 static int fill_hdr_info_packet(const struct drm_connector_state *state,
7587 				struct dc_info_packet *out)
7588 {
7589 	struct hdmi_drm_infoframe frame;
7590 	unsigned char buf[30]; /* 26 + 4 */
7591 	ssize_t len;
7592 	int ret, i;
7593 
7594 	memset(out, 0, sizeof(*out));
7595 
7596 	if (!state->hdr_output_metadata)
7597 		return 0;
7598 
7599 	ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
7600 	if (ret)
7601 		return ret;
7602 
7603 	len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
7604 	if (len < 0)
7605 		return (int)len;
7606 
7607 	/* Static metadata is a fixed 26 bytes + 4 byte header. */
7608 	if (len != 30)
7609 		return -EINVAL;
7610 
7611 	/* Prepare the infopacket for DC. */
7612 	switch (state->connector->connector_type) {
7613 	case DRM_MODE_CONNECTOR_HDMIA:
7614 		out->hb0 = 0x87; /* type */
7615 		out->hb1 = 0x01; /* version */
7616 		out->hb2 = 0x1A; /* length */
7617 		out->sb[0] = buf[3]; /* checksum */
7618 		i = 1;
7619 		break;
7620 
7621 	case DRM_MODE_CONNECTOR_DisplayPort:
7622 	case DRM_MODE_CONNECTOR_eDP:
7623 		out->hb0 = 0x00; /* sdp id, zero */
7624 		out->hb1 = 0x87; /* type */
7625 		out->hb2 = 0x1D; /* payload len - 1 */
7626 		out->hb3 = (0x13 << 2); /* sdp version */
7627 		out->sb[0] = 0x01; /* version */
7628 		out->sb[1] = 0x1A; /* length */
7629 		i = 2;
7630 		break;
7631 
7632 	default:
7633 		return -EINVAL;
7634 	}
7635 
7636 	memcpy(&out->sb[i], &buf[4], 26);
7637 	out->valid = true;
7638 
7639 	print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
7640 		       sizeof(out->sb), false);
7641 
7642 	return 0;
7643 }
7644 
7645 static int
amdgpu_dm_connector_atomic_check(struct drm_connector * conn,struct drm_atomic_state * state)7646 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
7647 				 struct drm_atomic_state *state)
7648 {
7649 	struct drm_connector_state *new_con_state =
7650 		drm_atomic_get_new_connector_state(state, conn);
7651 	struct drm_connector_state *old_con_state =
7652 		drm_atomic_get_old_connector_state(state, conn);
7653 	struct drm_crtc *crtc = new_con_state->crtc;
7654 	struct drm_crtc_state *new_crtc_state;
7655 	struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
7656 	int ret;
7657 
7658 	trace_amdgpu_dm_connector_atomic_check(new_con_state);
7659 
7660 	if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
7661 		ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
7662 		if (ret < 0)
7663 			return ret;
7664 	}
7665 
7666 	if (!crtc)
7667 		return 0;
7668 
7669 	if (new_con_state->colorspace != old_con_state->colorspace) {
7670 		new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
7671 		if (IS_ERR(new_crtc_state))
7672 			return PTR_ERR(new_crtc_state);
7673 
7674 		new_crtc_state->mode_changed = true;
7675 	}
7676 
7677 	if (new_con_state->content_type != old_con_state->content_type) {
7678 		new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
7679 		if (IS_ERR(new_crtc_state))
7680 			return PTR_ERR(new_crtc_state);
7681 
7682 		new_crtc_state->mode_changed = true;
7683 	}
7684 
7685 	if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
7686 		struct dc_info_packet hdr_infopacket;
7687 
7688 		ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
7689 		if (ret)
7690 			return ret;
7691 
7692 		new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
7693 		if (IS_ERR(new_crtc_state))
7694 			return PTR_ERR(new_crtc_state);
7695 
7696 		/*
7697 		 * DC considers the stream backends changed if the
7698 		 * static metadata changes. Forcing the modeset also
7699 		 * gives a simple way for userspace to switch from
7700 		 * 8bpc to 10bpc when setting the metadata to enter
7701 		 * or exit HDR.
7702 		 *
7703 		 * Changing the static metadata after it's been
7704 		 * set is permissible, however. So only force a
7705 		 * modeset if we're entering or exiting HDR.
7706 		 */
7707 		new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
7708 			!old_con_state->hdr_output_metadata ||
7709 			!new_con_state->hdr_output_metadata;
7710 	}
7711 
7712 	return 0;
7713 }
7714 
7715 static const struct drm_connector_helper_funcs
7716 amdgpu_dm_connector_helper_funcs = {
7717 	/*
7718 	 * If hotplugging a second bigger display in FB Con mode, bigger resolution
7719 	 * modes will be filtered by drm_mode_validate_size(), and those modes
7720 	 * are missing after user start lightdm. So we need to renew modes list.
7721 	 * in get_modes call back, not just return the modes count
7722 	 */
7723 	.get_modes = get_modes,
7724 	.mode_valid = amdgpu_dm_connector_mode_valid,
7725 	.atomic_check = amdgpu_dm_connector_atomic_check,
7726 };
7727 
dm_encoder_helper_disable(struct drm_encoder * encoder)7728 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
7729 {
7730 
7731 }
7732 
convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)7733 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
7734 {
7735 	switch (display_color_depth) {
7736 	case COLOR_DEPTH_666:
7737 		return 6;
7738 	case COLOR_DEPTH_888:
7739 		return 8;
7740 	case COLOR_DEPTH_101010:
7741 		return 10;
7742 	case COLOR_DEPTH_121212:
7743 		return 12;
7744 	case COLOR_DEPTH_141414:
7745 		return 14;
7746 	case COLOR_DEPTH_161616:
7747 		return 16;
7748 	default:
7749 		break;
7750 	}
7751 	return 0;
7752 }
7753 
dm_encoder_helper_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)7754 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
7755 					  struct drm_crtc_state *crtc_state,
7756 					  struct drm_connector_state *conn_state)
7757 {
7758 	struct drm_atomic_state *state = crtc_state->state;
7759 	struct drm_connector *connector = conn_state->connector;
7760 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7761 	struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
7762 	const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
7763 	struct drm_dp_mst_topology_mgr *mst_mgr;
7764 	struct drm_dp_mst_port *mst_port;
7765 	struct drm_dp_mst_topology_state *mst_state;
7766 	enum dc_color_depth color_depth;
7767 	int clock, bpp = 0;
7768 	bool is_y420 = false;
7769 
7770 	if (!aconnector->mst_output_port)
7771 		return 0;
7772 
7773 	mst_port = aconnector->mst_output_port;
7774 	mst_mgr = &aconnector->mst_root->mst_mgr;
7775 
7776 	if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
7777 		return 0;
7778 
7779 	mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
7780 	if (IS_ERR(mst_state))
7781 		return PTR_ERR(mst_state);
7782 
7783 	mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link));
7784 
7785 	if (!state->duplicated) {
7786 		int max_bpc = conn_state->max_requested_bpc;
7787 
7788 		is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
7789 			  aconnector->force_yuv420_output;
7790 		color_depth = convert_color_depth_from_display_info(connector,
7791 								    is_y420,
7792 								    max_bpc);
7793 		bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
7794 		clock = adjusted_mode->clock;
7795 		dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);
7796 	}
7797 
7798 	dm_new_connector_state->vcpi_slots =
7799 		drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
7800 					      dm_new_connector_state->pbn);
7801 	if (dm_new_connector_state->vcpi_slots < 0) {
7802 		DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
7803 		return dm_new_connector_state->vcpi_slots;
7804 	}
7805 	return 0;
7806 }
7807 
7808 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
7809 	.disable = dm_encoder_helper_disable,
7810 	.atomic_check = dm_encoder_helper_atomic_check
7811 };
7812 
dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state * state,struct dc_state * dc_state,struct dsc_mst_fairness_vars * vars)7813 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
7814 					    struct dc_state *dc_state,
7815 					    struct dsc_mst_fairness_vars *vars)
7816 {
7817 	struct dc_stream_state *stream = NULL;
7818 	struct drm_connector *connector;
7819 	struct drm_connector_state *new_con_state;
7820 	struct amdgpu_dm_connector *aconnector;
7821 	struct dm_connector_state *dm_conn_state;
7822 	int i, j, ret;
7823 	int vcpi, pbn_div, pbn = 0, slot_num = 0;
7824 
7825 	for_each_new_connector_in_state(state, connector, new_con_state, i) {
7826 
7827 		if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
7828 			continue;
7829 
7830 		aconnector = to_amdgpu_dm_connector(connector);
7831 
7832 		if (!aconnector->mst_output_port)
7833 			continue;
7834 
7835 		if (!new_con_state || !new_con_state->crtc)
7836 			continue;
7837 
7838 		dm_conn_state = to_dm_connector_state(new_con_state);
7839 
7840 		for (j = 0; j < dc_state->stream_count; j++) {
7841 			stream = dc_state->streams[j];
7842 			if (!stream)
7843 				continue;
7844 
7845 			if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
7846 				break;
7847 
7848 			stream = NULL;
7849 		}
7850 
7851 		if (!stream)
7852 			continue;
7853 
7854 		pbn_div = dm_mst_get_pbn_divider(stream->link);
7855 		/* pbn is calculated by compute_mst_dsc_configs_for_state*/
7856 		for (j = 0; j < dc_state->stream_count; j++) {
7857 			if (vars[j].aconnector == aconnector) {
7858 				pbn = vars[j].pbn;
7859 				break;
7860 			}
7861 		}
7862 
7863 		if (j == dc_state->stream_count || pbn_div == 0)
7864 			continue;
7865 
7866 		slot_num = DIV_ROUND_UP(pbn, pbn_div);
7867 
7868 		if (stream->timing.flags.DSC != 1) {
7869 			dm_conn_state->pbn = pbn;
7870 			dm_conn_state->vcpi_slots = slot_num;
7871 
7872 			ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
7873 							   dm_conn_state->pbn, false);
7874 			if (ret < 0)
7875 				return ret;
7876 
7877 			continue;
7878 		}
7879 
7880 		vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
7881 		if (vcpi < 0)
7882 			return vcpi;
7883 
7884 		dm_conn_state->pbn = pbn;
7885 		dm_conn_state->vcpi_slots = vcpi;
7886 	}
7887 	return 0;
7888 }
7889 
to_drm_connector_type(enum signal_type st)7890 static int to_drm_connector_type(enum signal_type st)
7891 {
7892 	switch (st) {
7893 	case SIGNAL_TYPE_HDMI_TYPE_A:
7894 		return DRM_MODE_CONNECTOR_HDMIA;
7895 	case SIGNAL_TYPE_EDP:
7896 		return DRM_MODE_CONNECTOR_eDP;
7897 	case SIGNAL_TYPE_LVDS:
7898 		return DRM_MODE_CONNECTOR_LVDS;
7899 	case SIGNAL_TYPE_RGB:
7900 		return DRM_MODE_CONNECTOR_VGA;
7901 	case SIGNAL_TYPE_DISPLAY_PORT:
7902 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
7903 		return DRM_MODE_CONNECTOR_DisplayPort;
7904 	case SIGNAL_TYPE_DVI_DUAL_LINK:
7905 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
7906 		return DRM_MODE_CONNECTOR_DVID;
7907 	case SIGNAL_TYPE_VIRTUAL:
7908 		return DRM_MODE_CONNECTOR_VIRTUAL;
7909 
7910 	default:
7911 		return DRM_MODE_CONNECTOR_Unknown;
7912 	}
7913 }
7914 
amdgpu_dm_connector_to_encoder(struct drm_connector * connector)7915 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
7916 {
7917 	struct drm_encoder *encoder;
7918 
7919 	/* There is only one encoder per connector */
7920 	drm_connector_for_each_possible_encoder(connector, encoder)
7921 		return encoder;
7922 
7923 	return NULL;
7924 }
7925 
amdgpu_dm_get_native_mode(struct drm_connector * connector)7926 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
7927 {
7928 	struct drm_encoder *encoder;
7929 	struct amdgpu_encoder *amdgpu_encoder;
7930 
7931 	encoder = amdgpu_dm_connector_to_encoder(connector);
7932 
7933 	if (encoder == NULL)
7934 		return;
7935 
7936 	amdgpu_encoder = to_amdgpu_encoder(encoder);
7937 
7938 	amdgpu_encoder->native_mode.clock = 0;
7939 
7940 	if (!list_empty(&connector->probed_modes)) {
7941 		struct drm_display_mode *preferred_mode = NULL;
7942 
7943 		list_for_each_entry(preferred_mode,
7944 				    &connector->probed_modes,
7945 				    head) {
7946 			if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
7947 				amdgpu_encoder->native_mode = *preferred_mode;
7948 
7949 			break;
7950 		}
7951 
7952 	}
7953 }
7954 
7955 static struct drm_display_mode *
amdgpu_dm_create_common_mode(struct drm_encoder * encoder,char * name,int hdisplay,int vdisplay)7956 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
7957 			     char *name,
7958 			     int hdisplay, int vdisplay)
7959 {
7960 	struct drm_device *dev = encoder->dev;
7961 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7962 	struct drm_display_mode *mode = NULL;
7963 	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7964 
7965 	mode = drm_mode_duplicate(dev, native_mode);
7966 
7967 	if (mode == NULL)
7968 		return NULL;
7969 
7970 	mode->hdisplay = hdisplay;
7971 	mode->vdisplay = vdisplay;
7972 	mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7973 	strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7974 
7975 	return mode;
7976 
7977 }
7978 
amdgpu_dm_connector_add_common_modes(struct drm_encoder * encoder,struct drm_connector * connector)7979 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7980 						 struct drm_connector *connector)
7981 {
7982 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7983 	struct drm_display_mode *mode = NULL;
7984 	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7985 	struct amdgpu_dm_connector *amdgpu_dm_connector =
7986 				to_amdgpu_dm_connector(connector);
7987 	int i;
7988 	int n;
7989 	struct mode_size {
7990 		char name[DRM_DISPLAY_MODE_LEN];
7991 		int w;
7992 		int h;
7993 	} common_modes[] = {
7994 		{  "640x480",  640,  480},
7995 		{  "800x600",  800,  600},
7996 		{ "1024x768", 1024,  768},
7997 		{ "1280x720", 1280,  720},
7998 		{ "1280x800", 1280,  800},
7999 		{"1280x1024", 1280, 1024},
8000 		{ "1440x900", 1440,  900},
8001 		{"1680x1050", 1680, 1050},
8002 		{"1600x1200", 1600, 1200},
8003 		{"1920x1080", 1920, 1080},
8004 		{"1920x1200", 1920, 1200}
8005 	};
8006 
8007 	n = ARRAY_SIZE(common_modes);
8008 
8009 	for (i = 0; i < n; i++) {
8010 		struct drm_display_mode *curmode = NULL;
8011 		bool mode_existed = false;
8012 
8013 		if (common_modes[i].w > native_mode->hdisplay ||
8014 		    common_modes[i].h > native_mode->vdisplay ||
8015 		   (common_modes[i].w == native_mode->hdisplay &&
8016 		    common_modes[i].h == native_mode->vdisplay))
8017 			continue;
8018 
8019 		list_for_each_entry(curmode, &connector->probed_modes, head) {
8020 			if (common_modes[i].w == curmode->hdisplay &&
8021 			    common_modes[i].h == curmode->vdisplay) {
8022 				mode_existed = true;
8023 				break;
8024 			}
8025 		}
8026 
8027 		if (mode_existed)
8028 			continue;
8029 
8030 		mode = amdgpu_dm_create_common_mode(encoder,
8031 				common_modes[i].name, common_modes[i].w,
8032 				common_modes[i].h);
8033 		if (!mode)
8034 			continue;
8035 
8036 		drm_mode_probed_add(connector, mode);
8037 		amdgpu_dm_connector->num_modes++;
8038 	}
8039 }
8040 
amdgpu_set_panel_orientation(struct drm_connector * connector)8041 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
8042 {
8043 	struct drm_encoder *encoder;
8044 	struct amdgpu_encoder *amdgpu_encoder;
8045 	const struct drm_display_mode *native_mode;
8046 
8047 	if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
8048 	    connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
8049 		return;
8050 
8051 	mutex_lock(&connector->dev->mode_config.mutex);
8052 	amdgpu_dm_connector_get_modes(connector);
8053 	mutex_unlock(&connector->dev->mode_config.mutex);
8054 
8055 	encoder = amdgpu_dm_connector_to_encoder(connector);
8056 	if (!encoder)
8057 		return;
8058 
8059 	amdgpu_encoder = to_amdgpu_encoder(encoder);
8060 
8061 	native_mode = &amdgpu_encoder->native_mode;
8062 	if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
8063 		return;
8064 
8065 	drm_connector_set_panel_orientation_with_quirk(connector,
8066 						       DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
8067 						       native_mode->hdisplay,
8068 						       native_mode->vdisplay);
8069 }
8070 
amdgpu_dm_connector_ddc_get_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)8071 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
8072 					      const struct drm_edid *drm_edid)
8073 {
8074 	struct amdgpu_dm_connector *amdgpu_dm_connector =
8075 			to_amdgpu_dm_connector(connector);
8076 
8077 	if (drm_edid) {
8078 		/* empty probed_modes */
8079 		INIT_LIST_HEAD(&connector->probed_modes);
8080 		amdgpu_dm_connector->num_modes =
8081 				drm_edid_connector_add_modes(connector);
8082 
8083 		/* sorting the probed modes before calling function
8084 		 * amdgpu_dm_get_native_mode() since EDID can have
8085 		 * more than one preferred mode. The modes that are
8086 		 * later in the probed mode list could be of higher
8087 		 * and preferred resolution. For example, 3840x2160
8088 		 * resolution in base EDID preferred timing and 4096x2160
8089 		 * preferred resolution in DID extension block later.
8090 		 */
8091 		drm_mode_sort(&connector->probed_modes);
8092 		amdgpu_dm_get_native_mode(connector);
8093 
8094 		/* Freesync capabilities are reset by calling
8095 		 * drm_edid_connector_add_modes() and need to be
8096 		 * restored here.
8097 		 */
8098 		amdgpu_dm_update_freesync_caps(connector, drm_edid);
8099 	} else {
8100 		amdgpu_dm_connector->num_modes = 0;
8101 	}
8102 }
8103 
is_duplicate_mode(struct amdgpu_dm_connector * aconnector,struct drm_display_mode * mode)8104 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
8105 			      struct drm_display_mode *mode)
8106 {
8107 	struct drm_display_mode *m;
8108 
8109 	list_for_each_entry(m, &aconnector->base.probed_modes, head) {
8110 		if (drm_mode_equal(m, mode))
8111 			return true;
8112 	}
8113 
8114 	return false;
8115 }
8116 
add_fs_modes(struct amdgpu_dm_connector * aconnector)8117 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
8118 {
8119 	const struct drm_display_mode *m;
8120 	struct drm_display_mode *new_mode;
8121 	uint i;
8122 	u32 new_modes_count = 0;
8123 
8124 	/* Standard FPS values
8125 	 *
8126 	 * 23.976       - TV/NTSC
8127 	 * 24           - Cinema
8128 	 * 25           - TV/PAL
8129 	 * 29.97        - TV/NTSC
8130 	 * 30           - TV/NTSC
8131 	 * 48           - Cinema HFR
8132 	 * 50           - TV/PAL
8133 	 * 60           - Commonly used
8134 	 * 48,72,96,120 - Multiples of 24
8135 	 */
8136 	static const u32 common_rates[] = {
8137 		23976, 24000, 25000, 29970, 30000,
8138 		48000, 50000, 60000, 72000, 96000, 120000
8139 	};
8140 
8141 	/*
8142 	 * Find mode with highest refresh rate with the same resolution
8143 	 * as the preferred mode. Some monitors report a preferred mode
8144 	 * with lower resolution than the highest refresh rate supported.
8145 	 */
8146 
8147 	m = get_highest_refresh_rate_mode(aconnector, true);
8148 	if (!m)
8149 		return 0;
8150 
8151 	for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
8152 		u64 target_vtotal, target_vtotal_diff;
8153 		u64 num, den;
8154 
8155 		if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
8156 			continue;
8157 
8158 		if (common_rates[i] < aconnector->min_vfreq * 1000 ||
8159 		    common_rates[i] > aconnector->max_vfreq * 1000)
8160 			continue;
8161 
8162 		num = (unsigned long long)m->clock * 1000 * 1000;
8163 		den = common_rates[i] * (unsigned long long)m->htotal;
8164 		target_vtotal = div_u64(num, den);
8165 		target_vtotal_diff = target_vtotal - m->vtotal;
8166 
8167 		/* Check for illegal modes */
8168 		if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
8169 		    m->vsync_end + target_vtotal_diff < m->vsync_start ||
8170 		    m->vtotal + target_vtotal_diff < m->vsync_end)
8171 			continue;
8172 
8173 		new_mode = drm_mode_duplicate(aconnector->base.dev, m);
8174 		if (!new_mode)
8175 			goto out;
8176 
8177 		new_mode->vtotal += (u16)target_vtotal_diff;
8178 		new_mode->vsync_start += (u16)target_vtotal_diff;
8179 		new_mode->vsync_end += (u16)target_vtotal_diff;
8180 		new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
8181 		new_mode->type |= DRM_MODE_TYPE_DRIVER;
8182 
8183 		if (!is_duplicate_mode(aconnector, new_mode)) {
8184 			drm_mode_probed_add(&aconnector->base, new_mode);
8185 			new_modes_count += 1;
8186 		} else
8187 			drm_mode_destroy(aconnector->base.dev, new_mode);
8188 	}
8189  out:
8190 	return new_modes_count;
8191 }
8192 
amdgpu_dm_connector_add_freesync_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)8193 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
8194 						   const struct drm_edid *drm_edid)
8195 {
8196 	struct amdgpu_dm_connector *amdgpu_dm_connector =
8197 		to_amdgpu_dm_connector(connector);
8198 
8199 	if (!(amdgpu_freesync_vid_mode && drm_edid))
8200 		return;
8201 
8202 	if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
8203 		amdgpu_dm_connector->num_modes +=
8204 			add_fs_modes(amdgpu_dm_connector);
8205 }
8206 
amdgpu_dm_connector_get_modes(struct drm_connector * connector)8207 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
8208 {
8209 	struct amdgpu_dm_connector *amdgpu_dm_connector =
8210 			to_amdgpu_dm_connector(connector);
8211 	struct drm_encoder *encoder;
8212 	const struct drm_edid *drm_edid = amdgpu_dm_connector->drm_edid;
8213 	struct dc_link_settings *verified_link_cap =
8214 			&amdgpu_dm_connector->dc_link->verified_link_cap;
8215 	const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
8216 
8217 	encoder = amdgpu_dm_connector_to_encoder(connector);
8218 
8219 	if (!drm_edid) {
8220 		amdgpu_dm_connector->num_modes =
8221 				drm_add_modes_noedid(connector, 640, 480);
8222 		if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
8223 			amdgpu_dm_connector->num_modes +=
8224 				drm_add_modes_noedid(connector, 1920, 1080);
8225 	} else {
8226 		amdgpu_dm_connector_ddc_get_modes(connector, drm_edid);
8227 		if (encoder)
8228 			amdgpu_dm_connector_add_common_modes(encoder, connector);
8229 		amdgpu_dm_connector_add_freesync_modes(connector, drm_edid);
8230 	}
8231 	amdgpu_dm_fbc_init(connector);
8232 
8233 	return amdgpu_dm_connector->num_modes;
8234 }
8235 
8236 static const u32 supported_colorspaces =
8237 	BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
8238 	BIT(DRM_MODE_COLORIMETRY_OPRGB) |
8239 	BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
8240 	BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
8241 
amdgpu_dm_connector_init_helper(struct amdgpu_display_manager * dm,struct amdgpu_dm_connector * aconnector,int connector_type,struct dc_link * link,int link_index)8242 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
8243 				     struct amdgpu_dm_connector *aconnector,
8244 				     int connector_type,
8245 				     struct dc_link *link,
8246 				     int link_index)
8247 {
8248 	struct amdgpu_device *adev = drm_to_adev(dm->ddev);
8249 
8250 	/*
8251 	 * Some of the properties below require access to state, like bpc.
8252 	 * Allocate some default initial connector state with our reset helper.
8253 	 */
8254 	if (aconnector->base.funcs->reset)
8255 		aconnector->base.funcs->reset(&aconnector->base);
8256 
8257 	aconnector->connector_id = link_index;
8258 	aconnector->bl_idx = -1;
8259 	aconnector->dc_link = link;
8260 	aconnector->base.interlace_allowed = false;
8261 	aconnector->base.doublescan_allowed = false;
8262 	aconnector->base.stereo_allowed = false;
8263 	aconnector->base.dpms = DRM_MODE_DPMS_OFF;
8264 	aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
8265 	aconnector->audio_inst = -1;
8266 	aconnector->pack_sdp_v1_3 = false;
8267 	aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
8268 	memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
8269 	mutex_init(&aconnector->hpd_lock);
8270 	mutex_init(&aconnector->handle_mst_msg_ready);
8271 
8272 	/*
8273 	 * configure support HPD hot plug connector_>polled default value is 0
8274 	 * which means HPD hot plug not supported
8275 	 */
8276 	switch (connector_type) {
8277 	case DRM_MODE_CONNECTOR_HDMIA:
8278 		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
8279 		aconnector->base.ycbcr_420_allowed =
8280 			link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
8281 		break;
8282 	case DRM_MODE_CONNECTOR_DisplayPort:
8283 		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
8284 		link->link_enc = link_enc_cfg_get_link_enc(link);
8285 		ASSERT(link->link_enc);
8286 		if (link->link_enc)
8287 			aconnector->base.ycbcr_420_allowed =
8288 			link->link_enc->features.dp_ycbcr420_supported ? true : false;
8289 		break;
8290 	case DRM_MODE_CONNECTOR_DVID:
8291 		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
8292 		break;
8293 	default:
8294 		break;
8295 	}
8296 
8297 	drm_object_attach_property(&aconnector->base.base,
8298 				dm->ddev->mode_config.scaling_mode_property,
8299 				DRM_MODE_SCALE_NONE);
8300 
8301 	drm_object_attach_property(&aconnector->base.base,
8302 				adev->mode_info.underscan_property,
8303 				UNDERSCAN_OFF);
8304 	drm_object_attach_property(&aconnector->base.base,
8305 				adev->mode_info.underscan_hborder_property,
8306 				0);
8307 	drm_object_attach_property(&aconnector->base.base,
8308 				adev->mode_info.underscan_vborder_property,
8309 				0);
8310 
8311 	if (!aconnector->mst_root)
8312 		drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
8313 
8314 	aconnector->base.state->max_bpc = 16;
8315 	aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
8316 
8317 	if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
8318 		/* Content Type is currently only implemented for HDMI. */
8319 		drm_connector_attach_content_type_property(&aconnector->base);
8320 	}
8321 
8322 	if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
8323 		if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
8324 			drm_connector_attach_colorspace_property(&aconnector->base);
8325 	} else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) ||
8326 		   connector_type == DRM_MODE_CONNECTOR_eDP) {
8327 		if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
8328 			drm_connector_attach_colorspace_property(&aconnector->base);
8329 	}
8330 
8331 	if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
8332 	    connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
8333 	    connector_type == DRM_MODE_CONNECTOR_eDP) {
8334 		drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
8335 
8336 		if (!aconnector->mst_root)
8337 			drm_connector_attach_vrr_capable_property(&aconnector->base);
8338 
8339 		if (adev->dm.hdcp_workqueue)
8340 			drm_connector_attach_content_protection_property(&aconnector->base, true);
8341 	}
8342 }
8343 
amdgpu_dm_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msgs,int num)8344 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
8345 			      struct i2c_msg *msgs, int num)
8346 {
8347 	struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
8348 	struct ddc_service *ddc_service = i2c->ddc_service;
8349 	struct i2c_command cmd;
8350 	int i;
8351 	int result = -EIO;
8352 
8353 	if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported)
8354 		return result;
8355 
8356 	cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
8357 
8358 	if (!cmd.payloads)
8359 		return result;
8360 
8361 	cmd.number_of_payloads = num;
8362 	cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
8363 	cmd.speed = 100;
8364 
8365 	for (i = 0; i < num; i++) {
8366 		cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
8367 		cmd.payloads[i].address = msgs[i].addr;
8368 		cmd.payloads[i].length = msgs[i].len;
8369 		cmd.payloads[i].data = msgs[i].buf;
8370 	}
8371 
8372 	if (dc_submit_i2c(
8373 			ddc_service->ctx->dc,
8374 			ddc_service->link->link_index,
8375 			&cmd))
8376 		result = num;
8377 
8378 	kfree(cmd.payloads);
8379 	return result;
8380 }
8381 
amdgpu_dm_i2c_func(struct i2c_adapter * adap)8382 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
8383 {
8384 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
8385 }
8386 
8387 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
8388 	.master_xfer = amdgpu_dm_i2c_xfer,
8389 	.functionality = amdgpu_dm_i2c_func,
8390 };
8391 
8392 static struct amdgpu_i2c_adapter *
create_i2c(struct ddc_service * ddc_service,int link_index,int * res)8393 create_i2c(struct ddc_service *ddc_service,
8394 	   int link_index,
8395 	   int *res)
8396 {
8397 	struct amdgpu_device *adev = ddc_service->ctx->driver_context;
8398 	struct amdgpu_i2c_adapter *i2c;
8399 
8400 	i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
8401 	if (!i2c)
8402 		return NULL;
8403 	i2c->base.owner = THIS_MODULE;
8404 	i2c->base.dev.parent = &adev->pdev->dev;
8405 	i2c->base.algo = &amdgpu_dm_i2c_algo;
8406 	snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
8407 	i2c_set_adapdata(&i2c->base, i2c);
8408 	i2c->ddc_service = ddc_service;
8409 
8410 	return i2c;
8411 }
8412 
amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector * aconnector)8413 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector)
8414 {
8415 	struct cec_connector_info conn_info;
8416 	struct drm_device *ddev = aconnector->base.dev;
8417 	struct device *hdmi_dev = ddev->dev;
8418 
8419 	if (amdgpu_dc_debug_mask & DC_DISABLE_HDMI_CEC) {
8420 		drm_info(ddev, "HDMI-CEC feature masked\n");
8421 		return -EINVAL;
8422 	}
8423 
8424 	cec_fill_conn_info_from_drm(&conn_info, &aconnector->base);
8425 	aconnector->notifier =
8426 		cec_notifier_conn_register(hdmi_dev, NULL, &conn_info);
8427 	if (!aconnector->notifier) {
8428 		drm_err(ddev, "Failed to create cec notifier\n");
8429 		return -ENOMEM;
8430 	}
8431 
8432 	return 0;
8433 }
8434 
8435 /*
8436  * Note: this function assumes that dc_link_detect() was called for the
8437  * dc_link which will be represented by this aconnector.
8438  */
amdgpu_dm_connector_init(struct amdgpu_display_manager * dm,struct amdgpu_dm_connector * aconnector,u32 link_index,struct amdgpu_encoder * aencoder)8439 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
8440 				    struct amdgpu_dm_connector *aconnector,
8441 				    u32 link_index,
8442 				    struct amdgpu_encoder *aencoder)
8443 {
8444 	int res = 0;
8445 	int connector_type;
8446 	struct dc *dc = dm->dc;
8447 	struct dc_link *link = dc_get_link_at_index(dc, link_index);
8448 	struct amdgpu_i2c_adapter *i2c;
8449 
8450 	/* Not needed for writeback connector */
8451 	link->priv = aconnector;
8452 
8453 
8454 	i2c = create_i2c(link->ddc, link->link_index, &res);
8455 	if (!i2c) {
8456 		DRM_ERROR("Failed to create i2c adapter data\n");
8457 		return -ENOMEM;
8458 	}
8459 
8460 	aconnector->i2c = i2c;
8461 	res = i2c_add_adapter(&i2c->base);
8462 
8463 	if (res) {
8464 		DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
8465 		goto out_free;
8466 	}
8467 
8468 	connector_type = to_drm_connector_type(link->connector_signal);
8469 
8470 	res = drm_connector_init_with_ddc(
8471 			dm->ddev,
8472 			&aconnector->base,
8473 			&amdgpu_dm_connector_funcs,
8474 			connector_type,
8475 			&i2c->base);
8476 
8477 	if (res) {
8478 		DRM_ERROR("connector_init failed\n");
8479 		aconnector->connector_id = -1;
8480 		goto out_free;
8481 	}
8482 
8483 	drm_connector_helper_add(
8484 			&aconnector->base,
8485 			&amdgpu_dm_connector_helper_funcs);
8486 
8487 	amdgpu_dm_connector_init_helper(
8488 		dm,
8489 		aconnector,
8490 		connector_type,
8491 		link,
8492 		link_index);
8493 
8494 	drm_connector_attach_encoder(
8495 		&aconnector->base, &aencoder->base);
8496 
8497 	if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
8498 	    connector_type == DRM_MODE_CONNECTOR_HDMIB)
8499 		amdgpu_dm_initialize_hdmi_connector(aconnector);
8500 
8501 	if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
8502 		|| connector_type == DRM_MODE_CONNECTOR_eDP)
8503 		amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
8504 
8505 out_free:
8506 	if (res) {
8507 		kfree(i2c);
8508 		aconnector->i2c = NULL;
8509 	}
8510 	return res;
8511 }
8512 
amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device * adev)8513 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
8514 {
8515 	switch (adev->mode_info.num_crtc) {
8516 	case 1:
8517 		return 0x1;
8518 	case 2:
8519 		return 0x3;
8520 	case 3:
8521 		return 0x7;
8522 	case 4:
8523 		return 0xf;
8524 	case 5:
8525 		return 0x1f;
8526 	case 6:
8527 	default:
8528 		return 0x3f;
8529 	}
8530 }
8531 
amdgpu_dm_encoder_init(struct drm_device * dev,struct amdgpu_encoder * aencoder,uint32_t link_index)8532 static int amdgpu_dm_encoder_init(struct drm_device *dev,
8533 				  struct amdgpu_encoder *aencoder,
8534 				  uint32_t link_index)
8535 {
8536 	struct amdgpu_device *adev = drm_to_adev(dev);
8537 
8538 	int res = drm_encoder_init(dev,
8539 				   &aencoder->base,
8540 				   &amdgpu_dm_encoder_funcs,
8541 				   DRM_MODE_ENCODER_TMDS,
8542 				   NULL);
8543 
8544 	aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
8545 
8546 	if (!res)
8547 		aencoder->encoder_id = link_index;
8548 	else
8549 		aencoder->encoder_id = -1;
8550 
8551 	drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
8552 
8553 	return res;
8554 }
8555 
manage_dm_interrupts(struct amdgpu_device * adev,struct amdgpu_crtc * acrtc,struct dm_crtc_state * acrtc_state)8556 static void manage_dm_interrupts(struct amdgpu_device *adev,
8557 				 struct amdgpu_crtc *acrtc,
8558 				 struct dm_crtc_state *acrtc_state)
8559 {
8560 	struct drm_vblank_crtc_config config = {0};
8561 	struct dc_crtc_timing *timing;
8562 	int offdelay;
8563 
8564 	if (acrtc_state) {
8565 		if (amdgpu_ip_version(adev, DCE_HWIP, 0) <
8566 		    IP_VERSION(3, 5, 0) ||
8567 		    acrtc_state->stream->link->psr_settings.psr_version <
8568 		    DC_PSR_VERSION_UNSUPPORTED ||
8569 		    !(adev->flags & AMD_IS_APU)) {
8570 			timing = &acrtc_state->stream->timing;
8571 
8572 			/* at least 2 frames */
8573 			offdelay = DIV64_U64_ROUND_UP((u64)20 *
8574 						      timing->v_total *
8575 						      timing->h_total,
8576 						      timing->pix_clk_100hz);
8577 
8578 			config.offdelay_ms = offdelay ?: 30;
8579 		} else {
8580 			config.disable_immediate = true;
8581 		}
8582 
8583 		drm_crtc_vblank_on_config(&acrtc->base,
8584 					  &config);
8585 	} else {
8586 		drm_crtc_vblank_off(&acrtc->base);
8587 	}
8588 }
8589 
dm_update_pflip_irq_state(struct amdgpu_device * adev,struct amdgpu_crtc * acrtc)8590 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
8591 				      struct amdgpu_crtc *acrtc)
8592 {
8593 	int irq_type =
8594 		amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
8595 
8596 	/**
8597 	 * This reads the current state for the IRQ and force reapplies
8598 	 * the setting to hardware.
8599 	 */
8600 	amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
8601 }
8602 
8603 static bool
is_scaling_state_different(const struct dm_connector_state * dm_state,const struct dm_connector_state * old_dm_state)8604 is_scaling_state_different(const struct dm_connector_state *dm_state,
8605 			   const struct dm_connector_state *old_dm_state)
8606 {
8607 	if (dm_state->scaling != old_dm_state->scaling)
8608 		return true;
8609 	if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
8610 		if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
8611 			return true;
8612 	} else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
8613 		if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
8614 			return true;
8615 	} else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
8616 		   dm_state->underscan_vborder != old_dm_state->underscan_vborder)
8617 		return true;
8618 	return false;
8619 }
8620 
is_content_protection_different(struct drm_crtc_state * new_crtc_state,struct drm_crtc_state * old_crtc_state,struct drm_connector_state * new_conn_state,struct drm_connector_state * old_conn_state,const struct drm_connector * connector,struct hdcp_workqueue * hdcp_w)8621 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
8622 					    struct drm_crtc_state *old_crtc_state,
8623 					    struct drm_connector_state *new_conn_state,
8624 					    struct drm_connector_state *old_conn_state,
8625 					    const struct drm_connector *connector,
8626 					    struct hdcp_workqueue *hdcp_w)
8627 {
8628 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8629 	struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
8630 
8631 	pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8632 		connector->index, connector->status, connector->dpms);
8633 	pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8634 		old_conn_state->content_protection, new_conn_state->content_protection);
8635 
8636 	if (old_crtc_state)
8637 		pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8638 		old_crtc_state->enable,
8639 		old_crtc_state->active,
8640 		old_crtc_state->mode_changed,
8641 		old_crtc_state->active_changed,
8642 		old_crtc_state->connectors_changed);
8643 
8644 	if (new_crtc_state)
8645 		pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8646 		new_crtc_state->enable,
8647 		new_crtc_state->active,
8648 		new_crtc_state->mode_changed,
8649 		new_crtc_state->active_changed,
8650 		new_crtc_state->connectors_changed);
8651 
8652 	/* hdcp content type change */
8653 	if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
8654 	    new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
8655 		new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8656 		pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
8657 		return true;
8658 	}
8659 
8660 	/* CP is being re enabled, ignore this */
8661 	if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
8662 	    new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
8663 		if (new_crtc_state && new_crtc_state->mode_changed) {
8664 			new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8665 			pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
8666 			return true;
8667 		}
8668 		new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
8669 		pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
8670 		return false;
8671 	}
8672 
8673 	/* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
8674 	 *
8675 	 * Handles:	UNDESIRED -> ENABLED
8676 	 */
8677 	if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
8678 	    new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
8679 		new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8680 
8681 	/* Stream removed and re-enabled
8682 	 *
8683 	 * Can sometimes overlap with the HPD case,
8684 	 * thus set update_hdcp to false to avoid
8685 	 * setting HDCP multiple times.
8686 	 *
8687 	 * Handles:	DESIRED -> DESIRED (Special case)
8688 	 */
8689 	if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
8690 		new_conn_state->crtc && new_conn_state->crtc->enabled &&
8691 		connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
8692 		dm_con_state->update_hdcp = false;
8693 		pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
8694 			__func__);
8695 		return true;
8696 	}
8697 
8698 	/* Hot-plug, headless s3, dpms
8699 	 *
8700 	 * Only start HDCP if the display is connected/enabled.
8701 	 * update_hdcp flag will be set to false until the next
8702 	 * HPD comes in.
8703 	 *
8704 	 * Handles:	DESIRED -> DESIRED (Special case)
8705 	 */
8706 	if (dm_con_state->update_hdcp &&
8707 	new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
8708 	connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
8709 		dm_con_state->update_hdcp = false;
8710 		pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
8711 			__func__);
8712 		return true;
8713 	}
8714 
8715 	if (old_conn_state->content_protection == new_conn_state->content_protection) {
8716 		if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
8717 			if (new_crtc_state && new_crtc_state->mode_changed) {
8718 				pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
8719 					__func__);
8720 				return true;
8721 			}
8722 			pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
8723 				__func__);
8724 			return false;
8725 		}
8726 
8727 		pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
8728 		return false;
8729 	}
8730 
8731 	if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8732 		pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
8733 			__func__);
8734 		return true;
8735 	}
8736 
8737 	pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
8738 	return false;
8739 }
8740 
remove_stream(struct amdgpu_device * adev,struct amdgpu_crtc * acrtc,struct dc_stream_state * stream)8741 static void remove_stream(struct amdgpu_device *adev,
8742 			  struct amdgpu_crtc *acrtc,
8743 			  struct dc_stream_state *stream)
8744 {
8745 	/* this is the update mode case */
8746 
8747 	acrtc->otg_inst = -1;
8748 	acrtc->enabled = false;
8749 }
8750 
prepare_flip_isr(struct amdgpu_crtc * acrtc)8751 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
8752 {
8753 
8754 	assert_spin_locked(&acrtc->base.dev->event_lock);
8755 	WARN_ON(acrtc->event);
8756 
8757 	acrtc->event = acrtc->base.state->event;
8758 
8759 	/* Set the flip status */
8760 	acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
8761 
8762 	/* Mark this event as consumed */
8763 	acrtc->base.state->event = NULL;
8764 
8765 	drm_dbg_state(acrtc->base.dev,
8766 		      "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
8767 		      acrtc->crtc_id);
8768 }
8769 
update_freesync_state_on_stream(struct amdgpu_display_manager * dm,struct dm_crtc_state * new_crtc_state,struct dc_stream_state * new_stream,struct dc_plane_state * surface,u32 flip_timestamp_in_us)8770 static void update_freesync_state_on_stream(
8771 	struct amdgpu_display_manager *dm,
8772 	struct dm_crtc_state *new_crtc_state,
8773 	struct dc_stream_state *new_stream,
8774 	struct dc_plane_state *surface,
8775 	u32 flip_timestamp_in_us)
8776 {
8777 	struct mod_vrr_params vrr_params;
8778 	struct dc_info_packet vrr_infopacket = {0};
8779 	struct amdgpu_device *adev = dm->adev;
8780 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
8781 	unsigned long flags;
8782 	bool pack_sdp_v1_3 = false;
8783 	struct amdgpu_dm_connector *aconn;
8784 	enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
8785 
8786 	if (!new_stream)
8787 		return;
8788 
8789 	/*
8790 	 * TODO: Determine why min/max totals and vrefresh can be 0 here.
8791 	 * For now it's sufficient to just guard against these conditions.
8792 	 */
8793 
8794 	if (!new_stream->timing.h_total || !new_stream->timing.v_total)
8795 		return;
8796 
8797 	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8798 	vrr_params = acrtc->dm_irq_params.vrr_params;
8799 
8800 	if (surface) {
8801 		mod_freesync_handle_preflip(
8802 			dm->freesync_module,
8803 			surface,
8804 			new_stream,
8805 			flip_timestamp_in_us,
8806 			&vrr_params);
8807 
8808 		if (adev->family < AMDGPU_FAMILY_AI &&
8809 		    amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
8810 			mod_freesync_handle_v_update(dm->freesync_module,
8811 						     new_stream, &vrr_params);
8812 
8813 			/* Need to call this before the frame ends. */
8814 			dc_stream_adjust_vmin_vmax(dm->dc,
8815 						   new_crtc_state->stream,
8816 						   &vrr_params.adjust);
8817 		}
8818 	}
8819 
8820 	aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
8821 
8822 	if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) {
8823 		pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
8824 
8825 		if (aconn->vsdb_info.amd_vsdb_version == 1)
8826 			packet_type = PACKET_TYPE_FS_V1;
8827 		else if (aconn->vsdb_info.amd_vsdb_version == 2)
8828 			packet_type = PACKET_TYPE_FS_V2;
8829 		else if (aconn->vsdb_info.amd_vsdb_version == 3)
8830 			packet_type = PACKET_TYPE_FS_V3;
8831 
8832 		mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
8833 					&new_stream->adaptive_sync_infopacket);
8834 	}
8835 
8836 	mod_freesync_build_vrr_infopacket(
8837 		dm->freesync_module,
8838 		new_stream,
8839 		&vrr_params,
8840 		packet_type,
8841 		TRANSFER_FUNC_UNKNOWN,
8842 		&vrr_infopacket,
8843 		pack_sdp_v1_3);
8844 
8845 	new_crtc_state->freesync_vrr_info_changed |=
8846 		(memcmp(&new_crtc_state->vrr_infopacket,
8847 			&vrr_infopacket,
8848 			sizeof(vrr_infopacket)) != 0);
8849 
8850 	acrtc->dm_irq_params.vrr_params = vrr_params;
8851 	new_crtc_state->vrr_infopacket = vrr_infopacket;
8852 
8853 	new_stream->vrr_infopacket = vrr_infopacket;
8854 	new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
8855 
8856 	if (new_crtc_state->freesync_vrr_info_changed)
8857 		DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
8858 			      new_crtc_state->base.crtc->base.id,
8859 			      (int)new_crtc_state->base.vrr_enabled,
8860 			      (int)vrr_params.state);
8861 
8862 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8863 }
8864 
update_stream_irq_parameters(struct amdgpu_display_manager * dm,struct dm_crtc_state * new_crtc_state)8865 static void update_stream_irq_parameters(
8866 	struct amdgpu_display_manager *dm,
8867 	struct dm_crtc_state *new_crtc_state)
8868 {
8869 	struct dc_stream_state *new_stream = new_crtc_state->stream;
8870 	struct mod_vrr_params vrr_params;
8871 	struct mod_freesync_config config = new_crtc_state->freesync_config;
8872 	struct amdgpu_device *adev = dm->adev;
8873 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
8874 	unsigned long flags;
8875 
8876 	if (!new_stream)
8877 		return;
8878 
8879 	/*
8880 	 * TODO: Determine why min/max totals and vrefresh can be 0 here.
8881 	 * For now it's sufficient to just guard against these conditions.
8882 	 */
8883 	if (!new_stream->timing.h_total || !new_stream->timing.v_total)
8884 		return;
8885 
8886 	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8887 	vrr_params = acrtc->dm_irq_params.vrr_params;
8888 
8889 	if (new_crtc_state->vrr_supported &&
8890 	    config.min_refresh_in_uhz &&
8891 	    config.max_refresh_in_uhz) {
8892 		/*
8893 		 * if freesync compatible mode was set, config.state will be set
8894 		 * in atomic check
8895 		 */
8896 		if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
8897 		    (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
8898 		     new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
8899 			vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
8900 			vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
8901 			vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
8902 			vrr_params.state = VRR_STATE_ACTIVE_FIXED;
8903 		} else {
8904 			config.state = new_crtc_state->base.vrr_enabled ?
8905 						     VRR_STATE_ACTIVE_VARIABLE :
8906 						     VRR_STATE_INACTIVE;
8907 		}
8908 	} else {
8909 		config.state = VRR_STATE_UNSUPPORTED;
8910 	}
8911 
8912 	mod_freesync_build_vrr_params(dm->freesync_module,
8913 				      new_stream,
8914 				      &config, &vrr_params);
8915 
8916 	new_crtc_state->freesync_config = config;
8917 	/* Copy state for access from DM IRQ handler */
8918 	acrtc->dm_irq_params.freesync_config = config;
8919 	acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
8920 	acrtc->dm_irq_params.vrr_params = vrr_params;
8921 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8922 }
8923 
amdgpu_dm_handle_vrr_transition(struct dm_crtc_state * old_state,struct dm_crtc_state * new_state)8924 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
8925 					    struct dm_crtc_state *new_state)
8926 {
8927 	bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
8928 	bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
8929 
8930 	if (!old_vrr_active && new_vrr_active) {
8931 		/* Transition VRR inactive -> active:
8932 		 * While VRR is active, we must not disable vblank irq, as a
8933 		 * reenable after disable would compute bogus vblank/pflip
8934 		 * timestamps if it likely happened inside display front-porch.
8935 		 *
8936 		 * We also need vupdate irq for the actual core vblank handling
8937 		 * at end of vblank.
8938 		 */
8939 		WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
8940 		WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
8941 		DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
8942 				 __func__, new_state->base.crtc->base.id);
8943 	} else if (old_vrr_active && !new_vrr_active) {
8944 		/* Transition VRR active -> inactive:
8945 		 * Allow vblank irq disable again for fixed refresh rate.
8946 		 */
8947 		WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
8948 		drm_crtc_vblank_put(new_state->base.crtc);
8949 		DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
8950 				 __func__, new_state->base.crtc->base.id);
8951 	}
8952 }
8953 
amdgpu_dm_commit_cursors(struct drm_atomic_state * state)8954 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
8955 {
8956 	struct drm_plane *plane;
8957 	struct drm_plane_state *old_plane_state;
8958 	int i;
8959 
8960 	/*
8961 	 * TODO: Make this per-stream so we don't issue redundant updates for
8962 	 * commits with multiple streams.
8963 	 */
8964 	for_each_old_plane_in_state(state, plane, old_plane_state, i)
8965 		if (plane->type == DRM_PLANE_TYPE_CURSOR)
8966 			amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
8967 }
8968 
get_mem_type(struct drm_framebuffer * fb)8969 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
8970 {
8971 	struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
8972 
8973 	return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
8974 }
8975 
amdgpu_dm_update_cursor(struct drm_plane * plane,struct drm_plane_state * old_plane_state,struct dc_stream_update * update)8976 static void amdgpu_dm_update_cursor(struct drm_plane *plane,
8977 				    struct drm_plane_state *old_plane_state,
8978 				    struct dc_stream_update *update)
8979 {
8980 	struct amdgpu_device *adev = drm_to_adev(plane->dev);
8981 	struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
8982 	struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
8983 	struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
8984 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
8985 	uint64_t address = afb ? afb->address : 0;
8986 	struct dc_cursor_position position = {0};
8987 	struct dc_cursor_attributes attributes;
8988 	int ret;
8989 
8990 	if (!plane->state->fb && !old_plane_state->fb)
8991 		return;
8992 
8993 	drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n",
8994 		       amdgpu_crtc->crtc_id, plane->state->crtc_w,
8995 		       plane->state->crtc_h);
8996 
8997 	ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position);
8998 	if (ret)
8999 		return;
9000 
9001 	if (!position.enable) {
9002 		/* turn off cursor */
9003 		if (crtc_state && crtc_state->stream) {
9004 			dc_stream_set_cursor_position(crtc_state->stream,
9005 						      &position);
9006 			update->cursor_position = &crtc_state->stream->cursor_position;
9007 		}
9008 		return;
9009 	}
9010 
9011 	amdgpu_crtc->cursor_width = plane->state->crtc_w;
9012 	amdgpu_crtc->cursor_height = plane->state->crtc_h;
9013 
9014 	memset(&attributes, 0, sizeof(attributes));
9015 	attributes.address.high_part = upper_32_bits(address);
9016 	attributes.address.low_part  = lower_32_bits(address);
9017 	attributes.width             = plane->state->crtc_w;
9018 	attributes.height            = plane->state->crtc_h;
9019 	attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
9020 	attributes.rotation_angle    = 0;
9021 	attributes.attribute_flags.value = 0;
9022 
9023 	/* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM
9024 	 * legacy gamma setup.
9025 	 */
9026 	if (crtc_state->cm_is_degamma_srgb &&
9027 	    adev->dm.dc->caps.color.dpp.gamma_corr)
9028 		attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1;
9029 
9030 	if (afb)
9031 		attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0];
9032 
9033 	if (crtc_state->stream) {
9034 		if (!dc_stream_set_cursor_attributes(crtc_state->stream,
9035 						     &attributes))
9036 			DRM_ERROR("DC failed to set cursor attributes\n");
9037 
9038 		update->cursor_attributes = &crtc_state->stream->cursor_attributes;
9039 
9040 		if (!dc_stream_set_cursor_position(crtc_state->stream,
9041 						   &position))
9042 			DRM_ERROR("DC failed to set cursor position\n");
9043 
9044 		update->cursor_position = &crtc_state->stream->cursor_position;
9045 	}
9046 }
9047 
amdgpu_dm_enable_self_refresh(struct amdgpu_crtc * acrtc_attach,const struct dm_crtc_state * acrtc_state,const u64 current_ts)9048 static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach,
9049 					  const struct dm_crtc_state *acrtc_state,
9050 					  const u64 current_ts)
9051 {
9052 	struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
9053 	struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;
9054 	struct amdgpu_dm_connector *aconn =
9055 		(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
9056 	bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
9057 
9058 	if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
9059 		if (pr->config.replay_supported && !pr->replay_feature_enabled)
9060 			amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
9061 		else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED &&
9062 			     !psr->psr_feature_enabled)
9063 			if (!aconn->disallow_edp_enter_psr)
9064 				amdgpu_dm_link_setup_psr(acrtc_state->stream);
9065 	}
9066 
9067 	/* Decrement skip count when SR is enabled and we're doing fast updates. */
9068 	if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
9069 	    (psr->psr_feature_enabled || pr->config.replay_supported)) {
9070 		if (aconn->sr_skip_count > 0)
9071 			aconn->sr_skip_count--;
9072 
9073 		/* Allow SR when skip count is 0. */
9074 		acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count;
9075 
9076 		/*
9077 		 * If sink supports PSR SU/Panel Replay, there is no need to rely on
9078 		 * a vblank event disable request to enable PSR/RP. PSR SU/RP
9079 		 * can be enabled immediately once OS demonstrates an
9080 		 * adequate number of fast atomic commits to notify KMD
9081 		 * of update events. See `vblank_control_worker()`.
9082 		 */
9083 		if (!vrr_active &&
9084 		    acrtc_attach->dm_irq_params.allow_sr_entry &&
9085 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
9086 		    !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
9087 #endif
9088 		    (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) {
9089 			if (pr->replay_feature_enabled && !pr->replay_allow_active)
9090 				amdgpu_dm_replay_enable(acrtc_state->stream, true);
9091 			if (psr->psr_version == DC_PSR_VERSION_SU_1 &&
9092 			    !psr->psr_allow_active && !aconn->disallow_edp_enter_psr)
9093 				amdgpu_dm_psr_enable(acrtc_state->stream);
9094 		}
9095 	} else {
9096 		acrtc_attach->dm_irq_params.allow_sr_entry = false;
9097 	}
9098 }
9099 
amdgpu_dm_commit_planes(struct drm_atomic_state * state,struct drm_device * dev,struct amdgpu_display_manager * dm,struct drm_crtc * pcrtc,bool wait_for_vblank)9100 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
9101 				    struct drm_device *dev,
9102 				    struct amdgpu_display_manager *dm,
9103 				    struct drm_crtc *pcrtc,
9104 				    bool wait_for_vblank)
9105 {
9106 	u32 i;
9107 	u64 timestamp_ns = ktime_get_ns();
9108 	struct drm_plane *plane;
9109 	struct drm_plane_state *old_plane_state, *new_plane_state;
9110 	struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
9111 	struct drm_crtc_state *new_pcrtc_state =
9112 			drm_atomic_get_new_crtc_state(state, pcrtc);
9113 	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
9114 	struct dm_crtc_state *dm_old_crtc_state =
9115 			to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
9116 	int planes_count = 0, vpos, hpos;
9117 	unsigned long flags;
9118 	u32 target_vblank, last_flip_vblank;
9119 	bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
9120 	bool cursor_update = false;
9121 	bool pflip_present = false;
9122 	bool dirty_rects_changed = false;
9123 	bool updated_planes_and_streams = false;
9124 	struct {
9125 		struct dc_surface_update surface_updates[MAX_SURFACES];
9126 		struct dc_plane_info plane_infos[MAX_SURFACES];
9127 		struct dc_scaling_info scaling_infos[MAX_SURFACES];
9128 		struct dc_flip_addrs flip_addrs[MAX_SURFACES];
9129 		struct dc_stream_update stream_update;
9130 	} *bundle;
9131 
9132 	bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
9133 
9134 	if (!bundle) {
9135 		drm_err(dev, "Failed to allocate update bundle\n");
9136 		goto cleanup;
9137 	}
9138 
9139 	/*
9140 	 * Disable the cursor first if we're disabling all the planes.
9141 	 * It'll remain on the screen after the planes are re-enabled
9142 	 * if we don't.
9143 	 *
9144 	 * If the cursor is transitioning from native to overlay mode, the
9145 	 * native cursor needs to be disabled first.
9146 	 */
9147 	if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE &&
9148 	    dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) {
9149 		struct dc_cursor_position cursor_position = {0};
9150 
9151 		if (!dc_stream_set_cursor_position(acrtc_state->stream,
9152 						   &cursor_position))
9153 			drm_err(dev, "DC failed to disable native cursor\n");
9154 
9155 		bundle->stream_update.cursor_position =
9156 				&acrtc_state->stream->cursor_position;
9157 	}
9158 
9159 	if (acrtc_state->active_planes == 0 &&
9160 	    dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE)
9161 		amdgpu_dm_commit_cursors(state);
9162 
9163 	/* update planes when needed */
9164 	for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9165 		struct drm_crtc *crtc = new_plane_state->crtc;
9166 		struct drm_crtc_state *new_crtc_state;
9167 		struct drm_framebuffer *fb = new_plane_state->fb;
9168 		struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
9169 		bool plane_needs_flip;
9170 		struct dc_plane_state *dc_plane;
9171 		struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
9172 
9173 		/* Cursor plane is handled after stream updates */
9174 		if (plane->type == DRM_PLANE_TYPE_CURSOR &&
9175 		    acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) {
9176 			if ((fb && crtc == pcrtc) ||
9177 			    (old_plane_state->fb && old_plane_state->crtc == pcrtc)) {
9178 				cursor_update = true;
9179 				if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0)
9180 					amdgpu_dm_update_cursor(plane, old_plane_state, &bundle->stream_update);
9181 			}
9182 
9183 			continue;
9184 		}
9185 
9186 		if (!fb || !crtc || pcrtc != crtc)
9187 			continue;
9188 
9189 		new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
9190 		if (!new_crtc_state->active)
9191 			continue;
9192 
9193 		dc_plane = dm_new_plane_state->dc_state;
9194 		if (!dc_plane)
9195 			continue;
9196 
9197 		bundle->surface_updates[planes_count].surface = dc_plane;
9198 		if (new_pcrtc_state->color_mgmt_changed) {
9199 			bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction;
9200 			bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func;
9201 			bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
9202 			bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult;
9203 			bundle->surface_updates[planes_count].func_shaper = &dc_plane->in_shaper_func;
9204 			bundle->surface_updates[planes_count].lut3d_func = &dc_plane->lut3d_func;
9205 			bundle->surface_updates[planes_count].blend_tf = &dc_plane->blend_tf;
9206 		}
9207 
9208 		amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
9209 				     &bundle->scaling_infos[planes_count]);
9210 
9211 		bundle->surface_updates[planes_count].scaling_info =
9212 			&bundle->scaling_infos[planes_count];
9213 
9214 		plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
9215 
9216 		pflip_present = pflip_present || plane_needs_flip;
9217 
9218 		if (!plane_needs_flip) {
9219 			planes_count += 1;
9220 			continue;
9221 		}
9222 
9223 		fill_dc_plane_info_and_addr(
9224 			dm->adev, new_plane_state,
9225 			afb->tiling_flags,
9226 			&bundle->plane_infos[planes_count],
9227 			&bundle->flip_addrs[planes_count].address,
9228 			afb->tmz_surface);
9229 
9230 		drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
9231 				 new_plane_state->plane->index,
9232 				 bundle->plane_infos[planes_count].dcc.enable);
9233 
9234 		bundle->surface_updates[planes_count].plane_info =
9235 			&bundle->plane_infos[planes_count];
9236 
9237 		if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||
9238 		    acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
9239 			fill_dc_dirty_rects(plane, old_plane_state,
9240 					    new_plane_state, new_crtc_state,
9241 					    &bundle->flip_addrs[planes_count],
9242 					    acrtc_state->stream->link->psr_settings.psr_version ==
9243 					    DC_PSR_VERSION_SU_1,
9244 					    &dirty_rects_changed);
9245 
9246 			/*
9247 			 * If the dirty regions changed, PSR-SU need to be disabled temporarily
9248 			 * and enabled it again after dirty regions are stable to avoid video glitch.
9249 			 * PSR-SU will be enabled in vblank_control_worker() if user pause the video
9250 			 * during the PSR-SU was disabled.
9251 			 */
9252 			if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
9253 			    acrtc_attach->dm_irq_params.allow_sr_entry &&
9254 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
9255 			    !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
9256 #endif
9257 			    dirty_rects_changed) {
9258 				mutex_lock(&dm->dc_lock);
9259 				acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
9260 				timestamp_ns;
9261 				if (acrtc_state->stream->link->psr_settings.psr_allow_active)
9262 					amdgpu_dm_psr_disable(acrtc_state->stream, true);
9263 				mutex_unlock(&dm->dc_lock);
9264 			}
9265 		}
9266 
9267 		/*
9268 		 * Only allow immediate flips for fast updates that don't
9269 		 * change memory domain, FB pitch, DCC state, rotation or
9270 		 * mirroring.
9271 		 *
9272 		 * dm_crtc_helper_atomic_check() only accepts async flips with
9273 		 * fast updates.
9274 		 */
9275 		if (crtc->state->async_flip &&
9276 		    (acrtc_state->update_type != UPDATE_TYPE_FAST ||
9277 		     get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
9278 			drm_warn_once(state->dev,
9279 				      "[PLANE:%d:%s] async flip with non-fast update\n",
9280 				      plane->base.id, plane->name);
9281 
9282 		bundle->flip_addrs[planes_count].flip_immediate =
9283 			crtc->state->async_flip &&
9284 			acrtc_state->update_type == UPDATE_TYPE_FAST &&
9285 			get_mem_type(old_plane_state->fb) == get_mem_type(fb);
9286 
9287 		timestamp_ns = ktime_get_ns();
9288 		bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
9289 		bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
9290 		bundle->surface_updates[planes_count].surface = dc_plane;
9291 
9292 		if (!bundle->surface_updates[planes_count].surface) {
9293 			DRM_ERROR("No surface for CRTC: id=%d\n",
9294 					acrtc_attach->crtc_id);
9295 			continue;
9296 		}
9297 
9298 		if (plane == pcrtc->primary)
9299 			update_freesync_state_on_stream(
9300 				dm,
9301 				acrtc_state,
9302 				acrtc_state->stream,
9303 				dc_plane,
9304 				bundle->flip_addrs[planes_count].flip_timestamp_in_us);
9305 
9306 		drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
9307 				 __func__,
9308 				 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
9309 				 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
9310 
9311 		planes_count += 1;
9312 
9313 	}
9314 
9315 	if (pflip_present) {
9316 		if (!vrr_active) {
9317 			/* Use old throttling in non-vrr fixed refresh rate mode
9318 			 * to keep flip scheduling based on target vblank counts
9319 			 * working in a backwards compatible way, e.g., for
9320 			 * clients using the GLX_OML_sync_control extension or
9321 			 * DRI3/Present extension with defined target_msc.
9322 			 */
9323 			last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
9324 		} else {
9325 			/* For variable refresh rate mode only:
9326 			 * Get vblank of last completed flip to avoid > 1 vrr
9327 			 * flips per video frame by use of throttling, but allow
9328 			 * flip programming anywhere in the possibly large
9329 			 * variable vrr vblank interval for fine-grained flip
9330 			 * timing control and more opportunity to avoid stutter
9331 			 * on late submission of flips.
9332 			 */
9333 			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
9334 			last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
9335 			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
9336 		}
9337 
9338 		target_vblank = last_flip_vblank + wait_for_vblank;
9339 
9340 		/*
9341 		 * Wait until we're out of the vertical blank period before the one
9342 		 * targeted by the flip
9343 		 */
9344 		while ((acrtc_attach->enabled &&
9345 			(amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
9346 							    0, &vpos, &hpos, NULL,
9347 							    NULL, &pcrtc->hwmode)
9348 			 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
9349 			(DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
9350 			(int)(target_vblank -
9351 			  amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
9352 			usleep_range(1000, 1100);
9353 		}
9354 
9355 		/**
9356 		 * Prepare the flip event for the pageflip interrupt to handle.
9357 		 *
9358 		 * This only works in the case where we've already turned on the
9359 		 * appropriate hardware blocks (eg. HUBP) so in the transition case
9360 		 * from 0 -> n planes we have to skip a hardware generated event
9361 		 * and rely on sending it from software.
9362 		 */
9363 		if (acrtc_attach->base.state->event &&
9364 		    acrtc_state->active_planes > 0) {
9365 			drm_crtc_vblank_get(pcrtc);
9366 
9367 			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
9368 
9369 			WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
9370 			prepare_flip_isr(acrtc_attach);
9371 
9372 			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
9373 		}
9374 
9375 		if (acrtc_state->stream) {
9376 			if (acrtc_state->freesync_vrr_info_changed)
9377 				bundle->stream_update.vrr_infopacket =
9378 					&acrtc_state->stream->vrr_infopacket;
9379 		}
9380 	} else if (cursor_update && acrtc_state->active_planes > 0) {
9381 		spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
9382 		if (acrtc_attach->base.state->event) {
9383 			drm_crtc_vblank_get(pcrtc);
9384 			acrtc_attach->event = acrtc_attach->base.state->event;
9385 			acrtc_attach->base.state->event = NULL;
9386 		}
9387 		spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
9388 	}
9389 
9390 	/* Update the planes if changed or disable if we don't have any. */
9391 	if ((planes_count || acrtc_state->active_planes == 0) &&
9392 		acrtc_state->stream) {
9393 		/*
9394 		 * If PSR or idle optimizations are enabled then flush out
9395 		 * any pending work before hardware programming.
9396 		 */
9397 		if (dm->vblank_control_workqueue)
9398 			flush_workqueue(dm->vblank_control_workqueue);
9399 
9400 		bundle->stream_update.stream = acrtc_state->stream;
9401 		if (new_pcrtc_state->mode_changed) {
9402 			bundle->stream_update.src = acrtc_state->stream->src;
9403 			bundle->stream_update.dst = acrtc_state->stream->dst;
9404 		}
9405 
9406 		if (new_pcrtc_state->color_mgmt_changed) {
9407 			/*
9408 			 * TODO: This isn't fully correct since we've actually
9409 			 * already modified the stream in place.
9410 			 */
9411 			bundle->stream_update.gamut_remap =
9412 				&acrtc_state->stream->gamut_remap_matrix;
9413 			bundle->stream_update.output_csc_transform =
9414 				&acrtc_state->stream->csc_color_matrix;
9415 			bundle->stream_update.out_transfer_func =
9416 				&acrtc_state->stream->out_transfer_func;
9417 			bundle->stream_update.lut3d_func =
9418 				(struct dc_3dlut *) acrtc_state->stream->lut3d_func;
9419 			bundle->stream_update.func_shaper =
9420 				(struct dc_transfer_func *) acrtc_state->stream->func_shaper;
9421 		}
9422 
9423 		acrtc_state->stream->abm_level = acrtc_state->abm_level;
9424 		if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
9425 			bundle->stream_update.abm_level = &acrtc_state->abm_level;
9426 
9427 		mutex_lock(&dm->dc_lock);
9428 		if ((acrtc_state->update_type > UPDATE_TYPE_FAST) || vrr_active) {
9429 			if (acrtc_state->stream->link->replay_settings.replay_allow_active)
9430 				amdgpu_dm_replay_disable(acrtc_state->stream);
9431 			if (acrtc_state->stream->link->psr_settings.psr_allow_active)
9432 				amdgpu_dm_psr_disable(acrtc_state->stream, true);
9433 		}
9434 		mutex_unlock(&dm->dc_lock);
9435 
9436 		/*
9437 		 * If FreeSync state on the stream has changed then we need to
9438 		 * re-adjust the min/max bounds now that DC doesn't handle this
9439 		 * as part of commit.
9440 		 */
9441 		if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
9442 			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
9443 			dc_stream_adjust_vmin_vmax(
9444 				dm->dc, acrtc_state->stream,
9445 				&acrtc_attach->dm_irq_params.vrr_params.adjust);
9446 			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
9447 		}
9448 		mutex_lock(&dm->dc_lock);
9449 		update_planes_and_stream_adapter(dm->dc,
9450 					 acrtc_state->update_type,
9451 					 planes_count,
9452 					 acrtc_state->stream,
9453 					 &bundle->stream_update,
9454 					 bundle->surface_updates);
9455 		updated_planes_and_streams = true;
9456 
9457 		/**
9458 		 * Enable or disable the interrupts on the backend.
9459 		 *
9460 		 * Most pipes are put into power gating when unused.
9461 		 *
9462 		 * When power gating is enabled on a pipe we lose the
9463 		 * interrupt enablement state when power gating is disabled.
9464 		 *
9465 		 * So we need to update the IRQ control state in hardware
9466 		 * whenever the pipe turns on (since it could be previously
9467 		 * power gated) or off (since some pipes can't be power gated
9468 		 * on some ASICs).
9469 		 */
9470 		if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
9471 			dm_update_pflip_irq_state(drm_to_adev(dev),
9472 						  acrtc_attach);
9473 
9474 		amdgpu_dm_enable_self_refresh(acrtc_attach, acrtc_state, timestamp_ns);
9475 		mutex_unlock(&dm->dc_lock);
9476 	}
9477 
9478 	/*
9479 	 * Update cursor state *after* programming all the planes.
9480 	 * This avoids redundant programming in the case where we're going
9481 	 * to be disabling a single plane - those pipes are being disabled.
9482 	 */
9483 	if (acrtc_state->active_planes &&
9484 	    (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) &&
9485 	    acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE)
9486 		amdgpu_dm_commit_cursors(state);
9487 
9488 cleanup:
9489 	kfree(bundle);
9490 }
9491 
amdgpu_dm_commit_audio(struct drm_device * dev,struct drm_atomic_state * state)9492 static void amdgpu_dm_commit_audio(struct drm_device *dev,
9493 				   struct drm_atomic_state *state)
9494 {
9495 	struct amdgpu_device *adev = drm_to_adev(dev);
9496 	struct amdgpu_dm_connector *aconnector;
9497 	struct drm_connector *connector;
9498 	struct drm_connector_state *old_con_state, *new_con_state;
9499 	struct drm_crtc_state *new_crtc_state;
9500 	struct dm_crtc_state *new_dm_crtc_state;
9501 	const struct dc_stream_status *status;
9502 	int i, inst;
9503 
9504 	/* Notify device removals. */
9505 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9506 		if (old_con_state->crtc != new_con_state->crtc) {
9507 			/* CRTC changes require notification. */
9508 			goto notify;
9509 		}
9510 
9511 		if (!new_con_state->crtc)
9512 			continue;
9513 
9514 		new_crtc_state = drm_atomic_get_new_crtc_state(
9515 			state, new_con_state->crtc);
9516 
9517 		if (!new_crtc_state)
9518 			continue;
9519 
9520 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9521 			continue;
9522 
9523 notify:
9524 		if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
9525 			continue;
9526 
9527 		aconnector = to_amdgpu_dm_connector(connector);
9528 
9529 		mutex_lock(&adev->dm.audio_lock);
9530 		inst = aconnector->audio_inst;
9531 		aconnector->audio_inst = -1;
9532 		mutex_unlock(&adev->dm.audio_lock);
9533 
9534 		amdgpu_dm_audio_eld_notify(adev, inst);
9535 	}
9536 
9537 	/* Notify audio device additions. */
9538 	for_each_new_connector_in_state(state, connector, new_con_state, i) {
9539 		if (!new_con_state->crtc)
9540 			continue;
9541 
9542 		new_crtc_state = drm_atomic_get_new_crtc_state(
9543 			state, new_con_state->crtc);
9544 
9545 		if (!new_crtc_state)
9546 			continue;
9547 
9548 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9549 			continue;
9550 
9551 		new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
9552 		if (!new_dm_crtc_state->stream)
9553 			continue;
9554 
9555 		status = dc_stream_get_status(new_dm_crtc_state->stream);
9556 		if (!status)
9557 			continue;
9558 
9559 		if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
9560 			continue;
9561 
9562 		aconnector = to_amdgpu_dm_connector(connector);
9563 
9564 		mutex_lock(&adev->dm.audio_lock);
9565 		inst = status->audio_inst;
9566 		aconnector->audio_inst = inst;
9567 		mutex_unlock(&adev->dm.audio_lock);
9568 
9569 		amdgpu_dm_audio_eld_notify(adev, inst);
9570 	}
9571 }
9572 
9573 /*
9574  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
9575  * @crtc_state: the DRM CRTC state
9576  * @stream_state: the DC stream state.
9577  *
9578  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
9579  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
9580  */
amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state * crtc_state,struct dc_stream_state * stream_state)9581 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
9582 						struct dc_stream_state *stream_state)
9583 {
9584 	stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
9585 }
9586 
dm_clear_writeback(struct amdgpu_display_manager * dm,struct dm_crtc_state * crtc_state)9587 static void dm_clear_writeback(struct amdgpu_display_manager *dm,
9588 			      struct dm_crtc_state *crtc_state)
9589 {
9590 	dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0);
9591 }
9592 
amdgpu_dm_commit_streams(struct drm_atomic_state * state,struct dc_state * dc_state)9593 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
9594 					struct dc_state *dc_state)
9595 {
9596 	struct drm_device *dev = state->dev;
9597 	struct amdgpu_device *adev = drm_to_adev(dev);
9598 	struct amdgpu_display_manager *dm = &adev->dm;
9599 	struct drm_crtc *crtc;
9600 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9601 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9602 	struct drm_connector_state *old_con_state;
9603 	struct drm_connector *connector;
9604 	bool mode_set_reset_required = false;
9605 	u32 i;
9606 	struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count};
9607 	bool set_backlight_level = false;
9608 
9609 	/* Disable writeback */
9610 	for_each_old_connector_in_state(state, connector, old_con_state, i) {
9611 		struct dm_connector_state *dm_old_con_state;
9612 		struct amdgpu_crtc *acrtc;
9613 
9614 		if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
9615 			continue;
9616 
9617 		old_crtc_state = NULL;
9618 
9619 		dm_old_con_state = to_dm_connector_state(old_con_state);
9620 		if (!dm_old_con_state->base.crtc)
9621 			continue;
9622 
9623 		acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc);
9624 		if (acrtc)
9625 			old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
9626 
9627 		if (!acrtc || !acrtc->wb_enabled)
9628 			continue;
9629 
9630 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9631 
9632 		dm_clear_writeback(dm, dm_old_crtc_state);
9633 		acrtc->wb_enabled = false;
9634 	}
9635 
9636 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
9637 				      new_crtc_state, i) {
9638 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
9639 
9640 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9641 
9642 		if (old_crtc_state->active &&
9643 		    (!new_crtc_state->active ||
9644 		     drm_atomic_crtc_needs_modeset(new_crtc_state))) {
9645 			manage_dm_interrupts(adev, acrtc, NULL);
9646 			dc_stream_release(dm_old_crtc_state->stream);
9647 		}
9648 	}
9649 
9650 	drm_atomic_helper_calc_timestamping_constants(state);
9651 
9652 	/* update changed items */
9653 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9654 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
9655 
9656 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9657 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9658 
9659 		drm_dbg_state(state->dev,
9660 			"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
9661 			acrtc->crtc_id,
9662 			new_crtc_state->enable,
9663 			new_crtc_state->active,
9664 			new_crtc_state->planes_changed,
9665 			new_crtc_state->mode_changed,
9666 			new_crtc_state->active_changed,
9667 			new_crtc_state->connectors_changed);
9668 
9669 		/* Disable cursor if disabling crtc */
9670 		if (old_crtc_state->active && !new_crtc_state->active) {
9671 			struct dc_cursor_position position;
9672 
9673 			memset(&position, 0, sizeof(position));
9674 			mutex_lock(&dm->dc_lock);
9675 			dc_exit_ips_for_hw_access(dm->dc);
9676 			dc_stream_program_cursor_position(dm_old_crtc_state->stream, &position);
9677 			mutex_unlock(&dm->dc_lock);
9678 		}
9679 
9680 		/* Copy all transient state flags into dc state */
9681 		if (dm_new_crtc_state->stream) {
9682 			amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
9683 							    dm_new_crtc_state->stream);
9684 		}
9685 
9686 		/* handles headless hotplug case, updating new_state and
9687 		 * aconnector as needed
9688 		 */
9689 
9690 		if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
9691 
9692 			drm_dbg_atomic(dev,
9693 				       "Atomic commit: SET crtc id %d: [%p]\n",
9694 				       acrtc->crtc_id, acrtc);
9695 
9696 			if (!dm_new_crtc_state->stream) {
9697 				/*
9698 				 * this could happen because of issues with
9699 				 * userspace notifications delivery.
9700 				 * In this case userspace tries to set mode on
9701 				 * display which is disconnected in fact.
9702 				 * dc_sink is NULL in this case on aconnector.
9703 				 * We expect reset mode will come soon.
9704 				 *
9705 				 * This can also happen when unplug is done
9706 				 * during resume sequence ended
9707 				 *
9708 				 * In this case, we want to pretend we still
9709 				 * have a sink to keep the pipe running so that
9710 				 * hw state is consistent with the sw state
9711 				 */
9712 				drm_dbg_atomic(dev,
9713 					       "Failed to create new stream for crtc %d\n",
9714 						acrtc->base.base.id);
9715 				continue;
9716 			}
9717 
9718 			if (dm_old_crtc_state->stream)
9719 				remove_stream(adev, acrtc, dm_old_crtc_state->stream);
9720 
9721 			pm_runtime_get_noresume(dev->dev);
9722 
9723 			acrtc->enabled = true;
9724 			acrtc->hw_mode = new_crtc_state->mode;
9725 			crtc->hwmode = new_crtc_state->mode;
9726 			mode_set_reset_required = true;
9727 			set_backlight_level = true;
9728 		} else if (modereset_required(new_crtc_state)) {
9729 			drm_dbg_atomic(dev,
9730 				       "Atomic commit: RESET. crtc id %d:[%p]\n",
9731 				       acrtc->crtc_id, acrtc);
9732 			/* i.e. reset mode */
9733 			if (dm_old_crtc_state->stream)
9734 				remove_stream(adev, acrtc, dm_old_crtc_state->stream);
9735 
9736 			mode_set_reset_required = true;
9737 		}
9738 	} /* for_each_crtc_in_state() */
9739 
9740 	/* if there mode set or reset, disable eDP PSR, Replay */
9741 	if (mode_set_reset_required) {
9742 		if (dm->vblank_control_workqueue)
9743 			flush_workqueue(dm->vblank_control_workqueue);
9744 
9745 		amdgpu_dm_replay_disable_all(dm);
9746 		amdgpu_dm_psr_disable_all(dm);
9747 	}
9748 
9749 	dm_enable_per_frame_crtc_master_sync(dc_state);
9750 	mutex_lock(&dm->dc_lock);
9751 	dc_exit_ips_for_hw_access(dm->dc);
9752 	WARN_ON(!dc_commit_streams(dm->dc, &params));
9753 
9754 	/* Allow idle optimization when vblank count is 0 for display off */
9755 	if ((dm->active_vblank_irq_count == 0) && amdgpu_dm_is_headless(dm->adev))
9756 		dc_allow_idle_optimizations(dm->dc, true);
9757 	mutex_unlock(&dm->dc_lock);
9758 
9759 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9760 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
9761 
9762 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9763 
9764 		if (dm_new_crtc_state->stream != NULL) {
9765 			const struct dc_stream_status *status =
9766 					dc_stream_get_status(dm_new_crtc_state->stream);
9767 
9768 			if (!status)
9769 				status = dc_state_get_stream_status(dc_state,
9770 									 dm_new_crtc_state->stream);
9771 			if (!status)
9772 				drm_err(dev,
9773 					"got no status for stream %p on acrtc%p\n",
9774 					dm_new_crtc_state->stream, acrtc);
9775 			else
9776 				acrtc->otg_inst = status->primary_otg_inst;
9777 		}
9778 	}
9779 
9780 	/* During boot up and resume the DC layer will reset the panel brightness
9781 	 * to fix a flicker issue.
9782 	 * It will cause the dm->actual_brightness is not the current panel brightness
9783 	 * level. (the dm->brightness is the correct panel level)
9784 	 * So we set the backlight level with dm->brightness value after set mode
9785 	 */
9786 	if (set_backlight_level) {
9787 		for (i = 0; i < dm->num_of_edps; i++) {
9788 			if (dm->backlight_dev[i])
9789 				amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
9790 		}
9791 	}
9792 }
9793 
dm_set_writeback(struct amdgpu_display_manager * dm,struct dm_crtc_state * crtc_state,struct drm_connector * connector,struct drm_connector_state * new_con_state)9794 static void dm_set_writeback(struct amdgpu_display_manager *dm,
9795 			      struct dm_crtc_state *crtc_state,
9796 			      struct drm_connector *connector,
9797 			      struct drm_connector_state *new_con_state)
9798 {
9799 	struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector);
9800 	struct amdgpu_device *adev = dm->adev;
9801 	struct amdgpu_crtc *acrtc;
9802 	struct dc_writeback_info *wb_info;
9803 	struct pipe_ctx *pipe = NULL;
9804 	struct amdgpu_framebuffer *afb;
9805 	int i = 0;
9806 
9807 	wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL);
9808 	if (!wb_info) {
9809 		DRM_ERROR("Failed to allocate wb_info\n");
9810 		return;
9811 	}
9812 
9813 	acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc);
9814 	if (!acrtc) {
9815 		DRM_ERROR("no amdgpu_crtc found\n");
9816 		kfree(wb_info);
9817 		return;
9818 	}
9819 
9820 	afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb);
9821 	if (!afb) {
9822 		DRM_ERROR("No amdgpu_framebuffer found\n");
9823 		kfree(wb_info);
9824 		return;
9825 	}
9826 
9827 	for (i = 0; i < MAX_PIPES; i++) {
9828 		if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {
9829 			pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i];
9830 			break;
9831 		}
9832 	}
9833 
9834 	/* fill in wb_info */
9835 	wb_info->wb_enabled = true;
9836 
9837 	wb_info->dwb_pipe_inst = 0;
9838 	wb_info->dwb_params.dwbscl_black_color = 0;
9839 	wb_info->dwb_params.hdr_mult = 0x1F000;
9840 	wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS;
9841 	wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13;
9842 	wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC;
9843 	wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC;
9844 
9845 	/* width & height from crtc */
9846 	wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay;
9847 	wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay;
9848 	wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay;
9849 	wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay;
9850 
9851 	wb_info->dwb_params.cnv_params.crop_en = false;
9852 	wb_info->dwb_params.stereo_params.stereo_enabled = false;
9853 
9854 	wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff;	// 10 bits
9855 	wb_info->dwb_params.cnv_params.out_min_pix_val = 0;
9856 	wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB;
9857 	wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS;
9858 
9859 	wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444;
9860 
9861 	wb_info->dwb_params.capture_rate = dwb_capture_rate_0;
9862 
9863 	wb_info->dwb_params.scaler_taps.h_taps = 4;
9864 	wb_info->dwb_params.scaler_taps.v_taps = 4;
9865 	wb_info->dwb_params.scaler_taps.h_taps_c = 2;
9866 	wb_info->dwb_params.scaler_taps.v_taps_c = 2;
9867 	wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING;
9868 
9869 	wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0];
9870 	wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1];
9871 
9872 	for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) {
9873 		wb_info->mcif_buf_params.luma_address[i] = afb->address;
9874 		wb_info->mcif_buf_params.chroma_address[i] = 0;
9875 	}
9876 
9877 	wb_info->mcif_buf_params.p_vmid = 1;
9878 	if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) {
9879 		wb_info->mcif_warmup_params.start_address.quad_part = afb->address;
9880 		wb_info->mcif_warmup_params.region_size =
9881 			wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height;
9882 	}
9883 	wb_info->mcif_warmup_params.p_vmid = 1;
9884 	wb_info->writeback_source_plane = pipe->plane_state;
9885 
9886 	dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info);
9887 
9888 	acrtc->wb_pending = true;
9889 	acrtc->wb_conn = wb_conn;
9890 	drm_writeback_queue_job(wb_conn, new_con_state);
9891 }
9892 
9893 /**
9894  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
9895  * @state: The atomic state to commit
9896  *
9897  * This will tell DC to commit the constructed DC state from atomic_check,
9898  * programming the hardware. Any failures here implies a hardware failure, since
9899  * atomic check should have filtered anything non-kosher.
9900  */
amdgpu_dm_atomic_commit_tail(struct drm_atomic_state * state)9901 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
9902 {
9903 	struct drm_device *dev = state->dev;
9904 	struct amdgpu_device *adev = drm_to_adev(dev);
9905 	struct amdgpu_display_manager *dm = &adev->dm;
9906 	struct dm_atomic_state *dm_state;
9907 	struct dc_state *dc_state = NULL;
9908 	u32 i, j;
9909 	struct drm_crtc *crtc;
9910 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9911 	unsigned long flags;
9912 	bool wait_for_vblank = true;
9913 	struct drm_connector *connector;
9914 	struct drm_connector_state *old_con_state, *new_con_state;
9915 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9916 	int crtc_disable_count = 0;
9917 
9918 	trace_amdgpu_dm_atomic_commit_tail_begin(state);
9919 
9920 	drm_atomic_helper_update_legacy_modeset_state(dev, state);
9921 	drm_dp_mst_atomic_wait_for_dependencies(state);
9922 
9923 	dm_state = dm_atomic_get_new_state(state);
9924 	if (dm_state && dm_state->context) {
9925 		dc_state = dm_state->context;
9926 		amdgpu_dm_commit_streams(state, dc_state);
9927 	}
9928 
9929 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9930 		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9931 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9932 		struct amdgpu_dm_connector *aconnector;
9933 
9934 		if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
9935 			continue;
9936 
9937 		aconnector = to_amdgpu_dm_connector(connector);
9938 
9939 		if (!adev->dm.hdcp_workqueue)
9940 			continue;
9941 
9942 		pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
9943 
9944 		if (!connector)
9945 			continue;
9946 
9947 		pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
9948 			connector->index, connector->status, connector->dpms);
9949 		pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
9950 			old_con_state->content_protection, new_con_state->content_protection);
9951 
9952 		if (aconnector->dc_sink) {
9953 			if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
9954 				aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
9955 				pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
9956 				aconnector->dc_sink->edid_caps.display_name);
9957 			}
9958 		}
9959 
9960 		new_crtc_state = NULL;
9961 		old_crtc_state = NULL;
9962 
9963 		if (acrtc) {
9964 			new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
9965 			old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
9966 		}
9967 
9968 		if (old_crtc_state)
9969 			pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
9970 			old_crtc_state->enable,
9971 			old_crtc_state->active,
9972 			old_crtc_state->mode_changed,
9973 			old_crtc_state->active_changed,
9974 			old_crtc_state->connectors_changed);
9975 
9976 		if (new_crtc_state)
9977 			pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
9978 			new_crtc_state->enable,
9979 			new_crtc_state->active,
9980 			new_crtc_state->mode_changed,
9981 			new_crtc_state->active_changed,
9982 			new_crtc_state->connectors_changed);
9983 	}
9984 
9985 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9986 		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9987 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9988 		struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9989 
9990 		if (!adev->dm.hdcp_workqueue)
9991 			continue;
9992 
9993 		new_crtc_state = NULL;
9994 		old_crtc_state = NULL;
9995 
9996 		if (acrtc) {
9997 			new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
9998 			old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
9999 		}
10000 
10001 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10002 
10003 		if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
10004 		    connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
10005 			hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
10006 			new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
10007 			dm_new_con_state->update_hdcp = true;
10008 			continue;
10009 		}
10010 
10011 		if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
10012 											old_con_state, connector, adev->dm.hdcp_workqueue)) {
10013 			/* when display is unplugged from mst hub, connctor will
10014 			 * be destroyed within dm_dp_mst_connector_destroy. connector
10015 			 * hdcp perperties, like type, undesired, desired, enabled,
10016 			 * will be lost. So, save hdcp properties into hdcp_work within
10017 			 * amdgpu_dm_atomic_commit_tail. if the same display is
10018 			 * plugged back with same display index, its hdcp properties
10019 			 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
10020 			 */
10021 
10022 			bool enable_encryption = false;
10023 
10024 			if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
10025 				enable_encryption = true;
10026 
10027 			if (aconnector->dc_link && aconnector->dc_sink &&
10028 				aconnector->dc_link->type == dc_connection_mst_branch) {
10029 				struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
10030 				struct hdcp_workqueue *hdcp_w =
10031 					&hdcp_work[aconnector->dc_link->link_index];
10032 
10033 				hdcp_w->hdcp_content_type[connector->index] =
10034 					new_con_state->hdcp_content_type;
10035 				hdcp_w->content_protection[connector->index] =
10036 					new_con_state->content_protection;
10037 			}
10038 
10039 			if (new_crtc_state && new_crtc_state->mode_changed &&
10040 				new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
10041 				enable_encryption = true;
10042 
10043 			DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
10044 
10045 			if (aconnector->dc_link)
10046 				hdcp_update_display(
10047 					adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
10048 					new_con_state->hdcp_content_type, enable_encryption);
10049 		}
10050 	}
10051 
10052 	/* Handle connector state changes */
10053 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10054 		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10055 		struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10056 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10057 		struct dc_surface_update *dummy_updates;
10058 		struct dc_stream_update stream_update;
10059 		struct dc_info_packet hdr_packet;
10060 		struct dc_stream_status *status = NULL;
10061 		bool abm_changed, hdr_changed, scaling_changed;
10062 
10063 		memset(&stream_update, 0, sizeof(stream_update));
10064 
10065 		if (acrtc) {
10066 			new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
10067 			old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
10068 		}
10069 
10070 		/* Skip any modesets/resets */
10071 		if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
10072 			continue;
10073 
10074 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10075 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10076 
10077 		scaling_changed = is_scaling_state_different(dm_new_con_state,
10078 							     dm_old_con_state);
10079 
10080 		abm_changed = dm_new_crtc_state->abm_level !=
10081 			      dm_old_crtc_state->abm_level;
10082 
10083 		hdr_changed =
10084 			!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
10085 
10086 		if (!scaling_changed && !abm_changed && !hdr_changed)
10087 			continue;
10088 
10089 		stream_update.stream = dm_new_crtc_state->stream;
10090 		if (scaling_changed) {
10091 			update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
10092 					dm_new_con_state, dm_new_crtc_state->stream);
10093 
10094 			stream_update.src = dm_new_crtc_state->stream->src;
10095 			stream_update.dst = dm_new_crtc_state->stream->dst;
10096 		}
10097 
10098 		if (abm_changed) {
10099 			dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
10100 
10101 			stream_update.abm_level = &dm_new_crtc_state->abm_level;
10102 		}
10103 
10104 		if (hdr_changed) {
10105 			fill_hdr_info_packet(new_con_state, &hdr_packet);
10106 			stream_update.hdr_static_metadata = &hdr_packet;
10107 		}
10108 
10109 		status = dc_stream_get_status(dm_new_crtc_state->stream);
10110 
10111 		if (WARN_ON(!status))
10112 			continue;
10113 
10114 		WARN_ON(!status->plane_count);
10115 
10116 		/*
10117 		 * TODO: DC refuses to perform stream updates without a dc_surface_update.
10118 		 * Here we create an empty update on each plane.
10119 		 * To fix this, DC should permit updating only stream properties.
10120 		 */
10121 		dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);
10122 		if (!dummy_updates) {
10123 			DRM_ERROR("Failed to allocate memory for dummy_updates.\n");
10124 			continue;
10125 		}
10126 		for (j = 0; j < status->plane_count; j++)
10127 			dummy_updates[j].surface = status->plane_states[0];
10128 
10129 		sort(dummy_updates, status->plane_count,
10130 		     sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL);
10131 
10132 		mutex_lock(&dm->dc_lock);
10133 		dc_exit_ips_for_hw_access(dm->dc);
10134 		dc_update_planes_and_stream(dm->dc,
10135 					    dummy_updates,
10136 					    status->plane_count,
10137 					    dm_new_crtc_state->stream,
10138 					    &stream_update);
10139 		mutex_unlock(&dm->dc_lock);
10140 		kfree(dummy_updates);
10141 	}
10142 
10143 	/**
10144 	 * Enable interrupts for CRTCs that are newly enabled or went through
10145 	 * a modeset. It was intentionally deferred until after the front end
10146 	 * state was modified to wait until the OTG was on and so the IRQ
10147 	 * handlers didn't access stale or invalid state.
10148 	 */
10149 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10150 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
10151 #ifdef CONFIG_DEBUG_FS
10152 		enum amdgpu_dm_pipe_crc_source cur_crc_src;
10153 #endif
10154 		/* Count number of newly disabled CRTCs for dropping PM refs later. */
10155 		if (old_crtc_state->active && !new_crtc_state->active)
10156 			crtc_disable_count++;
10157 
10158 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10159 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10160 
10161 		/* For freesync config update on crtc state and params for irq */
10162 		update_stream_irq_parameters(dm, dm_new_crtc_state);
10163 
10164 #ifdef CONFIG_DEBUG_FS
10165 		spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
10166 		cur_crc_src = acrtc->dm_irq_params.crc_src;
10167 		spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
10168 #endif
10169 
10170 		if (new_crtc_state->active &&
10171 		    (!old_crtc_state->active ||
10172 		     drm_atomic_crtc_needs_modeset(new_crtc_state))) {
10173 			dc_stream_retain(dm_new_crtc_state->stream);
10174 			acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
10175 			manage_dm_interrupts(adev, acrtc, dm_new_crtc_state);
10176 		}
10177 		/* Handle vrr on->off / off->on transitions */
10178 		amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
10179 
10180 #ifdef CONFIG_DEBUG_FS
10181 		if (new_crtc_state->active &&
10182 		    (!old_crtc_state->active ||
10183 		     drm_atomic_crtc_needs_modeset(new_crtc_state))) {
10184 			/**
10185 			 * Frontend may have changed so reapply the CRC capture
10186 			 * settings for the stream.
10187 			 */
10188 			if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
10189 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
10190 				if (amdgpu_dm_crc_window_is_activated(crtc)) {
10191 					uint8_t cnt;
10192 					spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
10193 					for (cnt = 0; cnt < MAX_CRC_WINDOW_NUM; cnt++) {
10194 						if (acrtc->dm_irq_params.window_param[cnt].enable) {
10195 							acrtc->dm_irq_params.window_param[cnt].update_win = true;
10196 
10197 							/**
10198 							 * It takes 2 frames for HW to stably generate CRC when
10199 							 * resuming from suspend, so we set skip_frame_cnt 2.
10200 							 */
10201 							acrtc->dm_irq_params.window_param[cnt].skip_frame_cnt = 2;
10202 						}
10203 					}
10204 					spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
10205 				}
10206 #endif
10207 				if (amdgpu_dm_crtc_configure_crc_source(
10208 					crtc, dm_new_crtc_state, cur_crc_src))
10209 					drm_dbg_atomic(dev, "Failed to configure crc source");
10210 			}
10211 		}
10212 #endif
10213 	}
10214 
10215 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
10216 		if (new_crtc_state->async_flip)
10217 			wait_for_vblank = false;
10218 
10219 	/* update planes when needed per crtc*/
10220 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
10221 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10222 
10223 		if (dm_new_crtc_state->stream)
10224 			amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
10225 	}
10226 
10227 	/* Enable writeback */
10228 	for_each_new_connector_in_state(state, connector, new_con_state, i) {
10229 		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10230 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10231 
10232 		if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
10233 			continue;
10234 
10235 		if (!new_con_state->writeback_job)
10236 			continue;
10237 
10238 		new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
10239 
10240 		if (!new_crtc_state)
10241 			continue;
10242 
10243 		if (acrtc->wb_enabled)
10244 			continue;
10245 
10246 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10247 
10248 		dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state);
10249 		acrtc->wb_enabled = true;
10250 	}
10251 
10252 	/* Update audio instances for each connector. */
10253 	amdgpu_dm_commit_audio(dev, state);
10254 
10255 	/* restore the backlight level */
10256 	for (i = 0; i < dm->num_of_edps; i++) {
10257 		if (dm->backlight_dev[i] &&
10258 		    (dm->actual_brightness[i] != dm->brightness[i]))
10259 			amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
10260 	}
10261 
10262 	/*
10263 	 * send vblank event on all events not handled in flip and
10264 	 * mark consumed event for drm_atomic_helper_commit_hw_done
10265 	 */
10266 	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
10267 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10268 
10269 		if (new_crtc_state->event)
10270 			drm_send_event_locked(dev, &new_crtc_state->event->base);
10271 
10272 		new_crtc_state->event = NULL;
10273 	}
10274 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
10275 
10276 	/* Signal HW programming completion */
10277 	drm_atomic_helper_commit_hw_done(state);
10278 
10279 	if (wait_for_vblank)
10280 		drm_atomic_helper_wait_for_flip_done(dev, state);
10281 
10282 	drm_atomic_helper_cleanup_planes(dev, state);
10283 
10284 	/* Don't free the memory if we are hitting this as part of suspend.
10285 	 * This way we don't free any memory during suspend; see
10286 	 * amdgpu_bo_free_kernel().  The memory will be freed in the first
10287 	 * non-suspend modeset or when the driver is torn down.
10288 	 */
10289 	if (!adev->in_suspend) {
10290 		/* return the stolen vga memory back to VRAM */
10291 		if (!adev->mman.keep_stolen_vga_memory)
10292 			amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
10293 		amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
10294 	}
10295 
10296 	/*
10297 	 * Finally, drop a runtime PM reference for each newly disabled CRTC,
10298 	 * so we can put the GPU into runtime suspend if we're not driving any
10299 	 * displays anymore
10300 	 */
10301 	for (i = 0; i < crtc_disable_count; i++)
10302 		pm_runtime_put_autosuspend(dev->dev);
10303 	pm_runtime_mark_last_busy(dev->dev);
10304 
10305 	trace_amdgpu_dm_atomic_commit_tail_finish(state);
10306 }
10307 
dm_force_atomic_commit(struct drm_connector * connector)10308 static int dm_force_atomic_commit(struct drm_connector *connector)
10309 {
10310 	int ret = 0;
10311 	struct drm_device *ddev = connector->dev;
10312 	struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
10313 	struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
10314 	struct drm_plane *plane = disconnected_acrtc->base.primary;
10315 	struct drm_connector_state *conn_state;
10316 	struct drm_crtc_state *crtc_state;
10317 	struct drm_plane_state *plane_state;
10318 
10319 	if (!state)
10320 		return -ENOMEM;
10321 
10322 	state->acquire_ctx = ddev->mode_config.acquire_ctx;
10323 
10324 	/* Construct an atomic state to restore previous display setting */
10325 
10326 	/*
10327 	 * Attach connectors to drm_atomic_state
10328 	 */
10329 	conn_state = drm_atomic_get_connector_state(state, connector);
10330 
10331 	ret = PTR_ERR_OR_ZERO(conn_state);
10332 	if (ret)
10333 		goto out;
10334 
10335 	/* Attach crtc to drm_atomic_state*/
10336 	crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
10337 
10338 	ret = PTR_ERR_OR_ZERO(crtc_state);
10339 	if (ret)
10340 		goto out;
10341 
10342 	/* force a restore */
10343 	crtc_state->mode_changed = true;
10344 
10345 	/* Attach plane to drm_atomic_state */
10346 	plane_state = drm_atomic_get_plane_state(state, plane);
10347 
10348 	ret = PTR_ERR_OR_ZERO(plane_state);
10349 	if (ret)
10350 		goto out;
10351 
10352 	/* Call commit internally with the state we just constructed */
10353 	ret = drm_atomic_commit(state);
10354 
10355 out:
10356 	drm_atomic_state_put(state);
10357 	if (ret)
10358 		DRM_ERROR("Restoring old state failed with %i\n", ret);
10359 
10360 	return ret;
10361 }
10362 
10363 /*
10364  * This function handles all cases when set mode does not come upon hotplug.
10365  * This includes when a display is unplugged then plugged back into the
10366  * same port and when running without usermode desktop manager supprot
10367  */
dm_restore_drm_connector_state(struct drm_device * dev,struct drm_connector * connector)10368 void dm_restore_drm_connector_state(struct drm_device *dev,
10369 				    struct drm_connector *connector)
10370 {
10371 	struct amdgpu_dm_connector *aconnector;
10372 	struct amdgpu_crtc *disconnected_acrtc;
10373 	struct dm_crtc_state *acrtc_state;
10374 
10375 	if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
10376 		return;
10377 
10378 	aconnector = to_amdgpu_dm_connector(connector);
10379 
10380 	if (!aconnector->dc_sink || !connector->state || !connector->encoder)
10381 		return;
10382 
10383 	disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
10384 	if (!disconnected_acrtc)
10385 		return;
10386 
10387 	acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
10388 	if (!acrtc_state->stream)
10389 		return;
10390 
10391 	/*
10392 	 * If the previous sink is not released and different from the current,
10393 	 * we deduce we are in a state where we can not rely on usermode call
10394 	 * to turn on the display, so we do it here
10395 	 */
10396 	if (acrtc_state->stream->sink != aconnector->dc_sink)
10397 		dm_force_atomic_commit(&aconnector->base);
10398 }
10399 
10400 /*
10401  * Grabs all modesetting locks to serialize against any blocking commits,
10402  * Waits for completion of all non blocking commits.
10403  */
do_aquire_global_lock(struct drm_device * dev,struct drm_atomic_state * state)10404 static int do_aquire_global_lock(struct drm_device *dev,
10405 				 struct drm_atomic_state *state)
10406 {
10407 	struct drm_crtc *crtc;
10408 	struct drm_crtc_commit *commit;
10409 	long ret;
10410 
10411 	/*
10412 	 * Adding all modeset locks to aquire_ctx will
10413 	 * ensure that when the framework release it the
10414 	 * extra locks we are locking here will get released to
10415 	 */
10416 	ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
10417 	if (ret)
10418 		return ret;
10419 
10420 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10421 		spin_lock(&crtc->commit_lock);
10422 		commit = list_first_entry_or_null(&crtc->commit_list,
10423 				struct drm_crtc_commit, commit_entry);
10424 		if (commit)
10425 			drm_crtc_commit_get(commit);
10426 		spin_unlock(&crtc->commit_lock);
10427 
10428 		if (!commit)
10429 			continue;
10430 
10431 		/*
10432 		 * Make sure all pending HW programming completed and
10433 		 * page flips done
10434 		 */
10435 		ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
10436 
10437 		if (ret > 0)
10438 			ret = wait_for_completion_interruptible_timeout(
10439 					&commit->flip_done, 10*HZ);
10440 
10441 		if (ret == 0)
10442 			DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",
10443 				  crtc->base.id, crtc->name);
10444 
10445 		drm_crtc_commit_put(commit);
10446 	}
10447 
10448 	return ret < 0 ? ret : 0;
10449 }
10450 
get_freesync_config_for_crtc(struct dm_crtc_state * new_crtc_state,struct dm_connector_state * new_con_state)10451 static void get_freesync_config_for_crtc(
10452 	struct dm_crtc_state *new_crtc_state,
10453 	struct dm_connector_state *new_con_state)
10454 {
10455 	struct mod_freesync_config config = {0};
10456 	struct amdgpu_dm_connector *aconnector;
10457 	struct drm_display_mode *mode = &new_crtc_state->base.mode;
10458 	int vrefresh = drm_mode_vrefresh(mode);
10459 	bool fs_vid_mode = false;
10460 
10461 	if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
10462 		return;
10463 
10464 	aconnector = to_amdgpu_dm_connector(new_con_state->base.connector);
10465 
10466 	new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
10467 					vrefresh >= aconnector->min_vfreq &&
10468 					vrefresh <= aconnector->max_vfreq;
10469 
10470 	if (new_crtc_state->vrr_supported) {
10471 		new_crtc_state->stream->ignore_msa_timing_param = true;
10472 		fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
10473 
10474 		config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
10475 		config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
10476 		config.vsif_supported = true;
10477 		config.btr = true;
10478 
10479 		if (fs_vid_mode) {
10480 			config.state = VRR_STATE_ACTIVE_FIXED;
10481 			config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
10482 			goto out;
10483 		} else if (new_crtc_state->base.vrr_enabled) {
10484 			config.state = VRR_STATE_ACTIVE_VARIABLE;
10485 		} else {
10486 			config.state = VRR_STATE_INACTIVE;
10487 		}
10488 	}
10489 out:
10490 	new_crtc_state->freesync_config = config;
10491 }
10492 
reset_freesync_config_for_crtc(struct dm_crtc_state * new_crtc_state)10493 static void reset_freesync_config_for_crtc(
10494 	struct dm_crtc_state *new_crtc_state)
10495 {
10496 	new_crtc_state->vrr_supported = false;
10497 
10498 	memset(&new_crtc_state->vrr_infopacket, 0,
10499 	       sizeof(new_crtc_state->vrr_infopacket));
10500 }
10501 
10502 static bool
is_timing_unchanged_for_freesync(struct drm_crtc_state * old_crtc_state,struct drm_crtc_state * new_crtc_state)10503 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
10504 				 struct drm_crtc_state *new_crtc_state)
10505 {
10506 	const struct drm_display_mode *old_mode, *new_mode;
10507 
10508 	if (!old_crtc_state || !new_crtc_state)
10509 		return false;
10510 
10511 	old_mode = &old_crtc_state->mode;
10512 	new_mode = &new_crtc_state->mode;
10513 
10514 	if (old_mode->clock       == new_mode->clock &&
10515 	    old_mode->hdisplay    == new_mode->hdisplay &&
10516 	    old_mode->vdisplay    == new_mode->vdisplay &&
10517 	    old_mode->htotal      == new_mode->htotal &&
10518 	    old_mode->vtotal      != new_mode->vtotal &&
10519 	    old_mode->hsync_start == new_mode->hsync_start &&
10520 	    old_mode->vsync_start != new_mode->vsync_start &&
10521 	    old_mode->hsync_end   == new_mode->hsync_end &&
10522 	    old_mode->vsync_end   != new_mode->vsync_end &&
10523 	    old_mode->hskew       == new_mode->hskew &&
10524 	    old_mode->vscan       == new_mode->vscan &&
10525 	    (old_mode->vsync_end - old_mode->vsync_start) ==
10526 	    (new_mode->vsync_end - new_mode->vsync_start))
10527 		return true;
10528 
10529 	return false;
10530 }
10531 
set_freesync_fixed_config(struct dm_crtc_state * dm_new_crtc_state)10532 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
10533 {
10534 	u64 num, den, res;
10535 	struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
10536 
10537 	dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
10538 
10539 	num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
10540 	den = (unsigned long long)new_crtc_state->mode.htotal *
10541 	      (unsigned long long)new_crtc_state->mode.vtotal;
10542 
10543 	res = div_u64(num, den);
10544 	dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
10545 }
10546 
dm_update_crtc_state(struct amdgpu_display_manager * dm,struct drm_atomic_state * state,struct drm_crtc * crtc,struct drm_crtc_state * old_crtc_state,struct drm_crtc_state * new_crtc_state,bool enable,bool * lock_and_validation_needed)10547 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
10548 			 struct drm_atomic_state *state,
10549 			 struct drm_crtc *crtc,
10550 			 struct drm_crtc_state *old_crtc_state,
10551 			 struct drm_crtc_state *new_crtc_state,
10552 			 bool enable,
10553 			 bool *lock_and_validation_needed)
10554 {
10555 	struct dm_atomic_state *dm_state = NULL;
10556 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
10557 	struct dc_stream_state *new_stream;
10558 	int ret = 0;
10559 
10560 	/*
10561 	 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
10562 	 * update changed items
10563 	 */
10564 	struct amdgpu_crtc *acrtc = NULL;
10565 	struct drm_connector *connector = NULL;
10566 	struct amdgpu_dm_connector *aconnector = NULL;
10567 	struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
10568 	struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
10569 
10570 	new_stream = NULL;
10571 
10572 	dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10573 	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10574 	acrtc = to_amdgpu_crtc(crtc);
10575 	connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
10576 	if (connector)
10577 		aconnector = to_amdgpu_dm_connector(connector);
10578 
10579 	/* TODO This hack should go away */
10580 	if (connector && enable) {
10581 		/* Make sure fake sink is created in plug-in scenario */
10582 		drm_new_conn_state = drm_atomic_get_new_connector_state(state,
10583 									connector);
10584 		drm_old_conn_state = drm_atomic_get_old_connector_state(state,
10585 									connector);
10586 
10587 		if (IS_ERR(drm_new_conn_state)) {
10588 			ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
10589 			goto fail;
10590 		}
10591 
10592 		dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
10593 		dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
10594 
10595 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
10596 			goto skip_modeset;
10597 
10598 		new_stream = create_validate_stream_for_sink(aconnector,
10599 							     &new_crtc_state->mode,
10600 							     dm_new_conn_state,
10601 							     dm_old_crtc_state->stream);
10602 
10603 		/*
10604 		 * we can have no stream on ACTION_SET if a display
10605 		 * was disconnected during S3, in this case it is not an
10606 		 * error, the OS will be updated after detection, and
10607 		 * will do the right thing on next atomic commit
10608 		 */
10609 
10610 		if (!new_stream) {
10611 			DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
10612 					__func__, acrtc->base.base.id);
10613 			ret = -ENOMEM;
10614 			goto fail;
10615 		}
10616 
10617 		/*
10618 		 * TODO: Check VSDB bits to decide whether this should
10619 		 * be enabled or not.
10620 		 */
10621 		new_stream->triggered_crtc_reset.enabled =
10622 			dm->force_timing_sync;
10623 
10624 		dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
10625 
10626 		ret = fill_hdr_info_packet(drm_new_conn_state,
10627 					   &new_stream->hdr_static_metadata);
10628 		if (ret)
10629 			goto fail;
10630 
10631 		/*
10632 		 * If we already removed the old stream from the context
10633 		 * (and set the new stream to NULL) then we can't reuse
10634 		 * the old stream even if the stream and scaling are unchanged.
10635 		 * We'll hit the BUG_ON and black screen.
10636 		 *
10637 		 * TODO: Refactor this function to allow this check to work
10638 		 * in all conditions.
10639 		 */
10640 		if (amdgpu_freesync_vid_mode &&
10641 		    dm_new_crtc_state->stream &&
10642 		    is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
10643 			goto skip_modeset;
10644 
10645 		if (dm_new_crtc_state->stream &&
10646 		    dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
10647 		    dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
10648 			new_crtc_state->mode_changed = false;
10649 			DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
10650 					 new_crtc_state->mode_changed);
10651 		}
10652 	}
10653 
10654 	/* mode_changed flag may get updated above, need to check again */
10655 	if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
10656 		goto skip_modeset;
10657 
10658 	drm_dbg_state(state->dev,
10659 		"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
10660 		acrtc->crtc_id,
10661 		new_crtc_state->enable,
10662 		new_crtc_state->active,
10663 		new_crtc_state->planes_changed,
10664 		new_crtc_state->mode_changed,
10665 		new_crtc_state->active_changed,
10666 		new_crtc_state->connectors_changed);
10667 
10668 	/* Remove stream for any changed/disabled CRTC */
10669 	if (!enable) {
10670 
10671 		if (!dm_old_crtc_state->stream)
10672 			goto skip_modeset;
10673 
10674 		/* Unset freesync video if it was active before */
10675 		if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
10676 			dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
10677 			dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
10678 		}
10679 
10680 		/* Now check if we should set freesync video mode */
10681 		if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
10682 		    dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
10683 		    dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
10684 		    is_timing_unchanged_for_freesync(new_crtc_state,
10685 						     old_crtc_state)) {
10686 			new_crtc_state->mode_changed = false;
10687 			DRM_DEBUG_DRIVER(
10688 				"Mode change not required for front porch change, setting mode_changed to %d",
10689 				new_crtc_state->mode_changed);
10690 
10691 			set_freesync_fixed_config(dm_new_crtc_state);
10692 
10693 			goto skip_modeset;
10694 		} else if (amdgpu_freesync_vid_mode && aconnector &&
10695 			   is_freesync_video_mode(&new_crtc_state->mode,
10696 						  aconnector)) {
10697 			struct drm_display_mode *high_mode;
10698 
10699 			high_mode = get_highest_refresh_rate_mode(aconnector, false);
10700 			if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
10701 				set_freesync_fixed_config(dm_new_crtc_state);
10702 		}
10703 
10704 		ret = dm_atomic_get_state(state, &dm_state);
10705 		if (ret)
10706 			goto fail;
10707 
10708 		DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
10709 				crtc->base.id);
10710 
10711 		/* i.e. reset mode */
10712 		if (dc_state_remove_stream(
10713 				dm->dc,
10714 				dm_state->context,
10715 				dm_old_crtc_state->stream) != DC_OK) {
10716 			ret = -EINVAL;
10717 			goto fail;
10718 		}
10719 
10720 		dc_stream_release(dm_old_crtc_state->stream);
10721 		dm_new_crtc_state->stream = NULL;
10722 
10723 		reset_freesync_config_for_crtc(dm_new_crtc_state);
10724 
10725 		*lock_and_validation_needed = true;
10726 
10727 	} else {/* Add stream for any updated/enabled CRTC */
10728 		/*
10729 		 * Quick fix to prevent NULL pointer on new_stream when
10730 		 * added MST connectors not found in existing crtc_state in the chained mode
10731 		 * TODO: need to dig out the root cause of that
10732 		 */
10733 		if (!connector)
10734 			goto skip_modeset;
10735 
10736 		if (modereset_required(new_crtc_state))
10737 			goto skip_modeset;
10738 
10739 		if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
10740 				     dm_old_crtc_state->stream)) {
10741 
10742 			WARN_ON(dm_new_crtc_state->stream);
10743 
10744 			ret = dm_atomic_get_state(state, &dm_state);
10745 			if (ret)
10746 				goto fail;
10747 
10748 			dm_new_crtc_state->stream = new_stream;
10749 
10750 			dc_stream_retain(new_stream);
10751 
10752 			DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
10753 					 crtc->base.id);
10754 
10755 			if (dc_state_add_stream(
10756 					dm->dc,
10757 					dm_state->context,
10758 					dm_new_crtc_state->stream) != DC_OK) {
10759 				ret = -EINVAL;
10760 				goto fail;
10761 			}
10762 
10763 			*lock_and_validation_needed = true;
10764 		}
10765 	}
10766 
10767 skip_modeset:
10768 	/* Release extra reference */
10769 	if (new_stream)
10770 		dc_stream_release(new_stream);
10771 
10772 	/*
10773 	 * We want to do dc stream updates that do not require a
10774 	 * full modeset below.
10775 	 */
10776 	if (!(enable && connector && new_crtc_state->active))
10777 		return 0;
10778 	/*
10779 	 * Given above conditions, the dc state cannot be NULL because:
10780 	 * 1. We're in the process of enabling CRTCs (just been added
10781 	 *    to the dc context, or already is on the context)
10782 	 * 2. Has a valid connector attached, and
10783 	 * 3. Is currently active and enabled.
10784 	 * => The dc stream state currently exists.
10785 	 */
10786 	BUG_ON(dm_new_crtc_state->stream == NULL);
10787 
10788 	/* Scaling or underscan settings */
10789 	if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
10790 				drm_atomic_crtc_needs_modeset(new_crtc_state))
10791 		update_stream_scaling_settings(
10792 			&new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
10793 
10794 	/* ABM settings */
10795 	dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
10796 
10797 	/*
10798 	 * Color management settings. We also update color properties
10799 	 * when a modeset is needed, to ensure it gets reprogrammed.
10800 	 */
10801 	if (dm_new_crtc_state->base.color_mgmt_changed ||
10802 	    dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf ||
10803 	    drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10804 		ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
10805 		if (ret)
10806 			goto fail;
10807 	}
10808 
10809 	/* Update Freesync settings. */
10810 	get_freesync_config_for_crtc(dm_new_crtc_state,
10811 				     dm_new_conn_state);
10812 
10813 	return ret;
10814 
10815 fail:
10816 	if (new_stream)
10817 		dc_stream_release(new_stream);
10818 	return ret;
10819 }
10820 
should_reset_plane(struct drm_atomic_state * state,struct drm_plane * plane,struct drm_plane_state * old_plane_state,struct drm_plane_state * new_plane_state)10821 static bool should_reset_plane(struct drm_atomic_state *state,
10822 			       struct drm_plane *plane,
10823 			       struct drm_plane_state *old_plane_state,
10824 			       struct drm_plane_state *new_plane_state)
10825 {
10826 	struct drm_plane *other;
10827 	struct drm_plane_state *old_other_state, *new_other_state;
10828 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10829 	struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state;
10830 	struct amdgpu_device *adev = drm_to_adev(plane->dev);
10831 	int i;
10832 
10833 	/*
10834 	 * TODO: Remove this hack for all asics once it proves that the
10835 	 * fast updates works fine on DCN3.2+.
10836 	 */
10837 	if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) &&
10838 	    state->allow_modeset)
10839 		return true;
10840 
10841 	/* Exit early if we know that we're adding or removing the plane. */
10842 	if (old_plane_state->crtc != new_plane_state->crtc)
10843 		return true;
10844 
10845 	/* old crtc == new_crtc == NULL, plane not in context. */
10846 	if (!new_plane_state->crtc)
10847 		return false;
10848 
10849 	new_crtc_state =
10850 		drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
10851 	old_crtc_state =
10852 		drm_atomic_get_old_crtc_state(state, old_plane_state->crtc);
10853 
10854 	if (!new_crtc_state)
10855 		return true;
10856 
10857 	/*
10858 	 * A change in cursor mode means a new dc pipe needs to be acquired or
10859 	 * released from the state
10860 	 */
10861 	old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
10862 	new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
10863 	if (plane->type == DRM_PLANE_TYPE_CURSOR &&
10864 	    old_dm_crtc_state != NULL &&
10865 	    old_dm_crtc_state->cursor_mode != new_dm_crtc_state->cursor_mode) {
10866 		return true;
10867 	}
10868 
10869 	/* CRTC Degamma changes currently require us to recreate planes. */
10870 	if (new_crtc_state->color_mgmt_changed)
10871 		return true;
10872 
10873 	/*
10874 	 * On zpos change, planes need to be reordered by removing and re-adding
10875 	 * them one by one to the dc state, in order of descending zpos.
10876 	 *
10877 	 * TODO: We can likely skip bandwidth validation if the only thing that
10878 	 * changed about the plane was it'z z-ordering.
10879 	 */
10880 	if (old_plane_state->normalized_zpos != new_plane_state->normalized_zpos)
10881 		return true;
10882 
10883 	if (drm_atomic_crtc_needs_modeset(new_crtc_state))
10884 		return true;
10885 
10886 	/*
10887 	 * If there are any new primary or overlay planes being added or
10888 	 * removed then the z-order can potentially change. To ensure
10889 	 * correct z-order and pipe acquisition the current DC architecture
10890 	 * requires us to remove and recreate all existing planes.
10891 	 *
10892 	 * TODO: Come up with a more elegant solution for this.
10893 	 */
10894 	for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
10895 		struct amdgpu_framebuffer *old_afb, *new_afb;
10896 		struct dm_plane_state *dm_new_other_state, *dm_old_other_state;
10897 
10898 		dm_new_other_state = to_dm_plane_state(new_other_state);
10899 		dm_old_other_state = to_dm_plane_state(old_other_state);
10900 
10901 		if (other->type == DRM_PLANE_TYPE_CURSOR)
10902 			continue;
10903 
10904 		if (old_other_state->crtc != new_plane_state->crtc &&
10905 		    new_other_state->crtc != new_plane_state->crtc)
10906 			continue;
10907 
10908 		if (old_other_state->crtc != new_other_state->crtc)
10909 			return true;
10910 
10911 		/* Src/dst size and scaling updates. */
10912 		if (old_other_state->src_w != new_other_state->src_w ||
10913 		    old_other_state->src_h != new_other_state->src_h ||
10914 		    old_other_state->crtc_w != new_other_state->crtc_w ||
10915 		    old_other_state->crtc_h != new_other_state->crtc_h)
10916 			return true;
10917 
10918 		/* Rotation / mirroring updates. */
10919 		if (old_other_state->rotation != new_other_state->rotation)
10920 			return true;
10921 
10922 		/* Blending updates. */
10923 		if (old_other_state->pixel_blend_mode !=
10924 		    new_other_state->pixel_blend_mode)
10925 			return true;
10926 
10927 		/* Alpha updates. */
10928 		if (old_other_state->alpha != new_other_state->alpha)
10929 			return true;
10930 
10931 		/* Colorspace changes. */
10932 		if (old_other_state->color_range != new_other_state->color_range ||
10933 		    old_other_state->color_encoding != new_other_state->color_encoding)
10934 			return true;
10935 
10936 		/* HDR/Transfer Function changes. */
10937 		if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf ||
10938 		    dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut ||
10939 		    dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult ||
10940 		    dm_old_other_state->ctm != dm_new_other_state->ctm ||
10941 		    dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut ||
10942 		    dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf ||
10943 		    dm_old_other_state->lut3d != dm_new_other_state->lut3d ||
10944 		    dm_old_other_state->blend_lut != dm_new_other_state->blend_lut ||
10945 		    dm_old_other_state->blend_tf != dm_new_other_state->blend_tf)
10946 			return true;
10947 
10948 		/* Framebuffer checks fall at the end. */
10949 		if (!old_other_state->fb || !new_other_state->fb)
10950 			continue;
10951 
10952 		/* Pixel format changes can require bandwidth updates. */
10953 		if (old_other_state->fb->format != new_other_state->fb->format)
10954 			return true;
10955 
10956 		old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
10957 		new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
10958 
10959 		/* Tiling and DCC changes also require bandwidth updates. */
10960 		if (old_afb->tiling_flags != new_afb->tiling_flags ||
10961 		    old_afb->base.modifier != new_afb->base.modifier)
10962 			return true;
10963 	}
10964 
10965 	return false;
10966 }
10967 
dm_check_cursor_fb(struct amdgpu_crtc * new_acrtc,struct drm_plane_state * new_plane_state,struct drm_framebuffer * fb)10968 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
10969 			      struct drm_plane_state *new_plane_state,
10970 			      struct drm_framebuffer *fb)
10971 {
10972 	struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
10973 	struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
10974 	unsigned int pitch;
10975 	bool linear;
10976 
10977 	if (fb->width > new_acrtc->max_cursor_width ||
10978 	    fb->height > new_acrtc->max_cursor_height) {
10979 		DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
10980 				 new_plane_state->fb->width,
10981 				 new_plane_state->fb->height);
10982 		return -EINVAL;
10983 	}
10984 	if (new_plane_state->src_w != fb->width << 16 ||
10985 	    new_plane_state->src_h != fb->height << 16) {
10986 		DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
10987 		return -EINVAL;
10988 	}
10989 
10990 	/* Pitch in pixels */
10991 	pitch = fb->pitches[0] / fb->format->cpp[0];
10992 
10993 	if (fb->width != pitch) {
10994 		DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
10995 				 fb->width, pitch);
10996 		return -EINVAL;
10997 	}
10998 
10999 	switch (pitch) {
11000 	case 64:
11001 	case 128:
11002 	case 256:
11003 		/* FB pitch is supported by cursor plane */
11004 		break;
11005 	default:
11006 		DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
11007 		return -EINVAL;
11008 	}
11009 
11010 	/* Core DRM takes care of checking FB modifiers, so we only need to
11011 	 * check tiling flags when the FB doesn't have a modifier.
11012 	 */
11013 	if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
11014 		if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) {
11015 			linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0;
11016 		} else if (adev->family >= AMDGPU_FAMILY_AI) {
11017 			linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
11018 		} else {
11019 			linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
11020 				 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
11021 				 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
11022 		}
11023 		if (!linear) {
11024 			DRM_DEBUG_ATOMIC("Cursor FB not linear");
11025 			return -EINVAL;
11026 		}
11027 	}
11028 
11029 	return 0;
11030 }
11031 
11032 /*
11033  * Helper function for checking the cursor in native mode
11034  */
dm_check_native_cursor_state(struct drm_crtc * new_plane_crtc,struct drm_plane * plane,struct drm_plane_state * new_plane_state,bool enable)11035 static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc,
11036 					struct drm_plane *plane,
11037 					struct drm_plane_state *new_plane_state,
11038 					bool enable)
11039 {
11040 
11041 	struct amdgpu_crtc *new_acrtc;
11042 	int ret;
11043 
11044 	if (!enable || !new_plane_crtc ||
11045 	    drm_atomic_plane_disabling(plane->state, new_plane_state))
11046 		return 0;
11047 
11048 	new_acrtc = to_amdgpu_crtc(new_plane_crtc);
11049 
11050 	if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
11051 		DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
11052 		return -EINVAL;
11053 	}
11054 
11055 	if (new_plane_state->fb) {
11056 		ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
11057 						new_plane_state->fb);
11058 		if (ret)
11059 			return ret;
11060 	}
11061 
11062 	return 0;
11063 }
11064 
dm_should_update_native_cursor(struct drm_atomic_state * state,struct drm_crtc * old_plane_crtc,struct drm_crtc * new_plane_crtc,bool enable)11065 static bool dm_should_update_native_cursor(struct drm_atomic_state *state,
11066 					   struct drm_crtc *old_plane_crtc,
11067 					   struct drm_crtc *new_plane_crtc,
11068 					   bool enable)
11069 {
11070 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11071 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
11072 
11073 	if (!enable) {
11074 		if (old_plane_crtc == NULL)
11075 			return true;
11076 
11077 		old_crtc_state = drm_atomic_get_old_crtc_state(
11078 			state, old_plane_crtc);
11079 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
11080 
11081 		return dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE;
11082 	} else {
11083 		if (new_plane_crtc == NULL)
11084 			return true;
11085 
11086 		new_crtc_state = drm_atomic_get_new_crtc_state(
11087 			state, new_plane_crtc);
11088 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
11089 
11090 		return dm_new_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE;
11091 	}
11092 }
11093 
dm_update_plane_state(struct dc * dc,struct drm_atomic_state * state,struct drm_plane * plane,struct drm_plane_state * old_plane_state,struct drm_plane_state * new_plane_state,bool enable,bool * lock_and_validation_needed,bool * is_top_most_overlay)11094 static int dm_update_plane_state(struct dc *dc,
11095 				 struct drm_atomic_state *state,
11096 				 struct drm_plane *plane,
11097 				 struct drm_plane_state *old_plane_state,
11098 				 struct drm_plane_state *new_plane_state,
11099 				 bool enable,
11100 				 bool *lock_and_validation_needed,
11101 				 bool *is_top_most_overlay)
11102 {
11103 
11104 	struct dm_atomic_state *dm_state = NULL;
11105 	struct drm_crtc *new_plane_crtc, *old_plane_crtc;
11106 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11107 	struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
11108 	struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
11109 	bool needs_reset, update_native_cursor;
11110 	int ret = 0;
11111 
11112 
11113 	new_plane_crtc = new_plane_state->crtc;
11114 	old_plane_crtc = old_plane_state->crtc;
11115 	dm_new_plane_state = to_dm_plane_state(new_plane_state);
11116 	dm_old_plane_state = to_dm_plane_state(old_plane_state);
11117 
11118 	update_native_cursor = dm_should_update_native_cursor(state,
11119 							      old_plane_crtc,
11120 							      new_plane_crtc,
11121 							      enable);
11122 
11123 	if (plane->type == DRM_PLANE_TYPE_CURSOR && update_native_cursor) {
11124 		ret = dm_check_native_cursor_state(new_plane_crtc, plane,
11125 						    new_plane_state, enable);
11126 		if (ret)
11127 			return ret;
11128 
11129 		return 0;
11130 	}
11131 
11132 	needs_reset = should_reset_plane(state, plane, old_plane_state,
11133 					 new_plane_state);
11134 
11135 	/* Remove any changed/removed planes */
11136 	if (!enable) {
11137 		if (!needs_reset)
11138 			return 0;
11139 
11140 		if (!old_plane_crtc)
11141 			return 0;
11142 
11143 		old_crtc_state = drm_atomic_get_old_crtc_state(
11144 				state, old_plane_crtc);
11145 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
11146 
11147 		if (!dm_old_crtc_state->stream)
11148 			return 0;
11149 
11150 		DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
11151 				plane->base.id, old_plane_crtc->base.id);
11152 
11153 		ret = dm_atomic_get_state(state, &dm_state);
11154 		if (ret)
11155 			return ret;
11156 
11157 		if (!dc_state_remove_plane(
11158 				dc,
11159 				dm_old_crtc_state->stream,
11160 				dm_old_plane_state->dc_state,
11161 				dm_state->context)) {
11162 
11163 			return -EINVAL;
11164 		}
11165 
11166 		if (dm_old_plane_state->dc_state)
11167 			dc_plane_state_release(dm_old_plane_state->dc_state);
11168 
11169 		dm_new_plane_state->dc_state = NULL;
11170 
11171 		*lock_and_validation_needed = true;
11172 
11173 	} else { /* Add new planes */
11174 		struct dc_plane_state *dc_new_plane_state;
11175 
11176 		if (drm_atomic_plane_disabling(plane->state, new_plane_state))
11177 			return 0;
11178 
11179 		if (!new_plane_crtc)
11180 			return 0;
11181 
11182 		new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
11183 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
11184 
11185 		if (!dm_new_crtc_state->stream)
11186 			return 0;
11187 
11188 		if (!needs_reset)
11189 			return 0;
11190 
11191 		ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
11192 		if (ret)
11193 			goto out;
11194 
11195 		WARN_ON(dm_new_plane_state->dc_state);
11196 
11197 		dc_new_plane_state = dc_create_plane_state(dc);
11198 		if (!dc_new_plane_state) {
11199 			ret = -ENOMEM;
11200 			goto out;
11201 		}
11202 
11203 		DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
11204 				 plane->base.id, new_plane_crtc->base.id);
11205 
11206 		ret = fill_dc_plane_attributes(
11207 			drm_to_adev(new_plane_crtc->dev),
11208 			dc_new_plane_state,
11209 			new_plane_state,
11210 			new_crtc_state);
11211 		if (ret) {
11212 			dc_plane_state_release(dc_new_plane_state);
11213 			goto out;
11214 		}
11215 
11216 		ret = dm_atomic_get_state(state, &dm_state);
11217 		if (ret) {
11218 			dc_plane_state_release(dc_new_plane_state);
11219 			goto out;
11220 		}
11221 
11222 		/*
11223 		 * Any atomic check errors that occur after this will
11224 		 * not need a release. The plane state will be attached
11225 		 * to the stream, and therefore part of the atomic
11226 		 * state. It'll be released when the atomic state is
11227 		 * cleaned.
11228 		 */
11229 		if (!dc_state_add_plane(
11230 				dc,
11231 				dm_new_crtc_state->stream,
11232 				dc_new_plane_state,
11233 				dm_state->context)) {
11234 
11235 			dc_plane_state_release(dc_new_plane_state);
11236 			ret = -EINVAL;
11237 			goto out;
11238 		}
11239 
11240 		dm_new_plane_state->dc_state = dc_new_plane_state;
11241 
11242 		dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
11243 
11244 		/* Tell DC to do a full surface update every time there
11245 		 * is a plane change. Inefficient, but works for now.
11246 		 */
11247 		dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
11248 
11249 		*lock_and_validation_needed = true;
11250 	}
11251 
11252 out:
11253 	/* If enabling cursor overlay failed, attempt fallback to native mode */
11254 	if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) {
11255 		ret = dm_check_native_cursor_state(new_plane_crtc, plane,
11256 						    new_plane_state, enable);
11257 		if (ret)
11258 			return ret;
11259 
11260 		dm_new_crtc_state->cursor_mode = DM_CURSOR_NATIVE_MODE;
11261 	}
11262 
11263 	return ret;
11264 }
11265 
dm_get_oriented_plane_size(struct drm_plane_state * plane_state,int * src_w,int * src_h)11266 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
11267 				       int *src_w, int *src_h)
11268 {
11269 	switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
11270 	case DRM_MODE_ROTATE_90:
11271 	case DRM_MODE_ROTATE_270:
11272 		*src_w = plane_state->src_h >> 16;
11273 		*src_h = plane_state->src_w >> 16;
11274 		break;
11275 	case DRM_MODE_ROTATE_0:
11276 	case DRM_MODE_ROTATE_180:
11277 	default:
11278 		*src_w = plane_state->src_w >> 16;
11279 		*src_h = plane_state->src_h >> 16;
11280 		break;
11281 	}
11282 }
11283 
11284 static void
dm_get_plane_scale(struct drm_plane_state * plane_state,int * out_plane_scale_w,int * out_plane_scale_h)11285 dm_get_plane_scale(struct drm_plane_state *plane_state,
11286 		   int *out_plane_scale_w, int *out_plane_scale_h)
11287 {
11288 	int plane_src_w, plane_src_h;
11289 
11290 	dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);
11291 	*out_plane_scale_w = plane_src_w ? plane_state->crtc_w * 1000 / plane_src_w : 0;
11292 	*out_plane_scale_h = plane_src_h ? plane_state->crtc_h * 1000 / plane_src_h : 0;
11293 }
11294 
11295 /*
11296  * The normalized_zpos value cannot be used by this iterator directly. It's only
11297  * calculated for enabled planes, potentially causing normalized_zpos collisions
11298  * between enabled/disabled planes in the atomic state. We need a unique value
11299  * so that the iterator will not generate the same object twice, or loop
11300  * indefinitely.
11301  */
__get_next_zpos(struct drm_atomic_state * state,struct __drm_planes_state * prev)11302 static inline struct __drm_planes_state *__get_next_zpos(
11303 	struct drm_atomic_state *state,
11304 	struct __drm_planes_state *prev)
11305 {
11306 	unsigned int highest_zpos = 0, prev_zpos = 256;
11307 	uint32_t highest_id = 0, prev_id = UINT_MAX;
11308 	struct drm_plane_state *new_plane_state;
11309 	struct drm_plane *plane;
11310 	int i, highest_i = -1;
11311 
11312 	if (prev != NULL) {
11313 		prev_zpos = prev->new_state->zpos;
11314 		prev_id = prev->ptr->base.id;
11315 	}
11316 
11317 	for_each_new_plane_in_state(state, plane, new_plane_state, i) {
11318 		/* Skip planes with higher zpos than the previously returned */
11319 		if (new_plane_state->zpos > prev_zpos ||
11320 		    (new_plane_state->zpos == prev_zpos &&
11321 		     plane->base.id >= prev_id))
11322 			continue;
11323 
11324 		/* Save the index of the plane with highest zpos */
11325 		if (new_plane_state->zpos > highest_zpos ||
11326 		    (new_plane_state->zpos == highest_zpos &&
11327 		     plane->base.id > highest_id)) {
11328 			highest_zpos = new_plane_state->zpos;
11329 			highest_id = plane->base.id;
11330 			highest_i = i;
11331 		}
11332 	}
11333 
11334 	if (highest_i < 0)
11335 		return NULL;
11336 
11337 	return &state->planes[highest_i];
11338 }
11339 
11340 /*
11341  * Use the uniqueness of the plane's (zpos, drm obj ID) combination to iterate
11342  * by descending zpos, as read from the new plane state. This is the same
11343  * ordering as defined by drm_atomic_normalize_zpos().
11344  */
11345 #define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) \
11346 	for (struct __drm_planes_state *__i = __get_next_zpos((__state), NULL); \
11347 	     __i != NULL; __i = __get_next_zpos((__state), __i))		\
11348 		for_each_if(((plane) = __i->ptr,				\
11349 			     (void)(plane) /* Only to avoid unused-but-set-variable warning */, \
11350 			     (old_plane_state) = __i->old_state,		\
11351 			     (new_plane_state) = __i->new_state, 1))
11352 
add_affected_mst_dsc_crtcs(struct drm_atomic_state * state,struct drm_crtc * crtc)11353 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
11354 {
11355 	struct drm_connector *connector;
11356 	struct drm_connector_state *conn_state, *old_conn_state;
11357 	struct amdgpu_dm_connector *aconnector = NULL;
11358 	int i;
11359 
11360 	for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
11361 		if (!conn_state->crtc)
11362 			conn_state = old_conn_state;
11363 
11364 		if (conn_state->crtc != crtc)
11365 			continue;
11366 
11367 		if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
11368 			continue;
11369 
11370 		aconnector = to_amdgpu_dm_connector(connector);
11371 		if (!aconnector->mst_output_port || !aconnector->mst_root)
11372 			aconnector = NULL;
11373 		else
11374 			break;
11375 	}
11376 
11377 	if (!aconnector)
11378 		return 0;
11379 
11380 	return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
11381 }
11382 
11383 /**
11384  * DOC: Cursor Modes - Native vs Overlay
11385  *
11386  * In native mode, the cursor uses a integrated cursor pipe within each DCN hw
11387  * plane. It does not require a dedicated hw plane to enable, but it is
11388  * subjected to the same z-order and scaling as the hw plane. It also has format
11389  * restrictions, a RGB cursor in native mode cannot be enabled within a non-RGB
11390  * hw plane.
11391  *
11392  * In overlay mode, the cursor uses a separate DCN hw plane, and thus has its
11393  * own scaling and z-pos. It also has no blending restrictions. It lends to a
11394  * cursor behavior more akin to a DRM client's expectations. However, it does
11395  * occupy an extra DCN plane, and therefore will only be used if a DCN plane is
11396  * available.
11397  */
11398 
11399 /**
11400  * dm_crtc_get_cursor_mode() - Determine the required cursor mode on crtc
11401  * @adev: amdgpu device
11402  * @state: DRM atomic state
11403  * @dm_crtc_state: amdgpu state for the CRTC containing the cursor
11404  * @cursor_mode: Returns the required cursor mode on dm_crtc_state
11405  *
11406  * Get whether the cursor should be enabled in native mode, or overlay mode, on
11407  * the dm_crtc_state.
11408  *
11409  * The cursor should be enabled in overlay mode if there exists an underlying
11410  * plane - on which the cursor may be blended - that is either YUV formatted, or
11411  * scaled differently from the cursor.
11412  *
11413  * Since zpos info is required, drm_atomic_normalize_zpos must be called before
11414  * calling this function.
11415  *
11416  * Return: 0 on success, or an error code if getting the cursor plane state
11417  * failed.
11418  */
dm_crtc_get_cursor_mode(struct amdgpu_device * adev,struct drm_atomic_state * state,struct dm_crtc_state * dm_crtc_state,enum amdgpu_dm_cursor_mode * cursor_mode)11419 static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev,
11420 				   struct drm_atomic_state *state,
11421 				   struct dm_crtc_state *dm_crtc_state,
11422 				   enum amdgpu_dm_cursor_mode *cursor_mode)
11423 {
11424 	struct drm_plane_state *old_plane_state, *plane_state, *cursor_state;
11425 	struct drm_crtc_state *crtc_state = &dm_crtc_state->base;
11426 	struct drm_plane *plane;
11427 	bool consider_mode_change = false;
11428 	bool entire_crtc_covered = false;
11429 	bool cursor_changed = false;
11430 	int underlying_scale_w, underlying_scale_h;
11431 	int cursor_scale_w, cursor_scale_h;
11432 	int i;
11433 
11434 	/* Overlay cursor not supported on HW before DCN
11435 	 * DCN401 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions
11436 	 * as previous DCN generations, so enable native mode on DCN401 in addition to DCE
11437 	 */
11438 	if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0 ||
11439 	    amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) {
11440 		*cursor_mode = DM_CURSOR_NATIVE_MODE;
11441 		return 0;
11442 	}
11443 
11444 	/* Init cursor_mode to be the same as current */
11445 	*cursor_mode = dm_crtc_state->cursor_mode;
11446 
11447 	/*
11448 	 * Cursor mode can change if a plane's format changes, scale changes, is
11449 	 * enabled/disabled, or z-order changes.
11450 	 */
11451 	for_each_oldnew_plane_in_state(state, plane, old_plane_state, plane_state, i) {
11452 		int new_scale_w, new_scale_h, old_scale_w, old_scale_h;
11453 
11454 		/* Only care about planes on this CRTC */
11455 		if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0)
11456 			continue;
11457 
11458 		if (plane->type == DRM_PLANE_TYPE_CURSOR)
11459 			cursor_changed = true;
11460 
11461 		if (drm_atomic_plane_enabling(old_plane_state, plane_state) ||
11462 		    drm_atomic_plane_disabling(old_plane_state, plane_state) ||
11463 		    old_plane_state->fb->format != plane_state->fb->format) {
11464 			consider_mode_change = true;
11465 			break;
11466 		}
11467 
11468 		dm_get_plane_scale(plane_state, &new_scale_w, &new_scale_h);
11469 		dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);
11470 		if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {
11471 			consider_mode_change = true;
11472 			break;
11473 		}
11474 	}
11475 
11476 	if (!consider_mode_change && !crtc_state->zpos_changed)
11477 		return 0;
11478 
11479 	/*
11480 	 * If no cursor change on this CRTC, and not enabled on this CRTC, then
11481 	 * no need to set cursor mode. This avoids needlessly locking the cursor
11482 	 * state.
11483 	 */
11484 	if (!cursor_changed &&
11485 	    !(drm_plane_mask(crtc_state->crtc->cursor) & crtc_state->plane_mask)) {
11486 		return 0;
11487 	}
11488 
11489 	cursor_state = drm_atomic_get_plane_state(state,
11490 						  crtc_state->crtc->cursor);
11491 	if (IS_ERR(cursor_state))
11492 		return PTR_ERR(cursor_state);
11493 
11494 	/* Cursor is disabled */
11495 	if (!cursor_state->fb)
11496 		return 0;
11497 
11498 	/* For all planes in descending z-order (all of which are below cursor
11499 	 * as per zpos definitions), check their scaling and format
11500 	 */
11501 	for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, plane_state) {
11502 
11503 		/* Only care about non-cursor planes on this CRTC */
11504 		if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0 ||
11505 		    plane->type == DRM_PLANE_TYPE_CURSOR)
11506 			continue;
11507 
11508 		/* Underlying plane is YUV format - use overlay cursor */
11509 		if (amdgpu_dm_plane_is_video_format(plane_state->fb->format->format)) {
11510 			*cursor_mode = DM_CURSOR_OVERLAY_MODE;
11511 			return 0;
11512 		}
11513 
11514 		dm_get_plane_scale(plane_state,
11515 				   &underlying_scale_w, &underlying_scale_h);
11516 		dm_get_plane_scale(cursor_state,
11517 				   &cursor_scale_w, &cursor_scale_h);
11518 
11519 		/* Underlying plane has different scale - use overlay cursor */
11520 		if (cursor_scale_w != underlying_scale_w &&
11521 		    cursor_scale_h != underlying_scale_h) {
11522 			*cursor_mode = DM_CURSOR_OVERLAY_MODE;
11523 			return 0;
11524 		}
11525 
11526 		/* If this plane covers the whole CRTC, no need to check planes underneath */
11527 		if (plane_state->crtc_x <= 0 && plane_state->crtc_y <= 0 &&
11528 		    plane_state->crtc_x + plane_state->crtc_w >= crtc_state->mode.hdisplay &&
11529 		    plane_state->crtc_y + plane_state->crtc_h >= crtc_state->mode.vdisplay) {
11530 			entire_crtc_covered = true;
11531 			break;
11532 		}
11533 	}
11534 
11535 	/* If planes do not cover the entire CRTC, use overlay mode to enable
11536 	 * cursor over holes
11537 	 */
11538 	if (entire_crtc_covered)
11539 		*cursor_mode = DM_CURSOR_NATIVE_MODE;
11540 	else
11541 		*cursor_mode = DM_CURSOR_OVERLAY_MODE;
11542 
11543 	return 0;
11544 }
11545 
amdgpu_dm_crtc_mem_type_changed(struct drm_device * dev,struct drm_atomic_state * state,struct drm_crtc_state * crtc_state)11546 static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev,
11547 					    struct drm_atomic_state *state,
11548 					    struct drm_crtc_state *crtc_state)
11549 {
11550 	struct drm_plane *plane;
11551 	struct drm_plane_state *new_plane_state, *old_plane_state;
11552 
11553 	drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) {
11554 		new_plane_state = drm_atomic_get_plane_state(state, plane);
11555 		old_plane_state = drm_atomic_get_plane_state(state, plane);
11556 
11557 		if (IS_ERR(new_plane_state) || IS_ERR(old_plane_state)) {
11558 			DRM_ERROR("Failed to get plane state for plane %s\n", plane->name);
11559 			return false;
11560 		}
11561 
11562 		if (old_plane_state->fb && new_plane_state->fb &&
11563 		    get_mem_type(old_plane_state->fb) != get_mem_type(new_plane_state->fb))
11564 			return true;
11565 	}
11566 
11567 	return false;
11568 }
11569 
11570 /**
11571  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
11572  *
11573  * @dev: The DRM device
11574  * @state: The atomic state to commit
11575  *
11576  * Validate that the given atomic state is programmable by DC into hardware.
11577  * This involves constructing a &struct dc_state reflecting the new hardware
11578  * state we wish to commit, then querying DC to see if it is programmable. It's
11579  * important not to modify the existing DC state. Otherwise, atomic_check
11580  * may unexpectedly commit hardware changes.
11581  *
11582  * When validating the DC state, it's important that the right locks are
11583  * acquired. For full updates case which removes/adds/updates streams on one
11584  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
11585  * that any such full update commit will wait for completion of any outstanding
11586  * flip using DRMs synchronization events.
11587  *
11588  * Note that DM adds the affected connectors for all CRTCs in state, when that
11589  * might not seem necessary. This is because DC stream creation requires the
11590  * DC sink, which is tied to the DRM connector state. Cleaning this up should
11591  * be possible but non-trivial - a possible TODO item.
11592  *
11593  * Return: -Error code if validation failed.
11594  */
amdgpu_dm_atomic_check(struct drm_device * dev,struct drm_atomic_state * state)11595 static int amdgpu_dm_atomic_check(struct drm_device *dev,
11596 				  struct drm_atomic_state *state)
11597 {
11598 	struct amdgpu_device *adev = drm_to_adev(dev);
11599 	struct dm_atomic_state *dm_state = NULL;
11600 	struct dc *dc = adev->dm.dc;
11601 	struct drm_connector *connector;
11602 	struct drm_connector_state *old_con_state, *new_con_state;
11603 	struct drm_crtc *crtc;
11604 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11605 	struct drm_plane *plane;
11606 	struct drm_plane_state *old_plane_state, *new_plane_state, *new_cursor_state;
11607 	enum dc_status status;
11608 	int ret, i;
11609 	bool lock_and_validation_needed = false;
11610 	bool is_top_most_overlay = true;
11611 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
11612 	struct drm_dp_mst_topology_mgr *mgr;
11613 	struct drm_dp_mst_topology_state *mst_state;
11614 	struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0};
11615 
11616 	trace_amdgpu_dm_atomic_check_begin(state);
11617 
11618 	ret = drm_atomic_helper_check_modeset(dev, state);
11619 	if (ret) {
11620 		drm_dbg_atomic(dev, "drm_atomic_helper_check_modeset() failed\n");
11621 		goto fail;
11622 	}
11623 
11624 	/* Check connector changes */
11625 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
11626 		struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
11627 		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
11628 
11629 		/* Skip connectors that are disabled or part of modeset already. */
11630 		if (!new_con_state->crtc)
11631 			continue;
11632 
11633 		new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
11634 		if (IS_ERR(new_crtc_state)) {
11635 			drm_dbg_atomic(dev, "drm_atomic_get_crtc_state() failed\n");
11636 			ret = PTR_ERR(new_crtc_state);
11637 			goto fail;
11638 		}
11639 
11640 		if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
11641 		    dm_old_con_state->scaling != dm_new_con_state->scaling)
11642 			new_crtc_state->connectors_changed = true;
11643 	}
11644 
11645 	if (dc_resource_is_dsc_encoding_supported(dc)) {
11646 		for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11647 			if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
11648 				ret = add_affected_mst_dsc_crtcs(state, crtc);
11649 				if (ret) {
11650 					drm_dbg_atomic(dev, "add_affected_mst_dsc_crtcs() failed\n");
11651 					goto fail;
11652 				}
11653 			}
11654 		}
11655 	}
11656 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11657 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
11658 
11659 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
11660 		    !new_crtc_state->color_mgmt_changed &&
11661 		    old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
11662 			dm_old_crtc_state->dsc_force_changed == false)
11663 			continue;
11664 
11665 		ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
11666 		if (ret) {
11667 			drm_dbg_atomic(dev, "amdgpu_dm_verify_lut_sizes() failed\n");
11668 			goto fail;
11669 		}
11670 
11671 		if (!new_crtc_state->enable)
11672 			continue;
11673 
11674 		ret = drm_atomic_add_affected_connectors(state, crtc);
11675 		if (ret) {
11676 			drm_dbg_atomic(dev, "drm_atomic_add_affected_connectors() failed\n");
11677 			goto fail;
11678 		}
11679 
11680 		ret = drm_atomic_add_affected_planes(state, crtc);
11681 		if (ret) {
11682 			drm_dbg_atomic(dev, "drm_atomic_add_affected_planes() failed\n");
11683 			goto fail;
11684 		}
11685 
11686 		if (dm_old_crtc_state->dsc_force_changed)
11687 			new_crtc_state->mode_changed = true;
11688 	}
11689 
11690 	/*
11691 	 * Add all primary and overlay planes on the CRTC to the state
11692 	 * whenever a plane is enabled to maintain correct z-ordering
11693 	 * and to enable fast surface updates.
11694 	 */
11695 	drm_for_each_crtc(crtc, dev) {
11696 		bool modified = false;
11697 
11698 		for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
11699 			if (plane->type == DRM_PLANE_TYPE_CURSOR)
11700 				continue;
11701 
11702 			if (new_plane_state->crtc == crtc ||
11703 			    old_plane_state->crtc == crtc) {
11704 				modified = true;
11705 				break;
11706 			}
11707 		}
11708 
11709 		if (!modified)
11710 			continue;
11711 
11712 		drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
11713 			if (plane->type == DRM_PLANE_TYPE_CURSOR)
11714 				continue;
11715 
11716 			new_plane_state =
11717 				drm_atomic_get_plane_state(state, plane);
11718 
11719 			if (IS_ERR(new_plane_state)) {
11720 				ret = PTR_ERR(new_plane_state);
11721 				drm_dbg_atomic(dev, "new_plane_state is BAD\n");
11722 				goto fail;
11723 			}
11724 		}
11725 	}
11726 
11727 	/*
11728 	 * DC consults the zpos (layer_index in DC terminology) to determine the
11729 	 * hw plane on which to enable the hw cursor (see
11730 	 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
11731 	 * atomic state, so call drm helper to normalize zpos.
11732 	 */
11733 	ret = drm_atomic_normalize_zpos(dev, state);
11734 	if (ret) {
11735 		drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
11736 		goto fail;
11737 	}
11738 
11739 	/*
11740 	 * Determine whether cursors on each CRTC should be enabled in native or
11741 	 * overlay mode.
11742 	 */
11743 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11744 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
11745 
11746 		ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state,
11747 					      &dm_new_crtc_state->cursor_mode);
11748 		if (ret) {
11749 			drm_dbg(dev, "Failed to determine cursor mode\n");
11750 			goto fail;
11751 		}
11752 
11753 		/*
11754 		 * If overlay cursor is needed, DC cannot go through the
11755 		 * native cursor update path. All enabled planes on the CRTC
11756 		 * need to be added for DC to not disable a plane by mistake
11757 		 */
11758 		if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) {
11759 			ret = drm_atomic_add_affected_planes(state, crtc);
11760 			if (ret)
11761 				goto fail;
11762 		}
11763 	}
11764 
11765 	/* Remove exiting planes if they are modified */
11766 	for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {
11767 
11768 		ret = dm_update_plane_state(dc, state, plane,
11769 					    old_plane_state,
11770 					    new_plane_state,
11771 					    false,
11772 					    &lock_and_validation_needed,
11773 					    &is_top_most_overlay);
11774 		if (ret) {
11775 			drm_dbg_atomic(dev, "dm_update_plane_state() failed\n");
11776 			goto fail;
11777 		}
11778 	}
11779 
11780 	/* Disable all crtcs which require disable */
11781 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11782 		ret = dm_update_crtc_state(&adev->dm, state, crtc,
11783 					   old_crtc_state,
11784 					   new_crtc_state,
11785 					   false,
11786 					   &lock_and_validation_needed);
11787 		if (ret) {
11788 			drm_dbg_atomic(dev, "DISABLE: dm_update_crtc_state() failed\n");
11789 			goto fail;
11790 		}
11791 	}
11792 
11793 	/* Enable all crtcs which require enable */
11794 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11795 		ret = dm_update_crtc_state(&adev->dm, state, crtc,
11796 					   old_crtc_state,
11797 					   new_crtc_state,
11798 					   true,
11799 					   &lock_and_validation_needed);
11800 		if (ret) {
11801 			drm_dbg_atomic(dev, "ENABLE: dm_update_crtc_state() failed\n");
11802 			goto fail;
11803 		}
11804 	}
11805 
11806 	/* Add new/modified planes */
11807 	for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {
11808 		ret = dm_update_plane_state(dc, state, plane,
11809 					    old_plane_state,
11810 					    new_plane_state,
11811 					    true,
11812 					    &lock_and_validation_needed,
11813 					    &is_top_most_overlay);
11814 		if (ret) {
11815 			drm_dbg_atomic(dev, "dm_update_plane_state() failed\n");
11816 			goto fail;
11817 		}
11818 	}
11819 
11820 #if defined(CONFIG_DRM_AMD_DC_FP)
11821 	if (dc_resource_is_dsc_encoding_supported(dc)) {
11822 		ret = pre_validate_dsc(state, &dm_state, vars);
11823 		if (ret != 0)
11824 			goto fail;
11825 	}
11826 #endif
11827 
11828 	/* Run this here since we want to validate the streams we created */
11829 	ret = drm_atomic_helper_check_planes(dev, state);
11830 	if (ret) {
11831 		drm_dbg_atomic(dev, "drm_atomic_helper_check_planes() failed\n");
11832 		goto fail;
11833 	}
11834 
11835 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11836 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
11837 		if (dm_new_crtc_state->mpo_requested)
11838 			drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc);
11839 	}
11840 
11841 	/* Check cursor restrictions */
11842 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11843 		enum amdgpu_dm_cursor_mode required_cursor_mode;
11844 		int is_rotated, is_scaled;
11845 
11846 		/* Overlay cusor not subject to native cursor restrictions */
11847 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
11848 		if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE)
11849 			continue;
11850 
11851 		/* Check if rotation or scaling is enabled on DCN401 */
11852 		if ((drm_plane_mask(crtc->cursor) & new_crtc_state->plane_mask) &&
11853 		    amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) {
11854 			new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor);
11855 
11856 			is_rotated = new_cursor_state &&
11857 				((new_cursor_state->rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0);
11858 			is_scaled = new_cursor_state && ((new_cursor_state->src_w >> 16 != new_cursor_state->crtc_w) ||
11859 				(new_cursor_state->src_h >> 16 != new_cursor_state->crtc_h));
11860 
11861 			if (is_rotated || is_scaled) {
11862 				drm_dbg_driver(
11863 					crtc->dev,
11864 					"[CRTC:%d:%s] cannot enable hardware cursor due to rotation/scaling\n",
11865 					crtc->base.id, crtc->name);
11866 				ret = -EINVAL;
11867 				goto fail;
11868 			}
11869 		}
11870 
11871 		/* If HW can only do native cursor, check restrictions again */
11872 		ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state,
11873 					      &required_cursor_mode);
11874 		if (ret) {
11875 			drm_dbg_driver(crtc->dev,
11876 				       "[CRTC:%d:%s] Checking cursor mode failed\n",
11877 				       crtc->base.id, crtc->name);
11878 			goto fail;
11879 		} else if (required_cursor_mode == DM_CURSOR_OVERLAY_MODE) {
11880 			drm_dbg_driver(crtc->dev,
11881 				       "[CRTC:%d:%s] Cannot enable native cursor due to scaling or YUV restrictions\n",
11882 				       crtc->base.id, crtc->name);
11883 			ret = -EINVAL;
11884 			goto fail;
11885 		}
11886 	}
11887 
11888 	if (state->legacy_cursor_update) {
11889 		/*
11890 		 * This is a fast cursor update coming from the plane update
11891 		 * helper, check if it can be done asynchronously for better
11892 		 * performance.
11893 		 */
11894 		state->async_update =
11895 			!drm_atomic_helper_async_check(dev, state);
11896 
11897 		/*
11898 		 * Skip the remaining global validation if this is an async
11899 		 * update. Cursor updates can be done without affecting
11900 		 * state or bandwidth calcs and this avoids the performance
11901 		 * penalty of locking the private state object and
11902 		 * allocating a new dc_state.
11903 		 */
11904 		if (state->async_update)
11905 			return 0;
11906 	}
11907 
11908 	/* Check scaling and underscan changes*/
11909 	/* TODO Removed scaling changes validation due to inability to commit
11910 	 * new stream into context w\o causing full reset. Need to
11911 	 * decide how to handle.
11912 	 */
11913 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
11914 		struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
11915 		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
11916 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
11917 
11918 		/* Skip any modesets/resets */
11919 		if (!acrtc || drm_atomic_crtc_needs_modeset(
11920 				drm_atomic_get_new_crtc_state(state, &acrtc->base)))
11921 			continue;
11922 
11923 		/* Skip any thing not scale or underscan changes */
11924 		if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
11925 			continue;
11926 
11927 		lock_and_validation_needed = true;
11928 	}
11929 
11930 	/* set the slot info for each mst_state based on the link encoding format */
11931 	for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
11932 		struct amdgpu_dm_connector *aconnector;
11933 		struct drm_connector *connector;
11934 		struct drm_connector_list_iter iter;
11935 		u8 link_coding_cap;
11936 
11937 		drm_connector_list_iter_begin(dev, &iter);
11938 		drm_for_each_connector_iter(connector, &iter) {
11939 			if (connector->index == mst_state->mgr->conn_base_id) {
11940 				aconnector = to_amdgpu_dm_connector(connector);
11941 				link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
11942 				drm_dp_mst_update_slots(mst_state, link_coding_cap);
11943 
11944 				break;
11945 			}
11946 		}
11947 		drm_connector_list_iter_end(&iter);
11948 	}
11949 
11950 	/**
11951 	 * Streams and planes are reset when there are changes that affect
11952 	 * bandwidth. Anything that affects bandwidth needs to go through
11953 	 * DC global validation to ensure that the configuration can be applied
11954 	 * to hardware.
11955 	 *
11956 	 * We have to currently stall out here in atomic_check for outstanding
11957 	 * commits to finish in this case because our IRQ handlers reference
11958 	 * DRM state directly - we can end up disabling interrupts too early
11959 	 * if we don't.
11960 	 *
11961 	 * TODO: Remove this stall and drop DM state private objects.
11962 	 */
11963 	if (lock_and_validation_needed) {
11964 		ret = dm_atomic_get_state(state, &dm_state);
11965 		if (ret) {
11966 			drm_dbg_atomic(dev, "dm_atomic_get_state() failed\n");
11967 			goto fail;
11968 		}
11969 
11970 		ret = do_aquire_global_lock(dev, state);
11971 		if (ret) {
11972 			drm_dbg_atomic(dev, "do_aquire_global_lock() failed\n");
11973 			goto fail;
11974 		}
11975 
11976 #if defined(CONFIG_DRM_AMD_DC_FP)
11977 		if (dc_resource_is_dsc_encoding_supported(dc)) {
11978 			ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
11979 			if (ret) {
11980 				drm_dbg_atomic(dev, "MST_DSC compute_mst_dsc_configs_for_state() failed\n");
11981 				ret = -EINVAL;
11982 				goto fail;
11983 			}
11984 		}
11985 #endif
11986 
11987 		ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
11988 		if (ret) {
11989 			drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed\n");
11990 			goto fail;
11991 		}
11992 
11993 		/*
11994 		 * Perform validation of MST topology in the state:
11995 		 * We need to perform MST atomic check before calling
11996 		 * dc_validate_global_state(), or there is a chance
11997 		 * to get stuck in an infinite loop and hang eventually.
11998 		 */
11999 		ret = drm_dp_mst_atomic_check(state);
12000 		if (ret) {
12001 			drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed\n");
12002 			goto fail;
12003 		}
12004 		status = dc_validate_global_state(dc, dm_state->context, true);
12005 		if (status != DC_OK) {
12006 			drm_dbg_atomic(dev, "DC global validation failure: %s (%d)",
12007 				       dc_status_to_str(status), status);
12008 			ret = -EINVAL;
12009 			goto fail;
12010 		}
12011 	} else {
12012 		/*
12013 		 * The commit is a fast update. Fast updates shouldn't change
12014 		 * the DC context, affect global validation, and can have their
12015 		 * commit work done in parallel with other commits not touching
12016 		 * the same resource. If we have a new DC context as part of
12017 		 * the DM atomic state from validation we need to free it and
12018 		 * retain the existing one instead.
12019 		 *
12020 		 * Furthermore, since the DM atomic state only contains the DC
12021 		 * context and can safely be annulled, we can free the state
12022 		 * and clear the associated private object now to free
12023 		 * some memory and avoid a possible use-after-free later.
12024 		 */
12025 
12026 		for (i = 0; i < state->num_private_objs; i++) {
12027 			struct drm_private_obj *obj = state->private_objs[i].ptr;
12028 
12029 			if (obj->funcs == adev->dm.atomic_obj.funcs) {
12030 				int j = state->num_private_objs-1;
12031 
12032 				dm_atomic_destroy_state(obj,
12033 						state->private_objs[i].state);
12034 
12035 				/* If i is not at the end of the array then the
12036 				 * last element needs to be moved to where i was
12037 				 * before the array can safely be truncated.
12038 				 */
12039 				if (i != j)
12040 					state->private_objs[i] =
12041 						state->private_objs[j];
12042 
12043 				state->private_objs[j].ptr = NULL;
12044 				state->private_objs[j].state = NULL;
12045 				state->private_objs[j].old_state = NULL;
12046 				state->private_objs[j].new_state = NULL;
12047 
12048 				state->num_private_objs = j;
12049 				break;
12050 			}
12051 		}
12052 	}
12053 
12054 	/* Store the overall update type for use later in atomic check. */
12055 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12056 		struct dm_crtc_state *dm_new_crtc_state =
12057 			to_dm_crtc_state(new_crtc_state);
12058 
12059 		/*
12060 		 * Only allow async flips for fast updates that don't change
12061 		 * the FB pitch, the DCC state, rotation, mem_type, etc.
12062 		 */
12063 		if (new_crtc_state->async_flip &&
12064 		    (lock_and_validation_needed ||
12065 		     amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) {
12066 			drm_dbg_atomic(crtc->dev,
12067 				       "[CRTC:%d:%s] async flips are only supported for fast updates\n",
12068 				       crtc->base.id, crtc->name);
12069 			ret = -EINVAL;
12070 			goto fail;
12071 		}
12072 
12073 		dm_new_crtc_state->update_type = lock_and_validation_needed ?
12074 			UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
12075 	}
12076 
12077 	/* Must be success */
12078 	WARN_ON(ret);
12079 
12080 	trace_amdgpu_dm_atomic_check_finish(state, ret);
12081 
12082 	return ret;
12083 
12084 fail:
12085 	if (ret == -EDEADLK)
12086 		drm_dbg_atomic(dev, "Atomic check stopped to avoid deadlock.\n");
12087 	else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
12088 		drm_dbg_atomic(dev, "Atomic check stopped due to signal.\n");
12089 	else
12090 		drm_dbg_atomic(dev, "Atomic check failed with err: %d\n", ret);
12091 
12092 	trace_amdgpu_dm_atomic_check_finish(state, ret);
12093 
12094 	return ret;
12095 }
12096 
dm_edid_parser_send_cea(struct amdgpu_display_manager * dm,unsigned int offset,unsigned int total_length,u8 * data,unsigned int length,struct amdgpu_hdmi_vsdb_info * vsdb)12097 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
12098 		unsigned int offset,
12099 		unsigned int total_length,
12100 		u8 *data,
12101 		unsigned int length,
12102 		struct amdgpu_hdmi_vsdb_info *vsdb)
12103 {
12104 	bool res;
12105 	union dmub_rb_cmd cmd;
12106 	struct dmub_cmd_send_edid_cea *input;
12107 	struct dmub_cmd_edid_cea_output *output;
12108 
12109 	if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
12110 		return false;
12111 
12112 	memset(&cmd, 0, sizeof(cmd));
12113 
12114 	input = &cmd.edid_cea.data.input;
12115 
12116 	cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
12117 	cmd.edid_cea.header.sub_type = 0;
12118 	cmd.edid_cea.header.payload_bytes =
12119 		sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
12120 	input->offset = offset;
12121 	input->length = length;
12122 	input->cea_total_length = total_length;
12123 	memcpy(input->payload, data, length);
12124 
12125 	res = dc_wake_and_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
12126 	if (!res) {
12127 		DRM_ERROR("EDID CEA parser failed\n");
12128 		return false;
12129 	}
12130 
12131 	output = &cmd.edid_cea.data.output;
12132 
12133 	if (output->type == DMUB_CMD__EDID_CEA_ACK) {
12134 		if (!output->ack.success) {
12135 			DRM_ERROR("EDID CEA ack failed at offset %d\n",
12136 					output->ack.offset);
12137 		}
12138 	} else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
12139 		if (!output->amd_vsdb.vsdb_found)
12140 			return false;
12141 
12142 		vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
12143 		vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
12144 		vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
12145 		vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
12146 	} else {
12147 		DRM_WARN("Unknown EDID CEA parser results\n");
12148 		return false;
12149 	}
12150 
12151 	return true;
12152 }
12153 
parse_edid_cea_dmcu(struct amdgpu_display_manager * dm,u8 * edid_ext,int len,struct amdgpu_hdmi_vsdb_info * vsdb_info)12154 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
12155 		u8 *edid_ext, int len,
12156 		struct amdgpu_hdmi_vsdb_info *vsdb_info)
12157 {
12158 	int i;
12159 
12160 	/* send extension block to DMCU for parsing */
12161 	for (i = 0; i < len; i += 8) {
12162 		bool res;
12163 		int offset;
12164 
12165 		/* send 8 bytes a time */
12166 		if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
12167 			return false;
12168 
12169 		if (i+8 == len) {
12170 			/* EDID block sent completed, expect result */
12171 			int version, min_rate, max_rate;
12172 
12173 			res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
12174 			if (res) {
12175 				/* amd vsdb found */
12176 				vsdb_info->freesync_supported = 1;
12177 				vsdb_info->amd_vsdb_version = version;
12178 				vsdb_info->min_refresh_rate_hz = min_rate;
12179 				vsdb_info->max_refresh_rate_hz = max_rate;
12180 				return true;
12181 			}
12182 			/* not amd vsdb */
12183 			return false;
12184 		}
12185 
12186 		/* check for ack*/
12187 		res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
12188 		if (!res)
12189 			return false;
12190 	}
12191 
12192 	return false;
12193 }
12194 
parse_edid_cea_dmub(struct amdgpu_display_manager * dm,u8 * edid_ext,int len,struct amdgpu_hdmi_vsdb_info * vsdb_info)12195 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
12196 		u8 *edid_ext, int len,
12197 		struct amdgpu_hdmi_vsdb_info *vsdb_info)
12198 {
12199 	int i;
12200 
12201 	/* send extension block to DMCU for parsing */
12202 	for (i = 0; i < len; i += 8) {
12203 		/* send 8 bytes a time */
12204 		if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
12205 			return false;
12206 	}
12207 
12208 	return vsdb_info->freesync_supported;
12209 }
12210 
parse_edid_cea(struct amdgpu_dm_connector * aconnector,u8 * edid_ext,int len,struct amdgpu_hdmi_vsdb_info * vsdb_info)12211 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
12212 		u8 *edid_ext, int len,
12213 		struct amdgpu_hdmi_vsdb_info *vsdb_info)
12214 {
12215 	struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
12216 	bool ret;
12217 
12218 	mutex_lock(&adev->dm.dc_lock);
12219 	if (adev->dm.dmub_srv)
12220 		ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
12221 	else
12222 		ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
12223 	mutex_unlock(&adev->dm.dc_lock);
12224 	return ret;
12225 }
12226 
parse_edid_displayid_vrr(struct drm_connector * connector,const struct edid * edid)12227 static void parse_edid_displayid_vrr(struct drm_connector *connector,
12228 				     const struct edid *edid)
12229 {
12230 	u8 *edid_ext = NULL;
12231 	int i;
12232 	int j = 0;
12233 	u16 min_vfreq;
12234 	u16 max_vfreq;
12235 
12236 	if (edid == NULL || edid->extensions == 0)
12237 		return;
12238 
12239 	/* Find DisplayID extension */
12240 	for (i = 0; i < edid->extensions; i++) {
12241 		edid_ext = (void *)(edid + (i + 1));
12242 		if (edid_ext[0] == DISPLAYID_EXT)
12243 			break;
12244 	}
12245 
12246 	if (edid_ext == NULL)
12247 		return;
12248 
12249 	while (j < EDID_LENGTH) {
12250 		/* Get dynamic video timing range from DisplayID if available */
12251 		if (EDID_LENGTH - j > 13 && edid_ext[j] == 0x25	&&
12252 		    (edid_ext[j+1] & 0xFE) == 0 && (edid_ext[j+2] == 9)) {
12253 			min_vfreq = edid_ext[j+9];
12254 			if (edid_ext[j+1] & 7)
12255 				max_vfreq = edid_ext[j+10] + ((edid_ext[j+11] & 3) << 8);
12256 			else
12257 				max_vfreq = edid_ext[j+10];
12258 
12259 			if (max_vfreq && min_vfreq) {
12260 				connector->display_info.monitor_range.max_vfreq = max_vfreq;
12261 				connector->display_info.monitor_range.min_vfreq = min_vfreq;
12262 
12263 				return;
12264 			}
12265 		}
12266 		j++;
12267 	}
12268 }
12269 
parse_amd_vsdb(struct amdgpu_dm_connector * aconnector,const struct edid * edid,struct amdgpu_hdmi_vsdb_info * vsdb_info)12270 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
12271 			  const struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
12272 {
12273 	u8 *edid_ext = NULL;
12274 	int i;
12275 	int j = 0;
12276 
12277 	if (edid == NULL || edid->extensions == 0)
12278 		return -ENODEV;
12279 
12280 	/* Find DisplayID extension */
12281 	for (i = 0; i < edid->extensions; i++) {
12282 		edid_ext = (void *)(edid + (i + 1));
12283 		if (edid_ext[0] == DISPLAYID_EXT)
12284 			break;
12285 	}
12286 
12287 	while (j < EDID_LENGTH - sizeof(struct amd_vsdb_block)) {
12288 		struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
12289 		unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
12290 
12291 		if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&
12292 				amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {
12293 			vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
12294 			vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;
12295 			DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);
12296 
12297 			return true;
12298 		}
12299 		j++;
12300 	}
12301 
12302 	return false;
12303 }
12304 
parse_hdmi_amd_vsdb(struct amdgpu_dm_connector * aconnector,const struct edid * edid,struct amdgpu_hdmi_vsdb_info * vsdb_info)12305 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
12306 			       const struct edid *edid,
12307 			       struct amdgpu_hdmi_vsdb_info *vsdb_info)
12308 {
12309 	u8 *edid_ext = NULL;
12310 	int i;
12311 	bool valid_vsdb_found = false;
12312 
12313 	/*----- drm_find_cea_extension() -----*/
12314 	/* No EDID or EDID extensions */
12315 	if (edid == NULL || edid->extensions == 0)
12316 		return -ENODEV;
12317 
12318 	/* Find CEA extension */
12319 	for (i = 0; i < edid->extensions; i++) {
12320 		edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
12321 		if (edid_ext[0] == CEA_EXT)
12322 			break;
12323 	}
12324 
12325 	if (i == edid->extensions)
12326 		return -ENODEV;
12327 
12328 	/*----- cea_db_offsets() -----*/
12329 	if (edid_ext[0] != CEA_EXT)
12330 		return -ENODEV;
12331 
12332 	valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
12333 
12334 	return valid_vsdb_found ? i : -ENODEV;
12335 }
12336 
12337 /**
12338  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
12339  *
12340  * @connector: Connector to query.
12341  * @drm_edid: DRM EDID from monitor
12342  *
12343  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
12344  * track of some of the display information in the internal data struct used by
12345  * amdgpu_dm. This function checks which type of connector we need to set the
12346  * FreeSync parameters.
12347  */
amdgpu_dm_update_freesync_caps(struct drm_connector * connector,const struct drm_edid * drm_edid)12348 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
12349 				    const struct drm_edid *drm_edid)
12350 {
12351 	int i = 0;
12352 	struct amdgpu_dm_connector *amdgpu_dm_connector =
12353 			to_amdgpu_dm_connector(connector);
12354 	struct dm_connector_state *dm_con_state = NULL;
12355 	struct dc_sink *sink;
12356 	struct amdgpu_device *adev = drm_to_adev(connector->dev);
12357 	struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
12358 	const struct edid *edid;
12359 	bool freesync_capable = false;
12360 	enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
12361 
12362 	if (!connector->state) {
12363 		DRM_ERROR("%s - Connector has no state", __func__);
12364 		goto update;
12365 	}
12366 
12367 	sink = amdgpu_dm_connector->dc_sink ?
12368 		amdgpu_dm_connector->dc_sink :
12369 		amdgpu_dm_connector->dc_em_sink;
12370 
12371 	drm_edid_connector_update(connector, drm_edid);
12372 
12373 	if (!drm_edid || !sink) {
12374 		dm_con_state = to_dm_connector_state(connector->state);
12375 
12376 		amdgpu_dm_connector->min_vfreq = 0;
12377 		amdgpu_dm_connector->max_vfreq = 0;
12378 		freesync_capable = false;
12379 
12380 		goto update;
12381 	}
12382 
12383 	dm_con_state = to_dm_connector_state(connector->state);
12384 
12385 	if (!adev->dm.freesync_module)
12386 		goto update;
12387 
12388 	edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()
12389 
12390 	/* Some eDP panels only have the refresh rate range info in DisplayID */
12391 	if ((connector->display_info.monitor_range.min_vfreq == 0 ||
12392 	     connector->display_info.monitor_range.max_vfreq == 0))
12393 		parse_edid_displayid_vrr(connector, edid);
12394 
12395 	if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
12396 		     sink->sink_signal == SIGNAL_TYPE_EDP)) {
12397 		if (amdgpu_dm_connector->dc_link &&
12398 		    amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) {
12399 			amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq;
12400 			amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq;
12401 			if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
12402 				freesync_capable = true;
12403 		}
12404 
12405 		parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
12406 
12407 		if (vsdb_info.replay_mode) {
12408 			amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
12409 			amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
12410 			amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
12411 		}
12412 
12413 	} else if (drm_edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
12414 		i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
12415 		if (i >= 0 && vsdb_info.freesync_supported) {
12416 			amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
12417 			amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
12418 			if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
12419 				freesync_capable = true;
12420 
12421 			connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
12422 			connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
12423 		}
12424 	}
12425 
12426 	if (amdgpu_dm_connector->dc_link)
12427 		as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
12428 
12429 	if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
12430 		i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
12431 		if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
12432 
12433 			amdgpu_dm_connector->pack_sdp_v1_3 = true;
12434 			amdgpu_dm_connector->as_type = as_type;
12435 			amdgpu_dm_connector->vsdb_info = vsdb_info;
12436 
12437 			amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
12438 			amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
12439 			if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
12440 				freesync_capable = true;
12441 
12442 			connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
12443 			connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
12444 		}
12445 	}
12446 
12447 update:
12448 	if (dm_con_state)
12449 		dm_con_state->freesync_capable = freesync_capable;
12450 
12451 	if (connector->state && amdgpu_dm_connector->dc_link && !freesync_capable &&
12452 	    amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported) {
12453 		amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported = false;
12454 		amdgpu_dm_connector->dc_link->replay_settings.replay_feature_enabled = false;
12455 	}
12456 
12457 	if (connector->vrr_capable_property)
12458 		drm_connector_set_vrr_capable_property(connector,
12459 						       freesync_capable);
12460 }
12461 
amdgpu_dm_trigger_timing_sync(struct drm_device * dev)12462 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
12463 {
12464 	struct amdgpu_device *adev = drm_to_adev(dev);
12465 	struct dc *dc = adev->dm.dc;
12466 	int i;
12467 
12468 	mutex_lock(&adev->dm.dc_lock);
12469 	if (dc->current_state) {
12470 		for (i = 0; i < dc->current_state->stream_count; ++i)
12471 			dc->current_state->streams[i]
12472 				->triggered_crtc_reset.enabled =
12473 				adev->dm.force_timing_sync;
12474 
12475 		dm_enable_per_frame_crtc_master_sync(dc->current_state);
12476 		dc_trigger_sync(dc, dc->current_state);
12477 	}
12478 	mutex_unlock(&adev->dm.dc_lock);
12479 }
12480 
amdgpu_dm_exit_ips_for_hw_access(struct dc * dc)12481 static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc)
12482 {
12483 	if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter)
12484 		dc_exit_ips_for_hw_access(dc);
12485 }
12486 
dm_write_reg_func(const struct dc_context * ctx,uint32_t address,u32 value,const char * func_name)12487 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
12488 		       u32 value, const char *func_name)
12489 {
12490 #ifdef DM_CHECK_ADDR_0
12491 	if (address == 0) {
12492 		drm_err(adev_to_drm(ctx->driver_context),
12493 			"invalid register write. address = 0");
12494 		return;
12495 	}
12496 #endif
12497 
12498 	amdgpu_dm_exit_ips_for_hw_access(ctx->dc);
12499 	cgs_write_register(ctx->cgs_device, address, value);
12500 	trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
12501 }
12502 
dm_read_reg_func(const struct dc_context * ctx,uint32_t address,const char * func_name)12503 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
12504 			  const char *func_name)
12505 {
12506 	u32 value;
12507 #ifdef DM_CHECK_ADDR_0
12508 	if (address == 0) {
12509 		drm_err(adev_to_drm(ctx->driver_context),
12510 			"invalid register read; address = 0\n");
12511 		return 0;
12512 	}
12513 #endif
12514 
12515 	if (ctx->dmub_srv &&
12516 	    ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
12517 	    !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
12518 		ASSERT(false);
12519 		return 0;
12520 	}
12521 
12522 	amdgpu_dm_exit_ips_for_hw_access(ctx->dc);
12523 
12524 	value = cgs_read_register(ctx->cgs_device, address);
12525 
12526 	trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
12527 
12528 	return value;
12529 }
12530 
amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context * ctx,unsigned int link_index,struct aux_payload * payload,enum aux_return_code_type * operation_result)12531 int amdgpu_dm_process_dmub_aux_transfer_sync(
12532 		struct dc_context *ctx,
12533 		unsigned int link_index,
12534 		struct aux_payload *payload,
12535 		enum aux_return_code_type *operation_result)
12536 {
12537 	struct amdgpu_device *adev = ctx->driver_context;
12538 	struct dmub_notification *p_notify = adev->dm.dmub_notify;
12539 	int ret = -1;
12540 
12541 	mutex_lock(&adev->dm.dpia_aux_lock);
12542 	if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
12543 		*operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
12544 		goto out;
12545 	}
12546 
12547 	if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
12548 		DRM_ERROR("wait_for_completion_timeout timeout!");
12549 		*operation_result = AUX_RET_ERROR_TIMEOUT;
12550 		goto out;
12551 	}
12552 
12553 	if (p_notify->result != AUX_RET_SUCCESS) {
12554 		/*
12555 		 * Transient states before tunneling is enabled could
12556 		 * lead to this error. We can ignore this for now.
12557 		 */
12558 		if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
12559 			DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
12560 					payload->address, payload->length,
12561 					p_notify->result);
12562 		}
12563 		*operation_result = AUX_RET_ERROR_INVALID_REPLY;
12564 		goto out;
12565 	}
12566 
12567 
12568 	payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
12569 	if (!payload->write && p_notify->aux_reply.length &&
12570 			(payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
12571 
12572 		if (payload->length != p_notify->aux_reply.length) {
12573 			DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
12574 				p_notify->aux_reply.length,
12575 					payload->address, payload->length);
12576 			*operation_result = AUX_RET_ERROR_INVALID_REPLY;
12577 			goto out;
12578 		}
12579 
12580 		memcpy(payload->data, p_notify->aux_reply.data,
12581 				p_notify->aux_reply.length);
12582 	}
12583 
12584 	/* success */
12585 	ret = p_notify->aux_reply.length;
12586 	*operation_result = p_notify->result;
12587 out:
12588 	reinit_completion(&adev->dm.dmub_aux_transfer_done);
12589 	mutex_unlock(&adev->dm.dpia_aux_lock);
12590 	return ret;
12591 }
12592 
amdgpu_dm_process_dmub_set_config_sync(struct dc_context * ctx,unsigned int link_index,struct set_config_cmd_payload * payload,enum set_config_status * operation_result)12593 int amdgpu_dm_process_dmub_set_config_sync(
12594 		struct dc_context *ctx,
12595 		unsigned int link_index,
12596 		struct set_config_cmd_payload *payload,
12597 		enum set_config_status *operation_result)
12598 {
12599 	struct amdgpu_device *adev = ctx->driver_context;
12600 	bool is_cmd_complete;
12601 	int ret;
12602 
12603 	mutex_lock(&adev->dm.dpia_aux_lock);
12604 	is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
12605 			link_index, payload, adev->dm.dmub_notify);
12606 
12607 	if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
12608 		ret = 0;
12609 		*operation_result = adev->dm.dmub_notify->sc_status;
12610 	} else {
12611 		DRM_ERROR("wait_for_completion_timeout timeout!");
12612 		ret = -1;
12613 		*operation_result = SET_CONFIG_UNKNOWN_ERROR;
12614 	}
12615 
12616 	if (!is_cmd_complete)
12617 		reinit_completion(&adev->dm.dmub_aux_transfer_done);
12618 	mutex_unlock(&adev->dm.dpia_aux_lock);
12619 	return ret;
12620 }
12621 
dm_execute_dmub_cmd(const struct dc_context * ctx,union dmub_rb_cmd * cmd,enum dm_dmub_wait_type wait_type)12622 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
12623 {
12624 	return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
12625 }
12626 
dm_execute_dmub_cmd_list(const struct dc_context * ctx,unsigned int count,union dmub_rb_cmd * cmd,enum dm_dmub_wait_type wait_type)12627 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
12628 {
12629 	return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
12630 }
12631