1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2016, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/err.h> 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/regulator/consumer.h> 9 #include <linux/types.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 #include <sound/soc.h> 14 #include <sound/pcm.h> 15 #include <sound/pcm_params.h> 16 #include <sound/tlv.h> 17 #include <sound/jack.h> 18 19 #define CDC_D_REVISION1 (0xf000) 20 #define CDC_D_PERPH_SUBTYPE (0xf005) 21 #define CDC_D_INT_EN_SET (0xf015) 22 #define CDC_D_INT_EN_CLR (0xf016) 23 #define MBHC_SWITCH_INT BIT(7) 24 #define MBHC_MIC_ELECTRICAL_INS_REM_DET BIT(6) 25 #define MBHC_BUTTON_PRESS_DET BIT(5) 26 #define MBHC_BUTTON_RELEASE_DET BIT(4) 27 #define CDC_D_CDC_RST_CTL (0xf046) 28 #define RST_CTL_DIG_SW_RST_N_MASK BIT(7) 29 #define RST_CTL_DIG_SW_RST_N_RESET 0 30 #define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7) 31 32 #define CDC_D_CDC_TOP_CLK_CTL (0xf048) 33 #define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3)) 34 #define TOP_CLK_CTL_A_MCLK_EN_ENABLE BIT(2) 35 #define TOP_CLK_CTL_A_MCLK2_EN_ENABLE BIT(3) 36 37 #define CDC_D_CDC_ANA_CLK_CTL (0xf049) 38 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0) 39 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0) 40 #define ANA_CLK_CTL_EAR_HPHL_CLK_EN BIT(1) 41 #define ANA_CLK_CTL_SPKR_CLK_EN_MASK BIT(4) 42 #define ANA_CLK_CTL_SPKR_CLK_EN BIT(4) 43 #define ANA_CLK_CTL_TXA_CLK25_EN BIT(5) 44 45 #define CDC_D_CDC_DIG_CLK_CTL (0xf04A) 46 #define DIG_CLK_CTL_RXD1_CLK_EN BIT(0) 47 #define DIG_CLK_CTL_RXD2_CLK_EN BIT(1) 48 #define DIG_CLK_CTL_RXD3_CLK_EN BIT(2) 49 #define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK BIT(3) 50 #define DIG_CLK_CTL_D_MBHC_CLK_EN BIT(3) 51 #define DIG_CLK_CTL_TXD_CLK_EN BIT(4) 52 #define DIG_CLK_CTL_NCP_CLK_EN_MASK BIT(6) 53 #define DIG_CLK_CTL_NCP_CLK_EN BIT(6) 54 #define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7) 55 #define DIG_CLK_CTL_RXD_PDM_CLK_EN BIT(7) 56 57 #define CDC_D_CDC_CONN_TX1_CTL (0xf050) 58 #define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0) 59 #define CONN_TX1_SERIAL_TX1_ADC_1 0x0 60 #define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1 61 #define CONN_TX1_SERIAL_TX1_ZERO 0x2 62 63 #define CDC_D_CDC_CONN_TX2_CTL (0xf051) 64 #define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0) 65 #define CONN_TX2_SERIAL_TX2_ADC_2 0x0 66 #define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1 67 #define CONN_TX2_SERIAL_TX2_ZERO 0x2 68 #define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052) 69 #define CDC_D_CDC_CONN_RX1_CTL (0xf053) 70 #define CDC_D_CDC_CONN_RX2_CTL (0xf054) 71 #define CDC_D_CDC_CONN_RX3_CTL (0xf055) 72 #define CDC_D_CDC_CONN_RX_LB_CTL (0xf056) 73 #define CDC_D_SEC_ACCESS (0xf0D0) 74 #define CDC_D_PERPH_RESET_CTL3 (0xf0DA) 75 #define CDC_D_PERPH_RESET_CTL4 (0xf0DB) 76 #define CDC_A_REVISION1 (0xf100) 77 #define CDC_A_REVISION2 (0xf101) 78 #define CDC_A_REVISION3 (0xf102) 79 #define CDC_A_REVISION4 (0xf103) 80 #define CDC_A_PERPH_TYPE (0xf104) 81 #define CDC_A_PERPH_SUBTYPE (0xf105) 82 #define CDC_A_INT_RT_STS (0xf110) 83 #define CDC_A_INT_SET_TYPE (0xf111) 84 #define CDC_A_INT_POLARITY_HIGH (0xf112) 85 #define CDC_A_INT_POLARITY_LOW (0xf113) 86 #define CDC_A_INT_LATCHED_CLR (0xf114) 87 #define CDC_A_INT_EN_SET (0xf115) 88 #define CDC_A_INT_EN_CLR (0xf116) 89 #define CDC_A_INT_LATCHED_STS (0xf118) 90 #define CDC_A_INT_PENDING_STS (0xf119) 91 #define CDC_A_INT_MID_SEL (0xf11A) 92 #define CDC_A_INT_PRIORITY (0xf11B) 93 #define CDC_A_MICB_1_EN (0xf140) 94 #define MICB_1_EN_MICB_ENABLE BIT(7) 95 #define MICB_1_EN_BYP_CAP_MASK BIT(6) 96 #define MICB_1_EN_NO_EXT_BYP_CAP BIT(6) 97 #define MICB_1_EN_EXT_BYP_CAP 0 98 #define MICB_1_EN_PULL_DOWN_EN_MASK BIT(5) 99 #define MICB_1_EN_PULL_DOWN_EN_ENABLE BIT(5) 100 #define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1) 101 #define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4) 102 #define MICB_1_EN_PULL_UP_EN_MASK BIT(4) 103 #define MICB_1_EN_TX3_GND_SEL_MASK BIT(0) 104 #define MICB_1_EN_TX3_GND_SEL_TX_GND 0 105 106 #define CDC_A_MICB_1_VAL (0xf141) 107 #define MICB_MIN_VAL 1600 108 #define MICB_STEP_SIZE 50 109 #define MICB_VOLTAGE_REGVAL(v) (((v - MICB_MIN_VAL)/MICB_STEP_SIZE) << 3) 110 #define MICB_1_VAL_MICB_OUT_VAL_MASK GENMASK(7, 3) 111 #define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3) 112 #define MICB_1_VAL_MICB_OUT_VAL_V1P80V ((0x4) << 3) 113 #define CDC_A_MICB_1_CTL (0xf142) 114 115 #define MICB_1_CTL_CFILT_REF_SEL_MASK BIT(1) 116 #define MICB_1_CTL_CFILT_REF_SEL_HPF_REF BIT(1) 117 #define MICB_1_CTL_EXT_PRECHARG_EN_MASK BIT(5) 118 #define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE BIT(5) 119 #define MICB_1_CTL_INT_PRECHARG_BYP_MASK BIT(6) 120 #define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL BIT(6) 121 122 #define CDC_A_MICB_1_INT_RBIAS (0xf143) 123 #define MICB_1_INT_TX1_INT_RBIAS_EN_MASK BIT(7) 124 #define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE BIT(7) 125 #define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0 126 127 #define MICB_1_INT_TX1_INT_PULLUP_EN_MASK BIT(6) 128 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6) 129 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0 130 131 #define MICB_1_INT_TX2_INT_RBIAS_EN_MASK BIT(4) 132 #define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE BIT(4) 133 #define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0 134 #define MICB_1_INT_TX2_INT_PULLUP_EN_MASK BIT(3) 135 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3) 136 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0 137 138 #define MICB_1_INT_TX3_INT_RBIAS_EN_MASK BIT(1) 139 #define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE BIT(1) 140 #define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0 141 #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0) 142 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0) 143 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0 144 145 #define CDC_A_MICB_2_EN (0xf144) 146 #define CDC_A_MICB_2_EN_ENABLE BIT(7) 147 #define CDC_A_MICB_2_PULL_DOWN_EN_MASK BIT(5) 148 #define CDC_A_MICB_2_PULL_DOWN_EN BIT(5) 149 #define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145) 150 #define CDC_A_MASTER_BIAS_CTL (0xf146) 151 #define CDC_A_MBHC_DET_CTL_1 (0xf147) 152 #define CDC_A_MBHC_DET_CTL_L_DET_EN BIT(7) 153 #define CDC_A_MBHC_DET_CTL_GND_DET_EN BIT(6) 154 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION BIT(5) 155 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL (0) 156 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK BIT(5) 157 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT (5) 158 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO BIT(4) 159 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL BIT(3) 160 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK GENMASK(4, 3) 161 #define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN BIT(2) 162 #define CDC_A_MBHC_DET_CTL_2 (0xf150) 163 #define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 (BIT(7) | BIT(6)) 164 #define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD BIT(5) 165 #define CDC_A_PLUG_TYPE_MASK GENMASK(4, 3) 166 #define CDC_A_HPHL_PLUG_TYPE_NO BIT(4) 167 #define CDC_A_GND_PLUG_TYPE_NO BIT(3) 168 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK BIT(0) 169 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN BIT(0) 170 #define CDC_A_MBHC_FSM_CTL (0xf151) 171 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN BIT(7) 172 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK BIT(7) 173 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA (0x3 << 4) 174 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK GENMASK(6, 4) 175 #define CDC_A_MBHC_DBNC_TIMER (0xf152) 176 #define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS BIT(3) 177 #define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS (0x9 << 4) 178 #define CDC_A_MBHC_BTN0_ZDET_CTL_0 (0xf153) 179 #define CDC_A_MBHC_BTN1_ZDET_CTL_1 (0xf154) 180 #define CDC_A_MBHC_BTN2_ZDET_CTL_2 (0xf155) 181 #define CDC_A_MBHC_BTN3_CTL (0xf156) 182 #define CDC_A_MBHC_BTN4_CTL (0xf157) 183 #define CDC_A_MBHC_BTN_VREF_FINE_SHIFT (2) 184 #define CDC_A_MBHC_BTN_VREF_FINE_MASK GENMASK(4, 2) 185 #define CDC_A_MBHC_BTN_VREF_COARSE_MASK GENMASK(7, 5) 186 #define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT (5) 187 #define CDC_A_MBHC_BTN_VREF_MASK (CDC_A_MBHC_BTN_VREF_COARSE_MASK | \ 188 CDC_A_MBHC_BTN_VREF_FINE_MASK) 189 #define CDC_A_MBHC_RESULT_1 (0xf158) 190 #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK GENMASK(4, 0) 191 #define CDC_A_TX_1_EN (0xf160) 192 #define CDC_A_TX_2_EN (0xf161) 193 #define CDC_A_TX_1_2_TEST_CTL_1 (0xf162) 194 #define CDC_A_TX_1_2_TEST_CTL_2 (0xf163) 195 #define CDC_A_TX_1_2_ATEST_CTL (0xf164) 196 #define CDC_A_TX_1_2_OPAMP_BIAS (0xf165) 197 #define CDC_A_TX_3_EN (0xf167) 198 #define CDC_A_NCP_EN (0xf180) 199 #define CDC_A_NCP_CLK (0xf181) 200 #define CDC_A_NCP_FBCTRL (0xf183) 201 #define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK BIT(5) 202 #define CDC_A_NCP_FBCTRL_FB_CLK_INV BIT(5) 203 #define CDC_A_NCP_BIAS (0xf184) 204 #define CDC_A_NCP_VCTRL (0xf185) 205 #define CDC_A_NCP_TEST (0xf186) 206 #define CDC_A_NCP_CLIM_ADDR (0xf187) 207 #define CDC_A_RX_CLOCK_DIVIDER (0xf190) 208 #define CDC_A_RX_COM_OCP_CTL (0xf191) 209 #define CDC_A_RX_COM_OCP_COUNT (0xf192) 210 #define CDC_A_RX_COM_BIAS_DAC (0xf193) 211 #define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK BIT(7) 212 #define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE BIT(7) 213 #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0) 214 #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0) 215 216 #define CDC_A_RX_HPH_BIAS_PA (0xf194) 217 #define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195) 218 #define CDC_A_RX_HPH_BIAS_CNP (0xf196) 219 #define CDC_A_RX_HPH_CNP_EN (0xf197) 220 #define CDC_A_RX_HPH_L_TEST (0xf19A) 221 #define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B) 222 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK BIT(1) 223 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET BIT(1) 224 #define CDC_A_RX_HPH_R_TEST (0xf19C) 225 #define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D) 226 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET BIT(1) 227 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1) 228 229 #define CDC_A_RX_EAR_CTL (0xf19E) 230 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0) 231 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0) 232 #define RX_EAR_CTL_PA_EAR_PA_EN_MASK BIT(6) 233 #define RX_EAR_CTL_PA_EAR_PA_EN_ENABLE BIT(6) 234 #define RX_EAR_CTL_PA_SEL_MASK BIT(7) 235 #define RX_EAR_CTL_PA_SEL BIT(7) 236 237 #define CDC_A_RX_EAR_STATUS (0xf1A1) 238 239 #define CDC_A_SPKR_DAC_CTL (0xf1B0) 240 #define SPKR_DAC_CTL_DAC_RESET_MASK BIT(4) 241 #define SPKR_DAC_CTL_DAC_RESET_NORMAL 0 242 243 #define CDC_A_SPKR_DRV_CTL (0xf1B2) 244 #define SPKR_DRV_CTL_DEF_MASK 0xEF 245 #define SPKR_DRV_CLASSD_PA_EN_MASK BIT(7) 246 #define SPKR_DRV_CLASSD_PA_EN_ENABLE BIT(7) 247 #define SPKR_DRV_CAL_EN BIT(6) 248 #define SPKR_DRV_SETTLE_EN BIT(5) 249 #define SPKR_DRV_FW_EN BIT(3) 250 #define SPKR_DRV_BOOST_SET BIT(2) 251 #define SPKR_DRV_CMFB_SET BIT(1) 252 #define SPKR_DRV_GAIN_SET BIT(0) 253 #define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \ 254 SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \ 255 SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \ 256 SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET) 257 #define CDC_A_SPKR_ANA_BIAS_SET (0xf1B3) 258 #define CDC_A_SPKR_OCP_CTL (0xf1B4) 259 #define CDC_A_SPKR_PWRSTG_CTL (0xf1B5) 260 #define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0) 261 #define SPKR_PWRSTG_CTL_DAC_EN BIT(0) 262 #define SPKR_PWRSTG_CTL_MASK 0xE0 263 #define SPKR_PWRSTG_CTL_BBM_MASK BIT(7) 264 #define SPKR_PWRSTG_CTL_BBM_EN BIT(7) 265 #define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK BIT(6) 266 #define SPKR_PWRSTG_CTL_HBRDGE_EN BIT(6) 267 #define SPKR_PWRSTG_CTL_CLAMP_EN_MASK BIT(5) 268 #define SPKR_PWRSTG_CTL_CLAMP_EN BIT(5) 269 270 #define CDC_A_SPKR_DRV_DBG (0xf1B7) 271 #define CDC_A_CURRENT_LIMIT (0xf1C0) 272 #define CDC_A_BYPASS_MODE (0xf1C2) 273 #define CDC_A_BOOST_EN_CTL (0xf1C3) 274 #define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4) 275 #define CDC_A_SEC_ACCESS (0xf1D0) 276 #define CDC_A_PERPH_RESET_CTL3 (0xf1DA) 277 #define CDC_A_PERPH_RESET_CTL4 (0xf1DB) 278 279 #define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 280 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000) 281 #define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 282 SNDRV_PCM_FMTBIT_S32_LE) 283 284 static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | 285 SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4; 286 static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET; 287 288 static const char * const supply_names[] = { 289 "vdd-cdc-io", 290 "vdd-cdc-tx-rx-cx", 291 }; 292 293 #define MBHC_MAX_BUTTONS (5) 294 295 struct wcd_reg_seq { 296 const struct reg_default *seq; 297 int seq_size; 298 }; 299 300 struct pm8916_wcd_analog_priv { 301 u16 pmic_rev; 302 u16 codec_version; 303 bool mbhc_btn_enabled; 304 /* special event to detect accessory type */ 305 int mbhc_btn0_released; 306 bool detect_accessory_type; 307 struct clk *mclk; 308 struct snd_soc_component *component; 309 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; 310 struct snd_soc_jack *jack; 311 bool hphl_jack_type_normally_open; 312 bool gnd_jack_type_normally_open; 313 /* Voltage threshold when internal current source of 100uA is used */ 314 u32 vref_btn_cs[MBHC_MAX_BUTTONS]; 315 /* Voltage threshold when microphone bias is ON */ 316 u32 vref_btn_micb[MBHC_MAX_BUTTONS]; 317 unsigned int micbias1_cap_mode; 318 unsigned int micbias2_cap_mode; 319 unsigned int micbias_mv; 320 }; 321 322 static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" }; 323 static const char *const rdac2_mux_text[] = { "RX1", "RX2" }; 324 static const char *const hph_text[] = { "ZERO", "Switch", }; 325 326 static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT( 327 ARRAY_SIZE(hph_text), hph_text); 328 329 static const struct snd_kcontrol_new ear_mux = SOC_DAPM_ENUM("EAR_S", hph_enum); 330 static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum); 331 static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum); 332 333 /* ADC2 MUX */ 334 static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT( 335 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 336 337 /* RDAC2 MUX */ 338 static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE( 339 CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 2, rdac2_mux_text); 340 341 static const struct snd_kcontrol_new spkr_switch[] = { 342 SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0) 343 }; 344 345 static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM( 346 "RDAC2 MUX Mux", rdac2_mux_enum); 347 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM( 348 "ADC2 MUX Mux", adc2_enum); 349 350 /* Analog Gain control 0 dB to +24 dB in 6 dB steps */ 351 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0); 352 353 static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = { 354 SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain), 355 SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain), 356 SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain), 357 }; 358 359 static void pm8916_wcd_analog_micbias_enable(struct snd_soc_component *component) 360 { 361 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 362 363 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, 364 MICB_1_CTL_EXT_PRECHARG_EN_MASK | 365 MICB_1_CTL_INT_PRECHARG_BYP_MASK, 366 MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL 367 | MICB_1_CTL_EXT_PRECHARG_EN_ENABLE); 368 369 if (wcd->micbias_mv) { 370 snd_soc_component_update_bits(component, CDC_A_MICB_1_VAL, 371 MICB_1_VAL_MICB_OUT_VAL_MASK, 372 MICB_VOLTAGE_REGVAL(wcd->micbias_mv)); 373 /* 374 * Special headset needs MICBIAS as 2.7V so wait for 375 * 50 msec for the MICBIAS to reach 2.7 volts. 376 */ 377 if (wcd->micbias_mv >= 2700) 378 msleep(50); 379 } 380 381 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, 382 MICB_1_CTL_EXT_PRECHARG_EN_MASK | 383 MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0); 384 385 } 386 387 static int pm8916_wcd_analog_enable_micbias(struct snd_soc_component *component, 388 int event, unsigned int cap_mode) 389 { 390 switch (event) { 391 case SND_SOC_DAPM_POST_PMU: 392 pm8916_wcd_analog_micbias_enable(component); 393 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN, 394 MICB_1_EN_BYP_CAP_MASK, cap_mode); 395 break; 396 } 397 398 return 0; 399 } 400 401 static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_dapm_widget *w, 402 struct snd_kcontrol *kcontrol, 403 int event) 404 { 405 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 406 407 switch (event) { 408 case SND_SOC_DAPM_PRE_PMU: 409 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN, 410 MICB_1_EN_OPA_STG2_TAIL_CURR_MASK, 411 MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA); 412 break; 413 } 414 415 return 0; 416 } 417 418 static int pm8916_wcd_analog_enable_micbias1(struct snd_soc_dapm_widget *w, 419 struct snd_kcontrol *kcontrol, 420 int event) 421 { 422 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 423 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 424 425 return pm8916_wcd_analog_enable_micbias(component, event, 426 wcd->micbias1_cap_mode); 427 } 428 429 static int pm8916_wcd_analog_enable_micbias2(struct snd_soc_dapm_widget *w, 430 struct snd_kcontrol *kcontrol, 431 int event) 432 { 433 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 434 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 435 436 return pm8916_wcd_analog_enable_micbias(component, event, 437 wcd->micbias2_cap_mode); 438 439 } 440 441 static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv, 442 bool micbias2_enabled) 443 { 444 struct snd_soc_component *component = priv->component; 445 u32 coarse, fine, reg_val, reg_addr; 446 int *vrefs, i; 447 448 if (!micbias2_enabled) { /* use internal 100uA Current source */ 449 /* Enable internal 2.2k Internal Rbias Resistor */ 450 snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS, 451 MICB_1_INT_TX2_INT_RBIAS_EN_MASK, 452 MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE); 453 /* Remove pull down on MIC BIAS2 */ 454 snd_soc_component_update_bits(component, CDC_A_MICB_2_EN, 455 CDC_A_MICB_2_PULL_DOWN_EN_MASK, 456 0); 457 /* enable 100uA internal current source */ 458 snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL, 459 CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK, 460 CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA); 461 } 462 snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL, 463 CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK, 464 CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN); 465 466 if (micbias2_enabled) 467 vrefs = &priv->vref_btn_micb[0]; 468 else 469 vrefs = &priv->vref_btn_cs[0]; 470 471 /* program vref ranges for all the buttons */ 472 reg_addr = CDC_A_MBHC_BTN0_ZDET_CTL_0; 473 for (i = 0; i < MBHC_MAX_BUTTONS; i++) { 474 /* split mv in to coarse parts of 100mv & fine parts of 12mv */ 475 coarse = (vrefs[i] / 100); 476 fine = ((vrefs[i] % 100) / 12); 477 reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) | 478 (fine << CDC_A_MBHC_BTN_VREF_FINE_SHIFT); 479 snd_soc_component_update_bits(component, reg_addr, 480 CDC_A_MBHC_BTN_VREF_MASK, 481 reg_val); 482 reg_addr++; 483 } 484 485 return 0; 486 } 487 488 static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd) 489 { 490 struct snd_soc_component *component = wcd->component; 491 bool micbias_enabled = false; 492 u32 plug_type = 0; 493 u32 int_en_mask; 494 495 snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_1, 496 CDC_A_MBHC_DET_CTL_L_DET_EN | 497 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION | 498 CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO | 499 CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN); 500 501 if (wcd->hphl_jack_type_normally_open) 502 plug_type |= CDC_A_HPHL_PLUG_TYPE_NO; 503 504 if (wcd->gnd_jack_type_normally_open) 505 plug_type |= CDC_A_GND_PLUG_TYPE_NO; 506 507 snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_2, 508 CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 | 509 CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD | 510 plug_type | 511 CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN); 512 513 514 snd_soc_component_write(component, CDC_A_MBHC_DBNC_TIMER, 515 CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS | 516 CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS); 517 518 /* enable MBHC clock */ 519 snd_soc_component_update_bits(component, CDC_D_CDC_DIG_CLK_CTL, 520 DIG_CLK_CTL_D_MBHC_CLK_EN_MASK, 521 DIG_CLK_CTL_D_MBHC_CLK_EN); 522 523 if (snd_soc_component_read(component, CDC_A_MICB_2_EN) & CDC_A_MICB_2_EN_ENABLE) 524 micbias_enabled = true; 525 526 pm8916_mbhc_configure_bias(wcd, micbias_enabled); 527 528 int_en_mask = MBHC_SWITCH_INT; 529 if (wcd->mbhc_btn_enabled) 530 int_en_mask |= MBHC_BUTTON_PRESS_DET | MBHC_BUTTON_RELEASE_DET; 531 532 snd_soc_component_update_bits(component, CDC_D_INT_EN_CLR, int_en_mask, 0); 533 snd_soc_component_update_bits(component, CDC_D_INT_EN_SET, int_en_mask, int_en_mask); 534 wcd->mbhc_btn0_released = false; 535 wcd->detect_accessory_type = true; 536 } 537 538 static int pm8916_wcd_analog_enable_micbias_int2(struct 539 snd_soc_dapm_widget 540 *w, struct snd_kcontrol 541 *kcontrol, int event) 542 { 543 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 544 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 545 546 switch (event) { 547 case SND_SOC_DAPM_PRE_PMU: 548 snd_soc_component_update_bits(component, CDC_A_MICB_2_EN, 549 CDC_A_MICB_2_PULL_DOWN_EN_MASK, 0); 550 break; 551 case SND_SOC_DAPM_POST_PMU: 552 pm8916_mbhc_configure_bias(wcd, true); 553 break; 554 case SND_SOC_DAPM_POST_PMD: 555 pm8916_mbhc_configure_bias(wcd, false); 556 break; 557 } 558 559 return pm8916_wcd_analog_enable_micbias_int(w, kcontrol, event); 560 } 561 562 static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w, 563 struct snd_kcontrol *kcontrol, 564 int event) 565 { 566 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 567 u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2; 568 u8 init_bit_shift; 569 570 if (w->reg == CDC_A_TX_1_EN) 571 init_bit_shift = 5; 572 else 573 init_bit_shift = 4; 574 575 switch (event) { 576 case SND_SOC_DAPM_PRE_PMU: 577 if (w->reg == CDC_A_TX_2_EN) 578 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, 579 MICB_1_CTL_CFILT_REF_SEL_MASK, 580 MICB_1_CTL_CFILT_REF_SEL_HPF_REF); 581 /* 582 * Add delay of 10 ms to give sufficient time for the voltage 583 * to shoot up and settle so that the txfe init does not 584 * happen when the input voltage is changing too much. 585 */ 586 usleep_range(10000, 10010); 587 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 588 1 << init_bit_shift); 589 switch (w->reg) { 590 case CDC_A_TX_1_EN: 591 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL, 592 CONN_TX1_SERIAL_TX1_MUX, 593 CONN_TX1_SERIAL_TX1_ADC_1); 594 break; 595 case CDC_A_TX_2_EN: 596 case CDC_A_TX_3_EN: 597 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL, 598 CONN_TX2_SERIAL_TX2_MUX, 599 CONN_TX2_SERIAL_TX2_ADC_2); 600 break; 601 } 602 break; 603 case SND_SOC_DAPM_POST_PMU: 604 /* 605 * Add delay of 12 ms before deasserting the init 606 * to reduce the tx pop 607 */ 608 usleep_range(12000, 12010); 609 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 0x00); 610 break; 611 case SND_SOC_DAPM_POST_PMD: 612 switch (w->reg) { 613 case CDC_A_TX_1_EN: 614 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL, 615 CONN_TX1_SERIAL_TX1_MUX, 616 CONN_TX1_SERIAL_TX1_ZERO); 617 break; 618 case CDC_A_TX_2_EN: 619 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, 620 MICB_1_CTL_CFILT_REF_SEL_MASK, 0); 621 fallthrough; 622 case CDC_A_TX_3_EN: 623 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL, 624 CONN_TX2_SERIAL_TX2_MUX, 625 CONN_TX2_SERIAL_TX2_ZERO); 626 break; 627 } 628 629 630 break; 631 } 632 return 0; 633 } 634 635 static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w, 636 struct snd_kcontrol *kcontrol, 637 int event) 638 { 639 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 640 641 switch (event) { 642 case SND_SOC_DAPM_PRE_PMU: 643 snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL, 644 SPKR_PWRSTG_CTL_DAC_EN_MASK | 645 SPKR_PWRSTG_CTL_BBM_MASK | 646 SPKR_PWRSTG_CTL_HBRDGE_EN_MASK | 647 SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 648 SPKR_PWRSTG_CTL_DAC_EN| 649 SPKR_PWRSTG_CTL_BBM_EN | 650 SPKR_PWRSTG_CTL_HBRDGE_EN | 651 SPKR_PWRSTG_CTL_CLAMP_EN); 652 653 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 654 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 655 RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE); 656 break; 657 case SND_SOC_DAPM_POST_PMU: 658 snd_soc_component_update_bits(component, CDC_A_SPKR_DRV_CTL, 659 SPKR_DRV_CTL_DEF_MASK, 660 SPKR_DRV_CTL_DEF_VAL); 661 snd_soc_component_update_bits(component, w->reg, 662 SPKR_DRV_CLASSD_PA_EN_MASK, 663 SPKR_DRV_CLASSD_PA_EN_ENABLE); 664 break; 665 case SND_SOC_DAPM_POST_PMD: 666 snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL, 667 SPKR_PWRSTG_CTL_DAC_EN_MASK| 668 SPKR_PWRSTG_CTL_BBM_MASK | 669 SPKR_PWRSTG_CTL_HBRDGE_EN_MASK | 670 SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0); 671 672 snd_soc_component_update_bits(component, CDC_A_SPKR_DAC_CTL, 673 SPKR_DAC_CTL_DAC_RESET_MASK, 674 SPKR_DAC_CTL_DAC_RESET_NORMAL); 675 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 676 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0); 677 break; 678 } 679 return 0; 680 } 681 682 static int pm8916_wcd_analog_enable_ear_pa(struct snd_soc_dapm_widget *w, 683 struct snd_kcontrol *kcontrol, 684 int event) 685 { 686 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 687 688 switch (event) { 689 case SND_SOC_DAPM_PRE_PMU: 690 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 691 RX_EAR_CTL_PA_SEL_MASK, RX_EAR_CTL_PA_SEL); 692 break; 693 case SND_SOC_DAPM_POST_PMU: 694 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 695 RX_EAR_CTL_PA_EAR_PA_EN_MASK, 696 RX_EAR_CTL_PA_EAR_PA_EN_ENABLE); 697 break; 698 case SND_SOC_DAPM_POST_PMD: 699 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 700 RX_EAR_CTL_PA_EAR_PA_EN_MASK, 0); 701 /* Delay to reduce ear turn off pop */ 702 usleep_range(7000, 7100); 703 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 704 RX_EAR_CTL_PA_SEL_MASK, 0); 705 break; 706 } 707 return 0; 708 } 709 710 static int pm8916_wcd_analog_enable_hphl_pa(struct snd_soc_dapm_widget *w, 711 struct snd_kcontrol *kcontrol, 712 int event) 713 { 714 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 715 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev); 716 717 /* This quirk is not required for revisions prior to CAJON_2_0 */ 718 if (priv->codec_version < 4) 719 return 0; 720 721 switch (event) { 722 case SND_SOC_DAPM_POST_PMU: 723 usleep_range(7000, 7100); 724 snd_soc_component_update_bits(component, CDC_A_RX_HPH_L_TEST, 725 0x04, 0x04); 726 break; 727 case SND_SOC_DAPM_POST_PMD: 728 /* wait 20 ms after the digital codec has powered down */ 729 msleep(20); 730 snd_soc_component_update_bits(component, CDC_A_RX_HPH_L_TEST, 731 0x04, 0x00); 732 break; 733 } 734 return 0; 735 } 736 737 static int pm8916_wcd_analog_enable_hphr_pa(struct snd_soc_dapm_widget *w, 738 struct snd_kcontrol *kcontrol, 739 int event) 740 { 741 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 742 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev); 743 744 /* This quirk is not required for revisions prior to CAJON_2_0 */ 745 if (priv->codec_version < 4) 746 return 0; 747 748 switch (event) { 749 case SND_SOC_DAPM_POST_PMU: 750 usleep_range(7000, 7100); 751 snd_soc_component_update_bits(component, CDC_A_RX_HPH_R_TEST, 752 0x04, 0x04); 753 break; 754 case SND_SOC_DAPM_POST_PMD: 755 msleep(20); 756 snd_soc_component_update_bits(component, CDC_A_RX_HPH_R_TEST, 757 0x04, 0x00); 758 break; 759 } 760 return 0; 761 } 762 763 static const struct reg_default wcd_reg_defaults_2_0[] = { 764 {CDC_A_RX_COM_OCP_CTL, 0xD1}, 765 {CDC_A_RX_COM_OCP_COUNT, 0xFF}, 766 {CDC_D_SEC_ACCESS, 0xA5}, 767 {CDC_D_PERPH_RESET_CTL3, 0x0F}, 768 {CDC_A_TX_1_2_OPAMP_BIAS, 0x4F}, 769 {CDC_A_NCP_FBCTRL, 0x28}, 770 {CDC_A_SPKR_DRV_CTL, 0x69}, 771 {CDC_A_SPKR_DRV_DBG, 0x01}, 772 {CDC_A_BOOST_EN_CTL, 0x5F}, 773 {CDC_A_SLOPE_COMP_IP_ZERO, 0x88}, 774 {CDC_A_SEC_ACCESS, 0xA5}, 775 {CDC_A_PERPH_RESET_CTL3, 0x0F}, 776 {CDC_A_CURRENT_LIMIT, 0x82}, 777 {CDC_A_SPKR_DAC_CTL, 0x03}, 778 {CDC_A_SPKR_OCP_CTL, 0xE1}, 779 {CDC_A_MASTER_BIAS_CTL, 0x30}, 780 }; 781 782 static const struct wcd_reg_seq pm8916_data = { 783 .seq = wcd_reg_defaults_2_0, 784 .seq_size = ARRAY_SIZE(wcd_reg_defaults_2_0), 785 }; 786 787 static const struct reg_default wcd_reg_defaults_pm8950[] = { 788 {CDC_A_RX_COM_OCP_CTL, 0xd1}, 789 {CDC_A_RX_COM_OCP_COUNT, 0xff}, 790 {CDC_D_SEC_ACCESS, 0xa5}, 791 {CDC_D_PERPH_RESET_CTL3, 0x0f}, 792 {CDC_A_TX_1_2_OPAMP_BIAS, 0x4c}, 793 {CDC_A_NCP_FBCTRL, 0xa8}, 794 {CDC_A_NCP_VCTRL, 0xa4}, 795 {CDC_A_SPKR_DRV_CTL, 0x69}, 796 {CDC_A_SPKR_DRV_DBG, 0x01}, 797 {CDC_A_SEC_ACCESS, 0xa5}, 798 {CDC_A_PERPH_RESET_CTL3, 0x0f}, 799 {CDC_A_CURRENT_LIMIT, 0x82}, 800 {CDC_A_SPKR_ANA_BIAS_SET, 0x41}, 801 {CDC_A_SPKR_DAC_CTL, 0x03}, 802 {CDC_A_SPKR_OCP_CTL, 0xe1}, 803 {CDC_A_RX_HPH_BIAS_PA, 0xfa}, 804 {CDC_A_MASTER_BIAS_CTL, 0x30}, 805 {CDC_A_MICB_1_INT_RBIAS, 0x00}, 806 }; 807 808 static const struct wcd_reg_seq pm8950_data = { 809 .seq = wcd_reg_defaults_pm8950, 810 .seq_size = ARRAY_SIZE(wcd_reg_defaults_pm8950), 811 }; 812 813 static const struct reg_default wcd_reg_defaults_pm8953[] = { 814 {CDC_A_RX_COM_OCP_CTL, 0xd1}, 815 {CDC_A_RX_COM_OCP_COUNT, 0xff}, 816 {CDC_D_SEC_ACCESS, 0xa5}, 817 {CDC_D_PERPH_RESET_CTL3, 0x0f}, 818 {CDC_A_TX_1_2_OPAMP_BIAS, 0x4c}, 819 {CDC_A_NCP_FBCTRL, 0xa8}, 820 {CDC_A_NCP_VCTRL, 0xa4}, 821 {CDC_A_SPKR_DRV_CTL, 0x69}, 822 {CDC_A_SPKR_DRV_DBG, 0x01}, 823 {CDC_A_SEC_ACCESS, 0xa5}, 824 {CDC_A_PERPH_RESET_CTL3, 0x0f}, 825 {CDC_A_CURRENT_LIMIT, 0xa2}, 826 {CDC_A_BYPASS_MODE, 0x18}, 827 {CDC_A_SPKR_ANA_BIAS_SET, 0x41}, 828 {CDC_A_SPKR_DAC_CTL, 0x03}, 829 {CDC_A_SPKR_OCP_CTL, 0xe1}, 830 {CDC_A_RX_HPH_BIAS_PA, 0xfa}, 831 {CDC_A_RX_EAR_STATUS, 0x10}, 832 {CDC_A_MASTER_BIAS_CTL, 0x30}, 833 {CDC_A_MICB_1_INT_RBIAS, 0x00}, 834 }; 835 836 static const struct wcd_reg_seq pm8953_data = { 837 .seq = wcd_reg_defaults_pm8953, 838 .seq_size = ARRAY_SIZE(wcd_reg_defaults_pm8953), 839 }; 840 841 static int pm8916_wcd_analog_probe(struct snd_soc_component *component) 842 { 843 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev); 844 const struct wcd_reg_seq *wcd_reg_init_data; 845 int err, reg; 846 847 err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 848 if (err != 0) { 849 dev_err(component->dev, "failed to enable regulators (%d)\n", err); 850 return err; 851 } 852 853 snd_soc_component_init_regmap(component, 854 dev_get_regmap(component->dev->parent, NULL)); 855 snd_soc_component_set_drvdata(component, priv); 856 priv->pmic_rev = snd_soc_component_read(component, CDC_D_REVISION1); 857 priv->codec_version = snd_soc_component_read(component, CDC_D_PERPH_SUBTYPE); 858 859 dev_info(component->dev, "PMIC REV: %d\t CODEC Version: %d\n", 860 priv->pmic_rev, priv->codec_version); 861 862 snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01); 863 snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01); 864 865 wcd_reg_init_data = of_device_get_match_data(component->dev); 866 867 for (reg = 0; reg < wcd_reg_init_data->seq_size; reg++) 868 snd_soc_component_write(component, wcd_reg_init_data->seq[reg].reg, 869 wcd_reg_init_data->seq[reg].def); 870 871 priv->component = component; 872 873 snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL, 874 RST_CTL_DIG_SW_RST_N_MASK, 875 RST_CTL_DIG_SW_RST_N_REMOVE_RESET); 876 877 pm8916_wcd_setup_mbhc(priv); 878 879 return 0; 880 } 881 882 static void pm8916_wcd_analog_remove(struct snd_soc_component *component) 883 { 884 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev); 885 886 snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL, 887 RST_CTL_DIG_SW_RST_N_MASK, 0); 888 889 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 890 priv->supplies); 891 } 892 893 static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = { 894 895 {"PDM_RX1", NULL, "PDM Playback"}, 896 {"PDM_RX2", NULL, "PDM Playback"}, 897 {"PDM_RX3", NULL, "PDM Playback"}, 898 {"PDM Capture", NULL, "PDM_TX"}, 899 900 /* ADC Connections */ 901 {"PDM_TX", NULL, "ADC2"}, 902 {"PDM_TX", NULL, "ADC3"}, 903 {"ADC2", NULL, "ADC2 MUX"}, 904 {"ADC3", NULL, "ADC2 MUX"}, 905 {"ADC2 MUX", "INP2", "ADC2_INP2"}, 906 {"ADC2 MUX", "INP3", "ADC2_INP3"}, 907 908 {"PDM_TX", NULL, "ADC1"}, 909 {"ADC1", NULL, "AMIC1"}, 910 {"ADC2_INP2", NULL, "AMIC2"}, 911 {"ADC2_INP3", NULL, "AMIC3"}, 912 913 /* RDAC Connections */ 914 {"HPHR DAC", NULL, "RDAC2 MUX"}, 915 {"RDAC2 MUX", "RX1", "PDM_RX1"}, 916 {"RDAC2 MUX", "RX2", "PDM_RX2"}, 917 {"HPHL DAC", NULL, "PDM_RX1"}, 918 {"PDM_RX1", NULL, "RXD1_CLK"}, 919 {"PDM_RX2", NULL, "RXD2_CLK"}, 920 {"PDM_RX3", NULL, "RXD3_CLK"}, 921 922 {"PDM_RX1", NULL, "RXD_PDM_CLK"}, 923 {"PDM_RX2", NULL, "RXD_PDM_CLK"}, 924 {"PDM_RX3", NULL, "RXD_PDM_CLK"}, 925 926 {"ADC1", NULL, "TXD_CLK"}, 927 {"ADC2", NULL, "TXD_CLK"}, 928 {"ADC3", NULL, "TXD_CLK"}, 929 930 {"ADC1", NULL, "TXA_CLK25"}, 931 {"ADC2", NULL, "TXA_CLK25"}, 932 {"ADC3", NULL, "TXA_CLK25"}, 933 934 {"PDM_RX1", NULL, "A_MCLK2"}, 935 {"PDM_RX2", NULL, "A_MCLK2"}, 936 {"PDM_RX3", NULL, "A_MCLK2"}, 937 938 {"PDM_TX", NULL, "A_MCLK2"}, 939 {"A_MCLK2", NULL, "A_MCLK"}, 940 941 /* Earpiece (RX MIX1) */ 942 {"EAR", NULL, "EAR_S"}, 943 {"EAR_S", "Switch", "EAR PA"}, 944 {"EAR PA", NULL, "RX_BIAS"}, 945 {"EAR PA", NULL, "HPHL DAC"}, 946 {"EAR PA", NULL, "HPHR DAC"}, 947 {"EAR PA", NULL, "EAR CP"}, 948 949 /* Headset (RX MIX1 and RX MIX2) */ 950 {"HPH_L", NULL, "HPHL PA"}, 951 {"HPH_R", NULL, "HPHR PA"}, 952 953 {"HPHL DAC", NULL, "EAR_HPHL_CLK"}, 954 {"HPHR DAC", NULL, "EAR_HPHR_CLK"}, 955 956 {"CP", NULL, "NCP_CLK"}, 957 958 {"HPHL PA", NULL, "HPHL"}, 959 {"HPHR PA", NULL, "HPHR"}, 960 {"HPHL PA", NULL, "CP"}, 961 {"HPHL PA", NULL, "RX_BIAS"}, 962 {"HPHR PA", NULL, "CP"}, 963 {"HPHR PA", NULL, "RX_BIAS"}, 964 {"HPHL", "Switch", "HPHL DAC"}, 965 {"HPHR", "Switch", "HPHR DAC"}, 966 967 {"RX_BIAS", NULL, "DAC_REF"}, 968 969 {"SPK_OUT", NULL, "SPK PA"}, 970 {"SPK PA", NULL, "RX_BIAS"}, 971 {"SPK PA", NULL, "SPKR_CLK"}, 972 {"SPK PA", NULL, "SPK DAC"}, 973 {"SPK DAC", "Switch", "PDM_RX3"}, 974 975 {"MIC_BIAS1", NULL, "INT_LDO_H"}, 976 {"MIC_BIAS2", NULL, "INT_LDO_H"}, 977 {"MIC_BIAS1", NULL, "vdd-micbias"}, 978 {"MIC_BIAS2", NULL, "vdd-micbias"}, 979 980 {"MIC BIAS External1", NULL, "MIC_BIAS1"}, 981 {"MIC BIAS Internal1", NULL, "MIC_BIAS1"}, 982 {"MIC BIAS External2", NULL, "MIC_BIAS2"}, 983 {"MIC BIAS Internal2", NULL, "MIC_BIAS2"}, 984 {"MIC BIAS Internal3", NULL, "MIC_BIAS1"}, 985 }; 986 987 static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = { 988 989 SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0), 990 SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0), 991 SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0), 992 SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0), 993 994 SND_SOC_DAPM_INPUT("AMIC1"), 995 SND_SOC_DAPM_INPUT("AMIC3"), 996 SND_SOC_DAPM_INPUT("AMIC2"), 997 SND_SOC_DAPM_OUTPUT("EAR"), 998 SND_SOC_DAPM_OUTPUT("HPH_L"), 999 SND_SOC_DAPM_OUTPUT("HPH_R"), 1000 1001 /* RX stuff */ 1002 SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0), 1003 1004 SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM, 1005 0, 0, NULL, 0, 1006 pm8916_wcd_analog_enable_ear_pa, 1007 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1008 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1009 SND_SOC_DAPM_MUX("EAR_S", SND_SOC_NOPM, 0, 0, &ear_mux), 1010 SND_SOC_DAPM_SUPPLY("EAR CP", CDC_A_NCP_EN, 4, 0, NULL, 0), 1011 1012 SND_SOC_DAPM_PGA_E("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0, 1013 pm8916_wcd_analog_enable_hphl_pa, 1014 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1015 SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux), 1016 SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL, 1017 0), 1018 SND_SOC_DAPM_PGA_E("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0, 1019 pm8916_wcd_analog_enable_hphr_pa, 1020 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1021 SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux), 1022 SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL, 1023 0), 1024 SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0, 1025 spkr_switch, ARRAY_SIZE(spkr_switch)), 1026 1027 /* Speaker */ 1028 SND_SOC_DAPM_OUTPUT("SPK_OUT"), 1029 SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL, 1030 6, 0, NULL, 0, 1031 pm8916_wcd_analog_enable_spk_pa, 1032 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1033 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1034 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0), 1035 SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0), 1036 1037 SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0), 1038 SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0), 1039 1040 /* TX */ 1041 SND_SOC_DAPM_SUPPLY("MIC_BIAS1", CDC_A_MICB_1_EN, 7, 0, 1042 pm8916_wcd_analog_enable_micbias1, 1043 SND_SOC_DAPM_POST_PMU), 1044 SND_SOC_DAPM_SUPPLY("MIC_BIAS2", CDC_A_MICB_2_EN, 7, 0, 1045 pm8916_wcd_analog_enable_micbias2, 1046 SND_SOC_DAPM_POST_PMU), 1047 1048 SND_SOC_DAPM_SUPPLY("MIC BIAS External1", SND_SOC_NOPM, 0, 0, NULL, 0), 1049 SND_SOC_DAPM_SUPPLY("MIC BIAS External2", SND_SOC_NOPM, 0, 0, NULL, 0), 1050 1051 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_INT_RBIAS, 7, 0, 1052 pm8916_wcd_analog_enable_micbias_int, 1053 SND_SOC_DAPM_PRE_PMU), 1054 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_1_INT_RBIAS, 4, 0, 1055 pm8916_wcd_analog_enable_micbias_int2, 1056 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1057 SND_SOC_DAPM_POST_PMD), 1058 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal3", CDC_A_MICB_1_INT_RBIAS, 1, 0, 1059 pm8916_wcd_analog_enable_micbias_int, 1060 SND_SOC_DAPM_PRE_PMU), 1061 1062 SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0, 1063 pm8916_wcd_analog_enable_adc, 1064 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1065 SND_SOC_DAPM_POST_PMD), 1066 SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0, 1067 pm8916_wcd_analog_enable_adc, 1068 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1069 SND_SOC_DAPM_POST_PMD), 1070 SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0, 1071 pm8916_wcd_analog_enable_adc, 1072 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1073 SND_SOC_DAPM_POST_PMD), 1074 1075 SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 1076 SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 1077 1078 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 1079 SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux), 1080 1081 /* Analog path clocks */ 1082 SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL, 1083 0), 1084 SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL, 1085 0), 1086 SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0), 1087 SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0), 1088 1089 /* Digital path clocks */ 1090 1091 SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0), 1092 SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0), 1093 SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0), 1094 1095 SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0), 1096 SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0), 1097 SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL, 1098 0), 1099 1100 /* System Clock source */ 1101 SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0), 1102 /* TX ADC and RX DAC Clock source. */ 1103 SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0), 1104 }; 1105 1106 static int pm8916_wcd_analog_set_jack(struct snd_soc_component *component, 1107 struct snd_soc_jack *jack, 1108 void *data) 1109 { 1110 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 1111 1112 wcd->jack = jack; 1113 1114 return 0; 1115 } 1116 1117 static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg) 1118 { 1119 struct pm8916_wcd_analog_priv *priv = arg; 1120 1121 if (priv->detect_accessory_type) { 1122 struct snd_soc_component *component = priv->component; 1123 u32 val = snd_soc_component_read(component, CDC_A_MBHC_RESULT_1); 1124 1125 /* check if its BTN0 thats released */ 1126 if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK)) 1127 priv->mbhc_btn0_released = true; 1128 1129 } else { 1130 snd_soc_jack_report(priv->jack, 0, btn_mask); 1131 } 1132 1133 return IRQ_HANDLED; 1134 } 1135 1136 static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg) 1137 { 1138 struct pm8916_wcd_analog_priv *priv = arg; 1139 struct snd_soc_component *component = priv->component; 1140 u32 btn_result; 1141 1142 btn_result = snd_soc_component_read(component, CDC_A_MBHC_RESULT_1) & 1143 CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK; 1144 1145 switch (btn_result) { 1146 case 0xf: 1147 snd_soc_jack_report(priv->jack, SND_JACK_BTN_4, btn_mask); 1148 break; 1149 case 0x7: 1150 snd_soc_jack_report(priv->jack, SND_JACK_BTN_3, btn_mask); 1151 break; 1152 case 0x3: 1153 snd_soc_jack_report(priv->jack, SND_JACK_BTN_2, btn_mask); 1154 break; 1155 case 0x1: 1156 snd_soc_jack_report(priv->jack, SND_JACK_BTN_1, btn_mask); 1157 break; 1158 case 0x0: 1159 /* handle BTN_0 specially for type detection */ 1160 if (!priv->detect_accessory_type) 1161 snd_soc_jack_report(priv->jack, 1162 SND_JACK_BTN_0, btn_mask); 1163 break; 1164 default: 1165 dev_err(component->dev, 1166 "Unexpected button press result (%x)", btn_result); 1167 break; 1168 } 1169 1170 return IRQ_HANDLED; 1171 } 1172 1173 static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg) 1174 { 1175 struct pm8916_wcd_analog_priv *priv = arg; 1176 struct snd_soc_component *component = priv->component; 1177 bool ins = false; 1178 1179 if (snd_soc_component_read(component, CDC_A_MBHC_DET_CTL_1) & 1180 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK) 1181 ins = true; 1182 1183 /* Set the detection type appropriately */ 1184 snd_soc_component_update_bits(component, CDC_A_MBHC_DET_CTL_1, 1185 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK, 1186 (!ins << CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT)); 1187 1188 1189 if (ins) { /* hs insertion */ 1190 bool micbias_enabled = false; 1191 1192 if (snd_soc_component_read(component, CDC_A_MICB_2_EN) & 1193 CDC_A_MICB_2_EN_ENABLE) 1194 micbias_enabled = true; 1195 1196 pm8916_mbhc_configure_bias(priv, micbias_enabled); 1197 1198 /* 1199 * if only a btn0 press event is receive just before 1200 * insert event then its a 3 pole headphone else if 1201 * both press and release event received then its 1202 * a headset. 1203 */ 1204 if (priv->mbhc_btn0_released) 1205 snd_soc_jack_report(priv->jack, 1206 SND_JACK_HEADSET, hs_jack_mask); 1207 else 1208 snd_soc_jack_report(priv->jack, 1209 SND_JACK_HEADPHONE, hs_jack_mask); 1210 1211 priv->detect_accessory_type = false; 1212 1213 } else { /* removal */ 1214 snd_soc_jack_report(priv->jack, 0, hs_jack_mask); 1215 priv->detect_accessory_type = true; 1216 priv->mbhc_btn0_released = false; 1217 } 1218 1219 return IRQ_HANDLED; 1220 } 1221 1222 static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = { 1223 [0] = { 1224 .name = "pm8916_wcd_analog_pdm_rx", 1225 .id = 0, 1226 .playback = { 1227 .stream_name = "PDM Playback", 1228 .rates = MSM8916_WCD_ANALOG_RATES, 1229 .formats = MSM8916_WCD_ANALOG_FORMATS, 1230 .channels_min = 1, 1231 .channels_max = 3, 1232 }, 1233 }, 1234 [1] = { 1235 .name = "pm8916_wcd_analog_pdm_tx", 1236 .id = 1, 1237 .capture = { 1238 .stream_name = "PDM Capture", 1239 .rates = MSM8916_WCD_ANALOG_RATES, 1240 .formats = MSM8916_WCD_ANALOG_FORMATS, 1241 .channels_min = 1, 1242 .channels_max = 4, 1243 }, 1244 }, 1245 }; 1246 1247 static const struct snd_soc_component_driver pm8916_wcd_analog = { 1248 .probe = pm8916_wcd_analog_probe, 1249 .remove = pm8916_wcd_analog_remove, 1250 .set_jack = pm8916_wcd_analog_set_jack, 1251 .controls = pm8916_wcd_analog_snd_controls, 1252 .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls), 1253 .dapm_widgets = pm8916_wcd_analog_dapm_widgets, 1254 .num_dapm_widgets = ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets), 1255 .dapm_routes = pm8916_wcd_analog_audio_map, 1256 .num_dapm_routes = ARRAY_SIZE(pm8916_wcd_analog_audio_map), 1257 .idle_bias_on = 1, 1258 .use_pmdown_time = 1, 1259 .endianness = 1, 1260 }; 1261 1262 static int pm8916_wcd_analog_parse_dt(struct device *dev, 1263 struct pm8916_wcd_analog_priv *priv) 1264 { 1265 int rval; 1266 1267 if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap")) 1268 priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP; 1269 else 1270 priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP; 1271 1272 if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap")) 1273 priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP; 1274 else 1275 priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP; 1276 1277 of_property_read_u32(dev->of_node, "qcom,micbias-lvl", 1278 &priv->micbias_mv); 1279 1280 if (of_property_read_bool(dev->of_node, 1281 "qcom,hphl-jack-type-normally-open")) 1282 priv->hphl_jack_type_normally_open = true; 1283 else 1284 priv->hphl_jack_type_normally_open = false; 1285 1286 if (of_property_read_bool(dev->of_node, 1287 "qcom,gnd-jack-type-normally-open")) 1288 priv->gnd_jack_type_normally_open = true; 1289 else 1290 priv->gnd_jack_type_normally_open = false; 1291 1292 priv->mbhc_btn_enabled = true; 1293 rval = of_property_read_u32_array(dev->of_node, 1294 "qcom,mbhc-vthreshold-low", 1295 &priv->vref_btn_cs[0], 1296 MBHC_MAX_BUTTONS); 1297 if (rval < 0) { 1298 priv->mbhc_btn_enabled = false; 1299 } else { 1300 rval = of_property_read_u32_array(dev->of_node, 1301 "qcom,mbhc-vthreshold-high", 1302 &priv->vref_btn_micb[0], 1303 MBHC_MAX_BUTTONS); 1304 if (rval < 0) 1305 priv->mbhc_btn_enabled = false; 1306 } 1307 1308 if (!priv->mbhc_btn_enabled) 1309 dev_err(dev, 1310 "DT property missing, MBHC btn detection disabled\n"); 1311 1312 1313 return 0; 1314 } 1315 1316 static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev) 1317 { 1318 struct pm8916_wcd_analog_priv *priv; 1319 struct device *dev = &pdev->dev; 1320 int ret, i, irq; 1321 1322 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1323 if (!priv) 1324 return -ENOMEM; 1325 1326 ret = pm8916_wcd_analog_parse_dt(dev, priv); 1327 if (ret < 0) 1328 return ret; 1329 1330 for (i = 0; i < ARRAY_SIZE(supply_names); i++) 1331 priv->supplies[i].supply = supply_names[i]; 1332 1333 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies), 1334 priv->supplies); 1335 if (ret) { 1336 dev_err(dev, "Failed to get regulator supplies %d\n", ret); 1337 return ret; 1338 } 1339 1340 irq = platform_get_irq_byname(pdev, "mbhc_switch_int"); 1341 if (irq < 0) 1342 return irq; 1343 1344 ret = devm_request_threaded_irq(dev, irq, NULL, 1345 pm8916_mbhc_switch_irq_handler, 1346 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | 1347 IRQF_ONESHOT, 1348 "mbhc switch irq", priv); 1349 if (ret) { 1350 dev_err(dev, "cannot request mbhc switch irq\n"); 1351 return ret; 1352 } 1353 1354 if (priv->mbhc_btn_enabled) { 1355 irq = platform_get_irq_byname(pdev, "mbhc_but_press_det"); 1356 if (irq < 0) 1357 return irq; 1358 1359 ret = devm_request_threaded_irq(dev, irq, NULL, 1360 mbhc_btn_press_irq_handler, 1361 IRQF_TRIGGER_RISING | 1362 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1363 "mbhc btn press irq", priv); 1364 if (ret) { 1365 dev_err(dev, "cannot request mbhc button press irq\n"); 1366 return ret; 1367 } 1368 1369 irq = platform_get_irq_byname(pdev, "mbhc_but_rel_det"); 1370 if (irq < 0) 1371 return irq; 1372 1373 ret = devm_request_threaded_irq(dev, irq, NULL, 1374 mbhc_btn_release_irq_handler, 1375 IRQF_TRIGGER_RISING | 1376 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1377 "mbhc btn release irq", priv); 1378 if (ret) { 1379 dev_err(dev, "cannot request mbhc button release irq\n"); 1380 return ret; 1381 } 1382 } 1383 1384 dev_set_drvdata(dev, priv); 1385 1386 return devm_snd_soc_register_component(dev, &pm8916_wcd_analog, 1387 pm8916_wcd_analog_dai, 1388 ARRAY_SIZE(pm8916_wcd_analog_dai)); 1389 } 1390 1391 static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = { 1392 { .compatible = "qcom,pm8916-wcd-analog-codec", .data = &pm8916_data }, 1393 { .compatible = "qcom,pm8950-wcd-analog-codec", .data = &pm8950_data }, 1394 { .compatible = "qcom,pm8953-wcd-analog-codec", .data = &pm8953_data }, 1395 { } 1396 }; 1397 1398 MODULE_DEVICE_TABLE(of, pm8916_wcd_analog_spmi_match_table); 1399 1400 static struct platform_driver pm8916_wcd_analog_spmi_driver = { 1401 .driver = { 1402 .name = "qcom,pm8916-wcd-spmi-codec", 1403 .of_match_table = pm8916_wcd_analog_spmi_match_table, 1404 }, 1405 .probe = pm8916_wcd_analog_spmi_probe, 1406 }; 1407 1408 module_platform_driver(pm8916_wcd_analog_spmi_driver); 1409 1410 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>"); 1411 MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver"); 1412 MODULE_LICENSE("GPL v2"); 1413