1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/arm/coresight-cti-dt.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/stm32mp13-clks.h> 9#include <dt-bindings/reset/stm32mp13-resets.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a7"; 21 device_type = "cpu"; 22 reg = <0>; 23 }; 24 }; 25 26 arm-pmu { 27 compatible = "arm,cortex-a7-pmu"; 28 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 29 interrupt-affinity = <&cpu0>; 30 interrupt-parent = <&intc>; 31 }; 32 33 arm_wdt: watchdog { 34 compatible = "arm,smc-wdt"; 35 arm,smc-id = <0xbc000000>; 36 status = "disabled"; 37 }; 38 39 firmware { 40 optee { 41 method = "smc"; 42 compatible = "linaro,optee-tz"; 43 interrupt-parent = <&intc>; 44 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 45 }; 46 47 scmi: scmi { 48 compatible = "linaro,scmi-optee"; 49 #address-cells = <1>; 50 #size-cells = <0>; 51 linaro,optee-channel-id = <0>; 52 53 scmi_clk: protocol@14 { 54 reg = <0x14>; 55 #clock-cells = <1>; 56 }; 57 58 scmi_reset: protocol@16 { 59 reg = <0x16>; 60 #reset-cells = <1>; 61 }; 62 63 scmi_voltd: protocol@17 { 64 reg = <0x17>; 65 66 scmi_regu: regulators { 67 #address-cells = <1>; 68 #size-cells = <0>; 69 70 scmi_reg11: regulator@0 { 71 reg = <VOLTD_SCMI_REG11>; 72 regulator-name = "reg11"; 73 }; 74 scmi_reg18: regulator@1 { 75 reg = <VOLTD_SCMI_REG18>; 76 regulator-name = "reg18"; 77 }; 78 scmi_usb33: regulator@2 { 79 reg = <VOLTD_SCMI_USB33>; 80 regulator-name = "usb33"; 81 }; 82 }; 83 }; 84 }; 85 }; 86 87 intc: interrupt-controller@a0021000 { 88 compatible = "arm,cortex-a7-gic"; 89 #interrupt-cells = <3>; 90 interrupt-controller; 91 reg = <0xa0021000 0x1000>, 92 <0xa0022000 0x2000>; 93 }; 94 95 psci { 96 compatible = "arm,psci-1.0"; 97 method = "smc"; 98 }; 99 100 timer { 101 compatible = "arm,armv7-timer"; 102 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 103 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 104 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 105 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 106 interrupt-parent = <&intc>; 107 always-on; 108 }; 109 110 thermal-zones { 111 cpu_thermal: cpu-thermal { 112 polling-delay-passive = <0>; 113 polling-delay = <0>; 114 thermal-sensors = <&dts>; 115 116 trips { 117 cpu_alert1: cpu-alert1 { 118 temperature = <85000>; 119 hysteresis = <0>; 120 type = "passive"; 121 }; 122 123 cpu-crit { 124 temperature = <120000>; 125 hysteresis = <0>; 126 type = "critical"; 127 }; 128 }; 129 130 cooling-maps { 131 }; 132 }; 133 }; 134 135 soc { 136 compatible = "simple-bus"; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 interrupt-parent = <&intc>; 140 ranges; 141 142 timers2: timer@40000000 { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 compatible = "st,stm32-timers"; 146 reg = <0x40000000 0x400>; 147 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 148 interrupt-names = "global"; 149 clocks = <&rcc TIM2_K>; 150 clock-names = "int"; 151 dmas = <&dmamux1 18 0x400 0x1>, 152 <&dmamux1 19 0x400 0x1>, 153 <&dmamux1 20 0x400 0x1>, 154 <&dmamux1 21 0x400 0x1>, 155 <&dmamux1 22 0x400 0x1>; 156 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 157 status = "disabled"; 158 159 pwm { 160 compatible = "st,stm32-pwm"; 161 #pwm-cells = <3>; 162 status = "disabled"; 163 }; 164 165 timer@1 { 166 compatible = "st,stm32h7-timer-trigger"; 167 reg = <1>; 168 status = "disabled"; 169 }; 170 171 counter { 172 compatible = "st,stm32-timer-counter"; 173 status = "disabled"; 174 }; 175 }; 176 177 timers3: timer@40001000 { 178 #address-cells = <1>; 179 #size-cells = <0>; 180 compatible = "st,stm32-timers"; 181 reg = <0x40001000 0x400>; 182 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 183 interrupt-names = "global"; 184 clocks = <&rcc TIM3_K>; 185 clock-names = "int"; 186 dmas = <&dmamux1 23 0x400 0x1>, 187 <&dmamux1 24 0x400 0x1>, 188 <&dmamux1 25 0x400 0x1>, 189 <&dmamux1 26 0x400 0x1>, 190 <&dmamux1 27 0x400 0x1>, 191 <&dmamux1 28 0x400 0x1>; 192 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 193 status = "disabled"; 194 195 pwm { 196 compatible = "st,stm32-pwm"; 197 #pwm-cells = <3>; 198 status = "disabled"; 199 }; 200 201 timer@2 { 202 compatible = "st,stm32h7-timer-trigger"; 203 reg = <2>; 204 status = "disabled"; 205 }; 206 207 counter { 208 compatible = "st,stm32-timer-counter"; 209 status = "disabled"; 210 }; 211 }; 212 213 timers4: timer@40002000 { 214 #address-cells = <1>; 215 #size-cells = <0>; 216 compatible = "st,stm32-timers"; 217 reg = <0x40002000 0x400>; 218 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 219 interrupt-names = "global"; 220 clocks = <&rcc TIM4_K>; 221 clock-names = "int"; 222 dmas = <&dmamux1 29 0x400 0x1>, 223 <&dmamux1 30 0x400 0x1>, 224 <&dmamux1 31 0x400 0x1>, 225 <&dmamux1 32 0x400 0x1>; 226 dma-names = "ch1", "ch2", "ch3", "up"; 227 status = "disabled"; 228 229 pwm { 230 compatible = "st,stm32-pwm"; 231 #pwm-cells = <3>; 232 status = "disabled"; 233 }; 234 235 timer@3 { 236 compatible = "st,stm32h7-timer-trigger"; 237 reg = <3>; 238 status = "disabled"; 239 }; 240 241 counter { 242 compatible = "st,stm32-timer-counter"; 243 status = "disabled"; 244 }; 245 }; 246 247 timers5: timer@40003000 { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 compatible = "st,stm32-timers"; 251 reg = <0x40003000 0x400>; 252 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 253 interrupt-names = "global"; 254 clocks = <&rcc TIM5_K>; 255 clock-names = "int"; 256 dmas = <&dmamux1 55 0x400 0x1>, 257 <&dmamux1 56 0x400 0x1>, 258 <&dmamux1 57 0x400 0x1>, 259 <&dmamux1 58 0x400 0x1>, 260 <&dmamux1 59 0x400 0x1>, 261 <&dmamux1 60 0x400 0x1>; 262 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 263 status = "disabled"; 264 265 pwm { 266 compatible = "st,stm32-pwm"; 267 #pwm-cells = <3>; 268 status = "disabled"; 269 }; 270 271 timer@4 { 272 compatible = "st,stm32h7-timer-trigger"; 273 reg = <4>; 274 status = "disabled"; 275 }; 276 277 counter { 278 compatible = "st,stm32-timer-counter"; 279 status = "disabled"; 280 }; 281 }; 282 283 timers6: timer@40004000 { 284 #address-cells = <1>; 285 #size-cells = <0>; 286 compatible = "st,stm32-timers"; 287 reg = <0x40004000 0x400>; 288 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 289 interrupt-names = "global"; 290 clocks = <&rcc TIM6_K>; 291 clock-names = "int"; 292 dmas = <&dmamux1 69 0x400 0x1>; 293 dma-names = "up"; 294 status = "disabled"; 295 296 counter { 297 compatible = "st,stm32-timer-counter"; 298 status = "disabled"; 299 }; 300 301 timer@5 { 302 compatible = "st,stm32h7-timer-trigger"; 303 reg = <5>; 304 status = "disabled"; 305 }; 306 }; 307 308 timers7: timer@40005000 { 309 #address-cells = <1>; 310 #size-cells = <0>; 311 compatible = "st,stm32-timers"; 312 reg = <0x40005000 0x400>; 313 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 314 interrupt-names = "global"; 315 clocks = <&rcc TIM7_K>; 316 clock-names = "int"; 317 dmas = <&dmamux1 70 0x400 0x1>; 318 dma-names = "up"; 319 status = "disabled"; 320 321 counter { 322 compatible = "st,stm32-timer-counter"; 323 status = "disabled"; 324 }; 325 326 timer@6 { 327 compatible = "st,stm32h7-timer-trigger"; 328 reg = <6>; 329 status = "disabled"; 330 }; 331 }; 332 333 lptimer1: timer@40009000 { 334 #address-cells = <1>; 335 #size-cells = <0>; 336 compatible = "st,stm32-lptimer"; 337 reg = <0x40009000 0x400>; 338 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&rcc LPTIM1_K>; 340 clock-names = "mux"; 341 wakeup-source; 342 status = "disabled"; 343 344 pwm { 345 compatible = "st,stm32-pwm-lp"; 346 #pwm-cells = <3>; 347 status = "disabled"; 348 }; 349 350 trigger@0 { 351 compatible = "st,stm32-lptimer-trigger"; 352 reg = <0>; 353 status = "disabled"; 354 }; 355 356 counter { 357 compatible = "st,stm32-lptimer-counter"; 358 status = "disabled"; 359 }; 360 361 timer { 362 compatible = "st,stm32-lptimer-timer"; 363 status = "disabled"; 364 }; 365 }; 366 367 i2s2: audio-controller@4000b000 { 368 compatible = "st,stm32h7-i2s"; 369 reg = <0x4000b000 0x400>; 370 #sound-dai-cells = <0>; 371 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 372 dmas = <&dmamux1 39 0x400 0x01>, 373 <&dmamux1 40 0x400 0x01>; 374 dma-names = "rx", "tx"; 375 status = "disabled"; 376 }; 377 378 spi2: spi@4000b000 { 379 compatible = "st,stm32h7-spi"; 380 reg = <0x4000b000 0x400>; 381 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&rcc SPI2_K>; 383 resets = <&rcc SPI2_R>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 dmas = <&dmamux1 39 0x400 0x01>, 387 <&dmamux1 40 0x400 0x01>; 388 dma-names = "rx", "tx"; 389 status = "disabled"; 390 }; 391 392 i2s3: audio-controller@4000c000 { 393 compatible = "st,stm32h7-i2s"; 394 reg = <0x4000c000 0x400>; 395 #sound-dai-cells = <0>; 396 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 397 dmas = <&dmamux1 61 0x400 0x01>, 398 <&dmamux1 62 0x400 0x01>; 399 dma-names = "rx", "tx"; 400 status = "disabled"; 401 }; 402 403 spi3: spi@4000c000 { 404 compatible = "st,stm32h7-spi"; 405 reg = <0x4000c000 0x400>; 406 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&rcc SPI3_K>; 408 resets = <&rcc SPI3_R>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 dmas = <&dmamux1 61 0x400 0x01>, 412 <&dmamux1 62 0x400 0x01>; 413 dma-names = "rx", "tx"; 414 status = "disabled"; 415 }; 416 417 spdifrx: audio-controller@4000d000 { 418 compatible = "st,stm32h7-spdifrx"; 419 reg = <0x4000d000 0x400>; 420 #sound-dai-cells = <0>; 421 clocks = <&rcc SPDIF_K>; 422 clock-names = "kclk"; 423 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 424 dmas = <&dmamux1 93 0x400 0x01>, 425 <&dmamux1 94 0x400 0x01>; 426 dma-names = "rx", "rx-ctrl"; 427 status = "disabled"; 428 }; 429 430 usart3: serial@4000f000 { 431 compatible = "st,stm32h7-uart"; 432 reg = <0x4000f000 0x400>; 433 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&rcc USART3_K>; 435 resets = <&rcc USART3_R>; 436 wakeup-source; 437 dmas = <&dmamux1 45 0x400 0x5>, 438 <&dmamux1 46 0x400 0x1>; 439 dma-names = "rx", "tx"; 440 status = "disabled"; 441 }; 442 443 uart4: serial@40010000 { 444 compatible = "st,stm32h7-uart"; 445 reg = <0x40010000 0x400>; 446 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&rcc UART4_K>; 448 resets = <&rcc UART4_R>; 449 wakeup-source; 450 dmas = <&dmamux1 63 0x400 0x5>, 451 <&dmamux1 64 0x400 0x1>; 452 dma-names = "rx", "tx"; 453 status = "disabled"; 454 }; 455 456 uart5: serial@40011000 { 457 compatible = "st,stm32h7-uart"; 458 reg = <0x40011000 0x400>; 459 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&rcc UART5_K>; 461 resets = <&rcc UART5_R>; 462 wakeup-source; 463 dmas = <&dmamux1 65 0x400 0x5>, 464 <&dmamux1 66 0x400 0x1>; 465 dma-names = "rx", "tx"; 466 status = "disabled"; 467 }; 468 469 i2c1: i2c@40012000 { 470 compatible = "st,stm32mp13-i2c"; 471 reg = <0x40012000 0x400>; 472 interrupt-names = "event", "error"; 473 interrupts-extended = <&exti 21 IRQ_TYPE_LEVEL_HIGH>, 474 <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&rcc I2C1_K>; 476 resets = <&rcc I2C1_R>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 dmas = <&dmamux1 33 0x400 0x1>, 480 <&dmamux1 34 0x400 0x1>; 481 dma-names = "rx", "tx"; 482 wakeup-source; 483 st,syscfg-fmp = <&syscfg 0x4 0x1>; 484 i2c-analog-filter; 485 status = "disabled"; 486 }; 487 488 i2c2: i2c@40013000 { 489 compatible = "st,stm32mp13-i2c"; 490 reg = <0x40013000 0x400>; 491 interrupt-names = "event", "error"; 492 interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>, 493 <&intc GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&rcc I2C2_K>; 495 resets = <&rcc I2C2_R>; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 dmas = <&dmamux1 35 0x400 0x1>, 499 <&dmamux1 36 0x400 0x1>; 500 dma-names = "rx", "tx"; 501 st,syscfg-fmp = <&syscfg 0x4 0x2>; 502 wakeup-source; 503 i2c-analog-filter; 504 status = "disabled"; 505 }; 506 507 uart7: serial@40018000 { 508 compatible = "st,stm32h7-uart"; 509 reg = <0x40018000 0x400>; 510 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&rcc UART7_K>; 512 resets = <&rcc UART7_R>; 513 wakeup-source; 514 dmas = <&dmamux1 79 0x400 0x5>, 515 <&dmamux1 80 0x400 0x1>; 516 dma-names = "rx", "tx"; 517 status = "disabled"; 518 }; 519 520 uart8: serial@40019000 { 521 compatible = "st,stm32h7-uart"; 522 reg = <0x40019000 0x400>; 523 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&rcc UART8_K>; 525 resets = <&rcc UART8_R>; 526 wakeup-source; 527 dmas = <&dmamux1 81 0x400 0x5>, 528 <&dmamux1 82 0x400 0x1>; 529 dma-names = "rx", "tx"; 530 status = "disabled"; 531 }; 532 533 timers1: timer@44000000 { 534 #address-cells = <1>; 535 #size-cells = <0>; 536 compatible = "st,stm32-timers"; 537 reg = <0x44000000 0x400>; 538 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 542 interrupt-names = "brk", "up", "trg-com", "cc"; 543 clocks = <&rcc TIM1_K>; 544 clock-names = "int"; 545 dmas = <&dmamux1 11 0x400 0x1>, 546 <&dmamux1 12 0x400 0x1>, 547 <&dmamux1 13 0x400 0x1>, 548 <&dmamux1 14 0x400 0x1>, 549 <&dmamux1 15 0x400 0x1>, 550 <&dmamux1 16 0x400 0x1>, 551 <&dmamux1 17 0x400 0x1>; 552 dma-names = "ch1", "ch2", "ch3", "ch4", 553 "up", "trig", "com"; 554 status = "disabled"; 555 556 pwm { 557 compatible = "st,stm32-pwm"; 558 #pwm-cells = <3>; 559 status = "disabled"; 560 }; 561 562 timer@0 { 563 compatible = "st,stm32h7-timer-trigger"; 564 reg = <0>; 565 status = "disabled"; 566 }; 567 568 counter { 569 compatible = "st,stm32-timer-counter"; 570 status = "disabled"; 571 }; 572 }; 573 574 timers8: timer@44001000 { 575 #address-cells = <1>; 576 #size-cells = <0>; 577 compatible = "st,stm32-timers"; 578 reg = <0x44001000 0x400>; 579 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 583 interrupt-names = "brk", "up", "trg-com", "cc"; 584 clocks = <&rcc TIM8_K>; 585 clock-names = "int"; 586 dmas = <&dmamux1 47 0x400 0x1>, 587 <&dmamux1 48 0x400 0x1>, 588 <&dmamux1 49 0x400 0x1>, 589 <&dmamux1 50 0x400 0x1>, 590 <&dmamux1 51 0x400 0x1>, 591 <&dmamux1 52 0x400 0x1>, 592 <&dmamux1 53 0x400 0x1>; 593 dma-names = "ch1", "ch2", "ch3", "ch4", 594 "up", "trig", "com"; 595 status = "disabled"; 596 597 pwm { 598 compatible = "st,stm32-pwm"; 599 #pwm-cells = <3>; 600 status = "disabled"; 601 }; 602 603 timer@7 { 604 compatible = "st,stm32h7-timer-trigger"; 605 reg = <7>; 606 status = "disabled"; 607 }; 608 609 counter { 610 compatible = "st,stm32-timer-counter"; 611 status = "disabled"; 612 }; 613 }; 614 615 usart6: serial@44003000 { 616 compatible = "st,stm32h7-uart"; 617 reg = <0x44003000 0x400>; 618 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&rcc USART6_K>; 620 resets = <&rcc USART6_R>; 621 wakeup-source; 622 dmas = <&dmamux1 71 0x400 0x5>, 623 <&dmamux1 72 0x400 0x1>; 624 dma-names = "rx", "tx"; 625 status = "disabled"; 626 }; 627 628 i2s1: audio-controller@44004000 { 629 compatible = "st,stm32h7-i2s"; 630 reg = <0x44004000 0x400>; 631 #sound-dai-cells = <0>; 632 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 633 dmas = <&dmamux1 37 0x400 0x01>, 634 <&dmamux1 38 0x400 0x01>; 635 dma-names = "rx", "tx"; 636 status = "disabled"; 637 }; 638 639 spi1: spi@44004000 { 640 compatible = "st,stm32h7-spi"; 641 reg = <0x44004000 0x400>; 642 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&rcc SPI1_K>; 644 resets = <&rcc SPI1_R>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 dmas = <&dmamux1 37 0x400 0x01>, 648 <&dmamux1 38 0x400 0x01>; 649 dma-names = "rx", "tx"; 650 status = "disabled"; 651 }; 652 653 sai1: sai@4400a000 { 654 compatible = "st,stm32h7-sai"; 655 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 656 ranges = <0 0x4400a000 0x400>; 657 #address-cells = <1>; 658 #size-cells = <1>; 659 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 660 resets = <&rcc SAI1_R>; 661 status = "disabled"; 662 663 sai1a: audio-controller@4400a004 { 664 compatible = "st,stm32-sai-sub-a"; 665 reg = <0x4 0x20>; 666 #sound-dai-cells = <0>; 667 clocks = <&rcc SAI1_K>; 668 clock-names = "sai_ck"; 669 dmas = <&dmamux1 87 0x400 0x01>; 670 status = "disabled"; 671 }; 672 673 sai1b: audio-controller@4400a024 { 674 compatible = "st,stm32-sai-sub-b"; 675 reg = <0x24 0x20>; 676 #sound-dai-cells = <0>; 677 clocks = <&rcc SAI1_K>; 678 clock-names = "sai_ck"; 679 dmas = <&dmamux1 88 0x400 0x01>; 680 status = "disabled"; 681 }; 682 }; 683 684 sai2: sai@4400b000 { 685 compatible = "st,stm32h7-sai"; 686 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 687 ranges = <0 0x4400b000 0x400>; 688 #address-cells = <1>; 689 #size-cells = <1>; 690 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 691 resets = <&rcc SAI2_R>; 692 status = "disabled"; 693 694 sai2a: audio-controller@4400b004 { 695 compatible = "st,stm32-sai-sub-a"; 696 reg = <0x4 0x20>; 697 #sound-dai-cells = <0>; 698 clocks = <&rcc SAI2_K>; 699 clock-names = "sai_ck"; 700 dmas = <&dmamux1 89 0x400 0x01>; 701 status = "disabled"; 702 }; 703 704 sai2b: audio-controller@4400b024 { 705 compatible = "st,stm32-sai-sub-b"; 706 reg = <0x24 0x20>; 707 #sound-dai-cells = <0>; 708 clocks = <&rcc SAI2_K>; 709 clock-names = "sai_ck"; 710 dmas = <&dmamux1 90 0x400 0x01>; 711 status = "disabled"; 712 }; 713 }; 714 715 dfsdm: dfsdm@4400d000 { 716 compatible = "st,stm32mp1-dfsdm"; 717 reg = <0x4400d000 0x800>; 718 clocks = <&rcc DFSDM_K>; 719 clock-names = "dfsdm"; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 status = "disabled"; 723 724 dfsdm0: filter@0 { 725 compatible = "st,stm32-dfsdm-adc"; 726 reg = <0>; 727 #io-channel-cells = <1>; 728 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 729 dmas = <&dmamux1 101 0x400 0x01>; 730 dma-names = "rx"; 731 status = "disabled"; 732 }; 733 734 dfsdm1: filter@1 { 735 compatible = "st,stm32-dfsdm-adc"; 736 reg = <1>; 737 #io-channel-cells = <1>; 738 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 739 dmas = <&dmamux1 102 0x400 0x01>; 740 dma-names = "rx"; 741 status = "disabled"; 742 }; 743 }; 744 745 dma1: dma-controller@48000000 { 746 compatible = "st,stm32-dma"; 747 reg = <0x48000000 0x400>; 748 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&rcc DMA1>; 757 resets = <&rcc DMA1_R>; 758 #dma-cells = <4>; 759 st,mem2mem; 760 dma-requests = <8>; 761 }; 762 763 dma2: dma-controller@48001000 { 764 compatible = "st,stm32-dma"; 765 reg = <0x48001000 0x400>; 766 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 774 clocks = <&rcc DMA2>; 775 resets = <&rcc DMA2_R>; 776 #dma-cells = <4>; 777 st,mem2mem; 778 dma-requests = <8>; 779 }; 780 781 dmamux1: dma-router@48002000 { 782 compatible = "st,stm32h7-dmamux"; 783 reg = <0x48002000 0x40>; 784 clocks = <&rcc DMAMUX1>; 785 resets = <&rcc DMAMUX1_R>; 786 #dma-cells = <3>; 787 dma-masters = <&dma1 &dma2>; 788 dma-requests = <128>; 789 dma-channels = <16>; 790 }; 791 792 rcc: rcc@50000000 { 793 compatible = "st,stm32mp13-rcc", "syscon"; 794 reg = <0x50000000 0x1000>; 795 #clock-cells = <1>; 796 #reset-cells = <1>; 797 clock-names = "hse", "hsi", "csi", "lse", "lsi"; 798 clocks = <&scmi_clk CK_SCMI_HSE>, 799 <&scmi_clk CK_SCMI_HSI>, 800 <&scmi_clk CK_SCMI_CSI>, 801 <&scmi_clk CK_SCMI_LSE>, 802 <&scmi_clk CK_SCMI_LSI>; 803 }; 804 805 pwr_regulators: pwr@50001000 { 806 compatible = "st,stm32mp1,pwr-reg"; 807 reg = <0x50001000 0x10>; 808 status = "disabled"; 809 810 reg11: reg11 { 811 regulator-name = "reg11"; 812 regulator-min-microvolt = <1100000>; 813 regulator-max-microvolt = <1100000>; 814 }; 815 816 reg18: reg18 { 817 regulator-name = "reg18"; 818 regulator-min-microvolt = <1800000>; 819 regulator-max-microvolt = <1800000>; 820 }; 821 822 usb33: usb33 { 823 regulator-name = "usb33"; 824 regulator-min-microvolt = <3300000>; 825 regulator-max-microvolt = <3300000>; 826 }; 827 }; 828 829 exti: interrupt-controller@5000d000 { 830 compatible = "st,stm32mp1-exti", "syscon"; 831 interrupt-controller; 832 #interrupt-cells = <2>; 833 reg = <0x5000d000 0x400>; 834 interrupts-extended = 835 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 836 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 837 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 838 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 839 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 840 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 841 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 842 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 843 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 844 <&intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 845 <&intc GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 846 <&intc GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 847 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 848 <&intc GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 849 <&intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 850 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 851 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 852 <0>, 853 <0>, 854 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 855 <0>, /* EXTI_20 */ 856 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 857 <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 858 <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 859 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 860 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 861 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 862 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 863 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 864 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 865 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 866 <&intc GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 867 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 868 <&intc GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 869 <0>, 870 <0>, 871 <0>, 872 <0>, 873 <0>, 874 <0>, 875 <0>, /* EXTI_40 */ 876 <0>, 877 <0>, 878 <0>, 879 <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 880 <0>, 881 <0>, 882 <&intc GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 883 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 884 <0>, 885 <&intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 886 <0>, 887 <&intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 888 <&intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 889 <0>, 890 <0>, 891 <0>, 892 <0>, 893 <0>, 894 <0>, 895 <0>, /* EXTI_60 */ 896 <0>, 897 <0>, 898 <0>, 899 <0>, 900 <0>, 901 <0>, 902 <0>, 903 <&intc GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 904 <0>, 905 <&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 906 }; 907 908 syscfg: syscon@50020000 { 909 compatible = "st,stm32mp157-syscfg", "syscon"; 910 reg = <0x50020000 0x400>; 911 clocks = <&rcc SYSCFG>; 912 }; 913 914 lptimer4: timer@50023000 { 915 compatible = "st,stm32-lptimer"; 916 reg = <0x50023000 0x400>; 917 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&rcc LPTIM4_K>; 919 clock-names = "mux"; 920 wakeup-source; 921 status = "disabled"; 922 923 pwm { 924 compatible = "st,stm32-pwm-lp"; 925 #pwm-cells = <3>; 926 status = "disabled"; 927 }; 928 929 timer { 930 compatible = "st,stm32-lptimer-timer"; 931 status = "disabled"; 932 }; 933 }; 934 935 lptimer5: timer@50024000 { 936 compatible = "st,stm32-lptimer"; 937 reg = <0x50024000 0x400>; 938 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 939 clocks = <&rcc LPTIM5_K>; 940 clock-names = "mux"; 941 wakeup-source; 942 status = "disabled"; 943 944 pwm { 945 compatible = "st,stm32-pwm-lp"; 946 #pwm-cells = <3>; 947 status = "disabled"; 948 }; 949 950 timer { 951 compatible = "st,stm32-lptimer-timer"; 952 status = "disabled"; 953 }; 954 }; 955 956 dts: thermal@50028000 { 957 compatible = "st,stm32-thermal"; 958 reg = <0x50028000 0x100>; 959 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&rcc DTS>; 961 clock-names = "pclk"; 962 #thermal-sensor-cells = <0>; 963 status = "disabled"; 964 }; 965 966 hdp: pinctrl@5002a000 { 967 compatible = "st,stm32mp131-hdp"; 968 reg = <0x5002a000 0x400>; 969 clocks = <&rcc HDP>; 970 access-controllers = <&dbg_bus 1>; 971 status = "disabled"; 972 }; 973 974 dbg_bus: bus@50080000 { 975 compatible = "st,stm32mp131-dbg-bus"; 976 #address-cells = <1>; 977 #size-cells = <1>; 978 #access-controller-cells = <1>; 979 ranges = <0x50080000 0x50080000 0x3f80000>; 980 status = "disabled"; 981 982 cs_etf: etf@50092000 { 983 compatible = "arm,coresight-tmc", "arm,primecell"; 984 reg = <0x50092000 0x1000>; 985 clocks = <&rcc CK_DBG>; 986 clock-names = "apb_pclk"; 987 access-controllers = <&dbg_bus 0>; 988 status = "disabled"; 989 990 in-ports { 991 port { 992 etf_in_port: endpoint { 993 remote-endpoint = <&etm0_out_port>; 994 }; 995 }; 996 }; 997 998 out-ports { 999 port { 1000 etf_out_port: endpoint { 1001 remote-endpoint = <&tpiu_in_port>; 1002 }; 1003 }; 1004 }; 1005 }; 1006 1007 cs_tpiu: tpiu@50093000 { 1008 compatible = "arm,coresight-tpiu", "arm,primecell"; 1009 reg = <0x50093000 0x1000>; 1010 clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; 1011 clock-names = "apb_pclk", "atclk"; 1012 access-controllers = <&dbg_bus 0>; 1013 status = "disabled"; 1014 1015 in-ports { 1016 port { 1017 tpiu_in_port: endpoint { 1018 remote-endpoint = <&etf_out_port>; 1019 }; 1020 }; 1021 }; 1022 }; 1023 1024 cs_cti_trace: cti@50094000 { 1025 compatible = "arm,coresight-cti", "arm,primecell"; 1026 reg = <0x50094000 0x1000>; 1027 clocks = <&rcc CK_DBG>; 1028 clock-names = "apb_pclk"; 1029 access-controllers = <&dbg_bus 0>; 1030 status = "disabled"; 1031 }; 1032 1033 cs_cti_cpu0: cti@500d8000 { 1034 compatible = "arm,coresight-cti", "arm,primecell"; 1035 reg = <0x500d8000 0x1000>; 1036 clocks = <&rcc CK_DBG>; 1037 clock-names = "apb_pclk"; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 access-controllers = <&dbg_bus 0>; 1041 status = "disabled"; 1042 1043 trig-conns@0 { 1044 reg = <0>; 1045 arm,trig-in-sigs = <0 4 5>; 1046 arm,trig-in-types = <PE_DBGTRIGGER 1047 GEN_IO 1048 GEN_IO>; 1049 arm,trig-out-sigs = <0 7>; 1050 arm,trig-out-types = <PE_EDBGREQ 1051 PE_DBGRESTART>; 1052 cpu = <&cpu0>; 1053 }; 1054 1055 trig-conns@2 { 1056 reg = <2>; 1057 arm,trig-in-sigs = <2 3 6>; 1058 arm,trig-in-types = <ETM_EXTOUT 1059 ETM_EXTOUT 1060 ETM_EXTOUT>; 1061 arm,trig-out-sigs = <1 2 3 4>; 1062 arm,trig-out-types = <ETM_EXTIN 1063 ETM_EXTIN 1064 ETM_EXTIN 1065 ETM_EXTIN>; 1066 arm,cs-dev-assoc = <&cs_etm0>; 1067 }; 1068 }; 1069 1070 cs_etm0: etm@500dc000 { 1071 compatible = "arm,coresight-etm3x", "arm,primecell"; 1072 reg = <0x500dc000 0x1000>; 1073 cpu = <&cpu0>; 1074 clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; 1075 clock-names = "apb_pclk", "atclk"; 1076 access-controllers = <&dbg_bus 0>; 1077 status = "disabled"; 1078 1079 out-ports { 1080 port { 1081 etm0_out_port: endpoint { 1082 remote-endpoint = <&etf_in_port>; 1083 }; 1084 }; 1085 }; 1086 }; 1087 }; 1088 1089 mdma: dma-controller@58000000 { 1090 compatible = "st,stm32h7-mdma"; 1091 reg = <0x58000000 0x1000>; 1092 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&rcc MDMA>; 1094 #dma-cells = <5>; 1095 dma-channels = <32>; 1096 dma-requests = <48>; 1097 }; 1098 1099 crc1: crc@58009000 { 1100 compatible = "st,stm32f7-crc"; 1101 reg = <0x58009000 0x400>; 1102 clocks = <&rcc CRC1>; 1103 status = "disabled"; 1104 }; 1105 1106 usbh_ohci: usb@5800c000 { 1107 compatible = "generic-ohci"; 1108 reg = <0x5800c000 0x1000>; 1109 clocks = <&usbphyc>, <&rcc USBH>; 1110 resets = <&rcc USBH_R>; 1111 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1112 status = "disabled"; 1113 }; 1114 1115 usbh_ehci: usb@5800d000 { 1116 compatible = "generic-ehci"; 1117 reg = <0x5800d000 0x1000>; 1118 clocks = <&usbphyc>, <&rcc USBH>; 1119 resets = <&rcc USBH_R>; 1120 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1121 companion = <&usbh_ohci>; 1122 status = "disabled"; 1123 }; 1124 1125 iwdg2: watchdog@5a002000 { 1126 compatible = "st,stm32mp1-iwdg"; 1127 reg = <0x5a002000 0x400>; 1128 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; 1130 clock-names = "pclk", "lsi"; 1131 status = "disabled"; 1132 }; 1133 1134 rtc: rtc@5c004000 { 1135 compatible = "st,stm32mp1-rtc"; 1136 reg = <0x5c004000 0x400>; 1137 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 1138 clocks = <&scmi_clk CK_SCMI_RTCAPB>, 1139 <&scmi_clk CK_SCMI_RTC>; 1140 clock-names = "pclk", "rtc_ck"; 1141 status = "disabled"; 1142 }; 1143 1144 bsec: efuse@5c005000 { 1145 compatible = "st,stm32mp13-bsec"; 1146 reg = <0x5c005000 0x400>; 1147 #address-cells = <1>; 1148 #size-cells = <1>; 1149 1150 part_number_otp: part_number_otp@4 { 1151 reg = <0x4 0x2>; 1152 bits = <0 12>; 1153 }; 1154 vrefint: vrefin-cal@52 { 1155 reg = <0x52 0x2>; 1156 }; 1157 ts_cal1: calib@5c { 1158 reg = <0x5c 0x2>; 1159 }; 1160 ts_cal2: calib@5e { 1161 reg = <0x5e 0x2>; 1162 }; 1163 ethernet_mac1_address: mac1@e4 { 1164 reg = <0xe4 0x6>; 1165 }; 1166 ethernet_mac2_address: mac2@ea { 1167 reg = <0xea 0x6>; 1168 }; 1169 }; 1170 1171 etzpc: bus@5c007000 { 1172 compatible = "st,stm32-etzpc", "simple-bus"; 1173 reg = <0x5c007000 0x400>; 1174 #address-cells = <1>; 1175 #size-cells = <1>; 1176 #access-controller-cells = <1>; 1177 ranges; 1178 1179 adc_2: adc@48004000 { 1180 compatible = "st,stm32mp13-adc-core"; 1181 reg = <0x48004000 0x400>; 1182 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1183 clocks = <&rcc ADC2>, <&rcc ADC2_K>; 1184 clock-names = "bus", "adc"; 1185 interrupt-controller; 1186 #interrupt-cells = <1>; 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 access-controllers = <&etzpc 33>; 1190 status = "disabled"; 1191 1192 adc2: adc@0 { 1193 compatible = "st,stm32mp13-adc"; 1194 #io-channel-cells = <1>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 reg = <0x0>; 1198 interrupt-parent = <&adc_2>; 1199 interrupts = <0>; 1200 dmas = <&dmamux1 10 0x400 0x80000001>; 1201 dma-names = "rx"; 1202 nvmem-cells = <&vrefint>; 1203 nvmem-cell-names = "vrefint"; 1204 status = "disabled"; 1205 1206 channel@13 { 1207 reg = <13>; 1208 label = "vrefint"; 1209 }; 1210 channel@14 { 1211 reg = <14>; 1212 label = "vddcore"; 1213 }; 1214 channel@16 { 1215 reg = <16>; 1216 label = "vddcpu"; 1217 }; 1218 channel@17 { 1219 reg = <17>; 1220 label = "vddq_ddr"; 1221 }; 1222 }; 1223 }; 1224 1225 usbotg_hs: usb@49000000 { 1226 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1227 reg = <0x49000000 0x40000>; 1228 clocks = <&rcc USBO_K>; 1229 clock-names = "otg"; 1230 resets = <&rcc USBO_R>; 1231 reset-names = "dwc2"; 1232 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1233 g-rx-fifo-size = <512>; 1234 g-np-tx-fifo-size = <32>; 1235 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1236 dr_mode = "otg"; 1237 otg-rev = <0x200>; 1238 usb33d-supply = <&scmi_usb33>; 1239 access-controllers = <&etzpc 34>; 1240 status = "disabled"; 1241 }; 1242 1243 usart1: serial@4c000000 { 1244 compatible = "st,stm32h7-uart"; 1245 reg = <0x4c000000 0x400>; 1246 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1247 clocks = <&rcc USART1_K>; 1248 resets = <&rcc USART1_R>; 1249 wakeup-source; 1250 dmas = <&dmamux1 41 0x400 0x5>, 1251 <&dmamux1 42 0x400 0x1>; 1252 dma-names = "rx", "tx"; 1253 access-controllers = <&etzpc 16>; 1254 status = "disabled"; 1255 }; 1256 1257 usart2: serial@4c001000 { 1258 compatible = "st,stm32h7-uart"; 1259 reg = <0x4c001000 0x400>; 1260 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 1261 clocks = <&rcc USART2_K>; 1262 resets = <&rcc USART2_R>; 1263 wakeup-source; 1264 dmas = <&dmamux1 43 0x400 0x5>, 1265 <&dmamux1 44 0x400 0x1>; 1266 dma-names = "rx", "tx"; 1267 access-controllers = <&etzpc 17>; 1268 status = "disabled"; 1269 }; 1270 1271 i2s4: audio-controller@4c002000 { 1272 compatible = "st,stm32h7-i2s"; 1273 reg = <0x4c002000 0x400>; 1274 #sound-dai-cells = <0>; 1275 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1276 dmas = <&dmamux1 83 0x400 0x01>, 1277 <&dmamux1 84 0x400 0x01>; 1278 dma-names = "rx", "tx"; 1279 access-controllers = <&etzpc 13>; 1280 status = "disabled"; 1281 }; 1282 1283 spi4: spi@4c002000 { 1284 compatible = "st,stm32h7-spi"; 1285 reg = <0x4c002000 0x400>; 1286 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1287 clocks = <&rcc SPI4_K>; 1288 resets = <&rcc SPI4_R>; 1289 #address-cells = <1>; 1290 #size-cells = <0>; 1291 dmas = <&dmamux1 83 0x400 0x01>, 1292 <&dmamux1 84 0x400 0x01>; 1293 dma-names = "rx", "tx"; 1294 access-controllers = <&etzpc 18>; 1295 status = "disabled"; 1296 }; 1297 1298 spi5: spi@4c003000 { 1299 compatible = "st,stm32h7-spi"; 1300 reg = <0x4c003000 0x400>; 1301 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1302 clocks = <&rcc SPI5_K>; 1303 resets = <&rcc SPI5_R>; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 dmas = <&dmamux1 85 0x400 0x01>, 1307 <&dmamux1 86 0x400 0x01>; 1308 dma-names = "rx", "tx"; 1309 access-controllers = <&etzpc 19>; 1310 status = "disabled"; 1311 }; 1312 1313 i2c3: i2c@4c004000 { 1314 compatible = "st,stm32mp13-i2c"; 1315 reg = <0x4c004000 0x400>; 1316 interrupt-names = "event", "error"; 1317 interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>, 1318 <&intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1319 clocks = <&rcc I2C3_K>; 1320 resets = <&rcc I2C3_R>; 1321 #address-cells = <1>; 1322 #size-cells = <0>; 1323 dmas = <&dmamux1 73 0x400 0x1>, 1324 <&dmamux1 74 0x400 0x1>; 1325 dma-names = "rx", "tx"; 1326 st,syscfg-fmp = <&syscfg 0x4 0x4>; 1327 wakeup-source; 1328 i2c-analog-filter; 1329 access-controllers = <&etzpc 20>; 1330 status = "disabled"; 1331 }; 1332 1333 i2c4: i2c@4c005000 { 1334 compatible = "st,stm32mp13-i2c"; 1335 reg = <0x4c005000 0x400>; 1336 interrupt-names = "event", "error"; 1337 interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>, 1338 <&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1339 clocks = <&rcc I2C4_K>; 1340 resets = <&rcc I2C4_R>; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 dmas = <&dmamux1 75 0x400 0x1>, 1344 <&dmamux1 76 0x400 0x1>; 1345 dma-names = "rx", "tx"; 1346 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1347 wakeup-source; 1348 i2c-analog-filter; 1349 access-controllers = <&etzpc 21>; 1350 status = "disabled"; 1351 }; 1352 1353 i2c5: i2c@4c006000 { 1354 compatible = "st,stm32mp13-i2c"; 1355 reg = <0x4c006000 0x400>; 1356 interrupt-names = "event", "error"; 1357 interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>, 1358 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1359 clocks = <&rcc I2C5_K>; 1360 resets = <&rcc I2C5_R>; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 dmas = <&dmamux1 115 0x400 0x1>, 1364 <&dmamux1 116 0x400 0x1>; 1365 dma-names = "rx", "tx"; 1366 st,syscfg-fmp = <&syscfg 0x4 0x10>; 1367 wakeup-source; 1368 i2c-analog-filter; 1369 access-controllers = <&etzpc 22>; 1370 status = "disabled"; 1371 }; 1372 1373 timers12: timer@4c007000 { 1374 #address-cells = <1>; 1375 #size-cells = <0>; 1376 compatible = "st,stm32-timers"; 1377 reg = <0x4c007000 0x400>; 1378 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1379 interrupt-names = "global"; 1380 clocks = <&rcc TIM12_K>; 1381 clock-names = "int"; 1382 access-controllers = <&etzpc 23>; 1383 status = "disabled"; 1384 1385 counter { 1386 compatible = "st,stm32-timer-counter"; 1387 status = "disabled"; 1388 }; 1389 1390 pwm { 1391 compatible = "st,stm32-pwm"; 1392 #pwm-cells = <3>; 1393 status = "disabled"; 1394 }; 1395 1396 timer@11 { 1397 compatible = "st,stm32h7-timer-trigger"; 1398 reg = <11>; 1399 status = "disabled"; 1400 }; 1401 }; 1402 1403 timers13: timer@4c008000 { 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 compatible = "st,stm32-timers"; 1407 reg = <0x4c008000 0x400>; 1408 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1409 interrupt-names = "global"; 1410 clocks = <&rcc TIM13_K>; 1411 clock-names = "int"; 1412 access-controllers = <&etzpc 24>; 1413 status = "disabled"; 1414 1415 counter { 1416 compatible = "st,stm32-timer-counter"; 1417 status = "disabled"; 1418 }; 1419 1420 pwm { 1421 compatible = "st,stm32-pwm"; 1422 #pwm-cells = <3>; 1423 status = "disabled"; 1424 }; 1425 1426 timer@12 { 1427 compatible = "st,stm32h7-timer-trigger"; 1428 reg = <12>; 1429 status = "disabled"; 1430 }; 1431 }; 1432 1433 timers14: timer@4c009000 { 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 compatible = "st,stm32-timers"; 1437 reg = <0x4c009000 0x400>; 1438 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1439 interrupt-names = "global"; 1440 clocks = <&rcc TIM14_K>; 1441 clock-names = "int"; 1442 access-controllers = <&etzpc 25>; 1443 status = "disabled"; 1444 1445 counter { 1446 compatible = "st,stm32-timer-counter"; 1447 status = "disabled"; 1448 }; 1449 1450 pwm { 1451 compatible = "st,stm32-pwm"; 1452 #pwm-cells = <3>; 1453 status = "disabled"; 1454 }; 1455 1456 timer@13 { 1457 compatible = "st,stm32h7-timer-trigger"; 1458 reg = <13>; 1459 status = "disabled"; 1460 }; 1461 }; 1462 1463 timers15: timer@4c00a000 { 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 compatible = "st,stm32-timers"; 1467 reg = <0x4c00a000 0x400>; 1468 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1469 interrupt-names = "global"; 1470 clocks = <&rcc TIM15_K>; 1471 clock-names = "int"; 1472 dmas = <&dmamux1 105 0x400 0x1>, 1473 <&dmamux1 106 0x400 0x1>, 1474 <&dmamux1 107 0x400 0x1>, 1475 <&dmamux1 108 0x400 0x1>; 1476 dma-names = "ch1", "up", "trig", "com"; 1477 access-controllers = <&etzpc 26>; 1478 status = "disabled"; 1479 1480 counter { 1481 compatible = "st,stm32-timer-counter"; 1482 status = "disabled"; 1483 }; 1484 1485 pwm { 1486 compatible = "st,stm32-pwm"; 1487 #pwm-cells = <3>; 1488 status = "disabled"; 1489 }; 1490 1491 timer@14 { 1492 compatible = "st,stm32h7-timer-trigger"; 1493 reg = <14>; 1494 status = "disabled"; 1495 }; 1496 }; 1497 1498 timers16: timer@4c00b000 { 1499 #address-cells = <1>; 1500 #size-cells = <0>; 1501 compatible = "st,stm32-timers"; 1502 reg = <0x4c00b000 0x400>; 1503 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1504 interrupt-names = "global"; 1505 clocks = <&rcc TIM16_K>; 1506 clock-names = "int"; 1507 dmas = <&dmamux1 109 0x400 0x1>, 1508 <&dmamux1 110 0x400 0x1>; 1509 dma-names = "ch1", "up"; 1510 access-controllers = <&etzpc 27>; 1511 status = "disabled"; 1512 1513 counter { 1514 compatible = "st,stm32-timer-counter"; 1515 status = "disabled"; 1516 }; 1517 1518 pwm { 1519 compatible = "st,stm32-pwm"; 1520 #pwm-cells = <3>; 1521 status = "disabled"; 1522 }; 1523 1524 timer@15 { 1525 compatible = "st,stm32h7-timer-trigger"; 1526 reg = <15>; 1527 status = "disabled"; 1528 }; 1529 }; 1530 1531 timers17: timer@4c00c000 { 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 compatible = "st,stm32-timers"; 1535 reg = <0x4c00c000 0x400>; 1536 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1537 interrupt-names = "global"; 1538 clocks = <&rcc TIM17_K>; 1539 clock-names = "int"; 1540 dmas = <&dmamux1 111 0x400 0x1>, 1541 <&dmamux1 112 0x400 0x1>; 1542 dma-names = "ch1", "up"; 1543 access-controllers = <&etzpc 28>; 1544 status = "disabled"; 1545 1546 counter { 1547 compatible = "st,stm32-timer-counter"; 1548 status = "disabled"; 1549 }; 1550 1551 pwm { 1552 compatible = "st,stm32-pwm"; 1553 #pwm-cells = <3>; 1554 status = "disabled"; 1555 }; 1556 1557 timer@16 { 1558 compatible = "st,stm32h7-timer-trigger"; 1559 reg = <16>; 1560 status = "disabled"; 1561 }; 1562 }; 1563 1564 lptimer2: timer@50021000 { 1565 #address-cells = <1>; 1566 #size-cells = <0>; 1567 compatible = "st,stm32-lptimer"; 1568 reg = <0x50021000 0x400>; 1569 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1570 clocks = <&rcc LPTIM2_K>; 1571 clock-names = "mux"; 1572 wakeup-source; 1573 access-controllers = <&etzpc 1>; 1574 status = "disabled"; 1575 1576 pwm { 1577 compatible = "st,stm32-pwm-lp"; 1578 #pwm-cells = <3>; 1579 status = "disabled"; 1580 }; 1581 1582 trigger@1 { 1583 compatible = "st,stm32-lptimer-trigger"; 1584 reg = <1>; 1585 status = "disabled"; 1586 }; 1587 1588 counter { 1589 compatible = "st,stm32-lptimer-counter"; 1590 status = "disabled"; 1591 }; 1592 1593 timer { 1594 compatible = "st,stm32-lptimer-timer"; 1595 status = "disabled"; 1596 }; 1597 }; 1598 1599 lptimer3: timer@50022000 { 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 compatible = "st,stm32-lptimer"; 1603 reg = <0x50022000 0x400>; 1604 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1605 clocks = <&rcc LPTIM3_K>; 1606 clock-names = "mux"; 1607 wakeup-source; 1608 access-controllers = <&etzpc 2>; 1609 status = "disabled"; 1610 1611 pwm { 1612 compatible = "st,stm32-pwm-lp"; 1613 #pwm-cells = <3>; 1614 status = "disabled"; 1615 }; 1616 1617 trigger@2 { 1618 compatible = "st,stm32-lptimer-trigger"; 1619 reg = <2>; 1620 status = "disabled"; 1621 }; 1622 1623 timer { 1624 compatible = "st,stm32-lptimer-timer"; 1625 status = "disabled"; 1626 }; 1627 }; 1628 1629 hash: hash@54003000 { 1630 compatible = "st,stm32mp13-hash"; 1631 reg = <0x54003000 0x400>; 1632 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1633 clocks = <&rcc HASH1>; 1634 resets = <&rcc HASH1_R>; 1635 dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>; 1636 dma-names = "in"; 1637 access-controllers = <&etzpc 41>; 1638 status = "disabled"; 1639 }; 1640 1641 rng: rng@54004000 { 1642 compatible = "st,stm32mp13-rng"; 1643 reg = <0x54004000 0x400>; 1644 clocks = <&rcc RNG1_K>; 1645 resets = <&rcc RNG1_R>; 1646 access-controllers = <&etzpc 40>; 1647 status = "disabled"; 1648 }; 1649 1650 fmc: memory-controller@58002000 { 1651 compatible = "st,stm32mp1-fmc2-ebi"; 1652 reg = <0x58002000 0x1000>; 1653 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1654 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1655 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1656 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1657 <4 0 0x80000000 0x10000000>; /* NAND */ 1658 #address-cells = <2>; 1659 #size-cells = <1>; 1660 clocks = <&rcc FMC_K>; 1661 resets = <&rcc FMC_R>; 1662 access-controllers = <&etzpc 54>; 1663 status = "disabled"; 1664 1665 nand-controller@4,0 { 1666 compatible = "st,stm32mp1-fmc2-nfc"; 1667 reg = <4 0x00000000 0x1000>, 1668 <4 0x08010000 0x1000>, 1669 <4 0x08020000 0x1000>, 1670 <4 0x01000000 0x1000>, 1671 <4 0x09010000 0x1000>, 1672 <4 0x09020000 0x1000>; 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1676 dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, 1677 <&mdma 24 0x2 0x12000a08 0x0 0x0>, 1678 <&mdma 25 0x2 0x12000a0a 0x0 0x0>; 1679 dma-names = "tx", "rx", "ecc"; 1680 status = "disabled"; 1681 }; 1682 }; 1683 1684 qspi: spi@58003000 { 1685 compatible = "st,stm32f469-qspi"; 1686 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1687 reg-names = "qspi", "qspi_mm"; 1688 #address-cells = <1>; 1689 #size-cells = <0>; 1690 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1691 dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, 1692 <&mdma 26 0x2 0x10100008 0x0 0x0>; 1693 dma-names = "tx", "rx"; 1694 clocks = <&rcc QSPI_K>; 1695 resets = <&rcc QSPI_R>; 1696 access-controllers = <&etzpc 55>; 1697 status = "disabled"; 1698 }; 1699 1700 sdmmc1: mmc@58005000 { 1701 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1702 arm,primecell-periphid = <0x20253180>; 1703 reg = <0x58005000 0x1000>, <0x58006000 0x1000>; 1704 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1705 clocks = <&rcc SDMMC1_K>; 1706 clock-names = "apb_pclk"; 1707 resets = <&rcc SDMMC1_R>; 1708 cap-sd-highspeed; 1709 cap-mmc-highspeed; 1710 max-frequency = <130000000>; 1711 access-controllers = <&etzpc 50>; 1712 status = "disabled"; 1713 }; 1714 1715 sdmmc2: mmc@58007000 { 1716 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1717 arm,primecell-periphid = <0x20253180>; 1718 reg = <0x58007000 0x1000>, <0x58008000 0x1000>; 1719 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1720 clocks = <&rcc SDMMC2_K>; 1721 clock-names = "apb_pclk"; 1722 resets = <&rcc SDMMC2_R>; 1723 cap-sd-highspeed; 1724 cap-mmc-highspeed; 1725 max-frequency = <130000000>; 1726 access-controllers = <&etzpc 51>; 1727 status = "disabled"; 1728 }; 1729 1730 ethernet1: ethernet@5800a000 { 1731 compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; 1732 reg = <0x5800a000 0x2000>; 1733 reg-names = "stmmaceth"; 1734 interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1735 <&exti 68 1>; 1736 interrupt-names = "macirq", "eth_wake_irq"; 1737 clock-names = "stmmaceth", 1738 "mac-clk-tx", 1739 "mac-clk-rx", 1740 "ethstp", 1741 "ptp_ref", 1742 "eth-ck"; 1743 clocks = <&rcc ETH1MAC>, 1744 <&rcc ETH1TX>, 1745 <&rcc ETH1RX>, 1746 <&rcc ETH1STP>, 1747 <&rcc ETH1PTP_K>, 1748 <&rcc ETH1CK_K>; 1749 st,syscon = <&syscfg 0x4 0xff0000>; 1750 snps,mixed-burst; 1751 snps,pbl = <2>; 1752 snps,axi-config = <&stmmac_axi_config_1>; 1753 snps,tso; 1754 access-controllers = <&etzpc 48>; 1755 nvmem-cells = <ðernet_mac1_address>; 1756 nvmem-cell-names = "mac-address"; 1757 status = "disabled"; 1758 1759 stmmac_axi_config_1: stmmac-axi-config { 1760 snps,blen = <0 0 0 0 16 8 4>; 1761 snps,rd_osr_lmt = <0x7>; 1762 snps,wr_osr_lmt = <0x7>; 1763 }; 1764 }; 1765 1766 usbphyc: usbphyc@5a006000 { 1767 #address-cells = <1>; 1768 #size-cells = <0>; 1769 #clock-cells = <0>; 1770 compatible = "st,stm32mp1-usbphyc"; 1771 reg = <0x5a006000 0x1000>; 1772 clocks = <&rcc USBPHY_K>; 1773 resets = <&rcc USBPHY_R>; 1774 vdda1v1-supply = <&scmi_reg11>; 1775 vdda1v8-supply = <&scmi_reg18>; 1776 access-controllers = <&etzpc 5>; 1777 status = "disabled"; 1778 1779 usbphyc_port0: usb-phy@0 { 1780 #phy-cells = <0>; 1781 reg = <0>; 1782 }; 1783 1784 usbphyc_port1: usb-phy@1 { 1785 #phy-cells = <1>; 1786 reg = <1>; 1787 }; 1788 }; 1789 1790 iwdg1: watchdog@5c003000 { 1791 compatible = "st,stm32mp1-iwdg"; 1792 reg = <0x5c003000 0x400>; 1793 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1794 clocks = <&rcc IWDG1>, <&scmi_clk CK_SCMI_LSI>; 1795 clock-names = "pclk", "lsi"; 1796 access-controllers = <&etzpc 12>; 1797 status = "disabled"; 1798 }; 1799 }; 1800 1801 /* 1802 * Break node order to solve dependency probe issue between 1803 * pinctrl and exti. 1804 */ 1805 pinctrl: pinctrl@50002000 { 1806 #address-cells = <1>; 1807 #size-cells = <1>; 1808 compatible = "st,stm32mp135-pinctrl"; 1809 ranges = <0 0x50002000 0x8400>; 1810 interrupt-parent = <&exti>; 1811 st,syscfg = <&exti 0x60 0xff>; 1812 1813 gpioa: gpio@50002000 { 1814 gpio-controller; 1815 #gpio-cells = <2>; 1816 interrupt-controller; 1817 #interrupt-cells = <2>; 1818 reg = <0x0 0x400>; 1819 clocks = <&rcc GPIOA>; 1820 st,bank-name = "GPIOA"; 1821 ngpios = <16>; 1822 gpio-ranges = <&pinctrl 0 0 16>; 1823 }; 1824 1825 gpiob: gpio@50003000 { 1826 gpio-controller; 1827 #gpio-cells = <2>; 1828 interrupt-controller; 1829 #interrupt-cells = <2>; 1830 reg = <0x1000 0x400>; 1831 clocks = <&rcc GPIOB>; 1832 st,bank-name = "GPIOB"; 1833 ngpios = <16>; 1834 gpio-ranges = <&pinctrl 0 16 16>; 1835 }; 1836 1837 gpioc: gpio@50004000 { 1838 gpio-controller; 1839 #gpio-cells = <2>; 1840 interrupt-controller; 1841 #interrupt-cells = <2>; 1842 reg = <0x2000 0x400>; 1843 clocks = <&rcc GPIOC>; 1844 st,bank-name = "GPIOC"; 1845 ngpios = <16>; 1846 gpio-ranges = <&pinctrl 0 32 16>; 1847 }; 1848 1849 gpiod: gpio@50005000 { 1850 gpio-controller; 1851 #gpio-cells = <2>; 1852 interrupt-controller; 1853 #interrupt-cells = <2>; 1854 reg = <0x3000 0x400>; 1855 clocks = <&rcc GPIOD>; 1856 st,bank-name = "GPIOD"; 1857 ngpios = <16>; 1858 gpio-ranges = <&pinctrl 0 48 16>; 1859 }; 1860 1861 gpioe: gpio@50006000 { 1862 gpio-controller; 1863 #gpio-cells = <2>; 1864 interrupt-controller; 1865 #interrupt-cells = <2>; 1866 reg = <0x4000 0x400>; 1867 clocks = <&rcc GPIOE>; 1868 st,bank-name = "GPIOE"; 1869 ngpios = <16>; 1870 gpio-ranges = <&pinctrl 0 64 16>; 1871 }; 1872 1873 gpiof: gpio@50007000 { 1874 gpio-controller; 1875 #gpio-cells = <2>; 1876 interrupt-controller; 1877 #interrupt-cells = <2>; 1878 reg = <0x5000 0x400>; 1879 clocks = <&rcc GPIOF>; 1880 st,bank-name = "GPIOF"; 1881 ngpios = <16>; 1882 gpio-ranges = <&pinctrl 0 80 16>; 1883 }; 1884 1885 gpiog: gpio@50008000 { 1886 gpio-controller; 1887 #gpio-cells = <2>; 1888 interrupt-controller; 1889 #interrupt-cells = <2>; 1890 reg = <0x6000 0x400>; 1891 clocks = <&rcc GPIOG>; 1892 st,bank-name = "GPIOG"; 1893 ngpios = <16>; 1894 gpio-ranges = <&pinctrl 0 96 16>; 1895 }; 1896 1897 gpioh: gpio@50009000 { 1898 gpio-controller; 1899 #gpio-cells = <2>; 1900 interrupt-controller; 1901 #interrupt-cells = <2>; 1902 reg = <0x7000 0x400>; 1903 clocks = <&rcc GPIOH>; 1904 st,bank-name = "GPIOH"; 1905 ngpios = <15>; 1906 gpio-ranges = <&pinctrl 0 112 15>; 1907 }; 1908 1909 gpioi: gpio@5000a000 { 1910 gpio-controller; 1911 #gpio-cells = <2>; 1912 interrupt-controller; 1913 #interrupt-cells = <2>; 1914 reg = <0x8000 0x400>; 1915 clocks = <&rcc GPIOI>; 1916 st,bank-name = "GPIOI"; 1917 ngpios = <8>; 1918 gpio-ranges = <&pinctrl 0 128 8>; 1919 }; 1920 }; 1921 }; 1922}; 1923