1 // SPDX-License-Identifier: GPL-2.0
2 // TLV320ADCX140 Sound driver
3 // Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
4
5 #include <linux/module.h>
6 #include <linux/moduleparam.h>
7 #include <linux/init.h>
8 #include <linux/delay.h>
9 #include <linux/pm.h>
10 #include <linux/i2c.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/acpi.h>
14 #include <linux/of.h>
15 #include <linux/slab.h>
16 #include <sound/core.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/soc.h>
20 #include <sound/initval.h>
21 #include <sound/tlv.h>
22
23 #include "tlv320adcx140.h"
24
25 static const char *const adcx140_supply_names[] = {
26 "avdd",
27 "iovdd",
28 };
29
30 #define ADCX140_NUM_SUPPLIES ARRAY_SIZE(adcx140_supply_names)
31
32 struct adcx140_priv {
33 struct regulator *supply_areg;
34 struct regulator_bulk_data supplies[ADCX140_NUM_SUPPLIES];
35 struct gpio_desc *gpio_reset;
36 struct regmap *regmap;
37 struct device *dev;
38
39 bool micbias_vg;
40 bool phase_calib_on;
41
42 unsigned int dai_fmt;
43 unsigned int slot_width;
44 };
45
46 static const char * const gpo_config_names[] = {
47 "ti,gpo-config-1",
48 "ti,gpo-config-2",
49 "ti,gpo-config-3",
50 "ti,gpo-config-4",
51 };
52
53 static const struct reg_default adcx140_reg_defaults[] = {
54 { ADCX140_PAGE_SELECT, 0x00 },
55 { ADCX140_SW_RESET, 0x00 },
56 { ADCX140_SLEEP_CFG, 0x00 },
57 { ADCX140_SHDN_CFG, 0x05 },
58 { ADCX140_ASI_CFG0, 0x30 },
59 { ADCX140_ASI_CFG1, 0x00 },
60 { ADCX140_ASI_CFG2, 0x00 },
61 { ADCX140_ASI_CH1, 0x00 },
62 { ADCX140_ASI_CH2, 0x01 },
63 { ADCX140_ASI_CH3, 0x02 },
64 { ADCX140_ASI_CH4, 0x03 },
65 { ADCX140_ASI_CH5, 0x04 },
66 { ADCX140_ASI_CH6, 0x05 },
67 { ADCX140_ASI_CH7, 0x06 },
68 { ADCX140_ASI_CH8, 0x07 },
69 { ADCX140_MST_CFG0, 0x02 },
70 { ADCX140_MST_CFG1, 0x48 },
71 { ADCX140_ASI_STS, 0xff },
72 { ADCX140_CLK_SRC, 0x10 },
73 { ADCX140_PDMCLK_CFG, 0x40 },
74 { ADCX140_PDM_CFG, 0x00 },
75 { ADCX140_GPIO_CFG0, 0x22 },
76 { ADCX140_GPO_CFG0, 0x00 },
77 { ADCX140_GPO_CFG1, 0x00 },
78 { ADCX140_GPO_CFG2, 0x00 },
79 { ADCX140_GPO_CFG3, 0x00 },
80 { ADCX140_GPO_VAL, 0x00 },
81 { ADCX140_GPIO_MON, 0x00 },
82 { ADCX140_GPI_CFG0, 0x00 },
83 { ADCX140_GPI_CFG1, 0x00 },
84 { ADCX140_GPI_MON, 0x00 },
85 { ADCX140_INT_CFG, 0x00 },
86 { ADCX140_INT_MASK0, 0xff },
87 { ADCX140_INT_LTCH0, 0x00 },
88 { ADCX140_BIAS_CFG, 0x00 },
89 { ADCX140_CH1_CFG0, 0x00 },
90 { ADCX140_CH1_CFG1, 0x00 },
91 { ADCX140_CH1_CFG2, 0xc9 },
92 { ADCX140_CH1_CFG3, 0x80 },
93 { ADCX140_CH1_CFG4, 0x00 },
94 { ADCX140_CH2_CFG0, 0x00 },
95 { ADCX140_CH2_CFG1, 0x00 },
96 { ADCX140_CH2_CFG2, 0xc9 },
97 { ADCX140_CH2_CFG3, 0x80 },
98 { ADCX140_CH2_CFG4, 0x00 },
99 { ADCX140_CH3_CFG0, 0x00 },
100 { ADCX140_CH3_CFG1, 0x00 },
101 { ADCX140_CH3_CFG2, 0xc9 },
102 { ADCX140_CH3_CFG3, 0x80 },
103 { ADCX140_CH3_CFG4, 0x00 },
104 { ADCX140_CH4_CFG0, 0x00 },
105 { ADCX140_CH4_CFG1, 0x00 },
106 { ADCX140_CH4_CFG2, 0xc9 },
107 { ADCX140_CH4_CFG3, 0x80 },
108 { ADCX140_CH4_CFG4, 0x00 },
109 { ADCX140_CH5_CFG2, 0xc9 },
110 { ADCX140_CH5_CFG3, 0x80 },
111 { ADCX140_CH5_CFG4, 0x00 },
112 { ADCX140_CH6_CFG2, 0xc9 },
113 { ADCX140_CH6_CFG3, 0x80 },
114 { ADCX140_CH6_CFG4, 0x00 },
115 { ADCX140_CH7_CFG2, 0xc9 },
116 { ADCX140_CH7_CFG3, 0x80 },
117 { ADCX140_CH7_CFG4, 0x00 },
118 { ADCX140_CH8_CFG2, 0xc9 },
119 { ADCX140_CH8_CFG3, 0x80 },
120 { ADCX140_CH8_CFG4, 0x00 },
121 { ADCX140_DSP_CFG0, 0x01 },
122 { ADCX140_DSP_CFG1, 0x40 },
123 { ADCX140_DRE_CFG0, 0x7b },
124 { ADCX140_AGC_CFG0, 0xe7 },
125 { ADCX140_IN_CH_EN, 0xf0 },
126 { ADCX140_ASI_OUT_CH_EN, 0x00 },
127 { ADCX140_PWR_CFG, 0x00 },
128 { ADCX140_DEV_STS0, 0x00 },
129 { ADCX140_DEV_STS1, 0x80 },
130 };
131
132 static const struct regmap_range adcx140_wr_ranges[] = {
133 regmap_reg_range(ADCX140_PAGE_SELECT, ADCX140_SLEEP_CFG),
134 regmap_reg_range(ADCX140_SHDN_CFG, ADCX140_SHDN_CFG),
135 regmap_reg_range(ADCX140_ASI_CFG0, ADCX140_ASI_CFG2),
136 regmap_reg_range(ADCX140_ASI_CH1, ADCX140_MST_CFG1),
137 regmap_reg_range(ADCX140_CLK_SRC, ADCX140_CLK_SRC),
138 regmap_reg_range(ADCX140_PDMCLK_CFG, ADCX140_GPO_CFG3),
139 regmap_reg_range(ADCX140_GPO_VAL, ADCX140_GPO_VAL),
140 regmap_reg_range(ADCX140_GPI_CFG0, ADCX140_GPI_CFG1),
141 regmap_reg_range(ADCX140_GPI_MON, ADCX140_GPI_MON),
142 regmap_reg_range(ADCX140_INT_CFG, ADCX140_INT_MASK0),
143 regmap_reg_range(ADCX140_BIAS_CFG, ADCX140_CH4_CFG4),
144 regmap_reg_range(ADCX140_CH5_CFG2, ADCX140_CH5_CFG4),
145 regmap_reg_range(ADCX140_CH6_CFG2, ADCX140_CH6_CFG4),
146 regmap_reg_range(ADCX140_CH7_CFG2, ADCX140_CH7_CFG4),
147 regmap_reg_range(ADCX140_CH8_CFG2, ADCX140_CH8_CFG4),
148 regmap_reg_range(ADCX140_DSP_CFG0, ADCX140_DRE_CFG0),
149 regmap_reg_range(ADCX140_AGC_CFG0, ADCX140_AGC_CFG0),
150 regmap_reg_range(ADCX140_IN_CH_EN, ADCX140_PWR_CFG),
151 regmap_reg_range(ADCX140_PHASE_CALIB, ADCX140_PHASE_CALIB),
152 regmap_reg_range(0x7e, 0x7e),
153 };
154
155 static const struct regmap_access_table adcx140_wr_table = {
156 .yes_ranges = adcx140_wr_ranges,
157 .n_yes_ranges = ARRAY_SIZE(adcx140_wr_ranges),
158 };
159
160 static const struct regmap_range_cfg adcx140_ranges[] = {
161 {
162 .range_min = 0,
163 .range_max = 12 * 128,
164 .selector_reg = ADCX140_PAGE_SELECT,
165 .selector_mask = 0xff,
166 .selector_shift = 0,
167 .window_start = 0,
168 .window_len = 128,
169 },
170 };
171
adcx140_volatile(struct device * dev,unsigned int reg)172 static bool adcx140_volatile(struct device *dev, unsigned int reg)
173 {
174 switch (reg) {
175 case ADCX140_SW_RESET:
176 case ADCX140_DEV_STS0:
177 case ADCX140_DEV_STS1:
178 case ADCX140_ASI_STS:
179 return true;
180 default:
181 return false;
182 }
183 }
184
185 static const struct regmap_config adcx140_i2c_regmap = {
186 .reg_bits = 8,
187 .val_bits = 8,
188 .reg_defaults = adcx140_reg_defaults,
189 .num_reg_defaults = ARRAY_SIZE(adcx140_reg_defaults),
190 .cache_type = REGCACHE_FLAT,
191 .ranges = adcx140_ranges,
192 .num_ranges = ARRAY_SIZE(adcx140_ranges),
193 .max_register = 12 * 128,
194 .volatile_reg = adcx140_volatile,
195 .wr_table = &adcx140_wr_table,
196 };
197
198 /* Digital Volume control. From -100 to 27 dB in 0.5 dB steps */
199 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10050, 50, 0);
200
201 /* ADC gain. From 0 to 42 dB in 1 dB steps */
202 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0);
203
204 /* DRE Level. From -12 dB to -66 dB in 1 dB steps */
205 static DECLARE_TLV_DB_SCALE(dre_thresh_tlv, -6600, 100, 0);
206 /* DRE Max Gain. From 2 dB to 26 dB in 2 dB steps */
207 static DECLARE_TLV_DB_SCALE(dre_gain_tlv, 200, 200, 0);
208
209 /* AGC Level. From -6 dB to -36 dB in 2 dB steps */
210 static DECLARE_TLV_DB_SCALE(agc_thresh_tlv, -3600, 200, 0);
211 /* AGC Max Gain. From 3 dB to 42 dB in 3 dB steps */
212 static DECLARE_TLV_DB_SCALE(agc_gain_tlv, 300, 300, 0);
213
214 static const char * const decimation_filter_text[] = {
215 "Linear Phase", "Low Latency", "Ultra-low Latency"
216 };
217
218 static SOC_ENUM_SINGLE_DECL(decimation_filter_enum, ADCX140_DSP_CFG0, 4,
219 decimation_filter_text);
220
221 static const struct snd_kcontrol_new decimation_filter_controls[] = {
222 SOC_DAPM_ENUM("Decimation Filter", decimation_filter_enum),
223 };
224
225 static const char * const channel_summation_text[] = {
226 "Disabled", "2 Channel", "4 Channel"
227 };
228
229 static SOC_ENUM_SINGLE_DECL(channel_summation_enum, ADCX140_DSP_CFG0, 2,
230 channel_summation_text);
231
232 static const char * const pdmclk_text[] = {
233 "2.8224 MHz", "1.4112 MHz", "705.6 kHz", "5.6448 MHz"
234 };
235
236 static SOC_ENUM_SINGLE_DECL(pdmclk_select_enum, ADCX140_PDMCLK_CFG, 0,
237 pdmclk_text);
238
239 static const struct snd_kcontrol_new pdmclk_div_controls[] = {
240 SOC_DAPM_ENUM("PDM Clk Divider Select", pdmclk_select_enum),
241 };
242
243 static const char * const resistor_text[] = {
244 "2.5 kOhm", "10 kOhm", "20 kOhm"
245 };
246
247 static SOC_ENUM_SINGLE_DECL(in1_resistor_enum, ADCX140_CH1_CFG0, 2,
248 resistor_text);
249 static SOC_ENUM_SINGLE_DECL(in2_resistor_enum, ADCX140_CH2_CFG0, 2,
250 resistor_text);
251 static SOC_ENUM_SINGLE_DECL(in3_resistor_enum, ADCX140_CH3_CFG0, 2,
252 resistor_text);
253 static SOC_ENUM_SINGLE_DECL(in4_resistor_enum, ADCX140_CH4_CFG0, 2,
254 resistor_text);
255
256 static const struct snd_kcontrol_new in1_resistor_controls[] = {
257 SOC_DAPM_ENUM("CH1 Resistor Select", in1_resistor_enum),
258 };
259 static const struct snd_kcontrol_new in2_resistor_controls[] = {
260 SOC_DAPM_ENUM("CH2 Resistor Select", in2_resistor_enum),
261 };
262 static const struct snd_kcontrol_new in3_resistor_controls[] = {
263 SOC_DAPM_ENUM("CH3 Resistor Select", in3_resistor_enum),
264 };
265 static const struct snd_kcontrol_new in4_resistor_controls[] = {
266 SOC_DAPM_ENUM("CH4 Resistor Select", in4_resistor_enum),
267 };
268
269 /* Analog/Digital Selection */
270 static const char * const adcx140_mic_sel_text[] = {"Analog", "Line In", "Digital"};
271 static const char * const adcx140_analog_sel_text[] = {"Analog", "Line In"};
272
273 static SOC_ENUM_SINGLE_DECL(adcx140_mic1p_enum,
274 ADCX140_CH1_CFG0, 5,
275 adcx140_mic_sel_text);
276
277 static const struct snd_kcontrol_new adcx140_dapm_mic1p_control =
278 SOC_DAPM_ENUM("MIC1P MUX", adcx140_mic1p_enum);
279
280 static SOC_ENUM_SINGLE_DECL(adcx140_mic1_analog_enum,
281 ADCX140_CH1_CFG0, 7,
282 adcx140_analog_sel_text);
283
284 static const struct snd_kcontrol_new adcx140_dapm_mic1_analog_control =
285 SOC_DAPM_ENUM("MIC1 Analog MUX", adcx140_mic1_analog_enum);
286
287 static SOC_ENUM_SINGLE_DECL(adcx140_mic1m_enum,
288 ADCX140_CH1_CFG0, 5,
289 adcx140_mic_sel_text);
290
291 static const struct snd_kcontrol_new adcx140_dapm_mic1m_control =
292 SOC_DAPM_ENUM("MIC1M MUX", adcx140_mic1m_enum);
293
294 static SOC_ENUM_SINGLE_DECL(adcx140_mic2p_enum,
295 ADCX140_CH2_CFG0, 5,
296 adcx140_mic_sel_text);
297
298 static const struct snd_kcontrol_new adcx140_dapm_mic2p_control =
299 SOC_DAPM_ENUM("MIC2P MUX", adcx140_mic2p_enum);
300
301 static SOC_ENUM_SINGLE_DECL(adcx140_mic2_analog_enum,
302 ADCX140_CH2_CFG0, 7,
303 adcx140_analog_sel_text);
304
305 static const struct snd_kcontrol_new adcx140_dapm_mic2_analog_control =
306 SOC_DAPM_ENUM("MIC2 Analog MUX", adcx140_mic2_analog_enum);
307
308 static SOC_ENUM_SINGLE_DECL(adcx140_mic2m_enum,
309 ADCX140_CH2_CFG0, 5,
310 adcx140_mic_sel_text);
311
312 static const struct snd_kcontrol_new adcx140_dapm_mic2m_control =
313 SOC_DAPM_ENUM("MIC2M MUX", adcx140_mic2m_enum);
314
315 static SOC_ENUM_SINGLE_DECL(adcx140_mic3p_enum,
316 ADCX140_CH3_CFG0, 5,
317 adcx140_mic_sel_text);
318
319 static const struct snd_kcontrol_new adcx140_dapm_mic3p_control =
320 SOC_DAPM_ENUM("MIC3P MUX", adcx140_mic3p_enum);
321
322 static SOC_ENUM_SINGLE_DECL(adcx140_mic3_analog_enum,
323 ADCX140_CH3_CFG0, 7,
324 adcx140_analog_sel_text);
325
326 static const struct snd_kcontrol_new adcx140_dapm_mic3_analog_control =
327 SOC_DAPM_ENUM("MIC3 Analog MUX", adcx140_mic3_analog_enum);
328
329 static SOC_ENUM_SINGLE_DECL(adcx140_mic3m_enum,
330 ADCX140_CH3_CFG0, 5,
331 adcx140_mic_sel_text);
332
333 static const struct snd_kcontrol_new adcx140_dapm_mic3m_control =
334 SOC_DAPM_ENUM("MIC3M MUX", adcx140_mic3m_enum);
335
336 static SOC_ENUM_SINGLE_DECL(adcx140_mic4p_enum,
337 ADCX140_CH4_CFG0, 5,
338 adcx140_mic_sel_text);
339
340 static const struct snd_kcontrol_new adcx140_dapm_mic4p_control =
341 SOC_DAPM_ENUM("MIC4P MUX", adcx140_mic4p_enum);
342
343 static SOC_ENUM_SINGLE_DECL(adcx140_mic4_analog_enum,
344 ADCX140_CH4_CFG0, 7,
345 adcx140_analog_sel_text);
346
347 static const struct snd_kcontrol_new adcx140_dapm_mic4_analog_control =
348 SOC_DAPM_ENUM("MIC4 Analog MUX", adcx140_mic4_analog_enum);
349
350 static SOC_ENUM_SINGLE_DECL(adcx140_mic4m_enum,
351 ADCX140_CH4_CFG0, 5,
352 adcx140_mic_sel_text);
353
354 static const struct snd_kcontrol_new adcx140_dapm_mic4m_control =
355 SOC_DAPM_ENUM("MIC4M MUX", adcx140_mic4m_enum);
356
357 static const struct snd_kcontrol_new adcx140_dapm_ch1_en_switch =
358 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 7, 1, 0);
359 static const struct snd_kcontrol_new adcx140_dapm_ch2_en_switch =
360 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 6, 1, 0);
361 static const struct snd_kcontrol_new adcx140_dapm_ch3_en_switch =
362 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 5, 1, 0);
363 static const struct snd_kcontrol_new adcx140_dapm_ch4_en_switch =
364 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 4, 1, 0);
365 static const struct snd_kcontrol_new adcx140_dapm_ch5_en_switch =
366 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 3, 1, 0);
367 static const struct snd_kcontrol_new adcx140_dapm_ch6_en_switch =
368 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 2, 1, 0);
369 static const struct snd_kcontrol_new adcx140_dapm_ch7_en_switch =
370 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 1, 1, 0);
371 static const struct snd_kcontrol_new adcx140_dapm_ch8_en_switch =
372 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 0, 1, 0);
373
374 static const struct snd_kcontrol_new adcx140_dapm_ch1_dre_en_switch =
375 SOC_DAPM_SINGLE("Switch", ADCX140_CH1_CFG0, 0, 1, 0);
376 static const struct snd_kcontrol_new adcx140_dapm_ch2_dre_en_switch =
377 SOC_DAPM_SINGLE("Switch", ADCX140_CH2_CFG0, 0, 1, 0);
378 static const struct snd_kcontrol_new adcx140_dapm_ch3_dre_en_switch =
379 SOC_DAPM_SINGLE("Switch", ADCX140_CH3_CFG0, 0, 1, 0);
380 static const struct snd_kcontrol_new adcx140_dapm_ch4_dre_en_switch =
381 SOC_DAPM_SINGLE("Switch", ADCX140_CH4_CFG0, 0, 1, 0);
382
383 static const struct snd_kcontrol_new adcx140_dapm_dre_en_switch =
384 SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1, 3, 1, 1);
385
386 /* Output Mixer */
387 static const struct snd_kcontrol_new adcx140_output_mixer_controls[] = {
388 SOC_DAPM_SINGLE("Digital CH1 Switch", 0, 0, 0, 0),
389 SOC_DAPM_SINGLE("Digital CH2 Switch", 0, 0, 0, 0),
390 SOC_DAPM_SINGLE("Digital CH3 Switch", 0, 0, 0, 0),
391 SOC_DAPM_SINGLE("Digital CH4 Switch", 0, 0, 0, 0),
392 };
393
394 static const struct snd_soc_dapm_widget adcx140_dapm_widgets[] = {
395 /* Analog Differential Inputs */
396 SND_SOC_DAPM_INPUT("MIC1P"),
397 SND_SOC_DAPM_INPUT("MIC1M"),
398 SND_SOC_DAPM_INPUT("MIC2P"),
399 SND_SOC_DAPM_INPUT("MIC2M"),
400 SND_SOC_DAPM_INPUT("MIC3P"),
401 SND_SOC_DAPM_INPUT("MIC3M"),
402 SND_SOC_DAPM_INPUT("MIC4P"),
403 SND_SOC_DAPM_INPUT("MIC4M"),
404
405 SND_SOC_DAPM_OUTPUT("CH1_OUT"),
406 SND_SOC_DAPM_OUTPUT("CH2_OUT"),
407 SND_SOC_DAPM_OUTPUT("CH3_OUT"),
408 SND_SOC_DAPM_OUTPUT("CH4_OUT"),
409 SND_SOC_DAPM_OUTPUT("CH5_OUT"),
410 SND_SOC_DAPM_OUTPUT("CH6_OUT"),
411 SND_SOC_DAPM_OUTPUT("CH7_OUT"),
412 SND_SOC_DAPM_OUTPUT("CH8_OUT"),
413
414 SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
415 &adcx140_output_mixer_controls[0],
416 ARRAY_SIZE(adcx140_output_mixer_controls)),
417
418 /* Input Selection to MIC_PGA */
419 SND_SOC_DAPM_MUX("MIC1P Input Mux", SND_SOC_NOPM, 0, 0,
420 &adcx140_dapm_mic1p_control),
421 SND_SOC_DAPM_MUX("MIC2P Input Mux", SND_SOC_NOPM, 0, 0,
422 &adcx140_dapm_mic2p_control),
423 SND_SOC_DAPM_MUX("MIC3P Input Mux", SND_SOC_NOPM, 0, 0,
424 &adcx140_dapm_mic3p_control),
425 SND_SOC_DAPM_MUX("MIC4P Input Mux", SND_SOC_NOPM, 0, 0,
426 &adcx140_dapm_mic4p_control),
427
428 /* Input Selection to MIC_PGA */
429 SND_SOC_DAPM_MUX("MIC1 Analog Mux", SND_SOC_NOPM, 0, 0,
430 &adcx140_dapm_mic1_analog_control),
431 SND_SOC_DAPM_MUX("MIC2 Analog Mux", SND_SOC_NOPM, 0, 0,
432 &adcx140_dapm_mic2_analog_control),
433 SND_SOC_DAPM_MUX("MIC3 Analog Mux", SND_SOC_NOPM, 0, 0,
434 &adcx140_dapm_mic3_analog_control),
435 SND_SOC_DAPM_MUX("MIC4 Analog Mux", SND_SOC_NOPM, 0, 0,
436 &adcx140_dapm_mic4_analog_control),
437
438 SND_SOC_DAPM_MUX("MIC1M Input Mux", SND_SOC_NOPM, 0, 0,
439 &adcx140_dapm_mic1m_control),
440 SND_SOC_DAPM_MUX("MIC2M Input Mux", SND_SOC_NOPM, 0, 0,
441 &adcx140_dapm_mic2m_control),
442 SND_SOC_DAPM_MUX("MIC3M Input Mux", SND_SOC_NOPM, 0, 0,
443 &adcx140_dapm_mic3m_control),
444 SND_SOC_DAPM_MUX("MIC4M Input Mux", SND_SOC_NOPM, 0, 0,
445 &adcx140_dapm_mic4m_control),
446
447 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH1", SND_SOC_NOPM, 0, 0, NULL, 0),
448 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH2", SND_SOC_NOPM, 0, 0, NULL, 0),
449 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH3", SND_SOC_NOPM, 0, 0, NULL, 0),
450 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH4", SND_SOC_NOPM, 0, 0, NULL, 0),
451
452 SND_SOC_DAPM_ADC("CH1_ADC", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
453 SND_SOC_DAPM_ADC("CH2_ADC", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
454 SND_SOC_DAPM_ADC("CH3_ADC", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
455 SND_SOC_DAPM_ADC("CH4_ADC", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
456
457 SND_SOC_DAPM_ADC("CH1_DIG", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
458 SND_SOC_DAPM_ADC("CH2_DIG", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
459 SND_SOC_DAPM_ADC("CH3_DIG", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
460 SND_SOC_DAPM_ADC("CH4_DIG", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
461 SND_SOC_DAPM_ADC("CH5_DIG", "CH5 Capture", ADCX140_IN_CH_EN, 3, 0),
462 SND_SOC_DAPM_ADC("CH6_DIG", "CH6 Capture", ADCX140_IN_CH_EN, 2, 0),
463 SND_SOC_DAPM_ADC("CH7_DIG", "CH7 Capture", ADCX140_IN_CH_EN, 1, 0),
464 SND_SOC_DAPM_ADC("CH8_DIG", "CH8 Capture", ADCX140_IN_CH_EN, 0, 0),
465
466
467 SND_SOC_DAPM_SWITCH("CH1_ASI_EN", SND_SOC_NOPM, 0, 0,
468 &adcx140_dapm_ch1_en_switch),
469 SND_SOC_DAPM_SWITCH("CH2_ASI_EN", SND_SOC_NOPM, 0, 0,
470 &adcx140_dapm_ch2_en_switch),
471 SND_SOC_DAPM_SWITCH("CH3_ASI_EN", SND_SOC_NOPM, 0, 0,
472 &adcx140_dapm_ch3_en_switch),
473 SND_SOC_DAPM_SWITCH("CH4_ASI_EN", SND_SOC_NOPM, 0, 0,
474 &adcx140_dapm_ch4_en_switch),
475
476 SND_SOC_DAPM_SWITCH("CH5_ASI_EN", SND_SOC_NOPM, 0, 0,
477 &adcx140_dapm_ch5_en_switch),
478 SND_SOC_DAPM_SWITCH("CH6_ASI_EN", SND_SOC_NOPM, 0, 0,
479 &adcx140_dapm_ch6_en_switch),
480 SND_SOC_DAPM_SWITCH("CH7_ASI_EN", SND_SOC_NOPM, 0, 0,
481 &adcx140_dapm_ch7_en_switch),
482 SND_SOC_DAPM_SWITCH("CH8_ASI_EN", SND_SOC_NOPM, 0, 0,
483 &adcx140_dapm_ch8_en_switch),
484
485 SND_SOC_DAPM_SWITCH("DRE_ENABLE", SND_SOC_NOPM, 0, 0,
486 &adcx140_dapm_dre_en_switch),
487
488 SND_SOC_DAPM_SWITCH("CH1_DRE_EN", SND_SOC_NOPM, 0, 0,
489 &adcx140_dapm_ch1_dre_en_switch),
490 SND_SOC_DAPM_SWITCH("CH2_DRE_EN", SND_SOC_NOPM, 0, 0,
491 &adcx140_dapm_ch2_dre_en_switch),
492 SND_SOC_DAPM_SWITCH("CH3_DRE_EN", SND_SOC_NOPM, 0, 0,
493 &adcx140_dapm_ch3_dre_en_switch),
494 SND_SOC_DAPM_SWITCH("CH4_DRE_EN", SND_SOC_NOPM, 0, 0,
495 &adcx140_dapm_ch4_dre_en_switch),
496
497 SND_SOC_DAPM_MUX("IN1 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
498 in1_resistor_controls),
499 SND_SOC_DAPM_MUX("IN2 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
500 in2_resistor_controls),
501 SND_SOC_DAPM_MUX("IN3 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
502 in3_resistor_controls),
503 SND_SOC_DAPM_MUX("IN4 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
504 in4_resistor_controls),
505
506 SND_SOC_DAPM_MUX("PDM Clk Div Select", SND_SOC_NOPM, 0, 0,
507 pdmclk_div_controls),
508
509 SND_SOC_DAPM_MUX("Decimation Filter", SND_SOC_NOPM, 0, 0,
510 decimation_filter_controls),
511 };
512
513 static const struct snd_soc_dapm_route adcx140_audio_map[] = {
514 /* Outputs */
515 {"CH1_OUT", NULL, "Output Mixer"},
516 {"CH2_OUT", NULL, "Output Mixer"},
517 {"CH3_OUT", NULL, "Output Mixer"},
518 {"CH4_OUT", NULL, "Output Mixer"},
519
520 {"CH1_ASI_EN", "Switch", "CH1_ADC"},
521 {"CH2_ASI_EN", "Switch", "CH2_ADC"},
522 {"CH3_ASI_EN", "Switch", "CH3_ADC"},
523 {"CH4_ASI_EN", "Switch", "CH4_ADC"},
524
525 {"CH1_ASI_EN", "Switch", "CH1_DIG"},
526 {"CH2_ASI_EN", "Switch", "CH2_DIG"},
527 {"CH3_ASI_EN", "Switch", "CH3_DIG"},
528 {"CH4_ASI_EN", "Switch", "CH4_DIG"},
529 {"CH5_ASI_EN", "Switch", "CH5_DIG"},
530 {"CH6_ASI_EN", "Switch", "CH6_DIG"},
531 {"CH7_ASI_EN", "Switch", "CH7_DIG"},
532 {"CH8_ASI_EN", "Switch", "CH8_DIG"},
533
534 {"CH5_ASI_EN", "Switch", "CH5_OUT"},
535 {"CH6_ASI_EN", "Switch", "CH6_OUT"},
536 {"CH7_ASI_EN", "Switch", "CH7_OUT"},
537 {"CH8_ASI_EN", "Switch", "CH8_OUT"},
538
539 {"Decimation Filter", "Linear Phase", "DRE_ENABLE"},
540 {"Decimation Filter", "Low Latency", "DRE_ENABLE"},
541 {"Decimation Filter", "Ultra-low Latency", "DRE_ENABLE"},
542
543 {"DRE_ENABLE", "Switch", "CH1_DRE_EN"},
544 {"DRE_ENABLE", "Switch", "CH2_DRE_EN"},
545 {"DRE_ENABLE", "Switch", "CH3_DRE_EN"},
546 {"DRE_ENABLE", "Switch", "CH4_DRE_EN"},
547
548 {"CH1_DRE_EN", "Switch", "CH1_ADC"},
549 {"CH2_DRE_EN", "Switch", "CH2_ADC"},
550 {"CH3_DRE_EN", "Switch", "CH3_ADC"},
551 {"CH4_DRE_EN", "Switch", "CH4_ADC"},
552
553 /* Mic input */
554 {"CH1_ADC", NULL, "MIC_GAIN_CTL_CH1"},
555 {"CH2_ADC", NULL, "MIC_GAIN_CTL_CH2"},
556 {"CH3_ADC", NULL, "MIC_GAIN_CTL_CH3"},
557 {"CH4_ADC", NULL, "MIC_GAIN_CTL_CH4"},
558
559 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
560 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
561 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
562 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
563 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
564 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
565 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
566 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
567
568 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1P Input Mux"},
569 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1P Input Mux"},
570 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1P Input Mux"},
571
572 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1M Input Mux"},
573 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1M Input Mux"},
574 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1M Input Mux"},
575
576 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2P Input Mux"},
577 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2P Input Mux"},
578 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2P Input Mux"},
579
580 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2M Input Mux"},
581 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2M Input Mux"},
582 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2M Input Mux"},
583
584 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3P Input Mux"},
585 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3P Input Mux"},
586 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3P Input Mux"},
587
588 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3M Input Mux"},
589 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3M Input Mux"},
590 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3M Input Mux"},
591
592 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4P Input Mux"},
593 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4P Input Mux"},
594 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4P Input Mux"},
595
596 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4M Input Mux"},
597 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4M Input Mux"},
598 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4M Input Mux"},
599
600 {"PDM Clk Div Select", "2.8224 MHz", "MIC1P Input Mux"},
601 {"PDM Clk Div Select", "1.4112 MHz", "MIC1P Input Mux"},
602 {"PDM Clk Div Select", "705.6 kHz", "MIC1P Input Mux"},
603 {"PDM Clk Div Select", "5.6448 MHz", "MIC1P Input Mux"},
604
605 {"MIC1P Input Mux", NULL, "CH1_DIG"},
606 {"MIC1M Input Mux", NULL, "CH2_DIG"},
607 {"MIC2P Input Mux", NULL, "CH3_DIG"},
608 {"MIC2M Input Mux", NULL, "CH4_DIG"},
609 {"MIC3P Input Mux", NULL, "CH5_DIG"},
610 {"MIC3M Input Mux", NULL, "CH6_DIG"},
611 {"MIC4P Input Mux", NULL, "CH7_DIG"},
612 {"MIC4M Input Mux", NULL, "CH8_DIG"},
613
614 {"MIC1 Analog Mux", "Line In", "MIC1P"},
615 {"MIC2 Analog Mux", "Line In", "MIC2P"},
616 {"MIC3 Analog Mux", "Line In", "MIC3P"},
617 {"MIC4 Analog Mux", "Line In", "MIC4P"},
618
619 {"MIC1P Input Mux", "Analog", "MIC1P"},
620 {"MIC1M Input Mux", "Analog", "MIC1M"},
621 {"MIC2P Input Mux", "Analog", "MIC2P"},
622 {"MIC2M Input Mux", "Analog", "MIC2M"},
623 {"MIC3P Input Mux", "Analog", "MIC3P"},
624 {"MIC3M Input Mux", "Analog", "MIC3M"},
625 {"MIC4P Input Mux", "Analog", "MIC4P"},
626 {"MIC4M Input Mux", "Analog", "MIC4M"},
627
628 {"MIC1P Input Mux", "Digital", "MIC1P"},
629 {"MIC1M Input Mux", "Digital", "MIC1M"},
630 {"MIC2P Input Mux", "Digital", "MIC2P"},
631 {"MIC2M Input Mux", "Digital", "MIC2M"},
632 {"MIC3P Input Mux", "Digital", "MIC3P"},
633 {"MIC3M Input Mux", "Digital", "MIC3M"},
634 {"MIC4P Input Mux", "Digital", "MIC4P"},
635 {"MIC4M Input Mux", "Digital", "MIC4M"},
636 };
637
638 #define ADCX140_PHASE_CALIB_SWITCH(xname) {\
639 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
640 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
641 .info = adcx140_phase_calib_info, \
642 .get = adcx140_phase_calib_get, \
643 .put = adcx140_phase_calib_put}
644
adcx140_phase_calib_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)645 static int adcx140_phase_calib_info(struct snd_kcontrol *kcontrol,
646 struct snd_ctl_elem_info *uinfo)
647 {
648 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
649 uinfo->count = 1;
650 uinfo->value.integer.min = 0;
651 uinfo->value.integer.max = 1;
652 return 0;
653 }
654
adcx140_phase_calib_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * value)655 static int adcx140_phase_calib_get(struct snd_kcontrol *kcontrol,
656 struct snd_ctl_elem_value *value)
657 {
658 struct snd_soc_component *codec = snd_kcontrol_chip(kcontrol);
659 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(codec);
660
661 value->value.integer.value[0] = adcx140->phase_calib_on ? 1 : 0;
662
663
664 return 0;
665 }
666
adcx140_phase_calib_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * value)667 static int adcx140_phase_calib_put(struct snd_kcontrol *kcontrol,
668 struct snd_ctl_elem_value *value)
669 {
670 struct snd_soc_component *codec = snd_kcontrol_chip(kcontrol);
671 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(codec);
672
673 bool v = value->value.integer.value[0] ? true : false;
674
675 if (adcx140->phase_calib_on != v) {
676 adcx140->phase_calib_on = v;
677 return 1;
678 }
679 return 0;
680 }
681
682 static const struct snd_kcontrol_new adcx140_snd_controls[] = {
683 SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0,
684 adc_tlv),
685 SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH2_CFG1, 2, 42, 0,
686 adc_tlv),
687 SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH3_CFG1, 2, 42, 0,
688 adc_tlv),
689 SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH4_CFG1, 2, 42, 0,
690 adc_tlv),
691
692 SOC_SINGLE_TLV("DRE Threshold", ADCX140_DRE_CFG0, 4, 9, 0,
693 dre_thresh_tlv),
694 SOC_SINGLE_TLV("DRE Max Gain", ADCX140_DRE_CFG0, 0, 12, 0,
695 dre_gain_tlv),
696
697 SOC_SINGLE_TLV("AGC Threshold", ADCX140_AGC_CFG0, 4, 15, 0,
698 agc_thresh_tlv),
699 SOC_SINGLE_TLV("AGC Max Gain", ADCX140_AGC_CFG0, 0, 13, 0,
700 agc_gain_tlv),
701
702 SOC_SINGLE_TLV("Digital CH1 Out Volume", ADCX140_CH1_CFG2,
703 0, 0xff, 0, dig_vol_tlv),
704 SOC_SINGLE_TLV("Digital CH2 Out Volume", ADCX140_CH2_CFG2,
705 0, 0xff, 0, dig_vol_tlv),
706 SOC_SINGLE_TLV("Digital CH3 Out Volume", ADCX140_CH3_CFG2,
707 0, 0xff, 0, dig_vol_tlv),
708 SOC_SINGLE_TLV("Digital CH4 Out Volume", ADCX140_CH4_CFG2,
709 0, 0xff, 0, dig_vol_tlv),
710 SOC_SINGLE_TLV("Digital CH5 Out Volume", ADCX140_CH5_CFG2,
711 0, 0xff, 0, dig_vol_tlv),
712 SOC_SINGLE_TLV("Digital CH6 Out Volume", ADCX140_CH6_CFG2,
713 0, 0xff, 0, dig_vol_tlv),
714 SOC_SINGLE_TLV("Digital CH7 Out Volume", ADCX140_CH7_CFG2,
715 0, 0xff, 0, dig_vol_tlv),
716 SOC_SINGLE_TLV("Digital CH8 Out Volume", ADCX140_CH8_CFG2,
717 0, 0xff, 0, dig_vol_tlv),
718 ADCX140_PHASE_CALIB_SWITCH("Phase Calibration Switch"),
719
720 SOC_SINGLE("Biquads Per Channel", ADCX140_DSP_CFG1, 5, 3, 0),
721
722 SOC_ENUM("Channel Summation", channel_summation_enum),
723 };
724
adcx140_reset(struct adcx140_priv * adcx140)725 static int adcx140_reset(struct adcx140_priv *adcx140)
726 {
727 int ret = 0;
728
729 if (adcx140->gpio_reset) {
730 gpiod_direction_output(adcx140->gpio_reset, 0);
731 /* 8.4.1: wait for hw shutdown (25ms) + >= 1ms */
732 usleep_range(30000, 100000);
733 gpiod_direction_output(adcx140->gpio_reset, 1);
734 } else {
735 ret = regmap_write(adcx140->regmap, ADCX140_SW_RESET,
736 ADCX140_RESET);
737 }
738
739 /* 8.4.2: wait >= 10 ms after entering sleep mode. */
740 usleep_range(10000, 100000);
741
742 return ret;
743 }
744
adcx140_pwr_ctrl(struct adcx140_priv * adcx140,bool power_state)745 static void adcx140_pwr_ctrl(struct adcx140_priv *adcx140, bool power_state)
746 {
747 int pwr_ctrl = 0;
748 int ret = 0;
749
750 if (power_state)
751 pwr_ctrl = ADCX140_PWR_CFG_ADC_PDZ | ADCX140_PWR_CFG_PLL_PDZ;
752
753 if (adcx140->micbias_vg && power_state)
754 pwr_ctrl |= ADCX140_PWR_CFG_BIAS_PDZ;
755
756 if (pwr_ctrl) {
757 ret = regmap_write(adcx140->regmap, ADCX140_PHASE_CALIB,
758 adcx140->phase_calib_on ? 0x00 : 0x40);
759 if (ret)
760 dev_err(adcx140->dev, "%s: register write error %d\n",
761 __func__, ret);
762 }
763
764 regmap_update_bits(adcx140->regmap, ADCX140_PWR_CFG,
765 ADCX140_PWR_CTRL_MSK, pwr_ctrl);
766 }
767
adcx140_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)768 static int adcx140_hw_params(struct snd_pcm_substream *substream,
769 struct snd_pcm_hw_params *params,
770 struct snd_soc_dai *dai)
771 {
772 struct snd_soc_component *component = dai->component;
773 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
774 u8 data = 0;
775
776 switch (params_physical_width(params)) {
777 case 16:
778 data = ADCX140_16_BIT_WORD;
779 break;
780 case 20:
781 data = ADCX140_20_BIT_WORD;
782 break;
783 case 24:
784 data = ADCX140_24_BIT_WORD;
785 break;
786 case 32:
787 data = ADCX140_32_BIT_WORD;
788 break;
789 default:
790 dev_err(component->dev, "%s: Unsupported width %d\n",
791 __func__, params_physical_width(params));
792 return -EINVAL;
793 }
794
795 adcx140_pwr_ctrl(adcx140, false);
796
797 snd_soc_component_update_bits(component, ADCX140_ASI_CFG0,
798 ADCX140_WORD_LEN_MSK, data);
799
800 adcx140_pwr_ctrl(adcx140, true);
801
802 return 0;
803 }
804
adcx140_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)805 static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai,
806 unsigned int fmt)
807 {
808 struct snd_soc_component *component = codec_dai->component;
809 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
810 u8 iface_reg1 = 0;
811 u8 iface_reg2 = 0;
812 int offset = 0;
813 bool inverted_bclk = false;
814
815 /* set master/slave audio interface */
816 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
817 case SND_SOC_DAIFMT_CBP_CFP:
818 iface_reg2 |= ADCX140_BCLK_FSYNC_MASTER;
819 break;
820 case SND_SOC_DAIFMT_CBC_CFC:
821 break;
822 default:
823 dev_err(component->dev, "Invalid DAI clock provider\n");
824 return -EINVAL;
825 }
826
827 /* interface format */
828 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
829 case SND_SOC_DAIFMT_I2S:
830 iface_reg1 |= ADCX140_I2S_MODE_BIT;
831 break;
832 case SND_SOC_DAIFMT_LEFT_J:
833 iface_reg1 |= ADCX140_LEFT_JUST_BIT;
834 break;
835 case SND_SOC_DAIFMT_DSP_A:
836 offset = 1;
837 inverted_bclk = true;
838 break;
839 case SND_SOC_DAIFMT_DSP_B:
840 inverted_bclk = true;
841 break;
842 default:
843 dev_err(component->dev, "Invalid DAI interface format\n");
844 return -EINVAL;
845 }
846
847 /* signal polarity */
848 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
849 case SND_SOC_DAIFMT_IB_NF:
850 case SND_SOC_DAIFMT_IB_IF:
851 inverted_bclk = !inverted_bclk;
852 break;
853 case SND_SOC_DAIFMT_NB_IF:
854 iface_reg1 |= ADCX140_FSYNCINV_BIT;
855 break;
856 case SND_SOC_DAIFMT_NB_NF:
857 break;
858 default:
859 dev_err(component->dev, "Invalid DAI clock signal polarity\n");
860 return -EINVAL;
861 }
862
863 if (inverted_bclk)
864 iface_reg1 |= ADCX140_BCLKINV_BIT;
865
866 adcx140->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
867
868 adcx140_pwr_ctrl(adcx140, false);
869
870 snd_soc_component_update_bits(component, ADCX140_ASI_CFG0,
871 ADCX140_FSYNCINV_BIT |
872 ADCX140_BCLKINV_BIT |
873 ADCX140_ASI_FORMAT_MSK,
874 iface_reg1);
875 snd_soc_component_update_bits(component, ADCX140_MST_CFG0,
876 ADCX140_BCLK_FSYNC_MASTER, iface_reg2);
877
878 /* Configure data offset */
879 snd_soc_component_update_bits(component, ADCX140_ASI_CFG1,
880 ADCX140_TX_OFFSET_MASK, offset);
881
882 adcx140_pwr_ctrl(adcx140, true);
883
884 return 0;
885 }
886
adcx140_set_dai_tdm_slot(struct snd_soc_dai * codec_dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)887 static int adcx140_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
888 unsigned int tx_mask, unsigned int rx_mask,
889 int slots, int slot_width)
890 {
891 struct snd_soc_component *component = codec_dai->component;
892 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
893
894 /*
895 * The chip itself supports arbitrary masks, but the driver currently
896 * only supports adjacent slots beginning at the first slot.
897 */
898 if (tx_mask != GENMASK(__fls(tx_mask), 0)) {
899 dev_err(component->dev, "Only lower adjacent slots are supported\n");
900 return -EINVAL;
901 }
902
903 switch (slot_width) {
904 case 16:
905 case 20:
906 case 24:
907 case 32:
908 break;
909 default:
910 dev_err(component->dev, "Unsupported slot width %d\n", slot_width);
911 return -EINVAL;
912 }
913
914 adcx140->slot_width = slot_width;
915
916 return 0;
917 }
918
919 static const struct snd_soc_dai_ops adcx140_dai_ops = {
920 .hw_params = adcx140_hw_params,
921 .set_fmt = adcx140_set_dai_fmt,
922 .set_tdm_slot = adcx140_set_dai_tdm_slot,
923 };
924
adcx140_configure_gpo(struct adcx140_priv * adcx140)925 static int adcx140_configure_gpo(struct adcx140_priv *adcx140)
926 {
927 u32 gpo_outputs[ADCX140_NUM_GPOS];
928 u32 gpo_output_val = 0;
929 int ret;
930 int i;
931
932 for (i = 0; i < ADCX140_NUM_GPOS; i++) {
933 ret = device_property_read_u32_array(adcx140->dev,
934 gpo_config_names[i],
935 gpo_outputs,
936 ADCX140_NUM_GPO_CFGS);
937 if (ret)
938 continue;
939
940 if (gpo_outputs[0] > ADCX140_GPO_CFG_MAX) {
941 dev_err(adcx140->dev, "GPO%d config out of range\n", i + 1);
942 return -EINVAL;
943 }
944
945 if (gpo_outputs[1] > ADCX140_GPO_DRV_MAX) {
946 dev_err(adcx140->dev, "GPO%d drive out of range\n", i + 1);
947 return -EINVAL;
948 }
949
950 gpo_output_val = gpo_outputs[0] << ADCX140_GPO_SHIFT |
951 gpo_outputs[1];
952 ret = regmap_write(adcx140->regmap, ADCX140_GPO_CFG0 + i,
953 gpo_output_val);
954 if (ret)
955 return ret;
956 }
957
958 return 0;
959
960 }
961
adcx140_configure_gpio(struct adcx140_priv * adcx140)962 static int adcx140_configure_gpio(struct adcx140_priv *adcx140)
963 {
964 int gpio_count = 0;
965 u32 gpio_outputs[ADCX140_NUM_GPIO_CFGS];
966 u32 gpio_output_val = 0;
967 int ret;
968
969 gpio_count = device_property_count_u32(adcx140->dev,
970 "ti,gpio-config");
971 if (gpio_count <= 0)
972 return 0;
973
974 if (gpio_count != ADCX140_NUM_GPIO_CFGS)
975 return -EINVAL;
976
977 ret = device_property_read_u32_array(adcx140->dev, "ti,gpio-config",
978 gpio_outputs, gpio_count);
979 if (ret)
980 return ret;
981
982 if (gpio_outputs[0] > ADCX140_GPIO_CFG_MAX) {
983 dev_err(adcx140->dev, "GPIO config out of range\n");
984 return -EINVAL;
985 }
986
987 if (gpio_outputs[1] > ADCX140_GPIO_DRV_MAX) {
988 dev_err(adcx140->dev, "GPIO drive out of range\n");
989 return -EINVAL;
990 }
991
992 gpio_output_val = gpio_outputs[0] << ADCX140_GPIO_SHIFT
993 | gpio_outputs[1];
994
995 return regmap_write(adcx140->regmap, ADCX140_GPIO_CFG0, gpio_output_val);
996 }
997
adcx140_codec_probe(struct snd_soc_component * component)998 static int adcx140_codec_probe(struct snd_soc_component *component)
999 {
1000 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
1001 int sleep_cfg_val = ADCX140_WAKE_DEV;
1002 u32 bias_source;
1003 u32 vref_source;
1004 u8 bias_cfg;
1005 int pdm_count;
1006 u32 pdm_edges[ADCX140_NUM_PDM_EDGES];
1007 u32 pdm_edge_val = 0;
1008 int gpi_count;
1009 u32 gpi_inputs[ADCX140_NUM_GPI_PINS];
1010 u32 gpi_input_val = 0;
1011 int i;
1012 int ret;
1013 bool tx_high_z;
1014
1015 ret = device_property_read_u32(adcx140->dev, "ti,mic-bias-source",
1016 &bias_source);
1017 if (ret || bias_source > ADCX140_MIC_BIAS_VAL_AVDD) {
1018 bias_source = ADCX140_MIC_BIAS_VAL_VREF;
1019 adcx140->micbias_vg = false;
1020 } else {
1021 adcx140->micbias_vg = true;
1022 }
1023
1024 ret = device_property_read_u32(adcx140->dev, "ti,vref-source",
1025 &vref_source);
1026 if (ret)
1027 vref_source = ADCX140_MIC_BIAS_VREF_275V;
1028
1029 if (vref_source > ADCX140_MIC_BIAS_VREF_1375V) {
1030 dev_err(adcx140->dev, "Mic Bias source value is invalid\n");
1031 return -EINVAL;
1032 }
1033
1034 bias_cfg = bias_source << ADCX140_MIC_BIAS_SHIFT | vref_source;
1035
1036 ret = adcx140_reset(adcx140);
1037 if (ret)
1038 goto out;
1039
1040 if (adcx140->supply_areg == NULL)
1041 sleep_cfg_val |= ADCX140_AREG_INTERNAL;
1042
1043 ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val);
1044 if (ret) {
1045 dev_err(adcx140->dev, "setting sleep config failed %d\n", ret);
1046 goto out;
1047 }
1048
1049 /* 8.4.3: Wait >= 1ms after entering active mode. */
1050 usleep_range(1000, 100000);
1051
1052 pdm_count = device_property_count_u32(adcx140->dev,
1053 "ti,pdm-edge-select");
1054 if (pdm_count <= ADCX140_NUM_PDM_EDGES && pdm_count > 0) {
1055 ret = device_property_read_u32_array(adcx140->dev,
1056 "ti,pdm-edge-select",
1057 pdm_edges, pdm_count);
1058 if (ret)
1059 return ret;
1060
1061 for (i = 0; i < pdm_count; i++)
1062 pdm_edge_val |= pdm_edges[i] << (ADCX140_PDM_EDGE_SHIFT - i);
1063
1064 ret = regmap_write(adcx140->regmap, ADCX140_PDM_CFG,
1065 pdm_edge_val);
1066 if (ret)
1067 return ret;
1068 }
1069
1070 gpi_count = device_property_count_u32(adcx140->dev, "ti,gpi-config");
1071 if (gpi_count <= ADCX140_NUM_GPI_PINS && gpi_count > 0) {
1072 ret = device_property_read_u32_array(adcx140->dev,
1073 "ti,gpi-config",
1074 gpi_inputs, gpi_count);
1075 if (ret)
1076 return ret;
1077
1078 gpi_input_val = gpi_inputs[ADCX140_GPI1_INDEX] << ADCX140_GPI_SHIFT |
1079 gpi_inputs[ADCX140_GPI2_INDEX];
1080
1081 ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG0,
1082 gpi_input_val);
1083 if (ret)
1084 return ret;
1085
1086 gpi_input_val = gpi_inputs[ADCX140_GPI3_INDEX] << ADCX140_GPI_SHIFT |
1087 gpi_inputs[ADCX140_GPI4_INDEX];
1088
1089 ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG1,
1090 gpi_input_val);
1091 if (ret)
1092 return ret;
1093 }
1094
1095 ret = adcx140_configure_gpio(adcx140);
1096 if (ret)
1097 return ret;
1098
1099 ret = adcx140_configure_gpo(adcx140);
1100 if (ret)
1101 goto out;
1102
1103 ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG,
1104 ADCX140_MIC_BIAS_VAL_MSK |
1105 ADCX140_MIC_BIAS_VREF_MSK, bias_cfg);
1106 if (ret)
1107 dev_err(adcx140->dev, "setting MIC bias failed %d\n", ret);
1108
1109 tx_high_z = device_property_read_bool(adcx140->dev, "ti,asi-tx-drive");
1110 if (tx_high_z) {
1111 ret = regmap_update_bits(adcx140->regmap, ADCX140_ASI_CFG0,
1112 ADCX140_TX_FILL, ADCX140_TX_FILL);
1113 if (ret) {
1114 dev_err(adcx140->dev, "Setting Tx drive failed %d\n", ret);
1115 goto out;
1116 }
1117 }
1118
1119 adcx140_pwr_ctrl(adcx140, true);
1120 out:
1121 return ret;
1122 }
1123
adcx140_pwr_off(struct adcx140_priv * adcx140)1124 static int adcx140_pwr_off(struct adcx140_priv *adcx140)
1125 {
1126 int ret;
1127
1128 regcache_cache_only(adcx140->regmap, true);
1129 regcache_mark_dirty(adcx140->regmap);
1130
1131 /* Assert the reset GPIO */
1132 gpiod_set_value_cansleep(adcx140->gpio_reset, 0);
1133
1134 /*
1135 * Datasheet - TLV320ADC3140 Rev. B, TLV320ADC5140 Rev. A,
1136 * TLV320ADC6140 Rev. A 8.4.1:
1137 * wait for hw shutdown (25ms) + >= 1ms
1138 */
1139 usleep_range(30000, 100000);
1140
1141 /* Power off the regulators, `avdd` and `iovdd` */
1142 ret = regulator_bulk_disable(ARRAY_SIZE(adcx140->supplies),
1143 adcx140->supplies);
1144 if (ret) {
1145 dev_err(adcx140->dev, "Failed to disable supplies: %d\n", ret);
1146 return ret;
1147 }
1148
1149 return 0;
1150 }
1151
adcx140_pwr_on(struct adcx140_priv * adcx140)1152 static int adcx140_pwr_on(struct adcx140_priv *adcx140)
1153 {
1154 int ret;
1155
1156 /* Power on the regulators, `avdd` and `iovdd` */
1157 ret = regulator_bulk_enable(ARRAY_SIZE(adcx140->supplies),
1158 adcx140->supplies);
1159 if (ret) {
1160 dev_err(adcx140->dev, "Failed to enable supplies: %d\n", ret);
1161 return ret;
1162 }
1163
1164 /* De-assert the reset GPIO */
1165 gpiod_set_value_cansleep(adcx140->gpio_reset, 1);
1166
1167 /*
1168 * Datasheet - TLV320ADC3140 Rev. B, TLV320ADC5140 Rev. A,
1169 * TLV320ADC6140 Rev. A 8.4.2:
1170 * wait >= 10 ms after entering sleep mode.
1171 */
1172 usleep_range(10000, 100000);
1173
1174 regcache_cache_only(adcx140->regmap, false);
1175
1176 /* Flush the regcache */
1177 ret = regcache_sync(adcx140->regmap);
1178 if (ret) {
1179 dev_err(adcx140->dev, "Failed to restore register map: %d\n",
1180 ret);
1181 return ret;
1182 }
1183
1184 return 0;
1185 }
1186
adcx140_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1187 static int adcx140_set_bias_level(struct snd_soc_component *component,
1188 enum snd_soc_bias_level level)
1189 {
1190 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
1191 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1192 enum snd_soc_bias_level prev_level = snd_soc_dapm_get_bias_level(dapm);
1193
1194 switch (level) {
1195 case SND_SOC_BIAS_ON:
1196 case SND_SOC_BIAS_PREPARE:
1197 if (prev_level == SND_SOC_BIAS_STANDBY)
1198 adcx140_pwr_ctrl(adcx140, true);
1199 break;
1200 case SND_SOC_BIAS_STANDBY:
1201 if (prev_level == SND_SOC_BIAS_PREPARE)
1202 adcx140_pwr_ctrl(adcx140, false);
1203 if (prev_level == SND_SOC_BIAS_OFF)
1204 return adcx140_pwr_on(adcx140);
1205 break;
1206 case SND_SOC_BIAS_OFF:
1207 if (prev_level == SND_SOC_BIAS_STANDBY)
1208 return adcx140_pwr_off(adcx140);
1209 break;
1210 }
1211
1212 return 0;
1213 }
1214
1215 static const struct snd_soc_component_driver soc_codec_driver_adcx140 = {
1216 .probe = adcx140_codec_probe,
1217 .set_bias_level = adcx140_set_bias_level,
1218 .controls = adcx140_snd_controls,
1219 .num_controls = ARRAY_SIZE(adcx140_snd_controls),
1220 .dapm_widgets = adcx140_dapm_widgets,
1221 .num_dapm_widgets = ARRAY_SIZE(adcx140_dapm_widgets),
1222 .dapm_routes = adcx140_audio_map,
1223 .num_dapm_routes = ARRAY_SIZE(adcx140_audio_map),
1224 .suspend_bias_off = 1,
1225 .idle_bias_on = 0,
1226 .use_pmdown_time = 1,
1227 .endianness = 1,
1228 };
1229
1230 static struct snd_soc_dai_driver adcx140_dai_driver[] = {
1231 {
1232 .name = "tlv320adcx140-codec",
1233 .capture = {
1234 .stream_name = "Capture",
1235 .channels_min = 2,
1236 .channels_max = ADCX140_MAX_CHANNELS,
1237 .rates = ADCX140_RATES,
1238 .formats = ADCX140_FORMATS,
1239 },
1240 .ops = &adcx140_dai_ops,
1241 .symmetric_rate = 1,
1242 }
1243 };
1244
1245 #ifdef CONFIG_OF
1246 static const struct of_device_id tlv320adcx140_of_match[] = {
1247 { .compatible = "ti,tlv320adc3140" },
1248 { .compatible = "ti,tlv320adc5140" },
1249 { .compatible = "ti,tlv320adc6140" },
1250 {},
1251 };
1252 MODULE_DEVICE_TABLE(of, tlv320adcx140_of_match);
1253 #endif
1254
adcx140_disable_regulator(void * arg)1255 static void adcx140_disable_regulator(void *arg)
1256 {
1257 struct adcx140_priv *adcx140 = arg;
1258
1259 regulator_disable(adcx140->supply_areg);
1260 }
1261
adcx140_i2c_probe(struct i2c_client * i2c)1262 static int adcx140_i2c_probe(struct i2c_client *i2c)
1263 {
1264 struct adcx140_priv *adcx140;
1265 int ret;
1266
1267 adcx140 = devm_kzalloc(&i2c->dev, sizeof(*adcx140), GFP_KERNEL);
1268 if (!adcx140)
1269 return -ENOMEM;
1270
1271 adcx140->phase_calib_on = false;
1272 adcx140->dev = &i2c->dev;
1273
1274 for (int i = 0; i < ADCX140_NUM_SUPPLIES; i++)
1275 adcx140->supplies[i].supply = adcx140_supply_names[i];
1276
1277 ret = devm_regulator_bulk_get(&i2c->dev, ADCX140_NUM_SUPPLIES,
1278 adcx140->supplies);
1279 if (ret) {
1280 dev_err_probe(&i2c->dev, ret, "Failed to request supplies\n");
1281 return ret;
1282 }
1283
1284 adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev,
1285 "reset", GPIOD_OUT_LOW);
1286 if (IS_ERR(adcx140->gpio_reset))
1287 return dev_err_probe(&i2c->dev, PTR_ERR(adcx140->gpio_reset),
1288 "Failed to get Reset GPIO\n");
1289 if (!adcx140->gpio_reset)
1290 dev_info(&i2c->dev, "Reset GPIO not defined\n");
1291
1292 adcx140->supply_areg = devm_regulator_get_optional(adcx140->dev,
1293 "areg");
1294 if (IS_ERR(adcx140->supply_areg)) {
1295 if (PTR_ERR(adcx140->supply_areg) == -EPROBE_DEFER)
1296 return -EPROBE_DEFER;
1297
1298 adcx140->supply_areg = NULL;
1299 } else {
1300 ret = regulator_enable(adcx140->supply_areg);
1301 if (ret) {
1302 dev_err(adcx140->dev, "Failed to enable areg\n");
1303 return ret;
1304 }
1305
1306 ret = devm_add_action_or_reset(&i2c->dev, adcx140_disable_regulator, adcx140);
1307 if (ret)
1308 return ret;
1309 }
1310
1311 adcx140->regmap = devm_regmap_init_i2c(i2c, &adcx140_i2c_regmap);
1312 if (IS_ERR(adcx140->regmap)) {
1313 ret = PTR_ERR(adcx140->regmap);
1314 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1315 ret);
1316 return ret;
1317 }
1318
1319 regcache_cache_only(adcx140->regmap, true);
1320
1321 i2c_set_clientdata(i2c, adcx140);
1322
1323 return devm_snd_soc_register_component(&i2c->dev,
1324 &soc_codec_driver_adcx140,
1325 adcx140_dai_driver, 1);
1326 }
1327
1328 static const struct i2c_device_id adcx140_i2c_id[] = {
1329 { "tlv320adc3140", 0 },
1330 { "tlv320adc5140", 1 },
1331 { "tlv320adc6140", 2 },
1332 {}
1333 };
1334 MODULE_DEVICE_TABLE(i2c, adcx140_i2c_id);
1335
1336 static struct i2c_driver adcx140_i2c_driver = {
1337 .driver = {
1338 .name = "tlv320adcx140-codec",
1339 .of_match_table = of_match_ptr(tlv320adcx140_of_match),
1340 },
1341 .probe = adcx140_i2c_probe,
1342 .id_table = adcx140_i2c_id,
1343 };
1344 module_i2c_driver(adcx140_i2c_driver);
1345
1346 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
1347 MODULE_DESCRIPTION("ASoC TLV320ADCX140 CODEC Driver");
1348 MODULE_LICENSE("GPL v2");
1349