1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
3
4 #include <linux/bitfield.h>
5 #include <linux/clk.h>
6 #include <linux/interconnect.h>
7 #include <linux/of_platform.h>
8 #include <linux/platform_device.h>
9 #include <linux/pm_domain.h>
10 #include <linux/pm_opp.h>
11 #include <soc/qcom/cmd-db.h>
12 #include <soc/qcom/tcs.h>
13 #include <drm/drm_gem.h>
14
15 #include "a6xx_gpu.h"
16 #include "a6xx_gmu.xml.h"
17 #include "msm_gem.h"
18 #include "msm_gpu_trace.h"
19 #include "msm_mmu.h"
20
a6xx_gmu_fault(struct a6xx_gmu * gmu)21 static void a6xx_gmu_fault(struct a6xx_gmu *gmu)
22 {
23 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
24 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
25 struct msm_gpu *gpu = &adreno_gpu->base;
26
27 /* FIXME: add a banner here */
28 gmu->hung = true;
29
30 /* Turn off the hangcheck timer while we are resetting */
31 timer_delete(&gpu->hangcheck_timer);
32
33 /* Queue the GPU handler because we need to treat this as a recovery */
34 kthread_queue_work(gpu->worker, &gpu->recover_work);
35 }
36
a6xx_gmu_irq(int irq,void * data)37 static irqreturn_t a6xx_gmu_irq(int irq, void *data)
38 {
39 struct a6xx_gmu *gmu = data;
40 u32 status;
41
42 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS);
43 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status);
44
45 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) {
46 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n");
47
48 a6xx_gmu_fault(gmu);
49 }
50
51 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR)
52 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n");
53
54 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
55 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n",
56 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS));
57
58 return IRQ_HANDLED;
59 }
60
a6xx_hfi_irq(int irq,void * data)61 static irqreturn_t a6xx_hfi_irq(int irq, void *data)
62 {
63 struct a6xx_gmu *gmu = data;
64 u32 status;
65
66 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO);
67 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);
68
69 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) {
70 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n");
71
72 a6xx_gmu_fault(gmu);
73 }
74
75 return IRQ_HANDLED;
76 }
77
a6xx_gmu_sptprac_is_on(struct a6xx_gmu * gmu)78 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu)
79 {
80 u32 val;
81
82 /* This can be called from gpu state code so make sure GMU is valid */
83 if (!gmu->initialized)
84 return false;
85
86 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
87
88 return !(val &
89 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF |
90 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF));
91 }
92
93 /* Check to see if the GX rail is still powered */
a6xx_gmu_gx_is_on(struct a6xx_gmu * gmu)94 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
95 {
96 u32 val;
97
98 /* This can be called from gpu state code so make sure GMU is valid */
99 if (!gmu->initialized)
100 return false;
101
102 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
103
104 return !(val &
105 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF |
106 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
107 }
108
a6xx_gmu_set_freq(struct msm_gpu * gpu,struct dev_pm_opp * opp,bool suspended)109 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
110 bool suspended)
111 {
112 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
113 const struct a6xx_info *info = adreno_gpu->info->a6xx;
114 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
115 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
116 u32 perf_index;
117 u32 bw_index = 0;
118 unsigned long gpu_freq;
119 int ret = 0;
120
121 gpu_freq = dev_pm_opp_get_freq(opp);
122
123 if (gpu_freq == gmu->freq)
124 return;
125
126 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
127 if (gpu_freq == gmu->gpu_freqs[perf_index])
128 break;
129
130 /* If enabled, find the corresponding DDR bandwidth index */
131 if (info->bcms && gmu->nr_gpu_bws > 1) {
132 unsigned int bw = dev_pm_opp_get_bw(opp, true, 0);
133
134 for (bw_index = 0; bw_index < gmu->nr_gpu_bws - 1; bw_index++) {
135 if (bw == gmu->gpu_bw_table[bw_index])
136 break;
137 }
138
139 /* Vote AB as a fraction of the max bandwidth, starting from A750 */
140 if (bw && adreno_is_a750_family(adreno_gpu)) {
141 u64 tmp;
142
143 /* For now, vote for 25% of the bandwidth */
144 tmp = bw * 25;
145 do_div(tmp, 100);
146
147 /*
148 * The AB vote consists of a 16 bit wide quantized level
149 * against the maximum supported bandwidth.
150 * Quantization can be calculated as below:
151 * vote = (bandwidth * 2^16) / max bandwidth
152 */
153 tmp *= MAX_AB_VOTE;
154 do_div(tmp, gmu->gpu_bw_table[gmu->nr_gpu_bws - 1]);
155
156 bw_index |= AB_VOTE(clamp(tmp, 1, MAX_AB_VOTE));
157 bw_index |= AB_VOTE_ENABLE;
158 }
159 }
160
161 gmu->current_perf_index = perf_index;
162 gmu->freq = gmu->gpu_freqs[perf_index];
163
164 trace_msm_gmu_freq_change(gmu->freq, perf_index);
165
166 /*
167 * This can get called from devfreq while the hardware is idle. Don't
168 * bring up the power if it isn't already active. All we're doing here
169 * is updating the frequency so that when we come back online we're at
170 * the right rate.
171 */
172 if (suspended)
173 return;
174
175 if (!gmu->legacy) {
176 a6xx_hfi_set_freq(gmu, perf_index, bw_index);
177 /* With Bandwidth voting, we now vote for all resources, so skip OPP set */
178 if (!bw_index)
179 dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
180 return;
181 }
182
183 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
184
185 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
186 ((3 & 0xf) << 28) | perf_index);
187
188 /*
189 * Send an invalid index as a vote for the bus bandwidth and let the
190 * firmware decide on the right vote
191 */
192 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);
193
194 /* Set and clear the OOB for DCVS to trigger the GMU */
195 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET);
196 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET);
197
198 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
199 if (ret)
200 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
201
202 dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
203 }
204
a6xx_gmu_get_freq(struct msm_gpu * gpu)205 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
206 {
207 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
208 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
209 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
210
211 return gmu->freq;
212 }
213
a6xx_gmu_check_idle_level(struct a6xx_gmu * gmu)214 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
215 {
216 u32 val;
217 int local = gmu->idle_level;
218
219 /* SPTP and IFPC both report as IFPC */
220 if (gmu->idle_level == GMU_IDLE_STATE_SPTP)
221 local = GMU_IDLE_STATE_IFPC;
222
223 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
224
225 if (val == local) {
226 if (gmu->idle_level != GMU_IDLE_STATE_IFPC ||
227 !a6xx_gmu_gx_is_on(gmu))
228 return true;
229 }
230
231 return false;
232 }
233
234 /* Wait for the GMU to get to its most idle state */
a6xx_gmu_wait_for_idle(struct a6xx_gmu * gmu)235 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu)
236 {
237 return spin_until(a6xx_gmu_check_idle_level(gmu));
238 }
239
a6xx_gmu_start(struct a6xx_gmu * gmu)240 static int a6xx_gmu_start(struct a6xx_gmu *gmu)
241 {
242 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
243 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
244 u32 mask, reset_val, val;
245 int ret;
246
247 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);
248 if (val <= 0x20010004) {
249 mask = 0xffffffff;
250 reset_val = 0xbabeface;
251 } else {
252 mask = 0x1ff;
253 reset_val = 0x100;
254 }
255
256 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
257
258 /* Set the log wptr index
259 * note: downstream saves the value in poweroff and restores it here
260 */
261 if (adreno_is_a7xx(adreno_gpu))
262 gmu_write(gmu, REG_A7XX_GMU_GENERAL_9, 0);
263 else
264 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);
265
266
267 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);
268
269 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val,
270 (val & mask) == reset_val, 100, 10000);
271
272 if (ret)
273 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n");
274
275 return ret;
276 }
277
a6xx_gmu_hfi_start(struct a6xx_gmu * gmu)278 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu)
279 {
280 u32 val;
281 int ret;
282
283 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1);
284
285 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val,
286 val & 1, 100, 10000);
287 if (ret)
288 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n");
289
290 return ret;
291 }
292
293 struct a6xx_gmu_oob_bits {
294 int set, ack, set_new, ack_new, clear, clear_new;
295 const char *name;
296 };
297
298 /* These are the interrupt / ack bits for each OOB request that are set
299 * in a6xx_gmu_set_oob and a6xx_clear_oob
300 */
301 static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = {
302 [GMU_OOB_GPU_SET] = {
303 .name = "GPU_SET",
304 .set = 16,
305 .ack = 24,
306 .set_new = 30,
307 .ack_new = 31,
308 .clear = 24,
309 .clear_new = 31,
310 },
311
312 [GMU_OOB_PERFCOUNTER_SET] = {
313 .name = "PERFCOUNTER",
314 .set = 17,
315 .ack = 25,
316 .set_new = 28,
317 .ack_new = 30,
318 .clear = 25,
319 .clear_new = 29,
320 },
321
322 [GMU_OOB_BOOT_SLUMBER] = {
323 .name = "BOOT_SLUMBER",
324 .set = 22,
325 .ack = 30,
326 .clear = 30,
327 },
328
329 [GMU_OOB_DCVS_SET] = {
330 .name = "GPU_DCVS",
331 .set = 23,
332 .ack = 31,
333 .clear = 31,
334 },
335 };
336
337 /* Trigger a OOB (out of band) request to the GMU */
a6xx_gmu_set_oob(struct a6xx_gmu * gmu,enum a6xx_gmu_oob_state state)338 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
339 {
340 int ret;
341 u32 val;
342 int request, ack;
343
344 WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
345
346 if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
347 return -EINVAL;
348
349 if (gmu->legacy) {
350 request = a6xx_gmu_oob_bits[state].set;
351 ack = a6xx_gmu_oob_bits[state].ack;
352 } else {
353 request = a6xx_gmu_oob_bits[state].set_new;
354 ack = a6xx_gmu_oob_bits[state].ack_new;
355 if (!request || !ack) {
356 DRM_DEV_ERROR(gmu->dev,
357 "Invalid non-legacy GMU request %s\n",
358 a6xx_gmu_oob_bits[state].name);
359 return -EINVAL;
360 }
361 }
362
363 /* Trigger the equested OOB operation */
364 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);
365
366 /* Wait for the acknowledge interrupt */
367 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
368 val & (1 << ack), 100, 10000);
369
370 if (ret)
371 DRM_DEV_ERROR(gmu->dev,
372 "Timeout waiting for GMU OOB set %s: 0x%x\n",
373 a6xx_gmu_oob_bits[state].name,
374 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO));
375
376 /* Clear the acknowledge interrupt */
377 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack);
378
379 return ret;
380 }
381
382 /* Clear a pending OOB state in the GMU */
a6xx_gmu_clear_oob(struct a6xx_gmu * gmu,enum a6xx_gmu_oob_state state)383 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
384 {
385 int bit;
386
387 WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
388
389 if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
390 return;
391
392 if (gmu->legacy)
393 bit = a6xx_gmu_oob_bits[state].clear;
394 else
395 bit = a6xx_gmu_oob_bits[state].clear_new;
396
397 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit);
398 }
399
400 /* Enable CPU control of SPTP power power collapse */
a6xx_sptprac_enable(struct a6xx_gmu * gmu)401 int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
402 {
403 int ret;
404 u32 val;
405
406 if (!gmu->legacy)
407 return 0;
408
409 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);
410
411 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
412 (val & 0x38) == 0x28, 1, 100);
413
414 if (ret) {
415 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n",
416 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
417 }
418
419 return 0;
420 }
421
422 /* Disable CPU control of SPTP power power collapse */
a6xx_sptprac_disable(struct a6xx_gmu * gmu)423 void a6xx_sptprac_disable(struct a6xx_gmu *gmu)
424 {
425 u32 val;
426 int ret;
427
428 if (!gmu->legacy)
429 return;
430
431 /* Make sure retention is on */
432 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11));
433
434 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);
435
436 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
437 (val & 0x04), 100, 10000);
438
439 if (ret)
440 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n",
441 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
442 }
443
444 /* Let the GMU know we are starting a boot sequence */
a6xx_gmu_gfx_rail_on(struct a6xx_gmu * gmu)445 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu)
446 {
447 u32 vote;
448
449 /* Let the GMU know we are getting ready for boot */
450 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);
451
452 /* Choose the "default" power level as the highest available */
453 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1];
454
455 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);
456 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);
457
458 /* Let the GMU know the boot sequence has started */
459 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
460 }
461
a6xx_gemnoc_workaround(struct a6xx_gmu * gmu)462 static void a6xx_gemnoc_workaround(struct a6xx_gmu *gmu)
463 {
464 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
465 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
466
467 /*
468 * GEMNoC can power collapse whilst the GPU is being powered down, resulting
469 * in the power down sequence not being fully executed. That in turn can
470 * prevent CX_GDSC from collapsing. Assert Qactive to avoid this.
471 */
472 if (adreno_is_a621(adreno_gpu) || adreno_is_7c3(adreno_gpu))
473 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, BIT(0));
474 }
475
476 /* Let the GMU know that we are about to go into slumber */
a6xx_gmu_notify_slumber(struct a6xx_gmu * gmu)477 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu)
478 {
479 int ret;
480
481 /* Disable the power counter so the GMU isn't busy */
482 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);
483
484 /* Disable SPTP_PC if the CPU is responsible for it */
485 if (gmu->idle_level < GMU_IDLE_STATE_SPTP)
486 a6xx_sptprac_disable(gmu);
487
488 if (!gmu->legacy) {
489 ret = a6xx_hfi_send_prep_slumber(gmu);
490 goto out;
491 }
492
493 /* Tell the GMU to get ready to slumber */
494 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1);
495
496 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
497 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER);
498
499 if (!ret) {
500 /* Check to see if the GMU really did slumber */
501 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE)
502 != 0x0f) {
503 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n");
504 ret = -ETIMEDOUT;
505 }
506 }
507
508 out:
509 a6xx_gemnoc_workaround(gmu);
510
511 /* Put fence into allow mode */
512 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
513 return ret;
514 }
515
a6xx_rpmh_start(struct a6xx_gmu * gmu)516 static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
517 {
518 int ret;
519 u32 val;
520
521 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, BIT(1));
522
523 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val,
524 val & (1 << 1), 100, 10000);
525 if (ret) {
526 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n");
527 return ret;
528 }
529
530 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val,
531 !val, 100, 10000);
532
533 if (ret) {
534 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n");
535 return ret;
536 }
537
538 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
539
540 return 0;
541 }
542
a6xx_rpmh_stop(struct a6xx_gmu * gmu)543 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
544 {
545 int ret;
546 u32 val;
547
548 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
549
550 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
551 val, val & (1 << 16), 100, 10000);
552 if (ret)
553 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");
554
555 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
556 }
557
pdc_write(void __iomem * ptr,u32 offset,u32 value)558 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
559 {
560 writel(value, ptr + (offset << 2));
561 }
562
563 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
564 const char *name);
565
a6xx_gmu_rpmh_init(struct a6xx_gmu * gmu)566 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
567 {
568 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
569 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
570 struct platform_device *pdev = to_platform_device(gmu->dev);
571 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
572 u32 seqmem0_drv0_reg = REG_A6XX_RSCC_SEQ_MEM_0_DRV0;
573 void __iomem *seqptr = NULL;
574 uint32_t pdc_address_offset;
575 bool pdc_in_aop = false;
576
577 if (IS_ERR(pdcptr))
578 goto err;
579
580 if (adreno_is_a650_family(adreno_gpu) ||
581 adreno_is_a7xx(adreno_gpu))
582 pdc_in_aop = true;
583 else if (adreno_is_a618(adreno_gpu) || adreno_is_a640_family(adreno_gpu))
584 pdc_address_offset = 0x30090;
585 else if (adreno_is_a619(adreno_gpu))
586 pdc_address_offset = 0x300a0;
587 else
588 pdc_address_offset = 0x30080;
589
590 if (!pdc_in_aop) {
591 seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
592 if (IS_ERR(seqptr))
593 goto err;
594 }
595
596 /* Disable SDE clock gating */
597 gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
598
599 /* Setup RSC PDC handshake for sleep and wakeup */
600 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
601 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
602 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
603 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
604 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
605 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4,
606 adreno_is_a740_family(adreno_gpu) ? 0x80000021 : 0x80000000);
607 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
608 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
609 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
610 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
611 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
612
613 /* The second spin of A7xx GPUs messed with some register offsets.. */
614 if (adreno_is_a740_family(adreno_gpu))
615 seqmem0_drv0_reg = REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740;
616
617 /* Load RSC sequencer uCode for sleep and wakeup */
618 if (adreno_is_a650_family(adreno_gpu) ||
619 adreno_is_a7xx(adreno_gpu)) {
620 gmu_write_rscc(gmu, seqmem0_drv0_reg, 0xeaaae5a0);
621 gmu_write_rscc(gmu, seqmem0_drv0_reg + 1, 0xe1a1ebab);
622 gmu_write_rscc(gmu, seqmem0_drv0_reg + 2, 0xa2e0a581);
623 gmu_write_rscc(gmu, seqmem0_drv0_reg + 3, 0xecac82e2);
624 gmu_write_rscc(gmu, seqmem0_drv0_reg + 4, 0x0020edad);
625 } else {
626 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
627 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
628 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
629 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
630 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
631 }
632
633 if (pdc_in_aop)
634 goto setup_pdc;
635
636 /* Load PDC sequencer uCode for power up and power down sequence */
637 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
638 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
639 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
640 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
641 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
642
643 /* Set TCS commands used by PDC sequence for low power modes */
644 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
645 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
646 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
647 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
648 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
649 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
650 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
651 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
652 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
653
654 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
655 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset);
656 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
657
658 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
659 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
660 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
661 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
662 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
663 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
664
665 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
666 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
667 if (adreno_is_a618(adreno_gpu) || adreno_is_a619(adreno_gpu) ||
668 adreno_is_a650_family(adreno_gpu))
669 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
670 else
671 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
672 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
673 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset);
674 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
675
676 /* Setup GPU PDC */
677 setup_pdc:
678 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
679 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
680
681 /* ensure no writes happen before the uCode is fully written */
682 wmb();
683
684 a6xx_rpmh_stop(gmu);
685
686 err:
687 if (!IS_ERR_OR_NULL(pdcptr))
688 iounmap(pdcptr);
689 if (!IS_ERR_OR_NULL(seqptr))
690 iounmap(seqptr);
691 }
692
693 /*
694 * The lowest 16 bits of this value are the number of XO clock cycles for main
695 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are
696 * for the shorter hysteresis that happens after main - this is 0xa (.5 us)
697 */
698
699 #define GMU_PWR_COL_HYST 0x000a1680
700
701 /* Set up the idle state for the GMU */
a6xx_gmu_power_config(struct a6xx_gmu * gmu)702 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu)
703 {
704 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
705 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
706
707 /* Disable GMU WB/RB buffer */
708 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);
709 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);
710 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);
711
712 /* A7xx knows better by default! */
713 if (adreno_is_a7xx(adreno_gpu))
714 return;
715
716 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);
717
718 switch (gmu->idle_level) {
719 case GMU_IDLE_STATE_IFPC:
720 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST,
721 GMU_PWR_COL_HYST);
722 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
723 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
724 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE);
725 fallthrough;
726 case GMU_IDLE_STATE_SPTP:
727 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,
728 GMU_PWR_COL_HYST);
729 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
730 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
731 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE);
732 }
733
734 /* Enable RPMh GPU client */
735 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0,
736 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE |
737 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE |
738 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE |
739 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE |
740 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE |
741 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE);
742 }
743
744 struct block_header {
745 u32 addr;
746 u32 size;
747 u32 type;
748 u32 value;
749 u32 data[];
750 };
751
fw_block_mem(struct a6xx_gmu_bo * bo,const struct block_header * blk)752 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk)
753 {
754 if (!in_range(blk->addr, bo->iova, bo->size))
755 return false;
756
757 memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size);
758 return true;
759 }
760
a6xx_gmu_fw_load(struct a6xx_gmu * gmu)761 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)
762 {
763 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
764 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
765 const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU];
766 const struct block_header *blk;
767 u32 reg_offset;
768 u32 ver;
769
770 u32 itcm_base = 0x00000000;
771 u32 dtcm_base = 0x00040000;
772
773 if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu))
774 dtcm_base = 0x10004000;
775
776 if (gmu->legacy) {
777 /* Sanity check the size of the firmware that was loaded */
778 if (fw_image->size > 0x8000) {
779 DRM_DEV_ERROR(gmu->dev,
780 "GMU firmware is bigger than the available region\n");
781 return -EINVAL;
782 }
783
784 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START,
785 (u32*) fw_image->data, fw_image->size);
786 return 0;
787 }
788
789
790 for (blk = (const struct block_header *) fw_image->data;
791 (const u8*) blk < fw_image->data + fw_image->size;
792 blk = (const struct block_header *) &blk->data[blk->size >> 2]) {
793 if (blk->size == 0)
794 continue;
795
796 if (in_range(blk->addr, itcm_base, SZ_16K)) {
797 reg_offset = (blk->addr - itcm_base) >> 2;
798 gmu_write_bulk(gmu,
799 REG_A6XX_GMU_CM3_ITCM_START + reg_offset,
800 blk->data, blk->size);
801 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) {
802 reg_offset = (blk->addr - dtcm_base) >> 2;
803 gmu_write_bulk(gmu,
804 REG_A6XX_GMU_CM3_DTCM_START + reg_offset,
805 blk->data, blk->size);
806 } else if (!fw_block_mem(&gmu->icache, blk) &&
807 !fw_block_mem(&gmu->dcache, blk) &&
808 !fw_block_mem(&gmu->dummy, blk)) {
809 DRM_DEV_ERROR(gmu->dev,
810 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n",
811 blk->addr, blk->size, blk->data[0]);
812 }
813 }
814
815 ver = gmu_read(gmu, REG_A6XX_GMU_CORE_FW_VERSION);
816 DRM_INFO_ONCE("Loaded GMU firmware v%u.%u.%u\n",
817 FIELD_GET(A6XX_GMU_CORE_FW_VERSION_MAJOR__MASK, ver),
818 FIELD_GET(A6XX_GMU_CORE_FW_VERSION_MINOR__MASK, ver),
819 FIELD_GET(A6XX_GMU_CORE_FW_VERSION_STEP__MASK, ver));
820
821 return 0;
822 }
823
a6xx_gmu_fw_start(struct a6xx_gmu * gmu,unsigned int state)824 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
825 {
826 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
827 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
828 const struct a6xx_info *a6xx_info = adreno_gpu->info->a6xx;
829 u32 fence_range_lower, fence_range_upper;
830 u32 chipid = 0;
831 int ret;
832
833 /* Vote veto for FAL10 */
834 if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) {
835 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);
836 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
837 }
838
839 /* Turn on TCM (Tightly Coupled Memory) retention */
840 if (adreno_is_a7xx(adreno_gpu))
841 a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1);
842 else
843 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
844
845 if (state == GMU_WARM_BOOT) {
846 ret = a6xx_rpmh_start(gmu);
847 if (ret)
848 return ret;
849 } else {
850 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU],
851 "GMU firmware is not loaded\n"))
852 return -ENOENT;
853
854 ret = a6xx_rpmh_start(gmu);
855 if (ret)
856 return ret;
857
858 ret = a6xx_gmu_fw_load(gmu);
859 if (ret)
860 return ret;
861 }
862
863 /* Clear init result to make sure we are getting a fresh value */
864 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);
865 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);
866
867 /* Write the iova of the HFI table */
868 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova);
869 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1);
870
871 if (adreno_is_a7xx(adreno_gpu)) {
872 fence_range_upper = 0x32;
873 fence_range_lower = 0x8a0;
874 } else {
875 fence_range_upper = 0xa;
876 fence_range_lower = 0xa0;
877 }
878
879 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
880 BIT(31) |
881 FIELD_PREP(GENMASK(30, 18), fence_range_upper) |
882 FIELD_PREP(GENMASK(17, 0), fence_range_lower));
883
884 /*
885 * Snapshots toggle the NMI bit which will result in a jump to the NMI
886 * handler instead of __main. Set the M3 config value to avoid that.
887 */
888 gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052);
889
890 if (a6xx_info->gmu_chipid) {
891 chipid = a6xx_info->gmu_chipid;
892 } else {
893 /*
894 * Note that the GMU has a slightly different layout for
895 * chip_id, for whatever reason, so a bit of massaging
896 * is needed. The upper 16b are the same, but minor and
897 * patchid are packed in four bits each with the lower
898 * 8b unused:
899 */
900 chipid = adreno_gpu->chip_id & 0xffff0000;
901 chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */
902 chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
903 }
904
905 if (adreno_is_a7xx(adreno_gpu)) {
906 gmu_write(gmu, REG_A7XX_GMU_GENERAL_10, chipid);
907 gmu_write(gmu, REG_A7XX_GMU_GENERAL_8,
908 (gmu->log.iova & GENMASK(31, 12)) |
909 ((gmu->log.size / SZ_4K - 1) & GENMASK(7, 0)));
910 } else {
911 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
912
913 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,
914 gmu->log.iova | (gmu->log.size / SZ_4K - 1));
915 }
916
917 /* Set up the lowest idle level on the GMU */
918 a6xx_gmu_power_config(gmu);
919
920 ret = a6xx_gmu_start(gmu);
921 if (ret)
922 return ret;
923
924 if (gmu->legacy) {
925 ret = a6xx_gmu_gfx_rail_on(gmu);
926 if (ret)
927 return ret;
928 }
929
930 /* Enable SPTP_PC if the CPU is responsible for it */
931 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) {
932 ret = a6xx_sptprac_enable(gmu);
933 if (ret)
934 return ret;
935 }
936
937 ret = a6xx_gmu_hfi_start(gmu);
938 if (ret)
939 return ret;
940
941 /* FIXME: Do we need this wmb() here? */
942 wmb();
943
944 return 0;
945 }
946
947 #define A6XX_HFI_IRQ_MASK \
948 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT)
949
950 #define A6XX_GMU_IRQ_MASK \
951 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \
952 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \
953 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
954
a6xx_gmu_irq_disable(struct a6xx_gmu * gmu)955 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu)
956 {
957 disable_irq(gmu->gmu_irq);
958 disable_irq(gmu->hfi_irq);
959
960 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);
961 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);
962 }
963
a6xx_gmu_rpmh_off(struct a6xx_gmu * gmu)964 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
965 {
966 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
967 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
968 u32 val, seqmem_off = 0;
969
970 /* The second spin of A7xx GPUs messed with some register offsets.. */
971 if (adreno_is_a740_family(adreno_gpu))
972 seqmem_off = 4;
973
974 /* Make sure there are no outstanding RPMh votes */
975 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS + seqmem_off,
976 val, (val & 1), 100, 10000);
977 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS + seqmem_off,
978 val, (val & 1), 100, 10000);
979 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS + seqmem_off,
980 val, (val & 1), 100, 10000);
981 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off,
982 val, (val & 1), 100, 1000);
983 }
984
985 /* Force the GMU off in case it isn't responsive */
a6xx_gmu_force_off(struct a6xx_gmu * gmu)986 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
987 {
988 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
989 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
990 struct msm_gpu *gpu = &adreno_gpu->base;
991
992 /*
993 * Turn off keep alive that might have been enabled by the hang
994 * interrupt
995 */
996 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
997
998 /* Flush all the queues */
999 a6xx_hfi_stop(gmu);
1000
1001 /* Stop the interrupts */
1002 a6xx_gmu_irq_disable(gmu);
1003
1004 /* Force off SPTP in case the GMU is managing it */
1005 a6xx_sptprac_disable(gmu);
1006
1007 a6xx_gemnoc_workaround(gmu);
1008
1009 /* Make sure there are no outstanding RPMh votes */
1010 a6xx_gmu_rpmh_off(gmu);
1011
1012 /* Clear the WRITEDROPPED fields and put fence into allow mode */
1013 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7);
1014 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
1015
1016 /* Make sure the above writes go through */
1017 wmb();
1018
1019 /* Halt the gmu cm3 core */
1020 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
1021
1022 a6xx_bus_clear_pending_transactions(adreno_gpu, true);
1023
1024 /* Reset GPU core blocks */
1025 a6xx_gpu_sw_reset(gpu, true);
1026 }
1027
a6xx_gmu_set_initial_freq(struct msm_gpu * gpu,struct a6xx_gmu * gmu)1028 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
1029 {
1030 struct dev_pm_opp *gpu_opp;
1031 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
1032
1033 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
1034 if (IS_ERR(gpu_opp))
1035 return;
1036
1037 gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */
1038 a6xx_gmu_set_freq(gpu, gpu_opp, false);
1039 dev_pm_opp_put(gpu_opp);
1040 }
1041
a6xx_gmu_set_initial_bw(struct msm_gpu * gpu,struct a6xx_gmu * gmu)1042 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
1043 {
1044 struct dev_pm_opp *gpu_opp;
1045 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
1046
1047 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
1048 if (IS_ERR(gpu_opp))
1049 return;
1050
1051 dev_pm_opp_set_opp(&gpu->pdev->dev, gpu_opp);
1052 dev_pm_opp_put(gpu_opp);
1053 }
1054
a6xx_gmu_resume(struct a6xx_gpu * a6xx_gpu)1055 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
1056 {
1057 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1058 struct msm_gpu *gpu = &adreno_gpu->base;
1059 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1060 int status, ret;
1061
1062 if (WARN(!gmu->initialized, "The GMU is not set up yet\n"))
1063 return -EINVAL;
1064
1065 gmu->hung = false;
1066
1067 /* Notify AOSS about the ACD state (unimplemented for now => disable it) */
1068 if (!IS_ERR(gmu->qmp)) {
1069 ret = qmp_send(gmu->qmp, "{class: gpu, res: acd, val: %d}",
1070 0 /* Hardcode ACD to be disabled for now */);
1071 if (ret)
1072 dev_err(gmu->dev, "failed to send GPU ACD state\n");
1073 }
1074
1075 /* Turn on the resources */
1076 pm_runtime_get_sync(gmu->dev);
1077
1078 /*
1079 * "enable" the GX power domain which won't actually do anything but it
1080 * will make sure that the refcounting is correct in case we need to
1081 * bring down the GX after a GMU failure
1082 */
1083 if (!IS_ERR_OR_NULL(gmu->gxpd))
1084 pm_runtime_get_sync(gmu->gxpd);
1085
1086 /* Use a known rate to bring up the GMU */
1087 clk_set_rate(gmu->core_clk, 200000000);
1088 clk_set_rate(gmu->hub_clk, adreno_is_a740_family(adreno_gpu) ?
1089 200000000 : 150000000);
1090 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);
1091 if (ret) {
1092 pm_runtime_put(gmu->gxpd);
1093 pm_runtime_put(gmu->dev);
1094 return ret;
1095 }
1096
1097 /* Set the bus quota to a reasonable value for boot */
1098 a6xx_gmu_set_initial_bw(gpu, gmu);
1099
1100 /* Enable the GMU interrupt */
1101 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
1102 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK);
1103 enable_irq(gmu->gmu_irq);
1104
1105 /* Check to see if we are doing a cold or warm boot */
1106 if (adreno_is_a7xx(adreno_gpu)) {
1107 status = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) == 1 ?
1108 GMU_WARM_BOOT : GMU_COLD_BOOT;
1109 } else if (gmu->legacy) {
1110 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ?
1111 GMU_WARM_BOOT : GMU_COLD_BOOT;
1112 } else {
1113 /*
1114 * Warm boot path does not work on newer A6xx GPUs
1115 * Presumably this is because icache/dcache regions must be restored
1116 */
1117 status = GMU_COLD_BOOT;
1118 }
1119
1120 ret = a6xx_gmu_fw_start(gmu, status);
1121 if (ret)
1122 goto out;
1123
1124 ret = a6xx_hfi_start(gmu, status);
1125 if (ret)
1126 goto out;
1127
1128 /*
1129 * Turn on the GMU firmware fault interrupt after we know the boot
1130 * sequence is successful
1131 */
1132 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);
1133 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK);
1134 enable_irq(gmu->hfi_irq);
1135
1136 /* Set the GPU to the current freq */
1137 a6xx_gmu_set_initial_freq(gpu, gmu);
1138
1139 out:
1140 /* On failure, shut down the GMU to leave it in a good state */
1141 if (ret) {
1142 disable_irq(gmu->gmu_irq);
1143 a6xx_rpmh_stop(gmu);
1144 pm_runtime_put(gmu->gxpd);
1145 pm_runtime_put(gmu->dev);
1146 }
1147
1148 return ret;
1149 }
1150
a6xx_gmu_isidle(struct a6xx_gmu * gmu)1151 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu)
1152 {
1153 u32 reg;
1154
1155 if (!gmu->initialized)
1156 return true;
1157
1158 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS);
1159
1160 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB)
1161 return false;
1162
1163 return true;
1164 }
1165
1166 /* Gracefully try to shut down the GMU and by extension the GPU */
a6xx_gmu_shutdown(struct a6xx_gmu * gmu)1167 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu)
1168 {
1169 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1170 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1171 u32 val;
1172 int ret;
1173
1174 /*
1175 * GMU firmware's internal power state gets messed up if we send "prepare_slumber" hfi when
1176 * oob_gpu handshake wasn't done after the last wake up. So do a dummy handshake here when
1177 * required
1178 */
1179 if (adreno_gpu->base.needs_hw_init) {
1180 if (a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET))
1181 goto force_off;
1182
1183 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
1184 }
1185
1186 ret = a6xx_gmu_wait_for_idle(gmu);
1187
1188 /* If the GMU isn't responding assume it is hung */
1189 if (ret)
1190 goto force_off;
1191
1192 a6xx_bus_clear_pending_transactions(adreno_gpu, a6xx_gpu->hung);
1193
1194 /* tell the GMU we want to slumber */
1195 ret = a6xx_gmu_notify_slumber(gmu);
1196 if (ret)
1197 goto force_off;
1198
1199 ret = gmu_poll_timeout(gmu,
1200 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val,
1201 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB),
1202 100, 10000);
1203
1204 /*
1205 * Let the user know we failed to slumber but don't worry too
1206 * much because we are powering down anyway
1207 */
1208
1209 if (ret)
1210 DRM_DEV_ERROR(gmu->dev,
1211 "Unable to slumber GMU: status = 0%x/0%x\n",
1212 gmu_read(gmu,
1213 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS),
1214 gmu_read(gmu,
1215 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2));
1216
1217 /* Turn off HFI */
1218 a6xx_hfi_stop(gmu);
1219
1220 /* Stop the interrupts and mask the hardware */
1221 a6xx_gmu_irq_disable(gmu);
1222
1223 /* Tell RPMh to power off the GPU */
1224 a6xx_rpmh_stop(gmu);
1225
1226 return;
1227
1228 force_off:
1229 a6xx_gmu_force_off(gmu);
1230 }
1231
1232
a6xx_gmu_stop(struct a6xx_gpu * a6xx_gpu)1233 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
1234 {
1235 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1236 struct msm_gpu *gpu = &a6xx_gpu->base.base;
1237
1238 if (!pm_runtime_active(gmu->dev))
1239 return 0;
1240
1241 /*
1242 * Force the GMU off if we detected a hang, otherwise try to shut it
1243 * down gracefully
1244 */
1245 if (gmu->hung)
1246 a6xx_gmu_force_off(gmu);
1247 else
1248 a6xx_gmu_shutdown(gmu);
1249
1250 /* Remove the bus vote */
1251 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL);
1252
1253 /*
1254 * Make sure the GX domain is off before turning off the GMU (CX)
1255 * domain. Usually the GMU does this but only if the shutdown sequence
1256 * was successful
1257 */
1258 if (!IS_ERR_OR_NULL(gmu->gxpd))
1259 pm_runtime_put_sync(gmu->gxpd);
1260
1261 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
1262
1263 pm_runtime_put_sync(gmu->dev);
1264
1265 return 0;
1266 }
1267
a6xx_gmu_memory_free(struct a6xx_gmu * gmu)1268 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu)
1269 {
1270 msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace);
1271 msm_gem_kernel_put(gmu->debug.obj, gmu->aspace);
1272 msm_gem_kernel_put(gmu->icache.obj, gmu->aspace);
1273 msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace);
1274 msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace);
1275 msm_gem_kernel_put(gmu->log.obj, gmu->aspace);
1276
1277 gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu);
1278 msm_gem_address_space_put(gmu->aspace);
1279 }
1280
a6xx_gmu_memory_alloc(struct a6xx_gmu * gmu,struct a6xx_gmu_bo * bo,size_t size,u64 iova,const char * name)1281 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo,
1282 size_t size, u64 iova, const char *name)
1283 {
1284 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1285 struct drm_device *dev = a6xx_gpu->base.base.dev;
1286 uint32_t flags = MSM_BO_WC;
1287 u64 range_start, range_end;
1288 int ret;
1289
1290 size = PAGE_ALIGN(size);
1291 if (!iova) {
1292 /* no fixed address - use GMU's uncached range */
1293 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */
1294 range_end = 0x80000000;
1295 } else {
1296 /* range for fixed address */
1297 range_start = iova;
1298 range_end = iova + size;
1299 /* use IOMMU_PRIV for icache/dcache */
1300 flags |= MSM_BO_MAP_PRIV;
1301 }
1302
1303 bo->obj = msm_gem_new(dev, size, flags);
1304 if (IS_ERR(bo->obj))
1305 return PTR_ERR(bo->obj);
1306
1307 ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova,
1308 range_start, range_end);
1309 if (ret) {
1310 drm_gem_object_put(bo->obj);
1311 return ret;
1312 }
1313
1314 bo->virt = msm_gem_get_vaddr(bo->obj);
1315 bo->size = size;
1316
1317 msm_gem_object_set_name(bo->obj, "%s", name);
1318
1319 return 0;
1320 }
1321
a6xx_gmu_memory_probe(struct a6xx_gmu * gmu)1322 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
1323 {
1324 struct msm_mmu *mmu;
1325
1326 mmu = msm_iommu_new(gmu->dev, 0);
1327 if (!mmu)
1328 return -ENODEV;
1329 if (IS_ERR(mmu))
1330 return PTR_ERR(mmu);
1331
1332 gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);
1333 if (IS_ERR(gmu->aspace))
1334 return PTR_ERR(gmu->aspace);
1335
1336 return 0;
1337 }
1338
1339 /**
1340 * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager (BCM)
1341 * @unit: divisor used to convert bytes/sec bw value to an RPMh msg
1342 * @width: multiplier used to convert bytes/sec bw value to an RPMh msg
1343 * @vcd: virtual clock domain that this bcm belongs to
1344 * @reserved: reserved field
1345 */
1346 struct bcm_db {
1347 __le32 unit;
1348 __le16 width;
1349 u8 vcd;
1350 u8 reserved;
1351 };
1352
a6xx_gmu_rpmh_bw_votes_init(struct adreno_gpu * adreno_gpu,const struct a6xx_info * info,struct a6xx_gmu * gmu)1353 static int a6xx_gmu_rpmh_bw_votes_init(struct adreno_gpu *adreno_gpu,
1354 const struct a6xx_info *info,
1355 struct a6xx_gmu *gmu)
1356 {
1357 const struct bcm_db *bcm_data[GMU_MAX_BCMS] = { 0 };
1358 unsigned int bcm_index, bw_index, bcm_count = 0;
1359
1360 /* Retrieve BCM data from cmd-db */
1361 for (bcm_index = 0; bcm_index < GMU_MAX_BCMS; bcm_index++) {
1362 const struct a6xx_bcm *bcm = &info->bcms[bcm_index];
1363 size_t count;
1364
1365 /* Stop at NULL terminated bcm entry */
1366 if (!bcm->name)
1367 break;
1368
1369 bcm_data[bcm_index] = cmd_db_read_aux_data(bcm->name, &count);
1370 if (IS_ERR(bcm_data[bcm_index]))
1371 return PTR_ERR(bcm_data[bcm_index]);
1372
1373 if (!count) {
1374 dev_err(gmu->dev, "invalid BCM '%s' aux data size\n",
1375 bcm->name);
1376 return -EINVAL;
1377 }
1378
1379 bcm_count++;
1380 }
1381
1382 /* Generate BCM votes values for each bandwidth & BCM */
1383 for (bw_index = 0; bw_index < gmu->nr_gpu_bws; bw_index++) {
1384 u32 *data = gmu->gpu_ib_votes[bw_index];
1385 u32 bw = gmu->gpu_bw_table[bw_index];
1386
1387 /* Calculations loosely copied from bcm_aggregate() & tcs_cmd_gen() */
1388 for (bcm_index = 0; bcm_index < bcm_count; bcm_index++) {
1389 const struct a6xx_bcm *bcm = &info->bcms[bcm_index];
1390 bool commit = false;
1391 u64 peak;
1392 u32 vote;
1393
1394 if (bcm_index == bcm_count - 1 ||
1395 (bcm_data[bcm_index + 1] &&
1396 bcm_data[bcm_index]->vcd != bcm_data[bcm_index + 1]->vcd))
1397 commit = true;
1398
1399 if (!bw) {
1400 data[bcm_index] = BCM_TCS_CMD(commit, false, 0, 0);
1401 continue;
1402 }
1403
1404 if (bcm->fixed) {
1405 u32 perfmode = 0;
1406
1407 /* GMU on A6xx votes perfmode on all valid bandwidth */
1408 if (!adreno_is_a7xx(adreno_gpu) ||
1409 (bcm->perfmode_bw && bw >= bcm->perfmode_bw))
1410 perfmode = bcm->perfmode;
1411
1412 data[bcm_index] = BCM_TCS_CMD(commit, true, 0, perfmode);
1413 continue;
1414 }
1415
1416 /* Multiply the bandwidth by the width of the connection */
1417 peak = (u64)bw * le16_to_cpu(bcm_data[bcm_index]->width);
1418 do_div(peak, bcm->buswidth);
1419
1420 /* Input bandwidth value is in KBps, scale the value to BCM unit */
1421 peak *= 1000;
1422 do_div(peak, le32_to_cpu(bcm_data[bcm_index]->unit));
1423
1424 vote = clamp(peak, 1, BCM_TCS_CMD_VOTE_MASK);
1425
1426 /* GMUs on A7xx votes on both x & y */
1427 if (adreno_is_a7xx(adreno_gpu))
1428 data[bcm_index] = BCM_TCS_CMD(commit, true, vote, vote);
1429 else
1430 data[bcm_index] = BCM_TCS_CMD(commit, true, 0, vote);
1431 }
1432 }
1433
1434 return 0;
1435 }
1436
1437 /* Return the 'arc-level' for the given frequency */
a6xx_gmu_get_arc_level(struct device * dev,unsigned long freq)1438 static unsigned int a6xx_gmu_get_arc_level(struct device *dev,
1439 unsigned long freq)
1440 {
1441 struct dev_pm_opp *opp;
1442 unsigned int val;
1443
1444 if (!freq)
1445 return 0;
1446
1447 opp = dev_pm_opp_find_freq_exact(dev, freq, true);
1448 if (IS_ERR(opp))
1449 return 0;
1450
1451 val = dev_pm_opp_get_level(opp);
1452
1453 dev_pm_opp_put(opp);
1454
1455 return val;
1456 }
1457
a6xx_gmu_rpmh_arc_votes_init(struct device * dev,u32 * votes,unsigned long * freqs,int freqs_count,const char * id)1458 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
1459 unsigned long *freqs, int freqs_count, const char *id)
1460 {
1461 int i, j;
1462 const u16 *pri, *sec;
1463 size_t pri_count, sec_count;
1464
1465 pri = cmd_db_read_aux_data(id, &pri_count);
1466 if (IS_ERR(pri))
1467 return PTR_ERR(pri);
1468 /*
1469 * The data comes back as an array of unsigned shorts so adjust the
1470 * count accordingly
1471 */
1472 pri_count >>= 1;
1473 if (!pri_count)
1474 return -EINVAL;
1475
1476 /*
1477 * Some targets have a separate gfx mxc rail. So try to read that first and then fall back
1478 * to regular mx rail if it is missing
1479 */
1480 sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count);
1481 if (IS_ERR(sec) && sec != ERR_PTR(-EPROBE_DEFER))
1482 sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
1483 if (IS_ERR(sec))
1484 return PTR_ERR(sec);
1485
1486 sec_count >>= 1;
1487 if (!sec_count)
1488 return -EINVAL;
1489
1490 /* Construct a vote for each frequency */
1491 for (i = 0; i < freqs_count; i++) {
1492 u8 pindex = 0, sindex = 0;
1493 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]);
1494
1495 /* Get the primary index that matches the arc level */
1496 for (j = 0; j < pri_count; j++) {
1497 if (pri[j] >= level) {
1498 pindex = j;
1499 break;
1500 }
1501 }
1502
1503 if (j == pri_count) {
1504 DRM_DEV_ERROR(dev,
1505 "Level %u not found in the RPMh list\n",
1506 level);
1507 DRM_DEV_ERROR(dev, "Available levels:\n");
1508 for (j = 0; j < pri_count; j++)
1509 DRM_DEV_ERROR(dev, " %u\n", pri[j]);
1510
1511 return -EINVAL;
1512 }
1513
1514 /*
1515 * Look for a level in in the secondary list that matches. If
1516 * nothing fits, use the maximum non zero vote
1517 */
1518
1519 for (j = 0; j < sec_count; j++) {
1520 if (sec[j] >= level) {
1521 sindex = j;
1522 break;
1523 } else if (sec[j]) {
1524 sindex = j;
1525 }
1526 }
1527
1528 /* Construct the vote */
1529 votes[i] = ((pri[pindex] & 0xffff) << 16) |
1530 (sindex << 8) | pindex;
1531 }
1532
1533 return 0;
1534 }
1535
1536 /*
1537 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need
1538 * to construct the list of votes on the CPU and send it over. Query the RPMh
1539 * voltage levels and build the votes
1540 * The GMU can also vote for DDR interconnects, use the OPP bandwidth entries
1541 * and BCM parameters to build the votes.
1542 */
1543
a6xx_gmu_rpmh_votes_init(struct a6xx_gmu * gmu)1544 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu)
1545 {
1546 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1547 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1548 const struct a6xx_info *info = adreno_gpu->info->a6xx;
1549 struct msm_gpu *gpu = &adreno_gpu->base;
1550 int ret;
1551
1552 /* Build the GX votes */
1553 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes,
1554 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl");
1555
1556 /* Build the CX votes */
1557 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes,
1558 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl");
1559
1560 /* Build the interconnect votes */
1561 if (info->bcms && gmu->nr_gpu_bws > 1)
1562 ret |= a6xx_gmu_rpmh_bw_votes_init(adreno_gpu, info, gmu);
1563
1564 return ret;
1565 }
1566
a6xx_gmu_build_freq_table(struct device * dev,unsigned long * freqs,u32 size)1567 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs,
1568 u32 size)
1569 {
1570 int count = dev_pm_opp_get_opp_count(dev);
1571 struct dev_pm_opp *opp;
1572 int i, index = 0;
1573 unsigned long freq = 1;
1574
1575 /*
1576 * The OPP table doesn't contain the "off" frequency level so we need to
1577 * add 1 to the table size to account for it
1578 */
1579
1580 if (WARN(count + 1 > size,
1581 "The GMU frequency table is being truncated\n"))
1582 count = size - 1;
1583
1584 /* Set the "off" frequency */
1585 freqs[index++] = 0;
1586
1587 for (i = 0; i < count; i++) {
1588 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
1589 if (IS_ERR(opp))
1590 break;
1591
1592 dev_pm_opp_put(opp);
1593 freqs[index++] = freq++;
1594 }
1595
1596 return index;
1597 }
1598
a6xx_gmu_build_bw_table(struct device * dev,unsigned long * bandwidths,u32 size)1599 static int a6xx_gmu_build_bw_table(struct device *dev, unsigned long *bandwidths,
1600 u32 size)
1601 {
1602 int count = dev_pm_opp_get_opp_count(dev);
1603 struct dev_pm_opp *opp;
1604 int i, index = 0;
1605 unsigned int bandwidth = 1;
1606
1607 /*
1608 * The OPP table doesn't contain the "off" bandwidth level so we need to
1609 * add 1 to the table size to account for it
1610 */
1611
1612 if (WARN(count + 1 > size,
1613 "The GMU bandwidth table is being truncated\n"))
1614 count = size - 1;
1615
1616 /* Set the "off" bandwidth */
1617 bandwidths[index++] = 0;
1618
1619 for (i = 0; i < count; i++) {
1620 opp = dev_pm_opp_find_bw_ceil(dev, &bandwidth, 0);
1621 if (IS_ERR(opp))
1622 break;
1623
1624 dev_pm_opp_put(opp);
1625 bandwidths[index++] = bandwidth++;
1626 }
1627
1628 return index;
1629 }
1630
a6xx_gmu_pwrlevels_probe(struct a6xx_gmu * gmu)1631 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu)
1632 {
1633 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1634 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1635 const struct a6xx_info *info = adreno_gpu->info->a6xx;
1636 struct msm_gpu *gpu = &adreno_gpu->base;
1637
1638 int ret = 0;
1639
1640 /*
1641 * The GMU handles its own frequency switching so build a list of
1642 * available frequencies to send during initialization
1643 */
1644 ret = devm_pm_opp_of_add_table(gmu->dev);
1645 if (ret) {
1646 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n");
1647 return ret;
1648 }
1649
1650 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev,
1651 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs));
1652
1653 /*
1654 * The GMU also handles GPU frequency switching so build a list
1655 * from the GPU OPP table
1656 */
1657 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev,
1658 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs));
1659
1660 gmu->current_perf_index = gmu->nr_gpu_freqs - 1;
1661
1662 /*
1663 * The GMU also handles GPU Interconnect Votes so build a list
1664 * of DDR bandwidths from the GPU OPP table
1665 */
1666 if (info->bcms)
1667 gmu->nr_gpu_bws = a6xx_gmu_build_bw_table(&gpu->pdev->dev,
1668 gmu->gpu_bw_table, ARRAY_SIZE(gmu->gpu_bw_table));
1669
1670 /* Build the list of RPMh votes that we'll send to the GMU */
1671 return a6xx_gmu_rpmh_votes_init(gmu);
1672 }
1673
a6xx_gmu_clocks_probe(struct a6xx_gmu * gmu)1674 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu)
1675 {
1676 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks);
1677
1678 if (ret < 1)
1679 return ret;
1680
1681 gmu->nr_clocks = ret;
1682
1683 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks,
1684 gmu->nr_clocks, "gmu");
1685
1686 gmu->hub_clk = msm_clk_bulk_get_clock(gmu->clocks,
1687 gmu->nr_clocks, "hub");
1688
1689 return 0;
1690 }
1691
a6xx_gmu_get_mmio(struct platform_device * pdev,const char * name)1692 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
1693 const char *name)
1694 {
1695 void __iomem *ret;
1696 struct resource *res = platform_get_resource_byname(pdev,
1697 IORESOURCE_MEM, name);
1698
1699 if (!res) {
1700 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1701 return ERR_PTR(-EINVAL);
1702 }
1703
1704 ret = ioremap(res->start, resource_size(res));
1705 if (!ret) {
1706 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
1707 return ERR_PTR(-EINVAL);
1708 }
1709
1710 return ret;
1711 }
1712
a6xx_gmu_get_irq(struct a6xx_gmu * gmu,struct platform_device * pdev,const char * name,irq_handler_t handler)1713 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
1714 const char *name, irq_handler_t handler)
1715 {
1716 int irq, ret;
1717
1718 irq = platform_get_irq_byname(pdev, name);
1719
1720 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, name, gmu);
1721 if (ret) {
1722 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n",
1723 name, ret);
1724 return ret;
1725 }
1726
1727 return irq;
1728 }
1729
a6xx_gmu_remove(struct a6xx_gpu * a6xx_gpu)1730 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
1731 {
1732 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1733 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1734 struct platform_device *pdev = to_platform_device(gmu->dev);
1735
1736 mutex_lock(&gmu->lock);
1737 if (!gmu->initialized) {
1738 mutex_unlock(&gmu->lock);
1739 return;
1740 }
1741
1742 gmu->initialized = false;
1743
1744 mutex_unlock(&gmu->lock);
1745
1746 pm_runtime_force_suspend(gmu->dev);
1747
1748 /*
1749 * Since cxpd is a virt device, the devlink with gmu-dev will be removed
1750 * automatically when we do detach
1751 */
1752 dev_pm_domain_detach(gmu->cxpd, false);
1753
1754 if (!IS_ERR_OR_NULL(gmu->gxpd)) {
1755 pm_runtime_disable(gmu->gxpd);
1756 dev_pm_domain_detach(gmu->gxpd, false);
1757 }
1758
1759 if (!IS_ERR_OR_NULL(gmu->qmp))
1760 qmp_put(gmu->qmp);
1761
1762 iounmap(gmu->mmio);
1763 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1764 iounmap(gmu->rscc);
1765 gmu->mmio = NULL;
1766 gmu->rscc = NULL;
1767
1768 if (!adreno_has_gmu_wrapper(adreno_gpu)) {
1769 a6xx_gmu_memory_free(gmu);
1770
1771 free_irq(gmu->gmu_irq, gmu);
1772 free_irq(gmu->hfi_irq, gmu);
1773 }
1774
1775 /* Drop reference taken in of_find_device_by_node */
1776 put_device(gmu->dev);
1777 }
1778
cxpd_notifier_cb(struct notifier_block * nb,unsigned long action,void * data)1779 static int cxpd_notifier_cb(struct notifier_block *nb,
1780 unsigned long action, void *data)
1781 {
1782 struct a6xx_gmu *gmu = container_of(nb, struct a6xx_gmu, pd_nb);
1783
1784 if (action == GENPD_NOTIFY_OFF)
1785 complete_all(&gmu->pd_gate);
1786
1787 return 0;
1788 }
1789
a6xx_gmu_wrapper_init(struct a6xx_gpu * a6xx_gpu,struct device_node * node)1790 int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
1791 {
1792 struct platform_device *pdev = of_find_device_by_node(node);
1793 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1794 int ret;
1795
1796 if (!pdev)
1797 return -ENODEV;
1798
1799 gmu->dev = &pdev->dev;
1800
1801 ret = of_dma_configure(gmu->dev, node, true);
1802 if (ret)
1803 return ret;
1804
1805 pm_runtime_enable(gmu->dev);
1806
1807 /* Mark legacy for manual SPTPRAC control */
1808 gmu->legacy = true;
1809
1810 /* Map the GMU registers */
1811 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1812 if (IS_ERR(gmu->mmio)) {
1813 ret = PTR_ERR(gmu->mmio);
1814 goto err_mmio;
1815 }
1816
1817 gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx");
1818 if (IS_ERR(gmu->cxpd)) {
1819 ret = PTR_ERR(gmu->cxpd);
1820 goto err_mmio;
1821 }
1822
1823 if (!device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME)) {
1824 ret = -ENODEV;
1825 goto detach_cxpd;
1826 }
1827
1828 init_completion(&gmu->pd_gate);
1829 complete_all(&gmu->pd_gate);
1830 gmu->pd_nb.notifier_call = cxpd_notifier_cb;
1831
1832 /* Get a link to the GX power domain to reset the GPU */
1833 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
1834 if (IS_ERR(gmu->gxpd)) {
1835 ret = PTR_ERR(gmu->gxpd);
1836 goto err_mmio;
1837 }
1838
1839 gmu->initialized = true;
1840
1841 return 0;
1842
1843 detach_cxpd:
1844 dev_pm_domain_detach(gmu->cxpd, false);
1845
1846 err_mmio:
1847 iounmap(gmu->mmio);
1848
1849 /* Drop reference taken in of_find_device_by_node */
1850 put_device(gmu->dev);
1851
1852 return ret;
1853 }
1854
a6xx_gmu_init(struct a6xx_gpu * a6xx_gpu,struct device_node * node)1855 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
1856 {
1857 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1858 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1859 struct platform_device *pdev = of_find_device_by_node(node);
1860 struct device_link *link;
1861 int ret;
1862
1863 if (!pdev)
1864 return -ENODEV;
1865
1866 gmu->dev = &pdev->dev;
1867
1868 ret = of_dma_configure(gmu->dev, node, true);
1869 if (ret)
1870 return ret;
1871
1872 /* Fow now, don't do anything fancy until we get our feet under us */
1873 gmu->idle_level = GMU_IDLE_STATE_ACTIVE;
1874
1875 pm_runtime_enable(gmu->dev);
1876
1877 /* Get the list of clocks */
1878 ret = a6xx_gmu_clocks_probe(gmu);
1879 if (ret)
1880 goto err_put_device;
1881
1882 ret = a6xx_gmu_memory_probe(gmu);
1883 if (ret)
1884 goto err_put_device;
1885
1886
1887 /* A660 now requires handling "prealloc requests" in GMU firmware
1888 * For now just hardcode allocations based on the known firmware.
1889 * note: there is no indication that these correspond to "dummy" or
1890 * "debug" regions, but this "guess" allows reusing these BOs which
1891 * are otherwise unused by a660.
1892 */
1893 gmu->dummy.size = SZ_4K;
1894 if (adreno_is_a660_family(adreno_gpu) ||
1895 adreno_is_a7xx(adreno_gpu)) {
1896 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7,
1897 0x60400000, "debug");
1898 if (ret)
1899 goto err_memory;
1900
1901 gmu->dummy.size = SZ_8K;
1902 }
1903
1904 /* Allocate memory for the GMU dummy page */
1905 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size,
1906 0x60000000, "dummy");
1907 if (ret)
1908 goto err_memory;
1909
1910 /* Note that a650 family also includes a660 family: */
1911 if (adreno_is_a650_family(adreno_gpu) ||
1912 adreno_is_a7xx(adreno_gpu)) {
1913 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1914 SZ_16M - SZ_16K, 0x04000, "icache");
1915 if (ret)
1916 goto err_memory;
1917 /*
1918 * NOTE: when porting legacy ("pre-650-family") GPUs you may be tempted to add a condition
1919 * to allocate icache/dcache here, as per downstream code flow, but it may not actually be
1920 * necessary. If you omit this step and you don't get random pagefaults, you are likely
1921 * good to go without this!
1922 */
1923 } else if (adreno_is_a640_family(adreno_gpu)) {
1924 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1925 SZ_256K - SZ_16K, 0x04000, "icache");
1926 if (ret)
1927 goto err_memory;
1928
1929 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache,
1930 SZ_256K - SZ_16K, 0x44000, "dcache");
1931 if (ret)
1932 goto err_memory;
1933 } else if (adreno_is_a630_family(adreno_gpu)) {
1934 /* HFI v1, has sptprac */
1935 gmu->legacy = true;
1936
1937 /* Allocate memory for the GMU debug region */
1938 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0, "debug");
1939 if (ret)
1940 goto err_memory;
1941 }
1942
1943 /* Allocate memory for the GMU log region */
1944 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_16K, 0, "log");
1945 if (ret)
1946 goto err_memory;
1947
1948 /* Allocate memory for for the HFI queues */
1949 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi");
1950 if (ret)
1951 goto err_memory;
1952
1953 /* Map the GMU registers */
1954 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1955 if (IS_ERR(gmu->mmio)) {
1956 ret = PTR_ERR(gmu->mmio);
1957 goto err_memory;
1958 }
1959
1960 if (adreno_is_a650_family(adreno_gpu) ||
1961 adreno_is_a7xx(adreno_gpu)) {
1962 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
1963 if (IS_ERR(gmu->rscc)) {
1964 ret = -ENODEV;
1965 goto err_mmio;
1966 }
1967 } else {
1968 gmu->rscc = gmu->mmio + 0x23000;
1969 }
1970
1971 /* Get the HFI and GMU interrupts */
1972 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq);
1973 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq);
1974
1975 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) {
1976 ret = -ENODEV;
1977 goto err_mmio;
1978 }
1979
1980 gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx");
1981 if (IS_ERR(gmu->cxpd)) {
1982 ret = PTR_ERR(gmu->cxpd);
1983 goto err_mmio;
1984 }
1985
1986 link = device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME);
1987 if (!link) {
1988 ret = -ENODEV;
1989 goto detach_cxpd;
1990 }
1991
1992 gmu->qmp = qmp_get(gmu->dev);
1993 if (IS_ERR(gmu->qmp) && adreno_is_a7xx(adreno_gpu)) {
1994 ret = PTR_ERR(gmu->qmp);
1995 goto remove_device_link;
1996 }
1997
1998 init_completion(&gmu->pd_gate);
1999 complete_all(&gmu->pd_gate);
2000 gmu->pd_nb.notifier_call = cxpd_notifier_cb;
2001
2002 /*
2003 * Get a link to the GX power domain to reset the GPU in case of GMU
2004 * crash
2005 */
2006 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
2007
2008 /* Get the power levels for the GMU and GPU */
2009 a6xx_gmu_pwrlevels_probe(gmu);
2010
2011 /* Set up the HFI queues */
2012 a6xx_hfi_init(gmu);
2013
2014 /* Initialize RPMh */
2015 a6xx_gmu_rpmh_init(gmu);
2016
2017 gmu->initialized = true;
2018
2019 return 0;
2020
2021 remove_device_link:
2022 device_link_del(link);
2023
2024 detach_cxpd:
2025 dev_pm_domain_detach(gmu->cxpd, false);
2026
2027 err_mmio:
2028 iounmap(gmu->mmio);
2029 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
2030 iounmap(gmu->rscc);
2031 free_irq(gmu->gmu_irq, gmu);
2032 free_irq(gmu->hfi_irq, gmu);
2033
2034 err_memory:
2035 a6xx_gmu_memory_free(gmu);
2036 err_put_device:
2037 /* Drop reference taken in of_find_device_by_node */
2038 put_device(gmu->dev);
2039
2040 return ret;
2041 }
2042