1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/power/rk3588-power.h> 11#include <dt-bindings/reset/rockchip,rk3588-cru.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/ata/ahci.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 compatible = "rockchip,rk3588"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 gpio0 = &gpio0; 25 gpio1 = &gpio1; 26 gpio2 = &gpio2; 27 gpio3 = &gpio3; 28 gpio4 = &gpio4; 29 i2c0 = &i2c0; 30 i2c1 = &i2c1; 31 i2c2 = &i2c2; 32 i2c3 = &i2c3; 33 i2c4 = &i2c4; 34 i2c5 = &i2c5; 35 i2c6 = &i2c6; 36 i2c7 = &i2c7; 37 i2c8 = &i2c8; 38 serial0 = &uart0; 39 serial1 = &uart1; 40 serial2 = &uart2; 41 serial3 = &uart3; 42 serial4 = &uart4; 43 serial5 = &uart5; 44 serial6 = &uart6; 45 serial7 = &uart7; 46 serial8 = &uart8; 47 serial9 = &uart9; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi2 = &spi2; 51 spi3 = &spi3; 52 spi4 = &spi4; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu-map { 60 cluster0 { 61 core0 { 62 cpu = <&cpu_l0>; 63 }; 64 core1 { 65 cpu = <&cpu_l1>; 66 }; 67 core2 { 68 cpu = <&cpu_l2>; 69 }; 70 core3 { 71 cpu = <&cpu_l3>; 72 }; 73 }; 74 cluster1 { 75 core0 { 76 cpu = <&cpu_b0>; 77 }; 78 core1 { 79 cpu = <&cpu_b1>; 80 }; 81 }; 82 cluster2 { 83 core0 { 84 cpu = <&cpu_b2>; 85 }; 86 core1 { 87 cpu = <&cpu_b3>; 88 }; 89 }; 90 }; 91 92 cpu_l0: cpu@0 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a55"; 95 reg = <0x0>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <530>; 98 clocks = <&scmi_clk SCMI_CLK_CPUL>; 99 cpu-idle-states = <&CPU_SLEEP>; 100 i-cache-size = <32768>; 101 i-cache-line-size = <64>; 102 i-cache-sets = <128>; 103 d-cache-size = <32768>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 next-level-cache = <&l2_cache_l0>; 107 dynamic-power-coefficient = <228>; 108 #cooling-cells = <2>; 109 }; 110 111 cpu_l1: cpu@100 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a55"; 114 reg = <0x100>; 115 enable-method = "psci"; 116 capacity-dmips-mhz = <530>; 117 clocks = <&scmi_clk SCMI_CLK_CPUL>; 118 cpu-idle-states = <&CPU_SLEEP>; 119 i-cache-size = <32768>; 120 i-cache-line-size = <64>; 121 i-cache-sets = <128>; 122 d-cache-size = <32768>; 123 d-cache-line-size = <64>; 124 d-cache-sets = <128>; 125 next-level-cache = <&l2_cache_l1>; 126 dynamic-power-coefficient = <228>; 127 #cooling-cells = <2>; 128 }; 129 130 cpu_l2: cpu@200 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a55"; 133 reg = <0x200>; 134 enable-method = "psci"; 135 capacity-dmips-mhz = <530>; 136 clocks = <&scmi_clk SCMI_CLK_CPUL>; 137 cpu-idle-states = <&CPU_SLEEP>; 138 i-cache-size = <32768>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <128>; 141 d-cache-size = <32768>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <128>; 144 next-level-cache = <&l2_cache_l2>; 145 dynamic-power-coefficient = <228>; 146 #cooling-cells = <2>; 147 }; 148 149 cpu_l3: cpu@300 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a55"; 152 reg = <0x300>; 153 enable-method = "psci"; 154 capacity-dmips-mhz = <530>; 155 clocks = <&scmi_clk SCMI_CLK_CPUL>; 156 cpu-idle-states = <&CPU_SLEEP>; 157 i-cache-size = <32768>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <128>; 160 d-cache-size = <32768>; 161 d-cache-line-size = <64>; 162 d-cache-sets = <128>; 163 next-level-cache = <&l2_cache_l3>; 164 dynamic-power-coefficient = <228>; 165 #cooling-cells = <2>; 166 }; 167 168 cpu_b0: cpu@400 { 169 device_type = "cpu"; 170 compatible = "arm,cortex-a76"; 171 reg = <0x400>; 172 enable-method = "psci"; 173 capacity-dmips-mhz = <1024>; 174 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 175 cpu-idle-states = <&CPU_SLEEP>; 176 i-cache-size = <65536>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <65536>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&l2_cache_b0>; 183 dynamic-power-coefficient = <416>; 184 #cooling-cells = <2>; 185 }; 186 187 cpu_b1: cpu@500 { 188 device_type = "cpu"; 189 compatible = "arm,cortex-a76"; 190 reg = <0x500>; 191 enable-method = "psci"; 192 capacity-dmips-mhz = <1024>; 193 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 194 cpu-idle-states = <&CPU_SLEEP>; 195 i-cache-size = <65536>; 196 i-cache-line-size = <64>; 197 i-cache-sets = <256>; 198 d-cache-size = <65536>; 199 d-cache-line-size = <64>; 200 d-cache-sets = <256>; 201 next-level-cache = <&l2_cache_b1>; 202 dynamic-power-coefficient = <416>; 203 #cooling-cells = <2>; 204 }; 205 206 cpu_b2: cpu@600 { 207 device_type = "cpu"; 208 compatible = "arm,cortex-a76"; 209 reg = <0x600>; 210 enable-method = "psci"; 211 capacity-dmips-mhz = <1024>; 212 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 213 cpu-idle-states = <&CPU_SLEEP>; 214 i-cache-size = <65536>; 215 i-cache-line-size = <64>; 216 i-cache-sets = <256>; 217 d-cache-size = <65536>; 218 d-cache-line-size = <64>; 219 d-cache-sets = <256>; 220 next-level-cache = <&l2_cache_b2>; 221 dynamic-power-coefficient = <416>; 222 #cooling-cells = <2>; 223 }; 224 225 cpu_b3: cpu@700 { 226 device_type = "cpu"; 227 compatible = "arm,cortex-a76"; 228 reg = <0x700>; 229 enable-method = "psci"; 230 capacity-dmips-mhz = <1024>; 231 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 232 cpu-idle-states = <&CPU_SLEEP>; 233 i-cache-size = <65536>; 234 i-cache-line-size = <64>; 235 i-cache-sets = <256>; 236 d-cache-size = <65536>; 237 d-cache-line-size = <64>; 238 d-cache-sets = <256>; 239 next-level-cache = <&l2_cache_b3>; 240 dynamic-power-coefficient = <416>; 241 #cooling-cells = <2>; 242 }; 243 244 idle-states { 245 entry-method = "psci"; 246 CPU_SLEEP: cpu-sleep { 247 compatible = "arm,idle-state"; 248 local-timer-stop; 249 arm,psci-suspend-param = <0x0010000>; 250 entry-latency-us = <100>; 251 exit-latency-us = <120>; 252 min-residency-us = <1000>; 253 }; 254 }; 255 256 l2_cache_l0: l2-cache-l0 { 257 compatible = "cache"; 258 cache-size = <131072>; 259 cache-line-size = <64>; 260 cache-sets = <512>; 261 cache-level = <2>; 262 cache-unified; 263 next-level-cache = <&l3_cache>; 264 }; 265 266 l2_cache_l1: l2-cache-l1 { 267 compatible = "cache"; 268 cache-size = <131072>; 269 cache-line-size = <64>; 270 cache-sets = <512>; 271 cache-level = <2>; 272 cache-unified; 273 next-level-cache = <&l3_cache>; 274 }; 275 276 l2_cache_l2: l2-cache-l2 { 277 compatible = "cache"; 278 cache-size = <131072>; 279 cache-line-size = <64>; 280 cache-sets = <512>; 281 cache-level = <2>; 282 cache-unified; 283 next-level-cache = <&l3_cache>; 284 }; 285 286 l2_cache_l3: l2-cache-l3 { 287 compatible = "cache"; 288 cache-size = <131072>; 289 cache-line-size = <64>; 290 cache-sets = <512>; 291 cache-level = <2>; 292 cache-unified; 293 next-level-cache = <&l3_cache>; 294 }; 295 296 l2_cache_b0: l2-cache-b0 { 297 compatible = "cache"; 298 cache-size = <524288>; 299 cache-line-size = <64>; 300 cache-sets = <1024>; 301 cache-level = <2>; 302 cache-unified; 303 next-level-cache = <&l3_cache>; 304 }; 305 306 l2_cache_b1: l2-cache-b1 { 307 compatible = "cache"; 308 cache-size = <524288>; 309 cache-line-size = <64>; 310 cache-sets = <1024>; 311 cache-level = <2>; 312 cache-unified; 313 next-level-cache = <&l3_cache>; 314 }; 315 316 l2_cache_b2: l2-cache-b2 { 317 compatible = "cache"; 318 cache-size = <524288>; 319 cache-line-size = <64>; 320 cache-sets = <1024>; 321 cache-level = <2>; 322 cache-unified; 323 next-level-cache = <&l3_cache>; 324 }; 325 326 l2_cache_b3: l2-cache-b3 { 327 compatible = "cache"; 328 cache-size = <524288>; 329 cache-line-size = <64>; 330 cache-sets = <1024>; 331 cache-level = <2>; 332 cache-unified; 333 next-level-cache = <&l3_cache>; 334 }; 335 }; 336 337 /* 338 * The L3 cache belongs to the DynamIQ Shared Unit (DSU), 339 * so it's represented here, outside the "cpus" node 340 */ 341 l3_cache: l3-cache { 342 compatible = "cache"; 343 cache-size = <3145728>; 344 cache-line-size = <64>; 345 cache-sets = <4096>; 346 cache-level = <3>; 347 cache-unified; 348 }; 349 350 display_subsystem: display-subsystem { 351 compatible = "rockchip,display-subsystem"; 352 ports = <&vop_out>; 353 }; 354 355 firmware { 356 scmi: scmi { 357 compatible = "arm,scmi-smc"; 358 arm,smc-id = <0x82000010>; 359 shmem = <&scmi_shmem>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 363 scmi_clk: protocol@14 { 364 reg = <0x14>; 365 #clock-cells = <1>; 366 }; 367 368 scmi_reset: protocol@16 { 369 reg = <0x16>; 370 #reset-cells = <1>; 371 }; 372 }; 373 }; 374 375 hdmi0_sound: hdmi0-sound { 376 compatible = "simple-audio-card"; 377 simple-audio-card,format = "i2s"; 378 simple-audio-card,mclk-fs = <128>; 379 simple-audio-card,name = "hdmi0"; 380 status = "disabled"; 381 382 simple-audio-card,codec { 383 sound-dai = <&hdmi0>; 384 }; 385 386 simple-audio-card,cpu { 387 sound-dai = <&i2s5_8ch>; 388 }; 389 }; 390 391 pmu-a55 { 392 compatible = "arm,cortex-a55-pmu"; 393 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; 394 }; 395 396 pmu-a76 { 397 compatible = "arm,cortex-a76-pmu"; 398 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; 399 }; 400 401 psci { 402 compatible = "arm,psci-1.0"; 403 method = "smc"; 404 }; 405 406 spll: clock-0 { 407 compatible = "fixed-clock"; 408 clock-frequency = <702000000>; 409 clock-output-names = "spll"; 410 #clock-cells = <0>; 411 }; 412 413 timer { 414 compatible = "arm,armv8-timer"; 415 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 416 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 417 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 418 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, 419 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 420 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 421 }; 422 423 xin24m: clock-1 { 424 compatible = "fixed-clock"; 425 clock-frequency = <24000000>; 426 clock-output-names = "xin24m"; 427 #clock-cells = <0>; 428 }; 429 430 xin32k: clock-2 { 431 compatible = "fixed-clock"; 432 clock-frequency = <32768>; 433 clock-output-names = "xin32k"; 434 #clock-cells = <0>; 435 }; 436 437 reserved-memory { 438 #address-cells = <2>; 439 #size-cells = <2>; 440 ranges; 441 442 scmi_shmem: shmem@10f000 { 443 compatible = "arm,scmi-shmem"; 444 reg = <0x0 0x0010f000 0x0 0x100>; 445 no-map; 446 }; 447 }; 448 449 gpu: gpu@fb000000 { 450 compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; 451 reg = <0x0 0xfb000000 0x0 0x200000>; 452 #cooling-cells = <2>; 453 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 454 assigned-clock-rates = <200000000>; 455 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, 456 <&cru CLK_GPU_STACKS>; 457 clock-names = "core", "coregroup", "stacks"; 458 dynamic-power-coefficient = <2982>; 459 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, 460 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, 461 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>; 462 interrupt-names = "job", "mmu", "gpu"; 463 power-domains = <&power RK3588_PD_GPU>; 464 status = "disabled"; 465 }; 466 467 usb_host0_xhci: usb@fc000000 { 468 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 469 reg = <0x0 0xfc000000 0x0 0x400000>; 470 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 471 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, 472 <&cru ACLK_USB3OTG0>; 473 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 474 dr_mode = "otg"; 475 phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; 476 phy-names = "usb2-phy", "usb3-phy"; 477 phy_type = "utmi_wide"; 478 power-domains = <&power RK3588_PD_USB>; 479 resets = <&cru SRST_A_USB3OTG0>; 480 snps,dis_enblslpm_quirk; 481 snps,dis-u1-entry-quirk; 482 snps,dis-u2-entry-quirk; 483 snps,dis-u2-freeclk-exists-quirk; 484 snps,dis-del-phy-power-chg-quirk; 485 snps,dis-tx-ipgap-linecheck-quirk; 486 status = "disabled"; 487 }; 488 489 usb_host0_ehci: usb@fc800000 { 490 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 491 reg = <0x0 0xfc800000 0x0 0x40000>; 492 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; 493 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 494 phys = <&u2phy2_host>; 495 phy-names = "usb"; 496 power-domains = <&power RK3588_PD_USB>; 497 status = "disabled"; 498 }; 499 500 usb_host0_ohci: usb@fc840000 { 501 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 502 reg = <0x0 0xfc840000 0x0 0x40000>; 503 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; 504 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 505 phys = <&u2phy2_host>; 506 phy-names = "usb"; 507 power-domains = <&power RK3588_PD_USB>; 508 status = "disabled"; 509 }; 510 511 usb_host1_ehci: usb@fc880000 { 512 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 513 reg = <0x0 0xfc880000 0x0 0x40000>; 514 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; 515 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 516 phys = <&u2phy3_host>; 517 phy-names = "usb"; 518 power-domains = <&power RK3588_PD_USB>; 519 status = "disabled"; 520 }; 521 522 usb_host1_ohci: usb@fc8c0000 { 523 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 524 reg = <0x0 0xfc8c0000 0x0 0x40000>; 525 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; 526 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 527 phys = <&u2phy3_host>; 528 phy-names = "usb"; 529 power-domains = <&power RK3588_PD_USB>; 530 status = "disabled"; 531 }; 532 533 usb_host2_xhci: usb@fcd00000 { 534 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 535 reg = <0x0 0xfcd00000 0x0 0x400000>; 536 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; 537 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, 538 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, 539 <&cru CLK_PIPEPHY2_PIPE_U3_G>; 540 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; 541 dr_mode = "host"; 542 phys = <&combphy2_psu PHY_TYPE_USB3>; 543 phy-names = "usb3-phy"; 544 phy_type = "utmi_wide"; 545 resets = <&cru SRST_A_USB3OTG2>; 546 snps,dis_enblslpm_quirk; 547 snps,dis-u2-freeclk-exists-quirk; 548 snps,dis-del-phy-power-chg-quirk; 549 snps,dis-tx-ipgap-linecheck-quirk; 550 snps,dis_rxdet_inp3_quirk; 551 status = "disabled"; 552 }; 553 554 mmu600_pcie: iommu@fc900000 { 555 compatible = "arm,smmu-v3"; 556 reg = <0x0 0xfc900000 0x0 0x200000>; 557 interrupts = <GIC_SPI 369 IRQ_TYPE_EDGE_RISING 0>, 558 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING 0>, 559 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING 0>, 560 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>; 561 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 562 #iommu-cells = <1>; 563 }; 564 565 mmu600_php: iommu@fcb00000 { 566 compatible = "arm,smmu-v3"; 567 reg = <0x0 0xfcb00000 0x0 0x200000>; 568 interrupts = <GIC_SPI 381 IRQ_TYPE_EDGE_RISING 0>, 569 <GIC_SPI 383 IRQ_TYPE_EDGE_RISING 0>, 570 <GIC_SPI 386 IRQ_TYPE_EDGE_RISING 0>, 571 <GIC_SPI 379 IRQ_TYPE_EDGE_RISING 0>; 572 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 573 #iommu-cells = <1>; 574 status = "disabled"; 575 }; 576 577 pmu1grf: syscon@fd58a000 { 578 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; 579 reg = <0x0 0xfd58a000 0x0 0x10000>; 580 }; 581 582 sys_grf: syscon@fd58c000 { 583 compatible = "rockchip,rk3588-sys-grf", "syscon"; 584 reg = <0x0 0xfd58c000 0x0 0x1000>; 585 }; 586 587 mipidcphy0_grf: syscon@fd5e8000 { 588 compatible = "rockchip,rk3588-dcphy-grf", "syscon"; 589 reg = <0x0 0xfd5e8000 0x0 0x4000>; 590 }; 591 592 mipidcphy1_grf: syscon@fd5ec000 { 593 compatible = "rockchip,rk3588-dcphy-grf", "syscon"; 594 reg = <0x0 0xfd5ec000 0x0 0x4000>; 595 }; 596 597 vop_grf: syscon@fd5a4000 { 598 compatible = "rockchip,rk3588-vop-grf", "syscon"; 599 reg = <0x0 0xfd5a4000 0x0 0x2000>; 600 }; 601 602 vo0_grf: syscon@fd5a6000 { 603 compatible = "rockchip,rk3588-vo0-grf", "syscon"; 604 reg = <0x0 0xfd5a6000 0x0 0x2000>; 605 clocks = <&cru PCLK_VO0GRF>; 606 }; 607 608 vo1_grf: syscon@fd5a8000 { 609 compatible = "rockchip,rk3588-vo1-grf", "syscon"; 610 reg = <0x0 0xfd5a8000 0x0 0x4000>; 611 clocks = <&cru PCLK_VO1GRF>; 612 }; 613 614 usb_grf: syscon@fd5ac000 { 615 compatible = "rockchip,rk3588-usb-grf", "syscon"; 616 reg = <0x0 0xfd5ac000 0x0 0x4000>; 617 }; 618 619 php_grf: syscon@fd5b0000 { 620 compatible = "rockchip,rk3588-php-grf", "syscon"; 621 reg = <0x0 0xfd5b0000 0x0 0x1000>; 622 }; 623 624 pipe_phy0_grf: syscon@fd5bc000 { 625 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 626 reg = <0x0 0xfd5bc000 0x0 0x100>; 627 }; 628 629 pipe_phy2_grf: syscon@fd5c4000 { 630 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 631 reg = <0x0 0xfd5c4000 0x0 0x100>; 632 }; 633 634 usbdpphy0_grf: syscon@fd5c8000 { 635 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 636 reg = <0x0 0xfd5c8000 0x0 0x4000>; 637 }; 638 639 usb2phy0_grf: syscon@fd5d0000 { 640 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 641 reg = <0x0 0xfd5d0000 0x0 0x4000>; 642 #address-cells = <1>; 643 #size-cells = <1>; 644 645 u2phy0: usb2phy@0 { 646 compatible = "rockchip,rk3588-usb2phy"; 647 reg = <0x0 0x10>; 648 #clock-cells = <0>; 649 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 650 clock-names = "phyclk"; 651 clock-output-names = "usb480m_phy0"; 652 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; 653 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; 654 reset-names = "phy", "apb"; 655 status = "disabled"; 656 657 u2phy0_otg: otg-port { 658 #phy-cells = <0>; 659 status = "disabled"; 660 }; 661 }; 662 }; 663 664 usb2phy2_grf: syscon@fd5d8000 { 665 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 666 reg = <0x0 0xfd5d8000 0x0 0x4000>; 667 #address-cells = <1>; 668 #size-cells = <1>; 669 670 u2phy2: usb2phy@8000 { 671 compatible = "rockchip,rk3588-usb2phy"; 672 reg = <0x8000 0x10>; 673 #clock-cells = <0>; 674 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 675 clock-names = "phyclk"; 676 clock-output-names = "usb480m_phy2"; 677 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 678 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 679 reset-names = "phy", "apb"; 680 status = "disabled"; 681 682 u2phy2_host: host-port { 683 #phy-cells = <0>; 684 status = "disabled"; 685 }; 686 }; 687 }; 688 689 usb2phy3_grf: syscon@fd5dc000 { 690 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 691 reg = <0x0 0xfd5dc000 0x0 0x4000>; 692 #address-cells = <1>; 693 #size-cells = <1>; 694 695 u2phy3: usb2phy@c000 { 696 compatible = "rockchip,rk3588-usb2phy"; 697 reg = <0xc000 0x10>; 698 #clock-cells = <0>; 699 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 700 clock-names = "phyclk"; 701 clock-output-names = "usb480m_phy3"; 702 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 703 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 704 reset-names = "phy", "apb"; 705 status = "disabled"; 706 707 u2phy3_host: host-port { 708 #phy-cells = <0>; 709 status = "disabled"; 710 }; 711 }; 712 }; 713 714 hdptxphy0_grf: syscon@fd5e0000 { 715 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 716 reg = <0x0 0xfd5e0000 0x0 0x100>; 717 }; 718 719 ioc: syscon@fd5f0000 { 720 compatible = "rockchip,rk3588-ioc", "syscon"; 721 reg = <0x0 0xfd5f0000 0x0 0x10000>; 722 }; 723 724 system_sram1: sram@fd600000 { 725 compatible = "mmio-sram"; 726 reg = <0x0 0xfd600000 0x0 0x100000>; 727 ranges = <0x0 0x0 0xfd600000 0x100000>; 728 #address-cells = <1>; 729 #size-cells = <1>; 730 }; 731 732 cru: clock-controller@fd7c0000 { 733 compatible = "rockchip,rk3588-cru"; 734 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 735 assigned-clocks = 736 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 737 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 738 <&cru ACLK_CENTER_ROOT>, 739 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 740 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 741 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 742 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, 743 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 744 <&cru CLK_GPU>; 745 assigned-clock-rates = 746 <1100000000>, <786432000>, 747 <850000000>, <1188000000>, 748 <702000000>, 749 <400000000>, <500000000>, 750 <800000000>, <100000000>, 751 <400000000>, <100000000>, 752 <200000000>, <500000000>, 753 <375000000>, <150000000>, 754 <200000000>; 755 rockchip,grf = <&php_grf>; 756 #clock-cells = <1>; 757 #reset-cells = <1>; 758 }; 759 760 i2c0: i2c@fd880000 { 761 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 762 reg = <0x0 0xfd880000 0x0 0x1000>; 763 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; 764 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 765 clock-names = "i2c", "pclk"; 766 pinctrl-0 = <&i2c0m0_xfer>; 767 pinctrl-names = "default"; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 status = "disabled"; 771 }; 772 773 uart0: serial@fd890000 { 774 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 775 reg = <0x0 0xfd890000 0x0 0x100>; 776 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 777 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 778 clock-names = "baudclk", "apb_pclk"; 779 dmas = <&dmac0 6>, <&dmac0 7>; 780 dma-names = "tx", "rx"; 781 pinctrl-0 = <&uart0m1_xfer>; 782 pinctrl-names = "default"; 783 reg-shift = <2>; 784 reg-io-width = <4>; 785 status = "disabled"; 786 }; 787 788 pwm0: pwm@fd8b0000 { 789 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 790 reg = <0x0 0xfd8b0000 0x0 0x10>; 791 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 792 clock-names = "pwm", "pclk"; 793 pinctrl-0 = <&pwm0m0_pins>; 794 pinctrl-names = "default"; 795 #pwm-cells = <3>; 796 status = "disabled"; 797 }; 798 799 pwm1: pwm@fd8b0010 { 800 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 801 reg = <0x0 0xfd8b0010 0x0 0x10>; 802 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 803 clock-names = "pwm", "pclk"; 804 pinctrl-0 = <&pwm1m0_pins>; 805 pinctrl-names = "default"; 806 #pwm-cells = <3>; 807 status = "disabled"; 808 }; 809 810 pwm2: pwm@fd8b0020 { 811 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 812 reg = <0x0 0xfd8b0020 0x0 0x10>; 813 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 814 clock-names = "pwm", "pclk"; 815 pinctrl-0 = <&pwm2m0_pins>; 816 pinctrl-names = "default"; 817 #pwm-cells = <3>; 818 status = "disabled"; 819 }; 820 821 pwm3: pwm@fd8b0030 { 822 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 823 reg = <0x0 0xfd8b0030 0x0 0x10>; 824 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 825 clock-names = "pwm", "pclk"; 826 pinctrl-0 = <&pwm3m0_pins>; 827 pinctrl-names = "default"; 828 #pwm-cells = <3>; 829 status = "disabled"; 830 }; 831 832 pmu: power-management@fd8d8000 { 833 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 834 reg = <0x0 0xfd8d8000 0x0 0x400>; 835 836 power: power-controller { 837 compatible = "rockchip,rk3588-power-controller"; 838 #address-cells = <1>; 839 #power-domain-cells = <1>; 840 #size-cells = <0>; 841 status = "okay"; 842 843 /* These power domains are grouped by VD_NPU */ 844 power-domain@RK3588_PD_NPU { 845 reg = <RK3588_PD_NPU>; 846 #power-domain-cells = <0>; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 850 power-domain@RK3588_PD_NPUTOP { 851 reg = <RK3588_PD_NPUTOP>; 852 clocks = <&cru HCLK_NPU_ROOT>, 853 <&cru PCLK_NPU_ROOT>, 854 <&cru CLK_NPU_DSU0>, 855 <&cru HCLK_NPU_CM0_ROOT>; 856 pm_qos = <&qos_npu0_mwr>, 857 <&qos_npu0_mro>, 858 <&qos_mcu_npu>; 859 #power-domain-cells = <0>; 860 #address-cells = <1>; 861 #size-cells = <0>; 862 863 power-domain@RK3588_PD_NPU1 { 864 reg = <RK3588_PD_NPU1>; 865 clocks = <&cru HCLK_NPU_ROOT>, 866 <&cru PCLK_NPU_ROOT>, 867 <&cru CLK_NPU_DSU0>; 868 pm_qos = <&qos_npu1>; 869 #power-domain-cells = <0>; 870 }; 871 power-domain@RK3588_PD_NPU2 { 872 reg = <RK3588_PD_NPU2>; 873 clocks = <&cru HCLK_NPU_ROOT>, 874 <&cru PCLK_NPU_ROOT>, 875 <&cru CLK_NPU_DSU0>; 876 pm_qos = <&qos_npu2>; 877 #power-domain-cells = <0>; 878 }; 879 }; 880 }; 881 /* These power domains are grouped by VD_GPU */ 882 pd_gpu: power-domain@RK3588_PD_GPU { 883 reg = <RK3588_PD_GPU>; 884 clocks = <&cru CLK_GPU>, 885 <&cru CLK_GPU_COREGROUP>, 886 <&cru CLK_GPU_STACKS>; 887 pm_qos = <&qos_gpu_m0>, 888 <&qos_gpu_m1>, 889 <&qos_gpu_m2>, 890 <&qos_gpu_m3>; 891 #power-domain-cells = <0>; 892 }; 893 /* These power domains are grouped by VD_VCODEC */ 894 power-domain@RK3588_PD_VCODEC { 895 reg = <RK3588_PD_VCODEC>; 896 #address-cells = <1>; 897 #size-cells = <0>; 898 #power-domain-cells = <0>; 899 900 power-domain@RK3588_PD_RKVDEC0 { 901 reg = <RK3588_PD_RKVDEC0>; 902 clocks = <&cru HCLK_RKVDEC0>, 903 <&cru HCLK_VDPU_ROOT>, 904 <&cru ACLK_VDPU_ROOT>, 905 <&cru ACLK_RKVDEC0>, 906 <&cru ACLK_RKVDEC_CCU>; 907 pm_qos = <&qos_rkvdec0>; 908 #power-domain-cells = <0>; 909 }; 910 power-domain@RK3588_PD_RKVDEC1 { 911 reg = <RK3588_PD_RKVDEC1>; 912 clocks = <&cru HCLK_RKVDEC1>, 913 <&cru HCLK_VDPU_ROOT>, 914 <&cru ACLK_VDPU_ROOT>, 915 <&cru ACLK_RKVDEC1>; 916 pm_qos = <&qos_rkvdec1>; 917 #power-domain-cells = <0>; 918 }; 919 power-domain@RK3588_PD_VENC0 { 920 reg = <RK3588_PD_VENC0>; 921 clocks = <&cru HCLK_RKVENC0>, 922 <&cru ACLK_RKVENC0>; 923 pm_qos = <&qos_rkvenc0_m0ro>, 924 <&qos_rkvenc0_m1ro>, 925 <&qos_rkvenc0_m2wo>; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 #power-domain-cells = <0>; 929 930 power-domain@RK3588_PD_VENC1 { 931 reg = <RK3588_PD_VENC1>; 932 clocks = <&cru HCLK_RKVENC1>, 933 <&cru HCLK_RKVENC0>, 934 <&cru ACLK_RKVENC0>, 935 <&cru ACLK_RKVENC1>; 936 pm_qos = <&qos_rkvenc1_m0ro>, 937 <&qos_rkvenc1_m1ro>, 938 <&qos_rkvenc1_m2wo>; 939 #power-domain-cells = <0>; 940 }; 941 }; 942 }; 943 /* These power domains are grouped by VD_LOGIC */ 944 power-domain@RK3588_PD_VDPU { 945 reg = <RK3588_PD_VDPU>; 946 clocks = <&cru HCLK_VDPU_ROOT>, 947 <&cru ACLK_VDPU_LOW_ROOT>, 948 <&cru ACLK_VDPU_ROOT>, 949 <&cru ACLK_JPEG_DECODER_ROOT>, 950 <&cru ACLK_IEP2P0>, 951 <&cru HCLK_IEP2P0>, 952 <&cru ACLK_JPEG_ENCODER0>, 953 <&cru HCLK_JPEG_ENCODER0>, 954 <&cru ACLK_JPEG_ENCODER1>, 955 <&cru HCLK_JPEG_ENCODER1>, 956 <&cru ACLK_JPEG_ENCODER2>, 957 <&cru HCLK_JPEG_ENCODER2>, 958 <&cru ACLK_JPEG_ENCODER3>, 959 <&cru HCLK_JPEG_ENCODER3>, 960 <&cru ACLK_JPEG_DECODER>, 961 <&cru HCLK_JPEG_DECODER>, 962 <&cru ACLK_RGA2>, 963 <&cru HCLK_RGA2>; 964 pm_qos = <&qos_iep>, 965 <&qos_jpeg_dec>, 966 <&qos_jpeg_enc0>, 967 <&qos_jpeg_enc1>, 968 <&qos_jpeg_enc2>, 969 <&qos_jpeg_enc3>, 970 <&qos_rga2_mro>, 971 <&qos_rga2_mwo>; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 #power-domain-cells = <0>; 975 976 977 power-domain@RK3588_PD_AV1 { 978 reg = <RK3588_PD_AV1>; 979 clocks = <&cru PCLK_AV1>, 980 <&cru ACLK_AV1>, 981 <&cru HCLK_VDPU_ROOT>; 982 pm_qos = <&qos_av1>; 983 #power-domain-cells = <0>; 984 }; 985 power-domain@RK3588_PD_RKVDEC0 { 986 reg = <RK3588_PD_RKVDEC0>; 987 clocks = <&cru HCLK_RKVDEC0>, 988 <&cru HCLK_VDPU_ROOT>, 989 <&cru ACLK_VDPU_ROOT>, 990 <&cru ACLK_RKVDEC0>; 991 pm_qos = <&qos_rkvdec0>; 992 #power-domain-cells = <0>; 993 }; 994 power-domain@RK3588_PD_RKVDEC1 { 995 reg = <RK3588_PD_RKVDEC1>; 996 clocks = <&cru HCLK_RKVDEC1>, 997 <&cru HCLK_VDPU_ROOT>, 998 <&cru ACLK_VDPU_ROOT>; 999 pm_qos = <&qos_rkvdec1>; 1000 #power-domain-cells = <0>; 1001 }; 1002 power-domain@RK3588_PD_RGA30 { 1003 reg = <RK3588_PD_RGA30>; 1004 clocks = <&cru ACLK_RGA3_0>, 1005 <&cru HCLK_RGA3_0>; 1006 pm_qos = <&qos_rga3_0>; 1007 #power-domain-cells = <0>; 1008 }; 1009 }; 1010 power-domain@RK3588_PD_VOP { 1011 reg = <RK3588_PD_VOP>; 1012 clocks = <&cru PCLK_VOP_ROOT>, 1013 <&cru HCLK_VOP_ROOT>, 1014 <&cru ACLK_VOP>; 1015 pm_qos = <&qos_vop_m0>, 1016 <&qos_vop_m1>; 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 #power-domain-cells = <0>; 1020 1021 power-domain@RK3588_PD_VO0 { 1022 reg = <RK3588_PD_VO0>; 1023 clocks = <&cru PCLK_VO0_ROOT>, 1024 <&cru PCLK_VO0_S_ROOT>, 1025 <&cru HCLK_VO0_S_ROOT>, 1026 <&cru ACLK_VO0_ROOT>, 1027 <&cru HCLK_HDCP0>, 1028 <&cru ACLK_HDCP0>, 1029 <&cru HCLK_VOP_ROOT>; 1030 pm_qos = <&qos_hdcp0>; 1031 #power-domain-cells = <0>; 1032 }; 1033 }; 1034 power-domain@RK3588_PD_VO1 { 1035 reg = <RK3588_PD_VO1>; 1036 clocks = <&cru PCLK_VO1_ROOT>, 1037 <&cru PCLK_VO1_S_ROOT>, 1038 <&cru HCLK_VO1_S_ROOT>, 1039 <&cru HCLK_HDCP1>, 1040 <&cru ACLK_HDCP1>, 1041 <&cru ACLK_HDMIRX_ROOT>, 1042 <&cru HCLK_VO1USB_TOP_ROOT>; 1043 pm_qos = <&qos_hdcp1>, 1044 <&qos_hdmirx>; 1045 #power-domain-cells = <0>; 1046 }; 1047 power-domain@RK3588_PD_VI { 1048 reg = <RK3588_PD_VI>; 1049 clocks = <&cru HCLK_VI_ROOT>, 1050 <&cru PCLK_VI_ROOT>, 1051 <&cru HCLK_ISP0>, 1052 <&cru ACLK_ISP0>, 1053 <&cru HCLK_VICAP>, 1054 <&cru ACLK_VICAP>; 1055 pm_qos = <&qos_isp0_mro>, 1056 <&qos_isp0_mwo>, 1057 <&qos_vicap_m0>, 1058 <&qos_vicap_m1>; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 #power-domain-cells = <0>; 1062 1063 power-domain@RK3588_PD_ISP1 { 1064 reg = <RK3588_PD_ISP1>; 1065 clocks = <&cru HCLK_ISP1>, 1066 <&cru ACLK_ISP1>, 1067 <&cru HCLK_VI_ROOT>, 1068 <&cru PCLK_VI_ROOT>; 1069 pm_qos = <&qos_isp1_mwo>, 1070 <&qos_isp1_mro>; 1071 #power-domain-cells = <0>; 1072 }; 1073 power-domain@RK3588_PD_FEC { 1074 reg = <RK3588_PD_FEC>; 1075 clocks = <&cru HCLK_FISHEYE0>, 1076 <&cru ACLK_FISHEYE0>, 1077 <&cru HCLK_FISHEYE1>, 1078 <&cru ACLK_FISHEYE1>, 1079 <&cru PCLK_VI_ROOT>; 1080 pm_qos = <&qos_fisheye0>, 1081 <&qos_fisheye1>; 1082 #power-domain-cells = <0>; 1083 }; 1084 }; 1085 power-domain@RK3588_PD_RGA31 { 1086 reg = <RK3588_PD_RGA31>; 1087 clocks = <&cru HCLK_RGA3_1>, 1088 <&cru ACLK_RGA3_1>; 1089 pm_qos = <&qos_rga3_1>; 1090 #power-domain-cells = <0>; 1091 }; 1092 power-domain@RK3588_PD_USB { 1093 reg = <RK3588_PD_USB>; 1094 clocks = <&cru PCLK_PHP_ROOT>, 1095 <&cru ACLK_USB_ROOT>, 1096 <&cru ACLK_USB>, 1097 <&cru HCLK_USB_ROOT>, 1098 <&cru HCLK_HOST0>, 1099 <&cru HCLK_HOST_ARB0>, 1100 <&cru HCLK_HOST1>, 1101 <&cru HCLK_HOST_ARB1>; 1102 pm_qos = <&qos_usb3_0>, 1103 <&qos_usb3_1>, 1104 <&qos_usb2host_0>, 1105 <&qos_usb2host_1>; 1106 #power-domain-cells = <0>; 1107 }; 1108 power-domain@RK3588_PD_GMAC { 1109 reg = <RK3588_PD_GMAC>; 1110 clocks = <&cru PCLK_PHP_ROOT>, 1111 <&cru ACLK_PCIE_ROOT>, 1112 <&cru ACLK_PHP_ROOT>; 1113 #power-domain-cells = <0>; 1114 }; 1115 power-domain@RK3588_PD_PCIE { 1116 reg = <RK3588_PD_PCIE>; 1117 clocks = <&cru PCLK_PHP_ROOT>, 1118 <&cru ACLK_PCIE_ROOT>, 1119 <&cru ACLK_PHP_ROOT>; 1120 #power-domain-cells = <0>; 1121 }; 1122 power-domain@RK3588_PD_SDIO { 1123 reg = <RK3588_PD_SDIO>; 1124 clocks = <&cru HCLK_SDIO>, 1125 <&cru HCLK_NVM_ROOT>; 1126 pm_qos = <&qos_sdio>; 1127 #power-domain-cells = <0>; 1128 }; 1129 power-domain@RK3588_PD_AUDIO { 1130 reg = <RK3588_PD_AUDIO>; 1131 clocks = <&cru HCLK_AUDIO_ROOT>, 1132 <&cru PCLK_AUDIO_ROOT>; 1133 #power-domain-cells = <0>; 1134 }; 1135 power-domain@RK3588_PD_SDMMC { 1136 reg = <RK3588_PD_SDMMC>; 1137 pm_qos = <&qos_sdmmc>; 1138 #power-domain-cells = <0>; 1139 }; 1140 }; 1141 }; 1142 1143 vpu121: video-codec@fdb50000 { 1144 compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu"; 1145 reg = <0x0 0xfdb50000 0x0 0x800>; 1146 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1147 interrupt-names = "vdpu"; 1148 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1149 clock-names = "aclk", "hclk"; 1150 iommus = <&vpu121_mmu>; 1151 power-domains = <&power RK3588_PD_VDPU>; 1152 }; 1153 1154 vpu121_mmu: iommu@fdb50800 { 1155 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1156 reg = <0x0 0xfdb50800 0x0 0x40>; 1157 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1158 clock-names = "aclk", "iface"; 1159 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1160 power-domains = <&power RK3588_PD_VDPU>; 1161 #iommu-cells = <0>; 1162 }; 1163 1164 rga: rga@fdb80000 { 1165 compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga"; 1166 reg = <0x0 0xfdb80000 0x0 0x180>; 1167 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1168 clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>; 1169 clock-names = "aclk", "hclk", "sclk"; 1170 resets = <&cru SRST_RGA2_CORE>, <&cru SRST_A_RGA2>, <&cru SRST_H_RGA2>; 1171 reset-names = "core", "axi", "ahb"; 1172 power-domains = <&power RK3588_PD_VDPU>; 1173 }; 1174 1175 vepu121_0: video-codec@fdba0000 { 1176 compatible = "rockchip,rk3588-vepu121"; 1177 reg = <0x0 0xfdba0000 0x0 0x800>; 1178 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>; 1179 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 1180 clock-names = "aclk", "hclk"; 1181 iommus = <&vepu121_0_mmu>; 1182 power-domains = <&power RK3588_PD_VDPU>; 1183 }; 1184 1185 vepu121_0_mmu: iommu@fdba0800 { 1186 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1187 reg = <0x0 0xfdba0800 0x0 0x40>; 1188 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 1189 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 1190 clock-names = "aclk", "iface"; 1191 power-domains = <&power RK3588_PD_VDPU>; 1192 #iommu-cells = <0>; 1193 }; 1194 1195 vepu121_1: video-codec@fdba4000 { 1196 compatible = "rockchip,rk3588-vepu121"; 1197 reg = <0x0 0xfdba4000 0x0 0x800>; 1198 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>; 1199 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 1200 clock-names = "aclk", "hclk"; 1201 iommus = <&vepu121_1_mmu>; 1202 power-domains = <&power RK3588_PD_VDPU>; 1203 }; 1204 1205 vepu121_1_mmu: iommu@fdba4800 { 1206 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1207 reg = <0x0 0xfdba4800 0x0 0x40>; 1208 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>; 1209 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 1210 clock-names = "aclk", "iface"; 1211 power-domains = <&power RK3588_PD_VDPU>; 1212 #iommu-cells = <0>; 1213 }; 1214 1215 vepu121_2: video-codec@fdba8000 { 1216 compatible = "rockchip,rk3588-vepu121"; 1217 reg = <0x0 0xfdba8000 0x0 0x800>; 1218 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>; 1219 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 1220 clock-names = "aclk", "hclk"; 1221 iommus = <&vepu121_2_mmu>; 1222 power-domains = <&power RK3588_PD_VDPU>; 1223 }; 1224 1225 vepu121_2_mmu: iommu@fdba8800 { 1226 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1227 reg = <0x0 0xfdba8800 0x0 0x40>; 1228 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>; 1229 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 1230 clock-names = "aclk", "iface"; 1231 power-domains = <&power RK3588_PD_VDPU>; 1232 #iommu-cells = <0>; 1233 }; 1234 1235 vepu121_3: video-codec@fdbac000 { 1236 compatible = "rockchip,rk3588-vepu121"; 1237 reg = <0x0 0xfdbac000 0x0 0x800>; 1238 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; 1239 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 1240 clock-names = "aclk", "hclk"; 1241 iommus = <&vepu121_3_mmu>; 1242 power-domains = <&power RK3588_PD_VDPU>; 1243 }; 1244 1245 vepu121_3_mmu: iommu@fdbac800 { 1246 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1247 reg = <0x0 0xfdbac800 0x0 0x40>; 1248 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>; 1249 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 1250 clock-names = "aclk", "iface"; 1251 power-domains = <&power RK3588_PD_VDPU>; 1252 #iommu-cells = <0>; 1253 }; 1254 1255 av1d: video-codec@fdc70000 { 1256 compatible = "rockchip,rk3588-av1-vpu"; 1257 reg = <0x0 0xfdc70000 0x0 0x800>; 1258 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 1259 interrupt-names = "vdpu"; 1260 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1261 assigned-clock-rates = <400000000>, <400000000>; 1262 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1263 clock-names = "aclk", "hclk"; 1264 power-domains = <&power RK3588_PD_AV1>; 1265 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; 1266 }; 1267 1268 vop: vop@fdd90000 { 1269 compatible = "rockchip,rk3588-vop"; 1270 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; 1271 reg-names = "vop", "gamma-lut"; 1272 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1273 clocks = <&cru ACLK_VOP>, 1274 <&cru HCLK_VOP>, 1275 <&cru DCLK_VOP0>, 1276 <&cru DCLK_VOP1>, 1277 <&cru DCLK_VOP2>, 1278 <&cru DCLK_VOP3>, 1279 <&cru PCLK_VOP_ROOT>, 1280 <&hdptxphy0>; 1281 clock-names = "aclk", 1282 "hclk", 1283 "dclk_vp0", 1284 "dclk_vp1", 1285 "dclk_vp2", 1286 "dclk_vp3", 1287 "pclk_vop", 1288 "pll_hdmiphy0"; 1289 iommus = <&vop_mmu>; 1290 power-domains = <&power RK3588_PD_VOP>; 1291 rockchip,grf = <&sys_grf>; 1292 rockchip,vop-grf = <&vop_grf>; 1293 rockchip,vo1-grf = <&vo1_grf>; 1294 rockchip,pmu = <&pmu>; 1295 status = "disabled"; 1296 1297 vop_out: ports { 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 1301 vp0: port@0 { 1302 #address-cells = <1>; 1303 #size-cells = <0>; 1304 reg = <0>; 1305 }; 1306 1307 vp1: port@1 { 1308 #address-cells = <1>; 1309 #size-cells = <0>; 1310 reg = <1>; 1311 }; 1312 1313 vp2: port@2 { 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 reg = <2>; 1317 }; 1318 1319 vp3: port@3 { 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 reg = <3>; 1323 }; 1324 }; 1325 }; 1326 1327 vop_mmu: iommu@fdd97e00 { 1328 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1329 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 1330 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1331 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1332 clock-names = "aclk", "iface"; 1333 #iommu-cells = <0>; 1334 power-domains = <&power RK3588_PD_VOP>; 1335 status = "disabled"; 1336 }; 1337 1338 spdif_tx2: spdif-tx@fddb0000 { 1339 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1340 reg = <0x0 0xfddb0000 0x0 0x1000>; 1341 assigned-clock-parents = <&cru PLL_AUPLL>; 1342 assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>; 1343 clock-names = "mclk", "hclk"; 1344 clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>; 1345 dma-names = "tx"; 1346 dmas = <&dmac1 6>; 1347 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1348 power-domains = <&power RK3588_PD_VO0>; 1349 #sound-dai-cells = <0>; 1350 status = "disabled"; 1351 }; 1352 1353 i2s4_8ch: i2s@fddc0000 { 1354 compatible = "rockchip,rk3588-i2s-tdm"; 1355 reg = <0x0 0xfddc0000 0x0 0x1000>; 1356 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; 1357 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 1358 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1359 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 1360 assigned-clock-parents = <&cru PLL_AUPLL>; 1361 dmas = <&dmac2 0>; 1362 dma-names = "tx"; 1363 power-domains = <&power RK3588_PD_VO0>; 1364 resets = <&cru SRST_M_I2S4_8CH_TX>; 1365 reset-names = "tx-m"; 1366 #sound-dai-cells = <0>; 1367 status = "disabled"; 1368 }; 1369 1370 spdif_tx3: spdif-tx@fdde0000 { 1371 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1372 reg = <0x0 0xfdde0000 0x0 0x1000>; 1373 assigned-clock-parents = <&cru PLL_AUPLL>; 1374 assigned-clocks = <&cru CLK_SPDIF3_SRC>; 1375 clock-names = "mclk", "hclk"; 1376 clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; 1377 dma-names = "tx"; 1378 dmas = <&dmac1 7>; 1379 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1380 power-domains = <&power RK3588_PD_VO1>; 1381 #sound-dai-cells = <0>; 1382 status = "disabled"; 1383 }; 1384 1385 i2s5_8ch: i2s@fddf0000 { 1386 compatible = "rockchip,rk3588-i2s-tdm"; 1387 reg = <0x0 0xfddf0000 0x0 0x1000>; 1388 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; 1389 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 1390 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1391 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 1392 assigned-clock-parents = <&cru PLL_AUPLL>; 1393 dmas = <&dmac2 2>; 1394 dma-names = "tx"; 1395 power-domains = <&power RK3588_PD_VO1>; 1396 resets = <&cru SRST_M_I2S5_8CH_TX>; 1397 reset-names = "tx-m"; 1398 #sound-dai-cells = <0>; 1399 status = "disabled"; 1400 }; 1401 1402 i2s9_8ch: i2s@fddfc000 { 1403 compatible = "rockchip,rk3588-i2s-tdm"; 1404 reg = <0x0 0xfddfc000 0x0 0x1000>; 1405 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; 1406 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 1407 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1408 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 1409 assigned-clock-parents = <&cru PLL_AUPLL>; 1410 dmas = <&dmac2 23>; 1411 dma-names = "rx"; 1412 power-domains = <&power RK3588_PD_VO1>; 1413 resets = <&cru SRST_M_I2S9_8CH_RX>; 1414 reset-names = "rx-m"; 1415 #sound-dai-cells = <0>; 1416 status = "disabled"; 1417 }; 1418 1419 dsi0: dsi@fde20000 { 1420 compatible = "rockchip,rk3588-mipi-dsi2"; 1421 reg = <0x0 0xfde20000 0x0 0x10000>; 1422 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>; 1423 clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; 1424 clock-names = "pclk", "sys"; 1425 resets = <&cru SRST_P_DSIHOST0>; 1426 reset-names = "apb"; 1427 power-domains = <&power RK3588_PD_VOP>; 1428 phys = <&mipidcphy0 PHY_TYPE_DPHY>; 1429 phy-names = "dcphy"; 1430 rockchip,grf = <&vop_grf>; 1431 status = "disabled"; 1432 1433 ports { 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 1437 dsi0_in: port@0 { 1438 reg = <0>; 1439 }; 1440 1441 dsi0_out: port@1 { 1442 reg = <1>; 1443 }; 1444 }; 1445 }; 1446 1447 dsi1: dsi@fde30000 { 1448 compatible = "rockchip,rk3588-mipi-dsi2"; 1449 reg = <0x0 0xfde30000 0x0 0x10000>; 1450 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>; 1451 clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>; 1452 clock-names = "pclk", "sys"; 1453 resets = <&cru SRST_P_DSIHOST1>; 1454 reset-names = "apb"; 1455 power-domains = <&power RK3588_PD_VOP>; 1456 phys = <&mipidcphy1 PHY_TYPE_DPHY>; 1457 phy-names = "dcphy"; 1458 rockchip,grf = <&vop_grf>; 1459 status = "disabled"; 1460 1461 ports { 1462 #address-cells = <1>; 1463 #size-cells = <0>; 1464 1465 dsi1_in: port@0 { 1466 reg = <0>; 1467 }; 1468 1469 dsi1_out: port@1 { 1470 reg = <1>; 1471 }; 1472 }; 1473 }; 1474 1475 hdmi0: hdmi@fde80000 { 1476 compatible = "rockchip,rk3588-dw-hdmi-qp"; 1477 reg = <0x0 0xfde80000 0x0 0x20000>; 1478 clocks = <&cru PCLK_HDMITX0>, 1479 <&cru CLK_HDMITX0_EARC>, 1480 <&cru CLK_HDMITX0_REF>, 1481 <&cru MCLK_I2S5_8CH_TX>, 1482 <&cru CLK_HDMIHDP0>, 1483 <&cru HCLK_VO1>; 1484 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; 1485 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>, 1486 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>, 1487 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>, 1488 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>, 1489 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>; 1490 interrupt-names = "avp", "cec", "earc", "main", "hpd"; 1491 phys = <&hdptxphy0>; 1492 pinctrl-names = "default"; 1493 pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd 1494 &hdmim0_tx0_scl &hdmim0_tx0_sda>; 1495 power-domains = <&power RK3588_PD_VO1>; 1496 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; 1497 reset-names = "ref", "hdp"; 1498 rockchip,grf = <&sys_grf>; 1499 rockchip,vo-grf = <&vo1_grf>; 1500 #sound-dai-cells = <0>; 1501 status = "disabled"; 1502 1503 ports { 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 1507 hdmi0_in: port@0 { 1508 reg = <0>; 1509 }; 1510 1511 hdmi0_out: port@1 { 1512 reg = <1>; 1513 }; 1514 }; 1515 }; 1516 1517 edp0: edp@fdec0000 { 1518 compatible = "rockchip,rk3588-edp"; 1519 reg = <0x0 0xfdec0000 0x0 0x1000>; 1520 clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>; 1521 clock-names = "dp", "pclk"; 1522 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 1523 phys = <&hdptxphy0>; 1524 phy-names = "dp"; 1525 power-domains = <&power RK3588_PD_VO1>; 1526 resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; 1527 reset-names = "dp", "apb"; 1528 rockchip,grf = <&vo1_grf>; 1529 status = "disabled"; 1530 1531 ports { 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 1535 edp0_in: port@0 { 1536 reg = <0>; 1537 }; 1538 1539 edp0_out: port@1 { 1540 reg = <1>; 1541 }; 1542 }; 1543 }; 1544 1545 qos_gpu_m0: qos@fdf35000 { 1546 compatible = "rockchip,rk3588-qos", "syscon"; 1547 reg = <0x0 0xfdf35000 0x0 0x20>; 1548 }; 1549 1550 qos_gpu_m1: qos@fdf35200 { 1551 compatible = "rockchip,rk3588-qos", "syscon"; 1552 reg = <0x0 0xfdf35200 0x0 0x20>; 1553 }; 1554 1555 qos_gpu_m2: qos@fdf35400 { 1556 compatible = "rockchip,rk3588-qos", "syscon"; 1557 reg = <0x0 0xfdf35400 0x0 0x20>; 1558 }; 1559 1560 qos_gpu_m3: qos@fdf35600 { 1561 compatible = "rockchip,rk3588-qos", "syscon"; 1562 reg = <0x0 0xfdf35600 0x0 0x20>; 1563 }; 1564 1565 qos_rga3_1: qos@fdf36000 { 1566 compatible = "rockchip,rk3588-qos", "syscon"; 1567 reg = <0x0 0xfdf36000 0x0 0x20>; 1568 }; 1569 1570 qos_sdio: qos@fdf39000 { 1571 compatible = "rockchip,rk3588-qos", "syscon"; 1572 reg = <0x0 0xfdf39000 0x0 0x20>; 1573 }; 1574 1575 qos_sdmmc: qos@fdf3d800 { 1576 compatible = "rockchip,rk3588-qos", "syscon"; 1577 reg = <0x0 0xfdf3d800 0x0 0x20>; 1578 }; 1579 1580 qos_usb3_1: qos@fdf3e000 { 1581 compatible = "rockchip,rk3588-qos", "syscon"; 1582 reg = <0x0 0xfdf3e000 0x0 0x20>; 1583 }; 1584 1585 qos_usb3_0: qos@fdf3e200 { 1586 compatible = "rockchip,rk3588-qos", "syscon"; 1587 reg = <0x0 0xfdf3e200 0x0 0x20>; 1588 }; 1589 1590 qos_usb2host_0: qos@fdf3e400 { 1591 compatible = "rockchip,rk3588-qos", "syscon"; 1592 reg = <0x0 0xfdf3e400 0x0 0x20>; 1593 }; 1594 1595 qos_usb2host_1: qos@fdf3e600 { 1596 compatible = "rockchip,rk3588-qos", "syscon"; 1597 reg = <0x0 0xfdf3e600 0x0 0x20>; 1598 }; 1599 1600 qos_fisheye0: qos@fdf40000 { 1601 compatible = "rockchip,rk3588-qos", "syscon"; 1602 reg = <0x0 0xfdf40000 0x0 0x20>; 1603 }; 1604 1605 qos_fisheye1: qos@fdf40200 { 1606 compatible = "rockchip,rk3588-qos", "syscon"; 1607 reg = <0x0 0xfdf40200 0x0 0x20>; 1608 }; 1609 1610 qos_isp0_mro: qos@fdf40400 { 1611 compatible = "rockchip,rk3588-qos", "syscon"; 1612 reg = <0x0 0xfdf40400 0x0 0x20>; 1613 }; 1614 1615 qos_isp0_mwo: qos@fdf40500 { 1616 compatible = "rockchip,rk3588-qos", "syscon"; 1617 reg = <0x0 0xfdf40500 0x0 0x20>; 1618 }; 1619 1620 qos_vicap_m0: qos@fdf40600 { 1621 compatible = "rockchip,rk3588-qos", "syscon"; 1622 reg = <0x0 0xfdf40600 0x0 0x20>; 1623 }; 1624 1625 qos_vicap_m1: qos@fdf40800 { 1626 compatible = "rockchip,rk3588-qos", "syscon"; 1627 reg = <0x0 0xfdf40800 0x0 0x20>; 1628 }; 1629 1630 qos_isp1_mwo: qos@fdf41000 { 1631 compatible = "rockchip,rk3588-qos", "syscon"; 1632 reg = <0x0 0xfdf41000 0x0 0x20>; 1633 }; 1634 1635 qos_isp1_mro: qos@fdf41100 { 1636 compatible = "rockchip,rk3588-qos", "syscon"; 1637 reg = <0x0 0xfdf41100 0x0 0x20>; 1638 }; 1639 1640 qos_rkvenc0_m0ro: qos@fdf60000 { 1641 compatible = "rockchip,rk3588-qos", "syscon"; 1642 reg = <0x0 0xfdf60000 0x0 0x20>; 1643 }; 1644 1645 qos_rkvenc0_m1ro: qos@fdf60200 { 1646 compatible = "rockchip,rk3588-qos", "syscon"; 1647 reg = <0x0 0xfdf60200 0x0 0x20>; 1648 }; 1649 1650 qos_rkvenc0_m2wo: qos@fdf60400 { 1651 compatible = "rockchip,rk3588-qos", "syscon"; 1652 reg = <0x0 0xfdf60400 0x0 0x20>; 1653 }; 1654 1655 qos_rkvenc1_m0ro: qos@fdf61000 { 1656 compatible = "rockchip,rk3588-qos", "syscon"; 1657 reg = <0x0 0xfdf61000 0x0 0x20>; 1658 }; 1659 1660 qos_rkvenc1_m1ro: qos@fdf61200 { 1661 compatible = "rockchip,rk3588-qos", "syscon"; 1662 reg = <0x0 0xfdf61200 0x0 0x20>; 1663 }; 1664 1665 qos_rkvenc1_m2wo: qos@fdf61400 { 1666 compatible = "rockchip,rk3588-qos", "syscon"; 1667 reg = <0x0 0xfdf61400 0x0 0x20>; 1668 }; 1669 1670 qos_rkvdec0: qos@fdf62000 { 1671 compatible = "rockchip,rk3588-qos", "syscon"; 1672 reg = <0x0 0xfdf62000 0x0 0x20>; 1673 }; 1674 1675 qos_rkvdec1: qos@fdf63000 { 1676 compatible = "rockchip,rk3588-qos", "syscon"; 1677 reg = <0x0 0xfdf63000 0x0 0x20>; 1678 }; 1679 1680 qos_av1: qos@fdf64000 { 1681 compatible = "rockchip,rk3588-qos", "syscon"; 1682 reg = <0x0 0xfdf64000 0x0 0x20>; 1683 }; 1684 1685 qos_iep: qos@fdf66000 { 1686 compatible = "rockchip,rk3588-qos", "syscon"; 1687 reg = <0x0 0xfdf66000 0x0 0x20>; 1688 }; 1689 1690 qos_jpeg_dec: qos@fdf66200 { 1691 compatible = "rockchip,rk3588-qos", "syscon"; 1692 reg = <0x0 0xfdf66200 0x0 0x20>; 1693 }; 1694 1695 qos_jpeg_enc0: qos@fdf66400 { 1696 compatible = "rockchip,rk3588-qos", "syscon"; 1697 reg = <0x0 0xfdf66400 0x0 0x20>; 1698 }; 1699 1700 qos_jpeg_enc1: qos@fdf66600 { 1701 compatible = "rockchip,rk3588-qos", "syscon"; 1702 reg = <0x0 0xfdf66600 0x0 0x20>; 1703 }; 1704 1705 qos_jpeg_enc2: qos@fdf66800 { 1706 compatible = "rockchip,rk3588-qos", "syscon"; 1707 reg = <0x0 0xfdf66800 0x0 0x20>; 1708 }; 1709 1710 qos_jpeg_enc3: qos@fdf66a00 { 1711 compatible = "rockchip,rk3588-qos", "syscon"; 1712 reg = <0x0 0xfdf66a00 0x0 0x20>; 1713 }; 1714 1715 qos_rga2_mro: qos@fdf66c00 { 1716 compatible = "rockchip,rk3588-qos", "syscon"; 1717 reg = <0x0 0xfdf66c00 0x0 0x20>; 1718 }; 1719 1720 qos_rga2_mwo: qos@fdf66e00 { 1721 compatible = "rockchip,rk3588-qos", "syscon"; 1722 reg = <0x0 0xfdf66e00 0x0 0x20>; 1723 }; 1724 1725 qos_rga3_0: qos@fdf67000 { 1726 compatible = "rockchip,rk3588-qos", "syscon"; 1727 reg = <0x0 0xfdf67000 0x0 0x20>; 1728 }; 1729 1730 qos_vdpu: qos@fdf67200 { 1731 compatible = "rockchip,rk3588-qos", "syscon"; 1732 reg = <0x0 0xfdf67200 0x0 0x20>; 1733 }; 1734 1735 qos_npu1: qos@fdf70000 { 1736 compatible = "rockchip,rk3588-qos", "syscon"; 1737 reg = <0x0 0xfdf70000 0x0 0x20>; 1738 }; 1739 1740 qos_npu2: qos@fdf71000 { 1741 compatible = "rockchip,rk3588-qos", "syscon"; 1742 reg = <0x0 0xfdf71000 0x0 0x20>; 1743 }; 1744 1745 qos_npu0_mwr: qos@fdf72000 { 1746 compatible = "rockchip,rk3588-qos", "syscon"; 1747 reg = <0x0 0xfdf72000 0x0 0x20>; 1748 }; 1749 1750 qos_npu0_mro: qos@fdf72200 { 1751 compatible = "rockchip,rk3588-qos", "syscon"; 1752 reg = <0x0 0xfdf72200 0x0 0x20>; 1753 }; 1754 1755 qos_mcu_npu: qos@fdf72400 { 1756 compatible = "rockchip,rk3588-qos", "syscon"; 1757 reg = <0x0 0xfdf72400 0x0 0x20>; 1758 }; 1759 1760 qos_hdcp0: qos@fdf80000 { 1761 compatible = "rockchip,rk3588-qos", "syscon"; 1762 reg = <0x0 0xfdf80000 0x0 0x20>; 1763 }; 1764 1765 qos_hdcp1: qos@fdf81000 { 1766 compatible = "rockchip,rk3588-qos", "syscon"; 1767 reg = <0x0 0xfdf81000 0x0 0x20>; 1768 }; 1769 1770 qos_hdmirx: qos@fdf81200 { 1771 compatible = "rockchip,rk3588-qos", "syscon"; 1772 reg = <0x0 0xfdf81200 0x0 0x20>; 1773 }; 1774 1775 qos_vop_m0: qos@fdf82000 { 1776 compatible = "rockchip,rk3588-qos", "syscon"; 1777 reg = <0x0 0xfdf82000 0x0 0x20>; 1778 }; 1779 1780 qos_vop_m1: qos@fdf82200 { 1781 compatible = "rockchip,rk3588-qos", "syscon"; 1782 reg = <0x0 0xfdf82200 0x0 0x20>; 1783 }; 1784 1785 dfi: dfi@fe060000 { 1786 reg = <0x00 0xfe060000 0x00 0x10000>; 1787 compatible = "rockchip,rk3588-dfi"; 1788 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, 1789 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, 1790 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, 1791 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1792 rockchip,pmu = <&pmu1grf>; 1793 }; 1794 1795 pcie2x1l1: pcie@fe180000 { 1796 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1797 bus-range = <0x30 0x3f>; 1798 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 1799 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 1800 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; 1801 clock-names = "aclk_mst", "aclk_slv", 1802 "aclk_dbi", "pclk", 1803 "aux", "pipe"; 1804 device_type = "pci"; 1805 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, 1806 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, 1807 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, 1808 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, 1809 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; 1810 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1811 #interrupt-cells = <1>; 1812 interrupt-map-mask = <0 0 0 7>; 1813 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 1814 <0 0 0 2 &pcie2x1l1_intc 1>, 1815 <0 0 0 3 &pcie2x1l1_intc 2>, 1816 <0 0 0 4 &pcie2x1l1_intc 3>; 1817 linux,pci-domain = <3>; 1818 max-link-speed = <2>; 1819 msi-map = <0x3000 &its0 0x3000 0x1000>; 1820 iommu-map = <0x3000 &mmu600_pcie 0x3000 0x1000>; 1821 num-lanes = <1>; 1822 phys = <&combphy2_psu PHY_TYPE_PCIE>; 1823 phy-names = "pcie-phy"; 1824 power-domains = <&power RK3588_PD_PCIE>; 1825 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, 1826 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, 1827 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; 1828 reg = <0xa 0x40c00000 0x0 0x00400000>, 1829 <0x0 0xfe180000 0x0 0x00010000>, 1830 <0x0 0xf3000000 0x0 0x00100000>; 1831 reg-names = "dbi", "apb", "config"; 1832 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; 1833 reset-names = "pwr", "pipe"; 1834 #address-cells = <3>; 1835 #size-cells = <2>; 1836 status = "disabled"; 1837 1838 pcie2x1l1_intc: legacy-interrupt-controller { 1839 interrupt-controller; 1840 #address-cells = <0>; 1841 #interrupt-cells = <1>; 1842 interrupt-parent = <&gic>; 1843 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; 1844 }; 1845 }; 1846 1847 pcie2x1l2: pcie@fe190000 { 1848 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1849 bus-range = <0x40 0x4f>; 1850 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 1851 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 1852 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; 1853 clock-names = "aclk_mst", "aclk_slv", 1854 "aclk_dbi", "pclk", 1855 "aux", "pipe"; 1856 device_type = "pci"; 1857 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, 1858 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, 1859 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, 1860 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, 1861 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; 1862 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1863 #interrupt-cells = <1>; 1864 interrupt-map-mask = <0 0 0 7>; 1865 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 1866 <0 0 0 2 &pcie2x1l2_intc 1>, 1867 <0 0 0 3 &pcie2x1l2_intc 2>, 1868 <0 0 0 4 &pcie2x1l2_intc 3>; 1869 linux,pci-domain = <4>; 1870 max-link-speed = <2>; 1871 msi-map = <0x4000 &its0 0x4000 0x1000>; 1872 iommu-map = <0x4000 &mmu600_pcie 0x4000 0x1000>; 1873 num-lanes = <1>; 1874 phys = <&combphy0_ps PHY_TYPE_PCIE>; 1875 phy-names = "pcie-phy"; 1876 power-domains = <&power RK3588_PD_PCIE>; 1877 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 1878 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, 1879 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; 1880 reg = <0xa 0x41000000 0x0 0x00400000>, 1881 <0x0 0xfe190000 0x0 0x00010000>, 1882 <0x0 0xf4000000 0x0 0x00100000>; 1883 reg-names = "dbi", "apb", "config"; 1884 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; 1885 reset-names = "pwr", "pipe"; 1886 #address-cells = <3>; 1887 #size-cells = <2>; 1888 status = "disabled"; 1889 1890 pcie2x1l2_intc: legacy-interrupt-controller { 1891 interrupt-controller; 1892 #address-cells = <0>; 1893 #interrupt-cells = <1>; 1894 interrupt-parent = <&gic>; 1895 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; 1896 }; 1897 }; 1898 1899 gmac1: ethernet@fe1c0000 { 1900 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1901 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1902 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, 1903 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 1904 interrupt-names = "macirq", "eth_wake_irq"; 1905 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 1906 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1907 <&cru CLK_GMAC1_PTP_REF>; 1908 clock-names = "stmmaceth", "clk_mac_ref", 1909 "pclk_mac", "aclk_mac", 1910 "ptp_ref"; 1911 power-domains = <&power RK3588_PD_GMAC>; 1912 resets = <&cru SRST_A_GMAC1>; 1913 reset-names = "stmmaceth"; 1914 rockchip,grf = <&sys_grf>; 1915 rockchip,php-grf = <&php_grf>; 1916 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1917 snps,mixed-burst; 1918 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1919 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1920 snps,tso; 1921 status = "disabled"; 1922 1923 mdio1: mdio { 1924 compatible = "snps,dwmac-mdio"; 1925 #address-cells = <0x1>; 1926 #size-cells = <0x0>; 1927 }; 1928 1929 gmac1_stmmac_axi_setup: stmmac-axi-config { 1930 snps,blen = <0 0 0 0 16 8 4>; 1931 snps,wr_osr_lmt = <4>; 1932 snps,rd_osr_lmt = <8>; 1933 }; 1934 1935 gmac1_mtl_rx_setup: rx-queues-config { 1936 snps,rx-queues-to-use = <2>; 1937 queue0 {}; 1938 queue1 {}; 1939 }; 1940 1941 gmac1_mtl_tx_setup: tx-queues-config { 1942 snps,tx-queues-to-use = <2>; 1943 queue0 {}; 1944 queue1 {}; 1945 }; 1946 }; 1947 1948 sata0: sata@fe210000 { 1949 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1950 reg = <0 0xfe210000 0 0x1000>; 1951 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; 1952 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1953 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, 1954 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; 1955 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1956 ports-implemented = <0x1>; 1957 #address-cells = <1>; 1958 #size-cells = <0>; 1959 status = "disabled"; 1960 1961 sata-port@0 { 1962 reg = <0>; 1963 hba-port-cap = <HBA_PORT_FBSCP>; 1964 phys = <&combphy0_ps PHY_TYPE_SATA>; 1965 phy-names = "sata-phy"; 1966 snps,rx-ts-max = <32>; 1967 snps,tx-ts-max = <32>; 1968 }; 1969 }; 1970 1971 sata2: sata@fe230000 { 1972 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1973 reg = <0 0xfe230000 0 0x1000>; 1974 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; 1975 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 1976 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, 1977 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; 1978 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1979 ports-implemented = <0x1>; 1980 #address-cells = <1>; 1981 #size-cells = <0>; 1982 status = "disabled"; 1983 1984 sata-port@0 { 1985 reg = <0>; 1986 hba-port-cap = <HBA_PORT_FBSCP>; 1987 phys = <&combphy2_psu PHY_TYPE_SATA>; 1988 phy-names = "sata-phy"; 1989 snps,rx-ts-max = <32>; 1990 snps,tx-ts-max = <32>; 1991 }; 1992 }; 1993 1994 sfc: spi@fe2b0000 { 1995 compatible = "rockchip,sfc"; 1996 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1997 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; 1998 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1999 clock-names = "clk_sfc", "hclk_sfc"; 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 status = "disabled"; 2003 }; 2004 2005 sdmmc: mmc@fe2c0000 { 2006 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 2007 reg = <0x0 0xfe2c0000 0x0 0x4000>; 2008 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 2009 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 2010 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 2011 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2012 fifo-depth = <0x100>; 2013 max-frequency = <200000000>; 2014 pinctrl-names = "default"; 2015 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 2016 power-domains = <&power RK3588_PD_SDMMC>; 2017 status = "disabled"; 2018 }; 2019 2020 sdio: mmc@fe2d0000 { 2021 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 2022 reg = <0x00 0xfe2d0000 0x00 0x4000>; 2023 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; 2024 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 2025 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 2026 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2027 fifo-depth = <0x100>; 2028 max-frequency = <200000000>; 2029 pinctrl-names = "default"; 2030 pinctrl-0 = <&sdiom1_pins>; 2031 power-domains = <&power RK3588_PD_SDIO>; 2032 status = "disabled"; 2033 }; 2034 2035 sdhci: mmc@fe2e0000 { 2036 compatible = "rockchip,rk3588-dwcmshc"; 2037 reg = <0x0 0xfe2e0000 0x0 0x10000>; 2038 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 2039 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 2040 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 2041 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 2042 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 2043 <&cru TMCLK_EMMC>; 2044 clock-names = "core", "bus", "axi", "block", "timer"; 2045 max-frequency = <200000000>; 2046 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 2047 <&emmc_cmd>, <&emmc_data_strobe>; 2048 pinctrl-names = "default"; 2049 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 2050 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 2051 <&cru SRST_T_EMMC>; 2052 reset-names = "core", "bus", "axi", "block", "timer"; 2053 status = "disabled"; 2054 }; 2055 2056 rng@fe378000 { 2057 compatible = "rockchip,rk3588-rng"; 2058 reg = <0x0 0xfe378000 0x0 0x200>; 2059 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>; 2060 clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; 2061 resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>; 2062 }; 2063 2064 i2s0_8ch: i2s@fe470000 { 2065 compatible = "rockchip,rk3588-i2s-tdm"; 2066 reg = <0x0 0xfe470000 0x0 0x1000>; 2067 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; 2068 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 2069 clock-names = "mclk_tx", "mclk_rx", "hclk"; 2070 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 2071 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 2072 dmas = <&dmac0 0>, <&dmac0 1>; 2073 dma-names = "tx", "rx"; 2074 power-domains = <&power RK3588_PD_AUDIO>; 2075 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 2076 reset-names = "tx-m", "rx-m"; 2077 rockchip,trcm-sync-tx-only; 2078 pinctrl-names = "default"; 2079 pinctrl-0 = <&i2s0_lrck 2080 &i2s0_sclk 2081 &i2s0_sdi0 2082 &i2s0_sdi1 2083 &i2s0_sdi2 2084 &i2s0_sdi3 2085 &i2s0_sdo0 2086 &i2s0_sdo1 2087 &i2s0_sdo2 2088 &i2s0_sdo3>; 2089 #sound-dai-cells = <0>; 2090 status = "disabled"; 2091 }; 2092 2093 i2s1_8ch: i2s@fe480000 { 2094 compatible = "rockchip,rk3588-i2s-tdm"; 2095 reg = <0x0 0xfe480000 0x0 0x1000>; 2096 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; 2097 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 2098 clock-names = "mclk_tx", "mclk_rx", "hclk"; 2099 dmas = <&dmac0 2>, <&dmac0 3>; 2100 dma-names = "tx", "rx"; 2101 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 2102 reset-names = "tx-m", "rx-m"; 2103 rockchip,trcm-sync-tx-only; 2104 pinctrl-names = "default"; 2105 pinctrl-0 = <&i2s1m0_lrck 2106 &i2s1m0_sclk 2107 &i2s1m0_sdi0 2108 &i2s1m0_sdi1 2109 &i2s1m0_sdi2 2110 &i2s1m0_sdi3 2111 &i2s1m0_sdo0 2112 &i2s1m0_sdo1 2113 &i2s1m0_sdo2 2114 &i2s1m0_sdo3>; 2115 #sound-dai-cells = <0>; 2116 status = "disabled"; 2117 }; 2118 2119 i2s2_2ch: i2s@fe490000 { 2120 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 2121 reg = <0x0 0xfe490000 0x0 0x1000>; 2122 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; 2123 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 2124 clock-names = "i2s_clk", "i2s_hclk"; 2125 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 2126 assigned-clock-parents = <&cru PLL_AUPLL>; 2127 dmas = <&dmac1 0>, <&dmac1 1>; 2128 dma-names = "tx", "rx"; 2129 power-domains = <&power RK3588_PD_AUDIO>; 2130 pinctrl-names = "default"; 2131 pinctrl-0 = <&i2s2m1_lrck 2132 &i2s2m1_sclk 2133 &i2s2m1_sdi 2134 &i2s2m1_sdo>; 2135 #sound-dai-cells = <0>; 2136 status = "disabled"; 2137 }; 2138 2139 i2s3_2ch: i2s@fe4a0000 { 2140 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 2141 reg = <0x0 0xfe4a0000 0x0 0x1000>; 2142 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; 2143 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 2144 clock-names = "i2s_clk", "i2s_hclk"; 2145 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 2146 assigned-clock-parents = <&cru PLL_AUPLL>; 2147 dmas = <&dmac1 2>, <&dmac1 3>; 2148 dma-names = "tx", "rx"; 2149 power-domains = <&power RK3588_PD_AUDIO>; 2150 pinctrl-names = "default"; 2151 pinctrl-0 = <&i2s3_lrck 2152 &i2s3_sclk 2153 &i2s3_sdi 2154 &i2s3_sdo>; 2155 #sound-dai-cells = <0>; 2156 status = "disabled"; 2157 }; 2158 2159 spdif_tx0: spdif-tx@fe4e0000 { 2160 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 2161 reg = <0x0 0xfe4e0000 0x0 0x1000>; 2162 assigned-clock-parents = <&cru PLL_AUPLL>; 2163 assigned-clocks = <&cru CLK_SPDIF0_SRC>; 2164 clock-names = "mclk", "hclk"; 2165 clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; 2166 dma-names = "tx"; 2167 dmas = <&dmac0 5>; 2168 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 2169 pinctrl-0 = <&spdif0m0_tx>; 2170 pinctrl-names = "default"; 2171 power-domains = <&power RK3588_PD_AUDIO>; 2172 #sound-dai-cells = <0>; 2173 status = "disabled"; 2174 }; 2175 2176 spdif_tx1: spdif-tx@fe4f0000 { 2177 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 2178 reg = <0x0 0xfe4f0000 0x0 0x1000>; 2179 assigned-clock-parents = <&cru PLL_AUPLL>; 2180 assigned-clocks = <&cru CLK_SPDIF1_SRC>; 2181 clock-names = "mclk", "hclk"; 2182 clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; 2183 dma-names = "tx"; 2184 dmas = <&dmac1 5>; 2185 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 2186 pinctrl-0 = <&spdif1m0_tx>; 2187 pinctrl-names = "default"; 2188 power-domains = <&power RK3588_PD_AUDIO>; 2189 #sound-dai-cells = <0>; 2190 status = "disabled"; 2191 }; 2192 2193 gic: interrupt-controller@fe600000 { 2194 compatible = "arm,gic-v3"; 2195 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 2196 <0x0 0xfe680000 0 0x100000>; /* GICR */ 2197 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 2198 interrupt-controller; 2199 dma-noncoherent; 2200 mbi-alias = <0x0 0xfe610000>; 2201 mbi-ranges = <424 56>; 2202 msi-controller; 2203 ranges; 2204 #address-cells = <2>; 2205 #interrupt-cells = <4>; 2206 #size-cells = <2>; 2207 2208 its0: msi-controller@fe640000 { 2209 compatible = "arm,gic-v3-its"; 2210 reg = <0x0 0xfe640000 0x0 0x20000>; 2211 dma-noncoherent; 2212 msi-controller; 2213 #msi-cells = <1>; 2214 }; 2215 2216 its1: msi-controller@fe660000 { 2217 compatible = "arm,gic-v3-its"; 2218 reg = <0x0 0xfe660000 0x0 0x20000>; 2219 dma-noncoherent; 2220 msi-controller; 2221 #msi-cells = <1>; 2222 }; 2223 2224 ppi-partitions { 2225 ppi_partition0: interrupt-partition-0 { 2226 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 2227 }; 2228 2229 ppi_partition1: interrupt-partition-1 { 2230 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; 2231 }; 2232 }; 2233 }; 2234 2235 dmac0: dma-controller@fea10000 { 2236 compatible = "arm,pl330", "arm,primecell"; 2237 reg = <0x0 0xfea10000 0x0 0x4000>; 2238 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, 2239 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; 2240 arm,pl330-periph-burst; 2241 clocks = <&cru ACLK_DMAC0>; 2242 clock-names = "apb_pclk"; 2243 #dma-cells = <1>; 2244 }; 2245 2246 dmac1: dma-controller@fea30000 { 2247 compatible = "arm,pl330", "arm,primecell"; 2248 reg = <0x0 0xfea30000 0x0 0x4000>; 2249 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, 2250 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; 2251 arm,pl330-periph-burst; 2252 clocks = <&cru ACLK_DMAC1>; 2253 clock-names = "apb_pclk"; 2254 #dma-cells = <1>; 2255 }; 2256 2257 i2c1: i2c@fea90000 { 2258 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2259 reg = <0x0 0xfea90000 0x0 0x1000>; 2260 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 2261 clock-names = "i2c", "pclk"; 2262 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; 2263 pinctrl-0 = <&i2c1m0_xfer>; 2264 pinctrl-names = "default"; 2265 #address-cells = <1>; 2266 #size-cells = <0>; 2267 status = "disabled"; 2268 }; 2269 2270 i2c2: i2c@feaa0000 { 2271 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2272 reg = <0x0 0xfeaa0000 0x0 0x1000>; 2273 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 2274 clock-names = "i2c", "pclk"; 2275 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; 2276 pinctrl-0 = <&i2c2m0_xfer>; 2277 pinctrl-names = "default"; 2278 #address-cells = <1>; 2279 #size-cells = <0>; 2280 status = "disabled"; 2281 }; 2282 2283 i2c3: i2c@feab0000 { 2284 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2285 reg = <0x0 0xfeab0000 0x0 0x1000>; 2286 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 2287 clock-names = "i2c", "pclk"; 2288 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; 2289 pinctrl-0 = <&i2c3m0_xfer>; 2290 pinctrl-names = "default"; 2291 #address-cells = <1>; 2292 #size-cells = <0>; 2293 status = "disabled"; 2294 }; 2295 2296 i2c4: i2c@feac0000 { 2297 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2298 reg = <0x0 0xfeac0000 0x0 0x1000>; 2299 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2300 clock-names = "i2c", "pclk"; 2301 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; 2302 pinctrl-0 = <&i2c4m0_xfer>; 2303 pinctrl-names = "default"; 2304 #address-cells = <1>; 2305 #size-cells = <0>; 2306 status = "disabled"; 2307 }; 2308 2309 i2c5: i2c@fead0000 { 2310 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2311 reg = <0x0 0xfead0000 0x0 0x1000>; 2312 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2313 clock-names = "i2c", "pclk"; 2314 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; 2315 pinctrl-0 = <&i2c5m0_xfer>; 2316 pinctrl-names = "default"; 2317 #address-cells = <1>; 2318 #size-cells = <0>; 2319 status = "disabled"; 2320 }; 2321 2322 timer0: timer@feae0000 { 2323 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 2324 reg = <0x0 0xfeae0000 0x0 0x20>; 2325 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; 2326 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 2327 clock-names = "pclk", "timer"; 2328 }; 2329 2330 wdt: watchdog@feaf0000 { 2331 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; 2332 reg = <0x0 0xfeaf0000 0x0 0x100>; 2333 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 2334 clock-names = "tclk", "pclk"; 2335 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; 2336 }; 2337 2338 spi0: spi@feb00000 { 2339 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2340 reg = <0x0 0xfeb00000 0x0 0x1000>; 2341 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; 2342 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 2343 clock-names = "spiclk", "apb_pclk"; 2344 dmas = <&dmac0 14>, <&dmac0 15>; 2345 dma-names = "tx", "rx"; 2346 num-cs = <2>; 2347 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 2348 pinctrl-names = "default"; 2349 #address-cells = <1>; 2350 #size-cells = <0>; 2351 status = "disabled"; 2352 }; 2353 2354 spi1: spi@feb10000 { 2355 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2356 reg = <0x0 0xfeb10000 0x0 0x1000>; 2357 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; 2358 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 2359 clock-names = "spiclk", "apb_pclk"; 2360 dmas = <&dmac0 16>, <&dmac0 17>; 2361 dma-names = "tx", "rx"; 2362 num-cs = <2>; 2363 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 2364 pinctrl-names = "default"; 2365 #address-cells = <1>; 2366 #size-cells = <0>; 2367 status = "disabled"; 2368 }; 2369 2370 spi2: spi@feb20000 { 2371 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2372 reg = <0x0 0xfeb20000 0x0 0x1000>; 2373 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; 2374 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 2375 clock-names = "spiclk", "apb_pclk"; 2376 dmas = <&dmac1 15>, <&dmac1 16>; 2377 dma-names = "tx", "rx"; 2378 num-cs = <2>; 2379 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 2380 pinctrl-names = "default"; 2381 #address-cells = <1>; 2382 #size-cells = <0>; 2383 status = "disabled"; 2384 }; 2385 2386 spi3: spi@feb30000 { 2387 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2388 reg = <0x0 0xfeb30000 0x0 0x1000>; 2389 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; 2390 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 2391 clock-names = "spiclk", "apb_pclk"; 2392 dmas = <&dmac1 17>, <&dmac1 18>; 2393 dma-names = "tx", "rx"; 2394 num-cs = <2>; 2395 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 2396 pinctrl-names = "default"; 2397 #address-cells = <1>; 2398 #size-cells = <0>; 2399 status = "disabled"; 2400 }; 2401 2402 uart1: serial@feb40000 { 2403 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2404 reg = <0x0 0xfeb40000 0x0 0x100>; 2405 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; 2406 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 2407 clock-names = "baudclk", "apb_pclk"; 2408 dmas = <&dmac0 8>, <&dmac0 9>; 2409 dma-names = "tx", "rx"; 2410 pinctrl-0 = <&uart1m1_xfer>; 2411 pinctrl-names = "default"; 2412 reg-io-width = <4>; 2413 reg-shift = <2>; 2414 status = "disabled"; 2415 }; 2416 2417 uart2: serial@feb50000 { 2418 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2419 reg = <0x0 0xfeb50000 0x0 0x100>; 2420 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; 2421 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 2422 clock-names = "baudclk", "apb_pclk"; 2423 dmas = <&dmac0 10>, <&dmac0 11>; 2424 dma-names = "tx", "rx"; 2425 pinctrl-0 = <&uart2m1_xfer>; 2426 pinctrl-names = "default"; 2427 reg-io-width = <4>; 2428 reg-shift = <2>; 2429 status = "disabled"; 2430 }; 2431 2432 uart3: serial@feb60000 { 2433 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2434 reg = <0x0 0xfeb60000 0x0 0x100>; 2435 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; 2436 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 2437 clock-names = "baudclk", "apb_pclk"; 2438 dmas = <&dmac0 12>, <&dmac0 13>; 2439 dma-names = "tx", "rx"; 2440 pinctrl-0 = <&uart3m1_xfer>; 2441 pinctrl-names = "default"; 2442 reg-io-width = <4>; 2443 reg-shift = <2>; 2444 status = "disabled"; 2445 }; 2446 2447 uart4: serial@feb70000 { 2448 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2449 reg = <0x0 0xfeb70000 0x0 0x100>; 2450 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; 2451 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 2452 clock-names = "baudclk", "apb_pclk"; 2453 dmas = <&dmac1 9>, <&dmac1 10>; 2454 dma-names = "tx", "rx"; 2455 pinctrl-0 = <&uart4m1_xfer>; 2456 pinctrl-names = "default"; 2457 reg-io-width = <4>; 2458 reg-shift = <2>; 2459 status = "disabled"; 2460 }; 2461 2462 uart5: serial@feb80000 { 2463 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2464 reg = <0x0 0xfeb80000 0x0 0x100>; 2465 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; 2466 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2467 clock-names = "baudclk", "apb_pclk"; 2468 dmas = <&dmac1 11>, <&dmac1 12>; 2469 dma-names = "tx", "rx"; 2470 pinctrl-0 = <&uart5m1_xfer>; 2471 pinctrl-names = "default"; 2472 reg-io-width = <4>; 2473 reg-shift = <2>; 2474 status = "disabled"; 2475 }; 2476 2477 uart6: serial@feb90000 { 2478 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2479 reg = <0x0 0xfeb90000 0x0 0x100>; 2480 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; 2481 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2482 clock-names = "baudclk", "apb_pclk"; 2483 dmas = <&dmac1 13>, <&dmac1 14>; 2484 dma-names = "tx", "rx"; 2485 pinctrl-0 = <&uart6m1_xfer>; 2486 pinctrl-names = "default"; 2487 reg-io-width = <4>; 2488 reg-shift = <2>; 2489 status = "disabled"; 2490 }; 2491 2492 uart7: serial@feba0000 { 2493 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2494 reg = <0x0 0xfeba0000 0x0 0x100>; 2495 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; 2496 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2497 clock-names = "baudclk", "apb_pclk"; 2498 dmas = <&dmac2 7>, <&dmac2 8>; 2499 dma-names = "tx", "rx"; 2500 pinctrl-0 = <&uart7m1_xfer>; 2501 pinctrl-names = "default"; 2502 reg-io-width = <4>; 2503 reg-shift = <2>; 2504 status = "disabled"; 2505 }; 2506 2507 uart8: serial@febb0000 { 2508 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2509 reg = <0x0 0xfebb0000 0x0 0x100>; 2510 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; 2511 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2512 clock-names = "baudclk", "apb_pclk"; 2513 dmas = <&dmac2 9>, <&dmac2 10>; 2514 dma-names = "tx", "rx"; 2515 pinctrl-0 = <&uart8m1_xfer>; 2516 pinctrl-names = "default"; 2517 reg-io-width = <4>; 2518 reg-shift = <2>; 2519 status = "disabled"; 2520 }; 2521 2522 uart9: serial@febc0000 { 2523 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2524 reg = <0x0 0xfebc0000 0x0 0x100>; 2525 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; 2526 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2527 clock-names = "baudclk", "apb_pclk"; 2528 dmas = <&dmac2 11>, <&dmac2 12>; 2529 dma-names = "tx", "rx"; 2530 pinctrl-0 = <&uart9m1_xfer>; 2531 pinctrl-names = "default"; 2532 reg-io-width = <4>; 2533 reg-shift = <2>; 2534 status = "disabled"; 2535 }; 2536 2537 pwm4: pwm@febd0000 { 2538 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2539 reg = <0x0 0xfebd0000 0x0 0x10>; 2540 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2541 clock-names = "pwm", "pclk"; 2542 pinctrl-0 = <&pwm4m0_pins>; 2543 pinctrl-names = "default"; 2544 #pwm-cells = <3>; 2545 status = "disabled"; 2546 }; 2547 2548 pwm5: pwm@febd0010 { 2549 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2550 reg = <0x0 0xfebd0010 0x0 0x10>; 2551 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2552 clock-names = "pwm", "pclk"; 2553 pinctrl-0 = <&pwm5m0_pins>; 2554 pinctrl-names = "default"; 2555 #pwm-cells = <3>; 2556 status = "disabled"; 2557 }; 2558 2559 pwm6: pwm@febd0020 { 2560 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2561 reg = <0x0 0xfebd0020 0x0 0x10>; 2562 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2563 clock-names = "pwm", "pclk"; 2564 pinctrl-0 = <&pwm6m0_pins>; 2565 pinctrl-names = "default"; 2566 #pwm-cells = <3>; 2567 status = "disabled"; 2568 }; 2569 2570 pwm7: pwm@febd0030 { 2571 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2572 reg = <0x0 0xfebd0030 0x0 0x10>; 2573 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2574 clock-names = "pwm", "pclk"; 2575 pinctrl-0 = <&pwm7m0_pins>; 2576 pinctrl-names = "default"; 2577 #pwm-cells = <3>; 2578 status = "disabled"; 2579 }; 2580 2581 pwm8: pwm@febe0000 { 2582 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2583 reg = <0x0 0xfebe0000 0x0 0x10>; 2584 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2585 clock-names = "pwm", "pclk"; 2586 pinctrl-0 = <&pwm8m0_pins>; 2587 pinctrl-names = "default"; 2588 #pwm-cells = <3>; 2589 status = "disabled"; 2590 }; 2591 2592 pwm9: pwm@febe0010 { 2593 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2594 reg = <0x0 0xfebe0010 0x0 0x10>; 2595 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2596 clock-names = "pwm", "pclk"; 2597 pinctrl-0 = <&pwm9m0_pins>; 2598 pinctrl-names = "default"; 2599 #pwm-cells = <3>; 2600 status = "disabled"; 2601 }; 2602 2603 pwm10: pwm@febe0020 { 2604 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2605 reg = <0x0 0xfebe0020 0x0 0x10>; 2606 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2607 clock-names = "pwm", "pclk"; 2608 pinctrl-0 = <&pwm10m0_pins>; 2609 pinctrl-names = "default"; 2610 #pwm-cells = <3>; 2611 status = "disabled"; 2612 }; 2613 2614 pwm11: pwm@febe0030 { 2615 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2616 reg = <0x0 0xfebe0030 0x0 0x10>; 2617 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2618 clock-names = "pwm", "pclk"; 2619 pinctrl-0 = <&pwm11m0_pins>; 2620 pinctrl-names = "default"; 2621 #pwm-cells = <3>; 2622 status = "disabled"; 2623 }; 2624 2625 pwm12: pwm@febf0000 { 2626 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2627 reg = <0x0 0xfebf0000 0x0 0x10>; 2628 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2629 clock-names = "pwm", "pclk"; 2630 pinctrl-0 = <&pwm12m0_pins>; 2631 pinctrl-names = "default"; 2632 #pwm-cells = <3>; 2633 status = "disabled"; 2634 }; 2635 2636 pwm13: pwm@febf0010 { 2637 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2638 reg = <0x0 0xfebf0010 0x0 0x10>; 2639 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2640 clock-names = "pwm", "pclk"; 2641 pinctrl-0 = <&pwm13m0_pins>; 2642 pinctrl-names = "default"; 2643 #pwm-cells = <3>; 2644 status = "disabled"; 2645 }; 2646 2647 pwm14: pwm@febf0020 { 2648 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2649 reg = <0x0 0xfebf0020 0x0 0x10>; 2650 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2651 clock-names = "pwm", "pclk"; 2652 pinctrl-0 = <&pwm14m0_pins>; 2653 pinctrl-names = "default"; 2654 #pwm-cells = <3>; 2655 status = "disabled"; 2656 }; 2657 2658 pwm15: pwm@febf0030 { 2659 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2660 reg = <0x0 0xfebf0030 0x0 0x10>; 2661 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2662 clock-names = "pwm", "pclk"; 2663 pinctrl-0 = <&pwm15m0_pins>; 2664 pinctrl-names = "default"; 2665 #pwm-cells = <3>; 2666 status = "disabled"; 2667 }; 2668 2669 thermal_zones: thermal-zones { 2670 /* sensor near the center of the SoC */ 2671 package_thermal: package-thermal { 2672 polling-delay-passive = <0>; 2673 polling-delay = <0>; 2674 thermal-sensors = <&tsadc 0>; 2675 2676 trips { 2677 package_crit: package-crit { 2678 temperature = <115000>; 2679 hysteresis = <0>; 2680 type = "critical"; 2681 }; 2682 }; 2683 }; 2684 2685 /* sensor between A76 cores 0 and 1 */ 2686 bigcore0_thermal: bigcore0-thermal { 2687 polling-delay-passive = <100>; 2688 polling-delay = <0>; 2689 thermal-sensors = <&tsadc 1>; 2690 2691 trips { 2692 bigcore0_alert: bigcore0-alert { 2693 temperature = <85000>; 2694 hysteresis = <2000>; 2695 type = "passive"; 2696 }; 2697 2698 bigcore0_crit: bigcore0-crit { 2699 temperature = <115000>; 2700 hysteresis = <0>; 2701 type = "critical"; 2702 }; 2703 }; 2704 2705 cooling-maps { 2706 map0 { 2707 trip = <&bigcore0_alert>; 2708 cooling-device = 2709 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2710 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2711 }; 2712 }; 2713 }; 2714 2715 /* sensor between A76 cores 2 and 3 */ 2716 bigcore2_thermal: bigcore2-thermal { 2717 polling-delay-passive = <100>; 2718 polling-delay = <0>; 2719 thermal-sensors = <&tsadc 2>; 2720 2721 trips { 2722 bigcore2_alert: bigcore2-alert { 2723 temperature = <85000>; 2724 hysteresis = <2000>; 2725 type = "passive"; 2726 }; 2727 2728 bigcore2_crit: bigcore2-crit { 2729 temperature = <115000>; 2730 hysteresis = <0>; 2731 type = "critical"; 2732 }; 2733 }; 2734 2735 cooling-maps { 2736 map0 { 2737 trip = <&bigcore2_alert>; 2738 cooling-device = 2739 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2740 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2741 }; 2742 }; 2743 }; 2744 2745 /* sensor between the four A55 cores */ 2746 little_core_thermal: littlecore-thermal { 2747 polling-delay-passive = <100>; 2748 polling-delay = <0>; 2749 thermal-sensors = <&tsadc 3>; 2750 2751 trips { 2752 littlecore_alert: littlecore-alert { 2753 temperature = <85000>; 2754 hysteresis = <2000>; 2755 type = "passive"; 2756 }; 2757 2758 littlecore_crit: littlecore-crit { 2759 temperature = <115000>; 2760 hysteresis = <0>; 2761 type = "critical"; 2762 }; 2763 }; 2764 2765 cooling-maps { 2766 map0 { 2767 trip = <&littlecore_alert>; 2768 cooling-device = 2769 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2770 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2771 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2772 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2773 }; 2774 }; 2775 }; 2776 2777 /* sensor near the PD_CENTER power domain */ 2778 center_thermal: center-thermal { 2779 polling-delay-passive = <0>; 2780 polling-delay = <0>; 2781 thermal-sensors = <&tsadc 4>; 2782 2783 trips { 2784 center_crit: center-crit { 2785 temperature = <115000>; 2786 hysteresis = <0>; 2787 type = "critical"; 2788 }; 2789 }; 2790 }; 2791 2792 gpu_thermal: gpu-thermal { 2793 polling-delay-passive = <100>; 2794 polling-delay = <0>; 2795 thermal-sensors = <&tsadc 5>; 2796 2797 trips { 2798 gpu_alert: gpu-alert { 2799 temperature = <85000>; 2800 hysteresis = <2000>; 2801 type = "passive"; 2802 }; 2803 2804 gpu_crit: gpu-crit { 2805 temperature = <115000>; 2806 hysteresis = <0>; 2807 type = "critical"; 2808 }; 2809 }; 2810 2811 cooling-maps { 2812 map0 { 2813 trip = <&gpu_alert>; 2814 cooling-device = 2815 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2816 }; 2817 }; 2818 }; 2819 2820 npu_thermal: npu-thermal { 2821 polling-delay-passive = <0>; 2822 polling-delay = <0>; 2823 thermal-sensors = <&tsadc 6>; 2824 2825 trips { 2826 npu_crit: npu-crit { 2827 temperature = <115000>; 2828 hysteresis = <0>; 2829 type = "critical"; 2830 }; 2831 }; 2832 }; 2833 }; 2834 2835 tsadc: tsadc@fec00000 { 2836 compatible = "rockchip,rk3588-tsadc"; 2837 reg = <0x0 0xfec00000 0x0 0x400>; 2838 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; 2839 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2840 clock-names = "tsadc", "apb_pclk"; 2841 assigned-clocks = <&cru CLK_TSADC>; 2842 assigned-clock-rates = <2000000>; 2843 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 2844 reset-names = "tsadc-apb", "tsadc"; 2845 rockchip,hw-tshut-temp = <120000>; 2846 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 2847 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2848 pinctrl-0 = <&tsadc_shut_org>; 2849 pinctrl-1 = <&tsadc_gpio_func>; 2850 pinctrl-names = "default", "sleep"; 2851 #thermal-sensor-cells = <1>; 2852 status = "disabled"; 2853 }; 2854 2855 saradc: adc@fec10000 { 2856 compatible = "rockchip,rk3588-saradc"; 2857 reg = <0x0 0xfec10000 0x0 0x10000>; 2858 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; 2859 #io-channel-cells = <1>; 2860 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2861 clock-names = "saradc", "apb_pclk"; 2862 resets = <&cru SRST_P_SARADC>; 2863 reset-names = "saradc-apb"; 2864 status = "disabled"; 2865 }; 2866 2867 i2c6: i2c@fec80000 { 2868 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2869 reg = <0x0 0xfec80000 0x0 0x1000>; 2870 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2871 clock-names = "i2c", "pclk"; 2872 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; 2873 pinctrl-0 = <&i2c6m0_xfer>; 2874 pinctrl-names = "default"; 2875 #address-cells = <1>; 2876 #size-cells = <0>; 2877 status = "disabled"; 2878 }; 2879 2880 i2c7: i2c@fec90000 { 2881 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2882 reg = <0x0 0xfec90000 0x0 0x1000>; 2883 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2884 clock-names = "i2c", "pclk"; 2885 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 2886 pinctrl-0 = <&i2c7m0_xfer>; 2887 pinctrl-names = "default"; 2888 #address-cells = <1>; 2889 #size-cells = <0>; 2890 status = "disabled"; 2891 }; 2892 2893 i2c8: i2c@feca0000 { 2894 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2895 reg = <0x0 0xfeca0000 0x0 0x1000>; 2896 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2897 clock-names = "i2c", "pclk"; 2898 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; 2899 pinctrl-0 = <&i2c8m0_xfer>; 2900 pinctrl-names = "default"; 2901 #address-cells = <1>; 2902 #size-cells = <0>; 2903 status = "disabled"; 2904 }; 2905 2906 spi4: spi@fecb0000 { 2907 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2908 reg = <0x0 0xfecb0000 0x0 0x1000>; 2909 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; 2910 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2911 clock-names = "spiclk", "apb_pclk"; 2912 dmas = <&dmac2 13>, <&dmac2 14>; 2913 dma-names = "tx", "rx"; 2914 num-cs = <2>; 2915 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 2916 pinctrl-names = "default"; 2917 #address-cells = <1>; 2918 #size-cells = <0>; 2919 status = "disabled"; 2920 }; 2921 2922 otp: efuse@fecc0000 { 2923 compatible = "rockchip,rk3588-otp"; 2924 reg = <0x0 0xfecc0000 0x0 0x400>; 2925 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 2926 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; 2927 clock-names = "otp", "apb_pclk", "phy", "arb"; 2928 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 2929 <&cru SRST_OTPC_ARB>; 2930 reset-names = "otp", "apb", "arb"; 2931 #address-cells = <1>; 2932 #size-cells = <1>; 2933 2934 cpu_code: cpu-code@2 { 2935 reg = <0x02 0x2>; 2936 }; 2937 2938 otp_id: id@7 { 2939 reg = <0x07 0x10>; 2940 }; 2941 2942 cpub0_leakage: cpu-leakage@17 { 2943 reg = <0x17 0x1>; 2944 }; 2945 2946 cpub1_leakage: cpu-leakage@18 { 2947 reg = <0x18 0x1>; 2948 }; 2949 2950 cpul_leakage: cpu-leakage@19 { 2951 reg = <0x19 0x1>; 2952 }; 2953 2954 log_leakage: log-leakage@1a { 2955 reg = <0x1a 0x1>; 2956 }; 2957 2958 gpu_leakage: gpu-leakage@1b { 2959 reg = <0x1b 0x1>; 2960 }; 2961 2962 otp_cpu_version: cpu-version@1c { 2963 reg = <0x1c 0x1>; 2964 bits = <3 3>; 2965 }; 2966 2967 npu_leakage: npu-leakage@28 { 2968 reg = <0x28 0x1>; 2969 }; 2970 2971 codec_leakage: codec-leakage@29 { 2972 reg = <0x29 0x1>; 2973 }; 2974 }; 2975 2976 dmac2: dma-controller@fed10000 { 2977 compatible = "arm,pl330", "arm,primecell"; 2978 reg = <0x0 0xfed10000 0x0 0x4000>; 2979 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, 2980 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; 2981 arm,pl330-periph-burst; 2982 clocks = <&cru ACLK_DMAC2>; 2983 clock-names = "apb_pclk"; 2984 #dma-cells = <1>; 2985 }; 2986 2987 hdptxphy0: phy@fed60000 { 2988 compatible = "rockchip,rk3588-hdptx-phy"; 2989 reg = <0x0 0xfed60000 0x0 0x2000>; 2990 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 2991 clock-names = "ref", "apb"; 2992 #clock-cells = <0>; 2993 #phy-cells = <0>; 2994 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, 2995 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, 2996 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, 2997 <&cru SRST_HDPTX0_LCPLL>; 2998 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 2999 "lcpll"; 3000 rockchip,grf = <&hdptxphy0_grf>; 3001 status = "disabled"; 3002 }; 3003 3004 usbdp_phy0: phy@fed80000 { 3005 compatible = "rockchip,rk3588-usbdp-phy"; 3006 reg = <0x0 0xfed80000 0x0 0x10000>; 3007 #phy-cells = <1>; 3008 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 3009 <&cru CLK_USBDP_PHY0_IMMORTAL>, 3010 <&cru PCLK_USBDPPHY0>, 3011 <&u2phy0>; 3012 clock-names = "refclk", "immortal", "pclk", "utmi"; 3013 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 3014 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 3015 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 3016 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 3017 <&cru SRST_P_USBDPPHY0>; 3018 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 3019 rockchip,u2phy-grf = <&usb2phy0_grf>; 3020 rockchip,usb-grf = <&usb_grf>; 3021 rockchip,usbdpphy-grf = <&usbdpphy0_grf>; 3022 rockchip,vo-grf = <&vo0_grf>; 3023 status = "disabled"; 3024 }; 3025 3026 mipidcphy0: phy@feda0000 { 3027 compatible = "rockchip,rk3588-mipi-dcphy"; 3028 reg = <0x0 0xfeda0000 0x0 0x10000>; 3029 rockchip,grf = <&mipidcphy0_grf>; 3030 clocks = <&cru PCLK_MIPI_DCPHY0>, 3031 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; 3032 clock-names = "pclk", "ref"; 3033 resets = <&cru SRST_M_MIPI_DCPHY0>, 3034 <&cru SRST_P_MIPI_DCPHY0>, 3035 <&cru SRST_P_MIPI_DCPHY0_GRF>, 3036 <&cru SRST_S_MIPI_DCPHY0>; 3037 reset-names = "m_phy", "apb", "grf", "s_phy"; 3038 #phy-cells = <1>; 3039 status = "disabled"; 3040 }; 3041 3042 mipidcphy1: phy@fedb0000 { 3043 compatible = "rockchip,rk3588-mipi-dcphy"; 3044 reg = <0x0 0xfedb0000 0x0 0x10000>; 3045 rockchip,grf = <&mipidcphy1_grf>; 3046 clocks = <&cru PCLK_MIPI_DCPHY1>, 3047 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; 3048 clock-names = "pclk", "ref"; 3049 resets = <&cru SRST_M_MIPI_DCPHY1>, 3050 <&cru SRST_P_MIPI_DCPHY1>, 3051 <&cru SRST_P_MIPI_DCPHY1_GRF>, 3052 <&cru SRST_S_MIPI_DCPHY1>; 3053 reset-names = "m_phy", "apb", "grf", "s_phy"; 3054 #phy-cells = <1>; 3055 status = "disabled"; 3056 }; 3057 3058 combphy0_ps: phy@fee00000 { 3059 compatible = "rockchip,rk3588-naneng-combphy"; 3060 reg = <0x0 0xfee00000 0x0 0x100>; 3061 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, 3062 <&cru PCLK_PHP_ROOT>; 3063 clock-names = "ref", "apb", "pipe"; 3064 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 3065 assigned-clock-rates = <100000000>; 3066 #phy-cells = <1>; 3067 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; 3068 reset-names = "phy", "apb"; 3069 rockchip,pipe-grf = <&php_grf>; 3070 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 3071 status = "disabled"; 3072 }; 3073 3074 combphy2_psu: phy@fee20000 { 3075 compatible = "rockchip,rk3588-naneng-combphy"; 3076 reg = <0x0 0xfee20000 0x0 0x100>; 3077 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, 3078 <&cru PCLK_PHP_ROOT>; 3079 clock-names = "ref", "apb", "pipe"; 3080 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 3081 assigned-clock-rates = <100000000>; 3082 #phy-cells = <1>; 3083 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; 3084 reset-names = "phy", "apb"; 3085 rockchip,pipe-grf = <&php_grf>; 3086 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 3087 status = "disabled"; 3088 }; 3089 3090 system_sram2: sram@ff001000 { 3091 compatible = "mmio-sram"; 3092 reg = <0x0 0xff001000 0x0 0xef000>; 3093 ranges = <0x0 0x0 0xff001000 0xef000>; 3094 #address-cells = <1>; 3095 #size-cells = <1>; 3096 }; 3097 3098 pinctrl: pinctrl { 3099 compatible = "rockchip,rk3588-pinctrl"; 3100 ranges; 3101 rockchip,grf = <&ioc>; 3102 #address-cells = <2>; 3103 #size-cells = <2>; 3104 3105 gpio0: gpio@fd8a0000 { 3106 compatible = "rockchip,gpio-bank"; 3107 reg = <0x0 0xfd8a0000 0x0 0x100>; 3108 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 3109 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 3110 gpio-controller; 3111 gpio-ranges = <&pinctrl 0 0 32>; 3112 interrupt-controller; 3113 #gpio-cells = <2>; 3114 #interrupt-cells = <2>; 3115 }; 3116 3117 gpio1: gpio@fec20000 { 3118 compatible = "rockchip,gpio-bank"; 3119 reg = <0x0 0xfec20000 0x0 0x100>; 3120 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; 3121 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 3122 gpio-controller; 3123 gpio-ranges = <&pinctrl 0 32 32>; 3124 interrupt-controller; 3125 #gpio-cells = <2>; 3126 #interrupt-cells = <2>; 3127 }; 3128 3129 gpio2: gpio@fec30000 { 3130 compatible = "rockchip,gpio-bank"; 3131 reg = <0x0 0xfec30000 0x0 0x100>; 3132 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; 3133 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 3134 gpio-controller; 3135 gpio-ranges = <&pinctrl 0 64 32>; 3136 interrupt-controller; 3137 #gpio-cells = <2>; 3138 #interrupt-cells = <2>; 3139 }; 3140 3141 gpio3: gpio@fec40000 { 3142 compatible = "rockchip,gpio-bank"; 3143 reg = <0x0 0xfec40000 0x0 0x100>; 3144 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; 3145 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 3146 gpio-controller; 3147 gpio-ranges = <&pinctrl 0 96 32>; 3148 interrupt-controller; 3149 #gpio-cells = <2>; 3150 #interrupt-cells = <2>; 3151 }; 3152 3153 gpio4: gpio@fec50000 { 3154 compatible = "rockchip,gpio-bank"; 3155 reg = <0x0 0xfec50000 0x0 0x100>; 3156 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; 3157 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 3158 gpio-controller; 3159 gpio-ranges = <&pinctrl 0 128 32>; 3160 interrupt-controller; 3161 #gpio-cells = <2>; 3162 #interrupt-cells = <2>; 3163 }; 3164 }; 3165}; 3166 3167#include "rk3588-base-pinctrl.dtsi" 3168