1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/power/rk3588-power.h> 11#include <dt-bindings/reset/rockchip,rk3588-cru.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/ata/ahci.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 compatible = "rockchip,rk3588"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 gpio0 = &gpio0; 25 gpio1 = &gpio1; 26 gpio2 = &gpio2; 27 gpio3 = &gpio3; 28 gpio4 = &gpio4; 29 i2c0 = &i2c0; 30 i2c1 = &i2c1; 31 i2c2 = &i2c2; 32 i2c3 = &i2c3; 33 i2c4 = &i2c4; 34 i2c5 = &i2c5; 35 i2c6 = &i2c6; 36 i2c7 = &i2c7; 37 i2c8 = &i2c8; 38 serial0 = &uart0; 39 serial1 = &uart1; 40 serial2 = &uart2; 41 serial3 = &uart3; 42 serial4 = &uart4; 43 serial5 = &uart5; 44 serial6 = &uart6; 45 serial7 = &uart7; 46 serial8 = &uart8; 47 serial9 = &uart9; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi2 = &spi2; 51 spi3 = &spi3; 52 spi4 = &spi4; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu-map { 60 cluster0 { 61 core0 { 62 cpu = <&cpu_l0>; 63 }; 64 core1 { 65 cpu = <&cpu_l1>; 66 }; 67 core2 { 68 cpu = <&cpu_l2>; 69 }; 70 core3 { 71 cpu = <&cpu_l3>; 72 }; 73 }; 74 cluster1 { 75 core0 { 76 cpu = <&cpu_b0>; 77 }; 78 core1 { 79 cpu = <&cpu_b1>; 80 }; 81 }; 82 cluster2 { 83 core0 { 84 cpu = <&cpu_b2>; 85 }; 86 core1 { 87 cpu = <&cpu_b3>; 88 }; 89 }; 90 }; 91 92 cpu_l0: cpu@0 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a55"; 95 reg = <0x0>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <530>; 98 clocks = <&scmi_clk SCMI_CLK_CPUL>; 99 cpu-idle-states = <&CPU_SLEEP>; 100 i-cache-size = <32768>; 101 i-cache-line-size = <64>; 102 i-cache-sets = <128>; 103 d-cache-size = <32768>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 next-level-cache = <&l2_cache_l0>; 107 dynamic-power-coefficient = <228>; 108 #cooling-cells = <2>; 109 }; 110 111 cpu_l1: cpu@100 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a55"; 114 reg = <0x100>; 115 enable-method = "psci"; 116 capacity-dmips-mhz = <530>; 117 clocks = <&scmi_clk SCMI_CLK_CPUL>; 118 cpu-idle-states = <&CPU_SLEEP>; 119 i-cache-size = <32768>; 120 i-cache-line-size = <64>; 121 i-cache-sets = <128>; 122 d-cache-size = <32768>; 123 d-cache-line-size = <64>; 124 d-cache-sets = <128>; 125 next-level-cache = <&l2_cache_l1>; 126 dynamic-power-coefficient = <228>; 127 #cooling-cells = <2>; 128 }; 129 130 cpu_l2: cpu@200 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a55"; 133 reg = <0x200>; 134 enable-method = "psci"; 135 capacity-dmips-mhz = <530>; 136 clocks = <&scmi_clk SCMI_CLK_CPUL>; 137 cpu-idle-states = <&CPU_SLEEP>; 138 i-cache-size = <32768>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <128>; 141 d-cache-size = <32768>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <128>; 144 next-level-cache = <&l2_cache_l2>; 145 dynamic-power-coefficient = <228>; 146 #cooling-cells = <2>; 147 }; 148 149 cpu_l3: cpu@300 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a55"; 152 reg = <0x300>; 153 enable-method = "psci"; 154 capacity-dmips-mhz = <530>; 155 clocks = <&scmi_clk SCMI_CLK_CPUL>; 156 cpu-idle-states = <&CPU_SLEEP>; 157 i-cache-size = <32768>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <128>; 160 d-cache-size = <32768>; 161 d-cache-line-size = <64>; 162 d-cache-sets = <128>; 163 next-level-cache = <&l2_cache_l3>; 164 dynamic-power-coefficient = <228>; 165 #cooling-cells = <2>; 166 }; 167 168 cpu_b0: cpu@400 { 169 device_type = "cpu"; 170 compatible = "arm,cortex-a76"; 171 reg = <0x400>; 172 enable-method = "psci"; 173 capacity-dmips-mhz = <1024>; 174 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 175 cpu-idle-states = <&CPU_SLEEP>; 176 i-cache-size = <65536>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <65536>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&l2_cache_b0>; 183 dynamic-power-coefficient = <416>; 184 #cooling-cells = <2>; 185 }; 186 187 cpu_b1: cpu@500 { 188 device_type = "cpu"; 189 compatible = "arm,cortex-a76"; 190 reg = <0x500>; 191 enable-method = "psci"; 192 capacity-dmips-mhz = <1024>; 193 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 194 cpu-idle-states = <&CPU_SLEEP>; 195 i-cache-size = <65536>; 196 i-cache-line-size = <64>; 197 i-cache-sets = <256>; 198 d-cache-size = <65536>; 199 d-cache-line-size = <64>; 200 d-cache-sets = <256>; 201 next-level-cache = <&l2_cache_b1>; 202 dynamic-power-coefficient = <416>; 203 #cooling-cells = <2>; 204 }; 205 206 cpu_b2: cpu@600 { 207 device_type = "cpu"; 208 compatible = "arm,cortex-a76"; 209 reg = <0x600>; 210 enable-method = "psci"; 211 capacity-dmips-mhz = <1024>; 212 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 213 cpu-idle-states = <&CPU_SLEEP>; 214 i-cache-size = <65536>; 215 i-cache-line-size = <64>; 216 i-cache-sets = <256>; 217 d-cache-size = <65536>; 218 d-cache-line-size = <64>; 219 d-cache-sets = <256>; 220 next-level-cache = <&l2_cache_b2>; 221 dynamic-power-coefficient = <416>; 222 #cooling-cells = <2>; 223 }; 224 225 cpu_b3: cpu@700 { 226 device_type = "cpu"; 227 compatible = "arm,cortex-a76"; 228 reg = <0x700>; 229 enable-method = "psci"; 230 capacity-dmips-mhz = <1024>; 231 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 232 cpu-idle-states = <&CPU_SLEEP>; 233 i-cache-size = <65536>; 234 i-cache-line-size = <64>; 235 i-cache-sets = <256>; 236 d-cache-size = <65536>; 237 d-cache-line-size = <64>; 238 d-cache-sets = <256>; 239 next-level-cache = <&l2_cache_b3>; 240 dynamic-power-coefficient = <416>; 241 #cooling-cells = <2>; 242 }; 243 244 idle-states { 245 entry-method = "psci"; 246 CPU_SLEEP: cpu-sleep { 247 compatible = "arm,idle-state"; 248 local-timer-stop; 249 arm,psci-suspend-param = <0x0010000>; 250 entry-latency-us = <100>; 251 exit-latency-us = <120>; 252 min-residency-us = <1000>; 253 }; 254 }; 255 256 l2_cache_l0: l2-cache-l0 { 257 compatible = "cache"; 258 cache-size = <131072>; 259 cache-line-size = <64>; 260 cache-sets = <512>; 261 cache-level = <2>; 262 cache-unified; 263 next-level-cache = <&l3_cache>; 264 }; 265 266 l2_cache_l1: l2-cache-l1 { 267 compatible = "cache"; 268 cache-size = <131072>; 269 cache-line-size = <64>; 270 cache-sets = <512>; 271 cache-level = <2>; 272 cache-unified; 273 next-level-cache = <&l3_cache>; 274 }; 275 276 l2_cache_l2: l2-cache-l2 { 277 compatible = "cache"; 278 cache-size = <131072>; 279 cache-line-size = <64>; 280 cache-sets = <512>; 281 cache-level = <2>; 282 cache-unified; 283 next-level-cache = <&l3_cache>; 284 }; 285 286 l2_cache_l3: l2-cache-l3 { 287 compatible = "cache"; 288 cache-size = <131072>; 289 cache-line-size = <64>; 290 cache-sets = <512>; 291 cache-level = <2>; 292 cache-unified; 293 next-level-cache = <&l3_cache>; 294 }; 295 296 l2_cache_b0: l2-cache-b0 { 297 compatible = "cache"; 298 cache-size = <524288>; 299 cache-line-size = <64>; 300 cache-sets = <1024>; 301 cache-level = <2>; 302 cache-unified; 303 next-level-cache = <&l3_cache>; 304 }; 305 306 l2_cache_b1: l2-cache-b1 { 307 compatible = "cache"; 308 cache-size = <524288>; 309 cache-line-size = <64>; 310 cache-sets = <1024>; 311 cache-level = <2>; 312 cache-unified; 313 next-level-cache = <&l3_cache>; 314 }; 315 316 l2_cache_b2: l2-cache-b2 { 317 compatible = "cache"; 318 cache-size = <524288>; 319 cache-line-size = <64>; 320 cache-sets = <1024>; 321 cache-level = <2>; 322 cache-unified; 323 next-level-cache = <&l3_cache>; 324 }; 325 326 l2_cache_b3: l2-cache-b3 { 327 compatible = "cache"; 328 cache-size = <524288>; 329 cache-line-size = <64>; 330 cache-sets = <1024>; 331 cache-level = <2>; 332 cache-unified; 333 next-level-cache = <&l3_cache>; 334 }; 335 }; 336 337 /* 338 * The L3 cache belongs to the DynamIQ Shared Unit (DSU), 339 * so it's represented here, outside the "cpus" node 340 */ 341 l3_cache: l3-cache { 342 compatible = "cache"; 343 cache-size = <3145728>; 344 cache-line-size = <64>; 345 cache-sets = <4096>; 346 cache-level = <3>; 347 cache-unified; 348 }; 349 350 display_subsystem: display-subsystem { 351 compatible = "rockchip,display-subsystem"; 352 ports = <&vop_out>; 353 }; 354 355 firmware { 356 scmi: scmi { 357 compatible = "arm,scmi-smc"; 358 arm,smc-id = <0x82000010>; 359 shmem = <&scmi_shmem>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 363 scmi_clk: protocol@14 { 364 reg = <0x14>; 365 #clock-cells = <1>; 366 }; 367 368 scmi_reset: protocol@16 { 369 reg = <0x16>; 370 #reset-cells = <1>; 371 }; 372 }; 373 }; 374 375 hdmi0_sound: hdmi0-sound { 376 compatible = "simple-audio-card"; 377 simple-audio-card,format = "i2s"; 378 simple-audio-card,mclk-fs = <128>; 379 simple-audio-card,name = "hdmi0"; 380 status = "disabled"; 381 382 simple-audio-card,codec { 383 sound-dai = <&hdmi0>; 384 }; 385 386 simple-audio-card,cpu { 387 sound-dai = <&i2s5_8ch>; 388 }; 389 }; 390 391 pmu-a55 { 392 compatible = "arm,cortex-a55-pmu"; 393 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; 394 }; 395 396 pmu-a76 { 397 compatible = "arm,cortex-a76-pmu"; 398 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; 399 }; 400 401 psci { 402 compatible = "arm,psci-1.0"; 403 method = "smc"; 404 }; 405 406 spll: clock-0 { 407 compatible = "fixed-clock"; 408 clock-frequency = <702000000>; 409 clock-output-names = "spll"; 410 #clock-cells = <0>; 411 }; 412 413 timer { 414 compatible = "arm,armv8-timer"; 415 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 416 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 417 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 418 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, 419 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 420 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 421 }; 422 423 xin24m: clock-1 { 424 compatible = "fixed-clock"; 425 clock-frequency = <24000000>; 426 clock-output-names = "xin24m"; 427 #clock-cells = <0>; 428 }; 429 430 xin32k: clock-2 { 431 compatible = "fixed-clock"; 432 clock-frequency = <32768>; 433 clock-output-names = "xin32k"; 434 #clock-cells = <0>; 435 }; 436 437 reserved-memory { 438 #address-cells = <2>; 439 #size-cells = <2>; 440 ranges; 441 442 scmi_shmem: shmem@10f000 { 443 compatible = "arm,scmi-shmem"; 444 reg = <0x0 0x0010f000 0x0 0x100>; 445 no-map; 446 }; 447 }; 448 449 gpu: gpu@fb000000 { 450 compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; 451 reg = <0x0 0xfb000000 0x0 0x200000>; 452 #cooling-cells = <2>; 453 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 454 assigned-clock-rates = <200000000>; 455 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, 456 <&cru CLK_GPU_STACKS>; 457 clock-names = "core", "coregroup", "stacks"; 458 dynamic-power-coefficient = <2982>; 459 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, 460 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, 461 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>; 462 interrupt-names = "job", "mmu", "gpu"; 463 power-domains = <&power RK3588_PD_GPU>; 464 status = "disabled"; 465 }; 466 467 usb_host0_xhci: usb@fc000000 { 468 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 469 reg = <0x0 0xfc000000 0x0 0x400000>; 470 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 471 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, 472 <&cru ACLK_USB3OTG0>; 473 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 474 dr_mode = "otg"; 475 phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; 476 phy-names = "usb2-phy", "usb3-phy"; 477 phy_type = "utmi_wide"; 478 power-domains = <&power RK3588_PD_USB>; 479 resets = <&cru SRST_A_USB3OTG0>; 480 snps,dis_enblslpm_quirk; 481 snps,dis-u1-entry-quirk; 482 snps,dis-u2-entry-quirk; 483 snps,dis-u2-freeclk-exists-quirk; 484 snps,dis-del-phy-power-chg-quirk; 485 snps,dis-tx-ipgap-linecheck-quirk; 486 status = "disabled"; 487 }; 488 489 usb_host0_ehci: usb@fc800000 { 490 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 491 reg = <0x0 0xfc800000 0x0 0x40000>; 492 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; 493 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 494 phys = <&u2phy2_host>; 495 phy-names = "usb"; 496 power-domains = <&power RK3588_PD_USB>; 497 status = "disabled"; 498 }; 499 500 usb_host0_ohci: usb@fc840000 { 501 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 502 reg = <0x0 0xfc840000 0x0 0x40000>; 503 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; 504 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 505 phys = <&u2phy2_host>; 506 phy-names = "usb"; 507 power-domains = <&power RK3588_PD_USB>; 508 status = "disabled"; 509 }; 510 511 usb_host1_ehci: usb@fc880000 { 512 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 513 reg = <0x0 0xfc880000 0x0 0x40000>; 514 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; 515 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 516 phys = <&u2phy3_host>; 517 phy-names = "usb"; 518 power-domains = <&power RK3588_PD_USB>; 519 status = "disabled"; 520 }; 521 522 usb_host1_ohci: usb@fc8c0000 { 523 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 524 reg = <0x0 0xfc8c0000 0x0 0x40000>; 525 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; 526 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 527 phys = <&u2phy3_host>; 528 phy-names = "usb"; 529 power-domains = <&power RK3588_PD_USB>; 530 status = "disabled"; 531 }; 532 533 usb_host2_xhci: usb@fcd00000 { 534 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 535 reg = <0x0 0xfcd00000 0x0 0x400000>; 536 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; 537 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, 538 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, 539 <&cru CLK_PIPEPHY2_PIPE_U3_G>; 540 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; 541 dr_mode = "host"; 542 phys = <&combphy2_psu PHY_TYPE_USB3>; 543 phy-names = "usb3-phy"; 544 phy_type = "utmi_wide"; 545 resets = <&cru SRST_A_USB3OTG2>; 546 snps,dis_enblslpm_quirk; 547 snps,dis-u2-freeclk-exists-quirk; 548 snps,dis-del-phy-power-chg-quirk; 549 snps,dis-tx-ipgap-linecheck-quirk; 550 snps,dis_rxdet_inp3_quirk; 551 status = "disabled"; 552 }; 553 554 mmu600_pcie: iommu@fc900000 { 555 compatible = "arm,smmu-v3"; 556 reg = <0x0 0xfc900000 0x0 0x200000>; 557 interrupts = <GIC_SPI 369 IRQ_TYPE_EDGE_RISING 0>, 558 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING 0>, 559 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING 0>, 560 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>; 561 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 562 #iommu-cells = <1>; 563 }; 564 565 mmu600_php: iommu@fcb00000 { 566 compatible = "arm,smmu-v3"; 567 reg = <0x0 0xfcb00000 0x0 0x200000>; 568 interrupts = <GIC_SPI 381 IRQ_TYPE_EDGE_RISING 0>, 569 <GIC_SPI 383 IRQ_TYPE_EDGE_RISING 0>, 570 <GIC_SPI 386 IRQ_TYPE_EDGE_RISING 0>, 571 <GIC_SPI 379 IRQ_TYPE_EDGE_RISING 0>; 572 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 573 #iommu-cells = <1>; 574 status = "disabled"; 575 }; 576 577 pmu1grf: syscon@fd58a000 { 578 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; 579 reg = <0x0 0xfd58a000 0x0 0x10000>; 580 }; 581 582 sys_grf: syscon@fd58c000 { 583 compatible = "rockchip,rk3588-sys-grf", "syscon"; 584 reg = <0x0 0xfd58c000 0x0 0x1000>; 585 }; 586 587 mipidcphy0_grf: syscon@fd5e8000 { 588 compatible = "rockchip,rk3588-dcphy-grf", "syscon"; 589 reg = <0x0 0xfd5e8000 0x0 0x4000>; 590 }; 591 592 mipidcphy1_grf: syscon@fd5ec000 { 593 compatible = "rockchip,rk3588-dcphy-grf", "syscon"; 594 reg = <0x0 0xfd5ec000 0x0 0x4000>; 595 }; 596 597 vop_grf: syscon@fd5a4000 { 598 compatible = "rockchip,rk3588-vop-grf", "syscon"; 599 reg = <0x0 0xfd5a4000 0x0 0x2000>; 600 }; 601 602 vo0_grf: syscon@fd5a6000 { 603 compatible = "rockchip,rk3588-vo0-grf", "syscon"; 604 reg = <0x0 0xfd5a6000 0x0 0x2000>; 605 clocks = <&cru PCLK_VO0GRF>; 606 }; 607 608 vo1_grf: syscon@fd5a8000 { 609 compatible = "rockchip,rk3588-vo1-grf", "syscon"; 610 reg = <0x0 0xfd5a8000 0x0 0x4000>; 611 clocks = <&cru PCLK_VO1GRF>; 612 }; 613 614 usb_grf: syscon@fd5ac000 { 615 compatible = "rockchip,rk3588-usb-grf", "syscon"; 616 reg = <0x0 0xfd5ac000 0x0 0x4000>; 617 }; 618 619 php_grf: syscon@fd5b0000 { 620 compatible = "rockchip,rk3588-php-grf", "syscon"; 621 reg = <0x0 0xfd5b0000 0x0 0x1000>; 622 }; 623 624 csidphy0_grf: syscon@fd5b4000 { 625 compatible = "rockchip,rk3588-csidphy-grf", "syscon"; 626 reg = <0x0 0xfd5b4000 0x0 0x1000>; 627 }; 628 629 csidphy1_grf: syscon@fd5b5000 { 630 compatible = "rockchip,rk3588-csidphy-grf", "syscon"; 631 reg = <0x0 0xfd5b5000 0x0 0x1000>; 632 }; 633 634 pipe_phy0_grf: syscon@fd5bc000 { 635 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 636 reg = <0x0 0xfd5bc000 0x0 0x100>; 637 }; 638 639 pipe_phy2_grf: syscon@fd5c4000 { 640 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 641 reg = <0x0 0xfd5c4000 0x0 0x100>; 642 }; 643 644 usbdpphy0_grf: syscon@fd5c8000 { 645 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 646 reg = <0x0 0xfd5c8000 0x0 0x4000>; 647 }; 648 649 usb2phy0_grf: syscon@fd5d0000 { 650 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 651 reg = <0x0 0xfd5d0000 0x0 0x4000>; 652 #address-cells = <1>; 653 #size-cells = <1>; 654 655 u2phy0: usb2phy@0 { 656 compatible = "rockchip,rk3588-usb2phy"; 657 reg = <0x0 0x10>; 658 #clock-cells = <0>; 659 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 660 clock-names = "phyclk"; 661 clock-output-names = "usb480m_phy0"; 662 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; 663 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; 664 reset-names = "phy", "apb"; 665 status = "disabled"; 666 667 u2phy0_otg: otg-port { 668 #phy-cells = <0>; 669 status = "disabled"; 670 }; 671 }; 672 }; 673 674 usb2phy2_grf: syscon@fd5d8000 { 675 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 676 reg = <0x0 0xfd5d8000 0x0 0x4000>; 677 #address-cells = <1>; 678 #size-cells = <1>; 679 680 u2phy2: usb2phy@8000 { 681 compatible = "rockchip,rk3588-usb2phy"; 682 reg = <0x8000 0x10>; 683 #clock-cells = <0>; 684 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 685 clock-names = "phyclk"; 686 clock-output-names = "usb480m_phy2"; 687 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 688 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 689 reset-names = "phy", "apb"; 690 status = "disabled"; 691 692 u2phy2_host: host-port { 693 #phy-cells = <0>; 694 status = "disabled"; 695 }; 696 }; 697 }; 698 699 usb2phy3_grf: syscon@fd5dc000 { 700 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 701 reg = <0x0 0xfd5dc000 0x0 0x4000>; 702 #address-cells = <1>; 703 #size-cells = <1>; 704 705 u2phy3: usb2phy@c000 { 706 compatible = "rockchip,rk3588-usb2phy"; 707 reg = <0xc000 0x10>; 708 #clock-cells = <0>; 709 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 710 clock-names = "phyclk"; 711 clock-output-names = "usb480m_phy3"; 712 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 713 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 714 reset-names = "phy", "apb"; 715 status = "disabled"; 716 717 u2phy3_host: host-port { 718 #phy-cells = <0>; 719 status = "disabled"; 720 }; 721 }; 722 }; 723 724 hdptxphy0_grf: syscon@fd5e0000 { 725 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 726 reg = <0x0 0xfd5e0000 0x0 0x100>; 727 }; 728 729 ioc: syscon@fd5f0000 { 730 compatible = "rockchip,rk3588-ioc", "syscon"; 731 reg = <0x0 0xfd5f0000 0x0 0x10000>; 732 }; 733 734 system_sram1: sram@fd600000 { 735 compatible = "mmio-sram"; 736 reg = <0x0 0xfd600000 0x0 0x100000>; 737 ranges = <0x0 0x0 0xfd600000 0x100000>; 738 #address-cells = <1>; 739 #size-cells = <1>; 740 }; 741 742 cru: clock-controller@fd7c0000 { 743 compatible = "rockchip,rk3588-cru"; 744 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 745 assigned-clocks = 746 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 747 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 748 <&cru ACLK_CENTER_ROOT>, 749 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 750 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 751 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 752 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, 753 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 754 <&cru CLK_GPU>; 755 assigned-clock-rates = 756 <1100000000>, <786432000>, 757 <850000000>, <1188000000>, 758 <702000000>, 759 <400000000>, <500000000>, 760 <800000000>, <100000000>, 761 <400000000>, <100000000>, 762 <200000000>, <500000000>, 763 <375000000>, <150000000>, 764 <200000000>; 765 rockchip,grf = <&php_grf>; 766 #clock-cells = <1>; 767 #reset-cells = <1>; 768 }; 769 770 i2c0: i2c@fd880000 { 771 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 772 reg = <0x0 0xfd880000 0x0 0x1000>; 773 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; 774 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 775 clock-names = "i2c", "pclk"; 776 pinctrl-0 = <&i2c0m0_xfer>; 777 pinctrl-names = "default"; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 status = "disabled"; 781 }; 782 783 uart0: serial@fd890000 { 784 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 785 reg = <0x0 0xfd890000 0x0 0x100>; 786 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 787 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 788 clock-names = "baudclk", "apb_pclk"; 789 dmas = <&dmac0 6>, <&dmac0 7>; 790 dma-names = "tx", "rx"; 791 pinctrl-0 = <&uart0m1_xfer>; 792 pinctrl-names = "default"; 793 reg-shift = <2>; 794 reg-io-width = <4>; 795 status = "disabled"; 796 }; 797 798 pwm0: pwm@fd8b0000 { 799 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 800 reg = <0x0 0xfd8b0000 0x0 0x10>; 801 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 802 clock-names = "pwm", "pclk"; 803 pinctrl-0 = <&pwm0m0_pins>; 804 pinctrl-names = "default"; 805 #pwm-cells = <3>; 806 status = "disabled"; 807 }; 808 809 pwm1: pwm@fd8b0010 { 810 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 811 reg = <0x0 0xfd8b0010 0x0 0x10>; 812 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 813 clock-names = "pwm", "pclk"; 814 pinctrl-0 = <&pwm1m0_pins>; 815 pinctrl-names = "default"; 816 #pwm-cells = <3>; 817 status = "disabled"; 818 }; 819 820 pwm2: pwm@fd8b0020 { 821 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 822 reg = <0x0 0xfd8b0020 0x0 0x10>; 823 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 824 clock-names = "pwm", "pclk"; 825 pinctrl-0 = <&pwm2m0_pins>; 826 pinctrl-names = "default"; 827 #pwm-cells = <3>; 828 status = "disabled"; 829 }; 830 831 pwm3: pwm@fd8b0030 { 832 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 833 reg = <0x0 0xfd8b0030 0x0 0x10>; 834 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 835 clock-names = "pwm", "pclk"; 836 pinctrl-0 = <&pwm3m0_pins>; 837 pinctrl-names = "default"; 838 #pwm-cells = <3>; 839 status = "disabled"; 840 }; 841 842 pmu: power-management@fd8d8000 { 843 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 844 reg = <0x0 0xfd8d8000 0x0 0x400>; 845 846 power: power-controller { 847 compatible = "rockchip,rk3588-power-controller"; 848 #address-cells = <1>; 849 #power-domain-cells = <1>; 850 #size-cells = <0>; 851 status = "okay"; 852 853 /* These power domains are grouped by VD_NPU */ 854 pd_npu: power-domain@RK3588_PD_NPU { 855 reg = <RK3588_PD_NPU>; 856 #power-domain-cells = <0>; 857 #address-cells = <1>; 858 #size-cells = <0>; 859 860 power-domain@RK3588_PD_NPUTOP { 861 reg = <RK3588_PD_NPUTOP>; 862 clocks = <&cru HCLK_NPU_ROOT>, 863 <&cru PCLK_NPU_ROOT>, 864 <&cru CLK_NPU_DSU0>, 865 <&cru HCLK_NPU_CM0_ROOT>; 866 pm_qos = <&qos_npu0_mwr>, 867 <&qos_npu0_mro>, 868 <&qos_mcu_npu>; 869 #power-domain-cells = <0>; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 873 power-domain@RK3588_PD_NPU1 { 874 reg = <RK3588_PD_NPU1>; 875 clocks = <&cru HCLK_NPU_ROOT>, 876 <&cru PCLK_NPU_ROOT>, 877 <&cru CLK_NPU_DSU0>; 878 pm_qos = <&qos_npu1>; 879 #power-domain-cells = <0>; 880 }; 881 power-domain@RK3588_PD_NPU2 { 882 reg = <RK3588_PD_NPU2>; 883 clocks = <&cru HCLK_NPU_ROOT>, 884 <&cru PCLK_NPU_ROOT>, 885 <&cru CLK_NPU_DSU0>; 886 pm_qos = <&qos_npu2>; 887 #power-domain-cells = <0>; 888 }; 889 }; 890 }; 891 /* These power domains are grouped by VD_GPU */ 892 pd_gpu: power-domain@RK3588_PD_GPU { 893 reg = <RK3588_PD_GPU>; 894 clocks = <&cru CLK_GPU>, 895 <&cru CLK_GPU_COREGROUP>, 896 <&cru CLK_GPU_STACKS>; 897 pm_qos = <&qos_gpu_m0>, 898 <&qos_gpu_m1>, 899 <&qos_gpu_m2>, 900 <&qos_gpu_m3>; 901 #power-domain-cells = <0>; 902 }; 903 /* These power domains are grouped by VD_VCODEC */ 904 power-domain@RK3588_PD_VCODEC { 905 reg = <RK3588_PD_VCODEC>; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 #power-domain-cells = <0>; 909 910 power-domain@RK3588_PD_RKVDEC0 { 911 reg = <RK3588_PD_RKVDEC0>; 912 clocks = <&cru HCLK_RKVDEC0>, 913 <&cru HCLK_VDPU_ROOT>, 914 <&cru ACLK_VDPU_ROOT>, 915 <&cru ACLK_RKVDEC0>, 916 <&cru ACLK_RKVDEC_CCU>; 917 pm_qos = <&qos_rkvdec0>; 918 #power-domain-cells = <0>; 919 }; 920 power-domain@RK3588_PD_RKVDEC1 { 921 reg = <RK3588_PD_RKVDEC1>; 922 clocks = <&cru HCLK_RKVDEC1>, 923 <&cru HCLK_VDPU_ROOT>, 924 <&cru ACLK_VDPU_ROOT>, 925 <&cru ACLK_RKVDEC1>; 926 pm_qos = <&qos_rkvdec1>; 927 #power-domain-cells = <0>; 928 }; 929 power-domain@RK3588_PD_VENC0 { 930 reg = <RK3588_PD_VENC0>; 931 clocks = <&cru HCLK_RKVENC0>, 932 <&cru ACLK_RKVENC0>; 933 pm_qos = <&qos_rkvenc0_m0ro>, 934 <&qos_rkvenc0_m1ro>, 935 <&qos_rkvenc0_m2wo>; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 #power-domain-cells = <0>; 939 940 power-domain@RK3588_PD_VENC1 { 941 reg = <RK3588_PD_VENC1>; 942 clocks = <&cru HCLK_RKVENC1>, 943 <&cru HCLK_RKVENC0>, 944 <&cru ACLK_RKVENC0>, 945 <&cru ACLK_RKVENC1>; 946 pm_qos = <&qos_rkvenc1_m0ro>, 947 <&qos_rkvenc1_m1ro>, 948 <&qos_rkvenc1_m2wo>; 949 #power-domain-cells = <0>; 950 }; 951 }; 952 }; 953 /* These power domains are grouped by VD_LOGIC */ 954 power-domain@RK3588_PD_VDPU { 955 reg = <RK3588_PD_VDPU>; 956 clocks = <&cru HCLK_VDPU_ROOT>, 957 <&cru ACLK_VDPU_LOW_ROOT>, 958 <&cru ACLK_VDPU_ROOT>, 959 <&cru ACLK_JPEG_DECODER_ROOT>, 960 <&cru ACLK_IEP2P0>, 961 <&cru HCLK_IEP2P0>, 962 <&cru ACLK_JPEG_ENCODER0>, 963 <&cru HCLK_JPEG_ENCODER0>, 964 <&cru ACLK_JPEG_ENCODER1>, 965 <&cru HCLK_JPEG_ENCODER1>, 966 <&cru ACLK_JPEG_ENCODER2>, 967 <&cru HCLK_JPEG_ENCODER2>, 968 <&cru ACLK_JPEG_ENCODER3>, 969 <&cru HCLK_JPEG_ENCODER3>, 970 <&cru ACLK_JPEG_DECODER>, 971 <&cru HCLK_JPEG_DECODER>, 972 <&cru ACLK_RGA2>, 973 <&cru HCLK_RGA2>; 974 pm_qos = <&qos_iep>, 975 <&qos_jpeg_dec>, 976 <&qos_jpeg_enc0>, 977 <&qos_jpeg_enc1>, 978 <&qos_jpeg_enc2>, 979 <&qos_jpeg_enc3>, 980 <&qos_rga2_mro>, 981 <&qos_rga2_mwo>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 #power-domain-cells = <0>; 985 986 987 power-domain@RK3588_PD_AV1 { 988 reg = <RK3588_PD_AV1>; 989 clocks = <&cru PCLK_AV1>, 990 <&cru ACLK_AV1>, 991 <&cru HCLK_VDPU_ROOT>; 992 pm_qos = <&qos_av1>; 993 #power-domain-cells = <0>; 994 }; 995 power-domain@RK3588_PD_RKVDEC0 { 996 reg = <RK3588_PD_RKVDEC0>; 997 clocks = <&cru HCLK_RKVDEC0>, 998 <&cru HCLK_VDPU_ROOT>, 999 <&cru ACLK_VDPU_ROOT>, 1000 <&cru ACLK_RKVDEC0>; 1001 pm_qos = <&qos_rkvdec0>; 1002 #power-domain-cells = <0>; 1003 }; 1004 power-domain@RK3588_PD_RKVDEC1 { 1005 reg = <RK3588_PD_RKVDEC1>; 1006 clocks = <&cru HCLK_RKVDEC1>, 1007 <&cru HCLK_VDPU_ROOT>, 1008 <&cru ACLK_VDPU_ROOT>; 1009 pm_qos = <&qos_rkvdec1>; 1010 #power-domain-cells = <0>; 1011 }; 1012 power-domain@RK3588_PD_RGA30 { 1013 reg = <RK3588_PD_RGA30>; 1014 clocks = <&cru ACLK_RGA3_0>, 1015 <&cru HCLK_RGA3_0>; 1016 pm_qos = <&qos_rga3_0>; 1017 #power-domain-cells = <0>; 1018 }; 1019 }; 1020 power-domain@RK3588_PD_VOP { 1021 reg = <RK3588_PD_VOP>; 1022 clocks = <&cru PCLK_VOP_ROOT>, 1023 <&cru HCLK_VOP_ROOT>, 1024 <&cru ACLK_VOP>; 1025 pm_qos = <&qos_vop_m0>, 1026 <&qos_vop_m1>; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 #power-domain-cells = <0>; 1030 1031 power-domain@RK3588_PD_VO0 { 1032 reg = <RK3588_PD_VO0>; 1033 clocks = <&cru PCLK_VO0_ROOT>, 1034 <&cru PCLK_VO0_S_ROOT>, 1035 <&cru HCLK_VO0_S_ROOT>, 1036 <&cru ACLK_VO0_ROOT>, 1037 <&cru HCLK_HDCP0>, 1038 <&cru ACLK_HDCP0>, 1039 <&cru HCLK_VOP_ROOT>; 1040 pm_qos = <&qos_hdcp0>; 1041 #power-domain-cells = <0>; 1042 }; 1043 }; 1044 power-domain@RK3588_PD_VO1 { 1045 reg = <RK3588_PD_VO1>; 1046 clocks = <&cru PCLK_VO1_ROOT>, 1047 <&cru PCLK_VO1_S_ROOT>, 1048 <&cru HCLK_VO1_S_ROOT>, 1049 <&cru HCLK_HDCP1>, 1050 <&cru ACLK_HDCP1>, 1051 <&cru ACLK_HDMIRX_ROOT>, 1052 <&cru HCLK_VO1USB_TOP_ROOT>; 1053 pm_qos = <&qos_hdcp1>, 1054 <&qos_hdmirx>; 1055 #power-domain-cells = <0>; 1056 }; 1057 power-domain@RK3588_PD_VI { 1058 reg = <RK3588_PD_VI>; 1059 clocks = <&cru HCLK_VI_ROOT>, 1060 <&cru PCLK_VI_ROOT>, 1061 <&cru HCLK_ISP0>, 1062 <&cru ACLK_ISP0>, 1063 <&cru HCLK_VICAP>, 1064 <&cru ACLK_VICAP>; 1065 pm_qos = <&qos_isp0_mro>, 1066 <&qos_isp0_mwo>, 1067 <&qos_vicap_m0>, 1068 <&qos_vicap_m1>; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 #power-domain-cells = <0>; 1072 1073 power-domain@RK3588_PD_ISP1 { 1074 reg = <RK3588_PD_ISP1>; 1075 clocks = <&cru HCLK_ISP1>, 1076 <&cru ACLK_ISP1>, 1077 <&cru HCLK_VI_ROOT>, 1078 <&cru PCLK_VI_ROOT>; 1079 pm_qos = <&qos_isp1_mwo>, 1080 <&qos_isp1_mro>; 1081 #power-domain-cells = <0>; 1082 }; 1083 power-domain@RK3588_PD_FEC { 1084 reg = <RK3588_PD_FEC>; 1085 clocks = <&cru HCLK_FISHEYE0>, 1086 <&cru ACLK_FISHEYE0>, 1087 <&cru HCLK_FISHEYE1>, 1088 <&cru ACLK_FISHEYE1>, 1089 <&cru PCLK_VI_ROOT>; 1090 pm_qos = <&qos_fisheye0>, 1091 <&qos_fisheye1>; 1092 #power-domain-cells = <0>; 1093 }; 1094 }; 1095 power-domain@RK3588_PD_RGA31 { 1096 reg = <RK3588_PD_RGA31>; 1097 clocks = <&cru HCLK_RGA3_1>, 1098 <&cru ACLK_RGA3_1>; 1099 pm_qos = <&qos_rga3_1>; 1100 #power-domain-cells = <0>; 1101 }; 1102 power-domain@RK3588_PD_USB { 1103 reg = <RK3588_PD_USB>; 1104 clocks = <&cru PCLK_PHP_ROOT>, 1105 <&cru ACLK_USB_ROOT>, 1106 <&cru ACLK_USB>, 1107 <&cru HCLK_USB_ROOT>, 1108 <&cru HCLK_HOST0>, 1109 <&cru HCLK_HOST_ARB0>, 1110 <&cru HCLK_HOST1>, 1111 <&cru HCLK_HOST_ARB1>; 1112 pm_qos = <&qos_usb3_0>, 1113 <&qos_usb3_1>, 1114 <&qos_usb2host_0>, 1115 <&qos_usb2host_1>; 1116 #power-domain-cells = <0>; 1117 }; 1118 power-domain@RK3588_PD_GMAC { 1119 reg = <RK3588_PD_GMAC>; 1120 clocks = <&cru PCLK_PHP_ROOT>, 1121 <&cru ACLK_PCIE_ROOT>, 1122 <&cru ACLK_PHP_ROOT>; 1123 #power-domain-cells = <0>; 1124 }; 1125 power-domain@RK3588_PD_PCIE { 1126 reg = <RK3588_PD_PCIE>; 1127 clocks = <&cru PCLK_PHP_ROOT>, 1128 <&cru ACLK_PCIE_ROOT>, 1129 <&cru ACLK_PHP_ROOT>; 1130 #power-domain-cells = <0>; 1131 }; 1132 power-domain@RK3588_PD_SDIO { 1133 reg = <RK3588_PD_SDIO>; 1134 clocks = <&cru HCLK_SDIO>, 1135 <&cru HCLK_NVM_ROOT>; 1136 pm_qos = <&qos_sdio>; 1137 #power-domain-cells = <0>; 1138 }; 1139 power-domain@RK3588_PD_AUDIO { 1140 reg = <RK3588_PD_AUDIO>; 1141 clocks = <&cru HCLK_AUDIO_ROOT>, 1142 <&cru PCLK_AUDIO_ROOT>; 1143 #power-domain-cells = <0>; 1144 }; 1145 power-domain@RK3588_PD_SDMMC { 1146 reg = <RK3588_PD_SDMMC>; 1147 pm_qos = <&qos_sdmmc>; 1148 #power-domain-cells = <0>; 1149 }; 1150 }; 1151 }; 1152 1153 rknn_core_0: npu@fdab0000 { 1154 compatible = "rockchip,rk3588-rknn-core"; 1155 reg = <0x0 0xfdab0000 0x0 0x1000>, 1156 <0x0 0xfdab1000 0x0 0x1000>, 1157 <0x0 0xfdab3000 0x0 0x1000>; 1158 reg-names = "pc", "cna", "core"; 1159 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 1160 clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>, 1161 <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; 1162 clock-names = "aclk", "hclk", "npu", "pclk"; 1163 assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; 1164 assigned-clock-rates = <200000000>; 1165 resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>; 1166 reset-names = "srst_a", "srst_h"; 1167 power-domains = <&power RK3588_PD_NPUTOP>; 1168 iommus = <&rknn_mmu_0>; 1169 status = "disabled"; 1170 }; 1171 1172 rknn_mmu_0: iommu@fdab9000 { 1173 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1174 reg = <0x0 0xfdab9000 0x0 0x100>, 1175 <0x0 0xfdaba000 0x0 0x100>; 1176 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 1177 clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>; 1178 clock-names = "aclk", "iface"; 1179 #iommu-cells = <0>; 1180 power-domains = <&power RK3588_PD_NPUTOP>; 1181 status = "disabled"; 1182 }; 1183 1184 rknn_core_1: npu@fdac0000 { 1185 compatible = "rockchip,rk3588-rknn-core"; 1186 reg = <0x0 0xfdac0000 0x0 0x1000>, 1187 <0x0 0xfdac1000 0x0 0x1000>, 1188 <0x0 0xfdac3000 0x0 0x1000>; 1189 reg-names = "pc", "cna", "core"; 1190 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1191 clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>, 1192 <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; 1193 clock-names = "aclk", "hclk", "npu", "pclk"; 1194 assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; 1195 assigned-clock-rates = <200000000>; 1196 resets = <&cru SRST_A_RKNN1>, <&cru SRST_H_RKNN1>; 1197 reset-names = "srst_a", "srst_h"; 1198 power-domains = <&power RK3588_PD_NPU1>; 1199 iommus = <&rknn_mmu_1>; 1200 status = "disabled"; 1201 }; 1202 1203 rknn_mmu_1: iommu@fdaca000 { 1204 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1205 reg = <0x0 0xfdaca000 0x0 0x100>; 1206 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1207 clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>; 1208 clock-names = "aclk", "iface"; 1209 #iommu-cells = <0>; 1210 power-domains = <&power RK3588_PD_NPU1>; 1211 status = "disabled"; 1212 }; 1213 1214 rknn_core_2: npu@fdad0000 { 1215 compatible = "rockchip,rk3588-rknn-core"; 1216 reg = <0x0 0xfdad0000 0x0 0x1000>, 1217 <0x0 0xfdad1000 0x0 0x1000>, 1218 <0x0 0xfdad3000 0x0 0x1000>; 1219 reg-names = "pc", "cna", "core"; 1220 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 1221 clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>, 1222 <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; 1223 clock-names = "aclk", "hclk", "npu", "pclk"; 1224 assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; 1225 assigned-clock-rates = <200000000>; 1226 resets = <&cru SRST_A_RKNN2>, <&cru SRST_H_RKNN2>; 1227 reset-names = "srst_a", "srst_h"; 1228 power-domains = <&power RK3588_PD_NPU2>; 1229 iommus = <&rknn_mmu_2>; 1230 status = "disabled"; 1231 }; 1232 1233 rknn_mmu_2: iommu@fdada000 { 1234 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1235 reg = <0x0 0xfdada000 0x0 0x100>; 1236 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 1237 clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>; 1238 clock-names = "aclk", "iface"; 1239 #iommu-cells = <0>; 1240 power-domains = <&power RK3588_PD_NPU2>; 1241 status = "disabled"; 1242 }; 1243 1244 vpu121: video-codec@fdb50000 { 1245 compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu"; 1246 reg = <0x0 0xfdb50000 0x0 0x800>; 1247 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1248 interrupt-names = "vdpu"; 1249 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1250 clock-names = "aclk", "hclk"; 1251 iommus = <&vpu121_mmu>; 1252 power-domains = <&power RK3588_PD_VDPU>; 1253 }; 1254 1255 vpu121_mmu: iommu@fdb50800 { 1256 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1257 reg = <0x0 0xfdb50800 0x0 0x40>; 1258 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1259 clock-names = "aclk", "iface"; 1260 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1261 power-domains = <&power RK3588_PD_VDPU>; 1262 #iommu-cells = <0>; 1263 }; 1264 1265 rga: rga@fdb80000 { 1266 compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga"; 1267 reg = <0x0 0xfdb80000 0x0 0x180>; 1268 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1269 clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>; 1270 clock-names = "aclk", "hclk", "sclk"; 1271 resets = <&cru SRST_RGA2_CORE>, <&cru SRST_A_RGA2>, <&cru SRST_H_RGA2>; 1272 reset-names = "core", "axi", "ahb"; 1273 power-domains = <&power RK3588_PD_VDPU>; 1274 }; 1275 1276 vepu121_0: video-codec@fdba0000 { 1277 compatible = "rockchip,rk3588-vepu121"; 1278 reg = <0x0 0xfdba0000 0x0 0x800>; 1279 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>; 1280 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 1281 clock-names = "aclk", "hclk"; 1282 iommus = <&vepu121_0_mmu>; 1283 power-domains = <&power RK3588_PD_VDPU>; 1284 }; 1285 1286 vepu121_0_mmu: iommu@fdba0800 { 1287 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1288 reg = <0x0 0xfdba0800 0x0 0x40>; 1289 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 1290 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 1291 clock-names = "aclk", "iface"; 1292 power-domains = <&power RK3588_PD_VDPU>; 1293 #iommu-cells = <0>; 1294 }; 1295 1296 vepu121_1: video-codec@fdba4000 { 1297 compatible = "rockchip,rk3588-vepu121"; 1298 reg = <0x0 0xfdba4000 0x0 0x800>; 1299 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>; 1300 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 1301 clock-names = "aclk", "hclk"; 1302 iommus = <&vepu121_1_mmu>; 1303 power-domains = <&power RK3588_PD_VDPU>; 1304 }; 1305 1306 vepu121_1_mmu: iommu@fdba4800 { 1307 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1308 reg = <0x0 0xfdba4800 0x0 0x40>; 1309 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>; 1310 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 1311 clock-names = "aclk", "iface"; 1312 power-domains = <&power RK3588_PD_VDPU>; 1313 #iommu-cells = <0>; 1314 }; 1315 1316 vepu121_2: video-codec@fdba8000 { 1317 compatible = "rockchip,rk3588-vepu121"; 1318 reg = <0x0 0xfdba8000 0x0 0x800>; 1319 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>; 1320 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 1321 clock-names = "aclk", "hclk"; 1322 iommus = <&vepu121_2_mmu>; 1323 power-domains = <&power RK3588_PD_VDPU>; 1324 }; 1325 1326 vepu121_2_mmu: iommu@fdba8800 { 1327 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1328 reg = <0x0 0xfdba8800 0x0 0x40>; 1329 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>; 1330 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 1331 clock-names = "aclk", "iface"; 1332 power-domains = <&power RK3588_PD_VDPU>; 1333 #iommu-cells = <0>; 1334 }; 1335 1336 vepu121_3: video-codec@fdbac000 { 1337 compatible = "rockchip,rk3588-vepu121"; 1338 reg = <0x0 0xfdbac000 0x0 0x800>; 1339 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; 1340 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 1341 clock-names = "aclk", "hclk"; 1342 iommus = <&vepu121_3_mmu>; 1343 power-domains = <&power RK3588_PD_VDPU>; 1344 }; 1345 1346 vepu121_3_mmu: iommu@fdbac800 { 1347 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1348 reg = <0x0 0xfdbac800 0x0 0x40>; 1349 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>; 1350 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 1351 clock-names = "aclk", "iface"; 1352 power-domains = <&power RK3588_PD_VDPU>; 1353 #iommu-cells = <0>; 1354 }; 1355 1356 vdec0: video-codec@fdc38000 { 1357 compatible = "rockchip,rk3588-vdec"; 1358 reg = <0x0 0xfdc38100 0x0 0x500>, 1359 <0x0 0xfdc38000 0x0 0x100>, 1360 <0x0 0xfdc38600 0x0 0x100>; 1361 reg-names = "function", "link", "cache"; 1362 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>; 1363 clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>, 1364 <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; 1365 clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; 1366 assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, 1367 <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; 1368 assigned-clock-rates = <800000000>, <600000000>, 1369 <600000000>, <1000000000>; 1370 iommus = <&vdec0_mmu>; 1371 power-domains = <&power RK3588_PD_RKVDEC0>; 1372 resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>, 1373 <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>; 1374 reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; 1375 sram = <&vdec0_sram>; 1376 }; 1377 1378 vdec0_mmu: iommu@fdc38700 { 1379 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1380 reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; 1381 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>; 1382 clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; 1383 clock-names = "aclk", "iface"; 1384 power-domains = <&power RK3588_PD_RKVDEC0>; 1385 #iommu-cells = <0>; 1386 }; 1387 1388 vdec1: video-codec@fdc40000 { 1389 compatible = "rockchip,rk3588-vdec"; 1390 reg = <0x0 0xfdc40100 0x0 0x500>, 1391 <0x0 0xfdc40000 0x0 0x100>, 1392 <0x0 0xfdc40600 0x0 0x100>; 1393 reg-names = "function", "link", "cache"; 1394 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 1395 clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>, 1396 <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; 1397 clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; 1398 assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, 1399 <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; 1400 assigned-clock-rates = <800000000>, <600000000>, 1401 <600000000>, <1000000000>; 1402 iommus = <&vdec1_mmu>; 1403 power-domains = <&power RK3588_PD_RKVDEC1>; 1404 resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>, 1405 <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>; 1406 reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; 1407 sram = <&vdec1_sram>; 1408 }; 1409 1410 vdec1_mmu: iommu@fdc40700 { 1411 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1412 reg = <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>; 1413 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 1414 clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; 1415 clock-names = "aclk", "iface"; 1416 power-domains = <&power RK3588_PD_RKVDEC1>; 1417 #iommu-cells = <0>; 1418 }; 1419 1420 av1d: video-codec@fdc70000 { 1421 compatible = "rockchip,rk3588-av1-vpu"; 1422 reg = <0x0 0xfdc70000 0x0 0x800>; 1423 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 1424 interrupt-names = "vdpu"; 1425 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1426 assigned-clock-rates = <400000000>, <400000000>; 1427 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1428 clock-names = "aclk", "hclk"; 1429 power-domains = <&power RK3588_PD_AV1>; 1430 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; 1431 }; 1432 1433 vop: vop@fdd90000 { 1434 compatible = "rockchip,rk3588-vop"; 1435 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; 1436 reg-names = "vop", "gamma-lut"; 1437 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1438 clocks = <&cru ACLK_VOP>, 1439 <&cru HCLK_VOP>, 1440 <&cru DCLK_VOP0>, 1441 <&cru DCLK_VOP1>, 1442 <&cru DCLK_VOP2>, 1443 <&cru DCLK_VOP3>, 1444 <&cru PCLK_VOP_ROOT>, 1445 <&hdptxphy0>; 1446 clock-names = "aclk", 1447 "hclk", 1448 "dclk_vp0", 1449 "dclk_vp1", 1450 "dclk_vp2", 1451 "dclk_vp3", 1452 "pclk_vop", 1453 "pll_hdmiphy0"; 1454 iommus = <&vop_mmu>; 1455 power-domains = <&power RK3588_PD_VOP>; 1456 rockchip,grf = <&sys_grf>; 1457 rockchip,vop-grf = <&vop_grf>; 1458 rockchip,vo1-grf = <&vo1_grf>; 1459 rockchip,pmu = <&pmu>; 1460 status = "disabled"; 1461 1462 vop_out: ports { 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 1466 vp0: port@0 { 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 reg = <0>; 1470 }; 1471 1472 vp1: port@1 { 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 reg = <1>; 1476 }; 1477 1478 vp2: port@2 { 1479 #address-cells = <1>; 1480 #size-cells = <0>; 1481 reg = <2>; 1482 }; 1483 1484 vp3: port@3 { 1485 #address-cells = <1>; 1486 #size-cells = <0>; 1487 reg = <3>; 1488 }; 1489 }; 1490 }; 1491 1492 vop_mmu: iommu@fdd97e00 { 1493 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1494 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 1495 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1496 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1497 clock-names = "aclk", "iface"; 1498 #iommu-cells = <0>; 1499 power-domains = <&power RK3588_PD_VOP>; 1500 status = "disabled"; 1501 }; 1502 1503 spdif_tx2: spdif-tx@fddb0000 { 1504 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1505 reg = <0x0 0xfddb0000 0x0 0x1000>; 1506 assigned-clock-parents = <&cru PLL_AUPLL>; 1507 assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>; 1508 clock-names = "mclk", "hclk"; 1509 clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>; 1510 dma-names = "tx"; 1511 dmas = <&dmac1 6>; 1512 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1513 power-domains = <&power RK3588_PD_VO0>; 1514 #sound-dai-cells = <0>; 1515 status = "disabled"; 1516 }; 1517 1518 i2s4_8ch: i2s@fddc0000 { 1519 compatible = "rockchip,rk3588-i2s-tdm"; 1520 reg = <0x0 0xfddc0000 0x0 0x1000>; 1521 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; 1522 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 1523 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1524 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 1525 assigned-clock-parents = <&cru PLL_AUPLL>; 1526 dmas = <&dmac2 0>; 1527 dma-names = "tx"; 1528 power-domains = <&power RK3588_PD_VO0>; 1529 resets = <&cru SRST_M_I2S4_8CH_TX>; 1530 reset-names = "tx-m"; 1531 #sound-dai-cells = <0>; 1532 status = "disabled"; 1533 }; 1534 1535 spdif_tx3: spdif-tx@fdde0000 { 1536 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1537 reg = <0x0 0xfdde0000 0x0 0x1000>; 1538 assigned-clock-parents = <&cru PLL_AUPLL>; 1539 assigned-clocks = <&cru CLK_SPDIF3_SRC>; 1540 clock-names = "mclk", "hclk"; 1541 clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; 1542 dma-names = "tx"; 1543 dmas = <&dmac1 7>; 1544 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1545 power-domains = <&power RK3588_PD_VO1>; 1546 #sound-dai-cells = <0>; 1547 status = "disabled"; 1548 }; 1549 1550 i2s5_8ch: i2s@fddf0000 { 1551 compatible = "rockchip,rk3588-i2s-tdm"; 1552 reg = <0x0 0xfddf0000 0x0 0x1000>; 1553 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; 1554 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 1555 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1556 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 1557 assigned-clock-parents = <&cru PLL_AUPLL>; 1558 dmas = <&dmac2 2>; 1559 dma-names = "tx"; 1560 power-domains = <&power RK3588_PD_VO1>; 1561 resets = <&cru SRST_M_I2S5_8CH_TX>; 1562 reset-names = "tx-m"; 1563 #sound-dai-cells = <0>; 1564 status = "disabled"; 1565 }; 1566 1567 i2s9_8ch: i2s@fddfc000 { 1568 compatible = "rockchip,rk3588-i2s-tdm"; 1569 reg = <0x0 0xfddfc000 0x0 0x1000>; 1570 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; 1571 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 1572 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1573 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 1574 assigned-clock-parents = <&cru PLL_AUPLL>; 1575 dmas = <&dmac2 23>; 1576 dma-names = "rx"; 1577 power-domains = <&power RK3588_PD_VO1>; 1578 resets = <&cru SRST_M_I2S9_8CH_RX>; 1579 reset-names = "rx-m"; 1580 #sound-dai-cells = <0>; 1581 status = "disabled"; 1582 }; 1583 1584 dsi0: dsi@fde20000 { 1585 compatible = "rockchip,rk3588-mipi-dsi2"; 1586 reg = <0x0 0xfde20000 0x0 0x10000>; 1587 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>; 1588 clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; 1589 clock-names = "pclk", "sys"; 1590 resets = <&cru SRST_P_DSIHOST0>; 1591 reset-names = "apb"; 1592 power-domains = <&power RK3588_PD_VOP>; 1593 phys = <&mipidcphy0 PHY_TYPE_DPHY>; 1594 phy-names = "dcphy"; 1595 rockchip,grf = <&vop_grf>; 1596 status = "disabled"; 1597 1598 ports { 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 1602 dsi0_in: port@0 { 1603 reg = <0>; 1604 }; 1605 1606 dsi0_out: port@1 { 1607 reg = <1>; 1608 }; 1609 }; 1610 }; 1611 1612 dsi1: dsi@fde30000 { 1613 compatible = "rockchip,rk3588-mipi-dsi2"; 1614 reg = <0x0 0xfde30000 0x0 0x10000>; 1615 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>; 1616 clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>; 1617 clock-names = "pclk", "sys"; 1618 resets = <&cru SRST_P_DSIHOST1>; 1619 reset-names = "apb"; 1620 power-domains = <&power RK3588_PD_VOP>; 1621 phys = <&mipidcphy1 PHY_TYPE_DPHY>; 1622 phy-names = "dcphy"; 1623 rockchip,grf = <&vop_grf>; 1624 status = "disabled"; 1625 1626 ports { 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 1630 dsi1_in: port@0 { 1631 reg = <0>; 1632 }; 1633 1634 dsi1_out: port@1 { 1635 reg = <1>; 1636 }; 1637 }; 1638 }; 1639 1640 dp0: dp@fde50000 { 1641 compatible = "rockchip,rk3588-dp"; 1642 reg = <0x0 0xfde50000 0x0 0x4000>; 1643 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 1644 assigned-clocks = <&cru CLK_AUX16M_0>; 1645 assigned-clock-rates = <16000000>; 1646 clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>, 1647 <&cru CLK_DP0>, <&cru MCLK_I2S4_8CH_TX>, 1648 <&cru MCLK_SPDIF2_DP0>; 1649 clock-names = "apb", "aux", "hdcp", "i2s", "spdif"; 1650 phys = <&usbdp_phy0 PHY_TYPE_DP>; 1651 power-domains = <&power RK3588_PD_VO0>; 1652 resets = <&cru SRST_DP0>; 1653 #sound-dai-cells = <0>; 1654 status = "disabled"; 1655 1656 ports { 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 1660 dp0_in: port@0 { 1661 reg = <0>; 1662 }; 1663 1664 dp0_out: port@1 { 1665 reg = <1>; 1666 }; 1667 }; 1668 }; 1669 1670 hdmi0: hdmi@fde80000 { 1671 compatible = "rockchip,rk3588-dw-hdmi-qp"; 1672 reg = <0x0 0xfde80000 0x0 0x20000>; 1673 clocks = <&cru PCLK_HDMITX0>, 1674 <&cru CLK_HDMITX0_EARC>, 1675 <&cru CLK_HDMITX0_REF>, 1676 <&cru MCLK_I2S5_8CH_TX>, 1677 <&cru CLK_HDMIHDP0>, 1678 <&cru HCLK_VO1>; 1679 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; 1680 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>, 1681 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>, 1682 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>, 1683 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>, 1684 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>; 1685 interrupt-names = "avp", "cec", "earc", "main", "hpd"; 1686 phys = <&hdptxphy0>; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd 1689 &hdmim0_tx0_scl &hdmim0_tx0_sda>; 1690 power-domains = <&power RK3588_PD_VO1>; 1691 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; 1692 reset-names = "ref", "hdp"; 1693 rockchip,grf = <&sys_grf>; 1694 rockchip,vo-grf = <&vo1_grf>; 1695 #sound-dai-cells = <0>; 1696 status = "disabled"; 1697 1698 ports { 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 1702 hdmi0_in: port@0 { 1703 reg = <0>; 1704 }; 1705 1706 hdmi0_out: port@1 { 1707 reg = <1>; 1708 }; 1709 }; 1710 }; 1711 1712 edp0: edp@fdec0000 { 1713 compatible = "rockchip,rk3588-edp"; 1714 reg = <0x0 0xfdec0000 0x0 0x1000>; 1715 clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>; 1716 clock-names = "dp", "pclk"; 1717 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 1718 phys = <&hdptxphy0>; 1719 phy-names = "dp"; 1720 power-domains = <&power RK3588_PD_VO1>; 1721 resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; 1722 reset-names = "dp", "apb"; 1723 rockchip,grf = <&vo1_grf>; 1724 status = "disabled"; 1725 1726 ports { 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 1730 edp0_in: port@0 { 1731 reg = <0>; 1732 }; 1733 1734 edp0_out: port@1 { 1735 reg = <1>; 1736 }; 1737 }; 1738 }; 1739 1740 qos_gpu_m0: qos@fdf35000 { 1741 compatible = "rockchip,rk3588-qos", "syscon"; 1742 reg = <0x0 0xfdf35000 0x0 0x20>; 1743 }; 1744 1745 qos_gpu_m1: qos@fdf35200 { 1746 compatible = "rockchip,rk3588-qos", "syscon"; 1747 reg = <0x0 0xfdf35200 0x0 0x20>; 1748 }; 1749 1750 qos_gpu_m2: qos@fdf35400 { 1751 compatible = "rockchip,rk3588-qos", "syscon"; 1752 reg = <0x0 0xfdf35400 0x0 0x20>; 1753 }; 1754 1755 qos_gpu_m3: qos@fdf35600 { 1756 compatible = "rockchip,rk3588-qos", "syscon"; 1757 reg = <0x0 0xfdf35600 0x0 0x20>; 1758 }; 1759 1760 qos_rga3_1: qos@fdf36000 { 1761 compatible = "rockchip,rk3588-qos", "syscon"; 1762 reg = <0x0 0xfdf36000 0x0 0x20>; 1763 }; 1764 1765 qos_sdio: qos@fdf39000 { 1766 compatible = "rockchip,rk3588-qos", "syscon"; 1767 reg = <0x0 0xfdf39000 0x0 0x20>; 1768 }; 1769 1770 qos_sdmmc: qos@fdf3d800 { 1771 compatible = "rockchip,rk3588-qos", "syscon"; 1772 reg = <0x0 0xfdf3d800 0x0 0x20>; 1773 }; 1774 1775 qos_usb3_1: qos@fdf3e000 { 1776 compatible = "rockchip,rk3588-qos", "syscon"; 1777 reg = <0x0 0xfdf3e000 0x0 0x20>; 1778 }; 1779 1780 qos_usb3_0: qos@fdf3e200 { 1781 compatible = "rockchip,rk3588-qos", "syscon"; 1782 reg = <0x0 0xfdf3e200 0x0 0x20>; 1783 }; 1784 1785 qos_usb2host_0: qos@fdf3e400 { 1786 compatible = "rockchip,rk3588-qos", "syscon"; 1787 reg = <0x0 0xfdf3e400 0x0 0x20>; 1788 }; 1789 1790 qos_usb2host_1: qos@fdf3e600 { 1791 compatible = "rockchip,rk3588-qos", "syscon"; 1792 reg = <0x0 0xfdf3e600 0x0 0x20>; 1793 }; 1794 1795 qos_fisheye0: qos@fdf40000 { 1796 compatible = "rockchip,rk3588-qos", "syscon"; 1797 reg = <0x0 0xfdf40000 0x0 0x20>; 1798 }; 1799 1800 qos_fisheye1: qos@fdf40200 { 1801 compatible = "rockchip,rk3588-qos", "syscon"; 1802 reg = <0x0 0xfdf40200 0x0 0x20>; 1803 }; 1804 1805 qos_isp0_mro: qos@fdf40400 { 1806 compatible = "rockchip,rk3588-qos", "syscon"; 1807 reg = <0x0 0xfdf40400 0x0 0x20>; 1808 }; 1809 1810 qos_isp0_mwo: qos@fdf40500 { 1811 compatible = "rockchip,rk3588-qos", "syscon"; 1812 reg = <0x0 0xfdf40500 0x0 0x20>; 1813 }; 1814 1815 qos_vicap_m0: qos@fdf40600 { 1816 compatible = "rockchip,rk3588-qos", "syscon"; 1817 reg = <0x0 0xfdf40600 0x0 0x20>; 1818 }; 1819 1820 qos_vicap_m1: qos@fdf40800 { 1821 compatible = "rockchip,rk3588-qos", "syscon"; 1822 reg = <0x0 0xfdf40800 0x0 0x20>; 1823 }; 1824 1825 qos_isp1_mwo: qos@fdf41000 { 1826 compatible = "rockchip,rk3588-qos", "syscon"; 1827 reg = <0x0 0xfdf41000 0x0 0x20>; 1828 }; 1829 1830 qos_isp1_mro: qos@fdf41100 { 1831 compatible = "rockchip,rk3588-qos", "syscon"; 1832 reg = <0x0 0xfdf41100 0x0 0x20>; 1833 }; 1834 1835 qos_rkvenc0_m0ro: qos@fdf60000 { 1836 compatible = "rockchip,rk3588-qos", "syscon"; 1837 reg = <0x0 0xfdf60000 0x0 0x20>; 1838 }; 1839 1840 qos_rkvenc0_m1ro: qos@fdf60200 { 1841 compatible = "rockchip,rk3588-qos", "syscon"; 1842 reg = <0x0 0xfdf60200 0x0 0x20>; 1843 }; 1844 1845 qos_rkvenc0_m2wo: qos@fdf60400 { 1846 compatible = "rockchip,rk3588-qos", "syscon"; 1847 reg = <0x0 0xfdf60400 0x0 0x20>; 1848 }; 1849 1850 qos_rkvenc1_m0ro: qos@fdf61000 { 1851 compatible = "rockchip,rk3588-qos", "syscon"; 1852 reg = <0x0 0xfdf61000 0x0 0x20>; 1853 }; 1854 1855 qos_rkvenc1_m1ro: qos@fdf61200 { 1856 compatible = "rockchip,rk3588-qos", "syscon"; 1857 reg = <0x0 0xfdf61200 0x0 0x20>; 1858 }; 1859 1860 qos_rkvenc1_m2wo: qos@fdf61400 { 1861 compatible = "rockchip,rk3588-qos", "syscon"; 1862 reg = <0x0 0xfdf61400 0x0 0x20>; 1863 }; 1864 1865 qos_rkvdec0: qos@fdf62000 { 1866 compatible = "rockchip,rk3588-qos", "syscon"; 1867 reg = <0x0 0xfdf62000 0x0 0x20>; 1868 }; 1869 1870 qos_rkvdec1: qos@fdf63000 { 1871 compatible = "rockchip,rk3588-qos", "syscon"; 1872 reg = <0x0 0xfdf63000 0x0 0x20>; 1873 }; 1874 1875 qos_av1: qos@fdf64000 { 1876 compatible = "rockchip,rk3588-qos", "syscon"; 1877 reg = <0x0 0xfdf64000 0x0 0x20>; 1878 }; 1879 1880 qos_iep: qos@fdf66000 { 1881 compatible = "rockchip,rk3588-qos", "syscon"; 1882 reg = <0x0 0xfdf66000 0x0 0x20>; 1883 }; 1884 1885 qos_jpeg_dec: qos@fdf66200 { 1886 compatible = "rockchip,rk3588-qos", "syscon"; 1887 reg = <0x0 0xfdf66200 0x0 0x20>; 1888 }; 1889 1890 qos_jpeg_enc0: qos@fdf66400 { 1891 compatible = "rockchip,rk3588-qos", "syscon"; 1892 reg = <0x0 0xfdf66400 0x0 0x20>; 1893 }; 1894 1895 qos_jpeg_enc1: qos@fdf66600 { 1896 compatible = "rockchip,rk3588-qos", "syscon"; 1897 reg = <0x0 0xfdf66600 0x0 0x20>; 1898 }; 1899 1900 qos_jpeg_enc2: qos@fdf66800 { 1901 compatible = "rockchip,rk3588-qos", "syscon"; 1902 reg = <0x0 0xfdf66800 0x0 0x20>; 1903 }; 1904 1905 qos_jpeg_enc3: qos@fdf66a00 { 1906 compatible = "rockchip,rk3588-qos", "syscon"; 1907 reg = <0x0 0xfdf66a00 0x0 0x20>; 1908 }; 1909 1910 qos_rga2_mro: qos@fdf66c00 { 1911 compatible = "rockchip,rk3588-qos", "syscon"; 1912 reg = <0x0 0xfdf66c00 0x0 0x20>; 1913 }; 1914 1915 qos_rga2_mwo: qos@fdf66e00 { 1916 compatible = "rockchip,rk3588-qos", "syscon"; 1917 reg = <0x0 0xfdf66e00 0x0 0x20>; 1918 }; 1919 1920 qos_rga3_0: qos@fdf67000 { 1921 compatible = "rockchip,rk3588-qos", "syscon"; 1922 reg = <0x0 0xfdf67000 0x0 0x20>; 1923 }; 1924 1925 qos_vdpu: qos@fdf67200 { 1926 compatible = "rockchip,rk3588-qos", "syscon"; 1927 reg = <0x0 0xfdf67200 0x0 0x20>; 1928 }; 1929 1930 qos_npu1: qos@fdf70000 { 1931 compatible = "rockchip,rk3588-qos", "syscon"; 1932 reg = <0x0 0xfdf70000 0x0 0x20>; 1933 }; 1934 1935 qos_npu2: qos@fdf71000 { 1936 compatible = "rockchip,rk3588-qos", "syscon"; 1937 reg = <0x0 0xfdf71000 0x0 0x20>; 1938 }; 1939 1940 qos_npu0_mwr: qos@fdf72000 { 1941 compatible = "rockchip,rk3588-qos", "syscon"; 1942 reg = <0x0 0xfdf72000 0x0 0x20>; 1943 }; 1944 1945 qos_npu0_mro: qos@fdf72200 { 1946 compatible = "rockchip,rk3588-qos", "syscon"; 1947 reg = <0x0 0xfdf72200 0x0 0x20>; 1948 }; 1949 1950 qos_mcu_npu: qos@fdf72400 { 1951 compatible = "rockchip,rk3588-qos", "syscon"; 1952 reg = <0x0 0xfdf72400 0x0 0x20>; 1953 }; 1954 1955 qos_hdcp0: qos@fdf80000 { 1956 compatible = "rockchip,rk3588-qos", "syscon"; 1957 reg = <0x0 0xfdf80000 0x0 0x20>; 1958 }; 1959 1960 qos_hdcp1: qos@fdf81000 { 1961 compatible = "rockchip,rk3588-qos", "syscon"; 1962 reg = <0x0 0xfdf81000 0x0 0x20>; 1963 }; 1964 1965 qos_hdmirx: qos@fdf81200 { 1966 compatible = "rockchip,rk3588-qos", "syscon"; 1967 reg = <0x0 0xfdf81200 0x0 0x20>; 1968 }; 1969 1970 qos_vop_m0: qos@fdf82000 { 1971 compatible = "rockchip,rk3588-qos", "syscon"; 1972 reg = <0x0 0xfdf82000 0x0 0x20>; 1973 }; 1974 1975 qos_vop_m1: qos@fdf82200 { 1976 compatible = "rockchip,rk3588-qos", "syscon"; 1977 reg = <0x0 0xfdf82200 0x0 0x20>; 1978 }; 1979 1980 dfi: dfi@fe060000 { 1981 reg = <0x00 0xfe060000 0x00 0x10000>; 1982 compatible = "rockchip,rk3588-dfi"; 1983 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, 1984 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, 1985 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, 1986 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1987 rockchip,pmu = <&pmu1grf>; 1988 }; 1989 1990 pcie2x1l1: pcie@fe180000 { 1991 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1992 bus-range = <0x30 0x3f>; 1993 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 1994 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 1995 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; 1996 clock-names = "aclk_mst", "aclk_slv", 1997 "aclk_dbi", "pclk", 1998 "aux", "pipe"; 1999 device_type = "pci"; 2000 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, 2001 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, 2002 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, 2003 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, 2004 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; 2005 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 2006 #interrupt-cells = <1>; 2007 interrupt-map-mask = <0 0 0 7>; 2008 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 2009 <0 0 0 2 &pcie2x1l1_intc 1>, 2010 <0 0 0 3 &pcie2x1l1_intc 2>, 2011 <0 0 0 4 &pcie2x1l1_intc 3>; 2012 linux,pci-domain = <3>; 2013 max-link-speed = <2>; 2014 msi-map = <0x3000 &its0 0x3000 0x1000>; 2015 iommu-map = <0x3000 &mmu600_pcie 0x3000 0x1000>; 2016 num-lanes = <1>; 2017 phys = <&combphy2_psu PHY_TYPE_PCIE>; 2018 phy-names = "pcie-phy"; 2019 power-domains = <&power RK3588_PD_PCIE>; 2020 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, 2021 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, 2022 <0x03000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>; 2023 reg = <0xa 0x40c00000 0x0 0x00400000>, 2024 <0x0 0xfe180000 0x0 0x00010000>, 2025 <0x0 0xf3000000 0x0 0x00100000>; 2026 reg-names = "dbi", "apb", "config"; 2027 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; 2028 reset-names = "pwr", "pipe"; 2029 #address-cells = <3>; 2030 #size-cells = <2>; 2031 status = "disabled"; 2032 2033 pcie2x1l1_intc: legacy-interrupt-controller { 2034 interrupt-controller; 2035 #address-cells = <0>; 2036 #interrupt-cells = <1>; 2037 interrupt-parent = <&gic>; 2038 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; 2039 }; 2040 }; 2041 2042 pcie2x1l2: pcie@fe190000 { 2043 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 2044 bus-range = <0x40 0x4f>; 2045 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 2046 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 2047 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; 2048 clock-names = "aclk_mst", "aclk_slv", 2049 "aclk_dbi", "pclk", 2050 "aux", "pipe"; 2051 device_type = "pci"; 2052 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, 2053 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, 2054 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, 2055 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, 2056 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; 2057 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 2058 #interrupt-cells = <1>; 2059 interrupt-map-mask = <0 0 0 7>; 2060 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 2061 <0 0 0 2 &pcie2x1l2_intc 1>, 2062 <0 0 0 3 &pcie2x1l2_intc 2>, 2063 <0 0 0 4 &pcie2x1l2_intc 3>; 2064 linux,pci-domain = <4>; 2065 max-link-speed = <2>; 2066 msi-map = <0x4000 &its0 0x4000 0x1000>; 2067 iommu-map = <0x4000 &mmu600_pcie 0x4000 0x1000>; 2068 num-lanes = <1>; 2069 phys = <&combphy0_ps PHY_TYPE_PCIE>; 2070 phy-names = "pcie-phy"; 2071 power-domains = <&power RK3588_PD_PCIE>; 2072 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 2073 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, 2074 <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>; 2075 reg = <0xa 0x41000000 0x0 0x00400000>, 2076 <0x0 0xfe190000 0x0 0x00010000>, 2077 <0x0 0xf4000000 0x0 0x00100000>; 2078 reg-names = "dbi", "apb", "config"; 2079 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; 2080 reset-names = "pwr", "pipe"; 2081 #address-cells = <3>; 2082 #size-cells = <2>; 2083 status = "disabled"; 2084 2085 pcie2x1l2_intc: legacy-interrupt-controller { 2086 interrupt-controller; 2087 #address-cells = <0>; 2088 #interrupt-cells = <1>; 2089 interrupt-parent = <&gic>; 2090 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; 2091 }; 2092 }; 2093 2094 gmac1: ethernet@fe1c0000 { 2095 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 2096 reg = <0x0 0xfe1c0000 0x0 0x10000>; 2097 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, 2098 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 2099 interrupt-names = "macirq", "eth_wake_irq"; 2100 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 2101 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 2102 <&cru CLK_GMAC1_PTP_REF>; 2103 clock-names = "stmmaceth", "clk_mac_ref", 2104 "pclk_mac", "aclk_mac", 2105 "ptp_ref"; 2106 power-domains = <&power RK3588_PD_GMAC>; 2107 resets = <&cru SRST_A_GMAC1>; 2108 reset-names = "stmmaceth"; 2109 rockchip,grf = <&sys_grf>; 2110 rockchip,php-grf = <&php_grf>; 2111 snps,axi-config = <&gmac1_stmmac_axi_setup>; 2112 snps,mixed-burst; 2113 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 2114 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 2115 snps,tso; 2116 status = "disabled"; 2117 2118 mdio1: mdio { 2119 compatible = "snps,dwmac-mdio"; 2120 #address-cells = <0x1>; 2121 #size-cells = <0x0>; 2122 }; 2123 2124 gmac1_stmmac_axi_setup: stmmac-axi-config { 2125 snps,blen = <0 0 0 0 16 8 4>; 2126 snps,wr_osr_lmt = <4>; 2127 snps,rd_osr_lmt = <8>; 2128 }; 2129 2130 gmac1_mtl_rx_setup: rx-queues-config { 2131 snps,rx-queues-to-use = <2>; 2132 queue0 {}; 2133 queue1 {}; 2134 }; 2135 2136 gmac1_mtl_tx_setup: tx-queues-config { 2137 snps,tx-queues-to-use = <2>; 2138 queue0 {}; 2139 queue1 {}; 2140 }; 2141 }; 2142 2143 sata0: sata@fe210000 { 2144 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 2145 reg = <0 0xfe210000 0 0x1000>; 2146 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; 2147 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 2148 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, 2149 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; 2150 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 2151 ports-implemented = <0x1>; 2152 #address-cells = <1>; 2153 #size-cells = <0>; 2154 status = "disabled"; 2155 2156 sata-port@0 { 2157 reg = <0>; 2158 hba-port-cap = <HBA_PORT_FBSCP>; 2159 phys = <&combphy0_ps PHY_TYPE_SATA>; 2160 phy-names = "sata-phy"; 2161 snps,rx-ts-max = <32>; 2162 snps,tx-ts-max = <32>; 2163 }; 2164 }; 2165 2166 sata2: sata@fe230000 { 2167 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 2168 reg = <0 0xfe230000 0 0x1000>; 2169 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; 2170 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 2171 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, 2172 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; 2173 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 2174 ports-implemented = <0x1>; 2175 #address-cells = <1>; 2176 #size-cells = <0>; 2177 status = "disabled"; 2178 2179 sata-port@0 { 2180 reg = <0>; 2181 hba-port-cap = <HBA_PORT_FBSCP>; 2182 phys = <&combphy2_psu PHY_TYPE_SATA>; 2183 phy-names = "sata-phy"; 2184 snps,rx-ts-max = <32>; 2185 snps,tx-ts-max = <32>; 2186 }; 2187 }; 2188 2189 sfc: spi@fe2b0000 { 2190 compatible = "rockchip,sfc"; 2191 reg = <0x0 0xfe2b0000 0x0 0x4000>; 2192 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; 2193 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 2194 clock-names = "clk_sfc", "hclk_sfc"; 2195 #address-cells = <1>; 2196 #size-cells = <0>; 2197 status = "disabled"; 2198 }; 2199 2200 sdmmc: mmc@fe2c0000 { 2201 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 2202 reg = <0x0 0xfe2c0000 0x0 0x4000>; 2203 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 2204 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 2205 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 2206 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2207 fifo-depth = <0x100>; 2208 max-frequency = <200000000>; 2209 pinctrl-names = "default"; 2210 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 2211 power-domains = <&power RK3588_PD_SDMMC>; 2212 status = "disabled"; 2213 }; 2214 2215 sdio: mmc@fe2d0000 { 2216 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 2217 reg = <0x00 0xfe2d0000 0x00 0x4000>; 2218 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; 2219 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 2220 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 2221 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2222 fifo-depth = <0x100>; 2223 max-frequency = <200000000>; 2224 pinctrl-names = "default"; 2225 pinctrl-0 = <&sdiom1_pins>; 2226 power-domains = <&power RK3588_PD_SDIO>; 2227 status = "disabled"; 2228 }; 2229 2230 sdhci: mmc@fe2e0000 { 2231 compatible = "rockchip,rk3588-dwcmshc"; 2232 reg = <0x0 0xfe2e0000 0x0 0x10000>; 2233 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 2234 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 2235 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 2236 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 2237 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 2238 <&cru TMCLK_EMMC>; 2239 clock-names = "core", "bus", "axi", "block", "timer"; 2240 max-frequency = <200000000>; 2241 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 2242 <&emmc_cmd>, <&emmc_data_strobe>; 2243 pinctrl-names = "default"; 2244 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 2245 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 2246 <&cru SRST_T_EMMC>; 2247 reset-names = "core", "bus", "axi", "block", "timer"; 2248 supports-cqe; 2249 status = "disabled"; 2250 }; 2251 2252 rng@fe378000 { 2253 compatible = "rockchip,rk3588-rng"; 2254 reg = <0x0 0xfe378000 0x0 0x200>; 2255 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>; 2256 clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; 2257 resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>; 2258 }; 2259 2260 i2s0_8ch: i2s@fe470000 { 2261 compatible = "rockchip,rk3588-i2s-tdm"; 2262 reg = <0x0 0xfe470000 0x0 0x1000>; 2263 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; 2264 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 2265 clock-names = "mclk_tx", "mclk_rx", "hclk"; 2266 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 2267 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 2268 dmas = <&dmac0 0>, <&dmac0 1>; 2269 dma-names = "tx", "rx"; 2270 power-domains = <&power RK3588_PD_AUDIO>; 2271 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 2272 reset-names = "tx-m", "rx-m"; 2273 rockchip,trcm-sync-tx-only; 2274 pinctrl-names = "default"; 2275 pinctrl-0 = <&i2s0_lrck 2276 &i2s0_sclk 2277 &i2s0_sdi0 2278 &i2s0_sdi1 2279 &i2s0_sdi2 2280 &i2s0_sdi3 2281 &i2s0_sdo0 2282 &i2s0_sdo1 2283 &i2s0_sdo2 2284 &i2s0_sdo3>; 2285 #sound-dai-cells = <0>; 2286 status = "disabled"; 2287 }; 2288 2289 i2s1_8ch: i2s@fe480000 { 2290 compatible = "rockchip,rk3588-i2s-tdm"; 2291 reg = <0x0 0xfe480000 0x0 0x1000>; 2292 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; 2293 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 2294 clock-names = "mclk_tx", "mclk_rx", "hclk"; 2295 dmas = <&dmac0 2>, <&dmac0 3>; 2296 dma-names = "tx", "rx"; 2297 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 2298 reset-names = "tx-m", "rx-m"; 2299 rockchip,trcm-sync-tx-only; 2300 pinctrl-names = "default"; 2301 pinctrl-0 = <&i2s1m0_lrck 2302 &i2s1m0_sclk 2303 &i2s1m0_sdi0 2304 &i2s1m0_sdi1 2305 &i2s1m0_sdi2 2306 &i2s1m0_sdi3 2307 &i2s1m0_sdo0 2308 &i2s1m0_sdo1 2309 &i2s1m0_sdo2 2310 &i2s1m0_sdo3>; 2311 #sound-dai-cells = <0>; 2312 status = "disabled"; 2313 }; 2314 2315 i2s2_2ch: i2s@fe490000 { 2316 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 2317 reg = <0x0 0xfe490000 0x0 0x1000>; 2318 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; 2319 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 2320 clock-names = "i2s_clk", "i2s_hclk"; 2321 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 2322 assigned-clock-parents = <&cru PLL_AUPLL>; 2323 dmas = <&dmac1 0>, <&dmac1 1>; 2324 dma-names = "tx", "rx"; 2325 power-domains = <&power RK3588_PD_AUDIO>; 2326 pinctrl-names = "default"; 2327 pinctrl-0 = <&i2s2m1_lrck 2328 &i2s2m1_sclk 2329 &i2s2m1_sdi 2330 &i2s2m1_sdo>; 2331 #sound-dai-cells = <0>; 2332 status = "disabled"; 2333 }; 2334 2335 i2s3_2ch: i2s@fe4a0000 { 2336 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 2337 reg = <0x0 0xfe4a0000 0x0 0x1000>; 2338 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; 2339 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 2340 clock-names = "i2s_clk", "i2s_hclk"; 2341 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 2342 assigned-clock-parents = <&cru PLL_AUPLL>; 2343 dmas = <&dmac1 2>, <&dmac1 3>; 2344 dma-names = "tx", "rx"; 2345 power-domains = <&power RK3588_PD_AUDIO>; 2346 pinctrl-names = "default"; 2347 pinctrl-0 = <&i2s3_lrck 2348 &i2s3_sclk 2349 &i2s3_sdi 2350 &i2s3_sdo>; 2351 #sound-dai-cells = <0>; 2352 status = "disabled"; 2353 }; 2354 2355 spdif_tx0: spdif-tx@fe4e0000 { 2356 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 2357 reg = <0x0 0xfe4e0000 0x0 0x1000>; 2358 assigned-clock-parents = <&cru PLL_AUPLL>; 2359 assigned-clocks = <&cru CLK_SPDIF0_SRC>; 2360 clock-names = "mclk", "hclk"; 2361 clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; 2362 dma-names = "tx"; 2363 dmas = <&dmac0 5>; 2364 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 2365 pinctrl-0 = <&spdif0m0_tx>; 2366 pinctrl-names = "default"; 2367 power-domains = <&power RK3588_PD_AUDIO>; 2368 #sound-dai-cells = <0>; 2369 status = "disabled"; 2370 }; 2371 2372 spdif_tx1: spdif-tx@fe4f0000 { 2373 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 2374 reg = <0x0 0xfe4f0000 0x0 0x1000>; 2375 assigned-clock-parents = <&cru PLL_AUPLL>; 2376 assigned-clocks = <&cru CLK_SPDIF1_SRC>; 2377 clock-names = "mclk", "hclk"; 2378 clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; 2379 dma-names = "tx"; 2380 dmas = <&dmac1 5>; 2381 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 2382 pinctrl-0 = <&spdif1m0_tx>; 2383 pinctrl-names = "default"; 2384 power-domains = <&power RK3588_PD_AUDIO>; 2385 #sound-dai-cells = <0>; 2386 status = "disabled"; 2387 }; 2388 2389 gic: interrupt-controller@fe600000 { 2390 compatible = "arm,gic-v3"; 2391 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 2392 <0x0 0xfe680000 0 0x100000>; /* GICR */ 2393 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 2394 interrupt-controller; 2395 dma-noncoherent; 2396 mbi-alias = <0x0 0xfe610000>; 2397 mbi-ranges = <424 56>; 2398 msi-controller; 2399 ranges; 2400 #address-cells = <2>; 2401 #interrupt-cells = <4>; 2402 #size-cells = <2>; 2403 2404 its0: msi-controller@fe640000 { 2405 compatible = "arm,gic-v3-its"; 2406 reg = <0x0 0xfe640000 0x0 0x20000>; 2407 dma-noncoherent; 2408 msi-controller; 2409 #msi-cells = <1>; 2410 }; 2411 2412 its1: msi-controller@fe660000 { 2413 compatible = "arm,gic-v3-its"; 2414 reg = <0x0 0xfe660000 0x0 0x20000>; 2415 dma-noncoherent; 2416 msi-controller; 2417 #msi-cells = <1>; 2418 }; 2419 2420 ppi-partitions { 2421 ppi_partition0: interrupt-partition-0 { 2422 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 2423 }; 2424 2425 ppi_partition1: interrupt-partition-1 { 2426 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; 2427 }; 2428 }; 2429 }; 2430 2431 dmac0: dma-controller@fea10000 { 2432 compatible = "arm,pl330", "arm,primecell"; 2433 reg = <0x0 0xfea10000 0x0 0x4000>; 2434 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, 2435 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; 2436 arm,pl330-periph-burst; 2437 clocks = <&cru ACLK_DMAC0>; 2438 clock-names = "apb_pclk"; 2439 #dma-cells = <1>; 2440 }; 2441 2442 dmac1: dma-controller@fea30000 { 2443 compatible = "arm,pl330", "arm,primecell"; 2444 reg = <0x0 0xfea30000 0x0 0x4000>; 2445 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, 2446 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; 2447 arm,pl330-periph-burst; 2448 clocks = <&cru ACLK_DMAC1>; 2449 clock-names = "apb_pclk"; 2450 #dma-cells = <1>; 2451 }; 2452 2453 i2c1: i2c@fea90000 { 2454 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2455 reg = <0x0 0xfea90000 0x0 0x1000>; 2456 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 2457 clock-names = "i2c", "pclk"; 2458 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; 2459 pinctrl-0 = <&i2c1m0_xfer>; 2460 pinctrl-names = "default"; 2461 #address-cells = <1>; 2462 #size-cells = <0>; 2463 status = "disabled"; 2464 }; 2465 2466 i2c2: i2c@feaa0000 { 2467 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2468 reg = <0x0 0xfeaa0000 0x0 0x1000>; 2469 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 2470 clock-names = "i2c", "pclk"; 2471 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; 2472 pinctrl-0 = <&i2c2m0_xfer>; 2473 pinctrl-names = "default"; 2474 #address-cells = <1>; 2475 #size-cells = <0>; 2476 status = "disabled"; 2477 }; 2478 2479 i2c3: i2c@feab0000 { 2480 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2481 reg = <0x0 0xfeab0000 0x0 0x1000>; 2482 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 2483 clock-names = "i2c", "pclk"; 2484 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; 2485 pinctrl-0 = <&i2c3m0_xfer>; 2486 pinctrl-names = "default"; 2487 #address-cells = <1>; 2488 #size-cells = <0>; 2489 status = "disabled"; 2490 }; 2491 2492 i2c4: i2c@feac0000 { 2493 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2494 reg = <0x0 0xfeac0000 0x0 0x1000>; 2495 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2496 clock-names = "i2c", "pclk"; 2497 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; 2498 pinctrl-0 = <&i2c4m0_xfer>; 2499 pinctrl-names = "default"; 2500 #address-cells = <1>; 2501 #size-cells = <0>; 2502 status = "disabled"; 2503 }; 2504 2505 i2c5: i2c@fead0000 { 2506 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2507 reg = <0x0 0xfead0000 0x0 0x1000>; 2508 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2509 clock-names = "i2c", "pclk"; 2510 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; 2511 pinctrl-0 = <&i2c5m0_xfer>; 2512 pinctrl-names = "default"; 2513 #address-cells = <1>; 2514 #size-cells = <0>; 2515 status = "disabled"; 2516 }; 2517 2518 timer0: timer@feae0000 { 2519 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 2520 reg = <0x0 0xfeae0000 0x0 0x20>; 2521 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; 2522 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 2523 clock-names = "pclk", "timer"; 2524 }; 2525 2526 wdt: watchdog@feaf0000 { 2527 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; 2528 reg = <0x0 0xfeaf0000 0x0 0x100>; 2529 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 2530 clock-names = "tclk", "pclk"; 2531 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; 2532 }; 2533 2534 spi0: spi@feb00000 { 2535 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2536 reg = <0x0 0xfeb00000 0x0 0x1000>; 2537 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; 2538 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 2539 clock-names = "spiclk", "apb_pclk"; 2540 dmas = <&dmac0 14>, <&dmac0 15>; 2541 dma-names = "tx", "rx"; 2542 num-cs = <2>; 2543 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 2544 pinctrl-names = "default"; 2545 #address-cells = <1>; 2546 #size-cells = <0>; 2547 status = "disabled"; 2548 }; 2549 2550 spi1: spi@feb10000 { 2551 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2552 reg = <0x0 0xfeb10000 0x0 0x1000>; 2553 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; 2554 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 2555 clock-names = "spiclk", "apb_pclk"; 2556 dmas = <&dmac0 16>, <&dmac0 17>; 2557 dma-names = "tx", "rx"; 2558 num-cs = <2>; 2559 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 2560 pinctrl-names = "default"; 2561 #address-cells = <1>; 2562 #size-cells = <0>; 2563 status = "disabled"; 2564 }; 2565 2566 spi2: spi@feb20000 { 2567 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2568 reg = <0x0 0xfeb20000 0x0 0x1000>; 2569 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; 2570 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 2571 clock-names = "spiclk", "apb_pclk"; 2572 dmas = <&dmac1 15>, <&dmac1 16>; 2573 dma-names = "tx", "rx"; 2574 num-cs = <2>; 2575 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 2576 pinctrl-names = "default"; 2577 #address-cells = <1>; 2578 #size-cells = <0>; 2579 status = "disabled"; 2580 }; 2581 2582 spi3: spi@feb30000 { 2583 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2584 reg = <0x0 0xfeb30000 0x0 0x1000>; 2585 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; 2586 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 2587 clock-names = "spiclk", "apb_pclk"; 2588 dmas = <&dmac1 17>, <&dmac1 18>; 2589 dma-names = "tx", "rx"; 2590 num-cs = <2>; 2591 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 2592 pinctrl-names = "default"; 2593 #address-cells = <1>; 2594 #size-cells = <0>; 2595 status = "disabled"; 2596 }; 2597 2598 uart1: serial@feb40000 { 2599 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2600 reg = <0x0 0xfeb40000 0x0 0x100>; 2601 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; 2602 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 2603 clock-names = "baudclk", "apb_pclk"; 2604 dmas = <&dmac0 8>, <&dmac0 9>; 2605 dma-names = "tx", "rx"; 2606 pinctrl-0 = <&uart1m1_xfer>; 2607 pinctrl-names = "default"; 2608 reg-io-width = <4>; 2609 reg-shift = <2>; 2610 status = "disabled"; 2611 }; 2612 2613 uart2: serial@feb50000 { 2614 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2615 reg = <0x0 0xfeb50000 0x0 0x100>; 2616 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; 2617 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 2618 clock-names = "baudclk", "apb_pclk"; 2619 dmas = <&dmac0 10>, <&dmac0 11>; 2620 dma-names = "tx", "rx"; 2621 pinctrl-0 = <&uart2m1_xfer>; 2622 pinctrl-names = "default"; 2623 reg-io-width = <4>; 2624 reg-shift = <2>; 2625 status = "disabled"; 2626 }; 2627 2628 uart3: serial@feb60000 { 2629 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2630 reg = <0x0 0xfeb60000 0x0 0x100>; 2631 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; 2632 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 2633 clock-names = "baudclk", "apb_pclk"; 2634 dmas = <&dmac0 12>, <&dmac0 13>; 2635 dma-names = "tx", "rx"; 2636 pinctrl-0 = <&uart3m1_xfer>; 2637 pinctrl-names = "default"; 2638 reg-io-width = <4>; 2639 reg-shift = <2>; 2640 status = "disabled"; 2641 }; 2642 2643 uart4: serial@feb70000 { 2644 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2645 reg = <0x0 0xfeb70000 0x0 0x100>; 2646 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; 2647 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 2648 clock-names = "baudclk", "apb_pclk"; 2649 dmas = <&dmac1 9>, <&dmac1 10>; 2650 dma-names = "tx", "rx"; 2651 pinctrl-0 = <&uart4m1_xfer>; 2652 pinctrl-names = "default"; 2653 reg-io-width = <4>; 2654 reg-shift = <2>; 2655 status = "disabled"; 2656 }; 2657 2658 uart5: serial@feb80000 { 2659 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2660 reg = <0x0 0xfeb80000 0x0 0x100>; 2661 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; 2662 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2663 clock-names = "baudclk", "apb_pclk"; 2664 dmas = <&dmac1 11>, <&dmac1 12>; 2665 dma-names = "tx", "rx"; 2666 pinctrl-0 = <&uart5m1_xfer>; 2667 pinctrl-names = "default"; 2668 reg-io-width = <4>; 2669 reg-shift = <2>; 2670 status = "disabled"; 2671 }; 2672 2673 uart6: serial@feb90000 { 2674 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2675 reg = <0x0 0xfeb90000 0x0 0x100>; 2676 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; 2677 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2678 clock-names = "baudclk", "apb_pclk"; 2679 dmas = <&dmac1 13>, <&dmac1 14>; 2680 dma-names = "tx", "rx"; 2681 pinctrl-0 = <&uart6m1_xfer>; 2682 pinctrl-names = "default"; 2683 reg-io-width = <4>; 2684 reg-shift = <2>; 2685 status = "disabled"; 2686 }; 2687 2688 uart7: serial@feba0000 { 2689 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2690 reg = <0x0 0xfeba0000 0x0 0x100>; 2691 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; 2692 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2693 clock-names = "baudclk", "apb_pclk"; 2694 dmas = <&dmac2 7>, <&dmac2 8>; 2695 dma-names = "tx", "rx"; 2696 pinctrl-0 = <&uart7m1_xfer>; 2697 pinctrl-names = "default"; 2698 reg-io-width = <4>; 2699 reg-shift = <2>; 2700 status = "disabled"; 2701 }; 2702 2703 uart8: serial@febb0000 { 2704 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2705 reg = <0x0 0xfebb0000 0x0 0x100>; 2706 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; 2707 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2708 clock-names = "baudclk", "apb_pclk"; 2709 dmas = <&dmac2 9>, <&dmac2 10>; 2710 dma-names = "tx", "rx"; 2711 pinctrl-0 = <&uart8m1_xfer>; 2712 pinctrl-names = "default"; 2713 reg-io-width = <4>; 2714 reg-shift = <2>; 2715 status = "disabled"; 2716 }; 2717 2718 uart9: serial@febc0000 { 2719 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2720 reg = <0x0 0xfebc0000 0x0 0x100>; 2721 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; 2722 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2723 clock-names = "baudclk", "apb_pclk"; 2724 dmas = <&dmac2 11>, <&dmac2 12>; 2725 dma-names = "tx", "rx"; 2726 pinctrl-0 = <&uart9m1_xfer>; 2727 pinctrl-names = "default"; 2728 reg-io-width = <4>; 2729 reg-shift = <2>; 2730 status = "disabled"; 2731 }; 2732 2733 pwm4: pwm@febd0000 { 2734 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2735 reg = <0x0 0xfebd0000 0x0 0x10>; 2736 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2737 clock-names = "pwm", "pclk"; 2738 pinctrl-0 = <&pwm4m0_pins>; 2739 pinctrl-names = "default"; 2740 #pwm-cells = <3>; 2741 status = "disabled"; 2742 }; 2743 2744 pwm5: pwm@febd0010 { 2745 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2746 reg = <0x0 0xfebd0010 0x0 0x10>; 2747 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2748 clock-names = "pwm", "pclk"; 2749 pinctrl-0 = <&pwm5m0_pins>; 2750 pinctrl-names = "default"; 2751 #pwm-cells = <3>; 2752 status = "disabled"; 2753 }; 2754 2755 pwm6: pwm@febd0020 { 2756 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2757 reg = <0x0 0xfebd0020 0x0 0x10>; 2758 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2759 clock-names = "pwm", "pclk"; 2760 pinctrl-0 = <&pwm6m0_pins>; 2761 pinctrl-names = "default"; 2762 #pwm-cells = <3>; 2763 status = "disabled"; 2764 }; 2765 2766 pwm7: pwm@febd0030 { 2767 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2768 reg = <0x0 0xfebd0030 0x0 0x10>; 2769 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2770 clock-names = "pwm", "pclk"; 2771 pinctrl-0 = <&pwm7m0_pins>; 2772 pinctrl-names = "default"; 2773 #pwm-cells = <3>; 2774 status = "disabled"; 2775 }; 2776 2777 pwm8: pwm@febe0000 { 2778 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2779 reg = <0x0 0xfebe0000 0x0 0x10>; 2780 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2781 clock-names = "pwm", "pclk"; 2782 pinctrl-0 = <&pwm8m0_pins>; 2783 pinctrl-names = "default"; 2784 #pwm-cells = <3>; 2785 status = "disabled"; 2786 }; 2787 2788 pwm9: pwm@febe0010 { 2789 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2790 reg = <0x0 0xfebe0010 0x0 0x10>; 2791 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2792 clock-names = "pwm", "pclk"; 2793 pinctrl-0 = <&pwm9m0_pins>; 2794 pinctrl-names = "default"; 2795 #pwm-cells = <3>; 2796 status = "disabled"; 2797 }; 2798 2799 pwm10: pwm@febe0020 { 2800 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2801 reg = <0x0 0xfebe0020 0x0 0x10>; 2802 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2803 clock-names = "pwm", "pclk"; 2804 pinctrl-0 = <&pwm10m0_pins>; 2805 pinctrl-names = "default"; 2806 #pwm-cells = <3>; 2807 status = "disabled"; 2808 }; 2809 2810 pwm11: pwm@febe0030 { 2811 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2812 reg = <0x0 0xfebe0030 0x0 0x10>; 2813 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2814 clock-names = "pwm", "pclk"; 2815 pinctrl-0 = <&pwm11m0_pins>; 2816 pinctrl-names = "default"; 2817 #pwm-cells = <3>; 2818 status = "disabled"; 2819 }; 2820 2821 pwm12: pwm@febf0000 { 2822 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2823 reg = <0x0 0xfebf0000 0x0 0x10>; 2824 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2825 clock-names = "pwm", "pclk"; 2826 pinctrl-0 = <&pwm12m0_pins>; 2827 pinctrl-names = "default"; 2828 #pwm-cells = <3>; 2829 status = "disabled"; 2830 }; 2831 2832 pwm13: pwm@febf0010 { 2833 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2834 reg = <0x0 0xfebf0010 0x0 0x10>; 2835 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2836 clock-names = "pwm", "pclk"; 2837 pinctrl-0 = <&pwm13m0_pins>; 2838 pinctrl-names = "default"; 2839 #pwm-cells = <3>; 2840 status = "disabled"; 2841 }; 2842 2843 pwm14: pwm@febf0020 { 2844 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2845 reg = <0x0 0xfebf0020 0x0 0x10>; 2846 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2847 clock-names = "pwm", "pclk"; 2848 pinctrl-0 = <&pwm14m0_pins>; 2849 pinctrl-names = "default"; 2850 #pwm-cells = <3>; 2851 status = "disabled"; 2852 }; 2853 2854 pwm15: pwm@febf0030 { 2855 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2856 reg = <0x0 0xfebf0030 0x0 0x10>; 2857 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2858 clock-names = "pwm", "pclk"; 2859 pinctrl-0 = <&pwm15m0_pins>; 2860 pinctrl-names = "default"; 2861 #pwm-cells = <3>; 2862 status = "disabled"; 2863 }; 2864 2865 thermal_zones: thermal-zones { 2866 /* sensor near the center of the SoC */ 2867 package_thermal: package-thermal { 2868 polling-delay-passive = <0>; 2869 polling-delay = <0>; 2870 thermal-sensors = <&tsadc 0>; 2871 2872 trips { 2873 package_crit: package-crit { 2874 temperature = <115000>; 2875 hysteresis = <0>; 2876 type = "critical"; 2877 }; 2878 }; 2879 }; 2880 2881 /* sensor between A76 cores 0 and 1 */ 2882 bigcore0_thermal: bigcore0-thermal { 2883 polling-delay-passive = <100>; 2884 polling-delay = <0>; 2885 thermal-sensors = <&tsadc 1>; 2886 2887 trips { 2888 bigcore0_alert: bigcore0-alert { 2889 temperature = <85000>; 2890 hysteresis = <2000>; 2891 type = "passive"; 2892 }; 2893 2894 bigcore0_crit: bigcore0-crit { 2895 temperature = <115000>; 2896 hysteresis = <0>; 2897 type = "critical"; 2898 }; 2899 }; 2900 2901 cooling-maps { 2902 map0 { 2903 trip = <&bigcore0_alert>; 2904 cooling-device = 2905 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2906 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2907 }; 2908 }; 2909 }; 2910 2911 /* sensor between A76 cores 2 and 3 */ 2912 bigcore2_thermal: bigcore2-thermal { 2913 polling-delay-passive = <100>; 2914 polling-delay = <0>; 2915 thermal-sensors = <&tsadc 2>; 2916 2917 trips { 2918 bigcore2_alert: bigcore2-alert { 2919 temperature = <85000>; 2920 hysteresis = <2000>; 2921 type = "passive"; 2922 }; 2923 2924 bigcore2_crit: bigcore2-crit { 2925 temperature = <115000>; 2926 hysteresis = <0>; 2927 type = "critical"; 2928 }; 2929 }; 2930 2931 cooling-maps { 2932 map0 { 2933 trip = <&bigcore2_alert>; 2934 cooling-device = 2935 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2936 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2937 }; 2938 }; 2939 }; 2940 2941 /* sensor between the four A55 cores */ 2942 little_core_thermal: littlecore-thermal { 2943 polling-delay-passive = <100>; 2944 polling-delay = <0>; 2945 thermal-sensors = <&tsadc 3>; 2946 2947 trips { 2948 littlecore_alert: littlecore-alert { 2949 temperature = <85000>; 2950 hysteresis = <2000>; 2951 type = "passive"; 2952 }; 2953 2954 littlecore_crit: littlecore-crit { 2955 temperature = <115000>; 2956 hysteresis = <0>; 2957 type = "critical"; 2958 }; 2959 }; 2960 2961 cooling-maps { 2962 map0 { 2963 trip = <&littlecore_alert>; 2964 cooling-device = 2965 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2966 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2967 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2968 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2969 }; 2970 }; 2971 }; 2972 2973 /* sensor near the PD_CENTER power domain */ 2974 center_thermal: center-thermal { 2975 polling-delay-passive = <0>; 2976 polling-delay = <0>; 2977 thermal-sensors = <&tsadc 4>; 2978 2979 trips { 2980 center_crit: center-crit { 2981 temperature = <115000>; 2982 hysteresis = <0>; 2983 type = "critical"; 2984 }; 2985 }; 2986 }; 2987 2988 gpu_thermal: gpu-thermal { 2989 polling-delay-passive = <100>; 2990 polling-delay = <0>; 2991 thermal-sensors = <&tsadc 5>; 2992 2993 trips { 2994 gpu_alert: gpu-alert { 2995 temperature = <85000>; 2996 hysteresis = <2000>; 2997 type = "passive"; 2998 }; 2999 3000 gpu_crit: gpu-crit { 3001 temperature = <115000>; 3002 hysteresis = <0>; 3003 type = "critical"; 3004 }; 3005 }; 3006 3007 cooling-maps { 3008 map0 { 3009 trip = <&gpu_alert>; 3010 cooling-device = 3011 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3012 }; 3013 }; 3014 }; 3015 3016 npu_thermal: npu-thermal { 3017 polling-delay-passive = <0>; 3018 polling-delay = <0>; 3019 thermal-sensors = <&tsadc 6>; 3020 3021 trips { 3022 npu_crit: npu-crit { 3023 temperature = <115000>; 3024 hysteresis = <0>; 3025 type = "critical"; 3026 }; 3027 }; 3028 }; 3029 }; 3030 3031 tsadc: tsadc@fec00000 { 3032 compatible = "rockchip,rk3588-tsadc"; 3033 reg = <0x0 0xfec00000 0x0 0x400>; 3034 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; 3035 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 3036 clock-names = "tsadc", "apb_pclk"; 3037 assigned-clocks = <&cru CLK_TSADC>; 3038 assigned-clock-rates = <2000000>; 3039 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 3040 reset-names = "tsadc-apb", "tsadc"; 3041 rockchip,hw-tshut-temp = <120000>; 3042 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 3043 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 3044 pinctrl-0 = <&tsadc_shut_org>; 3045 pinctrl-1 = <&tsadc_gpio_func>; 3046 pinctrl-names = "default", "sleep"; 3047 #thermal-sensor-cells = <1>; 3048 status = "disabled"; 3049 }; 3050 3051 saradc: adc@fec10000 { 3052 compatible = "rockchip,rk3588-saradc"; 3053 reg = <0x0 0xfec10000 0x0 0x10000>; 3054 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; 3055 #io-channel-cells = <1>; 3056 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 3057 clock-names = "saradc", "apb_pclk"; 3058 resets = <&cru SRST_P_SARADC>; 3059 reset-names = "saradc-apb"; 3060 status = "disabled"; 3061 }; 3062 3063 i2c6: i2c@fec80000 { 3064 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 3065 reg = <0x0 0xfec80000 0x0 0x1000>; 3066 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 3067 clock-names = "i2c", "pclk"; 3068 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; 3069 pinctrl-0 = <&i2c6m0_xfer>; 3070 pinctrl-names = "default"; 3071 #address-cells = <1>; 3072 #size-cells = <0>; 3073 status = "disabled"; 3074 }; 3075 3076 i2c7: i2c@fec90000 { 3077 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 3078 reg = <0x0 0xfec90000 0x0 0x1000>; 3079 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 3080 clock-names = "i2c", "pclk"; 3081 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 3082 pinctrl-0 = <&i2c7m0_xfer>; 3083 pinctrl-names = "default"; 3084 #address-cells = <1>; 3085 #size-cells = <0>; 3086 status = "disabled"; 3087 }; 3088 3089 i2c8: i2c@feca0000 { 3090 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 3091 reg = <0x0 0xfeca0000 0x0 0x1000>; 3092 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 3093 clock-names = "i2c", "pclk"; 3094 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; 3095 pinctrl-0 = <&i2c8m0_xfer>; 3096 pinctrl-names = "default"; 3097 #address-cells = <1>; 3098 #size-cells = <0>; 3099 status = "disabled"; 3100 }; 3101 3102 spi4: spi@fecb0000 { 3103 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 3104 reg = <0x0 0xfecb0000 0x0 0x1000>; 3105 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; 3106 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 3107 clock-names = "spiclk", "apb_pclk"; 3108 dmas = <&dmac2 13>, <&dmac2 14>; 3109 dma-names = "tx", "rx"; 3110 num-cs = <2>; 3111 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 3112 pinctrl-names = "default"; 3113 #address-cells = <1>; 3114 #size-cells = <0>; 3115 status = "disabled"; 3116 }; 3117 3118 otp: efuse@fecc0000 { 3119 compatible = "rockchip,rk3588-otp"; 3120 reg = <0x0 0xfecc0000 0x0 0x400>; 3121 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 3122 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; 3123 clock-names = "otp", "apb_pclk", "phy", "arb"; 3124 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 3125 <&cru SRST_OTPC_ARB>; 3126 reset-names = "otp", "apb", "arb"; 3127 #address-cells = <1>; 3128 #size-cells = <1>; 3129 3130 cpu_code: cpu-code@2 { 3131 reg = <0x02 0x2>; 3132 }; 3133 3134 otp_id: id@7 { 3135 reg = <0x07 0x10>; 3136 }; 3137 3138 cpub0_leakage: cpu-leakage@17 { 3139 reg = <0x17 0x1>; 3140 }; 3141 3142 cpub1_leakage: cpu-leakage@18 { 3143 reg = <0x18 0x1>; 3144 }; 3145 3146 cpul_leakage: cpu-leakage@19 { 3147 reg = <0x19 0x1>; 3148 }; 3149 3150 log_leakage: log-leakage@1a { 3151 reg = <0x1a 0x1>; 3152 }; 3153 3154 gpu_leakage: gpu-leakage@1b { 3155 reg = <0x1b 0x1>; 3156 }; 3157 3158 otp_cpu_version: cpu-version@1c { 3159 reg = <0x1c 0x1>; 3160 bits = <3 3>; 3161 }; 3162 3163 npu_leakage: npu-leakage@28 { 3164 reg = <0x28 0x1>; 3165 }; 3166 3167 codec_leakage: codec-leakage@29 { 3168 reg = <0x29 0x1>; 3169 }; 3170 }; 3171 3172 dmac2: dma-controller@fed10000 { 3173 compatible = "arm,pl330", "arm,primecell"; 3174 reg = <0x0 0xfed10000 0x0 0x4000>; 3175 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, 3176 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; 3177 arm,pl330-periph-burst; 3178 clocks = <&cru ACLK_DMAC2>; 3179 clock-names = "apb_pclk"; 3180 #dma-cells = <1>; 3181 }; 3182 3183 hdptxphy0: phy@fed60000 { 3184 compatible = "rockchip,rk3588-hdptx-phy"; 3185 reg = <0x0 0xfed60000 0x0 0x2000>; 3186 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 3187 clock-names = "ref", "apb"; 3188 #clock-cells = <0>; 3189 #phy-cells = <0>; 3190 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, 3191 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, 3192 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, 3193 <&cru SRST_HDPTX0_LCPLL>; 3194 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 3195 "lcpll"; 3196 rockchip,grf = <&hdptxphy0_grf>; 3197 status = "disabled"; 3198 }; 3199 3200 usbdp_phy0: phy@fed80000 { 3201 compatible = "rockchip,rk3588-usbdp-phy"; 3202 reg = <0x0 0xfed80000 0x0 0x10000>; 3203 #phy-cells = <1>; 3204 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 3205 <&cru CLK_USBDP_PHY0_IMMORTAL>, 3206 <&cru PCLK_USBDPPHY0>, 3207 <&u2phy0>; 3208 clock-names = "refclk", "immortal", "pclk", "utmi"; 3209 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 3210 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 3211 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 3212 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 3213 <&cru SRST_P_USBDPPHY0>; 3214 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 3215 rockchip,u2phy-grf = <&usb2phy0_grf>; 3216 rockchip,usb-grf = <&usb_grf>; 3217 rockchip,usbdpphy-grf = <&usbdpphy0_grf>; 3218 rockchip,vo-grf = <&vo0_grf>; 3219 status = "disabled"; 3220 }; 3221 3222 mipidcphy0: phy@feda0000 { 3223 compatible = "rockchip,rk3588-mipi-dcphy"; 3224 reg = <0x0 0xfeda0000 0x0 0x10000>; 3225 rockchip,grf = <&mipidcphy0_grf>; 3226 clocks = <&cru PCLK_MIPI_DCPHY0>, 3227 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; 3228 clock-names = "pclk", "ref"; 3229 resets = <&cru SRST_M_MIPI_DCPHY0>, 3230 <&cru SRST_P_MIPI_DCPHY0>, 3231 <&cru SRST_P_MIPI_DCPHY0_GRF>, 3232 <&cru SRST_S_MIPI_DCPHY0>; 3233 reset-names = "m_phy", "apb", "grf", "s_phy"; 3234 #phy-cells = <1>; 3235 status = "disabled"; 3236 }; 3237 3238 mipidcphy1: phy@fedb0000 { 3239 compatible = "rockchip,rk3588-mipi-dcphy"; 3240 reg = <0x0 0xfedb0000 0x0 0x10000>; 3241 rockchip,grf = <&mipidcphy1_grf>; 3242 clocks = <&cru PCLK_MIPI_DCPHY1>, 3243 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; 3244 clock-names = "pclk", "ref"; 3245 resets = <&cru SRST_M_MIPI_DCPHY1>, 3246 <&cru SRST_P_MIPI_DCPHY1>, 3247 <&cru SRST_P_MIPI_DCPHY1_GRF>, 3248 <&cru SRST_S_MIPI_DCPHY1>; 3249 reset-names = "m_phy", "apb", "grf", "s_phy"; 3250 #phy-cells = <1>; 3251 status = "disabled"; 3252 }; 3253 3254 csi_dphy0: phy@fedc0000 { 3255 compatible = "rockchip,rk3588-csi-dphy"; 3256 reg = <0x0 0xfedc0000 0x0 0x8000>; 3257 clocks = <&cru PCLK_CSIPHY0>; 3258 clock-names = "pclk"; 3259 #phy-cells = <0>; 3260 resets = <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>; 3261 reset-names = "apb", "phy"; 3262 rockchip,grf = <&csidphy0_grf>; 3263 status = "disabled"; 3264 }; 3265 3266 csi_dphy1: phy@fedc8000 { 3267 compatible = "rockchip,rk3588-csi-dphy"; 3268 reg = <0x0 0xfedc8000 0x0 0x8000>; 3269 clocks = <&cru PCLK_CSIPHY1>; 3270 clock-names = "pclk"; 3271 #phy-cells = <0>; 3272 resets = <&cru SRST_P_CSIPHY1>, <&cru SRST_CSIPHY1>; 3273 reset-names = "apb", "phy"; 3274 rockchip,grf = <&csidphy1_grf>; 3275 status = "disabled"; 3276 }; 3277 3278 combphy0_ps: phy@fee00000 { 3279 compatible = "rockchip,rk3588-naneng-combphy"; 3280 reg = <0x0 0xfee00000 0x0 0x100>; 3281 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, 3282 <&cru PCLK_PHP_ROOT>; 3283 clock-names = "ref", "apb", "pipe"; 3284 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 3285 assigned-clock-rates = <100000000>; 3286 #phy-cells = <1>; 3287 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; 3288 reset-names = "phy", "apb"; 3289 rockchip,pipe-grf = <&php_grf>; 3290 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 3291 status = "disabled"; 3292 }; 3293 3294 combphy2_psu: phy@fee20000 { 3295 compatible = "rockchip,rk3588-naneng-combphy"; 3296 reg = <0x0 0xfee20000 0x0 0x100>; 3297 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, 3298 <&cru PCLK_PHP_ROOT>; 3299 clock-names = "ref", "apb", "pipe"; 3300 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 3301 assigned-clock-rates = <100000000>; 3302 #phy-cells = <1>; 3303 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; 3304 reset-names = "phy", "apb"; 3305 rockchip,pipe-grf = <&php_grf>; 3306 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 3307 status = "disabled"; 3308 }; 3309 3310 system_sram2: sram@ff001000 { 3311 compatible = "mmio-sram"; 3312 reg = <0x0 0xff001000 0x0 0xef000>; 3313 ranges = <0x0 0x0 0xff001000 0xef000>; 3314 #address-cells = <1>; 3315 #size-cells = <1>; 3316 3317 vdec0_sram: codec-sram@0 { 3318 reg = <0x0 0x78000>; 3319 pool; 3320 }; 3321 3322 vdec1_sram: codec-sram@78000 { 3323 reg = <0x78000 0x77000>; 3324 pool; 3325 }; 3326 }; 3327 3328 pinctrl: pinctrl { 3329 compatible = "rockchip,rk3588-pinctrl"; 3330 ranges; 3331 rockchip,grf = <&ioc>; 3332 #address-cells = <2>; 3333 #size-cells = <2>; 3334 3335 gpio0: gpio@fd8a0000 { 3336 compatible = "rockchip,gpio-bank"; 3337 reg = <0x0 0xfd8a0000 0x0 0x100>; 3338 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 3339 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 3340 gpio-controller; 3341 gpio-ranges = <&pinctrl 0 0 32>; 3342 interrupt-controller; 3343 #gpio-cells = <2>; 3344 #interrupt-cells = <2>; 3345 }; 3346 3347 gpio1: gpio@fec20000 { 3348 compatible = "rockchip,gpio-bank"; 3349 reg = <0x0 0xfec20000 0x0 0x100>; 3350 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; 3351 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 3352 gpio-controller; 3353 gpio-ranges = <&pinctrl 0 32 32>; 3354 interrupt-controller; 3355 #gpio-cells = <2>; 3356 #interrupt-cells = <2>; 3357 }; 3358 3359 gpio2: gpio@fec30000 { 3360 compatible = "rockchip,gpio-bank"; 3361 reg = <0x0 0xfec30000 0x0 0x100>; 3362 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; 3363 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 3364 gpio-controller; 3365 gpio-ranges = <&pinctrl 0 64 32>; 3366 interrupt-controller; 3367 #gpio-cells = <2>; 3368 #interrupt-cells = <2>; 3369 }; 3370 3371 gpio3: gpio@fec40000 { 3372 compatible = "rockchip,gpio-bank"; 3373 reg = <0x0 0xfec40000 0x0 0x100>; 3374 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; 3375 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 3376 gpio-controller; 3377 gpio-ranges = <&pinctrl 0 96 32>; 3378 interrupt-controller; 3379 #gpio-cells = <2>; 3380 #interrupt-cells = <2>; 3381 }; 3382 3383 gpio4: gpio@fec50000 { 3384 compatible = "rockchip,gpio-bank"; 3385 reg = <0x0 0xfec50000 0x0 0x100>; 3386 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; 3387 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 3388 gpio-controller; 3389 gpio-ranges = <&pinctrl 0 128 32>; 3390 interrupt-controller; 3391 #gpio-cells = <2>; 3392 #interrupt-cells = <2>; 3393 }; 3394 }; 3395}; 3396 3397#include "rk3588-base-pinctrl.dtsi" 3398