1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_H
3 #define __KVM_X86_VMX_H
4
5 #include <linux/kvm_host.h>
6
7 #include <asm/kvm.h>
8 #include <asm/intel_pt.h>
9 #include <asm/perf_event.h>
10 #include <asm/posted_intr.h>
11
12 #include "capabilities.h"
13 #include "../regs.h"
14 #include "pmu_intel.h"
15 #include "vmcs.h"
16 #include "vmx_ops.h"
17 #include "../cpuid.h"
18 #include "../mmu.h"
19 #include "common.h"
20
21 #ifdef CONFIG_X86_64
22 #define MAX_NR_USER_RETURN_MSRS 7
23 #else
24 #define MAX_NR_USER_RETURN_MSRS 4
25 #endif
26
27 #define MAX_NR_LOADSTORE_MSRS 8
28
29 struct vmx_msrs {
30 unsigned int nr;
31 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS];
32 };
33
34 struct vmx_uret_msr {
35 bool load_into_hardware;
36 u64 data;
37 u64 mask;
38 };
39
40 enum segment_cache_field {
41 SEG_FIELD_SEL = 0,
42 SEG_FIELD_BASE = 1,
43 SEG_FIELD_LIMIT = 2,
44 SEG_FIELD_AR = 3,
45
46 SEG_FIELD_NR = 4
47 };
48
49 #define RTIT_ADDR_RANGE 4
50
51 struct pt_ctx {
52 u64 ctl;
53 u64 status;
54 u64 output_base;
55 u64 output_mask;
56 u64 cr3_match;
57 u64 addr_a[RTIT_ADDR_RANGE];
58 u64 addr_b[RTIT_ADDR_RANGE];
59 };
60
61 struct pt_desc {
62 u64 ctl_bitmask;
63 u32 num_address_ranges;
64 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
65 struct pt_ctx host;
66 struct pt_ctx guest;
67 };
68
69 /*
70 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
71 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
72 */
73 struct nested_vmx {
74 /* Has the level1 guest done vmxon? */
75 bool vmxon;
76 gpa_t vmxon_ptr;
77 bool pml_full;
78
79 /* The guest-physical address of the current VMCS L1 keeps for L2 */
80 gpa_t current_vmptr;
81 /*
82 * Cache of the guest's VMCS, existing outside of guest memory.
83 * Loaded from guest memory during VMPTRLD. Flushed to guest
84 * memory during VMCLEAR and VMPTRLD.
85 */
86 struct vmcs12 *cached_vmcs12;
87 /*
88 * Cache of the guest's shadow VMCS, existing outside of guest
89 * memory. Loaded from guest memory during VM entry. Flushed
90 * to guest memory during VM exit.
91 */
92 struct vmcs12 *cached_shadow_vmcs12;
93
94 /*
95 * GPA to HVA cache for accessing vmcs12->vmcs_link_pointer
96 */
97 struct gfn_to_hva_cache shadow_vmcs12_cache;
98
99 /*
100 * GPA to HVA cache for VMCS12
101 */
102 struct gfn_to_hva_cache vmcs12_cache;
103
104 /*
105 * Indicates if the shadow vmcs or enlightened vmcs must be updated
106 * with the data held by struct vmcs12.
107 */
108 bool need_vmcs12_to_shadow_sync;
109 bool dirty_vmcs12;
110
111 /*
112 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to
113 * changes in MSR bitmap for L1 or switching to a different L2. Note,
114 * this flag can only be used reliably in conjunction with a paravirt L1
115 * which informs L0 whether any changes to MSR bitmap for L2 were done
116 * on its side.
117 */
118 bool force_msr_bitmap_recalc;
119
120 /*
121 * Indicates lazily loaded guest state has not yet been decached from
122 * vmcs02.
123 */
124 bool need_sync_vmcs02_to_vmcs12_rare;
125
126 /*
127 * vmcs02 has been initialized, i.e. state that is constant for
128 * vmcs02 has been written to the backing VMCS. Initialization
129 * is delayed until L1 actually attempts to run a nested VM.
130 */
131 bool vmcs02_initialized;
132
133 /*
134 * Enlightened VMCS has been enabled. It does not mean that L1 has to
135 * use it. However, VMX features available to L1 will be limited based
136 * on what the enlightened VMCS supports.
137 */
138 bool enlightened_vmcs_enabled;
139
140 /* Pending MTF VM-exit into L1. */
141 bool mtf_pending;
142
143 struct loaded_vmcs vmcs02;
144
145 /*
146 * Guest pages referred to in the vmcs02 with host-physical
147 * pointers, so we must keep them pinned while L2 runs.
148 */
149 struct kvm_host_map apic_access_page_map;
150 struct kvm_host_map virtual_apic_map;
151 struct kvm_host_map pi_desc_map;
152
153 struct pi_desc *pi_desc;
154 bool pi_pending;
155 u16 posted_intr_nv;
156
157 struct hrtimer preemption_timer;
158 u64 preemption_timer_deadline;
159 bool has_preemption_timer_deadline;
160 bool preemption_timer_expired;
161
162 /*
163 * Used to restore L1's CR3 if hardware detects a VM-Fail Consistency
164 * Check that KVM does not, in which case KVM needs to unwind CR3 back
165 * to its pre-VM-Enter state, NOT to vmcs01.HOST_CR3.
166 */
167 unsigned long pre_vmenter_cr3;
168
169 /*
170 * Used to snapshot MSRs that are conditionally loaded on VM-Enter in
171 * order to propagate the guest's pre-VM-Enter value into vmcs02. For
172 * emulation of VMLAUNCH/VMRESUME, the snapshot will be of L1's value.
173 * For KVM_SET_NESTED_STATE, the snapshot is of L2's value, _if_
174 * userspace restores MSRs before nested state. If userspace restores
175 * MSRs after nested state, the snapshot holds garbage, but KVM can't
176 * detect that, and the garbage value in vmcs02 will be overwritten by
177 * MSR restoration in any case.
178 */
179 u64 pre_vmenter_debugctl;
180 u64 pre_vmenter_bndcfgs;
181 u64 pre_vmenter_s_cet;
182 u64 pre_vmenter_ssp;
183 u64 pre_vmenter_ssp_tbl;
184
185 u16 vpid02;
186 u16 last_vpid;
187
188 int tsc_autostore_slot;
189 struct nested_vmx_msrs msrs;
190
191 /* SMM related state */
192 struct {
193 /* in VMX operation on SMM entry? */
194 bool vmxon;
195 /* in guest mode on SMM entry? */
196 bool guest_mode;
197 } smm;
198
199 #ifdef CONFIG_KVM_HYPERV
200 gpa_t hv_evmcs_vmptr;
201 struct kvm_host_map hv_evmcs_map;
202 struct hv_enlightened_vmcs *hv_evmcs;
203 #endif
204 };
205
206 struct vcpu_vmx {
207 struct kvm_vcpu vcpu;
208 struct vcpu_vt vt;
209 u8 fail;
210 u8 x2apic_msr_bitmap_mode;
211
212 u32 idt_vectoring_info;
213 ulong rflags;
214
215 /*
216 * User return MSRs are always emulated when enabled in the guest, but
217 * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside
218 * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to
219 * be loaded into hardware if those conditions aren't met.
220 */
221 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS];
222 bool guest_uret_msrs_loaded;
223 #ifdef CONFIG_X86_64
224 u64 msr_guest_kernel_gs_base;
225 #endif
226
227 u64 spec_ctrl;
228 u32 msr_ia32_umwait_control;
229
230 /*
231 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
232 * non-nested (L1) guest, it always points to vmcs01. For a nested
233 * guest (L2), it points to a different VMCS.
234 */
235 struct loaded_vmcs vmcs01;
236 struct loaded_vmcs *loaded_vmcs;
237
238 struct msr_autoload {
239 struct vmx_msrs guest;
240 struct vmx_msrs host;
241 } msr_autoload;
242
243 struct vmx_msrs msr_autostore;
244
245 struct {
246 int vm86_active;
247 ulong save_rflags;
248 struct kvm_segment segs[8];
249 } rmode;
250 struct {
251 u32 bitmask; /* 4 bits per segment (1 bit per field) */
252 struct kvm_save_segment {
253 u16 selector;
254 unsigned long base;
255 u32 limit;
256 u32 ar;
257 } seg[8];
258 } segment_cache;
259 int vpid;
260
261 /* Support for a guest hypervisor (nested VMX) */
262 struct nested_vmx nested;
263
264 /* Dynamic PLE window. */
265 unsigned int ple_window;
266 bool ple_window_dirty;
267
268 /* Support for PML */
269 #define PML_LOG_NR_ENTRIES 512
270 /* PML is written backwards: this is the first entry written by the CPU */
271 #define PML_HEAD_INDEX (PML_LOG_NR_ENTRIES-1)
272
273 struct page *pml_pg;
274
275 /* apic deadline value in host tsc */
276 u64 hv_deadline_tsc;
277
278 /*
279 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
280 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
281 * in msr_ia32_feature_control_valid_bits.
282 */
283 u64 msr_ia32_feature_control;
284 u64 msr_ia32_feature_control_valid_bits;
285 /* SGX Launch Control public key hash */
286 u64 msr_ia32_sgxlepubkeyhash[4];
287 u64 msr_ia32_mcu_opt_ctrl;
288 bool disable_fb_clear;
289
290 struct pt_desc pt_desc;
291 struct lbr_desc lbr_desc;
292
293 /* ve_info must be page aligned. */
294 struct vmx_ve_information *ve_info;
295 };
296
297 struct kvm_vmx {
298 struct kvm kvm;
299
300 unsigned int tss_addr;
301 bool ept_identity_pagetable_done;
302 gpa_t ept_identity_map_addr;
303 /* Posted Interrupt Descriptor (PID) table for IPI virtualization */
304 u64 *pid_table;
305 };
306
to_vt(struct kvm_vcpu * vcpu)307 static __always_inline struct vcpu_vt *to_vt(struct kvm_vcpu *vcpu)
308 {
309 return &(container_of(vcpu, struct vcpu_vmx, vcpu)->vt);
310 }
311
vt_to_vcpu(struct vcpu_vt * vt)312 static __always_inline struct kvm_vcpu *vt_to_vcpu(struct vcpu_vt *vt)
313 {
314 return &(container_of(vt, struct vcpu_vmx, vt)->vcpu);
315 }
316
vmx_get_exit_reason(struct kvm_vcpu * vcpu)317 static __always_inline union vmx_exit_reason vmx_get_exit_reason(struct kvm_vcpu *vcpu)
318 {
319 return to_vt(vcpu)->exit_reason;
320 }
321
vmx_get_exit_qual(struct kvm_vcpu * vcpu)322 static __always_inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu)
323 {
324 struct vcpu_vt *vt = to_vt(vcpu);
325
326 if (!kvm_register_test_and_mark_available(vcpu, VCPU_REG_EXIT_INFO_1) &&
327 !WARN_ON_ONCE(is_td_vcpu(vcpu)))
328 vt->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
329
330 return vt->exit_qualification;
331 }
332
vmx_get_intr_info(struct kvm_vcpu * vcpu)333 static __always_inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu)
334 {
335 struct vcpu_vt *vt = to_vt(vcpu);
336
337 if (!kvm_register_test_and_mark_available(vcpu, VCPU_REG_EXIT_INFO_2) &&
338 !WARN_ON_ONCE(is_td_vcpu(vcpu)))
339 vt->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
340
341 return vt->exit_intr_info;
342 }
343
344 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu);
345 int allocate_vpid(void);
346 void free_vpid(int vpid);
347 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
348 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
349 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
350 unsigned long fs_base, unsigned long gs_base);
351 int vmx_get_cpl(struct kvm_vcpu *vcpu);
352 int vmx_get_cpl_no_cache(struct kvm_vcpu *vcpu);
353 bool vmx_emulation_required(struct kvm_vcpu *vcpu);
354 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
355 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
356 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
357 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
358 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
359 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
360 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
361 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
362 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
363 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
364 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
365
366 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu);
367 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu);
368 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu);
369 bool __vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
370 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
371 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
372 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
373 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
374 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr);
375 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu);
376 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
377 unsigned int __vmx_vcpu_enter_flags(struct vcpu_vmx *vmx);
378 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned int flags);
379 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu);
380
381 void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type, bool set);
382
vmx_disable_intercept_for_msr(struct kvm_vcpu * vcpu,u32 msr,int type)383 static inline void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu,
384 u32 msr, int type)
385 {
386 vmx_set_intercept_for_msr(vcpu, msr, type, false);
387 }
388
vmx_enable_intercept_for_msr(struct kvm_vcpu * vcpu,u32 msr,int type)389 static inline void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu,
390 u32 msr, int type)
391 {
392 vmx_set_intercept_for_msr(vcpu, msr, type, true);
393 }
394
395 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu);
396 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu);
397
398 gva_t vmx_get_untagged_addr(struct kvm_vcpu *vcpu, gva_t gva, unsigned int flags);
399
400 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu);
401
402 u64 vmx_get_supported_debugctl(struct kvm_vcpu *vcpu, bool host_initiated);
403 bool vmx_is_valid_debugctl(struct kvm_vcpu *vcpu, u64 data, bool host_initiated);
404
405 #define VMX_HOST_OWNED_DEBUGCTL_BITS (DEBUGCTLMSR_FREEZE_IN_SMM)
406
vmx_guest_debugctl_write(struct kvm_vcpu * vcpu,u64 val)407 static inline void vmx_guest_debugctl_write(struct kvm_vcpu *vcpu, u64 val)
408 {
409 WARN_ON_ONCE(val & VMX_HOST_OWNED_DEBUGCTL_BITS);
410
411 val |= vcpu->arch.host_debugctl & VMX_HOST_OWNED_DEBUGCTL_BITS;
412 vmcs_write64(GUEST_IA32_DEBUGCTL, val);
413 }
414
vmx_guest_debugctl_read(void)415 static inline u64 vmx_guest_debugctl_read(void)
416 {
417 return vmcs_read64(GUEST_IA32_DEBUGCTL) & ~VMX_HOST_OWNED_DEBUGCTL_BITS;
418 }
419
vmx_reload_guest_debugctl(struct kvm_vcpu * vcpu)420 static inline void vmx_reload_guest_debugctl(struct kvm_vcpu *vcpu)
421 {
422 u64 val = vmcs_read64(GUEST_IA32_DEBUGCTL);
423
424 if (!((val ^ vcpu->arch.host_debugctl) & VMX_HOST_OWNED_DEBUGCTL_BITS))
425 return;
426
427 vmx_guest_debugctl_write(vcpu, val & ~VMX_HOST_OWNED_DEBUGCTL_BITS);
428 }
429
430 /*
431 * Note, early Intel manuals have the write-low and read-high bitmap offsets
432 * the wrong way round. The bitmaps control MSRs 0x00000000-0x00001fff and
433 * 0xc0000000-0xc0001fff. The former (low) uses bytes 0-0x3ff for reads and
434 * 0x800-0xbff for writes. The latter (high) uses 0x400-0x7ff for reads and
435 * 0xc00-0xfff for writes. MSRs not covered by either of the ranges always
436 * VM-Exit.
437 */
438 #define __BUILD_VMX_MSR_BITMAP_HELPER(rtype, action, bitop, access, base) \
439 static inline rtype vmx_##action##_msr_bitmap_##access(unsigned long *bitmap, \
440 u32 msr) \
441 { \
442 int f = sizeof(unsigned long); \
443 \
444 if (msr <= 0x1fff) \
445 return bitop##_bit(msr, bitmap + base / f); \
446 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) \
447 return bitop##_bit(msr & 0x1fff, bitmap + (base + 0x400) / f); \
448 return (rtype)true; \
449 }
450 #define BUILD_VMX_MSR_BITMAP_HELPERS(ret_type, action, bitop) \
451 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0x0) \
452 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 0x800)
453
BUILD_VMX_MSR_BITMAP_HELPERS(bool,test,test)454 BUILD_VMX_MSR_BITMAP_HELPERS(bool, test, test)
455 BUILD_VMX_MSR_BITMAP_HELPERS(void, clear, __clear)
456 BUILD_VMX_MSR_BITMAP_HELPERS(void, set, __set)
457
458 static inline u8 vmx_get_rvi(void)
459 {
460 return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
461 }
462
463 #define __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \
464 (VM_ENTRY_LOAD_DEBUG_CONTROLS)
465 #ifdef CONFIG_X86_64
466 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \
467 (__KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS | \
468 VM_ENTRY_IA32E_MODE)
469 #else
470 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \
471 __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS
472 #endif
473 #define KVM_OPTIONAL_VMX_VM_ENTRY_CONTROLS \
474 (VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | \
475 VM_ENTRY_LOAD_IA32_PAT | \
476 VM_ENTRY_LOAD_IA32_EFER | \
477 VM_ENTRY_LOAD_BNDCFGS | \
478 VM_ENTRY_PT_CONCEAL_PIP | \
479 VM_ENTRY_LOAD_IA32_RTIT_CTL | \
480 VM_ENTRY_LOAD_CET_STATE)
481
482 #define __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \
483 (VM_EXIT_SAVE_DEBUG_CONTROLS | \
484 VM_EXIT_ACK_INTR_ON_EXIT)
485 #ifdef CONFIG_X86_64
486 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \
487 (__KVM_REQUIRED_VMX_VM_EXIT_CONTROLS | \
488 VM_EXIT_HOST_ADDR_SPACE_SIZE)
489 #else
490 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \
491 __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS
492 #endif
493 #define KVM_OPTIONAL_VMX_VM_EXIT_CONTROLS \
494 (VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | \
495 VM_EXIT_SAVE_IA32_PAT | \
496 VM_EXIT_LOAD_IA32_PAT | \
497 VM_EXIT_SAVE_IA32_EFER | \
498 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | \
499 VM_EXIT_LOAD_IA32_EFER | \
500 VM_EXIT_CLEAR_BNDCFGS | \
501 VM_EXIT_PT_CONCEAL_PIP | \
502 VM_EXIT_CLEAR_IA32_RTIT_CTL | \
503 VM_EXIT_LOAD_CET_STATE | \
504 VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL)
505
506 #define KVM_REQUIRED_VMX_PIN_BASED_VM_EXEC_CONTROL \
507 (PIN_BASED_EXT_INTR_MASK | \
508 PIN_BASED_NMI_EXITING)
509 #define KVM_OPTIONAL_VMX_PIN_BASED_VM_EXEC_CONTROL \
510 (PIN_BASED_VIRTUAL_NMIS | \
511 PIN_BASED_POSTED_INTR | \
512 PIN_BASED_VMX_PREEMPTION_TIMER)
513
514 #define __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \
515 (CPU_BASED_HLT_EXITING | \
516 CPU_BASED_CR3_LOAD_EXITING | \
517 CPU_BASED_CR3_STORE_EXITING | \
518 CPU_BASED_UNCOND_IO_EXITING | \
519 CPU_BASED_MOV_DR_EXITING | \
520 CPU_BASED_USE_TSC_OFFSETTING | \
521 CPU_BASED_MWAIT_EXITING | \
522 CPU_BASED_MONITOR_EXITING | \
523 CPU_BASED_INVLPG_EXITING | \
524 CPU_BASED_RDPMC_EXITING | \
525 CPU_BASED_INTR_WINDOW_EXITING)
526
527 #ifdef CONFIG_X86_64
528 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \
529 (__KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL | \
530 CPU_BASED_CR8_LOAD_EXITING | \
531 CPU_BASED_CR8_STORE_EXITING)
532 #else
533 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \
534 __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL
535 #endif
536
537 #define KVM_OPTIONAL_VMX_CPU_BASED_VM_EXEC_CONTROL \
538 (CPU_BASED_RDTSC_EXITING | \
539 CPU_BASED_TPR_SHADOW | \
540 CPU_BASED_USE_IO_BITMAPS | \
541 CPU_BASED_MONITOR_TRAP_FLAG | \
542 CPU_BASED_USE_MSR_BITMAPS | \
543 CPU_BASED_NMI_WINDOW_EXITING | \
544 CPU_BASED_PAUSE_EXITING | \
545 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS | \
546 CPU_BASED_ACTIVATE_TERTIARY_CONTROLS)
547
548 #define KVM_REQUIRED_VMX_SECONDARY_VM_EXEC_CONTROL 0
549 #define KVM_OPTIONAL_VMX_SECONDARY_VM_EXEC_CONTROL \
550 (SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | \
551 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | \
552 SECONDARY_EXEC_WBINVD_EXITING | \
553 SECONDARY_EXEC_ENABLE_VPID | \
554 SECONDARY_EXEC_ENABLE_EPT | \
555 SECONDARY_EXEC_UNRESTRICTED_GUEST | \
556 SECONDARY_EXEC_PAUSE_LOOP_EXITING | \
557 SECONDARY_EXEC_DESC | \
558 SECONDARY_EXEC_ENABLE_RDTSCP | \
559 SECONDARY_EXEC_ENABLE_INVPCID | \
560 SECONDARY_EXEC_APIC_REGISTER_VIRT | \
561 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | \
562 SECONDARY_EXEC_SHADOW_VMCS | \
563 SECONDARY_EXEC_ENABLE_XSAVES | \
564 SECONDARY_EXEC_RDSEED_EXITING | \
565 SECONDARY_EXEC_RDRAND_EXITING | \
566 SECONDARY_EXEC_ENABLE_PML | \
567 SECONDARY_EXEC_TSC_SCALING | \
568 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | \
569 SECONDARY_EXEC_PT_USE_GPA | \
570 SECONDARY_EXEC_PT_CONCEAL_VMX | \
571 SECONDARY_EXEC_ENABLE_VMFUNC | \
572 SECONDARY_EXEC_BUS_LOCK_DETECTION | \
573 SECONDARY_EXEC_NOTIFY_VM_EXITING | \
574 SECONDARY_EXEC_MODE_BASED_EPT_EXEC | \
575 SECONDARY_EXEC_ENCLS_EXITING | \
576 SECONDARY_EXEC_EPT_VIOLATION_VE)
577
578 #define KVM_REQUIRED_VMX_TERTIARY_VM_EXEC_CONTROL 0
579 #define KVM_OPTIONAL_VMX_TERTIARY_VM_EXEC_CONTROL \
580 (TERTIARY_EXEC_IPI_VIRT)
581
582 #define BUILD_CONTROLS_SHADOW(lname, uname, bits) \
583 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u##bits val) \
584 { \
585 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
586 vmcs_write##bits(uname, val); \
587 vmx->loaded_vmcs->controls_shadow.lname = val; \
588 } \
589 } \
590 static inline u##bits __##lname##_controls_get(struct loaded_vmcs *vmcs) \
591 { \
592 return vmcs->controls_shadow.lname; \
593 } \
594 static inline u##bits lname##_controls_get(struct vcpu_vmx *vmx) \
595 { \
596 return __##lname##_controls_get(vmx->loaded_vmcs); \
597 } \
598 static __always_inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u##bits val) \
599 { \
600 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \
601 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \
602 } \
603 static __always_inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u##bits val) \
604 { \
605 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \
606 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \
607 } \
608 static __always_inline void lname##_controls_changebit(struct vcpu_vmx *vmx, u##bits val, \
609 bool set) \
610 { \
611 if (set) \
612 lname##_controls_setbit(vmx, val); \
613 else \
614 lname##_controls_clearbit(vmx, val); \
615 }
616 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32)
617 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32)
618 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL, 32)
619 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL, 32)
620 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL, 32)
621 BUILD_CONTROLS_SHADOW(tertiary_exec, TERTIARY_VM_EXEC_CONTROL, 64)
622
623 /*
624 * VMX_REGS_LAZY_LOAD_SET - The set of registers that will be updated in the
625 * cache on demand. Other registers not listed here are synced to
626 * the cache immediately after VM-Exit.
627 */
628 #define VMX_REGS_LAZY_LOAD_SET (BIT(VCPU_REGS_RSP) | \
629 BIT(VCPU_REG_RIP) | \
630 BIT(VCPU_REG_RFLAGS) | \
631 BIT(VCPU_REG_PDPTR) | \
632 BIT(VCPU_REG_SEGMENTS) | \
633 BIT(VCPU_REG_CR0) | \
634 BIT(VCPU_REG_CR3) | \
635 BIT(VCPU_REG_CR4) | \
636 BIT(VCPU_REG_EXIT_INFO_1) | \
637 BIT(VCPU_REG_EXIT_INFO_2))
638
vmx_l1_guest_owned_cr0_bits(void)639 static inline unsigned long vmx_l1_guest_owned_cr0_bits(void)
640 {
641 unsigned long bits = KVM_POSSIBLE_CR0_GUEST_BITS;
642
643 /*
644 * CR0.WP needs to be intercepted when KVM is shadowing legacy paging
645 * in order to construct shadow PTEs with the correct protections.
646 * Note! CR0.WP technically can be passed through to the guest if
647 * paging is disabled, but checking CR0.PG would generate a cyclical
648 * dependency of sorts due to forcing the caller to ensure CR0 holds
649 * the correct value prior to determining which CR0 bits can be owned
650 * by L1. Keep it simple and limit the optimization to EPT.
651 */
652 if (!enable_ept)
653 bits &= ~X86_CR0_WP;
654 return bits;
655 }
656
to_kvm_vmx(struct kvm * kvm)657 static __always_inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
658 {
659 return container_of(kvm, struct kvm_vmx, kvm);
660 }
661
to_vmx(struct kvm_vcpu * vcpu)662 static __always_inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
663 {
664 return container_of(vcpu, struct vcpu_vmx, vcpu);
665 }
666
667 void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu);
668 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu);
669 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu);
670
671 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
672 void free_vmcs(struct vmcs *vmcs);
673 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
674 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
675
alloc_vmcs(bool shadow)676 static inline struct vmcs *alloc_vmcs(bool shadow)
677 {
678 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
679 GFP_KERNEL_ACCOUNT);
680 }
681
vmx_has_waitpkg(struct vcpu_vmx * vmx)682 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
683 {
684 return secondary_exec_controls_get(vmx) &
685 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
686 }
687
vmx_need_pf_intercept(struct kvm_vcpu * vcpu)688 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu)
689 {
690 if (!enable_ept)
691 return true;
692
693 return allow_smaller_maxphyaddr &&
694 cpuid_maxphyaddr(vcpu) < kvm_host.maxphyaddr;
695 }
696
is_unrestricted_guest(struct kvm_vcpu * vcpu)697 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu)
698 {
699 return enable_unrestricted_guest && (!is_guest_mode(vcpu) ||
700 (secondary_exec_controls_get(to_vmx(vcpu)) &
701 SECONDARY_EXEC_UNRESTRICTED_GUEST));
702 }
703
704 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu);
vmx_guest_state_valid(struct kvm_vcpu * vcpu)705 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu)
706 {
707 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu);
708 }
709
710 void dump_vmcs(struct kvm_vcpu *vcpu);
711
vmx_get_instr_info_reg(u32 vmx_instr_info)712 static inline int vmx_get_instr_info_reg(u32 vmx_instr_info)
713 {
714 return (vmx_instr_info >> 3) & 0xf;
715 }
716
vmx_get_instr_info_reg2(u32 vmx_instr_info)717 static inline int vmx_get_instr_info_reg2(u32 vmx_instr_info)
718 {
719 return (vmx_instr_info >> 28) & 0xf;
720 }
721
vmx_can_use_ipiv(struct kvm_vcpu * vcpu)722 static inline bool vmx_can_use_ipiv(struct kvm_vcpu *vcpu)
723 {
724 return lapic_in_kernel(vcpu) && enable_ipiv;
725 }
726
vmx_segment_cache_clear(struct vcpu_vmx * vmx)727 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
728 {
729 vmx->segment_cache.bitmask = 0;
730 }
731
732 int vmx_init(void);
733 void vmx_exit(void);
734
735 #endif /* __KVM_X86_VMX_H */
736