1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /**************************************************************************
3 *
4 * Copyright 2009-2023 VMware, Inc., Palo Alto, CA., USA
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include "vmwgfx_drv.h"
30
31 #include "vmwgfx_bo.h"
32 #include "vmwgfx_binding.h"
33 #include "vmwgfx_devcaps.h"
34 #include "vmwgfx_mksstat.h"
35 #include "vmwgfx_vkms.h"
36 #include "ttm_object.h"
37
38 #include <drm/drm_client_setup.h>
39 #include <drm/drm_drv.h>
40 #include <drm/drm_fbdev_ttm.h>
41 #include <drm/drm_gem_ttm_helper.h>
42 #include <drm/drm_ioctl.h>
43 #include <drm/drm_module.h>
44 #include <drm/drm_sysfs.h>
45 #include <drm/ttm/ttm_range_manager.h>
46 #include <drm/ttm/ttm_placement.h>
47 #include <generated/utsrelease.h>
48
49 #ifdef CONFIG_X86
50 #include <asm/hypervisor.h>
51 #endif
52
53 #include <linux/aperture.h>
54 #include <linux/cc_platform.h>
55 #include <linux/dma-mapping.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/version.h>
59 #include <linux/vmalloc.h>
60
61 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
62
63 /*
64 * Fully encoded drm commands. Might move to vmw_drm.h
65 */
66
67 #define DRM_IOCTL_VMW_GET_PARAM \
68 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
69 struct drm_vmw_getparam_arg)
70 #define DRM_IOCTL_VMW_ALLOC_DMABUF \
71 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
72 union drm_vmw_alloc_dmabuf_arg)
73 #define DRM_IOCTL_VMW_UNREF_DMABUF \
74 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
75 struct drm_vmw_unref_dmabuf_arg)
76 #define DRM_IOCTL_VMW_CURSOR_BYPASS \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
78 struct drm_vmw_cursor_bypass_arg)
79
80 #define DRM_IOCTL_VMW_CONTROL_STREAM \
81 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
82 struct drm_vmw_control_stream_arg)
83 #define DRM_IOCTL_VMW_CLAIM_STREAM \
84 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
85 struct drm_vmw_stream_arg)
86 #define DRM_IOCTL_VMW_UNREF_STREAM \
87 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
88 struct drm_vmw_stream_arg)
89
90 #define DRM_IOCTL_VMW_CREATE_CONTEXT \
91 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
92 struct drm_vmw_context_arg)
93 #define DRM_IOCTL_VMW_UNREF_CONTEXT \
94 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
95 struct drm_vmw_context_arg)
96 #define DRM_IOCTL_VMW_CREATE_SURFACE \
97 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
98 union drm_vmw_surface_create_arg)
99 #define DRM_IOCTL_VMW_UNREF_SURFACE \
100 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
101 struct drm_vmw_surface_arg)
102 #define DRM_IOCTL_VMW_REF_SURFACE \
103 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
104 union drm_vmw_surface_reference_arg)
105 #define DRM_IOCTL_VMW_EXECBUF \
106 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
107 struct drm_vmw_execbuf_arg)
108 #define DRM_IOCTL_VMW_GET_3D_CAP \
109 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
110 struct drm_vmw_get_3d_cap_arg)
111 #define DRM_IOCTL_VMW_FENCE_WAIT \
112 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
113 struct drm_vmw_fence_wait_arg)
114 #define DRM_IOCTL_VMW_FENCE_SIGNALED \
115 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
116 struct drm_vmw_fence_signaled_arg)
117 #define DRM_IOCTL_VMW_FENCE_UNREF \
118 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
119 struct drm_vmw_fence_arg)
120 #define DRM_IOCTL_VMW_FENCE_EVENT \
121 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
122 struct drm_vmw_fence_event_arg)
123 #define DRM_IOCTL_VMW_PRESENT \
124 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
125 struct drm_vmw_present_arg)
126 #define DRM_IOCTL_VMW_PRESENT_READBACK \
127 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
128 struct drm_vmw_present_readback_arg)
129 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \
130 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
131 struct drm_vmw_update_layout_arg)
132 #define DRM_IOCTL_VMW_CREATE_SHADER \
133 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
134 struct drm_vmw_shader_create_arg)
135 #define DRM_IOCTL_VMW_UNREF_SHADER \
136 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
137 struct drm_vmw_shader_arg)
138 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
139 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
140 union drm_vmw_gb_surface_create_arg)
141 #define DRM_IOCTL_VMW_GB_SURFACE_REF \
142 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
143 union drm_vmw_gb_surface_reference_arg)
144 #define DRM_IOCTL_VMW_SYNCCPU \
145 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
146 struct drm_vmw_synccpu_arg)
147 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \
148 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \
149 struct drm_vmw_context_arg)
150 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \
151 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \
152 union drm_vmw_gb_surface_create_ext_arg)
153 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \
154 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \
155 union drm_vmw_gb_surface_reference_ext_arg)
156 #define DRM_IOCTL_VMW_MSG \
157 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \
158 struct drm_vmw_msg_arg)
159 #define DRM_IOCTL_VMW_MKSSTAT_RESET \
160 DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET)
161 #define DRM_IOCTL_VMW_MKSSTAT_ADD \
162 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \
163 struct drm_vmw_mksstat_add_arg)
164 #define DRM_IOCTL_VMW_MKSSTAT_REMOVE \
165 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \
166 struct drm_vmw_mksstat_remove_arg)
167
168 /*
169 * Ioctl definitions.
170 */
171
172 static const struct drm_ioctl_desc vmw_ioctls[] = {
173 DRM_IOCTL_DEF_DRV(VMW_GET_PARAM, vmw_getparam_ioctl,
174 DRM_RENDER_ALLOW),
175 DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF, vmw_gem_object_create_ioctl,
176 DRM_RENDER_ALLOW),
177 DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl,
178 DRM_RENDER_ALLOW),
179 DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS,
180 vmw_kms_cursor_bypass_ioctl,
181 DRM_MASTER),
182
183 DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
184 DRM_MASTER),
185 DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
186 DRM_MASTER),
187 DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
188 DRM_MASTER),
189
190 DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
191 DRM_RENDER_ALLOW),
192 DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
193 DRM_RENDER_ALLOW),
194 DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
195 DRM_RENDER_ALLOW),
196 DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
197 DRM_RENDER_ALLOW),
198 DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
199 DRM_RENDER_ALLOW),
200 DRM_IOCTL_DEF_DRV(VMW_EXECBUF, vmw_execbuf_ioctl,
201 DRM_RENDER_ALLOW),
202 DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
203 DRM_RENDER_ALLOW),
204 DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED,
205 vmw_fence_obj_signaled_ioctl,
206 DRM_RENDER_ALLOW),
207 DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
208 DRM_RENDER_ALLOW),
209 DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
210 DRM_RENDER_ALLOW),
211 DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
212 DRM_RENDER_ALLOW),
213
214 /* these allow direct access to the framebuffers mark as master only */
215 DRM_IOCTL_DEF_DRV(VMW_PRESENT, vmw_present_ioctl,
216 DRM_MASTER | DRM_AUTH),
217 DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK,
218 vmw_present_readback_ioctl,
219 DRM_MASTER | DRM_AUTH),
220 /*
221 * The permissions of the below ioctl are overridden in
222 * vmw_generic_ioctl(). We require either
223 * DRM_MASTER or capable(CAP_SYS_ADMIN).
224 */
225 DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT,
226 vmw_kms_update_layout_ioctl,
227 DRM_RENDER_ALLOW),
228 DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER,
229 vmw_shader_define_ioctl,
230 DRM_RENDER_ALLOW),
231 DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER,
232 vmw_shader_destroy_ioctl,
233 DRM_RENDER_ALLOW),
234 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE,
235 vmw_gb_surface_define_ioctl,
236 DRM_RENDER_ALLOW),
237 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF,
238 vmw_gb_surface_reference_ioctl,
239 DRM_RENDER_ALLOW),
240 DRM_IOCTL_DEF_DRV(VMW_SYNCCPU,
241 vmw_user_bo_synccpu_ioctl,
242 DRM_RENDER_ALLOW),
243 DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT,
244 vmw_extended_context_define_ioctl,
245 DRM_RENDER_ALLOW),
246 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT,
247 vmw_gb_surface_define_ext_ioctl,
248 DRM_RENDER_ALLOW),
249 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT,
250 vmw_gb_surface_reference_ext_ioctl,
251 DRM_RENDER_ALLOW),
252 DRM_IOCTL_DEF_DRV(VMW_MSG,
253 vmw_msg_ioctl,
254 DRM_RENDER_ALLOW),
255 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET,
256 vmw_mksstat_reset_ioctl,
257 DRM_RENDER_ALLOW),
258 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD,
259 vmw_mksstat_add_ioctl,
260 DRM_RENDER_ALLOW),
261 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE,
262 vmw_mksstat_remove_ioctl,
263 DRM_RENDER_ALLOW),
264 };
265
266 static const struct pci_device_id vmw_pci_id_list[] = {
267 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA2) },
268 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA3) },
269 { }
270 };
271 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
272
273 static int vmw_restrict_iommu;
274 static int vmw_force_coherent;
275 static int vmw_restrict_dma_mask;
276 static int vmw_assume_16bpp;
277
278 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
279 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
280 void *ptr);
281
282 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
283 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
284 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
285 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
286 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
287 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
288 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
289 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
290
291
292 struct bitmap_name {
293 uint32 value;
294 const char *name;
295 };
296
297 static const struct bitmap_name cap1_names[] = {
298 { SVGA_CAP_RECT_COPY, "rect copy" },
299 { SVGA_CAP_CURSOR, "cursor" },
300 { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" },
301 { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" },
302 { SVGA_CAP_8BIT_EMULATION, "8bit emulation" },
303 { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" },
304 { SVGA_CAP_3D, "3D" },
305 { SVGA_CAP_EXTENDED_FIFO, "extended fifo" },
306 { SVGA_CAP_MULTIMON, "multimon" },
307 { SVGA_CAP_PITCHLOCK, "pitchlock" },
308 { SVGA_CAP_IRQMASK, "irq mask" },
309 { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" },
310 { SVGA_CAP_GMR, "gmr" },
311 { SVGA_CAP_TRACES, "traces" },
312 { SVGA_CAP_GMR2, "gmr2" },
313 { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" },
314 { SVGA_CAP_COMMAND_BUFFERS, "command buffers" },
315 { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" },
316 { SVGA_CAP_GBOBJECTS, "gbobject" },
317 { SVGA_CAP_DX, "dx" },
318 { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" },
319 { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" },
320 { SVGA_CAP_CAP2_REGISTER, "cap2 register" },
321 };
322
323
324 static const struct bitmap_name cap2_names[] = {
325 { SVGA_CAP2_GROW_OTABLE, "grow otable" },
326 { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" },
327 { SVGA_CAP2_DX2, "dx2" },
328 { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" },
329 { SVGA_CAP2_SCREENDMA_REG, "screendma reg" },
330 { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" },
331 { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" },
332 { SVGA_CAP2_CURSOR_MOB, "cursor mob" },
333 { SVGA_CAP2_MSHINT, "mshint" },
334 { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" },
335 { SVGA_CAP2_DX3, "dx3" },
336 { SVGA_CAP2_FRAME_TYPE, "frame type" },
337 { SVGA_CAP2_COTABLE_COPY, "cotable copy" },
338 { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" },
339 { SVGA_CAP2_EXTRA_REGS, "extra regs" },
340 { SVGA_CAP2_LO_STAGING, "lo staging" },
341 };
342
vmw_print_bitmap(struct drm_device * drm,const char * prefix,uint32_t bitmap,const struct bitmap_name * bnames,uint32_t num_names)343 static void vmw_print_bitmap(struct drm_device *drm,
344 const char *prefix, uint32_t bitmap,
345 const struct bitmap_name *bnames,
346 uint32_t num_names)
347 {
348 char buf[512];
349 uint32_t i;
350 uint32_t offset = 0;
351 for (i = 0; i < num_names; ++i) {
352 if ((bitmap & bnames[i].value) != 0) {
353 offset += snprintf(buf + offset,
354 ARRAY_SIZE(buf) - offset,
355 "%s, ", bnames[i].name);
356 bitmap &= ~bnames[i].value;
357 }
358 }
359
360 drm_info(drm, "%s: %s\n", prefix, buf);
361 if (bitmap != 0)
362 drm_dbg(drm, "%s: unknown enums: %x\n", prefix, bitmap);
363 }
364
365
vmw_print_sm_type(struct vmw_private * dev_priv)366 static void vmw_print_sm_type(struct vmw_private *dev_priv)
367 {
368 static const char *names[] = {
369 [VMW_SM_LEGACY] = "Legacy",
370 [VMW_SM_4] = "SM4",
371 [VMW_SM_4_1] = "SM4_1",
372 [VMW_SM_5] = "SM_5",
373 [VMW_SM_5_1X] = "SM_5_1X",
374 [VMW_SM_MAX] = "Invalid"
375 };
376 BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1));
377 drm_info(&dev_priv->drm, "Available shader model: %s.\n",
378 names[dev_priv->sm_type]);
379 }
380
381 /**
382 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
383 *
384 * @dev_priv: A device private structure.
385 *
386 * This function creates a small buffer object that holds the query
387 * result for dummy queries emitted as query barriers.
388 * The function will then map the first page and initialize a pending
389 * occlusion query result structure, Finally it will unmap the buffer.
390 * No interruptible waits are done within this function.
391 *
392 * Returns an error if bo creation or initialization fails.
393 */
vmw_dummy_query_bo_create(struct vmw_private * dev_priv)394 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
395 {
396 int ret;
397 struct vmw_bo *vbo;
398 struct ttm_bo_kmap_obj map;
399 volatile SVGA3dQueryResult *result;
400 bool dummy;
401 struct vmw_bo_params bo_params = {
402 .domain = VMW_BO_DOMAIN_SYS,
403 .busy_domain = VMW_BO_DOMAIN_SYS,
404 .bo_type = ttm_bo_type_kernel,
405 .size = PAGE_SIZE,
406 .pin = true
407 };
408
409 /*
410 * Create the vbo as pinned, so that a tryreserve will
411 * immediately succeed. This is because we're the only
412 * user of the bo currently.
413 */
414 ret = vmw_bo_create(dev_priv, &bo_params, &vbo);
415 if (unlikely(ret != 0))
416 return ret;
417
418 ret = ttm_bo_reserve(&vbo->tbo, false, true, NULL);
419 BUG_ON(ret != 0);
420 vmw_bo_pin_reserved(vbo, true);
421
422 ret = ttm_bo_kmap(&vbo->tbo, 0, 1, &map);
423 if (likely(ret == 0)) {
424 result = ttm_kmap_obj_virtual(&map, &dummy);
425 result->totalSize = sizeof(*result);
426 result->state = SVGA3D_QUERYSTATE_PENDING;
427 result->result32 = 0xff;
428 ttm_bo_kunmap(&map);
429 }
430 vmw_bo_pin_reserved(vbo, false);
431 ttm_bo_unreserve(&vbo->tbo);
432
433 if (unlikely(ret != 0)) {
434 DRM_ERROR("Dummy query buffer map failed.\n");
435 vmw_bo_unreference(&vbo);
436 } else
437 dev_priv->dummy_query_bo = vbo;
438
439 return ret;
440 }
441
vmw_device_init(struct vmw_private * dev_priv)442 static int vmw_device_init(struct vmw_private *dev_priv)
443 {
444 bool uses_fb_traces = false;
445
446 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
447 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
448 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
449
450 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |
451 SVGA_REG_ENABLE_HIDE);
452
453 uses_fb_traces = !vmw_cmd_supported(dev_priv) &&
454 (dev_priv->capabilities & SVGA_CAP_TRACES) != 0;
455
456 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces);
457 dev_priv->fifo = vmw_fifo_create(dev_priv);
458 if (IS_ERR(dev_priv->fifo)) {
459 int err = PTR_ERR(dev_priv->fifo);
460 dev_priv->fifo = NULL;
461 return err;
462 } else if (!dev_priv->fifo) {
463 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
464 }
465
466 dev_priv->last_read_seqno = vmw_fence_read(dev_priv);
467 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
468 return 0;
469 }
470
vmw_device_fini(struct vmw_private * vmw)471 static void vmw_device_fini(struct vmw_private *vmw)
472 {
473 /*
474 * Legacy sync
475 */
476 vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
477 while (vmw_read(vmw, SVGA_REG_BUSY) != 0)
478 ;
479
480 vmw->last_read_seqno = vmw_fence_read(vmw);
481
482 vmw_write(vmw, SVGA_REG_CONFIG_DONE,
483 vmw->config_done_state);
484 vmw_write(vmw, SVGA_REG_ENABLE,
485 vmw->enable_state);
486 vmw_write(vmw, SVGA_REG_TRACES,
487 vmw->traces_state);
488
489 vmw_fifo_destroy(vmw);
490 }
491
492 /**
493 * vmw_request_device_late - Perform late device setup
494 *
495 * @dev_priv: Pointer to device private.
496 *
497 * This function performs setup of otables and enables large command
498 * buffer submission. These tasks are split out to a separate function
499 * because it reverts vmw_release_device_early and is intended to be used
500 * by an error path in the hibernation code.
501 */
vmw_request_device_late(struct vmw_private * dev_priv)502 static int vmw_request_device_late(struct vmw_private *dev_priv)
503 {
504 int ret;
505
506 if (dev_priv->has_mob) {
507 ret = vmw_otables_setup(dev_priv);
508 if (unlikely(ret != 0)) {
509 DRM_ERROR("Unable to initialize "
510 "guest Memory OBjects.\n");
511 return ret;
512 }
513 }
514
515 if (dev_priv->cman) {
516 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096);
517 if (ret) {
518 struct vmw_cmdbuf_man *man = dev_priv->cman;
519
520 dev_priv->cman = NULL;
521 vmw_cmdbuf_man_destroy(man);
522 }
523 }
524
525 return 0;
526 }
527
vmw_request_device(struct vmw_private * dev_priv)528 static int vmw_request_device(struct vmw_private *dev_priv)
529 {
530 int ret;
531
532 ret = vmw_device_init(dev_priv);
533 if (unlikely(ret != 0)) {
534 DRM_ERROR("Unable to initialize the device.\n");
535 return ret;
536 }
537 vmw_fence_fifo_up(dev_priv->fman);
538 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
539 if (IS_ERR(dev_priv->cman)) {
540 dev_priv->cman = NULL;
541 dev_priv->sm_type = VMW_SM_LEGACY;
542 }
543
544 ret = vmw_request_device_late(dev_priv);
545 if (ret)
546 goto out_no_mob;
547
548 ret = vmw_dummy_query_bo_create(dev_priv);
549 if (unlikely(ret != 0))
550 goto out_no_query_bo;
551
552 return 0;
553
554 out_no_query_bo:
555 if (dev_priv->cman)
556 vmw_cmdbuf_remove_pool(dev_priv->cman);
557 if (dev_priv->has_mob) {
558 struct ttm_resource_manager *man;
559
560 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB);
561 ttm_resource_manager_evict_all(&dev_priv->bdev, man);
562 vmw_otables_takedown(dev_priv);
563 }
564 if (dev_priv->cman)
565 vmw_cmdbuf_man_destroy(dev_priv->cman);
566 out_no_mob:
567 vmw_fence_fifo_down(dev_priv->fman);
568 vmw_device_fini(dev_priv);
569 return ret;
570 }
571
572 /**
573 * vmw_release_device_early - Early part of fifo takedown.
574 *
575 * @dev_priv: Pointer to device private struct.
576 *
577 * This is the first part of command submission takedown, to be called before
578 * buffer management is taken down.
579 */
vmw_release_device_early(struct vmw_private * dev_priv)580 static void vmw_release_device_early(struct vmw_private *dev_priv)
581 {
582 /*
583 * Previous destructions should've released
584 * the pinned bo.
585 */
586
587 BUG_ON(dev_priv->pinned_bo != NULL);
588
589 vmw_bo_unreference(&dev_priv->dummy_query_bo);
590 if (dev_priv->cman)
591 vmw_cmdbuf_remove_pool(dev_priv->cman);
592
593 if (dev_priv->has_mob) {
594 struct ttm_resource_manager *man;
595
596 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB);
597 ttm_resource_manager_evict_all(&dev_priv->bdev, man);
598 vmw_otables_takedown(dev_priv);
599 }
600 }
601
602 /**
603 * vmw_release_device_late - Late part of fifo takedown.
604 *
605 * @dev_priv: Pointer to device private struct.
606 *
607 * This is the last part of the command submission takedown, to be called when
608 * command submission is no longer needed. It may wait on pending fences.
609 */
vmw_release_device_late(struct vmw_private * dev_priv)610 static void vmw_release_device_late(struct vmw_private *dev_priv)
611 {
612 vmw_fence_fifo_down(dev_priv->fman);
613 if (dev_priv->cman)
614 vmw_cmdbuf_man_destroy(dev_priv->cman);
615
616 vmw_device_fini(dev_priv);
617 }
618
619 /*
620 * Sets the initial_[width|height] fields on the given vmw_private.
621 *
622 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
623 * clamping the value to fb_max_[width|height] fields and the
624 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
625 * If the values appear to be invalid, set them to
626 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
627 */
vmw_get_initial_size(struct vmw_private * dev_priv)628 static void vmw_get_initial_size(struct vmw_private *dev_priv)
629 {
630 uint32_t width;
631 uint32_t height;
632
633 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
634 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
635
636 width = max_t(uint32_t, width, VMWGFX_MIN_INITIAL_WIDTH);
637 height = max_t(uint32_t, height, VMWGFX_MIN_INITIAL_HEIGHT);
638
639 if (width > dev_priv->fb_max_width ||
640 height > dev_priv->fb_max_height) {
641
642 /*
643 * This is a host error and shouldn't occur.
644 */
645
646 width = VMWGFX_MIN_INITIAL_WIDTH;
647 height = VMWGFX_MIN_INITIAL_HEIGHT;
648 }
649
650 dev_priv->initial_width = width;
651 dev_priv->initial_height = height;
652 }
653
654 /**
655 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
656 * system.
657 *
658 * @dev_priv: Pointer to a struct vmw_private
659 *
660 * This functions tries to determine what actions need to be taken by the
661 * driver to make system pages visible to the device.
662 * If this function decides that DMA is not possible, it returns -EINVAL.
663 * The driver may then try to disable features of the device that require
664 * DMA.
665 */
vmw_dma_select_mode(struct vmw_private * dev_priv)666 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
667 {
668 static const char *names[vmw_dma_map_max] = {
669 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
670 [vmw_dma_map_populate] = "Caching DMA mappings.",
671 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
672
673 /*
674 * When running with SEV we always want dma mappings, because
675 * otherwise ttm tt pool pages will bounce through swiotlb running
676 * out of available space.
677 */
678 if (vmw_force_coherent || cc_platform_has(CC_ATTR_MEM_ENCRYPT))
679 dev_priv->map_mode = vmw_dma_alloc_coherent;
680 else if (vmw_restrict_iommu)
681 dev_priv->map_mode = vmw_dma_map_bind;
682 else
683 dev_priv->map_mode = vmw_dma_map_populate;
684
685 drm_info(&dev_priv->drm,
686 "DMA map mode: %s\n", names[dev_priv->map_mode]);
687 return 0;
688 }
689
690 /**
691 * vmw_dma_masks - set required page- and dma masks
692 *
693 * @dev_priv: Pointer to struct drm-device
694 *
695 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
696 * restriction also for 64-bit systems.
697 */
vmw_dma_masks(struct vmw_private * dev_priv)698 static int vmw_dma_masks(struct vmw_private *dev_priv)
699 {
700 struct drm_device *dev = &dev_priv->drm;
701 int ret = 0;
702
703 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64));
704 if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) {
705 drm_info(&dev_priv->drm,
706 "Restricting DMA addresses to 44 bits.\n");
707 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44));
708 }
709
710 return ret;
711 }
712
vmw_vram_manager_init(struct vmw_private * dev_priv)713 static int vmw_vram_manager_init(struct vmw_private *dev_priv)
714 {
715 int ret;
716 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false,
717 dev_priv->vram_size >> PAGE_SHIFT);
718 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false);
719 return ret;
720 }
721
vmw_vram_manager_fini(struct vmw_private * dev_priv)722 static void vmw_vram_manager_fini(struct vmw_private *dev_priv)
723 {
724 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM);
725 }
726
vmw_setup_pci_resources(struct vmw_private * dev,u32 pci_id)727 static int vmw_setup_pci_resources(struct vmw_private *dev,
728 u32 pci_id)
729 {
730 resource_size_t rmmio_start;
731 resource_size_t rmmio_size;
732 resource_size_t fifo_start;
733 resource_size_t fifo_size;
734 int ret;
735 struct pci_dev *pdev = to_pci_dev(dev->drm.dev);
736
737 pci_set_master(pdev);
738
739 ret = pci_request_regions(pdev, "vmwgfx probe");
740 if (ret)
741 return ret;
742
743 dev->pci_id = pci_id;
744 if (pci_id == VMWGFX_PCI_ID_SVGA3) {
745 rmmio_start = pci_resource_start(pdev, 0);
746 rmmio_size = pci_resource_len(pdev, 0);
747 dev->vram_start = pci_resource_start(pdev, 2);
748 dev->vram_size = pci_resource_len(pdev, 2);
749
750 drm_info(&dev->drm,
751 "Register MMIO at 0x%pa size is %llu KiB\n",
752 &rmmio_start, (uint64_t)rmmio_size / 1024);
753 dev->rmmio = devm_ioremap(dev->drm.dev,
754 rmmio_start,
755 rmmio_size);
756 if (!dev->rmmio) {
757 drm_err(&dev->drm,
758 "Failed mapping registers mmio memory.\n");
759 pci_release_regions(pdev);
760 return -ENOMEM;
761 }
762 } else if (pci_id == VMWGFX_PCI_ID_SVGA2) {
763 dev->io_start = pci_resource_start(pdev, 0);
764 dev->vram_start = pci_resource_start(pdev, 1);
765 dev->vram_size = pci_resource_len(pdev, 1);
766 fifo_start = pci_resource_start(pdev, 2);
767 fifo_size = pci_resource_len(pdev, 2);
768
769 drm_info(&dev->drm,
770 "FIFO at %pa size is %llu KiB\n",
771 &fifo_start, (uint64_t)fifo_size / 1024);
772 dev->fifo_mem = devm_memremap(dev->drm.dev,
773 fifo_start,
774 fifo_size,
775 MEMREMAP_WB);
776
777 if (IS_ERR(dev->fifo_mem)) {
778 drm_err(&dev->drm,
779 "Failed mapping FIFO memory.\n");
780 pci_release_regions(pdev);
781 return PTR_ERR(dev->fifo_mem);
782 }
783 } else {
784 pci_release_regions(pdev);
785 return -EINVAL;
786 }
787
788 /*
789 * This is approximate size of the vram, the exact size will only
790 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource
791 * size will be equal to or bigger than the size reported by
792 * SVGA_REG_VRAM_SIZE.
793 */
794 drm_info(&dev->drm,
795 "VRAM at %pa size is %llu KiB\n",
796 &dev->vram_start, (uint64_t)dev->vram_size / 1024);
797
798 return 0;
799 }
800
vmw_detect_version(struct vmw_private * dev)801 static int vmw_detect_version(struct vmw_private *dev)
802 {
803 uint32_t svga_id;
804
805 vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ?
806 SVGA_ID_3 : SVGA_ID_2);
807 svga_id = vmw_read(dev, SVGA_REG_ID);
808 if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) {
809 drm_err(&dev->drm,
810 "Unsupported SVGA ID 0x%x on chipset 0x%x\n",
811 svga_id, dev->pci_id);
812 return -ENOSYS;
813 }
814 BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3));
815 drm_info(&dev->drm,
816 "Running on SVGA version %d.\n", (svga_id & 0xff));
817 return 0;
818 }
819
vmw_write_driver_id(struct vmw_private * dev)820 static void vmw_write_driver_id(struct vmw_private *dev)
821 {
822 if ((dev->capabilities2 & SVGA_CAP2_DX2) != 0) {
823 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID,
824 SVGA_REG_GUEST_DRIVER_ID_LINUX);
825
826 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION1,
827 LINUX_VERSION_MAJOR << 24 |
828 LINUX_VERSION_PATCHLEVEL << 16 |
829 LINUX_VERSION_SUBLEVEL);
830 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION2,
831 VMWGFX_DRIVER_MAJOR << 24 |
832 VMWGFX_DRIVER_MINOR << 16 |
833 VMWGFX_DRIVER_PATCHLEVEL);
834 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION3, 0);
835
836 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID,
837 SVGA_REG_GUEST_DRIVER_ID_SUBMIT);
838 }
839 }
840
vmw_sw_context_init(struct vmw_private * dev_priv)841 static void vmw_sw_context_init(struct vmw_private *dev_priv)
842 {
843 struct vmw_sw_context *sw_context = &dev_priv->ctx;
844
845 hash_init(sw_context->res_ht);
846 }
847
vmw_sw_context_fini(struct vmw_private * dev_priv)848 static void vmw_sw_context_fini(struct vmw_private *dev_priv)
849 {
850 struct vmw_sw_context *sw_context = &dev_priv->ctx;
851
852 vfree(sw_context->cmd_bounce);
853 if (sw_context->staged_bindings)
854 vmw_binding_state_free(sw_context->staged_bindings);
855 }
856
vmw_driver_load(struct vmw_private * dev_priv,u32 pci_id)857 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
858 {
859 int ret;
860 enum vmw_res_type i;
861 bool refuse_dma = false;
862 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
863
864 vmw_sw_context_init(dev_priv);
865
866 mutex_init(&dev_priv->cmdbuf_mutex);
867 mutex_init(&dev_priv->binding_mutex);
868 spin_lock_init(&dev_priv->resource_lock);
869 spin_lock_init(&dev_priv->hw_lock);
870 spin_lock_init(&dev_priv->waiter_lock);
871 spin_lock_init(&dev_priv->cursor_lock);
872
873 ret = vmw_setup_pci_resources(dev_priv, pci_id);
874 if (ret)
875 return ret;
876 ret = vmw_detect_version(dev_priv);
877 if (ret)
878 goto out_no_pci_or_version;
879
880
881 for (i = vmw_res_context; i < vmw_res_max; ++i) {
882 idr_init_base(&dev_priv->res_idr[i], 1);
883 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
884 }
885
886 init_waitqueue_head(&dev_priv->fence_queue);
887 init_waitqueue_head(&dev_priv->fifo_queue);
888 dev_priv->fence_queue_waiters = 0;
889 dev_priv->fifo_queue_waiters = 0;
890
891 dev_priv->used_memory_size = 0;
892
893 dev_priv->assume_16bpp = !!vmw_assume_16bpp;
894
895 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
896 vmw_print_bitmap(&dev_priv->drm, "Capabilities",
897 dev_priv->capabilities,
898 cap1_names, ARRAY_SIZE(cap1_names));
899 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) {
900 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2);
901 vmw_print_bitmap(&dev_priv->drm, "Capabilities2",
902 dev_priv->capabilities2,
903 cap2_names, ARRAY_SIZE(cap2_names));
904 }
905
906 if (!vmwgfx_supported(dev_priv)) {
907 vmw_disable_backdoor();
908 drm_err_once(&dev_priv->drm,
909 "vmwgfx seems to be running on an unsupported hypervisor.");
910 drm_err_once(&dev_priv->drm,
911 "This configuration is likely broken.");
912 drm_err_once(&dev_priv->drm,
913 "Please switch to a supported graphics device to avoid problems.");
914 }
915
916 vmw_vkms_init(dev_priv);
917
918 ret = vmw_dma_select_mode(dev_priv);
919 if (unlikely(ret != 0)) {
920 drm_info(&dev_priv->drm,
921 "Restricting capabilities since DMA not available.\n");
922 refuse_dma = true;
923 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS)
924 drm_info(&dev_priv->drm,
925 "Disabling 3D acceleration.\n");
926 }
927
928 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
929 dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
930 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
931 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
932
933 vmw_get_initial_size(dev_priv);
934
935 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
936 dev_priv->max_gmr_ids =
937 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
938 dev_priv->max_gmr_pages =
939 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
940 dev_priv->memory_size =
941 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
942 dev_priv->memory_size -= dev_priv->vram_size;
943 } else {
944 /*
945 * An arbitrary limit of 512MiB on surface
946 * memory. But all HWV8 hardware supports GMR2.
947 */
948 dev_priv->memory_size = 512*1024*1024;
949 }
950 dev_priv->max_mob_pages = 0;
951 dev_priv->max_mob_size = 0;
952 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
953 uint64_t mem_size;
954
955 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2)
956 mem_size = vmw_read(dev_priv,
957 SVGA_REG_GBOBJECT_MEM_SIZE_KB);
958 else
959 mem_size =
960 vmw_read(dev_priv,
961 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
962
963 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
964 dev_priv->max_primary_mem =
965 vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM);
966 dev_priv->max_mob_size =
967 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
968 dev_priv->stdu_max_width =
969 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
970 dev_priv->stdu_max_height =
971 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
972
973 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
974 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
975 dev_priv->texture_max_width = vmw_read(dev_priv,
976 SVGA_REG_DEV_CAP);
977 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
978 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
979 dev_priv->texture_max_height = vmw_read(dev_priv,
980 SVGA_REG_DEV_CAP);
981 } else {
982 dev_priv->texture_max_width = 8192;
983 dev_priv->texture_max_height = 8192;
984 dev_priv->max_primary_mem = dev_priv->vram_size;
985 }
986 drm_info(&dev_priv->drm,
987 "Legacy memory limits: VRAM = %llu KiB, FIFO = %llu KiB, surface = %u KiB\n",
988 (u64)dev_priv->vram_size / 1024,
989 (u64)dev_priv->fifo_mem_size / 1024,
990 dev_priv->memory_size / 1024);
991
992 drm_info(&dev_priv->drm,
993 "MOB limits: max mob size = %u KiB, max mob pages = %u\n",
994 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages);
995
996 ret = vmw_dma_masks(dev_priv);
997 if (unlikely(ret != 0))
998 goto out_err0;
999
1000 dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX);
1001
1002 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
1003 drm_info(&dev_priv->drm,
1004 "Max GMR ids is %u\n",
1005 (unsigned)dev_priv->max_gmr_ids);
1006 drm_info(&dev_priv->drm,
1007 "Max number of GMR pages is %u\n",
1008 (unsigned)dev_priv->max_gmr_pages);
1009 }
1010 drm_info(&dev_priv->drm,
1011 "Maximum display memory size is %llu KiB\n",
1012 (uint64_t)dev_priv->max_primary_mem / 1024);
1013
1014 /* Need mmio memory to check for fifo pitchlock cap. */
1015 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
1016 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
1017 !vmw_fifo_have_pitchlock(dev_priv)) {
1018 ret = -ENOSYS;
1019 DRM_ERROR("Hardware has no pitchlock\n");
1020 goto out_err0;
1021 }
1022
1023 dev_priv->tdev = ttm_object_device_init(&vmw_prime_dmabuf_ops);
1024
1025 if (unlikely(dev_priv->tdev == NULL)) {
1026 drm_err(&dev_priv->drm,
1027 "Unable to initialize TTM object management.\n");
1028 ret = -ENOMEM;
1029 goto out_err0;
1030 }
1031
1032 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
1033 ret = vmw_irq_install(dev_priv);
1034 if (ret != 0) {
1035 drm_err(&dev_priv->drm,
1036 "Failed installing irq: %d\n", ret);
1037 goto out_no_irq;
1038 }
1039 }
1040
1041 dev_priv->fman = vmw_fence_manager_init(dev_priv);
1042 if (unlikely(dev_priv->fman == NULL)) {
1043 ret = -ENOMEM;
1044 goto out_no_fman;
1045 }
1046
1047 ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver,
1048 dev_priv->drm.dev,
1049 dev_priv->drm.anon_inode->i_mapping,
1050 dev_priv->drm.vma_offset_manager,
1051 dev_priv->map_mode == vmw_dma_alloc_coherent,
1052 false);
1053 if (unlikely(ret != 0)) {
1054 drm_err(&dev_priv->drm,
1055 "Failed initializing TTM buffer object driver.\n");
1056 goto out_no_bdev;
1057 }
1058
1059 /*
1060 * Enable VRAM, but initially don't use it until SVGA is enabled and
1061 * unhidden.
1062 */
1063
1064 ret = vmw_vram_manager_init(dev_priv);
1065 if (unlikely(ret != 0)) {
1066 drm_err(&dev_priv->drm,
1067 "Failed initializing memory manager for VRAM.\n");
1068 goto out_no_vram;
1069 }
1070
1071 ret = vmw_devcaps_create(dev_priv);
1072 if (unlikely(ret != 0)) {
1073 drm_err(&dev_priv->drm,
1074 "Failed initializing device caps.\n");
1075 goto out_no_vram;
1076 }
1077
1078 /*
1079 * "Guest Memory Regions" is an aperture like feature with
1080 * one slot per bo. There is an upper limit of the number of
1081 * slots as well as the bo size.
1082 */
1083 dev_priv->has_gmr = true;
1084 /* TODO: This is most likely not correct */
1085 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
1086 refuse_dma ||
1087 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) {
1088 drm_info(&dev_priv->drm,
1089 "No GMR memory available. "
1090 "Graphics memory resources are very limited.\n");
1091 dev_priv->has_gmr = false;
1092 }
1093
1094 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) {
1095 dev_priv->has_mob = true;
1096
1097 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) {
1098 drm_info(&dev_priv->drm,
1099 "No MOB memory available. "
1100 "3D will be disabled.\n");
1101 dev_priv->has_mob = false;
1102 }
1103 if (vmw_sys_man_init(dev_priv) != 0) {
1104 drm_info(&dev_priv->drm,
1105 "No MOB page table memory available. "
1106 "3D will be disabled.\n");
1107 dev_priv->has_mob = false;
1108 }
1109 }
1110
1111 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) {
1112 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT))
1113 dev_priv->sm_type = VMW_SM_4;
1114 }
1115
1116 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */
1117 if (has_sm4_context(dev_priv) &&
1118 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) {
1119 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41))
1120 dev_priv->sm_type = VMW_SM_4_1;
1121 if (has_sm4_1_context(dev_priv) &&
1122 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) {
1123 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) {
1124 dev_priv->sm_type = VMW_SM_5;
1125 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43))
1126 dev_priv->sm_type = VMW_SM_5_1X;
1127 }
1128 }
1129 }
1130
1131 ret = vmw_kms_init(dev_priv);
1132 if (unlikely(ret != 0))
1133 goto out_no_kms;
1134 vmw_overlay_init(dev_priv);
1135
1136 ret = vmw_request_device(dev_priv);
1137 if (ret)
1138 goto out_no_fifo;
1139
1140 vmw_print_sm_type(dev_priv);
1141 vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)",
1142 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
1143 VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE);
1144 vmw_write_driver_id(dev_priv);
1145
1146 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
1147 register_pm_notifier(&dev_priv->pm_nb);
1148
1149 return 0;
1150
1151 out_no_fifo:
1152 vmw_overlay_close(dev_priv);
1153 vmw_kms_close(dev_priv);
1154 out_no_kms:
1155 if (dev_priv->has_mob) {
1156 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
1157 vmw_sys_man_fini(dev_priv);
1158 }
1159 if (dev_priv->has_gmr)
1160 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
1161 vmw_devcaps_destroy(dev_priv);
1162 vmw_vram_manager_fini(dev_priv);
1163 out_no_vram:
1164 ttm_device_fini(&dev_priv->bdev);
1165 out_no_bdev:
1166 vmw_fence_manager_takedown(dev_priv->fman);
1167 out_no_fman:
1168 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1169 vmw_irq_uninstall(&dev_priv->drm);
1170 out_no_irq:
1171 ttm_object_device_release(&dev_priv->tdev);
1172 out_err0:
1173 for (i = vmw_res_context; i < vmw_res_max; ++i)
1174 idr_destroy(&dev_priv->res_idr[i]);
1175
1176 if (dev_priv->ctx.staged_bindings)
1177 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1178 out_no_pci_or_version:
1179 pci_release_regions(pdev);
1180 return ret;
1181 }
1182
vmw_driver_unload(struct drm_device * dev)1183 static void vmw_driver_unload(struct drm_device *dev)
1184 {
1185 struct vmw_private *dev_priv = vmw_priv(dev);
1186 struct pci_dev *pdev = to_pci_dev(dev->dev);
1187 enum vmw_res_type i;
1188
1189 unregister_pm_notifier(&dev_priv->pm_nb);
1190
1191 vmw_sw_context_fini(dev_priv);
1192 vmw_fifo_resource_dec(dev_priv);
1193
1194 vmw_svga_disable(dev_priv);
1195
1196 vmw_vkms_cleanup(dev_priv);
1197 vmw_kms_close(dev_priv);
1198 vmw_overlay_close(dev_priv);
1199
1200 if (dev_priv->has_gmr)
1201 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
1202
1203 vmw_release_device_early(dev_priv);
1204 if (dev_priv->has_mob) {
1205 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
1206 vmw_sys_man_fini(dev_priv);
1207 }
1208 vmw_devcaps_destroy(dev_priv);
1209 vmw_vram_manager_fini(dev_priv);
1210 ttm_device_fini(&dev_priv->bdev);
1211 vmw_release_device_late(dev_priv);
1212 vmw_fence_manager_takedown(dev_priv->fman);
1213 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1214 vmw_irq_uninstall(&dev_priv->drm);
1215
1216 ttm_object_device_release(&dev_priv->tdev);
1217
1218 for (i = vmw_res_context; i < vmw_res_max; ++i)
1219 idr_destroy(&dev_priv->res_idr[i]);
1220
1221 vmw_mksstat_remove_all(dev_priv);
1222
1223 pci_release_regions(pdev);
1224 }
1225
vmw_postclose(struct drm_device * dev,struct drm_file * file_priv)1226 static void vmw_postclose(struct drm_device *dev,
1227 struct drm_file *file_priv)
1228 {
1229 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1230
1231 ttm_object_file_release(&vmw_fp->tfile);
1232 kfree(vmw_fp);
1233 }
1234
vmw_driver_open(struct drm_device * dev,struct drm_file * file_priv)1235 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1236 {
1237 struct vmw_private *dev_priv = vmw_priv(dev);
1238 struct vmw_fpriv *vmw_fp;
1239 int ret = -ENOMEM;
1240
1241 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1242 if (unlikely(!vmw_fp))
1243 return ret;
1244
1245 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev);
1246 if (unlikely(vmw_fp->tfile == NULL))
1247 goto out_no_tfile;
1248
1249 file_priv->driver_priv = vmw_fp;
1250
1251 return 0;
1252
1253 out_no_tfile:
1254 kfree(vmw_fp);
1255 return ret;
1256 }
1257
vmw_generic_ioctl(struct file * filp,unsigned int cmd,unsigned long arg,long (* ioctl_func)(struct file *,unsigned int,unsigned long))1258 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1259 unsigned long arg,
1260 long (*ioctl_func)(struct file *, unsigned int,
1261 unsigned long))
1262 {
1263 struct drm_file *file_priv = filp->private_data;
1264 struct drm_device *dev = file_priv->minor->dev;
1265 unsigned int nr = DRM_IOCTL_NR(cmd);
1266 unsigned int flags;
1267
1268 /*
1269 * Do extra checking on driver private ioctls.
1270 */
1271
1272 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1273 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1274 const struct drm_ioctl_desc *ioctl =
1275 &vmw_ioctls[nr - DRM_COMMAND_BASE];
1276
1277 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1278 return ioctl_func(filp, cmd, arg);
1279 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) {
1280 if (!drm_is_current_master(file_priv) &&
1281 !capable(CAP_SYS_ADMIN))
1282 return -EACCES;
1283 }
1284
1285 if (unlikely(ioctl->cmd != cmd))
1286 goto out_io_encoding;
1287
1288 flags = ioctl->flags;
1289 } else if (!drm_ioctl_flags(nr, &flags))
1290 return -EINVAL;
1291
1292 return ioctl_func(filp, cmd, arg);
1293
1294 out_io_encoding:
1295 DRM_ERROR("Invalid command format, ioctl %d\n",
1296 nr - DRM_COMMAND_BASE);
1297
1298 return -EINVAL;
1299 }
1300
vmw_unlocked_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)1301 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1302 unsigned long arg)
1303 {
1304 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1305 }
1306
1307 #ifdef CONFIG_COMPAT
vmw_compat_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)1308 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1309 unsigned long arg)
1310 {
1311 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1312 }
1313 #endif
1314
vmw_master_set(struct drm_device * dev,struct drm_file * file_priv,bool from_open)1315 static void vmw_master_set(struct drm_device *dev,
1316 struct drm_file *file_priv,
1317 bool from_open)
1318 {
1319 /*
1320 * Inform a new master that the layout may have changed while
1321 * it was gone.
1322 */
1323 if (!from_open)
1324 drm_sysfs_hotplug_event(dev);
1325 }
1326
vmw_master_drop(struct drm_device * dev,struct drm_file * file_priv)1327 static void vmw_master_drop(struct drm_device *dev,
1328 struct drm_file *file_priv)
1329 {
1330 struct vmw_private *dev_priv = vmw_priv(dev);
1331
1332 vmw_kms_legacy_hotspot_clear(dev_priv);
1333 }
1334
vmwgfx_supported(struct vmw_private * vmw)1335 bool vmwgfx_supported(struct vmw_private *vmw)
1336 {
1337 #if defined(CONFIG_X86)
1338 return hypervisor_is_type(X86_HYPER_VMWARE);
1339 #elif defined(CONFIG_ARM64)
1340 /*
1341 * On aarch64 only svga3 is supported
1342 */
1343 return vmw->pci_id == VMWGFX_PCI_ID_SVGA3;
1344 #else
1345 drm_warn_once(&vmw->drm,
1346 "vmwgfx is running on an unknown architecture.");
1347 return false;
1348 #endif
1349 }
1350
1351 /**
1352 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1353 *
1354 * @dev_priv: Pointer to device private struct.
1355 * Needs the reservation sem to be held in non-exclusive mode.
1356 */
__vmw_svga_enable(struct vmw_private * dev_priv)1357 static void __vmw_svga_enable(struct vmw_private *dev_priv)
1358 {
1359 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1360
1361 if (!ttm_resource_manager_used(man)) {
1362 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE);
1363 ttm_resource_manager_set_used(man, true);
1364 }
1365 }
1366
1367 /**
1368 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1369 *
1370 * @dev_priv: Pointer to device private struct.
1371 */
vmw_svga_enable(struct vmw_private * dev_priv)1372 void vmw_svga_enable(struct vmw_private *dev_priv)
1373 {
1374 __vmw_svga_enable(dev_priv);
1375 }
1376
1377 /**
1378 * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1379 *
1380 * @dev_priv: Pointer to device private struct.
1381 * Needs the reservation sem to be held in exclusive mode.
1382 * Will not empty VRAM. VRAM must be emptied by caller.
1383 */
__vmw_svga_disable(struct vmw_private * dev_priv)1384 static void __vmw_svga_disable(struct vmw_private *dev_priv)
1385 {
1386 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1387
1388 if (ttm_resource_manager_used(man)) {
1389 ttm_resource_manager_set_used(man, false);
1390 vmw_write(dev_priv, SVGA_REG_ENABLE,
1391 SVGA_REG_ENABLE_HIDE |
1392 SVGA_REG_ENABLE_ENABLE);
1393 }
1394 }
1395
1396 /**
1397 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1398 * running.
1399 *
1400 * @dev_priv: Pointer to device private struct.
1401 * Will empty VRAM.
1402 */
vmw_svga_disable(struct vmw_private * dev_priv)1403 void vmw_svga_disable(struct vmw_private *dev_priv)
1404 {
1405 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1406 /*
1407 * Disabling SVGA will turn off device modesetting capabilities, so
1408 * notify KMS about that so that it doesn't cache atomic state that
1409 * isn't valid anymore, for example crtcs turned on.
1410 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex),
1411 * but vmw_kms_lost_device() takes the reservation sem and thus we'll
1412 * end up with lock order reversal. Thus, a master may actually perform
1413 * a new modeset just after we call vmw_kms_lost_device() and race with
1414 * vmw_svga_disable(), but that should at worst cause atomic KMS state
1415 * to be inconsistent with the device, causing modesetting problems.
1416 *
1417 */
1418 vmw_kms_lost_device(&dev_priv->drm);
1419 if (ttm_resource_manager_used(man)) {
1420 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man))
1421 DRM_ERROR("Failed evicting VRAM buffers.\n");
1422 ttm_resource_manager_set_used(man, false);
1423 vmw_write(dev_priv, SVGA_REG_ENABLE,
1424 SVGA_REG_ENABLE_HIDE |
1425 SVGA_REG_ENABLE_ENABLE);
1426 }
1427 }
1428
vmw_remove(struct pci_dev * pdev)1429 static void vmw_remove(struct pci_dev *pdev)
1430 {
1431 struct drm_device *dev = pci_get_drvdata(pdev);
1432
1433 drm_dev_unregister(dev);
1434 vmw_driver_unload(dev);
1435 }
1436
vmw_debugfs_resource_managers_init(struct vmw_private * vmw)1437 static void vmw_debugfs_resource_managers_init(struct vmw_private *vmw)
1438 {
1439 struct drm_minor *minor = vmw->drm.primary;
1440 struct dentry *root = minor->debugfs_root;
1441
1442 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_SYSTEM),
1443 root, "system_ttm");
1444 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_VRAM),
1445 root, "vram_ttm");
1446 if (vmw->has_gmr)
1447 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_GMR),
1448 root, "gmr_ttm");
1449 if (vmw->has_mob) {
1450 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_MOB),
1451 root, "mob_ttm");
1452 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_SYSTEM),
1453 root, "system_mob_ttm");
1454 }
1455 }
1456
vmwgfx_pm_notifier(struct notifier_block * nb,unsigned long val,void * ptr)1457 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1458 void *ptr)
1459 {
1460 struct vmw_private *dev_priv =
1461 container_of(nb, struct vmw_private, pm_nb);
1462
1463 switch (val) {
1464 case PM_HIBERNATION_PREPARE:
1465 /*
1466 * Take the reservation sem in write mode, which will make sure
1467 * there are no other processes holding a buffer object
1468 * reservation, meaning we should be able to evict all buffer
1469 * objects if needed.
1470 * Once user-space processes have been frozen, we can release
1471 * the lock again.
1472 */
1473 dev_priv->suspend_locked = true;
1474 break;
1475 case PM_POST_HIBERNATION:
1476 case PM_POST_RESTORE:
1477 if (READ_ONCE(dev_priv->suspend_locked)) {
1478 dev_priv->suspend_locked = false;
1479 }
1480 break;
1481 default:
1482 break;
1483 }
1484 return 0;
1485 }
1486
vmw_pci_suspend(struct pci_dev * pdev,pm_message_t state)1487 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1488 {
1489 struct drm_device *dev = pci_get_drvdata(pdev);
1490 struct vmw_private *dev_priv = vmw_priv(dev);
1491
1492 if (dev_priv->refuse_hibernation)
1493 return -EBUSY;
1494
1495 pci_save_state(pdev);
1496 pci_disable_device(pdev);
1497 pci_set_power_state(pdev, PCI_D3hot);
1498 return 0;
1499 }
1500
vmw_pci_resume(struct pci_dev * pdev)1501 static int vmw_pci_resume(struct pci_dev *pdev)
1502 {
1503 pci_set_power_state(pdev, PCI_D0);
1504 pci_restore_state(pdev);
1505 return pci_enable_device(pdev);
1506 }
1507
vmw_pm_suspend(struct device * kdev)1508 static int vmw_pm_suspend(struct device *kdev)
1509 {
1510 struct pci_dev *pdev = to_pci_dev(kdev);
1511 struct pm_message dummy;
1512
1513 dummy.event = 0;
1514
1515 return vmw_pci_suspend(pdev, dummy);
1516 }
1517
vmw_pm_resume(struct device * kdev)1518 static int vmw_pm_resume(struct device *kdev)
1519 {
1520 struct pci_dev *pdev = to_pci_dev(kdev);
1521
1522 return vmw_pci_resume(pdev);
1523 }
1524
vmw_pm_freeze(struct device * kdev)1525 static int vmw_pm_freeze(struct device *kdev)
1526 {
1527 struct pci_dev *pdev = to_pci_dev(kdev);
1528 struct drm_device *dev = pci_get_drvdata(pdev);
1529 struct vmw_private *dev_priv = vmw_priv(dev);
1530 struct ttm_operation_ctx ctx = {
1531 .interruptible = false,
1532 .no_wait_gpu = false
1533 };
1534 int ret;
1535
1536 /*
1537 * No user-space processes should be running now.
1538 */
1539 ret = vmw_kms_suspend(&dev_priv->drm);
1540 if (ret) {
1541 DRM_ERROR("Failed to freeze modesetting.\n");
1542 return ret;
1543 }
1544
1545 vmw_execbuf_release_pinned_bo(dev_priv);
1546 vmw_resource_evict_all(dev_priv);
1547 vmw_release_device_early(dev_priv);
1548 while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0);
1549 vmw_fifo_resource_dec(dev_priv);
1550 if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1551 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1552 vmw_fifo_resource_inc(dev_priv);
1553 WARN_ON(vmw_request_device_late(dev_priv));
1554 dev_priv->suspend_locked = false;
1555 if (dev_priv->suspend_state)
1556 vmw_kms_resume(dev);
1557 return -EBUSY;
1558 }
1559
1560 vmw_fence_fifo_down(dev_priv->fman);
1561 __vmw_svga_disable(dev_priv);
1562
1563 vmw_release_device_late(dev_priv);
1564 return 0;
1565 }
1566
vmw_pm_restore(struct device * kdev)1567 static int vmw_pm_restore(struct device *kdev)
1568 {
1569 struct pci_dev *pdev = to_pci_dev(kdev);
1570 struct drm_device *dev = pci_get_drvdata(pdev);
1571 struct vmw_private *dev_priv = vmw_priv(dev);
1572 int ret;
1573
1574 vmw_detect_version(dev_priv);
1575
1576 vmw_fifo_resource_inc(dev_priv);
1577
1578 ret = vmw_request_device(dev_priv);
1579 if (ret)
1580 return ret;
1581
1582 __vmw_svga_enable(dev_priv);
1583
1584 vmw_fence_fifo_up(dev_priv->fman);
1585 dev_priv->suspend_locked = false;
1586 if (dev_priv->suspend_state)
1587 vmw_kms_resume(&dev_priv->drm);
1588
1589 return 0;
1590 }
1591
1592 static const struct dev_pm_ops vmw_pm_ops = {
1593 .freeze = vmw_pm_freeze,
1594 .thaw = vmw_pm_restore,
1595 .restore = vmw_pm_restore,
1596 .suspend = vmw_pm_suspend,
1597 .resume = vmw_pm_resume,
1598 };
1599
1600 static const struct file_operations vmwgfx_driver_fops = {
1601 .owner = THIS_MODULE,
1602 .open = drm_open,
1603 .release = drm_release,
1604 .unlocked_ioctl = vmw_unlocked_ioctl,
1605 .mmap = drm_gem_mmap,
1606 .poll = drm_poll,
1607 .read = drm_read,
1608 #if defined(CONFIG_COMPAT)
1609 .compat_ioctl = vmw_compat_ioctl,
1610 #endif
1611 .llseek = noop_llseek,
1612 .fop_flags = FOP_UNSIGNED_OFFSET,
1613 };
1614
1615 static const struct drm_driver driver = {
1616 .driver_features =
1617 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_GEM | DRIVER_CURSOR_HOTSPOT,
1618 .ioctls = vmw_ioctls,
1619 .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1620 .master_set = vmw_master_set,
1621 .master_drop = vmw_master_drop,
1622 .open = vmw_driver_open,
1623 .postclose = vmw_postclose,
1624
1625 .dumb_create = vmw_dumb_create,
1626 .dumb_map_offset = drm_gem_ttm_dumb_map_offset,
1627
1628 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1629 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1630 .gem_prime_import_sg_table = vmw_prime_import_sg_table,
1631
1632 DRM_FBDEV_TTM_DRIVER_OPS,
1633
1634 .fops = &vmwgfx_driver_fops,
1635 .name = VMWGFX_DRIVER_NAME,
1636 .desc = VMWGFX_DRIVER_DESC,
1637 .date = VMWGFX_DRIVER_DATE,
1638 .major = VMWGFX_DRIVER_MAJOR,
1639 .minor = VMWGFX_DRIVER_MINOR,
1640 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1641 };
1642
1643 static struct pci_driver vmw_pci_driver = {
1644 .name = VMWGFX_DRIVER_NAME,
1645 .id_table = vmw_pci_id_list,
1646 .probe = vmw_probe,
1647 .remove = vmw_remove,
1648 .driver = {
1649 .pm = &vmw_pm_ops
1650 }
1651 };
1652
vmw_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1653 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1654 {
1655 struct vmw_private *vmw;
1656 int ret;
1657
1658 ret = aperture_remove_conflicting_pci_devices(pdev, driver.name);
1659 if (ret)
1660 goto out_error;
1661
1662 ret = pcim_enable_device(pdev);
1663 if (ret)
1664 goto out_error;
1665
1666 vmw = devm_drm_dev_alloc(&pdev->dev, &driver,
1667 struct vmw_private, drm);
1668 if (IS_ERR(vmw)) {
1669 ret = PTR_ERR(vmw);
1670 goto out_error;
1671 }
1672
1673 pci_set_drvdata(pdev, &vmw->drm);
1674
1675 ret = vmw_driver_load(vmw, ent->device);
1676 if (ret)
1677 goto out_error;
1678
1679 ret = drm_dev_register(&vmw->drm, 0);
1680 if (ret)
1681 goto out_unload;
1682
1683 vmw_fifo_resource_inc(vmw);
1684 vmw_svga_enable(vmw);
1685 drm_client_setup(&vmw->drm, NULL);
1686
1687 vmw_debugfs_gem_init(vmw);
1688 vmw_debugfs_resource_managers_init(vmw);
1689
1690 return 0;
1691 out_unload:
1692 vmw_driver_unload(&vmw->drm);
1693 out_error:
1694 return ret;
1695 }
1696
1697 drm_module_pci_driver(vmw_pci_driver);
1698
1699 MODULE_AUTHOR("VMware Inc. and others");
1700 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1701 MODULE_LICENSE("GPL and additional rights");
1702 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1703 __stringify(VMWGFX_DRIVER_MINOR) "."
1704 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1705 "0");
1706