1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/bsearch.h>
25 #include <linux/pci.h>
26 #include <linux/slab.h>
27 #include "kfd_priv.h"
28 #include "kfd_device_queue_manager.h"
29 #include "kfd_pm4_headers_vi.h"
30 #include "kfd_pm4_headers_aldebaran.h"
31 #include "cwsr_trap_handler.h"
32 #include "amdgpu_amdkfd.h"
33 #include "kfd_smi_events.h"
34 #include "kfd_svm.h"
35 #include "kfd_migrate.h"
36 #include "amdgpu.h"
37 #include "amdgpu_xcp.h"
38
39 #define MQD_SIZE_ALIGNED 768
40
41 /*
42 * kfd_locked is used to lock the kfd driver during suspend or reset
43 * once locked, kfd driver will stop any further GPU execution.
44 * create process (open) will return -EAGAIN.
45 */
46 static int kfd_locked;
47
48 #ifdef CONFIG_DRM_AMDGPU_CIK
49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
50 #endif
51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
53 extern const struct kfd2kgd_calls arcturus_kfd2kgd;
54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd;
55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd;
56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd;
59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd;
60
61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
62 unsigned int chunk_size);
63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
64
65 static int kfd_resume(struct kfd_node *kfd);
66
kfd_device_info_set_sdma_info(struct kfd_dev * kfd)67 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)
68 {
69 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0);
70
71 switch (sdma_version) {
72 case IP_VERSION(4, 0, 0):/* VEGA10 */
73 case IP_VERSION(4, 0, 1):/* VEGA12 */
74 case IP_VERSION(4, 1, 0):/* RAVEN */
75 case IP_VERSION(4, 1, 1):/* RAVEN */
76 case IP_VERSION(4, 1, 2):/* RENOIR */
77 case IP_VERSION(5, 2, 1):/* VANGOGH */
78 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
79 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */
80 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */
81 kfd->device_info.num_sdma_queues_per_engine = 2;
82 break;
83 case IP_VERSION(4, 2, 0):/* VEGA20 */
84 case IP_VERSION(4, 2, 2):/* ARCTURUS */
85 case IP_VERSION(4, 4, 0):/* ALDEBARAN */
86 case IP_VERSION(4, 4, 2):
87 case IP_VERSION(4, 4, 5):
88 case IP_VERSION(4, 4, 4):
89 case IP_VERSION(5, 0, 0):/* NAVI10 */
90 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */
91 case IP_VERSION(5, 0, 2):/* NAVI14 */
92 case IP_VERSION(5, 0, 5):/* NAVI12 */
93 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */
94 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */
95 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
96 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
97 case IP_VERSION(6, 0, 0):
98 case IP_VERSION(6, 0, 1):
99 case IP_VERSION(6, 0, 2):
100 case IP_VERSION(6, 0, 3):
101 case IP_VERSION(6, 1, 0):
102 case IP_VERSION(6, 1, 1):
103 case IP_VERSION(6, 1, 2):
104 case IP_VERSION(6, 1, 3):
105 case IP_VERSION(7, 0, 0):
106 case IP_VERSION(7, 0, 1):
107 kfd->device_info.num_sdma_queues_per_engine = 8;
108 break;
109 default:
110 dev_warn(kfd_device,
111 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n",
112 sdma_version);
113 kfd->device_info.num_sdma_queues_per_engine = 8;
114 }
115
116 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES);
117
118 switch (sdma_version) {
119 case IP_VERSION(6, 0, 0):
120 case IP_VERSION(6, 0, 1):
121 case IP_VERSION(6, 0, 2):
122 case IP_VERSION(6, 0, 3):
123 case IP_VERSION(6, 1, 0):
124 case IP_VERSION(6, 1, 1):
125 case IP_VERSION(6, 1, 2):
126 case IP_VERSION(6, 1, 3):
127 case IP_VERSION(7, 0, 0):
128 case IP_VERSION(7, 0, 1):
129 /* Reserve 1 for paging and 1 for gfx */
130 kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
131 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */
132 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0,
133 kfd->adev->sdma.num_instances *
134 kfd->device_info.num_reserved_sdma_queues_per_engine);
135 break;
136 default:
137 break;
138 }
139 }
140
kfd_device_info_set_event_interrupt_class(struct kfd_dev * kfd)141 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)
142 {
143 uint32_t gc_version = KFD_GC_VERSION(kfd);
144
145 switch (gc_version) {
146 case IP_VERSION(9, 0, 1): /* VEGA10 */
147 case IP_VERSION(9, 1, 0): /* RAVEN */
148 case IP_VERSION(9, 2, 1): /* VEGA12 */
149 case IP_VERSION(9, 2, 2): /* RAVEN */
150 case IP_VERSION(9, 3, 0): /* RENOIR */
151 case IP_VERSION(9, 4, 0): /* VEGA20 */
152 case IP_VERSION(9, 4, 1): /* ARCTURUS */
153 case IP_VERSION(9, 4, 2): /* ALDEBARAN */
154 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
155 break;
156 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */
157 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */
158 case IP_VERSION(9, 5, 0): /* GC 9.5.0 */
159 kfd->device_info.event_interrupt_class =
160 &event_interrupt_class_v9_4_3;
161 break;
162 case IP_VERSION(10, 3, 1): /* VANGOGH */
163 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */
164 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */
165 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */
166 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */
167 case IP_VERSION(10, 1, 4):
168 case IP_VERSION(10, 1, 10): /* NAVI10 */
169 case IP_VERSION(10, 1, 2): /* NAVI12 */
170 case IP_VERSION(10, 1, 1): /* NAVI14 */
171 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */
172 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */
173 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */
174 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */
175 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10;
176 break;
177 case IP_VERSION(11, 0, 0):
178 case IP_VERSION(11, 0, 1):
179 case IP_VERSION(11, 0, 2):
180 case IP_VERSION(11, 0, 3):
181 case IP_VERSION(11, 0, 4):
182 case IP_VERSION(11, 5, 0):
183 case IP_VERSION(11, 5, 1):
184 case IP_VERSION(11, 5, 2):
185 case IP_VERSION(11, 5, 3):
186 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
187 break;
188 case IP_VERSION(12, 0, 0):
189 case IP_VERSION(12, 0, 1):
190 /* GFX12_TODO: Change to v12 version. */
191 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
192 break;
193 default:
194 dev_warn(kfd_device, "v9 event interrupt handler is set due to "
195 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version);
196 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
197 }
198 }
199
kfd_device_info_init(struct kfd_dev * kfd,bool vf,uint32_t gfx_target_version)200 static void kfd_device_info_init(struct kfd_dev *kfd,
201 bool vf, uint32_t gfx_target_version)
202 {
203 uint32_t gc_version = KFD_GC_VERSION(kfd);
204 uint32_t asic_type = kfd->adev->asic_type;
205
206 kfd->device_info.max_pasid_bits = 16;
207 kfd->device_info.max_no_of_hqd = 24;
208 kfd->device_info.num_of_watch_points = 4;
209 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED;
210 kfd->device_info.gfx_target_version = gfx_target_version;
211
212 if (KFD_IS_SOC15(kfd)) {
213 kfd->device_info.doorbell_size = 8;
214 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t);
215 kfd->device_info.supports_cwsr = true;
216
217 kfd_device_info_set_sdma_info(kfd);
218
219 kfd_device_info_set_event_interrupt_class(kfd);
220
221 if (gc_version < IP_VERSION(11, 0, 0)) {
222 /* Navi2x+, Navi1x+ */
223 if (gc_version == IP_VERSION(10, 3, 6))
224 kfd->device_info.no_atomic_fw_version = 14;
225 else if (gc_version == IP_VERSION(10, 3, 7))
226 kfd->device_info.no_atomic_fw_version = 3;
227 else if (gc_version >= IP_VERSION(10, 3, 0))
228 kfd->device_info.no_atomic_fw_version = 92;
229 else if (gc_version >= IP_VERSION(10, 1, 1))
230 kfd->device_info.no_atomic_fw_version = 145;
231
232 /* Navi1x+ */
233 if (gc_version >= IP_VERSION(10, 1, 1))
234 kfd->device_info.needs_pci_atomics = true;
235 } else if (gc_version < IP_VERSION(12, 0, 0)) {
236 /*
237 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires
238 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require
239 * PCIe atomics support.
240 */
241 kfd->device_info.needs_pci_atomics = true;
242 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0;
243 } else if (gc_version < IP_VERSION(13, 0, 0)) {
244 kfd->device_info.needs_pci_atomics = true;
245 kfd->device_info.no_atomic_fw_version = 2090;
246 } else {
247 kfd->device_info.needs_pci_atomics = true;
248 }
249 } else {
250 kfd->device_info.doorbell_size = 4;
251 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t);
252 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik;
253 kfd->device_info.num_sdma_queues_per_engine = 2;
254
255 if (asic_type != CHIP_KAVERI &&
256 asic_type != CHIP_HAWAII &&
257 asic_type != CHIP_TONGA)
258 kfd->device_info.supports_cwsr = true;
259
260 if (asic_type != CHIP_HAWAII && !vf)
261 kfd->device_info.needs_pci_atomics = true;
262 }
263 }
264
kgd2kfd_probe(struct amdgpu_device * adev,bool vf)265 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
266 {
267 struct kfd_dev *kfd = NULL;
268 const struct kfd2kgd_calls *f2g = NULL;
269 uint32_t gfx_target_version = 0;
270
271 switch (adev->asic_type) {
272 #ifdef CONFIG_DRM_AMDGPU_CIK
273 case CHIP_KAVERI:
274 gfx_target_version = 70000;
275 if (!vf)
276 f2g = &gfx_v7_kfd2kgd;
277 break;
278 #endif
279 case CHIP_CARRIZO:
280 gfx_target_version = 80001;
281 if (!vf)
282 f2g = &gfx_v8_kfd2kgd;
283 break;
284 #ifdef CONFIG_DRM_AMDGPU_CIK
285 case CHIP_HAWAII:
286 gfx_target_version = 70001;
287 if (!amdgpu_exp_hw_support)
288 pr_info(
289 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n"
290 );
291 else if (!vf)
292 f2g = &gfx_v7_kfd2kgd;
293 break;
294 #endif
295 case CHIP_TONGA:
296 gfx_target_version = 80002;
297 if (!vf)
298 f2g = &gfx_v8_kfd2kgd;
299 break;
300 case CHIP_FIJI:
301 case CHIP_POLARIS10:
302 gfx_target_version = 80003;
303 f2g = &gfx_v8_kfd2kgd;
304 break;
305 case CHIP_POLARIS11:
306 case CHIP_POLARIS12:
307 case CHIP_VEGAM:
308 gfx_target_version = 80003;
309 if (!vf)
310 f2g = &gfx_v8_kfd2kgd;
311 break;
312 default:
313 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
314 /* Vega 10 */
315 case IP_VERSION(9, 0, 1):
316 gfx_target_version = 90000;
317 f2g = &gfx_v9_kfd2kgd;
318 break;
319 /* Raven */
320 case IP_VERSION(9, 1, 0):
321 case IP_VERSION(9, 2, 2):
322 gfx_target_version = 90002;
323 if (!vf)
324 f2g = &gfx_v9_kfd2kgd;
325 break;
326 /* Vega12 */
327 case IP_VERSION(9, 2, 1):
328 gfx_target_version = 90004;
329 if (!vf)
330 f2g = &gfx_v9_kfd2kgd;
331 break;
332 /* Renoir */
333 case IP_VERSION(9, 3, 0):
334 gfx_target_version = 90012;
335 if (!vf)
336 f2g = &gfx_v9_kfd2kgd;
337 break;
338 /* Vega20 */
339 case IP_VERSION(9, 4, 0):
340 gfx_target_version = 90006;
341 if (!vf)
342 f2g = &gfx_v9_kfd2kgd;
343 break;
344 /* Arcturus */
345 case IP_VERSION(9, 4, 1):
346 gfx_target_version = 90008;
347 f2g = &arcturus_kfd2kgd;
348 break;
349 /* Aldebaran */
350 case IP_VERSION(9, 4, 2):
351 gfx_target_version = 90010;
352 f2g = &aldebaran_kfd2kgd;
353 break;
354 case IP_VERSION(9, 4, 3):
355 case IP_VERSION(9, 4, 4):
356 gfx_target_version = 90402;
357 f2g = &gc_9_4_3_kfd2kgd;
358 break;
359 case IP_VERSION(9, 5, 0):
360 gfx_target_version = 90500;
361 f2g = &gc_9_4_3_kfd2kgd;
362 break;
363 /* Navi10 */
364 case IP_VERSION(10, 1, 10):
365 gfx_target_version = 100100;
366 if (!vf)
367 f2g = &gfx_v10_kfd2kgd;
368 break;
369 /* Navi12 */
370 case IP_VERSION(10, 1, 2):
371 gfx_target_version = 100101;
372 f2g = &gfx_v10_kfd2kgd;
373 break;
374 /* Navi14 */
375 case IP_VERSION(10, 1, 1):
376 gfx_target_version = 100102;
377 if (!vf)
378 f2g = &gfx_v10_kfd2kgd;
379 break;
380 /* Cyan Skillfish */
381 case IP_VERSION(10, 1, 3):
382 case IP_VERSION(10, 1, 4):
383 gfx_target_version = 100103;
384 if (!vf)
385 f2g = &gfx_v10_kfd2kgd;
386 break;
387 /* Sienna Cichlid */
388 case IP_VERSION(10, 3, 0):
389 gfx_target_version = 100300;
390 f2g = &gfx_v10_3_kfd2kgd;
391 break;
392 /* Navy Flounder */
393 case IP_VERSION(10, 3, 2):
394 gfx_target_version = 100301;
395 f2g = &gfx_v10_3_kfd2kgd;
396 break;
397 /* Van Gogh */
398 case IP_VERSION(10, 3, 1):
399 gfx_target_version = 100303;
400 if (!vf)
401 f2g = &gfx_v10_3_kfd2kgd;
402 break;
403 /* Dimgrey Cavefish */
404 case IP_VERSION(10, 3, 4):
405 gfx_target_version = 100302;
406 f2g = &gfx_v10_3_kfd2kgd;
407 break;
408 /* Beige Goby */
409 case IP_VERSION(10, 3, 5):
410 gfx_target_version = 100304;
411 f2g = &gfx_v10_3_kfd2kgd;
412 break;
413 /* Yellow Carp */
414 case IP_VERSION(10, 3, 3):
415 gfx_target_version = 100305;
416 if (!vf)
417 f2g = &gfx_v10_3_kfd2kgd;
418 break;
419 case IP_VERSION(10, 3, 6):
420 case IP_VERSION(10, 3, 7):
421 gfx_target_version = 100306;
422 if (!vf)
423 f2g = &gfx_v10_3_kfd2kgd;
424 break;
425 case IP_VERSION(11, 0, 0):
426 gfx_target_version = 110000;
427 f2g = &gfx_v11_kfd2kgd;
428 break;
429 case IP_VERSION(11, 0, 1):
430 case IP_VERSION(11, 0, 4):
431 gfx_target_version = 110003;
432 f2g = &gfx_v11_kfd2kgd;
433 break;
434 case IP_VERSION(11, 0, 2):
435 gfx_target_version = 110002;
436 f2g = &gfx_v11_kfd2kgd;
437 break;
438 case IP_VERSION(11, 0, 3):
439 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */
440 gfx_target_version = 110001;
441 f2g = &gfx_v11_kfd2kgd;
442 break;
443 case IP_VERSION(11, 5, 0):
444 gfx_target_version = 110500;
445 f2g = &gfx_v11_kfd2kgd;
446 break;
447 case IP_VERSION(11, 5, 1):
448 gfx_target_version = 110501;
449 f2g = &gfx_v11_kfd2kgd;
450 break;
451 case IP_VERSION(11, 5, 2):
452 gfx_target_version = 110502;
453 f2g = &gfx_v11_kfd2kgd;
454 break;
455 case IP_VERSION(11, 5, 3):
456 gfx_target_version = 110503;
457 f2g = &gfx_v11_kfd2kgd;
458 break;
459 case IP_VERSION(12, 0, 0):
460 gfx_target_version = 120000;
461 f2g = &gfx_v12_kfd2kgd;
462 break;
463 case IP_VERSION(12, 0, 1):
464 gfx_target_version = 120001;
465 f2g = &gfx_v12_kfd2kgd;
466 break;
467 default:
468 break;
469 }
470 break;
471 }
472
473 if (!f2g) {
474 if (amdgpu_ip_version(adev, GC_HWIP, 0))
475 dev_info(kfd_device,
476 "GC IP %06x %s not supported in kfd\n",
477 amdgpu_ip_version(adev, GC_HWIP, 0),
478 vf ? "VF" : "");
479 else
480 dev_info(kfd_device, "%s %s not supported in kfd\n",
481 amdgpu_asic_name[adev->asic_type], vf ? "VF" : "");
482 return NULL;
483 }
484
485 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
486 if (!kfd)
487 return NULL;
488
489 kfd->adev = adev;
490 kfd_device_info_init(kfd, vf, gfx_target_version);
491 kfd->init_complete = false;
492 kfd->kfd2kgd = f2g;
493 atomic_set(&kfd->compute_profile, 0);
494
495 mutex_init(&kfd->doorbell_mutex);
496
497 ida_init(&kfd->doorbell_ida);
498 atomic_set(&kfd->kfd_processes_count, 0);
499
500 return kfd;
501 }
502
kfd_cwsr_init(struct kfd_dev * kfd)503 static void kfd_cwsr_init(struct kfd_dev *kfd)
504 {
505 if (cwsr_enable && kfd->device_info.supports_cwsr) {
506 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) {
507 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex)
508 > KFD_CWSR_TMA_OFFSET);
509 kfd->cwsr_isa = cwsr_trap_gfx8_hex;
510 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
511 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) {
512 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex)
513 > KFD_CWSR_TMA_OFFSET);
514 kfd->cwsr_isa = cwsr_trap_arcturus_hex;
515 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
516 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) {
517 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex)
518 > KFD_CWSR_TMA_OFFSET);
519 kfd->cwsr_isa = cwsr_trap_aldebaran_hex;
520 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex);
521 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) ||
522 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) {
523 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex)
524 > KFD_CWSR_TMA_OFFSET);
525 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex;
526 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex);
527 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 5, 0)) {
528 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_5_0_hex) > PAGE_SIZE);
529 kfd->cwsr_isa = cwsr_trap_gfx9_5_0_hex;
530 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_5_0_hex);
531 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) {
532 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex)
533 > KFD_CWSR_TMA_OFFSET);
534 kfd->cwsr_isa = cwsr_trap_gfx9_hex;
535 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
536 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) {
537 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex)
538 > KFD_CWSR_TMA_OFFSET);
539 kfd->cwsr_isa = cwsr_trap_nv1x_hex;
540 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
541 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) {
542 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex)
543 > KFD_CWSR_TMA_OFFSET);
544 kfd->cwsr_isa = cwsr_trap_gfx10_hex;
545 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
546 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) {
547 /* The gfx11 cwsr trap handler must fit inside a single
548 page. */
549 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE);
550 kfd->cwsr_isa = cwsr_trap_gfx11_hex;
551 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex);
552 } else {
553 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex)
554 > KFD_CWSR_TMA_OFFSET);
555 kfd->cwsr_isa = cwsr_trap_gfx12_hex;
556 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex);
557 }
558
559 kfd->cwsr_enabled = true;
560 }
561 }
562
kfd_gws_init(struct kfd_node * node)563 static int kfd_gws_init(struct kfd_node *node)
564 {
565 int ret = 0;
566 struct kfd_dev *kfd = node->kfd;
567 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
568
569 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
570 return 0;
571
572 if (hws_gws_support || (KFD_IS_SOC15(node) &&
573 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1)
574 && kfd->mec2_fw_version >= 0x81b3) ||
575 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0)
576 && kfd->mec2_fw_version >= 0x1b3) ||
577 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1)
578 && kfd->mec2_fw_version >= 0x30) ||
579 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2)
580 && kfd->mec2_fw_version >= 0x28) ||
581 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) ||
582 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) ||
583 (KFD_GC_VERSION(node) == IP_VERSION(9, 5, 0)) ||
584 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0)
585 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0)
586 && kfd->mec2_fw_version >= 0x6b) ||
587 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0)
588 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0)
589 && mes_rev >= 68) ||
590 (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0))))) {
591 if (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0))
592 node->adev->gds.gws_size = 64;
593 ret = amdgpu_amdkfd_alloc_gws(node->adev,
594 node->adev->gds.gws_size, &node->gws);
595 }
596
597 return ret;
598 }
599
kfd_smi_init(struct kfd_node * dev)600 static void kfd_smi_init(struct kfd_node *dev)
601 {
602 INIT_LIST_HEAD(&dev->smi_clients);
603 spin_lock_init(&dev->smi_lock);
604 }
605
kfd_init_node(struct kfd_node * node)606 static int kfd_init_node(struct kfd_node *node)
607 {
608 int err = -1;
609
610 if (kfd_interrupt_init(node)) {
611 dev_err(kfd_device, "Error initializing interrupts\n");
612 goto kfd_interrupt_error;
613 }
614
615 node->dqm = device_queue_manager_init(node);
616 if (!node->dqm) {
617 dev_err(kfd_device, "Error initializing queue manager\n");
618 goto device_queue_manager_error;
619 }
620
621 if (kfd_gws_init(node)) {
622 dev_err(kfd_device, "Could not allocate %d gws\n",
623 node->adev->gds.gws_size);
624 goto gws_error;
625 }
626
627 if (kfd_resume(node))
628 goto kfd_resume_error;
629
630 if (kfd_topology_add_device(node)) {
631 dev_err(kfd_device, "Error adding device to topology\n");
632 goto kfd_topology_add_device_error;
633 }
634
635 kfd_smi_init(node);
636
637 return 0;
638
639 kfd_topology_add_device_error:
640 kfd_resume_error:
641 gws_error:
642 device_queue_manager_uninit(node->dqm);
643 device_queue_manager_error:
644 kfd_interrupt_exit(node);
645 kfd_interrupt_error:
646 if (node->gws)
647 amdgpu_amdkfd_free_gws(node->adev, node->gws);
648
649 /* Cleanup the node memory here */
650 kfree(node);
651 return err;
652 }
653
kfd_cleanup_nodes(struct kfd_dev * kfd,unsigned int num_nodes)654 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes)
655 {
656 struct kfd_node *knode;
657 unsigned int i;
658
659 /*
660 * flush_work ensures that there are no outstanding
661 * work-queue items that will access interrupt_ring. New work items
662 * can't be created because we stopped interrupt handling above.
663 */
664 flush_workqueue(kfd->ih_wq);
665 destroy_workqueue(kfd->ih_wq);
666
667 for (i = 0; i < num_nodes; i++) {
668 knode = kfd->nodes[i];
669 device_queue_manager_uninit(knode->dqm);
670 kfd_interrupt_exit(knode);
671 kfd_topology_remove_device(knode);
672 if (knode->gws)
673 amdgpu_amdkfd_free_gws(knode->adev, knode->gws);
674 kfree(knode);
675 kfd->nodes[i] = NULL;
676 }
677 }
678
kfd_setup_interrupt_bitmap(struct kfd_node * node,unsigned int kfd_node_idx)679 static void kfd_setup_interrupt_bitmap(struct kfd_node *node,
680 unsigned int kfd_node_idx)
681 {
682 struct amdgpu_device *adev = node->adev;
683 uint32_t xcc_mask = node->xcc_mask;
684 uint32_t xcc, mapped_xcc;
685 /*
686 * Interrupt bitmap is setup for processing interrupts from
687 * different XCDs and AIDs.
688 * Interrupt bitmap is defined as follows:
689 * 1. Bits 0-15 - correspond to the NodeId field.
690 * Each bit corresponds to NodeId number. For example, if
691 * a KFD node has interrupt bitmap set to 0x7, then this
692 * KFD node will process interrupts with NodeId = 0, 1 and 2
693 * in the IH cookie.
694 * 2. Bits 16-31 - unused.
695 *
696 * Please note that the kfd_node_idx argument passed to this
697 * function is not related to NodeId field received in the
698 * IH cookie.
699 *
700 * In CPX mode, a KFD node will process an interrupt if:
701 * - the Node Id matches the corresponding bit set in
702 * Bits 0-15.
703 * - AND VMID reported in the interrupt lies within the
704 * VMID range of the node.
705 */
706 for_each_inst(xcc, xcc_mask) {
707 mapped_xcc = GET_INST(GC, xcc);
708 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2));
709 }
710 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx,
711 node->interrupt_bitmap);
712 }
713
kgd2kfd_device_init(struct kfd_dev * kfd,const struct kgd2kfd_shared_resources * gpu_resources)714 bool kgd2kfd_device_init(struct kfd_dev *kfd,
715 const struct kgd2kfd_shared_resources *gpu_resources)
716 {
717 unsigned int size, map_process_packet_size, i;
718 struct kfd_node *node;
719 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd;
720 unsigned int max_proc_per_quantum;
721 int partition_mode;
722 int xcp_idx;
723
724 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
725 KGD_ENGINE_MEC1);
726 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
727 KGD_ENGINE_MEC2);
728 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
729 KGD_ENGINE_SDMA1);
730 kfd->shared_resources = *gpu_resources;
731
732 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr);
733
734 if (kfd->num_nodes == 0) {
735 dev_err(kfd_device,
736 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n",
737 kfd->adev->gfx.num_xcc_per_xcp);
738 goto out;
739 }
740
741 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
742 * 32 and 64-bit requests are possible and must be
743 * supported.
744 */
745 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev);
746 if (!kfd->pci_atomic_requested &&
747 kfd->device_info.needs_pci_atomics &&
748 (!kfd->device_info.no_atomic_fw_version ||
749 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) {
750 dev_info(kfd_device,
751 "skipped device %x:%x, PCI rejects atomics %d<%d\n",
752 kfd->adev->pdev->vendor, kfd->adev->pdev->device,
753 kfd->mec_fw_version,
754 kfd->device_info.no_atomic_fw_version);
755 return false;
756 }
757
758 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
759 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
760 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1;
761
762 /* For multi-partition capable GPUs, we need special handling for VMIDs
763 * depending on partition mode.
764 * In CPX mode, the VMID range needs to be shared between XCDs.
765 * Additionally, there are 13 VMIDs (3-15) available for KFD. To
766 * divide them equally, we change starting VMID to 4 and not use
767 * VMID 3.
768 * If the VMID range changes for multi-partition capable GPUs, then
769 * this code MUST be revisited.
770 */
771 if (kfd->adev->xcp_mgr) {
772 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr,
773 AMDGPU_XCP_FL_LOCKED);
774 if (partition_mode == AMDGPU_CPX_PARTITION_MODE &&
775 kfd->num_nodes != 1) {
776 vmid_num_kfd /= 2;
777 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2;
778 }
779 }
780
781 /* Verify module parameters regarding mapped process number*/
782 if (hws_max_conc_proc >= 0)
783 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd);
784 else
785 max_proc_per_quantum = vmid_num_kfd;
786
787 /* calculate max size of mqds needed for queues */
788 size = max_num_of_queues_per_device *
789 kfd->device_info.mqd_size_aligned;
790
791 /*
792 * calculate max size of runlist packet.
793 * There can be only 2 packets at once
794 */
795 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ?
796 sizeof(struct pm4_mes_map_process_aldebaran) :
797 sizeof(struct pm4_mes_map_process);
798 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size +
799 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
800 + sizeof(struct pm4_mes_runlist)) * 2;
801
802 /* Add size of HIQ & DIQ */
803 size += KFD_KERNEL_QUEUE_SIZE * 2;
804
805 /* add another 512KB for all other allocations on gart (HPD, fences) */
806 size += 512 * 1024;
807
808 if (amdgpu_amdkfd_alloc_gtt_mem(
809 kfd->adev, size, &kfd->gtt_mem,
810 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
811 false)) {
812 dev_err(kfd_device, "Could not allocate %d bytes\n", size);
813 goto alloc_gtt_mem_failure;
814 }
815
816 dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
817
818 /* Initialize GTT sa with 512 byte chunk size */
819 if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
820 dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
821 goto kfd_gtt_sa_init_error;
822 }
823
824 if (kfd_doorbell_init(kfd)) {
825 dev_err(kfd_device,
826 "Error initializing doorbell aperture\n");
827 goto kfd_doorbell_error;
828 }
829
830 if (amdgpu_use_xgmi_p2p)
831 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id;
832
833 /*
834 * For multi-partition capable GPUs, the KFD abstracts all partitions
835 * within a socket as xGMI connected in the topology so assign a unique
836 * hive id per device based on the pci device location if device is in
837 * PCIe mode.
838 */
839 if (!kfd->hive_id && kfd->num_nodes > 1)
840 kfd->hive_id = pci_dev_id(kfd->adev->pdev);
841
842 kfd->noretry = kfd->adev->gmc.noretry;
843
844 kfd_cwsr_init(kfd);
845
846 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n",
847 kfd->num_nodes);
848
849 /* Allocate the KFD nodes */
850 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) {
851 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL);
852 if (!node)
853 goto node_alloc_error;
854
855 node->node_id = i;
856 node->adev = kfd->adev;
857 node->kfd = kfd;
858 node->kfd2kgd = kfd->kfd2kgd;
859 node->vm_info.vmid_num_kfd = vmid_num_kfd;
860 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx);
861 /* TODO : Check if error handling is needed */
862 if (node->xcp) {
863 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX,
864 &node->xcc_mask);
865 ++xcp_idx;
866 } else {
867 node->xcc_mask =
868 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1;
869 }
870
871 if (node->xcp) {
872 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n",
873 node->node_id, node->xcp->mem_id,
874 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20);
875 }
876
877 if (partition_mode == AMDGPU_CPX_PARTITION_MODE &&
878 kfd->num_nodes != 1) {
879 /* For multi-partition capable GPUs and CPX mode, first
880 * XCD gets VMID range 4-9 and second XCD gets VMID
881 * range 10-15.
882 */
883
884 node->vm_info.first_vmid_kfd = (i%2 == 0) ?
885 first_vmid_kfd :
886 first_vmid_kfd+vmid_num_kfd;
887 node->vm_info.last_vmid_kfd = (i%2 == 0) ?
888 last_vmid_kfd-vmid_num_kfd :
889 last_vmid_kfd;
890 node->compute_vmid_bitmap =
891 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) -
892 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1);
893 } else {
894 node->vm_info.first_vmid_kfd = first_vmid_kfd;
895 node->vm_info.last_vmid_kfd = last_vmid_kfd;
896 node->compute_vmid_bitmap =
897 gpu_resources->compute_vmid_bitmap;
898 }
899 node->max_proc_per_quantum = max_proc_per_quantum;
900 atomic_set(&node->sram_ecc_flag, 0);
901
902 amdgpu_amdkfd_get_local_mem_info(kfd->adev,
903 &node->local_mem_info, node->xcp);
904
905 if (kfd->adev->xcp_mgr)
906 kfd_setup_interrupt_bitmap(node, i);
907
908 /* Initialize the KFD node */
909 if (kfd_init_node(node)) {
910 dev_err(kfd_device, "Error initializing KFD node\n");
911 goto node_init_error;
912 }
913
914 spin_lock_init(&node->watch_points_lock);
915
916 kfd->nodes[i] = node;
917 }
918
919 svm_range_set_max_pages(kfd->adev);
920
921 kfd->init_complete = true;
922 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor,
923 kfd->adev->pdev->device);
924
925 pr_debug("Starting kfd with the following scheduling policy %d\n",
926 node->dqm->sched_policy);
927
928 goto out;
929
930 node_init_error:
931 node_alloc_error:
932 kfd_cleanup_nodes(kfd, i);
933 kfd_doorbell_fini(kfd);
934 kfd_doorbell_error:
935 kfd_gtt_sa_fini(kfd);
936 kfd_gtt_sa_init_error:
937 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem);
938 alloc_gtt_mem_failure:
939 dev_err(kfd_device,
940 "device %x:%x NOT added due to errors\n",
941 kfd->adev->pdev->vendor, kfd->adev->pdev->device);
942 out:
943 return kfd->init_complete;
944 }
945
kgd2kfd_device_exit(struct kfd_dev * kfd)946 void kgd2kfd_device_exit(struct kfd_dev *kfd)
947 {
948 if (kfd->init_complete) {
949 /* Cleanup KFD nodes */
950 kfd_cleanup_nodes(kfd, kfd->num_nodes);
951 /* Cleanup common/shared resources */
952 kfd_doorbell_fini(kfd);
953 ida_destroy(&kfd->doorbell_ida);
954 kfd_gtt_sa_fini(kfd);
955 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem);
956 }
957
958 kfree(kfd);
959 }
960
kgd2kfd_pre_reset(struct kfd_dev * kfd,struct amdgpu_reset_context * reset_context)961 int kgd2kfd_pre_reset(struct kfd_dev *kfd,
962 struct amdgpu_reset_context *reset_context)
963 {
964 struct kfd_node *node;
965 int i;
966
967 if (!kfd->init_complete)
968 return 0;
969
970 for (i = 0; i < kfd->num_nodes; i++) {
971 node = kfd->nodes[i];
972 kfd_smi_event_update_gpu_reset(node, false, reset_context);
973 }
974
975 kgd2kfd_suspend(kfd, true);
976
977 for (i = 0; i < kfd->num_nodes; i++)
978 kfd_signal_reset_event(kfd->nodes[i]);
979
980 return 0;
981 }
982
983 /*
984 * Fix me. KFD won't be able to resume existing process for now.
985 * We will keep all existing process in a evicted state and
986 * wait the process to be terminated.
987 */
988
kgd2kfd_post_reset(struct kfd_dev * kfd)989 int kgd2kfd_post_reset(struct kfd_dev *kfd)
990 {
991 int ret;
992 struct kfd_node *node;
993 int i;
994
995 if (!kfd->init_complete)
996 return 0;
997
998 for (i = 0; i < kfd->num_nodes; i++) {
999 ret = kfd_resume(kfd->nodes[i]);
1000 if (ret)
1001 return ret;
1002 }
1003
1004 mutex_lock(&kfd_processes_mutex);
1005 --kfd_locked;
1006 mutex_unlock(&kfd_processes_mutex);
1007
1008 for (i = 0; i < kfd->num_nodes; i++) {
1009 node = kfd->nodes[i];
1010 atomic_set(&node->sram_ecc_flag, 0);
1011 kfd_smi_event_update_gpu_reset(node, true, NULL);
1012 }
1013
1014 return 0;
1015 }
1016
kfd_is_locked(struct kfd_dev * kfd)1017 bool kfd_is_locked(struct kfd_dev *kfd)
1018 {
1019 uint8_t id = 0;
1020 struct kfd_node *dev;
1021
1022 lockdep_assert_held(&kfd_processes_mutex);
1023
1024 /* check reset/suspend lock */
1025 if (kfd_locked > 0)
1026 return true;
1027
1028 if (kfd)
1029 return kfd->kfd_dev_lock > 0;
1030
1031 /* check lock on all cgroup accessible devices */
1032 while (kfd_topology_enum_kfd_devices(id++, &dev) == 0) {
1033 if (!dev || kfd_devcgroup_check_permission(dev))
1034 continue;
1035
1036 if (dev->kfd->kfd_dev_lock > 0)
1037 return true;
1038 }
1039
1040 return false;
1041 }
1042
kgd2kfd_suspend(struct kfd_dev * kfd,bool suspend_proc)1043 void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc)
1044 {
1045 struct kfd_node *node;
1046 int i;
1047
1048 if (!kfd->init_complete)
1049 return;
1050
1051 if (suspend_proc)
1052 kgd2kfd_suspend_process(kfd);
1053
1054 for (i = 0; i < kfd->num_nodes; i++) {
1055 node = kfd->nodes[i];
1056 node->dqm->ops.stop(node->dqm);
1057 }
1058 }
1059
kgd2kfd_resume(struct kfd_dev * kfd,bool resume_proc)1060 int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc)
1061 {
1062 int ret, i;
1063
1064 if (!kfd->init_complete)
1065 return 0;
1066
1067 for (i = 0; i < kfd->num_nodes; i++) {
1068 ret = kfd_resume(kfd->nodes[i]);
1069 if (ret)
1070 return ret;
1071 }
1072
1073 if (resume_proc)
1074 ret = kgd2kfd_resume_process(kfd);
1075
1076 return ret;
1077 }
1078
kgd2kfd_suspend_process(struct kfd_dev * kfd)1079 void kgd2kfd_suspend_process(struct kfd_dev *kfd)
1080 {
1081 if (!kfd->init_complete)
1082 return;
1083
1084 mutex_lock(&kfd_processes_mutex);
1085 /* For first KFD device suspend all the KFD processes */
1086 if (++kfd_locked == 1)
1087 kfd_suspend_all_processes();
1088 mutex_unlock(&kfd_processes_mutex);
1089 }
1090
kgd2kfd_resume_process(struct kfd_dev * kfd)1091 int kgd2kfd_resume_process(struct kfd_dev *kfd)
1092 {
1093 int ret = 0;
1094
1095 if (!kfd->init_complete)
1096 return 0;
1097
1098 mutex_lock(&kfd_processes_mutex);
1099 if (--kfd_locked == 0)
1100 ret = kfd_resume_all_processes();
1101 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error");
1102 mutex_unlock(&kfd_processes_mutex);
1103
1104 return ret;
1105 }
1106
kfd_resume(struct kfd_node * node)1107 static int kfd_resume(struct kfd_node *node)
1108 {
1109 int err = 0;
1110
1111 err = node->dqm->ops.start(node->dqm);
1112 if (err)
1113 dev_err(kfd_device,
1114 "Error starting queue manager for device %x:%x\n",
1115 node->adev->pdev->vendor, node->adev->pdev->device);
1116
1117 return err;
1118 }
1119
1120 /* This is called directly from KGD at ISR. */
kgd2kfd_interrupt(struct kfd_dev * kfd,const void * ih_ring_entry)1121 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
1122 {
1123 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i;
1124 bool is_patched = false;
1125 unsigned long flags;
1126 struct kfd_node *node;
1127
1128 if (!kfd->init_complete)
1129 return;
1130
1131 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) {
1132 dev_err_once(kfd_device, "Ring entry too small\n");
1133 return;
1134 }
1135
1136 for (i = 0; i < kfd->num_nodes; i++) {
1137 /* Race if another thread in b/w
1138 * kfd_cleanup_nodes and kfree(kfd),
1139 * when kfd->nodes[i] = NULL
1140 */
1141 if (kfd->nodes[i])
1142 node = kfd->nodes[i];
1143 else
1144 return;
1145
1146 spin_lock_irqsave(&node->interrupt_lock, flags);
1147
1148 if (node->interrupts_active
1149 && interrupt_is_wanted(node, ih_ring_entry,
1150 patched_ihre, &is_patched)
1151 && enqueue_ih_ring_entry(node,
1152 is_patched ? patched_ihre : ih_ring_entry)) {
1153 queue_work(node->kfd->ih_wq, &node->interrupt_work);
1154 spin_unlock_irqrestore(&node->interrupt_lock, flags);
1155 return;
1156 }
1157 spin_unlock_irqrestore(&node->interrupt_lock, flags);
1158 }
1159
1160 }
1161
kgd2kfd_quiesce_mm(struct mm_struct * mm,uint32_t trigger)1162 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger)
1163 {
1164 struct kfd_process *p;
1165 int r;
1166
1167 /* Because we are called from arbitrary context (workqueue) as opposed
1168 * to process context, kfd_process could attempt to exit while we are
1169 * running so the lookup function increments the process ref count.
1170 */
1171 p = kfd_lookup_process_by_mm(mm);
1172 if (!p)
1173 return -ESRCH;
1174
1175 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
1176 r = kfd_process_evict_queues(p, trigger);
1177
1178 kfd_unref_process(p);
1179 return r;
1180 }
1181
kgd2kfd_resume_mm(struct mm_struct * mm)1182 int kgd2kfd_resume_mm(struct mm_struct *mm)
1183 {
1184 struct kfd_process *p;
1185 int r;
1186
1187 /* Because we are called from arbitrary context (workqueue) as opposed
1188 * to process context, kfd_process could attempt to exit while we are
1189 * running so the lookup function increments the process ref count.
1190 */
1191 p = kfd_lookup_process_by_mm(mm);
1192 if (!p)
1193 return -ESRCH;
1194
1195 r = kfd_process_restore_queues(p);
1196
1197 kfd_unref_process(p);
1198 return r;
1199 }
1200
1201 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
1202 * prepare for safe eviction of KFD BOs that belong to the specified
1203 * process.
1204 *
1205 * @mm: mm_struct that identifies the specified KFD process
1206 * @fence: eviction fence attached to KFD process BOs
1207 *
1208 */
kgd2kfd_schedule_evict_and_restore_process(struct mm_struct * mm,struct dma_fence * fence)1209 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
1210 struct dma_fence *fence)
1211 {
1212 struct kfd_process *p;
1213 unsigned long active_time;
1214 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
1215
1216 if (!fence)
1217 return -EINVAL;
1218
1219 if (dma_fence_is_signaled(fence))
1220 return 0;
1221
1222 p = kfd_lookup_process_by_mm(mm);
1223 if (!p)
1224 return -ENODEV;
1225
1226 if (fence->seqno == p->last_eviction_seqno)
1227 goto out;
1228
1229 p->last_eviction_seqno = fence->seqno;
1230
1231 /* Avoid KFD process starvation. Wait for at least
1232 * PROCESS_ACTIVE_TIME_MS before evicting the process again
1233 */
1234 active_time = get_jiffies_64() - p->last_restore_timestamp;
1235 if (delay_jiffies > active_time)
1236 delay_jiffies -= active_time;
1237 else
1238 delay_jiffies = 0;
1239
1240 /* During process initialization eviction_work.dwork is initialized
1241 * to kfd_evict_bo_worker
1242 */
1243 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies",
1244 p->lead_thread->pid, delay_jiffies);
1245 schedule_delayed_work(&p->eviction_work, delay_jiffies);
1246 out:
1247 kfd_unref_process(p);
1248 return 0;
1249 }
1250
kfd_gtt_sa_init(struct kfd_dev * kfd,unsigned int buf_size,unsigned int chunk_size)1251 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
1252 unsigned int chunk_size)
1253 {
1254 if (WARN_ON(buf_size < chunk_size))
1255 return -EINVAL;
1256 if (WARN_ON(buf_size == 0))
1257 return -EINVAL;
1258 if (WARN_ON(chunk_size == 0))
1259 return -EINVAL;
1260
1261 kfd->gtt_sa_chunk_size = chunk_size;
1262 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
1263
1264 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks,
1265 GFP_KERNEL);
1266 if (!kfd->gtt_sa_bitmap)
1267 return -ENOMEM;
1268
1269 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
1270 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
1271
1272 mutex_init(&kfd->gtt_sa_lock);
1273
1274 return 0;
1275 }
1276
kfd_gtt_sa_fini(struct kfd_dev * kfd)1277 static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
1278 {
1279 mutex_destroy(&kfd->gtt_sa_lock);
1280 bitmap_free(kfd->gtt_sa_bitmap);
1281 }
1282
kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,unsigned int bit_num,unsigned int chunk_size)1283 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
1284 unsigned int bit_num,
1285 unsigned int chunk_size)
1286 {
1287 return start_addr + bit_num * chunk_size;
1288 }
1289
kfd_gtt_sa_calc_cpu_addr(void * start_addr,unsigned int bit_num,unsigned int chunk_size)1290 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
1291 unsigned int bit_num,
1292 unsigned int chunk_size)
1293 {
1294 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
1295 }
1296
kfd_gtt_sa_allocate(struct kfd_node * node,unsigned int size,struct kfd_mem_obj ** mem_obj)1297 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size,
1298 struct kfd_mem_obj **mem_obj)
1299 {
1300 unsigned int found, start_search, cur_size;
1301 struct kfd_dev *kfd = node->kfd;
1302
1303 if (size == 0)
1304 return -EINVAL;
1305
1306 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
1307 return -ENOMEM;
1308
1309 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
1310 if (!(*mem_obj))
1311 return -ENOMEM;
1312
1313 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
1314
1315 start_search = 0;
1316
1317 mutex_lock(&kfd->gtt_sa_lock);
1318
1319 kfd_gtt_restart_search:
1320 /* Find the first chunk that is free */
1321 found = find_next_zero_bit(kfd->gtt_sa_bitmap,
1322 kfd->gtt_sa_num_of_chunks,
1323 start_search);
1324
1325 pr_debug("Found = %d\n", found);
1326
1327 /* If there wasn't any free chunk, bail out */
1328 if (found == kfd->gtt_sa_num_of_chunks)
1329 goto kfd_gtt_no_free_chunk;
1330
1331 /* Update fields of mem_obj */
1332 (*mem_obj)->range_start = found;
1333 (*mem_obj)->range_end = found;
1334 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
1335 kfd->gtt_start_gpu_addr,
1336 found,
1337 kfd->gtt_sa_chunk_size);
1338 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
1339 kfd->gtt_start_cpu_ptr,
1340 found,
1341 kfd->gtt_sa_chunk_size);
1342
1343 pr_debug("gpu_addr = %p, cpu_addr = %p\n",
1344 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
1345
1346 /* If we need only one chunk, mark it as allocated and get out */
1347 if (size <= kfd->gtt_sa_chunk_size) {
1348 pr_debug("Single bit\n");
1349 __set_bit(found, kfd->gtt_sa_bitmap);
1350 goto kfd_gtt_out;
1351 }
1352
1353 /* Otherwise, try to see if we have enough contiguous chunks */
1354 cur_size = size - kfd->gtt_sa_chunk_size;
1355 do {
1356 (*mem_obj)->range_end =
1357 find_next_zero_bit(kfd->gtt_sa_bitmap,
1358 kfd->gtt_sa_num_of_chunks, ++found);
1359 /*
1360 * If next free chunk is not contiguous than we need to
1361 * restart our search from the last free chunk we found (which
1362 * wasn't contiguous to the previous ones
1363 */
1364 if ((*mem_obj)->range_end != found) {
1365 start_search = found;
1366 goto kfd_gtt_restart_search;
1367 }
1368
1369 /*
1370 * If we reached end of buffer, bail out with error
1371 */
1372 if (found == kfd->gtt_sa_num_of_chunks)
1373 goto kfd_gtt_no_free_chunk;
1374
1375 /* Check if we don't need another chunk */
1376 if (cur_size <= kfd->gtt_sa_chunk_size)
1377 cur_size = 0;
1378 else
1379 cur_size -= kfd->gtt_sa_chunk_size;
1380
1381 } while (cur_size > 0);
1382
1383 pr_debug("range_start = %d, range_end = %d\n",
1384 (*mem_obj)->range_start, (*mem_obj)->range_end);
1385
1386 /* Mark the chunks as allocated */
1387 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start,
1388 (*mem_obj)->range_end - (*mem_obj)->range_start + 1);
1389
1390 kfd_gtt_out:
1391 mutex_unlock(&kfd->gtt_sa_lock);
1392 return 0;
1393
1394 kfd_gtt_no_free_chunk:
1395 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj);
1396 mutex_unlock(&kfd->gtt_sa_lock);
1397 kfree(*mem_obj);
1398 return -ENOMEM;
1399 }
1400
kfd_gtt_sa_free(struct kfd_node * node,struct kfd_mem_obj * mem_obj)1401 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj)
1402 {
1403 struct kfd_dev *kfd = node->kfd;
1404
1405 /* Act like kfree when trying to free a NULL object */
1406 if (!mem_obj)
1407 return 0;
1408
1409 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
1410 mem_obj, mem_obj->range_start, mem_obj->range_end);
1411
1412 mutex_lock(&kfd->gtt_sa_lock);
1413
1414 /* Mark the chunks as free */
1415 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start,
1416 mem_obj->range_end - mem_obj->range_start + 1);
1417
1418 mutex_unlock(&kfd->gtt_sa_lock);
1419
1420 kfree(mem_obj);
1421 return 0;
1422 }
1423
kgd2kfd_set_sram_ecc_flag(struct kfd_dev * kfd)1424 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
1425 {
1426 /*
1427 * TODO: Currently update SRAM ECC flag for first node.
1428 * This needs to be updated later when we can
1429 * identify SRAM ECC error on other nodes also.
1430 */
1431 if (kfd)
1432 atomic_inc(&kfd->nodes[0]->sram_ecc_flag);
1433 }
1434
kfd_inc_compute_active(struct kfd_node * node)1435 void kfd_inc_compute_active(struct kfd_node *node)
1436 {
1437 if (atomic_inc_return(&node->kfd->compute_profile) == 1)
1438 amdgpu_amdkfd_set_compute_idle(node->adev, false);
1439 }
1440
kfd_dec_compute_active(struct kfd_node * node)1441 void kfd_dec_compute_active(struct kfd_node *node)
1442 {
1443 int count = atomic_dec_return(&node->kfd->compute_profile);
1444
1445 if (count == 0)
1446 amdgpu_amdkfd_set_compute_idle(node->adev, true);
1447 WARN_ONCE(count < 0, "Compute profile ref. count error");
1448 }
1449
kfd_compute_active(struct kfd_node * node)1450 static bool kfd_compute_active(struct kfd_node *node)
1451 {
1452 if (atomic_read(&node->kfd->compute_profile))
1453 return true;
1454 return false;
1455 }
1456
kgd2kfd_smi_event_throttle(struct kfd_dev * kfd,uint64_t throttle_bitmask)1457 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
1458 {
1459 /*
1460 * TODO: For now, raise the throttling event only on first node.
1461 * This will need to change after we are able to determine
1462 * which node raised the throttling event.
1463 */
1464 if (kfd && kfd->init_complete)
1465 kfd_smi_event_update_thermal_throttling(kfd->nodes[0],
1466 throttle_bitmask);
1467 }
1468
1469 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and
1470 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA.
1471 * When the device has more than two engines, we reserve two for PCIe to enable
1472 * full-duplex and the rest are used as XGMI.
1473 */
kfd_get_num_sdma_engines(struct kfd_node * node)1474 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node)
1475 {
1476 /* If XGMI is not supported, all SDMA engines are PCIe */
1477 if (!node->adev->gmc.xgmi.supported)
1478 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes;
1479
1480 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2);
1481 }
1482
kfd_get_num_xgmi_sdma_engines(struct kfd_node * node)1483 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node)
1484 {
1485 /* After reserved for PCIe, the rest of engines are XGMI */
1486 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes -
1487 kfd_get_num_sdma_engines(node);
1488 }
1489
kgd2kfd_check_and_lock_kfd(struct kfd_dev * kfd)1490 int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd)
1491 {
1492 struct kfd_process *p;
1493 int r = 0, temp, idx;
1494
1495 mutex_lock(&kfd_processes_mutex);
1496
1497 /* kfd_processes_count is per kfd_dev, return -EBUSY without
1498 * further check
1499 */
1500 if (!!atomic_read(&kfd->kfd_processes_count)) {
1501 pr_debug("process_wq_release not finished\n");
1502 r = -EBUSY;
1503 goto out;
1504 }
1505
1506 if (hash_empty(kfd_processes_table) && !kfd_is_locked(kfd))
1507 goto out;
1508
1509 /* fail under system reset/resume or kfd device is partition switching. */
1510 if (kfd_is_locked(kfd)) {
1511 r = -EBUSY;
1512 goto out;
1513 }
1514
1515 /*
1516 * ensure all running processes are cgroup excluded from device before mode switch.
1517 * i.e. no pdd was created on the process socket.
1518 */
1519 idx = srcu_read_lock(&kfd_processes_srcu);
1520 hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
1521 int i;
1522
1523 for (i = 0; i < p->n_pdds; i++) {
1524 if (p->pdds[i]->dev->kfd != kfd)
1525 continue;
1526
1527 r = -EBUSY;
1528 goto proc_check_unlock;
1529 }
1530 }
1531
1532 proc_check_unlock:
1533 srcu_read_unlock(&kfd_processes_srcu, idx);
1534 out:
1535 if (!r)
1536 ++kfd->kfd_dev_lock;
1537 mutex_unlock(&kfd_processes_mutex);
1538
1539 return r;
1540 }
1541
kgd2kfd_unlock_kfd(struct kfd_dev * kfd)1542 void kgd2kfd_unlock_kfd(struct kfd_dev *kfd)
1543 {
1544 mutex_lock(&kfd_processes_mutex);
1545 --kfd->kfd_dev_lock;
1546 mutex_unlock(&kfd_processes_mutex);
1547 }
1548
kgd2kfd_start_sched(struct kfd_dev * kfd,uint32_t node_id)1549 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id)
1550 {
1551 struct kfd_node *node;
1552 int ret;
1553
1554 if (!kfd->init_complete)
1555 return 0;
1556
1557 if (node_id >= kfd->num_nodes) {
1558 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n",
1559 node_id, kfd->num_nodes - 1);
1560 return -EINVAL;
1561 }
1562 node = kfd->nodes[node_id];
1563
1564 ret = node->dqm->ops.unhalt(node->dqm);
1565 if (ret)
1566 dev_err(kfd_device, "Error in starting scheduler\n");
1567
1568 return ret;
1569 }
1570
kgd2kfd_start_sched_all_nodes(struct kfd_dev * kfd)1571 int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd)
1572 {
1573 struct kfd_node *node;
1574 int i, r;
1575
1576 if (!kfd->init_complete)
1577 return 0;
1578
1579 for (i = 0; i < kfd->num_nodes; i++) {
1580 node = kfd->nodes[i];
1581 r = node->dqm->ops.unhalt(node->dqm);
1582 if (r) {
1583 dev_err(kfd_device, "Error in starting scheduler\n");
1584 return r;
1585 }
1586 }
1587 return 0;
1588 }
1589
kgd2kfd_stop_sched(struct kfd_dev * kfd,uint32_t node_id)1590 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id)
1591 {
1592 struct kfd_node *node;
1593
1594 if (!kfd->init_complete)
1595 return 0;
1596
1597 if (node_id >= kfd->num_nodes) {
1598 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n",
1599 node_id, kfd->num_nodes - 1);
1600 return -EINVAL;
1601 }
1602
1603 node = kfd->nodes[node_id];
1604 return node->dqm->ops.halt(node->dqm);
1605 }
1606
kgd2kfd_stop_sched_all_nodes(struct kfd_dev * kfd)1607 int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd)
1608 {
1609 struct kfd_node *node;
1610 int i, r;
1611
1612 if (!kfd->init_complete)
1613 return 0;
1614
1615 for (i = 0; i < kfd->num_nodes; i++) {
1616 node = kfd->nodes[i];
1617 r = node->dqm->ops.halt(node->dqm);
1618 if (r)
1619 return r;
1620 }
1621 return 0;
1622 }
1623
kgd2kfd_compute_active(struct kfd_dev * kfd,uint32_t node_id)1624 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id)
1625 {
1626 struct kfd_node *node;
1627
1628 if (!kfd->init_complete)
1629 return false;
1630
1631 if (node_id >= kfd->num_nodes) {
1632 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n",
1633 node_id, kfd->num_nodes - 1);
1634 return false;
1635 }
1636
1637 node = kfd->nodes[node_id];
1638
1639 return kfd_compute_active(node);
1640 }
1641
1642 /**
1643 * kgd2kfd_vmfault_fast_path() - KFD vm page fault interrupt handling fast path for gmc v9
1644 * @adev: amdgpu device
1645 * @entry: vm fault interrupt vector
1646 * @retry_fault: if this is retry fault
1647 *
1648 * retry fault -
1649 * with CAM enabled, adev primary ring
1650 * | gmc_v9_0_process_interrupt()
1651 * adev soft_ring
1652 * | gmc_v9_0_process_interrupt() worker failed to recover page fault
1653 * KFD node ih_fifo
1654 * | KFD interrupt_wq worker
1655 * kfd_signal_vm_fault_event
1656 *
1657 * without CAM, adev primary ring1
1658 * | gmc_v9_0_process_interrupt worker failed to recvoer page fault
1659 * KFD node ih_fifo
1660 * | KFD interrupt_wq worker
1661 * kfd_signal_vm_fault_event
1662 *
1663 * no-retry fault -
1664 * adev primary ring
1665 * | gmc_v9_0_process_interrupt()
1666 * KFD node ih_fifo
1667 * | KFD interrupt_wq worker
1668 * kfd_signal_vm_fault_event
1669 *
1670 * fast path - After kfd_signal_vm_fault_event, gmc_v9_0_process_interrupt drop the page fault
1671 * of same process, don't copy interrupt to KFD node ih_fifo.
1672 * With gdb debugger enabled, need convert the retry fault to no-retry fault for
1673 * debugger, cannot use the fast path.
1674 *
1675 * Return:
1676 * true - use the fast path to handle this fault
1677 * false - use normal path to handle it
1678 */
kgd2kfd_vmfault_fast_path(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry,bool retry_fault)1679 bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry,
1680 bool retry_fault)
1681 {
1682 struct kfd_process *p;
1683 u32 cam_index;
1684
1685 if (entry->ih == &adev->irq.ih_soft || entry->ih == &adev->irq.ih1) {
1686 p = kfd_lookup_process_by_pasid(entry->pasid, NULL);
1687 if (!p)
1688 return true;
1689
1690 if (p->gpu_page_fault && !p->debug_trap_enabled) {
1691 if (retry_fault && adev->irq.retry_cam_enabled) {
1692 cam_index = entry->src_data[2] & 0x3ff;
1693 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index);
1694 }
1695
1696 kfd_unref_process(p);
1697 return true;
1698 }
1699
1700 /*
1701 * This is the first page fault, set flag and then signal user space
1702 */
1703 p->gpu_page_fault = true;
1704 kfd_unref_process(p);
1705 }
1706 return false;
1707 }
1708
1709 #if defined(CONFIG_DEBUG_FS)
1710
1711 /* This function will send a package to HIQ to hang the HWS
1712 * which will trigger a GPU reset and bring the HWS back to normal state
1713 */
kfd_debugfs_hang_hws(struct kfd_node * dev)1714 int kfd_debugfs_hang_hws(struct kfd_node *dev)
1715 {
1716 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1717 pr_err("HWS is not enabled");
1718 return -EINVAL;
1719 }
1720
1721 if (dev->kfd->shared_resources.enable_mes) {
1722 dev_err(dev->adev->dev, "Inducing MES hang is not supported\n");
1723 return -EINVAL;
1724 }
1725
1726 return dqm_debugfs_hang_hws(dev->dqm);
1727 }
1728
1729 #endif
1730