1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree:
4 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5 * Copyright (c) 2025, Eugene Lepshy <fekz115@gmail.com>
6 * Copyright (c) 2025, Danila Tikhonov <danila@jiaxyga.com>
7 */
8
9 #include <linux/backlight.h>
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/module.h>
13 #include <linux/regulator/consumer.h>
14
15 #include <video/mipi_display.h>
16
17 #include <drm/display/drm_dsc.h>
18 #include <drm/display/drm_dsc_helper.h>
19 #include <drm/drm_mipi_dsi.h>
20 #include <drm/drm_modes.h>
21 #include <drm/drm_panel.h>
22 #include <drm/drm_probe_helper.h>
23
24 struct visionox_rm692e5 {
25 struct drm_panel panel;
26 struct mipi_dsi_device *dsi;
27 struct drm_dsc_config dsc;
28 struct gpio_desc *reset_gpio;
29 struct regulator_bulk_data *supplies;
30 };
31
32 static const struct regulator_bulk_data visionox_rm692e5_supplies[] = {
33 { .supply = "vddio" }, /* 1p8 */
34 { .supply = "vdd" }, /* 3p3 */
35 };
36
37 static inline
to_visionox_rm692e5(struct drm_panel * panel)38 struct visionox_rm692e5 *to_visionox_rm692e5(struct drm_panel *panel)
39 {
40 return container_of(panel, struct visionox_rm692e5, panel);
41 }
42
visionox_rm692e5_reset(struct visionox_rm692e5 * ctx)43 static void visionox_rm692e5_reset(struct visionox_rm692e5 *ctx)
44 {
45 gpiod_set_value_cansleep(ctx->reset_gpio, 0);
46 usleep_range(10000, 11000);
47 gpiod_set_value_cansleep(ctx->reset_gpio, 1);
48 usleep_range(1000, 2000);
49 gpiod_set_value_cansleep(ctx->reset_gpio, 0);
50 msleep(32);
51 }
52
visionox_rm692e5_on(struct visionox_rm692e5 * ctx)53 static int visionox_rm692e5_on(struct visionox_rm692e5 *ctx)
54 {
55 struct mipi_dsi_device *dsi = ctx->dsi;
56 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
57
58 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
59
60 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x40);
61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbd, 0x07);
62 mipi_dsi_usleep_range(&dsi_ctx, 17000, 18000);
63 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0xd2);
64 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x11);
65 mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x00ab);
66 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x30);
67 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x09);
68 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x60);
69 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x04);
70 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x38);
71 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x00);
72 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x14);
73 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x02);
74 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1c);
75 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x02);
76 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x00);
77 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0x20);
78 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x01);
79 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0xe8);
80 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x00);
81 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x07);
82 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x0c);
83 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x05);
84 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x0e);
85 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x05);
86 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x16);
87 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x18);
88 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x00);
89 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x10);
90 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0xf0);
91 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x07);
92 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x10);
93 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x20);
94 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x00);
95 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x06);
96 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x0f);
97 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x0f);
98 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x33);
99 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x0e);
100 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x1c);
101 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2a);
102 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x38);
103 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x46);
104 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x54);
105 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x62);
106 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x69);
107 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x70);
108 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x77);
109 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x79);
110 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x7b);
111 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x7d);
112 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x7e);
113 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x01);
114 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x83, 0x02);
115 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x84, 0x22);
116 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x85, 0x00);
117 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x86, 0x2a);
118 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x87, 0x40);
119 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x88, 0x2a);
120 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x89, 0xbe);
121 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8a, 0x3a);
122 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8b, 0xfc);
123 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8c, 0x3a);
124 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8d, 0xfa);
125 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8e, 0x3a);
126 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8f, 0xf8);
127 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x3b);
128 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x91, 0x38);
129 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x92, 0x3b);
130 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x93, 0x78);
131 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x94, 0x3b);
132 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x95, 0xb6);
133 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x96, 0x4b);
134 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x97, 0xf6);
135 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x98, 0x4c);
136 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x99, 0x34);
137 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9a, 0x4c);
138 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9b, 0x74);
139 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9c, 0x5c);
140 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9d, 0x74);
141 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9e, 0x8c);
142 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9f, 0xf4);
143 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_READ_PPS_START, 0x02);
144 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa3, 0x1c);
145 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa4, 0x00);
146 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa5, 0x00);
147 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa6, 0x00);
148 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa7, 0x00);
149 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_READ_PPS_CONTINUE, 0x00);
150 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xaa, 0x00);
151 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa0, 0x80);
152 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0xa1);
153 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcd, 0x6b);
154 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xce, 0xbb);
155 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0xd1);
156 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4, 0x01);
157 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x38);
158 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x0f);
159 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x0f);
160 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x00);
161 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfa, 0x01);
162 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc2, 0x08);
163 mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
164 mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x000d);
165 mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
166 mipi_dsi_msleep(&dsi_ctx, 50);
167 mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
168 mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000);
169
170 return dsi_ctx.accum_err;
171 }
172
visionox_rm692e5_disable(struct drm_panel * panel)173 static int visionox_rm692e5_disable(struct drm_panel *panel)
174 {
175 struct visionox_rm692e5 *ctx = to_visionox_rm692e5(panel);
176 struct mipi_dsi_device *dsi = ctx->dsi;
177 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
178
179 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
180
181 mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
182 mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000);
183 mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
184 mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000);
185
186 return dsi_ctx.accum_err;
187 }
188
visionox_rm692e5_prepare(struct drm_panel * panel)189 static int visionox_rm692e5_prepare(struct drm_panel *panel)
190 {
191 struct visionox_rm692e5 *ctx = to_visionox_rm692e5(panel);
192 struct drm_dsc_picture_parameter_set pps;
193 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
194 int ret;
195
196 ret = regulator_bulk_enable(ARRAY_SIZE(visionox_rm692e5_supplies),
197 ctx->supplies);
198 if (ret < 0)
199 return ret;
200
201 visionox_rm692e5_reset(ctx);
202
203 ret = visionox_rm692e5_on(ctx);
204 if (ret < 0) {
205 gpiod_set_value_cansleep(ctx->reset_gpio, 1);
206 goto err;
207 }
208
209 drm_dsc_pps_payload_pack(&pps, &ctx->dsc);
210 mipi_dsi_picture_parameter_set_multi(&dsi_ctx, &pps);
211 mipi_dsi_compression_mode_ext_multi(&dsi_ctx, true, MIPI_DSI_COMPRESSION_DSC, 0);
212
213 mipi_dsi_msleep(&dsi_ctx, 28);
214
215 if (dsi_ctx.accum_err < 0) {
216 ret = dsi_ctx.accum_err;
217 goto err;
218 }
219
220 return dsi_ctx.accum_err;
221 err:
222 regulator_bulk_disable(ARRAY_SIZE(visionox_rm692e5_supplies),
223 ctx->supplies);
224 return ret;
225 }
226
visionox_rm692e5_unprepare(struct drm_panel * panel)227 static int visionox_rm692e5_unprepare(struct drm_panel *panel)
228 {
229 struct visionox_rm692e5 *ctx = to_visionox_rm692e5(panel);
230
231 gpiod_set_value_cansleep(ctx->reset_gpio, 1);
232 regulator_bulk_disable(ARRAY_SIZE(visionox_rm692e5_supplies),
233 ctx->supplies);
234
235 return 0;
236 }
237
238 static const struct drm_display_mode visionox_rm692e5_modes[] = {
239 /* Let's initialize the highest frequency first */
240 { /* 120Hz mode */
241 .clock = (1080 + 26 + 39 + 36) * (2400 + 16 + 21 + 16) * 120 / 1000,
242 .hdisplay = 1080,
243 .hsync_start = 1080 + 26,
244 .hsync_end = 1080 + 26 + 39,
245 .htotal = 1080 + 26 + 39 + 36,
246 .vdisplay = 2400,
247 .vsync_start = 2400 + 16,
248 .vsync_end = 2400 + 16 + 21,
249 .vtotal = 2400 + 16 + 21 + 16,
250 .width_mm = 68,
251 .height_mm = 152,
252 .type = DRM_MODE_TYPE_DRIVER,
253 },
254 { /* 90Hz mode */
255 .clock = (1080 + 26 + 39 + 36) * (2400 + 16 + 21 + 16) * 90 / 1000,
256 .hdisplay = 1080,
257 .hsync_start = 1080 + 26,
258 .hsync_end = 1080 + 26 + 39,
259 .htotal = 1080 + 26 + 39 + 36,
260 .vdisplay = 2400,
261 .vsync_start = 2400 + 16,
262 .vsync_end = 2400 + 16 + 21,
263 .vtotal = 2400 + 16 + 21 + 16,
264 .width_mm = 68,
265 .height_mm = 152,
266 .type = DRM_MODE_TYPE_DRIVER,
267 },
268 { /* 60Hz mode */
269 .clock = (1080 + 26 + 39 + 36) * (2400 + 16 + 21 + 16) * 60 / 1000,
270 .hdisplay = 1080,
271 .hsync_start = 1080 + 26,
272 .hsync_end = 1080 + 26 + 39,
273 .htotal = 1080 + 26 + 39 + 36,
274 .vdisplay = 2400,
275 .vsync_start = 2400 + 16,
276 .vsync_end = 2400 + 16 + 21,
277 .vtotal = 2400 + 16 + 21 + 16,
278 .width_mm = 68,
279 .height_mm = 152,
280 .type = DRM_MODE_TYPE_DRIVER,
281 },
282 };
283
visionox_rm692e5_get_modes(struct drm_panel * panel,struct drm_connector * connector)284 static int visionox_rm692e5_get_modes(struct drm_panel *panel,
285 struct drm_connector *connector)
286 {
287 int count = 0;
288
289 for (int i = 0; i < ARRAY_SIZE(visionox_rm692e5_modes); i++)
290 count += drm_connector_helper_get_modes_fixed(connector,
291 &visionox_rm692e5_modes[i]);
292
293 return count;
294 }
295
296 static const struct drm_panel_funcs visionox_rm692e5_panel_funcs = {
297 .prepare = visionox_rm692e5_prepare,
298 .unprepare = visionox_rm692e5_unprepare,
299 .disable = visionox_rm692e5_disable,
300 .get_modes = visionox_rm692e5_get_modes,
301 };
302
visionox_rm692e5_bl_update_status(struct backlight_device * bl)303 static int visionox_rm692e5_bl_update_status(struct backlight_device *bl)
304 {
305 struct mipi_dsi_device *dsi = bl_get_data(bl);
306 u16 brightness = backlight_get_brightness(bl);
307 int ret;
308
309 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
310
311 ret = mipi_dsi_dcs_set_display_brightness_large(dsi, brightness);
312 if (ret < 0)
313 return ret;
314
315 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
316
317 return 0;
318 }
319
visionox_rm692e5_bl_get_brightness(struct backlight_device * bl)320 static int visionox_rm692e5_bl_get_brightness(struct backlight_device *bl)
321 {
322 struct mipi_dsi_device *dsi = bl_get_data(bl);
323 u16 brightness;
324 int ret;
325
326 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
327
328 ret = mipi_dsi_dcs_get_display_brightness_large(dsi, &brightness);
329 if (ret < 0)
330 return ret;
331
332 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
333
334 return brightness;
335 }
336
337 static const struct backlight_ops visionox_rm692e5_bl_ops = {
338 .update_status = visionox_rm692e5_bl_update_status,
339 .get_brightness = visionox_rm692e5_bl_get_brightness,
340 };
341
342 static struct backlight_device *
visionox_rm692e5_create_backlight(struct mipi_dsi_device * dsi)343 visionox_rm692e5_create_backlight(struct mipi_dsi_device *dsi)
344 {
345 struct device *dev = &dsi->dev;
346 const struct backlight_properties props = {
347 .type = BACKLIGHT_RAW,
348 .brightness = 2047,
349 .max_brightness = 4095,
350 };
351
352 return devm_backlight_device_register(dev, dev_name(dev), dev, dsi,
353 &visionox_rm692e5_bl_ops, &props);
354 }
355
visionox_rm692e5_probe(struct mipi_dsi_device * dsi)356 static int visionox_rm692e5_probe(struct mipi_dsi_device *dsi)
357 {
358 struct device *dev = &dsi->dev;
359 struct visionox_rm692e5 *ctx;
360 int ret;
361
362 ctx = devm_drm_panel_alloc(dev, struct visionox_rm692e5, panel,
363 &visionox_rm692e5_panel_funcs,
364 DRM_MODE_CONNECTOR_DSI);
365 if (IS_ERR(ctx))
366 return PTR_ERR(ctx);
367
368 ret = devm_regulator_bulk_get_const(&dsi->dev,
369 ARRAY_SIZE(visionox_rm692e5_supplies),
370 visionox_rm692e5_supplies,
371 &ctx->supplies);
372 if (ret < 0)
373 return dev_err_probe(dev, ret, "Failed to get regulators\n");
374
375 ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
376 if (IS_ERR(ctx->reset_gpio))
377 return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio),
378 "Failed to get reset-gpios\n");
379
380 ctx->dsi = dsi;
381 mipi_dsi_set_drvdata(dsi, ctx);
382
383 dsi->lanes = 4;
384 dsi->format = MIPI_DSI_FMT_RGB888;
385 dsi->mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS;
386
387 ctx->panel.prepare_prev_first = true;
388
389 ctx->panel.backlight = visionox_rm692e5_create_backlight(dsi);
390 if (IS_ERR(ctx->panel.backlight))
391 return dev_err_probe(dev, PTR_ERR(ctx->panel.backlight),
392 "Failed to create backlight\n");
393
394 drm_panel_add(&ctx->panel);
395
396 dsi->dsc = &ctx->dsc;
397 ctx->dsc.dsc_version_major = 1;
398 ctx->dsc.dsc_version_minor = 1;
399 ctx->dsc.slice_height = 20;
400 ctx->dsc.slice_width = 540;
401 ctx->dsc.slice_count = 1080 / ctx->dsc.slice_width;
402 ctx->dsc.bits_per_component = 10;
403 ctx->dsc.bits_per_pixel = 8 << 4;
404 ctx->dsc.block_pred_enable = true;
405
406 ret = devm_mipi_dsi_attach(dev, dsi);
407 if (ret < 0) {
408 drm_panel_remove(&ctx->panel);
409 return dev_err_probe(dev, ret, "Failed to attach to DSI host\n");
410 }
411
412 return 0;
413 }
414
visionox_rm692e5_remove(struct mipi_dsi_device * dsi)415 static void visionox_rm692e5_remove(struct mipi_dsi_device *dsi)
416 {
417 struct visionox_rm692e5 *ctx = mipi_dsi_get_drvdata(dsi);
418
419 drm_panel_remove(&ctx->panel);
420 }
421
422 static const struct of_device_id visionox_rm692e5_of_match[] = {
423 { .compatible = "visionox,rm692e5" },
424 { /* sentinel */ }
425 };
426 MODULE_DEVICE_TABLE(of, visionox_rm692e5_of_match);
427
428 static struct mipi_dsi_driver visionox_rm692e5_driver = {
429 .probe = visionox_rm692e5_probe,
430 .remove = visionox_rm692e5_remove,
431 .driver = {
432 .name = "panel-visionox-rm692e5",
433 .of_match_table = visionox_rm692e5_of_match,
434 },
435 };
436 module_mipi_dsi_driver(visionox_rm692e5_driver);
437
438 MODULE_AUTHOR("Eugene Lepshy <fekz115@gmail.com>");
439 MODULE_AUTHOR("Danila Tikhonov <danila@jiaxyga.com>");
440 MODULE_DESCRIPTION("DRM driver for Visionox RM692E5 cmd mode dsi panel");
441 MODULE_LICENSE("GPL");
442