xref: /linux/drivers/gpu/nova-core/fb/hal/tu102.rs (revision 220994d61cebfc04f071d69049127657c7e8191b)
1 // SPDX-License-Identifier: GPL-2.0
2 
3 use crate::driver::Bar0;
4 use crate::fb::hal::FbHal;
5 use crate::regs;
6 use kernel::prelude::*;
7 
8 /// Shift applied to the sysmem address before it is written into `NV_PFB_NISO_FLUSH_SYSMEM_ADDR`,
9 /// to be used by HALs.
10 pub(super) const FLUSH_SYSMEM_ADDR_SHIFT: u32 = 8;
11 
read_sysmem_flush_page_gm107(bar: &Bar0) -> u6412 pub(super) fn read_sysmem_flush_page_gm107(bar: &Bar0) -> u64 {
13     u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT
14 }
15 
write_sysmem_flush_page_gm107(bar: &Bar0, addr: u64) -> Result16 pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, addr: u64) -> Result {
17     // Check that the address doesn't overflow the receiving 32-bit register.
18     if addr >> (u32::BITS + FLUSH_SYSMEM_ADDR_SHIFT) == 0 {
19         regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::default()
20             .set_adr_39_08((addr >> FLUSH_SYSMEM_ADDR_SHIFT) as u32)
21             .write(bar);
22 
23         Ok(())
24     } else {
25         Err(EINVAL)
26     }
27 }
28 
display_enabled_gm107(bar: &Bar0) -> bool29 pub(super) fn display_enabled_gm107(bar: &Bar0) -> bool {
30     !regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disabled()
31 }
32 
vidmem_size_gp102(bar: &Bar0) -> u6433 pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 {
34     regs::NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE::read(bar).usable_fb_size()
35 }
36 
37 struct Tu102;
38 
39 impl FbHal for Tu102 {
read_sysmem_flush_page(&self, bar: &Bar0) -> u6440     fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 {
41         read_sysmem_flush_page_gm107(bar)
42     }
43 
write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result44     fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result {
45         write_sysmem_flush_page_gm107(bar, addr)
46     }
47 
supports_display(&self, bar: &Bar0) -> bool48     fn supports_display(&self, bar: &Bar0) -> bool {
49         display_enabled_gm107(bar)
50     }
51 
vidmem_size(&self, bar: &Bar0) -> u6452     fn vidmem_size(&self, bar: &Bar0) -> u64 {
53         vidmem_size_gp102(bar)
54     }
55 }
56 
57 const TU102: Tu102 = Tu102;
58 pub(super) const TU102_HAL: &dyn FbHal = &TU102;
59