xref: /linux/drivers/video/fbdev/via/hw.h (revision 58e16d792a6a8c6b750f637a4649967fcac853dc)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 
6  */
7 
8 #ifndef __HW_H__
9 #define __HW_H__
10 
11 #include <linux/seq_file.h>
12 
13 #include "viamode.h"
14 #include "global.h"
15 #include "via_modesetting.h"
16 
17 #define viafb_read_reg(p, i)			via_read_reg(p, i)
18 #define viafb_write_reg(i, p, d)		via_write_reg(p, i, d)
19 #define viafb_write_reg_mask(i, p, d, m)	via_write_reg_mask(p, i, d, m)
20 
21 /* VIA output devices */
22 #define VIA_LDVP0	0x00000001
23 #define VIA_LDVP1	0x00000002
24 #define VIA_DVP0	0x00000004
25 #define VIA_CRT		0x00000010
26 #define VIA_DVP1	0x00000020
27 #define VIA_LVDS1	0x00000040
28 #define VIA_LVDS2	0x00000080
29 
30 /* VIA output device power states */
31 #define VIA_STATE_ON		0
32 #define VIA_STATE_STANDBY	1
33 #define VIA_STATE_SUSPEND	2
34 #define VIA_STATE_OFF		3
35 
36 /* VIA output device sync polarity */
37 #define VIA_HSYNC_NEGATIVE	0x01
38 #define VIA_VSYNC_NEGATIVE	0x02
39 
40 /**********************************************************/
41 /* Definition IGA2 Design Method of CRTC Shadow Registers */
42 /**********************************************************/
43 #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x)           ((x/8)-5)
44 #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y)     (((x+y)/8)-1)
45 #define IGA2_VER_TOTAL_SHADOW_FORMULA(x)           ((x)-2)
46 #define IGA2_VER_ADDR_SHADOW_FORMULA(x)            ((x)-1)
47 #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x)     ((x)-1)
48 #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y)     ((x+y)-1)
49 #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x)      (x)
50 #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y)      (x+y)
51 
52 /* Define Register Number for IGA2 Shadow CRTC Timing */
53 
54 /* location: {CR6D,0,7},{CR71,3,3} */
55 #define IGA2_SHADOW_HOR_TOTAL_REG_NUM       2
56 /* location: {CR6E,0,7} */
57 #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM   1
58 /* location: {CR6F,0,7},{CR71,0,2} */
59 #define IGA2_SHADOW_VER_TOTAL_REG_NUM       2
60 /* location: {CR70,0,7},{CR71,4,6} */
61 #define IGA2_SHADOW_VER_ADDR_REG_NUM        2
62 /* location: {CR72,0,7},{CR74,4,6} */
63 #define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2
64 /* location: {CR73,0,7},{CR74,0,2} */
65 #define IGA2_SHADOW_VER_BLANK_END_REG_NUM   2
66 /* location: {CR75,0,7},{CR76,4,6} */
67 #define IGA2_SHADOW_VER_SYNC_START_REG_NUM  2
68 /* location: {CR76,0,3} */
69 #define IGA2_SHADOW_VER_SYNC_END_REG_NUM    1
70 
71 /* Define Fetch Count Register*/
72 
73 /* location: {SR1C,0,7},{SR1D,0,1} */
74 #define IGA1_FETCH_COUNT_REG_NUM        2
75 /* 16 bytes alignment. */
76 #define IGA1_FETCH_COUNT_ALIGN_BYTE     16
77 /* x: H resolution, y: color depth */
78 #define IGA1_FETCH_COUNT_PATCH_VALUE    4
79 #define IGA1_FETCH_COUNT_FORMULA(x, y)   \
80 	(((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE)
81 
82 /* location: {CR65,0,7},{CR67,2,3} */
83 #define IGA2_FETCH_COUNT_REG_NUM        2
84 #define IGA2_FETCH_COUNT_ALIGN_BYTE     16
85 #define IGA2_FETCH_COUNT_PATCH_VALUE    0
86 #define IGA2_FETCH_COUNT_FORMULA(x, y)   \
87 	(((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE)
88 
89 /* Staring Address*/
90 
91 /* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */
92 #define IGA1_STARTING_ADDR_REG_NUM      4
93 /* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */
94 #define IGA2_STARTING_ADDR_REG_NUM      3
95 
96 /* Define Display OFFSET*/
97 /* These value are by HW suggested value*/
98 /* location: {SR17,0,7} */
99 #define K800_IGA1_FIFO_MAX_DEPTH                384
100 /* location: {SR16,0,5},{SR16,7,7} */
101 #define K800_IGA1_FIFO_THRESHOLD                328
102 /* location: {SR18,0,5},{SR18,7,7} */
103 #define K800_IGA1_FIFO_HIGH_THRESHOLD           296
104 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
105 				/* because HW only 5 bits */
106 #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0
107 
108 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
109 #define K800_IGA2_FIFO_MAX_DEPTH                384
110 /* location: {CR68,0,3},{CR95,4,6} */
111 #define K800_IGA2_FIFO_THRESHOLD                328
112 /* location: {CR92,0,3},{CR95,0,2} */
113 #define K800_IGA2_FIFO_HIGH_THRESHOLD           296
114 /* location: {CR94,0,6} */
115 #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128
116 
117 /* location: {SR17,0,7} */
118 #define P880_IGA1_FIFO_MAX_DEPTH                192
119 /* location: {SR16,0,5},{SR16,7,7} */
120 #define P880_IGA1_FIFO_THRESHOLD                128
121 /* location: {SR18,0,5},{SR18,7,7} */
122 #define P880_IGA1_FIFO_HIGH_THRESHOLD           64
123 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
124 				/* because HW only 5 bits */
125 #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0
126 
127 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
128 #define P880_IGA2_FIFO_MAX_DEPTH                96
129 /* location: {CR68,0,3},{CR95,4,6} */
130 #define P880_IGA2_FIFO_THRESHOLD                64
131 /* location: {CR92,0,3},{CR95,0,2} */
132 #define P880_IGA2_FIFO_HIGH_THRESHOLD           32
133 /* location: {CR94,0,6} */
134 #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128
135 
136 /* VT3314 chipset*/
137 
138 /* location: {SR17,0,7} */
139 #define CN700_IGA1_FIFO_MAX_DEPTH               96
140 /* location: {SR16,0,5},{SR16,7,7} */
141 #define CN700_IGA1_FIFO_THRESHOLD               80
142 /* location: {SR18,0,5},{SR18,7,7} */
143 #define CN700_IGA1_FIFO_HIGH_THRESHOLD          64
144 /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero,
145 				because HW only 5 bits */
146 #define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     0
147 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
148 #define CN700_IGA2_FIFO_MAX_DEPTH               96
149 /* location: {CR68,0,3},{CR95,4,6} */
150 #define CN700_IGA2_FIFO_THRESHOLD               80
151 /* location: {CR92,0,3},{CR95,0,2} */
152 #define CN700_IGA2_FIFO_HIGH_THRESHOLD          32
153 /* location: {CR94,0,6} */
154 #define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
155 
156 /* For VT3324, these values are suggested by HW */
157 /* location: {SR17,0,7} */
158 #define CX700_IGA1_FIFO_MAX_DEPTH               192
159 /* location: {SR16,0,5},{SR16,7,7} */
160 #define CX700_IGA1_FIFO_THRESHOLD               128
161 /* location: {SR18,0,5},{SR18,7,7} */
162 #define CX700_IGA1_FIFO_HIGH_THRESHOLD          128
163 /* location: {SR22,0,4} */
164 #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124
165 
166 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
167 #define CX700_IGA2_FIFO_MAX_DEPTH               96
168 /* location: {CR68,0,3},{CR95,4,6} */
169 #define CX700_IGA2_FIFO_THRESHOLD               64
170 /* location: {CR92,0,3},{CR95,0,2} */
171 #define CX700_IGA2_FIFO_HIGH_THRESHOLD          32
172 /* location: {CR94,0,6} */
173 #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
174 
175 /* VT3336 chipset*/
176 /* location: {SR17,0,7} */
177 #define K8M890_IGA1_FIFO_MAX_DEPTH               360
178 /* location: {SR16,0,5},{SR16,7,7} */
179 #define K8M890_IGA1_FIFO_THRESHOLD               328
180 /* location: {SR18,0,5},{SR18,7,7} */
181 #define K8M890_IGA1_FIFO_HIGH_THRESHOLD          296
182 /* location: {SR22,0,4}. */
183 #define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124
184 
185 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
186 #define K8M890_IGA2_FIFO_MAX_DEPTH               360
187 /* location: {CR68,0,3},{CR95,4,6} */
188 #define K8M890_IGA2_FIFO_THRESHOLD               328
189 /* location: {CR92,0,3},{CR95,0,2} */
190 #define K8M890_IGA2_FIFO_HIGH_THRESHOLD          296
191 /* location: {CR94,0,6} */
192 #define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     124
193 
194 /* VT3327 chipset*/
195 /* location: {SR17,0,7} */
196 #define P4M890_IGA1_FIFO_MAX_DEPTH               96
197 /* location: {SR16,0,5},{SR16,7,7} */
198 #define P4M890_IGA1_FIFO_THRESHOLD               76
199 /* location: {SR18,0,5},{SR18,7,7} */
200 #define P4M890_IGA1_FIFO_HIGH_THRESHOLD          64
201 /* location: {SR22,0,4}. (32/4) =8 */
202 #define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     32
203 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
204 #define P4M890_IGA2_FIFO_MAX_DEPTH               96
205 /* location: {CR68,0,3},{CR95,4,6} */
206 #define P4M890_IGA2_FIFO_THRESHOLD               76
207 /* location: {CR92,0,3},{CR95,0,2} */
208 #define P4M890_IGA2_FIFO_HIGH_THRESHOLD          64
209 /* location: {CR94,0,6} */
210 #define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     32
211 
212 /* VT3364 chipset*/
213 /* location: {SR17,0,7} */
214 #define P4M900_IGA1_FIFO_MAX_DEPTH               96
215 /* location: {SR16,0,5},{SR16,7,7} */
216 #define P4M900_IGA1_FIFO_THRESHOLD               76
217 /* location: {SR18,0,5},{SR18,7,7} */
218 #define P4M900_IGA1_FIFO_HIGH_THRESHOLD          76
219 /* location: {SR22,0,4}. */
220 #define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     32
221 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
222 #define P4M900_IGA2_FIFO_MAX_DEPTH               96
223 /* location: {CR68,0,3},{CR95,4,6} */
224 #define P4M900_IGA2_FIFO_THRESHOLD               76
225 /* location: {CR92,0,3},{CR95,0,2} */
226 #define P4M900_IGA2_FIFO_HIGH_THRESHOLD          76
227 /* location: {CR94,0,6} */
228 #define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     32
229 
230 /* For VT3353, these values are suggested by HW */
231 /* location: {SR17,0,7} */
232 #define VX800_IGA1_FIFO_MAX_DEPTH               192
233 /* location: {SR16,0,5},{SR16,7,7} */
234 #define VX800_IGA1_FIFO_THRESHOLD               152
235 /* location: {SR18,0,5},{SR18,7,7} */
236 #define VX800_IGA1_FIFO_HIGH_THRESHOLD          152
237 /* location: {SR22,0,4} */
238 #define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      64
239 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
240 #define VX800_IGA2_FIFO_MAX_DEPTH               96
241 /* location: {CR68,0,3},{CR95,4,6} */
242 #define VX800_IGA2_FIFO_THRESHOLD               64
243 /* location: {CR92,0,3},{CR95,0,2} */
244 #define VX800_IGA2_FIFO_HIGH_THRESHOLD          32
245 /* location: {CR94,0,6} */
246 #define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
247 
248 /* For VT3409 */
249 #define VX855_IGA1_FIFO_MAX_DEPTH               400
250 #define VX855_IGA1_FIFO_THRESHOLD               320
251 #define VX855_IGA1_FIFO_HIGH_THRESHOLD          320
252 #define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     160
253 
254 #define VX855_IGA2_FIFO_MAX_DEPTH               200
255 #define VX855_IGA2_FIFO_THRESHOLD               160
256 #define VX855_IGA2_FIFO_HIGH_THRESHOLD          160
257 #define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     320
258 
259 /* For VT3410 */
260 #define VX900_IGA1_FIFO_MAX_DEPTH               400
261 #define VX900_IGA1_FIFO_THRESHOLD               320
262 #define VX900_IGA1_FIFO_HIGH_THRESHOLD          320
263 #define VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     160
264 
265 #define VX900_IGA2_FIFO_MAX_DEPTH               192
266 #define VX900_IGA2_FIFO_THRESHOLD               160
267 #define VX900_IGA2_FIFO_HIGH_THRESHOLD          160
268 #define VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     320
269 
270 #define IGA1_FIFO_DEPTH_SELECT_REG_NUM          1
271 #define IGA1_FIFO_THRESHOLD_REG_NUM             2
272 #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM        2
273 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
274 
275 #define IGA2_FIFO_DEPTH_SELECT_REG_NUM          3
276 #define IGA2_FIFO_THRESHOLD_REG_NUM             2
277 #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM        2
278 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
279 
280 #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x)                   ((x/2)-1)
281 #define IGA1_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
282 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
283 #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
284 #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x)                   (((x/2)/4)-1)
285 #define IGA2_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
286 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
287 #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
288 
289 /************************************************************************/
290 /*  LCD Timing                                                          */
291 /************************************************************************/
292 
293 /* 500 ms = 500000 us */
294 #define LCD_POWER_SEQ_TD0               500000
295 /* 50 ms = 50000 us */
296 #define LCD_POWER_SEQ_TD1               50000
297 /* 0 us */
298 #define LCD_POWER_SEQ_TD2               0
299 /* 210 ms = 210000 us */
300 #define LCD_POWER_SEQ_TD3               210000
301 /* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */
302 #define CLE266_POWER_SEQ_UNIT           71
303 /* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */
304 #define K800_POWER_SEQ_UNIT             142
305 /* 2^13 * (1/14.31818M) = 572.1 us */
306 #define P880_POWER_SEQ_UNIT             572
307 
308 #define CLE266_POWER_SEQ_FORMULA(x)     ((x)/CLE266_POWER_SEQ_UNIT)
309 #define K800_POWER_SEQ_FORMULA(x)       ((x)/K800_POWER_SEQ_UNIT)
310 #define P880_POWER_SEQ_FORMULA(x)       ((x)/P880_POWER_SEQ_UNIT)
311 
312 /* location: {CR8B,0,7},{CR8F,0,3} */
313 #define LCD_POWER_SEQ_TD0_REG_NUM       2
314 /* location: {CR8C,0,7},{CR8F,4,7} */
315 #define LCD_POWER_SEQ_TD1_REG_NUM       2
316 /* location: {CR8D,0,7},{CR90,0,3} */
317 #define LCD_POWER_SEQ_TD2_REG_NUM       2
318 /* location: {CR8E,0,7},{CR90,4,7} */
319 #define LCD_POWER_SEQ_TD3_REG_NUM       2
320 
321 /* LCD Scaling factor*/
322 /* x: indicate setting horizontal size*/
323 /* y: indicate panel horizontal size*/
324 
325 /* Horizontal scaling factor 10 bits (2^10) */
326 #define CLE266_LCD_HOR_SCF_FORMULA(x, y)   (((x-1)*1024)/(y-1))
327 /* Vertical scaling factor 10 bits (2^10) */
328 #define CLE266_LCD_VER_SCF_FORMULA(x, y)   (((x-1)*1024)/(y-1))
329 /* Horizontal scaling factor 10 bits (2^12) */
330 #define K800_LCD_HOR_SCF_FORMULA(x, y)     (((x-1)*4096)/(y-1))
331 /* Vertical scaling factor 10 bits (2^11) */
332 #define K800_LCD_VER_SCF_FORMULA(x, y)     (((x-1)*2048)/(y-1))
333 
334 /* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */
335 #define LCD_HOR_SCALING_FACTOR_REG_NUM  3
336 /* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */
337 #define LCD_VER_SCALING_FACTOR_REG_NUM  3
338 /* location: {CR77,0,7},{CR79,4,5} */
339 #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE  2
340 /* location: {CR78,0,7},{CR79,6,7} */
341 #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE  2
342 
343 struct io_register {
344 	u8 io_addr;
345 	u8 start_bit;
346 	u8 end_bit;
347 };
348 
349 /*****************************************************
350 **      Define IGA2 Shadow Display Timing         ****
351 *****************************************************/
352 
353 /* IGA2 Shadow Horizontal Total */
354 struct iga2_shadow_hor_total {
355 	int reg_num;
356 	struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM];
357 };
358 
359 /* IGA2 Shadow Horizontal Blank End */
360 struct iga2_shadow_hor_blank_end {
361 	int reg_num;
362 	struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];
363 };
364 
365 /* IGA2 Shadow Vertical Total */
366 struct iga2_shadow_ver_total {
367 	int reg_num;
368 	struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];
369 };
370 
371 /* IGA2 Shadow Vertical Addressable Video */
372 struct iga2_shadow_ver_addr {
373 	int reg_num;
374 	struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];
375 };
376 
377 /* IGA2 Shadow Vertical Blank Start */
378 struct iga2_shadow_ver_blank_start {
379 	int reg_num;
380 	struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];
381 };
382 
383 /* IGA2 Shadow Vertical Blank End */
384 struct iga2_shadow_ver_blank_end {
385 	int reg_num;
386 	struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];
387 };
388 
389 /* IGA2 Shadow Vertical Sync Start */
390 struct iga2_shadow_ver_sync_start {
391 	int reg_num;
392 	struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];
393 };
394 
395 /* IGA2 Shadow Vertical Sync End */
396 struct iga2_shadow_ver_sync_end {
397 	int reg_num;
398 	struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
399 };
400 
401 /* IGA1 Fetch Count Register */
402 struct iga1_fetch_count {
403 	int reg_num;
404 	struct io_register reg[IGA1_FETCH_COUNT_REG_NUM];
405 };
406 
407 /* IGA2 Fetch Count Register */
408 struct iga2_fetch_count {
409 	int reg_num;
410 	struct io_register reg[IGA2_FETCH_COUNT_REG_NUM];
411 };
412 
413 struct fetch_count {
414 	struct iga1_fetch_count iga1_fetch_count_reg;
415 	struct iga2_fetch_count iga2_fetch_count_reg;
416 };
417 
418 /* Starting Address Register */
419 struct iga1_starting_addr {
420 	int reg_num;
421 	struct io_register reg[IGA1_STARTING_ADDR_REG_NUM];
422 };
423 
424 struct iga2_starting_addr {
425 	int reg_num;
426 	struct io_register reg[IGA2_STARTING_ADDR_REG_NUM];
427 };
428 
429 struct starting_addr {
430 	struct iga1_starting_addr iga1_starting_addr_reg;
431 	struct iga2_starting_addr iga2_starting_addr_reg;
432 };
433 
434 /* LCD Power Sequence Timer */
435 struct lcd_pwd_seq_td0 {
436 	int reg_num;
437 	struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
438 };
439 
440 struct lcd_pwd_seq_td1 {
441 	int reg_num;
442 	struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
443 };
444 
445 struct lcd_pwd_seq_td2 {
446 	int reg_num;
447 	struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
448 };
449 
450 struct lcd_pwd_seq_td3 {
451 	int reg_num;
452 	struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
453 };
454 
455 struct _lcd_pwd_seq_timer {
456 	struct lcd_pwd_seq_td0 td0;
457 	struct lcd_pwd_seq_td1 td1;
458 	struct lcd_pwd_seq_td2 td2;
459 	struct lcd_pwd_seq_td3 td3;
460 };
461 
462 /* LCD Scaling Factor */
463 struct _lcd_hor_scaling_factor {
464 	int reg_num;
465 	struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
466 };
467 
468 struct _lcd_ver_scaling_factor {
469 	int reg_num;
470 	struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
471 };
472 
473 struct _lcd_scaling_factor {
474 	struct _lcd_hor_scaling_factor lcd_hor_scaling_factor;
475 	struct _lcd_ver_scaling_factor lcd_ver_scaling_factor;
476 };
477 
478 struct pll_limit {
479 	u16 multiplier_min;
480 	u16 multiplier_max;
481 	u8 divisor;
482 	u8 rshift;
483 };
484 
485 struct rgbLUT {
486 	u8 red;
487 	u8 green;
488 	u8 blue;
489 };
490 
491 struct lcd_pwd_seq_timer {
492 	u16 td0;
493 	u16 td1;
494 	u16 td2;
495 	u16 td3;
496 };
497 
498 /* Display FIFO Relation Registers*/
499 struct iga1_fifo_depth_select {
500 	int reg_num;
501 	struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
502 };
503 
504 struct iga1_fifo_threshold_select {
505 	int reg_num;
506 	struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];
507 };
508 
509 struct iga1_fifo_high_threshold_select {
510 	int reg_num;
511 	struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];
512 };
513 
514 struct iga1_display_queue_expire_num {
515 	int reg_num;
516 	struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
517 };
518 
519 struct iga2_fifo_depth_select {
520 	int reg_num;
521 	struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
522 };
523 
524 struct iga2_fifo_threshold_select {
525 	int reg_num;
526 	struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
527 };
528 
529 struct iga2_fifo_high_threshold_select {
530 	int reg_num;
531 	struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];
532 };
533 
534 struct iga2_display_queue_expire_num {
535 	int reg_num;
536 	struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
537 };
538 
539 struct fifo_depth_select {
540 	struct iga1_fifo_depth_select iga1_fifo_depth_select_reg;
541 	struct iga2_fifo_depth_select iga2_fifo_depth_select_reg;
542 };
543 
544 struct fifo_threshold_select {
545 	struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg;
546 	struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg;
547 };
548 
549 struct fifo_high_threshold_select {
550 	struct iga1_fifo_high_threshold_select
551 	 iga1_fifo_high_threshold_select_reg;
552 	struct iga2_fifo_high_threshold_select
553 	 iga2_fifo_high_threshold_select_reg;
554 };
555 
556 struct display_queue_expire_num {
557 	struct iga1_display_queue_expire_num
558 	 iga1_display_queue_expire_num_reg;
559 	struct iga2_display_queue_expire_num
560 	 iga2_display_queue_expire_num_reg;
561 };
562 
563 struct iga2_shadow_crtc_timing {
564 	struct iga2_shadow_hor_total hor_total_shadow;
565 	struct iga2_shadow_hor_blank_end hor_blank_end_shadow;
566 	struct iga2_shadow_ver_total ver_total_shadow;
567 	struct iga2_shadow_ver_addr ver_addr_shadow;
568 	struct iga2_shadow_ver_blank_start ver_blank_start_shadow;
569 	struct iga2_shadow_ver_blank_end ver_blank_end_shadow;
570 	struct iga2_shadow_ver_sync_start ver_sync_start_shadow;
571 	struct iga2_shadow_ver_sync_end ver_sync_end_shadow;
572 };
573 
574 /* device ID */
575 #define CLE266_FUNCTION3    0x3123
576 #define KM400_FUNCTION3     0x3205
577 #define CN400_FUNCTION2     0x2259
578 #define CN400_FUNCTION3     0x3259
579 /* support VT3314 chipset */
580 #define CN700_FUNCTION2     0x2314
581 #define CN700_FUNCTION3     0x3208
582 /* VT3324 chipset */
583 #define CX700_FUNCTION2     0x2324
584 #define CX700_FUNCTION3     0x3324
585 /* VT3204 chipset*/
586 #define KM800_FUNCTION3      0x3204
587 /* VT3336 chipset*/
588 #define KM890_FUNCTION3      0x3336
589 /* VT3327 chipset*/
590 #define P4M890_FUNCTION3     0x3327
591 /* VT3293 chipset*/
592 #define CN750_FUNCTION3     0x3208
593 /* VT3364 chipset*/
594 #define P4M900_FUNCTION3    0x3364
595 /* VT3353 chipset*/
596 #define VX800_FUNCTION3     0x3353
597 /* VT3409 chipset*/
598 #define VX855_FUNCTION3     0x3409
599 /* VT3410 chipset*/
600 #define VX900_FUNCTION3     0x3410
601 
602 struct IODATA {
603 	u8 Index;
604 	u8 Mask;
605 	u8 Data;
606 };
607 
608 struct pci_device_id_info {
609 	u32 vendor;
610 	u32 device;
611 	u32 chip_index;
612 };
613 
614 struct via_device_mapping {
615 	u32 device;
616 	const char *name;
617 };
618 
619 extern int viafb_SAMM_ON;
620 extern int viafb_dual_fb;
621 extern int viafb_LCD2_ON;
622 extern int viafb_LCD_ON;
623 extern int viafb_DVI_ON;
624 extern int viafb_hotplug;
625 
626 struct via_display_timing var_to_timing(const struct fb_var_screeninfo *var,
627 	u16 cxres, u16 cyres);
628 void viafb_fill_crtc_timing(const struct fb_var_screeninfo *var,
629 	u16 cxres, u16 cyres, int iga);
630 void viafb_set_vclock(u32 CLK, int set_iga);
631 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
632 	struct io_register *reg,
633 	      int io_type);
634 void via_set_source(u32 devices, u8 iga);
635 void via_set_state(u32 devices, u8 state);
636 void via_set_sync_polarity(u32 devices, u8 polarity);
637 u32 via_parse_odev(char *input, char **end);
638 void via_odev_to_seq(struct seq_file *m, u32 odev);
639 void init_ad9389(void);
640 /* Access I/O Function */
641 void viafb_lock_crt(void);
642 void viafb_unlock_crt(void);
643 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga);
644 void viafb_write_regx(struct io_reg RegTable[], int ItemNum);
645 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active);
646 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
647 					*p_gfx_dpa_setting);
648 
649 int viafb_setmode(void);
650 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var,
651 	const struct fb_videomode *mode);
652 void viafb_init_chip_info(int chip_type);
653 void viafb_init_dac(int set_iga);
654 int viafb_get_refresh(int hres, int vres, u32 float_refresh);
655 void viafb_update_device_setting(int hres, int vres, int bpp, int flag);
656 
657 void viafb_set_iga_path(void);
658 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue);
659 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue);
660 void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len);
661 
662 #endif /* __HW_H__ */
663