1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * pata_via.c - VIA PATA for new ATA layer
4 * (C) 2005-2006 Red Hat Inc
5 *
6 * Documentation
7 * Most chipset documentation available under NDA only
8 *
9 * VIA version guide
10 * VIA VT82C561 - early design, uses ata_generic currently
11 * VIA VT82C576 - MWDMA, 33Mhz
12 * VIA VT82C586 - MWDMA, 33Mhz
13 * VIA VT82C586a - Added UDMA to 33Mhz
14 * VIA VT82C586b - UDMA33
15 * VIA VT82C596a - Nonfunctional UDMA66
16 * VIA VT82C596b - Working UDMA66
17 * VIA VT82C686 - Nonfunctional UDMA66
18 * VIA VT82C686a - Working UDMA66
19 * VIA VT82C686b - Updated to UDMA100
20 * VIA VT8231 - UDMA100
21 * VIA VT8233 - UDMA100
22 * VIA VT8233a - UDMA133
23 * VIA VT8233c - UDMA100
24 * VIA VT8235 - UDMA133
25 * VIA VT8237 - UDMA133
26 * VIA VT8237A - UDMA133
27 * VIA VT8237S - UDMA133
28 * VIA VT8251 - UDMA133
29 *
30 * Most registers remain compatible across chips. Others start reserved
31 * and acquire sensible semantics if set to 1 (eg cable detect). A few
32 * exceptions exist, notably around the FIFO settings.
33 *
34 * One additional quirk of the VIA design is that like ALi they use few
35 * PCI IDs for a lot of chips.
36 *
37 * Based heavily on:
38 *
39 * Version 3.38
40 *
41 * VIA IDE driver for Linux. Supported southbridges:
42 *
43 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
44 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
45 * vt8235, vt8237
46 *
47 * Copyright (c) 2000-2002 Vojtech Pavlik
48 *
49 * Based on the work of:
50 * Michel Aubry
51 * Jeff Garzik
52 * Andre Hedrick
53
54 */
55
56 #include <linux/kernel.h>
57 #include <linux/module.h>
58 #include <linux/pci.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <linux/gfp.h>
62 #include <scsi/scsi_host.h>
63 #include <linux/libata.h>
64 #include <linux/dmi.h>
65
66 #define DRV_NAME "pata_via"
67 #define DRV_VERSION "0.3.4"
68
69 enum {
70 VIA_BAD_PREQ = 0x01, /* Crashes if PREQ# till DDACK# set */
71 VIA_BAD_CLK66 = 0x02, /* 66 MHz clock doesn't work correctly */
72 VIA_SET_FIFO = 0x04, /* Needs to have FIFO split set */
73 VIA_NO_UNMASK = 0x08, /* Doesn't work with IRQ unmasking on */
74 VIA_BAD_ID = 0x10, /* Has wrong vendor ID (0x1107) */
75 VIA_BAD_AST = 0x20, /* Don't touch Address Setup Timing */
76 VIA_NO_ENABLES = 0x40, /* Has no enablebits */
77 VIA_SATA_PATA = 0x80, /* SATA/PATA combined configuration */
78 };
79
80 enum {
81 VIA_IDFLAG_SINGLE = (1 << 0), /* single channel controller) */
82 };
83
84 /*
85 * VIA SouthBridge chips.
86 */
87
88 static const struct via_isa_bridge {
89 const char *name;
90 u16 id;
91 u8 rev_min;
92 u8 rev_max;
93 u8 udma_mask;
94 u8 flags;
95 } via_isa_bridges[] = {
96 { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
97 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
98 { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
99 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
100 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
101 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
102 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES },
103 { "vt6415", PCI_DEVICE_ID_VIA_6415, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES },
104 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
105 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
106 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
107 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
108 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
109 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
110 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
111 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
112 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
113 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
114 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
115 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
116 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
117 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
118 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
119 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
120 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
121 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
122 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
123 { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
124 { NULL }
125 };
126
127 static const struct dmi_system_id no_atapi_dma_dmi_table[] = {
128 {
129 .ident = "AVERATEC 3200",
130 .matches = {
131 DMI_MATCH(DMI_BOARD_VENDOR, "AVERATEC"),
132 DMI_MATCH(DMI_BOARD_NAME, "3200"),
133 },
134 },
135 { }
136 };
137
138 struct via_port {
139 u8 cached_device;
140 };
141
142 /*
143 * Cable special cases
144 */
145
146 static const struct dmi_system_id cable_dmi_table[] = {
147 {
148 .ident = "Acer Ferrari 3400",
149 .matches = {
150 DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
151 DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
152 },
153 },
154 { }
155 };
156
via_cable_override(struct pci_dev * pdev)157 static int via_cable_override(struct pci_dev *pdev)
158 {
159 /* Systems by DMI */
160 if (dmi_check_system(cable_dmi_table))
161 return 1;
162 /* Arima W730-K8/Targa Visionary 811/... */
163 if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032)
164 return 1;
165 return 0;
166 }
167
168
169 /**
170 * via_cable_detect - cable detection
171 * @ap: ATA port
172 *
173 * Perform cable detection. Actually for the VIA case the BIOS
174 * already did this for us. We read the values provided by the
175 * BIOS. If you are using an 8235 in a non-PC configuration you
176 * may need to update this code.
177 *
178 * Hotplug also impacts on this.
179 */
180
via_cable_detect(struct ata_port * ap)181 static int via_cable_detect(struct ata_port *ap) {
182 const struct via_isa_bridge *config = ap->host->private_data;
183 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
184 u32 ata66;
185
186 if (via_cable_override(pdev))
187 return ATA_CBL_PATA40_SHORT;
188
189 if ((config->flags & VIA_SATA_PATA) && ap->port_no == 0)
190 return ATA_CBL_SATA;
191
192 /* Early chips are 40 wire */
193 if (config->udma_mask < ATA_UDMA4)
194 return ATA_CBL_PATA40;
195 /* UDMA 66 chips have only drive side logic */
196 else if (config->udma_mask < ATA_UDMA5)
197 return ATA_CBL_PATA_UNK;
198 /* UDMA 100 or later */
199 pci_read_config_dword(pdev, 0x50, &ata66);
200 /* Check both the drive cable reporting bits, we might not have
201 two drives */
202 if (ata66 & (0x10100000 >> (16 * ap->port_no)))
203 return ATA_CBL_PATA80;
204
205 /* Check with ACPI so we can spot BIOS reported SATA bridges */
206 return ata_acpi_cbl_pata_type(ap);
207 }
208
via_pre_reset(struct ata_link * link,unsigned long deadline)209 static int via_pre_reset(struct ata_link *link, unsigned long deadline)
210 {
211 struct ata_port *ap = link->ap;
212 const struct via_isa_bridge *config = ap->host->private_data;
213
214 if (!(config->flags & VIA_NO_ENABLES)) {
215 static const struct pci_bits via_enable_bits[] = {
216 { 0x40, 1, 0x02, 0x02 },
217 { 0x40, 1, 0x01, 0x01 }
218 };
219 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
220 if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
221 return -ENOENT;
222 }
223
224 return ata_sff_prereset(link, deadline);
225 }
226
227
228 /**
229 * via_do_set_mode - set transfer mode data
230 * @ap: ATA interface
231 * @adev: ATA device
232 * @mode: ATA mode being programmed
233 * @set_ast: Set to program address setup
234 * @udma_type: UDMA mode/format of registers
235 *
236 * Program the VIA registers for DMA and PIO modes. Uses the ata timing
237 * support in order to compute modes.
238 *
239 * FIXME: Hotplug will require we serialize multiple mode changes
240 * on the two channels.
241 */
242
via_do_set_mode(struct ata_port * ap,struct ata_device * adev,int mode,int set_ast,int udma_type)243 static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev,
244 int mode, int set_ast, int udma_type)
245 {
246 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
247 struct ata_device *peer = ata_dev_pair(adev);
248 struct ata_timing t, p;
249 const int via_clock = 33333; /* Bus clock in kHz */
250 const int T = 1000000000 / via_clock;
251 int UT = T;
252 int ut;
253 int offset = 3 - (2*ap->port_no) - adev->devno;
254
255 switch (udma_type) {
256 case ATA_UDMA4:
257 UT = T / 2; break;
258 case ATA_UDMA5:
259 UT = T / 3; break;
260 case ATA_UDMA6:
261 UT = T / 4; break;
262 }
263
264 /* Calculate the timing values we require */
265 ata_timing_compute(adev, mode, &t, T, UT);
266
267 /* We share 8bit timing so we must merge the constraints */
268 if (peer) {
269 if (peer->pio_mode) {
270 ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
271 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
272 }
273 }
274
275 /* Address setup is programmable but breaks on UDMA133 setups */
276 if (set_ast) {
277 u8 setup; /* 2 bits per drive */
278 int shift = 2 * offset;
279
280 pci_read_config_byte(pdev, 0x4C, &setup);
281 setup &= ~(3 << shift);
282 setup |= (clamp_val(t.setup, 1, 4) - 1) << shift;
283 pci_write_config_byte(pdev, 0x4C, setup);
284 }
285
286 /* Load the PIO mode bits */
287 pci_write_config_byte(pdev, 0x4F - ap->port_no,
288 ((clamp_val(t.act8b, 1, 16) - 1) << 4) | (clamp_val(t.rec8b, 1, 16) - 1));
289 pci_write_config_byte(pdev, 0x48 + offset,
290 ((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1));
291
292 /* Load the UDMA bits according to type */
293 switch (udma_type) {
294 case ATA_UDMA2:
295 default:
296 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03;
297 break;
298 case ATA_UDMA4:
299 ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f;
300 break;
301 case ATA_UDMA5:
302 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
303 break;
304 case ATA_UDMA6:
305 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
306 break;
307 }
308
309 /* Set UDMA unless device is not UDMA capable */
310 if (udma_type) {
311 u8 udma_etc;
312
313 pci_read_config_byte(pdev, 0x50 + offset, &udma_etc);
314
315 /* clear transfer mode bit */
316 udma_etc &= ~0x20;
317
318 if (t.udma) {
319 /* preserve 80-wire cable detection bit */
320 udma_etc &= 0x10;
321 udma_etc |= ut;
322 }
323
324 pci_write_config_byte(pdev, 0x50 + offset, udma_etc);
325 }
326 }
327
via_set_piomode(struct ata_port * ap,struct ata_device * adev)328 static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
329 {
330 const struct via_isa_bridge *config = ap->host->private_data;
331 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
332
333 via_do_set_mode(ap, adev, adev->pio_mode, set_ast, config->udma_mask);
334 }
335
via_set_dmamode(struct ata_port * ap,struct ata_device * adev)336 static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
337 {
338 const struct via_isa_bridge *config = ap->host->private_data;
339 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
340
341 via_do_set_mode(ap, adev, adev->dma_mode, set_ast, config->udma_mask);
342 }
343
344 /**
345 * via_mode_filter - filter buggy device/mode pairs
346 * @dev: ATA device
347 * @mask: Mode bitmask
348 *
349 * We need to apply some minimal filtering for old controllers and at least
350 * one breed of Transcend SSD. Return the updated mask.
351 */
352
via_mode_filter(struct ata_device * dev,unsigned int mask)353 static unsigned int via_mode_filter(struct ata_device *dev, unsigned int mask)
354 {
355 struct ata_host *host = dev->link->ap->host;
356 const struct via_isa_bridge *config = host->private_data;
357 unsigned char model_num[ATA_ID_PROD_LEN + 1];
358
359 if (config->id == PCI_DEVICE_ID_VIA_82C586_0) {
360 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
361 if (strcmp(model_num, "TS64GSSD25-M") == 0) {
362 ata_dev_warn(dev,
363 "disabling UDMA mode due to reported lockups with this device\n");
364 mask &= ~ ATA_MASK_UDMA;
365 }
366 }
367
368 if (dev->class == ATA_DEV_ATAPI &&
369 (dmi_check_system(no_atapi_dma_dmi_table) ||
370 config->id == PCI_DEVICE_ID_VIA_6415)) {
371 ata_dev_warn(dev, "controller locks up on ATAPI DMA, forcing PIO\n");
372 mask &= ATA_MASK_PIO;
373 }
374
375 return mask;
376 }
377
378 /**
379 * via_tf_load - send taskfile registers to host controller
380 * @ap: Port to which output is sent
381 * @tf: ATA taskfile register set
382 *
383 * Outputs ATA taskfile to standard ATA host controller.
384 *
385 * Note: This is to fix the internal bug of via chipsets, which
386 * will reset the device register after changing the IEN bit on
387 * ctl register
388 */
via_tf_load(struct ata_port * ap,const struct ata_taskfile * tf)389 static void via_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
390 {
391 struct ata_ioports *ioaddr = &ap->ioaddr;
392 struct via_port *vp = ap->private_data;
393 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
394 int newctl = 0;
395
396 if (tf->ctl != ap->last_ctl) {
397 iowrite8(tf->ctl, ioaddr->ctl_addr);
398 ap->last_ctl = tf->ctl;
399 ata_wait_idle(ap);
400 newctl = 1;
401 }
402
403 if (tf->flags & ATA_TFLAG_DEVICE) {
404 iowrite8(tf->device, ioaddr->device_addr);
405 vp->cached_device = tf->device;
406 } else if (newctl)
407 iowrite8(vp->cached_device, ioaddr->device_addr);
408
409 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
410 WARN_ON_ONCE(!ioaddr->ctl_addr);
411 iowrite8(tf->hob_feature, ioaddr->feature_addr);
412 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
413 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
414 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
415 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
416 }
417
418 if (is_addr) {
419 iowrite8(tf->feature, ioaddr->feature_addr);
420 iowrite8(tf->nsect, ioaddr->nsect_addr);
421 iowrite8(tf->lbal, ioaddr->lbal_addr);
422 iowrite8(tf->lbam, ioaddr->lbam_addr);
423 iowrite8(tf->lbah, ioaddr->lbah_addr);
424 }
425
426 ata_wait_idle(ap);
427 }
428
via_port_start(struct ata_port * ap)429 static int via_port_start(struct ata_port *ap)
430 {
431 struct via_port *vp;
432 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
433
434 int ret = ata_bmdma_port_start(ap);
435 if (ret < 0)
436 return ret;
437
438 vp = devm_kzalloc(&pdev->dev, sizeof(struct via_port), GFP_KERNEL);
439 if (vp == NULL)
440 return -ENOMEM;
441 ap->private_data = vp;
442 return 0;
443 }
444
445 static const struct scsi_host_template via_sht = {
446 ATA_BMDMA_SHT(DRV_NAME),
447 };
448
449 static struct ata_port_operations via_port_ops = {
450 .inherits = &ata_bmdma_port_ops,
451 .cable_detect = via_cable_detect,
452 .set_piomode = via_set_piomode,
453 .set_dmamode = via_set_dmamode,
454 .prereset = via_pre_reset,
455 .sff_tf_load = via_tf_load,
456 .port_start = via_port_start,
457 .mode_filter = via_mode_filter,
458 };
459
460 static struct ata_port_operations via_port_ops_noirq = {
461 .inherits = &via_port_ops,
462 .sff_data_xfer = ata_sff_data_xfer32,
463 };
464
465 /**
466 * via_config_fifo - set up the FIFO
467 * @pdev: PCI device
468 * @flags: configuration flags
469 *
470 * Set the FIFO properties for this device if necessary. Used both on
471 * set up and on and the resume path
472 */
473
via_config_fifo(struct pci_dev * pdev,unsigned int flags)474 static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
475 {
476 u8 enable;
477
478 /* 0x40 low bits indicate enabled channels */
479 pci_read_config_byte(pdev, 0x40 , &enable);
480 enable &= 3;
481
482 if (flags & VIA_SET_FIFO) {
483 static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
484 u8 fifo;
485
486 pci_read_config_byte(pdev, 0x43, &fifo);
487
488 /* Clear PREQ# until DDACK# for errata */
489 if (flags & VIA_BAD_PREQ)
490 fifo &= 0x7F;
491 else
492 fifo &= 0x9f;
493 /* Turn on FIFO for enabled channels */
494 fifo |= fifo_setting[enable];
495 pci_write_config_byte(pdev, 0x43, fifo);
496 }
497 }
498
via_fixup(struct pci_dev * pdev,const struct via_isa_bridge * config)499 static void via_fixup(struct pci_dev *pdev, const struct via_isa_bridge *config)
500 {
501 u32 timing;
502
503 /* Initialise the FIFO for the enabled channels. */
504 via_config_fifo(pdev, config->flags);
505
506 if (config->udma_mask == ATA_UDMA4) {
507 /* The 66 MHz devices require we enable the clock */
508 pci_read_config_dword(pdev, 0x50, &timing);
509 timing |= 0x80008;
510 pci_write_config_dword(pdev, 0x50, timing);
511 }
512 if (config->flags & VIA_BAD_CLK66) {
513 /* Disable the 66MHz clock on problem devices */
514 pci_read_config_dword(pdev, 0x50, &timing);
515 timing &= ~0x80008;
516 pci_write_config_dword(pdev, 0x50, timing);
517 }
518 }
519
520 /**
521 * via_init_one - discovery callback
522 * @pdev: PCI device
523 * @id: PCI table info
524 *
525 * A VIA IDE interface has been discovered. Figure out what revision
526 * and perform configuration work before handing it to the ATA layer
527 */
528
via_init_one(struct pci_dev * pdev,const struct pci_device_id * id)529 static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
530 {
531 /* Early VIA without UDMA support */
532 static const struct ata_port_info via_mwdma_info = {
533 .flags = ATA_FLAG_SLAVE_POSS,
534 .pio_mask = ATA_PIO4,
535 .mwdma_mask = ATA_MWDMA2,
536 .port_ops = &via_port_ops
537 };
538 /* Ditto with IRQ masking required */
539 static const struct ata_port_info via_mwdma_info_borked = {
540 .flags = ATA_FLAG_SLAVE_POSS,
541 .pio_mask = ATA_PIO4,
542 .mwdma_mask = ATA_MWDMA2,
543 .port_ops = &via_port_ops_noirq,
544 };
545 /* VIA UDMA 33 devices (and borked 66) */
546 static const struct ata_port_info via_udma33_info = {
547 .flags = ATA_FLAG_SLAVE_POSS,
548 .pio_mask = ATA_PIO4,
549 .mwdma_mask = ATA_MWDMA2,
550 .udma_mask = ATA_UDMA2,
551 .port_ops = &via_port_ops
552 };
553 /* VIA UDMA 66 devices */
554 static const struct ata_port_info via_udma66_info = {
555 .flags = ATA_FLAG_SLAVE_POSS,
556 .pio_mask = ATA_PIO4,
557 .mwdma_mask = ATA_MWDMA2,
558 .udma_mask = ATA_UDMA4,
559 .port_ops = &via_port_ops
560 };
561 /* VIA UDMA 100 devices */
562 static const struct ata_port_info via_udma100_info = {
563 .flags = ATA_FLAG_SLAVE_POSS,
564 .pio_mask = ATA_PIO4,
565 .mwdma_mask = ATA_MWDMA2,
566 .udma_mask = ATA_UDMA5,
567 .port_ops = &via_port_ops
568 };
569 /* UDMA133 with bad AST (All current 133) */
570 static const struct ata_port_info via_udma133_info = {
571 .flags = ATA_FLAG_SLAVE_POSS,
572 .pio_mask = ATA_PIO4,
573 .mwdma_mask = ATA_MWDMA2,
574 .udma_mask = ATA_UDMA6, /* FIXME: should check north bridge */
575 .port_ops = &via_port_ops
576 };
577 const struct ata_port_info *ppi[] = { NULL, NULL };
578 struct pci_dev *isa;
579 const struct via_isa_bridge *config;
580 u8 enable;
581 unsigned long flags = id->driver_data;
582 int rc;
583
584 ata_print_version_once(&pdev->dev, DRV_VERSION);
585
586 rc = pcim_enable_device(pdev);
587 if (rc)
588 return rc;
589
590 if (flags & VIA_IDFLAG_SINGLE)
591 ppi[1] = &ata_dummy_port_info;
592
593 /* To find out how the IDE will behave and what features we
594 actually have to look at the bridge not the IDE controller */
595 for (config = via_isa_bridges; config->id != PCI_DEVICE_ID_VIA_ANON;
596 config++)
597 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
598 !!(config->flags & VIA_BAD_ID),
599 config->id, NULL))) {
600 u8 rev = isa->revision;
601 pci_dev_put(isa);
602
603 if ((id->device == 0x0415 || id->device == 0x3164) &&
604 (config->id != id->device))
605 continue;
606
607 if (rev >= config->rev_min && rev <= config->rev_max)
608 break;
609 }
610
611 if (!(config->flags & VIA_NO_ENABLES)) {
612 /* 0x40 low bits indicate enabled channels */
613 pci_read_config_byte(pdev, 0x40 , &enable);
614 enable &= 3;
615 if (enable == 0)
616 return -ENODEV;
617 }
618
619 /* Clock set up */
620 switch (config->udma_mask) {
621 case 0x00:
622 if (config->flags & VIA_NO_UNMASK)
623 ppi[0] = &via_mwdma_info_borked;
624 else
625 ppi[0] = &via_mwdma_info;
626 break;
627 case ATA_UDMA2:
628 ppi[0] = &via_udma33_info;
629 break;
630 case ATA_UDMA4:
631 ppi[0] = &via_udma66_info;
632 break;
633 case ATA_UDMA5:
634 ppi[0] = &via_udma100_info;
635 break;
636 case ATA_UDMA6:
637 ppi[0] = &via_udma133_info;
638 break;
639 default:
640 WARN_ON(1);
641 return -ENODEV;
642 }
643
644 via_fixup(pdev, config);
645
646 /* We have established the device type, now fire it up */
647 return ata_pci_bmdma_init_one(pdev, ppi, &via_sht, (void *)config, 0);
648 }
649
650 #ifdef CONFIG_PM_SLEEP
651 /**
652 * via_reinit_one - reinit after resume
653 * @pdev: PCI device
654 *
655 * Called when the VIA PATA device is resumed. We must then
656 * reconfigure the fifo and other setup we may have altered. In
657 * addition the kernel needs to have the resume methods on PCI
658 * quirk supported.
659 */
660
via_reinit_one(struct pci_dev * pdev)661 static int via_reinit_one(struct pci_dev *pdev)
662 {
663 struct ata_host *host = pci_get_drvdata(pdev);
664 int rc;
665
666 rc = ata_pci_device_do_resume(pdev);
667 if (rc)
668 return rc;
669
670 via_fixup(pdev, host->private_data);
671
672 ata_host_resume(host);
673 return 0;
674 }
675 #endif
676
677 static const struct pci_device_id via[] = {
678 { PCI_VDEVICE(VIA, 0x0415), },
679 { PCI_VDEVICE(VIA, 0x0571), },
680 { PCI_VDEVICE(VIA, 0x0581), },
681 { PCI_VDEVICE(VIA, 0x1571), },
682 { PCI_VDEVICE(VIA, 0x3164), },
683 { PCI_VDEVICE(VIA, 0x5324), },
684 { PCI_VDEVICE(VIA, 0xC409), VIA_IDFLAG_SINGLE },
685 { PCI_VDEVICE(VIA, 0x9001), VIA_IDFLAG_SINGLE },
686
687 { },
688 };
689
690 static struct pci_driver via_pci_driver = {
691 .name = DRV_NAME,
692 .id_table = via,
693 .probe = via_init_one,
694 .remove = ata_pci_remove_one,
695 #ifdef CONFIG_PM_SLEEP
696 .suspend = ata_pci_device_suspend,
697 .resume = via_reinit_one,
698 #endif
699 };
700
701 module_pci_driver(via_pci_driver);
702
703 MODULE_AUTHOR("Alan Cox");
704 MODULE_DESCRIPTION("low-level driver for VIA PATA");
705 MODULE_LICENSE("GPL");
706 MODULE_DEVICE_TABLE(pci, via);
707 MODULE_VERSION(DRV_VERSION);
708