xref: /linux/arch/arm64/kvm/vgic/vgic-v3.c (revision c4bb3a2d641c02ac2c7aa45534b4cefdf9bf416b)
1 // SPDX-License-Identifier: GPL-2.0-only
2 
3 #include <linux/irqchip/arm-gic-v3.h>
4 #include <linux/irq.h>
5 #include <linux/irqdomain.h>
6 #include <linux/kstrtox.h>
7 #include <linux/kvm.h>
8 #include <linux/kvm_host.h>
9 #include <kvm/arm_vgic.h>
10 #include <asm/kvm_hyp.h>
11 #include <asm/kvm_mmu.h>
12 #include <asm/kvm_asm.h>
13 
14 #include "vgic.h"
15 
16 static bool group0_trap;
17 static bool group1_trap;
18 static bool common_trap;
19 static bool dir_trap;
20 static bool gicv4_enable;
21 
vgic_v3_set_underflow(struct kvm_vcpu * vcpu)22 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
23 {
24 	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
25 
26 	cpuif->vgic_hcr |= ICH_HCR_UIE;
27 }
28 
lr_signals_eoi_mi(u64 lr_val)29 static bool lr_signals_eoi_mi(u64 lr_val)
30 {
31 	return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) &&
32 	       !(lr_val & ICH_LR_HW);
33 }
34 
vgic_v3_fold_lr_state(struct kvm_vcpu * vcpu)35 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
36 {
37 	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
38 	struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3;
39 	u32 model = vcpu->kvm->arch.vgic.vgic_model;
40 	int lr;
41 
42 	DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
43 
44 	cpuif->vgic_hcr &= ~ICH_HCR_UIE;
45 
46 	for (lr = 0; lr < cpuif->used_lrs; lr++) {
47 		u64 val = cpuif->vgic_lr[lr];
48 		u32 intid, cpuid;
49 		struct vgic_irq *irq;
50 		bool is_v2_sgi = false;
51 		bool deactivated;
52 
53 		cpuid = val & GICH_LR_PHYSID_CPUID;
54 		cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
55 
56 		if (model == KVM_DEV_TYPE_ARM_VGIC_V3) {
57 			intid = val & ICH_LR_VIRTUAL_ID_MASK;
58 		} else {
59 			intid = val & GICH_LR_VIRTUALID;
60 			is_v2_sgi = vgic_irq_is_sgi(intid);
61 		}
62 
63 		/* Notify fds when the guest EOI'ed a level-triggered IRQ */
64 		if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
65 			kvm_notify_acked_irq(vcpu->kvm, 0,
66 					     intid - VGIC_NR_PRIVATE_IRQS);
67 
68 		irq = vgic_get_vcpu_irq(vcpu, intid);
69 		if (!irq)	/* An LPI could have been unmapped. */
70 			continue;
71 
72 		raw_spin_lock(&irq->irq_lock);
73 
74 		/* Always preserve the active bit, note deactivation */
75 		deactivated = irq->active && !(val & ICH_LR_ACTIVE_BIT);
76 		irq->active = !!(val & ICH_LR_ACTIVE_BIT);
77 
78 		if (irq->active && is_v2_sgi)
79 			irq->active_source = cpuid;
80 
81 		/* Edge is the only case where we preserve the pending bit */
82 		if (irq->config == VGIC_CONFIG_EDGE &&
83 		    (val & ICH_LR_PENDING_BIT)) {
84 			irq->pending_latch = true;
85 
86 			if (is_v2_sgi)
87 				irq->source |= (1 << cpuid);
88 		}
89 
90 		/*
91 		 * Clear soft pending state when level irqs have been acked.
92 		 */
93 		if (irq->config == VGIC_CONFIG_LEVEL && !(val & ICH_LR_STATE))
94 			irq->pending_latch = false;
95 
96 		/* Handle resampling for mapped interrupts if required */
97 		vgic_irq_handle_resampling(irq, deactivated, val & ICH_LR_PENDING_BIT);
98 
99 		raw_spin_unlock(&irq->irq_lock);
100 		vgic_put_irq(vcpu->kvm, irq);
101 	}
102 
103 	cpuif->used_lrs = 0;
104 }
105 
106 /* Requires the irq to be locked already */
vgic_v3_populate_lr(struct kvm_vcpu * vcpu,struct vgic_irq * irq,int lr)107 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
108 {
109 	u32 model = vcpu->kvm->arch.vgic.vgic_model;
110 	u64 val = irq->intid;
111 	bool allow_pending = true, is_v2_sgi;
112 
113 	is_v2_sgi = (vgic_irq_is_sgi(irq->intid) &&
114 		     model == KVM_DEV_TYPE_ARM_VGIC_V2);
115 
116 	if (irq->active) {
117 		val |= ICH_LR_ACTIVE_BIT;
118 		if (is_v2_sgi)
119 			val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT;
120 		if (vgic_irq_is_multi_sgi(irq)) {
121 			allow_pending = false;
122 			val |= ICH_LR_EOI;
123 		}
124 	}
125 
126 	if (irq->hw && !vgic_irq_needs_resampling(irq)) {
127 		val |= ICH_LR_HW;
128 		val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
129 		/*
130 		 * Never set pending+active on a HW interrupt, as the
131 		 * pending state is kept at the physical distributor
132 		 * level.
133 		 */
134 		if (irq->active)
135 			allow_pending = false;
136 	} else {
137 		if (irq->config == VGIC_CONFIG_LEVEL) {
138 			val |= ICH_LR_EOI;
139 
140 			/*
141 			 * Software resampling doesn't work very well
142 			 * if we allow P+A, so let's not do that.
143 			 */
144 			if (irq->active)
145 				allow_pending = false;
146 		}
147 	}
148 
149 	if (allow_pending && irq_is_pending(irq)) {
150 		val |= ICH_LR_PENDING_BIT;
151 
152 		if (irq->config == VGIC_CONFIG_EDGE)
153 			irq->pending_latch = false;
154 
155 		if (vgic_irq_is_sgi(irq->intid) &&
156 		    model == KVM_DEV_TYPE_ARM_VGIC_V2) {
157 			u32 src = ffs(irq->source);
158 
159 			if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",
160 					   irq->intid))
161 				return;
162 
163 			val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
164 			irq->source &= ~(1 << (src - 1));
165 			if (irq->source) {
166 				irq->pending_latch = true;
167 				val |= ICH_LR_EOI;
168 			}
169 		}
170 	}
171 
172 	/*
173 	 * Level-triggered mapped IRQs are special because we only observe
174 	 * rising edges as input to the VGIC.  We therefore lower the line
175 	 * level here, so that we can take new virtual IRQs.  See
176 	 * vgic_v3_fold_lr_state for more info.
177 	 */
178 	if (vgic_irq_is_mapped_level(irq) && (val & ICH_LR_PENDING_BIT))
179 		irq->line_level = false;
180 
181 	if (irq->group)
182 		val |= ICH_LR_GROUP;
183 
184 	val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
185 
186 	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
187 }
188 
vgic_v3_clear_lr(struct kvm_vcpu * vcpu,int lr)189 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
190 {
191 	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
192 }
193 
vgic_v3_set_vmcr(struct kvm_vcpu * vcpu,struct vgic_vmcr * vmcrp)194 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
195 {
196 	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
197 	u32 model = vcpu->kvm->arch.vgic.vgic_model;
198 	u32 vmcr;
199 
200 	if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
201 		vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) &
202 			ICH_VMCR_ACK_CTL_MASK;
203 		vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) &
204 			ICH_VMCR_FIQ_EN_MASK;
205 	} else {
206 		/*
207 		 * When emulating GICv3 on GICv3 with SRE=1 on the
208 		 * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
209 		 */
210 		vmcr = ICH_VMCR_FIQ_EN_MASK;
211 	}
212 
213 	vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
214 	vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
215 	vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
216 	vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
217 	vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
218 	vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
219 	vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
220 
221 	cpu_if->vgic_vmcr = vmcr;
222 }
223 
vgic_v3_get_vmcr(struct kvm_vcpu * vcpu,struct vgic_vmcr * vmcrp)224 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
225 {
226 	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
227 	u32 model = vcpu->kvm->arch.vgic.vgic_model;
228 	u32 vmcr;
229 
230 	vmcr = cpu_if->vgic_vmcr;
231 
232 	if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
233 		vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >>
234 			ICH_VMCR_ACK_CTL_SHIFT;
235 		vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >>
236 			ICH_VMCR_FIQ_EN_SHIFT;
237 	} else {
238 		/*
239 		 * When emulating GICv3 on GICv3 with SRE=1 on the
240 		 * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
241 		 */
242 		vmcrp->fiqen = 1;
243 		vmcrp->ackctl = 0;
244 	}
245 
246 	vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
247 	vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT;
248 	vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
249 	vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
250 	vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
251 	vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
252 	vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
253 }
254 
255 #define INITIAL_PENDBASER_VALUE						  \
256 	(GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)		| \
257 	GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner)	| \
258 	GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
259 
vgic_v3_enable(struct kvm_vcpu * vcpu)260 void vgic_v3_enable(struct kvm_vcpu *vcpu)
261 {
262 	struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
263 
264 	/*
265 	 * By forcing VMCR to zero, the GIC will restore the binary
266 	 * points to their reset values. Anything else resets to zero
267 	 * anyway.
268 	 */
269 	vgic_v3->vgic_vmcr = 0;
270 
271 	/*
272 	 * If we are emulating a GICv3, we do it in an non-GICv2-compatible
273 	 * way, so we force SRE to 1 to demonstrate this to the guest.
274 	 * Also, we don't support any form of IRQ/FIQ bypass.
275 	 * This goes with the spec allowing the value to be RAO/WI.
276 	 */
277 	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
278 		vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
279 				     ICC_SRE_EL1_DFB |
280 				     ICC_SRE_EL1_SRE);
281 		vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
282 	} else {
283 		vgic_v3->vgic_sre = 0;
284 	}
285 
286 	vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
287 					   ICH_VTR_ID_BITS_MASK) >>
288 					   ICH_VTR_ID_BITS_SHIFT;
289 	vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
290 					    ICH_VTR_PRI_BITS_MASK) >>
291 					    ICH_VTR_PRI_BITS_SHIFT) + 1;
292 
293 	/* Get the show on the road... */
294 	vgic_v3->vgic_hcr = ICH_HCR_EN;
295 }
296 
vcpu_set_ich_hcr(struct kvm_vcpu * vcpu)297 void vcpu_set_ich_hcr(struct kvm_vcpu *vcpu)
298 {
299 	struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
300 
301 	/* Hide GICv3 sysreg if necessary */
302 	if (!kvm_has_gicv3(vcpu->kvm)) {
303 		vgic_v3->vgic_hcr |= ICH_HCR_TALL0 | ICH_HCR_TALL1 | ICH_HCR_TC;
304 		return;
305 	}
306 
307 	if (group0_trap)
308 		vgic_v3->vgic_hcr |= ICH_HCR_TALL0;
309 	if (group1_trap)
310 		vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
311 	if (common_trap)
312 		vgic_v3->vgic_hcr |= ICH_HCR_TC;
313 	if (dir_trap)
314 		vgic_v3->vgic_hcr |= ICH_HCR_TDIR;
315 }
316 
vgic_v3_lpi_sync_pending_status(struct kvm * kvm,struct vgic_irq * irq)317 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
318 {
319 	struct kvm_vcpu *vcpu;
320 	int byte_offset, bit_nr;
321 	gpa_t pendbase, ptr;
322 	bool status;
323 	u8 val;
324 	int ret;
325 	unsigned long flags;
326 
327 retry:
328 	vcpu = irq->target_vcpu;
329 	if (!vcpu)
330 		return 0;
331 
332 	pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
333 
334 	byte_offset = irq->intid / BITS_PER_BYTE;
335 	bit_nr = irq->intid % BITS_PER_BYTE;
336 	ptr = pendbase + byte_offset;
337 
338 	ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
339 	if (ret)
340 		return ret;
341 
342 	status = val & (1 << bit_nr);
343 
344 	raw_spin_lock_irqsave(&irq->irq_lock, flags);
345 	if (irq->target_vcpu != vcpu) {
346 		raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
347 		goto retry;
348 	}
349 	irq->pending_latch = status;
350 	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
351 
352 	if (status) {
353 		/* clear consumed data */
354 		val &= ~(1 << bit_nr);
355 		ret = vgic_write_guest_lock(kvm, ptr, &val, 1);
356 		if (ret)
357 			return ret;
358 	}
359 	return 0;
360 }
361 
362 /*
363  * The deactivation of the doorbell interrupt will trigger the
364  * unmapping of the associated vPE.
365  */
unmap_all_vpes(struct kvm * kvm)366 static void unmap_all_vpes(struct kvm *kvm)
367 {
368 	struct vgic_dist *dist = &kvm->arch.vgic;
369 	int i;
370 
371 	for (i = 0; i < dist->its_vm.nr_vpes; i++)
372 		free_irq(dist->its_vm.vpes[i]->irq, kvm_get_vcpu(kvm, i));
373 }
374 
map_all_vpes(struct kvm * kvm)375 static void map_all_vpes(struct kvm *kvm)
376 {
377 	struct vgic_dist *dist = &kvm->arch.vgic;
378 	int i;
379 
380 	for (i = 0; i < dist->its_vm.nr_vpes; i++)
381 		WARN_ON(vgic_v4_request_vpe_irq(kvm_get_vcpu(kvm, i),
382 						dist->its_vm.vpes[i]->irq));
383 }
384 
385 /*
386  * vgic_v3_save_pending_tables - Save the pending tables into guest RAM
387  * kvm lock and all vcpu lock must be held
388  */
vgic_v3_save_pending_tables(struct kvm * kvm)389 int vgic_v3_save_pending_tables(struct kvm *kvm)
390 {
391 	struct vgic_dist *dist = &kvm->arch.vgic;
392 	struct vgic_irq *irq;
393 	gpa_t last_ptr = ~(gpa_t)0;
394 	bool vlpi_avail = false;
395 	unsigned long index;
396 	int ret = 0;
397 	u8 val;
398 
399 	if (unlikely(!vgic_initialized(kvm)))
400 		return -ENXIO;
401 
402 	/*
403 	 * A preparation for getting any VLPI states.
404 	 * The above vgic initialized check also ensures that the allocation
405 	 * and enabling of the doorbells have already been done.
406 	 */
407 	if (kvm_vgic_global_state.has_gicv4_1) {
408 		unmap_all_vpes(kvm);
409 		vlpi_avail = true;
410 	}
411 
412 	xa_for_each(&dist->lpi_xa, index, irq) {
413 		int byte_offset, bit_nr;
414 		struct kvm_vcpu *vcpu;
415 		gpa_t pendbase, ptr;
416 		bool is_pending;
417 		bool stored;
418 
419 		vcpu = irq->target_vcpu;
420 		if (!vcpu)
421 			continue;
422 
423 		pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
424 
425 		byte_offset = irq->intid / BITS_PER_BYTE;
426 		bit_nr = irq->intid % BITS_PER_BYTE;
427 		ptr = pendbase + byte_offset;
428 
429 		if (ptr != last_ptr) {
430 			ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
431 			if (ret)
432 				goto out;
433 			last_ptr = ptr;
434 		}
435 
436 		stored = val & (1U << bit_nr);
437 
438 		is_pending = irq->pending_latch;
439 
440 		if (irq->hw && vlpi_avail)
441 			vgic_v4_get_vlpi_state(irq, &is_pending);
442 
443 		if (stored == is_pending)
444 			continue;
445 
446 		if (is_pending)
447 			val |= 1 << bit_nr;
448 		else
449 			val &= ~(1 << bit_nr);
450 
451 		ret = vgic_write_guest_lock(kvm, ptr, &val, 1);
452 		if (ret)
453 			goto out;
454 	}
455 
456 out:
457 	if (vlpi_avail)
458 		map_all_vpes(kvm);
459 
460 	return ret;
461 }
462 
463 /**
464  * vgic_v3_rdist_overlap - check if a region overlaps with any
465  * existing redistributor region
466  *
467  * @kvm: kvm handle
468  * @base: base of the region
469  * @size: size of region
470  *
471  * Return: true if there is an overlap
472  */
vgic_v3_rdist_overlap(struct kvm * kvm,gpa_t base,size_t size)473 bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size)
474 {
475 	struct vgic_dist *d = &kvm->arch.vgic;
476 	struct vgic_redist_region *rdreg;
477 
478 	list_for_each_entry(rdreg, &d->rd_regions, list) {
479 		if ((base + size > rdreg->base) &&
480 			(base < rdreg->base + vgic_v3_rd_region_size(kvm, rdreg)))
481 			return true;
482 	}
483 	return false;
484 }
485 
486 /*
487  * Check for overlapping regions and for regions crossing the end of memory
488  * for base addresses which have already been set.
489  */
vgic_v3_check_base(struct kvm * kvm)490 bool vgic_v3_check_base(struct kvm *kvm)
491 {
492 	struct vgic_dist *d = &kvm->arch.vgic;
493 	struct vgic_redist_region *rdreg;
494 
495 	if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
496 	    d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
497 		return false;
498 
499 	list_for_each_entry(rdreg, &d->rd_regions, list) {
500 		size_t sz = vgic_v3_rd_region_size(kvm, rdreg);
501 
502 		if (vgic_check_iorange(kvm, VGIC_ADDR_UNDEF,
503 				       rdreg->base, SZ_64K, sz))
504 			return false;
505 	}
506 
507 	if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base))
508 		return true;
509 
510 	return !vgic_v3_rdist_overlap(kvm, d->vgic_dist_base,
511 				      KVM_VGIC_V3_DIST_SIZE);
512 }
513 
514 /**
515  * vgic_v3_rdist_free_slot - Look up registered rdist regions and identify one
516  * which has free space to put a new rdist region.
517  *
518  * @rd_regions: redistributor region list head
519  *
520  * A redistributor regions maps n redistributors, n = region size / (2 x 64kB).
521  * Stride between redistributors is 0 and regions are filled in the index order.
522  *
523  * Return: the redist region handle, if any, that has space to map a new rdist
524  * region.
525  */
vgic_v3_rdist_free_slot(struct list_head * rd_regions)526 struct vgic_redist_region *vgic_v3_rdist_free_slot(struct list_head *rd_regions)
527 {
528 	struct vgic_redist_region *rdreg;
529 
530 	list_for_each_entry(rdreg, rd_regions, list) {
531 		if (!vgic_v3_redist_region_full(rdreg))
532 			return rdreg;
533 	}
534 	return NULL;
535 }
536 
vgic_v3_rdist_region_from_index(struct kvm * kvm,u32 index)537 struct vgic_redist_region *vgic_v3_rdist_region_from_index(struct kvm *kvm,
538 							   u32 index)
539 {
540 	struct list_head *rd_regions = &kvm->arch.vgic.rd_regions;
541 	struct vgic_redist_region *rdreg;
542 
543 	list_for_each_entry(rdreg, rd_regions, list) {
544 		if (rdreg->index == index)
545 			return rdreg;
546 	}
547 	return NULL;
548 }
549 
550 
vgic_v3_map_resources(struct kvm * kvm)551 int vgic_v3_map_resources(struct kvm *kvm)
552 {
553 	struct vgic_dist *dist = &kvm->arch.vgic;
554 	struct kvm_vcpu *vcpu;
555 	unsigned long c;
556 
557 	kvm_for_each_vcpu(c, vcpu, kvm) {
558 		struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
559 
560 		if (IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) {
561 			kvm_debug("vcpu %ld redistributor base not set\n", c);
562 			return -ENXIO;
563 		}
564 	}
565 
566 	if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base)) {
567 		kvm_debug("Need to set vgic distributor addresses first\n");
568 		return -ENXIO;
569 	}
570 
571 	if (!vgic_v3_check_base(kvm)) {
572 		kvm_debug("VGIC redist and dist frames overlap\n");
573 		return -EINVAL;
574 	}
575 
576 	/*
577 	 * For a VGICv3 we require the userland to explicitly initialize
578 	 * the VGIC before we need to use it.
579 	 */
580 	if (!vgic_initialized(kvm)) {
581 		return -EBUSY;
582 	}
583 
584 	if (kvm_vgic_global_state.has_gicv4_1)
585 		vgic_v4_configure_vsgis(kvm);
586 
587 	return 0;
588 }
589 
590 DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap);
591 
early_group0_trap_cfg(char * buf)592 static int __init early_group0_trap_cfg(char *buf)
593 {
594 	return kstrtobool(buf, &group0_trap);
595 }
596 early_param("kvm-arm.vgic_v3_group0_trap", early_group0_trap_cfg);
597 
early_group1_trap_cfg(char * buf)598 static int __init early_group1_trap_cfg(char *buf)
599 {
600 	return kstrtobool(buf, &group1_trap);
601 }
602 early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg);
603 
early_common_trap_cfg(char * buf)604 static int __init early_common_trap_cfg(char *buf)
605 {
606 	return kstrtobool(buf, &common_trap);
607 }
608 early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg);
609 
early_gicv4_enable(char * buf)610 static int __init early_gicv4_enable(char *buf)
611 {
612 	return kstrtobool(buf, &gicv4_enable);
613 }
614 early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable);
615 
616 static const struct midr_range broken_seis[] = {
617 	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM),
618 	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM),
619 	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO),
620 	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO),
621 	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX),
622 	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX),
623 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD),
624 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE),
625 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO),
626 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),
627 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),
628 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),
629 	{},
630 };
631 
vgic_v3_broken_seis(void)632 static bool vgic_v3_broken_seis(void)
633 {
634 	return ((kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK) &&
635 		is_midr_in_range_list(read_cpuid_id(), broken_seis));
636 }
637 
638 /**
639  * vgic_v3_probe - probe for a VGICv3 compatible interrupt controller
640  * @info:	pointer to the GIC description
641  *
642  * Returns 0 if the VGICv3 has been probed successfully, returns an error code
643  * otherwise
644  */
vgic_v3_probe(const struct gic_kvm_info * info)645 int vgic_v3_probe(const struct gic_kvm_info *info)
646 {
647 	u64 ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_gic_config);
648 	bool has_v2;
649 	int ret;
650 
651 	has_v2 = ich_vtr_el2 >> 63;
652 	ich_vtr_el2 = (u32)ich_vtr_el2;
653 
654 	/*
655 	 * The ListRegs field is 5 bits, but there is an architectural
656 	 * maximum of 16 list registers. Just ignore bit 4...
657 	 */
658 	kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
659 	kvm_vgic_global_state.can_emulate_gicv2 = false;
660 	kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
661 
662 	/* GICv4 support? */
663 	if (info->has_v4) {
664 		kvm_vgic_global_state.has_gicv4 = gicv4_enable;
665 		kvm_vgic_global_state.has_gicv4_1 = info->has_v4_1 && gicv4_enable;
666 		kvm_info("GICv4%s support %sabled\n",
667 			 kvm_vgic_global_state.has_gicv4_1 ? ".1" : "",
668 			 gicv4_enable ? "en" : "dis");
669 	}
670 
671 	kvm_vgic_global_state.vcpu_base = 0;
672 
673 	if (!info->vcpu.start) {
674 		kvm_info("GICv3: no GICV resource entry\n");
675 	} else if (!has_v2) {
676 		pr_warn(FW_BUG "CPU interface incapable of MMIO access\n");
677 	} else if (!PAGE_ALIGNED(info->vcpu.start)) {
678 		pr_warn("GICV physical address 0x%llx not page aligned\n",
679 			(unsigned long long)info->vcpu.start);
680 	} else if (kvm_get_mode() != KVM_MODE_PROTECTED) {
681 		kvm_vgic_global_state.vcpu_base = info->vcpu.start;
682 		kvm_vgic_global_state.can_emulate_gicv2 = true;
683 		ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
684 		if (ret) {
685 			kvm_err("Cannot register GICv2 KVM device.\n");
686 			return ret;
687 		}
688 		kvm_info("vgic-v2@%llx\n", info->vcpu.start);
689 	}
690 	ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
691 	if (ret) {
692 		kvm_err("Cannot register GICv3 KVM device.\n");
693 		kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
694 		return ret;
695 	}
696 
697 	if (kvm_vgic_global_state.vcpu_base == 0)
698 		kvm_info("disabling GICv2 emulation\n");
699 
700 	if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_30115)) {
701 		group0_trap = true;
702 		group1_trap = true;
703 	}
704 
705 	if (vgic_v3_broken_seis()) {
706 		kvm_info("GICv3 with broken locally generated SEI\n");
707 
708 		kvm_vgic_global_state.ich_vtr_el2 &= ~ICH_VTR_SEIS_MASK;
709 		group0_trap = true;
710 		group1_trap = true;
711 		if (ich_vtr_el2 & ICH_VTR_TDS_MASK)
712 			dir_trap = true;
713 		else
714 			common_trap = true;
715 	}
716 
717 	if (group0_trap || group1_trap || common_trap | dir_trap) {
718 		kvm_info("GICv3 sysreg trapping enabled ([%s%s%s%s], reduced performance)\n",
719 			 group0_trap ? "G0" : "",
720 			 group1_trap ? "G1" : "",
721 			 common_trap ? "C"  : "",
722 			 dir_trap    ? "D"  : "");
723 		static_branch_enable(&vgic_v3_cpuif_trap);
724 	}
725 
726 	kvm_vgic_global_state.vctrl_base = NULL;
727 	kvm_vgic_global_state.type = VGIC_V3;
728 	kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
729 
730 	return 0;
731 }
732 
vgic_v3_load(struct kvm_vcpu * vcpu)733 void vgic_v3_load(struct kvm_vcpu *vcpu)
734 {
735 	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
736 
737 	kvm_call_hyp(__vgic_v3_restore_vmcr_aprs, cpu_if);
738 
739 	if (has_vhe())
740 		__vgic_v3_activate_traps(cpu_if);
741 
742 	WARN_ON(vgic_v4_load(vcpu));
743 }
744 
vgic_v3_put(struct kvm_vcpu * vcpu)745 void vgic_v3_put(struct kvm_vcpu *vcpu)
746 {
747 	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
748 
749 	kvm_call_hyp(__vgic_v3_save_vmcr_aprs, cpu_if);
750 	WARN_ON(vgic_v4_put(vcpu));
751 
752 	if (has_vhe())
753 		__vgic_v3_deactivate_traps(cpu_if);
754 }
755