1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/irqchip/arm-gic-v3.h>
4 #include <linux/irq.h>
5 #include <linux/irqdomain.h>
6 #include <linux/kstrtox.h>
7 #include <linux/kvm.h>
8 #include <linux/kvm_host.h>
9 #include <linux/string_choices.h>
10 #include <kvm/arm_vgic.h>
11 #include <asm/kvm_hyp.h>
12 #include <asm/kvm_mmu.h>
13 #include <asm/kvm_asm.h>
14
15 #include "vgic.h"
16
17 static bool group0_trap;
18 static bool group1_trap;
19 static bool common_trap;
20 static bool dir_trap;
21 static bool gicv4_enable;
22
vgic_v3_set_underflow(struct kvm_vcpu * vcpu)23 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
24 {
25 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
26
27 cpuif->vgic_hcr |= ICH_HCR_EL2_UIE;
28 }
29
lr_signals_eoi_mi(u64 lr_val)30 static bool lr_signals_eoi_mi(u64 lr_val)
31 {
32 return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) &&
33 !(lr_val & ICH_LR_HW);
34 }
35
vgic_v3_fold_lr_state(struct kvm_vcpu * vcpu)36 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
37 {
38 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
39 struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3;
40 u32 model = vcpu->kvm->arch.vgic.vgic_model;
41 int lr;
42
43 DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
44
45 cpuif->vgic_hcr &= ~ICH_HCR_EL2_UIE;
46
47 for (lr = 0; lr < cpuif->used_lrs; lr++) {
48 u64 val = cpuif->vgic_lr[lr];
49 u32 intid, cpuid;
50 struct vgic_irq *irq;
51 bool is_v2_sgi = false;
52 bool deactivated;
53
54 cpuid = val & GICH_LR_PHYSID_CPUID;
55 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
56
57 if (model == KVM_DEV_TYPE_ARM_VGIC_V3) {
58 intid = val & ICH_LR_VIRTUAL_ID_MASK;
59 } else {
60 intid = val & GICH_LR_VIRTUALID;
61 is_v2_sgi = vgic_irq_is_sgi(intid);
62 }
63
64 /* Notify fds when the guest EOI'ed a level-triggered IRQ */
65 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
66 kvm_notify_acked_irq(vcpu->kvm, 0,
67 intid - VGIC_NR_PRIVATE_IRQS);
68
69 irq = vgic_get_vcpu_irq(vcpu, intid);
70 if (!irq) /* An LPI could have been unmapped. */
71 continue;
72
73 raw_spin_lock(&irq->irq_lock);
74
75 /* Always preserve the active bit, note deactivation */
76 deactivated = irq->active && !(val & ICH_LR_ACTIVE_BIT);
77 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
78
79 if (irq->active && is_v2_sgi)
80 irq->active_source = cpuid;
81
82 /* Edge is the only case where we preserve the pending bit */
83 if (irq->config == VGIC_CONFIG_EDGE &&
84 (val & ICH_LR_PENDING_BIT)) {
85 irq->pending_latch = true;
86
87 if (is_v2_sgi)
88 irq->source |= (1 << cpuid);
89 }
90
91 /*
92 * Clear soft pending state when level irqs have been acked.
93 */
94 if (irq->config == VGIC_CONFIG_LEVEL && !(val & ICH_LR_STATE))
95 irq->pending_latch = false;
96
97 /* Handle resampling for mapped interrupts if required */
98 vgic_irq_handle_resampling(irq, deactivated, val & ICH_LR_PENDING_BIT);
99
100 raw_spin_unlock(&irq->irq_lock);
101 vgic_put_irq(vcpu->kvm, irq);
102 }
103
104 cpuif->used_lrs = 0;
105 }
106
107 /* Requires the irq to be locked already */
vgic_v3_populate_lr(struct kvm_vcpu * vcpu,struct vgic_irq * irq,int lr)108 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
109 {
110 u32 model = vcpu->kvm->arch.vgic.vgic_model;
111 u64 val = irq->intid;
112 bool allow_pending = true, is_v2_sgi;
113
114 is_v2_sgi = (vgic_irq_is_sgi(irq->intid) &&
115 model == KVM_DEV_TYPE_ARM_VGIC_V2);
116
117 if (irq->active) {
118 val |= ICH_LR_ACTIVE_BIT;
119 if (is_v2_sgi)
120 val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT;
121 if (vgic_irq_is_multi_sgi(irq)) {
122 allow_pending = false;
123 val |= ICH_LR_EOI;
124 }
125 }
126
127 if (irq->hw && !vgic_irq_needs_resampling(irq)) {
128 val |= ICH_LR_HW;
129 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
130 /*
131 * Never set pending+active on a HW interrupt, as the
132 * pending state is kept at the physical distributor
133 * level.
134 */
135 if (irq->active)
136 allow_pending = false;
137 } else {
138 if (irq->config == VGIC_CONFIG_LEVEL) {
139 val |= ICH_LR_EOI;
140
141 /*
142 * Software resampling doesn't work very well
143 * if we allow P+A, so let's not do that.
144 */
145 if (irq->active)
146 allow_pending = false;
147 }
148 }
149
150 if (allow_pending && irq_is_pending(irq)) {
151 val |= ICH_LR_PENDING_BIT;
152
153 if (irq->config == VGIC_CONFIG_EDGE)
154 irq->pending_latch = false;
155
156 if (vgic_irq_is_sgi(irq->intid) &&
157 model == KVM_DEV_TYPE_ARM_VGIC_V2) {
158 u32 src = ffs(irq->source);
159
160 if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",
161 irq->intid))
162 return;
163
164 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
165 irq->source &= ~(1 << (src - 1));
166 if (irq->source) {
167 irq->pending_latch = true;
168 val |= ICH_LR_EOI;
169 }
170 }
171 }
172
173 /*
174 * Level-triggered mapped IRQs are special because we only observe
175 * rising edges as input to the VGIC. We therefore lower the line
176 * level here, so that we can take new virtual IRQs. See
177 * vgic_v3_fold_lr_state for more info.
178 */
179 if (vgic_irq_is_mapped_level(irq) && (val & ICH_LR_PENDING_BIT))
180 irq->line_level = false;
181
182 if (irq->group)
183 val |= ICH_LR_GROUP;
184
185 val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
186
187 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
188 }
189
vgic_v3_clear_lr(struct kvm_vcpu * vcpu,int lr)190 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
191 {
192 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
193 }
194
vgic_v3_set_vmcr(struct kvm_vcpu * vcpu,struct vgic_vmcr * vmcrp)195 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
196 {
197 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
198 u32 model = vcpu->kvm->arch.vgic.vgic_model;
199 u32 vmcr;
200
201 if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
202 vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) &
203 ICH_VMCR_ACK_CTL_MASK;
204 vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) &
205 ICH_VMCR_FIQ_EN_MASK;
206 } else {
207 /*
208 * When emulating GICv3 on GICv3 with SRE=1 on the
209 * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
210 */
211 vmcr = ICH_VMCR_FIQ_EN_MASK;
212 }
213
214 vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
215 vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
216 vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
217 vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
218 vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
219 vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
220 vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
221
222 cpu_if->vgic_vmcr = vmcr;
223 }
224
vgic_v3_get_vmcr(struct kvm_vcpu * vcpu,struct vgic_vmcr * vmcrp)225 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
226 {
227 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
228 u32 model = vcpu->kvm->arch.vgic.vgic_model;
229 u32 vmcr;
230
231 vmcr = cpu_if->vgic_vmcr;
232
233 if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
234 vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >>
235 ICH_VMCR_ACK_CTL_SHIFT;
236 vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >>
237 ICH_VMCR_FIQ_EN_SHIFT;
238 } else {
239 /*
240 * When emulating GICv3 on GICv3 with SRE=1 on the
241 * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
242 */
243 vmcrp->fiqen = 1;
244 vmcrp->ackctl = 0;
245 }
246
247 vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
248 vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT;
249 vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
250 vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
251 vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
252 vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
253 vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
254 }
255
256 #define INITIAL_PENDBASER_VALUE \
257 (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) | \
258 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) | \
259 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
260
vgic_v3_enable(struct kvm_vcpu * vcpu)261 void vgic_v3_enable(struct kvm_vcpu *vcpu)
262 {
263 struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
264
265 /*
266 * By forcing VMCR to zero, the GIC will restore the binary
267 * points to their reset values. Anything else resets to zero
268 * anyway.
269 */
270 vgic_v3->vgic_vmcr = 0;
271
272 /*
273 * If we are emulating a GICv3, we do it in an non-GICv2-compatible
274 * way, so we force SRE to 1 to demonstrate this to the guest.
275 * Also, we don't support any form of IRQ/FIQ bypass.
276 * This goes with the spec allowing the value to be RAO/WI.
277 */
278 if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
279 vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
280 ICC_SRE_EL1_DFB |
281 ICC_SRE_EL1_SRE);
282 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
283 } else {
284 vgic_v3->vgic_sre = 0;
285 }
286
287 vcpu->arch.vgic_cpu.num_id_bits = FIELD_GET(ICH_VTR_EL2_IDbits,
288 kvm_vgic_global_state.ich_vtr_el2);
289 vcpu->arch.vgic_cpu.num_pri_bits = FIELD_GET(ICH_VTR_EL2_PRIbits,
290 kvm_vgic_global_state.ich_vtr_el2) + 1;
291
292 /* Get the show on the road... */
293 vgic_v3->vgic_hcr = ICH_HCR_EL2_En;
294 }
295
vcpu_set_ich_hcr(struct kvm_vcpu * vcpu)296 void vcpu_set_ich_hcr(struct kvm_vcpu *vcpu)
297 {
298 struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
299
300 if (!vgic_is_v3(vcpu->kvm))
301 return;
302
303 /* Hide GICv3 sysreg if necessary */
304 if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2 ||
305 !irqchip_in_kernel(vcpu->kvm)) {
306 vgic_v3->vgic_hcr |= (ICH_HCR_EL2_TALL0 | ICH_HCR_EL2_TALL1 |
307 ICH_HCR_EL2_TC);
308 return;
309 }
310
311 if (group0_trap)
312 vgic_v3->vgic_hcr |= ICH_HCR_EL2_TALL0;
313 if (group1_trap)
314 vgic_v3->vgic_hcr |= ICH_HCR_EL2_TALL1;
315 if (common_trap)
316 vgic_v3->vgic_hcr |= ICH_HCR_EL2_TC;
317 if (dir_trap)
318 vgic_v3->vgic_hcr |= ICH_HCR_EL2_TDIR;
319 }
320
vgic_v3_lpi_sync_pending_status(struct kvm * kvm,struct vgic_irq * irq)321 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
322 {
323 struct kvm_vcpu *vcpu;
324 int byte_offset, bit_nr;
325 gpa_t pendbase, ptr;
326 bool status;
327 u8 val;
328 int ret;
329 unsigned long flags;
330
331 retry:
332 vcpu = irq->target_vcpu;
333 if (!vcpu)
334 return 0;
335
336 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
337
338 byte_offset = irq->intid / BITS_PER_BYTE;
339 bit_nr = irq->intid % BITS_PER_BYTE;
340 ptr = pendbase + byte_offset;
341
342 ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
343 if (ret)
344 return ret;
345
346 status = val & (1 << bit_nr);
347
348 raw_spin_lock_irqsave(&irq->irq_lock, flags);
349 if (irq->target_vcpu != vcpu) {
350 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
351 goto retry;
352 }
353 irq->pending_latch = status;
354 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
355
356 if (status) {
357 /* clear consumed data */
358 val &= ~(1 << bit_nr);
359 ret = vgic_write_guest_lock(kvm, ptr, &val, 1);
360 if (ret)
361 return ret;
362 }
363 return 0;
364 }
365
366 /*
367 * The deactivation of the doorbell interrupt will trigger the
368 * unmapping of the associated vPE.
369 */
unmap_all_vpes(struct kvm * kvm)370 static void unmap_all_vpes(struct kvm *kvm)
371 {
372 struct vgic_dist *dist = &kvm->arch.vgic;
373 int i;
374
375 for (i = 0; i < dist->its_vm.nr_vpes; i++)
376 free_irq(dist->its_vm.vpes[i]->irq, kvm_get_vcpu(kvm, i));
377 }
378
map_all_vpes(struct kvm * kvm)379 static void map_all_vpes(struct kvm *kvm)
380 {
381 struct vgic_dist *dist = &kvm->arch.vgic;
382 int i;
383
384 for (i = 0; i < dist->its_vm.nr_vpes; i++)
385 WARN_ON(vgic_v4_request_vpe_irq(kvm_get_vcpu(kvm, i),
386 dist->its_vm.vpes[i]->irq));
387 }
388
389 /*
390 * vgic_v3_save_pending_tables - Save the pending tables into guest RAM
391 * kvm lock and all vcpu lock must be held
392 */
vgic_v3_save_pending_tables(struct kvm * kvm)393 int vgic_v3_save_pending_tables(struct kvm *kvm)
394 {
395 struct vgic_dist *dist = &kvm->arch.vgic;
396 struct vgic_irq *irq;
397 gpa_t last_ptr = ~(gpa_t)0;
398 bool vlpi_avail = false;
399 unsigned long index;
400 int ret = 0;
401 u8 val;
402
403 if (unlikely(!vgic_initialized(kvm)))
404 return -ENXIO;
405
406 /*
407 * A preparation for getting any VLPI states.
408 * The above vgic initialized check also ensures that the allocation
409 * and enabling of the doorbells have already been done.
410 */
411 if (kvm_vgic_global_state.has_gicv4_1) {
412 unmap_all_vpes(kvm);
413 vlpi_avail = true;
414 }
415
416 xa_for_each(&dist->lpi_xa, index, irq) {
417 int byte_offset, bit_nr;
418 struct kvm_vcpu *vcpu;
419 gpa_t pendbase, ptr;
420 bool is_pending;
421 bool stored;
422
423 vcpu = irq->target_vcpu;
424 if (!vcpu)
425 continue;
426
427 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
428
429 byte_offset = irq->intid / BITS_PER_BYTE;
430 bit_nr = irq->intid % BITS_PER_BYTE;
431 ptr = pendbase + byte_offset;
432
433 if (ptr != last_ptr) {
434 ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
435 if (ret)
436 goto out;
437 last_ptr = ptr;
438 }
439
440 stored = val & (1U << bit_nr);
441
442 is_pending = irq->pending_latch;
443
444 if (irq->hw && vlpi_avail)
445 vgic_v4_get_vlpi_state(irq, &is_pending);
446
447 if (stored == is_pending)
448 continue;
449
450 if (is_pending)
451 val |= 1 << bit_nr;
452 else
453 val &= ~(1 << bit_nr);
454
455 ret = vgic_write_guest_lock(kvm, ptr, &val, 1);
456 if (ret)
457 goto out;
458 }
459
460 out:
461 if (vlpi_avail)
462 map_all_vpes(kvm);
463
464 return ret;
465 }
466
467 /**
468 * vgic_v3_rdist_overlap - check if a region overlaps with any
469 * existing redistributor region
470 *
471 * @kvm: kvm handle
472 * @base: base of the region
473 * @size: size of region
474 *
475 * Return: true if there is an overlap
476 */
vgic_v3_rdist_overlap(struct kvm * kvm,gpa_t base,size_t size)477 bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size)
478 {
479 struct vgic_dist *d = &kvm->arch.vgic;
480 struct vgic_redist_region *rdreg;
481
482 list_for_each_entry(rdreg, &d->rd_regions, list) {
483 if ((base + size > rdreg->base) &&
484 (base < rdreg->base + vgic_v3_rd_region_size(kvm, rdreg)))
485 return true;
486 }
487 return false;
488 }
489
490 /*
491 * Check for overlapping regions and for regions crossing the end of memory
492 * for base addresses which have already been set.
493 */
vgic_v3_check_base(struct kvm * kvm)494 bool vgic_v3_check_base(struct kvm *kvm)
495 {
496 struct vgic_dist *d = &kvm->arch.vgic;
497 struct vgic_redist_region *rdreg;
498
499 if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
500 d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
501 return false;
502
503 list_for_each_entry(rdreg, &d->rd_regions, list) {
504 size_t sz = vgic_v3_rd_region_size(kvm, rdreg);
505
506 if (vgic_check_iorange(kvm, VGIC_ADDR_UNDEF,
507 rdreg->base, SZ_64K, sz))
508 return false;
509 }
510
511 if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base))
512 return true;
513
514 return !vgic_v3_rdist_overlap(kvm, d->vgic_dist_base,
515 KVM_VGIC_V3_DIST_SIZE);
516 }
517
518 /**
519 * vgic_v3_rdist_free_slot - Look up registered rdist regions and identify one
520 * which has free space to put a new rdist region.
521 *
522 * @rd_regions: redistributor region list head
523 *
524 * A redistributor regions maps n redistributors, n = region size / (2 x 64kB).
525 * Stride between redistributors is 0 and regions are filled in the index order.
526 *
527 * Return: the redist region handle, if any, that has space to map a new rdist
528 * region.
529 */
vgic_v3_rdist_free_slot(struct list_head * rd_regions)530 struct vgic_redist_region *vgic_v3_rdist_free_slot(struct list_head *rd_regions)
531 {
532 struct vgic_redist_region *rdreg;
533
534 list_for_each_entry(rdreg, rd_regions, list) {
535 if (!vgic_v3_redist_region_full(rdreg))
536 return rdreg;
537 }
538 return NULL;
539 }
540
vgic_v3_rdist_region_from_index(struct kvm * kvm,u32 index)541 struct vgic_redist_region *vgic_v3_rdist_region_from_index(struct kvm *kvm,
542 u32 index)
543 {
544 struct list_head *rd_regions = &kvm->arch.vgic.rd_regions;
545 struct vgic_redist_region *rdreg;
546
547 list_for_each_entry(rdreg, rd_regions, list) {
548 if (rdreg->index == index)
549 return rdreg;
550 }
551 return NULL;
552 }
553
554
vgic_v3_map_resources(struct kvm * kvm)555 int vgic_v3_map_resources(struct kvm *kvm)
556 {
557 struct vgic_dist *dist = &kvm->arch.vgic;
558 struct kvm_vcpu *vcpu;
559 unsigned long c;
560
561 kvm_for_each_vcpu(c, vcpu, kvm) {
562 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
563
564 if (IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) {
565 kvm_debug("vcpu %ld redistributor base not set\n", c);
566 return -ENXIO;
567 }
568 }
569
570 if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base)) {
571 kvm_debug("Need to set vgic distributor addresses first\n");
572 return -ENXIO;
573 }
574
575 if (!vgic_v3_check_base(kvm)) {
576 kvm_debug("VGIC redist and dist frames overlap\n");
577 return -EINVAL;
578 }
579
580 /*
581 * For a VGICv3 we require the userland to explicitly initialize
582 * the VGIC before we need to use it.
583 */
584 if (!vgic_initialized(kvm)) {
585 return -EBUSY;
586 }
587
588 if (kvm_vgic_global_state.has_gicv4_1)
589 vgic_v4_configure_vsgis(kvm);
590
591 return 0;
592 }
593
594 DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap);
595 DEFINE_STATIC_KEY_FALSE(vgic_v3_has_v2_compat);
596
early_group0_trap_cfg(char * buf)597 static int __init early_group0_trap_cfg(char *buf)
598 {
599 return kstrtobool(buf, &group0_trap);
600 }
601 early_param("kvm-arm.vgic_v3_group0_trap", early_group0_trap_cfg);
602
early_group1_trap_cfg(char * buf)603 static int __init early_group1_trap_cfg(char *buf)
604 {
605 return kstrtobool(buf, &group1_trap);
606 }
607 early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg);
608
early_common_trap_cfg(char * buf)609 static int __init early_common_trap_cfg(char *buf)
610 {
611 return kstrtobool(buf, &common_trap);
612 }
613 early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg);
614
early_gicv4_enable(char * buf)615 static int __init early_gicv4_enable(char *buf)
616 {
617 return kstrtobool(buf, &gicv4_enable);
618 }
619 early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable);
620
621 static const struct midr_range broken_seis[] = {
622 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM),
623 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM),
624 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO),
625 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO),
626 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX),
627 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX),
628 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD),
629 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE),
630 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO),
631 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),
632 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),
633 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),
634 {},
635 };
636
vgic_v3_broken_seis(void)637 static bool vgic_v3_broken_seis(void)
638 {
639 return ((kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_EL2_SEIS) &&
640 is_midr_in_range_list(broken_seis));
641 }
642
643 /**
644 * vgic_v3_probe - probe for a VGICv3 compatible interrupt controller
645 * @info: pointer to the GIC description
646 *
647 * Returns 0 if the VGICv3 has been probed successfully, returns an error code
648 * otherwise
649 */
vgic_v3_probe(const struct gic_kvm_info * info)650 int vgic_v3_probe(const struct gic_kvm_info *info)
651 {
652 u64 ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_gic_config);
653 bool has_v2;
654 int ret;
655
656 has_v2 = ich_vtr_el2 >> 63;
657 ich_vtr_el2 = (u32)ich_vtr_el2;
658
659 /*
660 * The ListRegs field is 5 bits, but there is an architectural
661 * maximum of 16 list registers. Just ignore bit 4...
662 */
663 kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
664 kvm_vgic_global_state.can_emulate_gicv2 = false;
665 kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
666
667 /* GICv4 support? */
668 if (info->has_v4) {
669 kvm_vgic_global_state.has_gicv4 = gicv4_enable;
670 kvm_vgic_global_state.has_gicv4_1 = info->has_v4_1 && gicv4_enable;
671 kvm_info("GICv4%s support %s\n",
672 kvm_vgic_global_state.has_gicv4_1 ? ".1" : "",
673 str_enabled_disabled(gicv4_enable));
674 }
675
676 kvm_vgic_global_state.vcpu_base = 0;
677
678 if (!info->vcpu.start) {
679 kvm_info("GICv3: no GICV resource entry\n");
680 } else if (!has_v2) {
681 pr_warn(FW_BUG "CPU interface incapable of MMIO access\n");
682 } else if (!PAGE_ALIGNED(info->vcpu.start)) {
683 pr_warn("GICV physical address 0x%llx not page aligned\n",
684 (unsigned long long)info->vcpu.start);
685 } else if (kvm_get_mode() != KVM_MODE_PROTECTED) {
686 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
687 kvm_vgic_global_state.can_emulate_gicv2 = true;
688 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
689 if (ret) {
690 kvm_err("Cannot register GICv2 KVM device.\n");
691 return ret;
692 }
693 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
694 }
695 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
696 if (ret) {
697 kvm_err("Cannot register GICv3 KVM device.\n");
698 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
699 return ret;
700 }
701
702 if (kvm_vgic_global_state.vcpu_base == 0)
703 kvm_info("disabling GICv2 emulation\n");
704
705 /*
706 * Flip the static branch if the HW supports v2, even if we're
707 * not using it (such as in protected mode).
708 */
709 if (has_v2)
710 static_branch_enable(&vgic_v3_has_v2_compat);
711
712 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_30115)) {
713 group0_trap = true;
714 group1_trap = true;
715 }
716
717 if (vgic_v3_broken_seis()) {
718 kvm_info("GICv3 with broken locally generated SEI\n");
719
720 kvm_vgic_global_state.ich_vtr_el2 &= ~ICH_VTR_EL2_SEIS;
721 group0_trap = true;
722 group1_trap = true;
723 if (ich_vtr_el2 & ICH_VTR_EL2_TDS)
724 dir_trap = true;
725 else
726 common_trap = true;
727 }
728
729 if (group0_trap || group1_trap || common_trap | dir_trap) {
730 kvm_info("GICv3 sysreg trapping enabled ([%s%s%s%s], reduced performance)\n",
731 group0_trap ? "G0" : "",
732 group1_trap ? "G1" : "",
733 common_trap ? "C" : "",
734 dir_trap ? "D" : "");
735 static_branch_enable(&vgic_v3_cpuif_trap);
736 }
737
738 kvm_vgic_global_state.vctrl_base = NULL;
739 kvm_vgic_global_state.type = VGIC_V3;
740 kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
741
742 return 0;
743 }
744
vgic_v3_load(struct kvm_vcpu * vcpu)745 void vgic_v3_load(struct kvm_vcpu *vcpu)
746 {
747 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
748
749 /* If the vgic is nested, perform the full state loading */
750 if (vgic_state_is_nested(vcpu)) {
751 vgic_v3_load_nested(vcpu);
752 return;
753 }
754
755 if (likely(!is_protected_kvm_enabled()))
756 kvm_call_hyp(__vgic_v3_restore_vmcr_aprs, cpu_if);
757
758 if (has_vhe())
759 __vgic_v3_activate_traps(cpu_if);
760
761 WARN_ON(vgic_v4_load(vcpu));
762 }
763
vgic_v3_put(struct kvm_vcpu * vcpu)764 void vgic_v3_put(struct kvm_vcpu *vcpu)
765 {
766 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
767
768 if (vgic_state_is_nested(vcpu)) {
769 vgic_v3_put_nested(vcpu);
770 return;
771 }
772
773 if (likely(!is_protected_kvm_enabled()))
774 kvm_call_hyp(__vgic_v3_save_vmcr_aprs, cpu_if);
775 WARN_ON(vgic_v4_put(vcpu));
776
777 if (has_vhe())
778 __vgic_v3_deactivate_traps(cpu_if);
779 }
780