1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * drivers/net/phy/at803x.c
4 *
5 * Driver for Qualcomm Atheros AR803x PHY
6 *
7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
8 */
9
10 #include <linux/phy.h>
11 #include <linux/module.h>
12 #include <linux/string.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/ethtool_netlink.h>
16 #include <linux/bitfield.h>
17 #include <linux/regulator/of_regulator.h>
18 #include <linux/regulator/driver.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/of.h>
21 #include <linux/phylink.h>
22 #include <linux/sfp.h>
23 #include <dt-bindings/net/qca-ar803x.h>
24
25 #include "qcom.h"
26
27 #define AT803X_LED_CONTROL 0x18
28
29 #define AT803X_REG_CHIP_CONFIG 0x1f
30 #define AT803X_BT_BX_REG_SEL 0x8000
31
32 #define AT803X_MODE_CFG_MASK 0x0F
33 #define AT803X_MODE_CFG_BASET_RGMII 0x00
34 #define AT803X_MODE_CFG_BASET_SGMII 0x01
35 #define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02
36 #define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03
37 #define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04
38 #define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05
39 #define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06
40 #define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07
41 #define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B
42 #define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E
43 #define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F
44
45 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
46 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200
47
48 #define AT803X_DEBUG_REG_1F 0x1F
49 #define AT803X_DEBUG_PLL_ON BIT(2)
50 #define AT803X_DEBUG_RGMII_1V8 BIT(3)
51
52 /* AT803x supports either the XTAL input pad, an internal PLL or the
53 * DSP as clock reference for the clock output pad. The XTAL reference
54 * is only used for 25 MHz output, all other frequencies need the PLL.
55 * The DSP as a clock reference is used in synchronous ethernet
56 * applications.
57 *
58 * By default the PLL is only enabled if there is a link. Otherwise
59 * the PHY will go into low power state and disabled the PLL. You can
60 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
61 * enabled.
62 */
63 #define AT803X_MMD7_CLK25M 0x8016
64 #define AT803X_CLK_OUT_MASK GENMASK(4, 2)
65 #define AT803X_CLK_OUT_25MHZ_XTAL 0
66 #define AT803X_CLK_OUT_25MHZ_DSP 1
67 #define AT803X_CLK_OUT_50MHZ_PLL 2
68 #define AT803X_CLK_OUT_50MHZ_DSP 3
69 #define AT803X_CLK_OUT_62_5MHZ_PLL 4
70 #define AT803X_CLK_OUT_62_5MHZ_DSP 5
71 #define AT803X_CLK_OUT_125MHZ_PLL 6
72 #define AT803X_CLK_OUT_125MHZ_DSP 7
73
74 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
75 * but doesn't support choosing between XTAL/PLL and DSP.
76 */
77 #define AT8035_CLK_OUT_MASK GENMASK(4, 3)
78
79 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7)
80 #define AT803X_CLK_OUT_STRENGTH_FULL 0
81 #define AT803X_CLK_OUT_STRENGTH_HALF 1
82 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2
83
84 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b
85 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c
86 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d
87 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8)
88
89 #define ATH9331_PHY_ID 0x004dd041
90 #define ATH8030_PHY_ID 0x004dd076
91 #define ATH8031_PHY_ID 0x004dd074
92 #define ATH8032_PHY_ID 0x004dd023
93 #define ATH8035_PHY_ID 0x004dd072
94 #define AT8030_PHY_ID_MASK 0xffffffef
95
96 #define QCA9561_PHY_ID 0x004dd042
97
98 #define AT803X_PAGE_FIBER 0
99 #define AT803X_PAGE_COPPER 1
100
101 /* don't turn off internal PLL */
102 #define AT803X_KEEP_PLL_ENABLED BIT(0)
103 #define AT803X_DISABLE_SMARTEEE BIT(1)
104
105 /* disable hibernation mode */
106 #define AT803X_DISABLE_HIBERNATION_MODE BIT(2)
107
108 MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
109 MODULE_AUTHOR("Matus Ujhelyi");
110 MODULE_LICENSE("GPL");
111
112 struct at803x_priv {
113 int flags;
114 u16 clk_25m_reg;
115 u16 clk_25m_mask;
116 u8 smarteee_lpi_tw_1g;
117 u8 smarteee_lpi_tw_100m;
118 bool is_fiber;
119 bool is_1000basex;
120 struct regulator_dev *vddio_rdev;
121 struct regulator_dev *vddh_rdev;
122 };
123
124 struct at803x_context {
125 u16 bmcr;
126 u16 advertise;
127 u16 control1000;
128 u16 int_enable;
129 u16 smart_speed;
130 u16 led_control;
131 };
132
at803x_write_page(struct phy_device * phydev,int page)133 static int at803x_write_page(struct phy_device *phydev, int page)
134 {
135 int mask;
136 int set;
137
138 if (page == AT803X_PAGE_COPPER) {
139 set = AT803X_BT_BX_REG_SEL;
140 mask = 0;
141 } else {
142 set = 0;
143 mask = AT803X_BT_BX_REG_SEL;
144 }
145
146 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
147 }
148
at803x_read_page(struct phy_device * phydev)149 static int at803x_read_page(struct phy_device *phydev)
150 {
151 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
152
153 if (ccr < 0)
154 return ccr;
155
156 if (ccr & AT803X_BT_BX_REG_SEL)
157 return AT803X_PAGE_COPPER;
158
159 return AT803X_PAGE_FIBER;
160 }
161
at803x_enable_rx_delay(struct phy_device * phydev)162 static int at803x_enable_rx_delay(struct phy_device *phydev)
163 {
164 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
165 AT803X_DEBUG_RX_CLK_DLY_EN);
166 }
167
at803x_enable_tx_delay(struct phy_device * phydev)168 static int at803x_enable_tx_delay(struct phy_device *phydev)
169 {
170 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
171 AT803X_DEBUG_TX_CLK_DLY_EN);
172 }
173
at803x_disable_rx_delay(struct phy_device * phydev)174 static int at803x_disable_rx_delay(struct phy_device *phydev)
175 {
176 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
177 AT803X_DEBUG_RX_CLK_DLY_EN, 0);
178 }
179
at803x_disable_tx_delay(struct phy_device * phydev)180 static int at803x_disable_tx_delay(struct phy_device *phydev)
181 {
182 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
183 AT803X_DEBUG_TX_CLK_DLY_EN, 0);
184 }
185
186 /* save relevant PHY registers to private copy */
at803x_context_save(struct phy_device * phydev,struct at803x_context * context)187 static void at803x_context_save(struct phy_device *phydev,
188 struct at803x_context *context)
189 {
190 context->bmcr = phy_read(phydev, MII_BMCR);
191 context->advertise = phy_read(phydev, MII_ADVERTISE);
192 context->control1000 = phy_read(phydev, MII_CTRL1000);
193 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
194 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
195 context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
196 }
197
198 /* restore relevant PHY registers from private copy */
at803x_context_restore(struct phy_device * phydev,const struct at803x_context * context)199 static void at803x_context_restore(struct phy_device *phydev,
200 const struct at803x_context *context)
201 {
202 phy_write(phydev, MII_BMCR, context->bmcr);
203 phy_write(phydev, MII_ADVERTISE, context->advertise);
204 phy_write(phydev, MII_CTRL1000, context->control1000);
205 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
206 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
207 phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
208 }
209
at803x_suspend(struct phy_device * phydev)210 static int at803x_suspend(struct phy_device *phydev)
211 {
212 int value;
213 int wol_enabled;
214
215 value = phy_read(phydev, AT803X_INTR_ENABLE);
216 wol_enabled = value & AT803X_INTR_ENABLE_WOL;
217
218 if (wol_enabled)
219 value = BMCR_ISOLATE;
220 else
221 value = BMCR_PDOWN;
222
223 phy_modify(phydev, MII_BMCR, 0, value);
224
225 return 0;
226 }
227
at803x_resume(struct phy_device * phydev)228 static int at803x_resume(struct phy_device *phydev)
229 {
230 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
231 }
232
at803x_parse_dt(struct phy_device * phydev)233 static int at803x_parse_dt(struct phy_device *phydev)
234 {
235 struct device_node *node = phydev->mdio.dev.of_node;
236 struct at803x_priv *priv = phydev->priv;
237 u32 freq, strength, tw;
238 unsigned int sel;
239 int ret;
240
241 if (!IS_ENABLED(CONFIG_OF_MDIO))
242 return 0;
243
244 if (of_property_read_bool(node, "qca,disable-smarteee"))
245 priv->flags |= AT803X_DISABLE_SMARTEEE;
246
247 if (of_property_read_bool(node, "qca,disable-hibernation-mode"))
248 priv->flags |= AT803X_DISABLE_HIBERNATION_MODE;
249
250 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
251 if (!tw || tw > 255) {
252 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
253 return -EINVAL;
254 }
255 priv->smarteee_lpi_tw_1g = tw;
256 }
257
258 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
259 if (!tw || tw > 255) {
260 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
261 return -EINVAL;
262 }
263 priv->smarteee_lpi_tw_100m = tw;
264 }
265
266 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
267 if (!ret) {
268 switch (freq) {
269 case 25000000:
270 sel = AT803X_CLK_OUT_25MHZ_XTAL;
271 break;
272 case 50000000:
273 sel = AT803X_CLK_OUT_50MHZ_PLL;
274 break;
275 case 62500000:
276 sel = AT803X_CLK_OUT_62_5MHZ_PLL;
277 break;
278 case 125000000:
279 sel = AT803X_CLK_OUT_125MHZ_PLL;
280 break;
281 default:
282 phydev_err(phydev, "invalid qca,clk-out-frequency\n");
283 return -EINVAL;
284 }
285
286 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
287 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
288 }
289
290 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
291 if (!ret) {
292 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
293 switch (strength) {
294 case AR803X_STRENGTH_FULL:
295 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
296 break;
297 case AR803X_STRENGTH_HALF:
298 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
299 break;
300 case AR803X_STRENGTH_QUARTER:
301 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
302 break;
303 default:
304 phydev_err(phydev, "invalid qca,clk-out-strength\n");
305 return -EINVAL;
306 }
307 }
308
309 return 0;
310 }
311
at803x_probe(struct phy_device * phydev)312 static int at803x_probe(struct phy_device *phydev)
313 {
314 struct device *dev = &phydev->mdio.dev;
315 struct at803x_priv *priv;
316 int ret;
317
318 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
319 if (!priv)
320 return -ENOMEM;
321
322 phydev->priv = priv;
323
324 ret = at803x_parse_dt(phydev);
325 if (ret)
326 return ret;
327
328 return 0;
329 }
330
at803x_get_features(struct phy_device * phydev)331 static int at803x_get_features(struct phy_device *phydev)
332 {
333 struct at803x_priv *priv = phydev->priv;
334 int err;
335
336 err = genphy_read_abilities(phydev);
337 if (err)
338 return err;
339
340 if (phydev->drv->phy_id != ATH8031_PHY_ID)
341 return 0;
342
343 /* AR8031/AR8033 have different status registers
344 * for copper and fiber operation. However, the
345 * extended status register is the same for both
346 * operation modes.
347 *
348 * As a result of that, ESTATUS_1000_XFULL is set
349 * to 1 even when operating in copper TP mode.
350 *
351 * Remove this mode from the supported link modes
352 * when not operating in 1000BaseX mode.
353 */
354 if (!priv->is_1000basex)
355 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
356 phydev->supported);
357
358 return 0;
359 }
360
at803x_smarteee_config(struct phy_device * phydev)361 static int at803x_smarteee_config(struct phy_device *phydev)
362 {
363 struct at803x_priv *priv = phydev->priv;
364 u16 mask = 0, val = 0;
365 int ret;
366
367 if (priv->flags & AT803X_DISABLE_SMARTEEE)
368 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
369 AT803X_MMD3_SMARTEEE_CTL3,
370 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
371
372 if (priv->smarteee_lpi_tw_1g) {
373 mask |= 0xff00;
374 val |= priv->smarteee_lpi_tw_1g << 8;
375 }
376 if (priv->smarteee_lpi_tw_100m) {
377 mask |= 0x00ff;
378 val |= priv->smarteee_lpi_tw_100m;
379 }
380 if (!mask)
381 return 0;
382
383 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
384 mask, val);
385 if (ret)
386 return ret;
387
388 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
389 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
390 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
391 }
392
at803x_clk_out_config(struct phy_device * phydev)393 static int at803x_clk_out_config(struct phy_device *phydev)
394 {
395 struct at803x_priv *priv = phydev->priv;
396
397 if (!priv->clk_25m_mask)
398 return 0;
399
400 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
401 priv->clk_25m_mask, priv->clk_25m_reg);
402 }
403
at8031_pll_config(struct phy_device * phydev)404 static int at8031_pll_config(struct phy_device *phydev)
405 {
406 struct at803x_priv *priv = phydev->priv;
407
408 /* The default after hardware reset is PLL OFF. After a soft reset, the
409 * values are retained.
410 */
411 if (priv->flags & AT803X_KEEP_PLL_ENABLED)
412 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
413 0, AT803X_DEBUG_PLL_ON);
414 else
415 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
416 AT803X_DEBUG_PLL_ON, 0);
417 }
418
at803x_hibernation_mode_config(struct phy_device * phydev)419 static int at803x_hibernation_mode_config(struct phy_device *phydev)
420 {
421 struct at803x_priv *priv = phydev->priv;
422
423 /* The default after hardware reset is hibernation mode enabled. After
424 * software reset, the value is retained.
425 */
426 if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE) &&
427 !(phydev->dev_flags & PHY_F_RXC_ALWAYS_ON))
428 return 0;
429
430 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
431 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0);
432 }
433
at803x_config_init(struct phy_device * phydev)434 static int at803x_config_init(struct phy_device *phydev)
435 {
436 int ret;
437
438 /* The RX and TX delay default is:
439 * after HW reset: RX delay enabled and TX delay disabled
440 * after SW reset: RX delay enabled, while TX delay retains the
441 * value before reset.
442 */
443 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
444 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
445 ret = at803x_enable_rx_delay(phydev);
446 else
447 ret = at803x_disable_rx_delay(phydev);
448 if (ret < 0)
449 return ret;
450
451 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
452 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
453 ret = at803x_enable_tx_delay(phydev);
454 else
455 ret = at803x_disable_tx_delay(phydev);
456 if (ret < 0)
457 return ret;
458
459 ret = at803x_smarteee_config(phydev);
460 if (ret < 0)
461 return ret;
462
463 ret = at803x_clk_out_config(phydev);
464 if (ret < 0)
465 return ret;
466
467 ret = at803x_hibernation_mode_config(phydev);
468 if (ret < 0)
469 return ret;
470
471 /* Ar803x extended next page bit is enabled by default. Cisco
472 * multigig switches read this bit and attempt to negotiate 10Gbps
473 * rates even if the next page bit is disabled. This is incorrect
474 * behaviour but we still need to accommodate it. XNP is only needed
475 * for 10Gbps support, so disable XNP.
476 */
477 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
478 }
479
at803x_link_change_notify(struct phy_device * phydev)480 static void at803x_link_change_notify(struct phy_device *phydev)
481 {
482 /*
483 * Conduct a hardware reset for AT8030 every time a link loss is
484 * signalled. This is necessary to circumvent a hardware bug that
485 * occurs when the cable is unplugged while TX packets are pending
486 * in the FIFO. In such cases, the FIFO enters an error mode it
487 * cannot recover from by software.
488 */
489 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
490 struct at803x_context context;
491
492 at803x_context_save(phydev, &context);
493
494 phy_device_reset(phydev, 1);
495 usleep_range(1000, 2000);
496 phy_device_reset(phydev, 0);
497 usleep_range(1000, 2000);
498
499 at803x_context_restore(phydev, &context);
500
501 phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
502 }
503 }
504
at803x_config_aneg(struct phy_device * phydev)505 static int at803x_config_aneg(struct phy_device *phydev)
506 {
507 struct at803x_priv *priv = phydev->priv;
508 int ret;
509
510 ret = at803x_prepare_config_aneg(phydev);
511 if (ret)
512 return ret;
513
514 if (priv->is_1000basex)
515 return genphy_c37_config_aneg(phydev);
516
517 return genphy_config_aneg(phydev);
518 }
519
at803x_cable_test_result_trans(u16 status)520 static int at803x_cable_test_result_trans(u16 status)
521 {
522 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
523 case AT803X_CDT_STATUS_STAT_NORMAL:
524 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
525 case AT803X_CDT_STATUS_STAT_SHORT:
526 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
527 case AT803X_CDT_STATUS_STAT_OPEN:
528 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
529 case AT803X_CDT_STATUS_STAT_FAIL:
530 default:
531 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
532 }
533 }
534
at803x_cdt_test_failed(u16 status)535 static bool at803x_cdt_test_failed(u16 status)
536 {
537 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
538 AT803X_CDT_STATUS_STAT_FAIL;
539 }
540
at803x_cdt_fault_length_valid(u16 status)541 static bool at803x_cdt_fault_length_valid(u16 status)
542 {
543 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
544 case AT803X_CDT_STATUS_STAT_OPEN:
545 case AT803X_CDT_STATUS_STAT_SHORT:
546 return true;
547 }
548 return false;
549 }
550
at803x_cable_test_one_pair(struct phy_device * phydev,int pair)551 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
552 {
553 static const int ethtool_pair[] = {
554 ETHTOOL_A_CABLE_PAIR_A,
555 ETHTOOL_A_CABLE_PAIR_B,
556 ETHTOOL_A_CABLE_PAIR_C,
557 ETHTOOL_A_CABLE_PAIR_D,
558 };
559 int ret, val;
560
561 val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
562 AT803X_CDT_ENABLE_TEST;
563 ret = at803x_cdt_start(phydev, val);
564 if (ret)
565 return ret;
566
567 ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST);
568 if (ret)
569 return ret;
570
571 val = phy_read(phydev, AT803X_CDT_STATUS);
572 if (val < 0)
573 return val;
574
575 if (at803x_cdt_test_failed(val))
576 return 0;
577
578 ethnl_cable_test_result(phydev, ethtool_pair[pair],
579 at803x_cable_test_result_trans(val));
580
581 if (at803x_cdt_fault_length_valid(val)) {
582 val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val);
583 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
584 at803x_cdt_fault_length(val));
585 }
586
587 return 1;
588 }
589
at803x_cable_test_get_status(struct phy_device * phydev,bool * finished,unsigned long pair_mask)590 static int at803x_cable_test_get_status(struct phy_device *phydev,
591 bool *finished, unsigned long pair_mask)
592 {
593 int retries = 20;
594 int pair, ret;
595
596 *finished = false;
597
598 /* According to the datasheet the CDT can be performed when
599 * there is no link partner or when the link partner is
600 * auto-negotiating. Starting the test will restart the AN
601 * automatically. It seems that doing this repeatedly we will
602 * get a slot where our link partner won't disturb our
603 * measurement.
604 */
605 while (pair_mask && retries--) {
606 for_each_set_bit(pair, &pair_mask, 4) {
607 ret = at803x_cable_test_one_pair(phydev, pair);
608 if (ret < 0)
609 return ret;
610 if (ret)
611 clear_bit(pair, &pair_mask);
612 }
613 if (pair_mask)
614 msleep(250);
615 }
616
617 *finished = true;
618
619 return 0;
620 }
621
at803x_cable_test_autoneg(struct phy_device * phydev)622 static void at803x_cable_test_autoneg(struct phy_device *phydev)
623 {
624 /* Enable auto-negotiation, but advertise no capabilities, no link
625 * will be established. A restart of the auto-negotiation is not
626 * required, because the cable test will automatically break the link.
627 */
628 phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
629 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
630 }
631
at803x_cable_test_start(struct phy_device * phydev)632 static int at803x_cable_test_start(struct phy_device *phydev)
633 {
634 at803x_cable_test_autoneg(phydev);
635 /* we do all the (time consuming) work later */
636 return 0;
637 }
638
at8031_rgmii_reg_set_voltage_sel(struct regulator_dev * rdev,unsigned int selector)639 static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
640 unsigned int selector)
641 {
642 struct phy_device *phydev = rdev_get_drvdata(rdev);
643
644 if (selector)
645 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
646 0, AT803X_DEBUG_RGMII_1V8);
647 else
648 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
649 AT803X_DEBUG_RGMII_1V8, 0);
650 }
651
at8031_rgmii_reg_get_voltage_sel(struct regulator_dev * rdev)652 static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
653 {
654 struct phy_device *phydev = rdev_get_drvdata(rdev);
655 int val;
656
657 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
658 if (val < 0)
659 return val;
660
661 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
662 }
663
664 static const struct regulator_ops vddio_regulator_ops = {
665 .list_voltage = regulator_list_voltage_table,
666 .set_voltage_sel = at8031_rgmii_reg_set_voltage_sel,
667 .get_voltage_sel = at8031_rgmii_reg_get_voltage_sel,
668 };
669
670 static const unsigned int vddio_voltage_table[] = {
671 1500000,
672 1800000,
673 };
674
675 static const struct regulator_desc vddio_desc = {
676 .name = "vddio",
677 .of_match = of_match_ptr("vddio-regulator"),
678 .n_voltages = ARRAY_SIZE(vddio_voltage_table),
679 .volt_table = vddio_voltage_table,
680 .ops = &vddio_regulator_ops,
681 .type = REGULATOR_VOLTAGE,
682 .owner = THIS_MODULE,
683 };
684
685 static const struct regulator_ops vddh_regulator_ops = {
686 };
687
688 static const struct regulator_desc vddh_desc = {
689 .name = "vddh",
690 .of_match = of_match_ptr("vddh-regulator"),
691 .n_voltages = 1,
692 .fixed_uV = 2500000,
693 .ops = &vddh_regulator_ops,
694 .type = REGULATOR_VOLTAGE,
695 .owner = THIS_MODULE,
696 };
697
at8031_register_regulators(struct phy_device * phydev)698 static int at8031_register_regulators(struct phy_device *phydev)
699 {
700 struct at803x_priv *priv = phydev->priv;
701 struct device *dev = &phydev->mdio.dev;
702 struct regulator_config config = { };
703
704 config.dev = dev;
705 config.driver_data = phydev;
706
707 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
708 if (IS_ERR(priv->vddio_rdev)) {
709 phydev_err(phydev, "failed to register VDDIO regulator\n");
710 return PTR_ERR(priv->vddio_rdev);
711 }
712
713 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
714 if (IS_ERR(priv->vddh_rdev)) {
715 phydev_err(phydev, "failed to register VDDH regulator\n");
716 return PTR_ERR(priv->vddh_rdev);
717 }
718
719 return 0;
720 }
721
at8031_sfp_insert(void * upstream,const struct sfp_eeprom_id * id)722 static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
723 {
724 struct phy_device *phydev = upstream;
725 __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
726 __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
727 DECLARE_PHY_INTERFACE_MASK(interfaces);
728 phy_interface_t iface;
729
730 linkmode_zero(phy_support);
731 phylink_set(phy_support, 1000baseX_Full);
732 phylink_set(phy_support, 1000baseT_Full);
733 phylink_set(phy_support, Autoneg);
734 phylink_set(phy_support, Pause);
735 phylink_set(phy_support, Asym_Pause);
736
737 linkmode_zero(sfp_support);
738 sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces);
739 /* Some modules support 10G modes as well as others we support.
740 * Mask out non-supported modes so the correct interface is picked.
741 */
742 linkmode_and(sfp_support, phy_support, sfp_support);
743
744 if (linkmode_empty(sfp_support)) {
745 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
746 return -EINVAL;
747 }
748
749 iface = sfp_select_interface(phydev->sfp_bus, sfp_support);
750
751 /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
752 * interface for use with SFP modules.
753 * However, some copper modules detected as having a preferred SGMII
754 * interface do default to and function in 1000Base-X mode, so just
755 * print a warning and allow such modules, as they may have some chance
756 * of working.
757 */
758 if (iface == PHY_INTERFACE_MODE_SGMII)
759 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
760 else if (iface != PHY_INTERFACE_MODE_1000BASEX)
761 return -EINVAL;
762
763 return 0;
764 }
765
766 static const struct sfp_upstream_ops at8031_sfp_ops = {
767 .attach = phy_sfp_attach,
768 .detach = phy_sfp_detach,
769 .module_insert = at8031_sfp_insert,
770 .connect_phy = phy_sfp_connect_phy,
771 .disconnect_phy = phy_sfp_disconnect_phy,
772 };
773
at8031_parse_dt(struct phy_device * phydev)774 static int at8031_parse_dt(struct phy_device *phydev)
775 {
776 struct device_node *node = phydev->mdio.dev.of_node;
777 struct at803x_priv *priv = phydev->priv;
778 int ret;
779
780 if (of_property_read_bool(node, "qca,keep-pll-enabled"))
781 priv->flags |= AT803X_KEEP_PLL_ENABLED;
782
783 ret = at8031_register_regulators(phydev);
784 if (ret < 0)
785 return ret;
786
787 ret = devm_regulator_get_enable_optional(&phydev->mdio.dev,
788 "vddio");
789 if (ret) {
790 phydev_err(phydev, "failed to get VDDIO regulator\n");
791 return ret;
792 }
793
794 /* Only AR8031/8033 support 1000Base-X for SFP modules */
795 return phy_sfp_probe(phydev, &at8031_sfp_ops);
796 }
797
at8031_probe(struct phy_device * phydev)798 static int at8031_probe(struct phy_device *phydev)
799 {
800 struct at803x_priv *priv;
801 int mode_cfg;
802 int ccr;
803 int ret;
804
805 ret = at803x_probe(phydev);
806 if (ret)
807 return ret;
808
809 priv = phydev->priv;
810
811 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
812 * options.
813 */
814 ret = at8031_parse_dt(phydev);
815 if (ret)
816 return ret;
817
818 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
819 if (ccr < 0)
820 return ccr;
821 mode_cfg = ccr & AT803X_MODE_CFG_MASK;
822
823 switch (mode_cfg) {
824 case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
825 case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
826 priv->is_1000basex = true;
827 fallthrough;
828 case AT803X_MODE_CFG_FX100_RGMII_50OHM:
829 case AT803X_MODE_CFG_FX100_RGMII_75OHM:
830 priv->is_fiber = true;
831 break;
832 }
833
834 /* Disable WoL in 1588 register which is enabled
835 * by default
836 */
837 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
838 AT803X_PHY_MMD3_WOL_CTRL,
839 AT803X_WOL_EN, 0);
840 }
841
at8031_config_init(struct phy_device * phydev)842 static int at8031_config_init(struct phy_device *phydev)
843 {
844 struct at803x_priv *priv = phydev->priv;
845 int ret;
846
847 /* Some bootloaders leave the fiber page selected.
848 * Switch to the appropriate page (fiber or copper), as otherwise we
849 * read the PHY capabilities from the wrong page.
850 */
851 phy_lock_mdio_bus(phydev);
852 ret = at803x_write_page(phydev,
853 priv->is_fiber ? AT803X_PAGE_FIBER :
854 AT803X_PAGE_COPPER);
855 phy_unlock_mdio_bus(phydev);
856 if (ret)
857 return ret;
858
859 ret = at8031_pll_config(phydev);
860 if (ret < 0)
861 return ret;
862
863 return at803x_config_init(phydev);
864 }
865
at8031_config_intr(struct phy_device * phydev)866 static int at8031_config_intr(struct phy_device *phydev)
867 {
868 struct at803x_priv *priv = phydev->priv;
869 int err, value = 0;
870
871 if (phydev->interrupts == PHY_INTERRUPT_ENABLED &&
872 priv->is_fiber) {
873 /* Clear any pending interrupts */
874 err = at803x_ack_interrupt(phydev);
875 if (err)
876 return err;
877
878 value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
879 value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
880
881 err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value);
882 if (err)
883 return err;
884 }
885
886 return at803x_config_intr(phydev);
887 }
888
889 /* AR8031 and AR8033 share the same read status logic */
at8031_read_status(struct phy_device * phydev)890 static int at8031_read_status(struct phy_device *phydev)
891 {
892 struct at803x_priv *priv = phydev->priv;
893 bool changed;
894
895 if (priv->is_1000basex)
896 return genphy_c37_read_status(phydev, &changed);
897
898 return at803x_read_status(phydev);
899 }
900
901 /* AR8031 and AR8035 share the same cable test get status reg */
at8031_cable_test_get_status(struct phy_device * phydev,bool * finished)902 static int at8031_cable_test_get_status(struct phy_device *phydev,
903 bool *finished)
904 {
905 return at803x_cable_test_get_status(phydev, finished, 0xf);
906 }
907
908 /* AR8031 and AR8035 share the same cable test start logic */
at8031_cable_test_start(struct phy_device * phydev)909 static int at8031_cable_test_start(struct phy_device *phydev)
910 {
911 at803x_cable_test_autoneg(phydev);
912 phy_write(phydev, MII_CTRL1000, 0);
913 /* we do all the (time consuming) work later */
914 return 0;
915 }
916
917 /* AR8032, AR9331 and QCA9561 share the same cable test get status reg */
at8032_cable_test_get_status(struct phy_device * phydev,bool * finished)918 static int at8032_cable_test_get_status(struct phy_device *phydev,
919 bool *finished)
920 {
921 return at803x_cable_test_get_status(phydev, finished, 0x3);
922 }
923
at8035_parse_dt(struct phy_device * phydev)924 static int at8035_parse_dt(struct phy_device *phydev)
925 {
926 struct at803x_priv *priv = phydev->priv;
927
928 /* Mask is set by the generic at803x_parse_dt
929 * if property is set. Assume property is set
930 * with the mask not zero.
931 */
932 if (priv->clk_25m_mask) {
933 /* Fixup for the AR8030/AR8035. This chip has another mask and
934 * doesn't support the DSP reference. Eg. the lowest bit of the
935 * mask. The upper two bits select the same frequencies. Mask
936 * the lowest bit here.
937 *
938 * Warning:
939 * There was no datasheet for the AR8030 available so this is
940 * just a guess. But the AR8035 is listed as pin compatible
941 * to the AR8030 so there might be a good chance it works on
942 * the AR8030 too.
943 */
944 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
945 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
946 }
947
948 return 0;
949 }
950
951 /* AR8030 and AR8035 shared the same special mask for clk_25m */
at8035_probe(struct phy_device * phydev)952 static int at8035_probe(struct phy_device *phydev)
953 {
954 int ret;
955
956 ret = at803x_probe(phydev);
957 if (ret)
958 return ret;
959
960 return at8035_parse_dt(phydev);
961 }
962
963 static struct phy_driver at803x_driver[] = {
964 {
965 /* Qualcomm Atheros AR8035 */
966 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
967 .name = "Qualcomm Atheros AR8035",
968 .flags = PHY_POLL_CABLE_TEST,
969 .probe = at8035_probe,
970 .config_aneg = at803x_config_aneg,
971 .config_init = at803x_config_init,
972 .soft_reset = genphy_soft_reset,
973 .set_wol = at803x_set_wol,
974 .get_wol = at803x_get_wol,
975 .suspend = at803x_suspend,
976 .resume = at803x_resume,
977 /* PHY_GBIT_FEATURES */
978 .read_status = at803x_read_status,
979 .config_intr = at803x_config_intr,
980 .handle_interrupt = at803x_handle_interrupt,
981 .get_tunable = at803x_get_tunable,
982 .set_tunable = at803x_set_tunable,
983 .cable_test_start = at8031_cable_test_start,
984 .cable_test_get_status = at8031_cable_test_get_status,
985 }, {
986 /* Qualcomm Atheros AR8030 */
987 .phy_id = ATH8030_PHY_ID,
988 .name = "Qualcomm Atheros AR8030",
989 .phy_id_mask = AT8030_PHY_ID_MASK,
990 .probe = at8035_probe,
991 .config_init = at803x_config_init,
992 .link_change_notify = at803x_link_change_notify,
993 .set_wol = at803x_set_wol,
994 .get_wol = at803x_get_wol,
995 .suspend = at803x_suspend,
996 .resume = at803x_resume,
997 /* PHY_BASIC_FEATURES */
998 .config_intr = at803x_config_intr,
999 .handle_interrupt = at803x_handle_interrupt,
1000 }, {
1001 /* Qualcomm Atheros AR8031/AR8033 */
1002 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
1003 .name = "Qualcomm Atheros AR8031/AR8033",
1004 .flags = PHY_POLL_CABLE_TEST,
1005 .probe = at8031_probe,
1006 .config_init = at8031_config_init,
1007 .config_aneg = at803x_config_aneg,
1008 .soft_reset = genphy_soft_reset,
1009 .set_wol = at8031_set_wol,
1010 .get_wol = at803x_get_wol,
1011 .suspend = at803x_suspend,
1012 .resume = at803x_resume,
1013 .read_page = at803x_read_page,
1014 .write_page = at803x_write_page,
1015 .get_features = at803x_get_features,
1016 .read_status = at8031_read_status,
1017 .config_intr = at8031_config_intr,
1018 .handle_interrupt = at803x_handle_interrupt,
1019 .get_tunable = at803x_get_tunable,
1020 .set_tunable = at803x_set_tunable,
1021 .cable_test_start = at8031_cable_test_start,
1022 .cable_test_get_status = at8031_cable_test_get_status,
1023 }, {
1024 /* Qualcomm Atheros AR8032 */
1025 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
1026 .name = "Qualcomm Atheros AR8032",
1027 .probe = at803x_probe,
1028 .flags = PHY_POLL_CABLE_TEST,
1029 .config_init = at803x_config_init,
1030 .link_change_notify = at803x_link_change_notify,
1031 .suspend = at803x_suspend,
1032 .resume = at803x_resume,
1033 /* PHY_BASIC_FEATURES */
1034 .config_intr = at803x_config_intr,
1035 .handle_interrupt = at803x_handle_interrupt,
1036 .cable_test_start = at803x_cable_test_start,
1037 .cable_test_get_status = at8032_cable_test_get_status,
1038 }, {
1039 /* ATHEROS AR9331 */
1040 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
1041 .name = "Qualcomm Atheros AR9331 built-in PHY",
1042 .probe = at803x_probe,
1043 .suspend = at803x_suspend,
1044 .resume = at803x_resume,
1045 .flags = PHY_POLL_CABLE_TEST,
1046 /* PHY_BASIC_FEATURES */
1047 .config_intr = at803x_config_intr,
1048 .handle_interrupt = at803x_handle_interrupt,
1049 .cable_test_start = at803x_cable_test_start,
1050 .cable_test_get_status = at8032_cable_test_get_status,
1051 .read_status = at803x_read_status,
1052 .soft_reset = genphy_soft_reset,
1053 .config_aneg = at803x_config_aneg,
1054 }, {
1055 /* Qualcomm Atheros QCA9561 */
1056 PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
1057 .name = "Qualcomm Atheros QCA9561 built-in PHY",
1058 .probe = at803x_probe,
1059 .suspend = at803x_suspend,
1060 .resume = at803x_resume,
1061 .flags = PHY_POLL_CABLE_TEST,
1062 /* PHY_BASIC_FEATURES */
1063 .config_intr = at803x_config_intr,
1064 .handle_interrupt = at803x_handle_interrupt,
1065 .cable_test_start = at803x_cable_test_start,
1066 .cable_test_get_status = at8032_cable_test_get_status,
1067 .read_status = at803x_read_status,
1068 .soft_reset = genphy_soft_reset,
1069 .config_aneg = at803x_config_aneg,
1070 }, };
1071
1072 module_phy_driver(at803x_driver);
1073
1074 static const struct mdio_device_id __maybe_unused atheros_tbl[] = {
1075 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
1076 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
1077 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
1078 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
1079 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
1080 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
1081 { }
1082 };
1083
1084 MODULE_DEVICE_TABLE(mdio, atheros_tbl);
1085