1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/arm-smccc.h> 15 #include <linux/bitmap.h> 16 #include <linux/types.h> 17 #include <linux/jump_label.h> 18 #include <linux/kvm_types.h> 19 #include <linux/maple_tree.h> 20 #include <linux/percpu.h> 21 #include <linux/psci.h> 22 #include <asm/arch_gicv3.h> 23 #include <asm/barrier.h> 24 #include <asm/cpufeature.h> 25 #include <asm/cputype.h> 26 #include <asm/daifflags.h> 27 #include <asm/fpsimd.h> 28 #include <asm/kvm.h> 29 #include <asm/kvm_asm.h> 30 #include <asm/vncr_mapping.h> 31 32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 33 34 #define KVM_HALT_POLL_NS_DEFAULT 500000 35 36 #include <kvm/arm_vgic.h> 37 #include <kvm/arm_arch_timer.h> 38 #include <kvm/arm_pmu.h> 39 40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 41 42 #define KVM_VCPU_MAX_FEATURES 9 43 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1) 44 45 #define KVM_REQ_SLEEP \ 46 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 47 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 48 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 49 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 50 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 51 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5) 52 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6) 53 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7) 54 #define KVM_REQ_NESTED_S2_UNMAP KVM_ARCH_REQ(8) 55 #define KVM_REQ_GUEST_HYP_IRQ_PENDING KVM_ARCH_REQ(9) 56 #define KVM_REQ_MAP_L1_VNCR_EL2 KVM_ARCH_REQ(10) 57 #define KVM_REQ_VGIC_PROCESS_UPDATE KVM_ARCH_REQ(11) 58 59 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 60 KVM_DIRTY_LOG_INITIALLY_SET) 61 62 #define KVM_HAVE_MMU_RWLOCK 63 64 /* 65 * Mode of operation configurable with kvm-arm.mode early param. 66 * See Documentation/admin-guide/kernel-parameters.txt for more information. 67 */ 68 enum kvm_mode { 69 KVM_MODE_DEFAULT, 70 KVM_MODE_PROTECTED, 71 KVM_MODE_NV, 72 KVM_MODE_NONE, 73 }; 74 #ifdef CONFIG_KVM 75 enum kvm_mode kvm_get_mode(void); 76 #else 77 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; }; 78 #endif 79 80 extern unsigned int __ro_after_init kvm_sve_max_vl; 81 extern unsigned int __ro_after_init kvm_host_sve_max_vl; 82 int __init kvm_arm_init_sve(void); 83 84 u32 __attribute_const__ kvm_target_cpu(void); 85 void kvm_reset_vcpu(struct kvm_vcpu *vcpu); 86 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 87 88 struct kvm_hyp_memcache { 89 phys_addr_t head; 90 unsigned long nr_pages; 91 struct pkvm_mapping *mapping; /* only used from EL1 */ 92 93 #define HYP_MEMCACHE_ACCOUNT_STAGE2 BIT(1) 94 unsigned long flags; 95 }; 96 97 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc, 98 phys_addr_t *p, 99 phys_addr_t (*to_pa)(void *virt)) 100 { 101 *p = mc->head; 102 mc->head = to_pa(p); 103 mc->nr_pages++; 104 } 105 106 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc, 107 void *(*to_va)(phys_addr_t phys)) 108 { 109 phys_addr_t *p = to_va(mc->head & PAGE_MASK); 110 111 if (!mc->nr_pages) 112 return NULL; 113 114 mc->head = *p; 115 mc->nr_pages--; 116 117 return p; 118 } 119 120 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc, 121 unsigned long min_pages, 122 void *(*alloc_fn)(void *arg), 123 phys_addr_t (*to_pa)(void *virt), 124 void *arg) 125 { 126 while (mc->nr_pages < min_pages) { 127 phys_addr_t *p = alloc_fn(arg); 128 129 if (!p) 130 return -ENOMEM; 131 push_hyp_memcache(mc, p, to_pa); 132 } 133 134 return 0; 135 } 136 137 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc, 138 void (*free_fn)(void *virt, void *arg), 139 void *(*to_va)(phys_addr_t phys), 140 void *arg) 141 { 142 while (mc->nr_pages) 143 free_fn(pop_hyp_memcache(mc, to_va), arg); 144 } 145 146 void free_hyp_memcache(struct kvm_hyp_memcache *mc); 147 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages); 148 149 struct kvm_vmid { 150 atomic64_t id; 151 }; 152 153 struct kvm_s2_mmu { 154 struct kvm_vmid vmid; 155 156 /* 157 * stage2 entry level table 158 * 159 * Two kvm_s2_mmu structures in the same VM can point to the same 160 * pgd here. This happens when running a guest using a 161 * translation regime that isn't affected by its own stage-2 162 * translation, such as a non-VHE hypervisor running at vEL2, or 163 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the 164 * canonical stage-2 page tables. 165 */ 166 phys_addr_t pgd_phys; 167 struct kvm_pgtable *pgt; 168 169 /* 170 * VTCR value used on the host. For a non-NV guest (or a NV 171 * guest that runs in a context where its own S2 doesn't 172 * apply), its T0SZ value reflects that of the IPA size. 173 * 174 * For a shadow S2 MMU, T0SZ reflects the PARange exposed to 175 * the guest. 176 */ 177 u64 vtcr; 178 179 /* The last vcpu id that ran on each physical CPU */ 180 int __percpu *last_vcpu_ran; 181 182 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0 183 /* 184 * Memory cache used to split 185 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It 186 * is used to allocate stage2 page tables while splitting huge 187 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 188 * influences both the capacity of the split page cache, and 189 * how often KVM reschedules. Be wary of raising CHUNK_SIZE 190 * too high. 191 * 192 * Protected by kvm->slots_lock. 193 */ 194 struct kvm_mmu_memory_cache split_page_cache; 195 uint64_t split_page_chunk_size; 196 197 struct kvm_arch *arch; 198 199 /* 200 * For a shadow stage-2 MMU, the virtual vttbr used by the 201 * host to parse the guest S2. 202 * This either contains: 203 * - the virtual VTTBR programmed by the guest hypervisor with 204 * CnP cleared 205 * - The value 1 (VMID=0, BADDR=0, CnP=1) if invalid 206 * 207 * We also cache the full VTCR which gets used for TLB invalidation, 208 * taking the ARM ARM's "Any of the bits in VTCR_EL2 are permitted 209 * to be cached in a TLB" to the letter. 210 */ 211 u64 tlb_vttbr; 212 u64 tlb_vtcr; 213 214 /* 215 * true when this represents a nested context where virtual 216 * HCR_EL2.VM == 1 217 */ 218 bool nested_stage2_enabled; 219 220 /* 221 * true when this MMU needs to be unmapped before being used for a new 222 * purpose. 223 */ 224 bool pending_unmap; 225 226 /* 227 * 0: Nobody is currently using this, check vttbr for validity 228 * >0: Somebody is actively using this. 229 */ 230 atomic_t refcnt; 231 }; 232 233 struct kvm_arch_memory_slot { 234 }; 235 236 /** 237 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests 238 * 239 * @std_bmap: Bitmap of standard secure service calls 240 * @std_hyp_bmap: Bitmap of standard hypervisor service calls 241 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls 242 */ 243 struct kvm_smccc_features { 244 unsigned long std_bmap; 245 unsigned long std_hyp_bmap; 246 unsigned long vendor_hyp_bmap; /* Function numbers 0-63 */ 247 unsigned long vendor_hyp_bmap_2; /* Function numbers 64-127 */ 248 }; 249 250 typedef unsigned int pkvm_handle_t; 251 252 struct kvm_protected_vm { 253 pkvm_handle_t handle; 254 struct kvm_hyp_memcache teardown_mc; 255 struct kvm_hyp_memcache stage2_teardown_mc; 256 bool is_protected; 257 bool is_created; 258 }; 259 260 struct kvm_mpidr_data { 261 u64 mpidr_mask; 262 DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx); 263 }; 264 265 static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr) 266 { 267 unsigned long index = 0, mask = data->mpidr_mask; 268 unsigned long aff = mpidr & MPIDR_HWID_BITMASK; 269 270 bitmap_gather(&index, &aff, &mask, fls(mask)); 271 272 return index; 273 } 274 275 struct kvm_sysreg_masks; 276 277 enum fgt_group_id { 278 __NO_FGT_GROUP__, 279 HFGRTR_GROUP, 280 HFGWTR_GROUP = HFGRTR_GROUP, 281 HDFGRTR_GROUP, 282 HDFGWTR_GROUP = HDFGRTR_GROUP, 283 HFGITR_GROUP, 284 HAFGRTR_GROUP, 285 HFGRTR2_GROUP, 286 HFGWTR2_GROUP = HFGRTR2_GROUP, 287 HDFGRTR2_GROUP, 288 HDFGWTR2_GROUP = HDFGRTR2_GROUP, 289 HFGITR2_GROUP, 290 291 /* Must be last */ 292 __NR_FGT_GROUP_IDS__ 293 }; 294 295 struct kvm_arch { 296 struct kvm_s2_mmu mmu; 297 298 /* 299 * Fine-Grained UNDEF, mimicking the FGT layout defined by the 300 * architecture. We track them globally, as we present the 301 * same feature-set to all vcpus. 302 * 303 * Index 0 is currently spare. 304 */ 305 u64 fgu[__NR_FGT_GROUP_IDS__]; 306 307 /* 308 * Stage 2 paging state for VMs with nested S2 using a virtual 309 * VMID. 310 */ 311 struct kvm_s2_mmu *nested_mmus; 312 size_t nested_mmus_size; 313 int nested_mmus_next; 314 315 /* Interrupt controller */ 316 struct vgic_dist vgic; 317 318 /* Timers */ 319 struct arch_timer_vm_data timer_data; 320 321 /* Mandated version of PSCI */ 322 u32 psci_version; 323 324 /* Protects VM-scoped configuration data */ 325 struct mutex config_lock; 326 327 /* 328 * If we encounter a data abort without valid instruction syndrome 329 * information, report this to user space. User space can (and 330 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 331 * supported. 332 */ 333 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0 334 /* Memory Tagging Extension enabled for the guest */ 335 #define KVM_ARCH_FLAG_MTE_ENABLED 1 336 /* At least one vCPU has ran in the VM */ 337 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2 338 /* The vCPU feature set for the VM is configured */ 339 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3 340 /* PSCI SYSTEM_SUSPEND enabled for the guest */ 341 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4 342 /* VM counter offset */ 343 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5 344 /* Timer PPIs made immutable */ 345 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6 346 /* Initial ID reg values loaded */ 347 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 7 348 /* Fine-Grained UNDEF initialised */ 349 #define KVM_ARCH_FLAG_FGU_INITIALIZED 8 350 /* SVE exposed to guest */ 351 #define KVM_ARCH_FLAG_GUEST_HAS_SVE 9 352 /* MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are writable from userspace */ 353 #define KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS 10 354 /* Unhandled SEAs are taken to userspace */ 355 #define KVM_ARCH_FLAG_EXIT_SEA 11 356 unsigned long flags; 357 358 /* VM-wide vCPU feature set */ 359 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES); 360 361 /* MPIDR to vcpu index mapping, optional */ 362 struct kvm_mpidr_data *mpidr_data; 363 364 /* 365 * VM-wide PMU filter, implemented as a bitmap and big enough for 366 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+). 367 */ 368 unsigned long *pmu_filter; 369 struct arm_pmu *arm_pmu; 370 371 cpumask_var_t supported_cpus; 372 373 /* Maximum number of counters for the guest */ 374 u8 nr_pmu_counters; 375 376 /* Hypercall features firmware registers' descriptor */ 377 struct kvm_smccc_features smccc_feat; 378 struct maple_tree smccc_filter; 379 380 /* 381 * Emulated CPU ID registers per VM 382 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it 383 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. 384 * 385 * These emulated idregs are VM-wide, but accessed from the context of a vCPU. 386 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. 387 */ 388 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) 389 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) 390 u64 id_regs[KVM_ARM_ID_REG_NUM]; 391 392 u64 midr_el1; 393 u64 revidr_el1; 394 u64 aidr_el1; 395 u64 ctr_el0; 396 397 /* Masks for VNCR-backed and general EL2 sysregs */ 398 struct kvm_sysreg_masks *sysreg_masks; 399 400 /* Count the number of VNCR_EL2 currently mapped */ 401 atomic_t vncr_map_count; 402 403 /* 404 * For an untrusted host VM, 'pkvm.handle' is used to lookup 405 * the associated pKVM instance in the hypervisor. 406 */ 407 struct kvm_protected_vm pkvm; 408 }; 409 410 struct kvm_vcpu_fault_info { 411 u64 esr_el2; /* Hyp Syndrom Register */ 412 u64 far_el2; /* Hyp Fault Address Register */ 413 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 414 u64 disr_el1; /* Deferred [SError] Status Register */ 415 }; 416 417 /* 418 * VNCR() just places the VNCR_capable registers in the enum after 419 * __VNCR_START__, and the value (after correction) to be an 8-byte offset 420 * from the VNCR base. As we don't require the enum to be otherwise ordered, 421 * we need the terrible hack below to ensure that we correctly size the 422 * sys_regs array, no matter what. 423 * 424 * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful 425 * treasure trove of bit hacks: 426 * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax 427 */ 428 #define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y)))) 429 #define VNCR(r) \ 430 __before_##r, \ 431 r = __VNCR_START__ + ((VNCR_ ## r) / 8), \ 432 __after_##r = __MAX__(__before_##r - 1, r) 433 434 #define MARKER(m) \ 435 m, __after_##m = m - 1 436 437 enum vcpu_sysreg { 438 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 439 MPIDR_EL1, /* MultiProcessor Affinity Register */ 440 CLIDR_EL1, /* Cache Level ID Register */ 441 CSSELR_EL1, /* Cache Size Selection Register */ 442 TPIDR_EL0, /* Thread ID, User R/W */ 443 TPIDRRO_EL0, /* Thread ID, User R/O */ 444 TPIDR_EL1, /* Thread ID, Privileged */ 445 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 446 PAR_EL1, /* Physical Address Register */ 447 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 448 OSLSR_EL1, /* OS Lock Status Register */ 449 DISR_EL1, /* Deferred Interrupt Status Register */ 450 451 /* Performance Monitors Registers */ 452 PMCR_EL0, /* Control Register */ 453 PMSELR_EL0, /* Event Counter Selection Register */ 454 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 455 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 456 PMCCNTR_EL0, /* Cycle Counter Register */ 457 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 458 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 459 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 460 PMCNTENSET_EL0, /* Count Enable Set Register */ 461 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 462 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 463 PMUSERENR_EL0, /* User Enable Register */ 464 465 /* Pointer Authentication Registers in a strict increasing order. */ 466 APIAKEYLO_EL1, 467 APIAKEYHI_EL1, 468 APIBKEYLO_EL1, 469 APIBKEYHI_EL1, 470 APDAKEYLO_EL1, 471 APDAKEYHI_EL1, 472 APDBKEYLO_EL1, 473 APDBKEYHI_EL1, 474 APGAKEYLO_EL1, 475 APGAKEYHI_EL1, 476 477 /* Memory Tagging Extension registers */ 478 RGSR_EL1, /* Random Allocation Tag Seed Register */ 479 GCR_EL1, /* Tag Control Register */ 480 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ 481 482 POR_EL0, /* Permission Overlay Register 0 (EL0) */ 483 484 /* FP/SIMD/SVE */ 485 SVCR, 486 FPMR, 487 488 /* 32bit specific registers. */ 489 DACR32_EL2, /* Domain Access Control Register */ 490 IFSR32_EL2, /* Instruction Fault Status Register */ 491 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 492 DBGVCR32_EL2, /* Debug Vector Catch Register */ 493 494 /* EL2 registers */ 495 ACTLR_EL2, /* Auxiliary Control Register (EL2) */ 496 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ 497 HACR_EL2, /* Hypervisor Auxiliary Control Register */ 498 ZCR_EL2, /* SVE Control Register (EL2) */ 499 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ 500 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ 501 TCR_EL2, /* Translation Control Register (EL2) */ 502 PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */ 503 PIR_EL2, /* Permission Indirection Register 1 (EL2) */ 504 POR_EL2, /* Permission Overlay Register 2 (EL2) */ 505 SPSR_EL2, /* EL2 saved program status register */ 506 ELR_EL2, /* EL2 exception link register */ 507 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ 508 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */ 509 ESR_EL2, /* Exception Syndrome Register (EL2) */ 510 FAR_EL2, /* Fault Address Register (EL2) */ 511 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */ 512 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */ 513 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */ 514 VBAR_EL2, /* Vector Base Address Register (EL2) */ 515 RVBAR_EL2, /* Reset Vector Base Address Register */ 516 CONTEXTIDR_EL2, /* Context ID Register (EL2) */ 517 SP_EL2, /* EL2 Stack Pointer */ 518 CNTHP_CTL_EL2, 519 CNTHP_CVAL_EL2, 520 CNTHV_CTL_EL2, 521 CNTHV_CVAL_EL2, 522 523 /* Anything from this can be RES0/RES1 sanitised */ 524 MARKER(__SANITISED_REG_START__), 525 SCTLR_EL2, /* System Control Register (EL2) */ 526 TCR2_EL2, /* Extended Translation Control Register (EL2) */ 527 SCTLR2_EL2, /* System Control Register 2 (EL2) */ 528 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ 529 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ 530 531 /* Any VNCR-capable reg goes after this point */ 532 MARKER(__VNCR_START__), 533 534 VNCR(SCTLR_EL1),/* System Control Register */ 535 VNCR(ACTLR_EL1),/* Auxiliary Control Register */ 536 VNCR(CPACR_EL1),/* Coprocessor Access Control */ 537 VNCR(ZCR_EL1), /* SVE Control */ 538 VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ 539 VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ 540 VNCR(TCR_EL1), /* Translation Control Register */ 541 VNCR(TCR2_EL1), /* Extended Translation Control Register */ 542 VNCR(SCTLR2_EL1), /* System Control Register 2 */ 543 VNCR(ESR_EL1), /* Exception Syndrome Register */ 544 VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */ 545 VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */ 546 VNCR(FAR_EL1), /* Fault Address Register */ 547 VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */ 548 VNCR(VBAR_EL1), /* Vector Base Address Register */ 549 VNCR(CONTEXTIDR_EL1), /* Context ID Register */ 550 VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */ 551 VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */ 552 VNCR(ELR_EL1), 553 VNCR(SP_EL1), 554 VNCR(SPSR_EL1), 555 VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */ 556 VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */ 557 VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */ 558 VNCR(HCR_EL2), /* Hypervisor Configuration Register */ 559 VNCR(HSTR_EL2), /* Hypervisor System Trap Register */ 560 VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */ 561 VNCR(VTCR_EL2), /* Virtualization Translation Control Register */ 562 VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */ 563 VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */ 564 565 /* Permission Indirection Extension registers */ 566 VNCR(PIR_EL1), /* Permission Indirection Register 1 (EL1) */ 567 VNCR(PIRE0_EL1), /* Permission Indirection Register 0 (EL1) */ 568 569 VNCR(POR_EL1), /* Permission Overlay Register 1 (EL1) */ 570 571 /* FEAT_RAS registers */ 572 VNCR(VDISR_EL2), 573 VNCR(VSESR_EL2), 574 575 VNCR(HFGRTR_EL2), 576 VNCR(HFGWTR_EL2), 577 VNCR(HFGITR_EL2), 578 VNCR(HDFGRTR_EL2), 579 VNCR(HDFGWTR_EL2), 580 VNCR(HAFGRTR_EL2), 581 VNCR(HFGRTR2_EL2), 582 VNCR(HFGWTR2_EL2), 583 VNCR(HFGITR2_EL2), 584 VNCR(HDFGRTR2_EL2), 585 VNCR(HDFGWTR2_EL2), 586 587 VNCR(VNCR_EL2), 588 589 VNCR(CNTVOFF_EL2), 590 VNCR(CNTV_CVAL_EL0), 591 VNCR(CNTV_CTL_EL0), 592 VNCR(CNTP_CVAL_EL0), 593 VNCR(CNTP_CTL_EL0), 594 595 VNCR(ICH_LR0_EL2), 596 VNCR(ICH_LR1_EL2), 597 VNCR(ICH_LR2_EL2), 598 VNCR(ICH_LR3_EL2), 599 VNCR(ICH_LR4_EL2), 600 VNCR(ICH_LR5_EL2), 601 VNCR(ICH_LR6_EL2), 602 VNCR(ICH_LR7_EL2), 603 VNCR(ICH_LR8_EL2), 604 VNCR(ICH_LR9_EL2), 605 VNCR(ICH_LR10_EL2), 606 VNCR(ICH_LR11_EL2), 607 VNCR(ICH_LR12_EL2), 608 VNCR(ICH_LR13_EL2), 609 VNCR(ICH_LR14_EL2), 610 VNCR(ICH_LR15_EL2), 611 612 VNCR(ICH_AP0R0_EL2), 613 VNCR(ICH_AP0R1_EL2), 614 VNCR(ICH_AP0R2_EL2), 615 VNCR(ICH_AP0R3_EL2), 616 VNCR(ICH_AP1R0_EL2), 617 VNCR(ICH_AP1R1_EL2), 618 VNCR(ICH_AP1R2_EL2), 619 VNCR(ICH_AP1R3_EL2), 620 VNCR(ICH_HCR_EL2), 621 VNCR(ICH_VMCR_EL2), 622 623 NR_SYS_REGS /* Nothing after this line! */ 624 }; 625 626 struct resx { 627 u64 res0; 628 u64 res1; 629 }; 630 631 struct kvm_sysreg_masks { 632 struct resx mask[NR_SYS_REGS - __SANITISED_REG_START__]; 633 }; 634 635 static inline struct resx __kvm_get_sysreg_resx(struct kvm_arch *arch, 636 enum vcpu_sysreg sr) 637 { 638 struct kvm_sysreg_masks *masks; 639 640 masks = arch->sysreg_masks; 641 if (likely(masks && 642 sr >= __SANITISED_REG_START__ && sr < NR_SYS_REGS)) 643 return masks->mask[sr - __SANITISED_REG_START__]; 644 645 return (struct resx){}; 646 } 647 648 #define kvm_get_sysreg_resx(k, sr) __kvm_get_sysreg_resx(&(k)->arch, (sr)) 649 650 static inline void __kvm_set_sysreg_resx(struct kvm_arch *arch, 651 enum vcpu_sysreg sr, struct resx resx) 652 { 653 arch->sysreg_masks->mask[sr - __SANITISED_REG_START__] = resx; 654 } 655 656 #define kvm_set_sysreg_resx(k, sr, resx) \ 657 __kvm_set_sysreg_resx(&(k)->arch, (sr), (resx)) 658 659 struct fgt_masks { 660 const char *str; 661 u64 mask; 662 u64 nmask; 663 u64 res0; 664 u64 res1; 665 }; 666 667 extern struct fgt_masks hfgrtr_masks; 668 extern struct fgt_masks hfgwtr_masks; 669 extern struct fgt_masks hfgitr_masks; 670 extern struct fgt_masks hdfgrtr_masks; 671 extern struct fgt_masks hdfgwtr_masks; 672 extern struct fgt_masks hafgrtr_masks; 673 extern struct fgt_masks hfgrtr2_masks; 674 extern struct fgt_masks hfgwtr2_masks; 675 extern struct fgt_masks hfgitr2_masks; 676 extern struct fgt_masks hdfgrtr2_masks; 677 extern struct fgt_masks hdfgwtr2_masks; 678 679 extern struct fgt_masks kvm_nvhe_sym(hfgrtr_masks); 680 extern struct fgt_masks kvm_nvhe_sym(hfgwtr_masks); 681 extern struct fgt_masks kvm_nvhe_sym(hfgitr_masks); 682 extern struct fgt_masks kvm_nvhe_sym(hdfgrtr_masks); 683 extern struct fgt_masks kvm_nvhe_sym(hdfgwtr_masks); 684 extern struct fgt_masks kvm_nvhe_sym(hafgrtr_masks); 685 extern struct fgt_masks kvm_nvhe_sym(hfgrtr2_masks); 686 extern struct fgt_masks kvm_nvhe_sym(hfgwtr2_masks); 687 extern struct fgt_masks kvm_nvhe_sym(hfgitr2_masks); 688 extern struct fgt_masks kvm_nvhe_sym(hdfgrtr2_masks); 689 extern struct fgt_masks kvm_nvhe_sym(hdfgwtr2_masks); 690 691 struct kvm_cpu_context { 692 struct user_pt_regs regs; /* sp = sp_el0 */ 693 694 u64 spsr_abt; 695 u64 spsr_und; 696 u64 spsr_irq; 697 u64 spsr_fiq; 698 699 struct user_fpsimd_state fp_regs; 700 701 u64 sys_regs[NR_SYS_REGS]; 702 703 struct kvm_vcpu *__hyp_running_vcpu; 704 705 /* This pointer has to be 4kB aligned. */ 706 u64 *vncr_array; 707 }; 708 709 struct cpu_sve_state { 710 __u64 zcr_el1; 711 712 /* 713 * Ordering is important since __sve_save_state/__sve_restore_state 714 * relies on it. 715 */ 716 __u32 fpsr; 717 __u32 fpcr; 718 719 /* Must be SVE_VQ_BYTES (128 bit) aligned. */ 720 __u8 sve_regs[]; 721 }; 722 723 /* 724 * This structure is instantiated on a per-CPU basis, and contains 725 * data that is: 726 * 727 * - tied to a single physical CPU, and 728 * - either have a lifetime that does not extend past vcpu_put() 729 * - or is an invariant for the lifetime of the system 730 * 731 * Use host_data_ptr(field) as a way to access a pointer to such a 732 * field. 733 */ 734 struct kvm_host_data { 735 #define KVM_HOST_DATA_FLAG_HAS_SPE 0 736 #define KVM_HOST_DATA_FLAG_HAS_TRBE 1 737 #define KVM_HOST_DATA_FLAG_TRBE_ENABLED 2 738 #define KVM_HOST_DATA_FLAG_EL1_TRACING_CONFIGURED 3 739 #define KVM_HOST_DATA_FLAG_VCPU_IN_HYP_CONTEXT 4 740 #define KVM_HOST_DATA_FLAG_L1_VNCR_MAPPED 5 741 #define KVM_HOST_DATA_FLAG_HAS_BRBE 6 742 unsigned long flags; 743 744 struct kvm_cpu_context host_ctxt; 745 746 /* 747 * Hyp VA. 748 * sve_state is only used in pKVM and if system_supports_sve(). 749 */ 750 struct cpu_sve_state *sve_state; 751 752 /* Used by pKVM only. */ 753 u64 fpmr; 754 755 /* Ownership of the FP regs */ 756 enum { 757 FP_STATE_FREE, 758 FP_STATE_HOST_OWNED, 759 FP_STATE_GUEST_OWNED, 760 } fp_owner; 761 762 /* 763 * host_debug_state contains the host registers which are 764 * saved and restored during world switches. 765 */ 766 struct { 767 /* {Break,watch}point registers */ 768 struct kvm_guest_debug_arch regs; 769 /* Statistical profiling extension */ 770 u64 pmscr_el1; 771 /* Self-hosted trace */ 772 u64 trfcr_el1; 773 /* Values of trap registers for the host before guest entry. */ 774 u64 mdcr_el2; 775 u64 brbcr_el1; 776 } host_debug_state; 777 778 /* Guest trace filter value */ 779 u64 trfcr_while_in_guest; 780 781 /* Number of programmable event counters (PMCR_EL0.N) for this CPU */ 782 unsigned int nr_event_counters; 783 784 /* Number of debug breakpoints/watchpoints for this CPU (minus 1) */ 785 unsigned int debug_brps; 786 unsigned int debug_wrps; 787 }; 788 789 struct kvm_host_psci_config { 790 /* PSCI version used by host. */ 791 u32 version; 792 u32 smccc_version; 793 794 /* Function IDs used by host if version is v0.1. */ 795 struct psci_0_1_function_ids function_ids_0_1; 796 797 bool psci_0_1_cpu_suspend_implemented; 798 bool psci_0_1_cpu_on_implemented; 799 bool psci_0_1_cpu_off_implemented; 800 bool psci_0_1_migrate_implemented; 801 }; 802 803 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config); 804 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config) 805 806 extern s64 kvm_nvhe_sym(hyp_physvirt_offset); 807 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset) 808 809 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS]; 810 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map) 811 812 struct vcpu_reset_state { 813 unsigned long pc; 814 unsigned long r0; 815 bool be; 816 bool reset; 817 }; 818 819 struct vncr_tlb; 820 821 struct kvm_vcpu_arch { 822 struct kvm_cpu_context ctxt; 823 824 /* 825 * Guest floating point state 826 * 827 * The architecture has two main floating point extensions, 828 * the original FPSIMD and SVE. These have overlapping 829 * register views, with the FPSIMD V registers occupying the 830 * low 128 bits of the SVE Z registers. When the core 831 * floating point code saves the register state of a task it 832 * records which view it saved in fp_type. 833 */ 834 void *sve_state; 835 enum fp_type fp_type; 836 unsigned int sve_max_vl; 837 838 /* Stage 2 paging state used by the hardware on next switch */ 839 struct kvm_s2_mmu *hw_mmu; 840 841 /* Values of trap registers for the guest. */ 842 u64 hcr_el2; 843 u64 hcrx_el2; 844 u64 mdcr_el2; 845 846 struct { 847 u64 r; 848 u64 w; 849 } fgt[__NR_FGT_GROUP_IDS__]; 850 851 /* Exception Information */ 852 struct kvm_vcpu_fault_info fault; 853 854 /* Configuration flags, set once and for all before the vcpu can run */ 855 u8 cflags; 856 857 /* Input flags to the hypervisor code, potentially cleared after use */ 858 u8 iflags; 859 860 /* State flags for kernel bookkeeping, unused by the hypervisor code */ 861 u16 sflags; 862 863 /* 864 * Don't run the guest (internal implementation need). 865 * 866 * Contrary to the flags above, this is set/cleared outside of 867 * a vcpu context, and thus cannot be mixed with the flags 868 * themselves (or the flag accesses need to be made atomic). 869 */ 870 bool pause; 871 872 /* 873 * We maintain more than a single set of debug registers to support 874 * debugging the guest from the host and to maintain separate host and 875 * guest state during world switches. vcpu_debug_state are the debug 876 * registers of the vcpu as the guest sees them. 877 * 878 * external_debug_state contains the debug values we want to debug the 879 * guest. This is set via the KVM_SET_GUEST_DEBUG ioctl. 880 */ 881 struct kvm_guest_debug_arch vcpu_debug_state; 882 struct kvm_guest_debug_arch external_debug_state; 883 u64 external_mdscr_el1; 884 885 enum { 886 VCPU_DEBUG_FREE, 887 VCPU_DEBUG_HOST_OWNED, 888 VCPU_DEBUG_GUEST_OWNED, 889 } debug_owner; 890 891 /* VGIC state */ 892 struct vgic_cpu vgic_cpu; 893 struct arch_timer_cpu timer_cpu; 894 struct kvm_pmu pmu; 895 896 /* vcpu power state */ 897 struct kvm_mp_state mp_state; 898 spinlock_t mp_state_lock; 899 900 /* Cache some mmu pages needed inside spinlock regions */ 901 struct kvm_mmu_memory_cache mmu_page_cache; 902 903 /* Pages to top-up the pKVM/EL2 guest pool */ 904 struct kvm_hyp_memcache pkvm_memcache; 905 906 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 907 u64 vsesr_el2; 908 909 /* Additional reset state */ 910 struct vcpu_reset_state reset_state; 911 912 /* Guest PV state */ 913 struct { 914 u64 last_steal; 915 gpa_t base; 916 } steal; 917 918 /* Per-vcpu CCSIDR override or NULL */ 919 u32 *ccsidr; 920 921 /* Per-vcpu TLB for VNCR_EL2 -- NULL when !NV */ 922 struct vncr_tlb *vncr_tlb; 923 }; 924 925 /* 926 * Each 'flag' is composed of a comma-separated triplet: 927 * 928 * - the flag-set it belongs to in the vcpu->arch structure 929 * - the value for that flag 930 * - the mask for that flag 931 * 932 * __vcpu_single_flag() builds such a triplet for a single-bit flag. 933 * unpack_vcpu_flag() extract the flag value from the triplet for 934 * direct use outside of the flag accessors. 935 */ 936 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f) 937 938 #define __unpack_flag(_set, _f, _m) _f 939 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__) 940 941 #define __build_check_flag(v, flagset, f, m) \ 942 do { \ 943 typeof(v->arch.flagset) *_fset; \ 944 \ 945 /* Check that the flags fit in the mask */ \ 946 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \ 947 /* Check that the flags fit in the type */ \ 948 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \ 949 } while (0) 950 951 #define __vcpu_get_flag(v, flagset, f, m) \ 952 ({ \ 953 __build_check_flag(v, flagset, f, m); \ 954 \ 955 READ_ONCE(v->arch.flagset) & (m); \ 956 }) 957 958 /* 959 * Note that the set/clear accessors must be preempt-safe in order to 960 * avoid nesting them with load/put which also manipulate flags... 961 */ 962 #ifdef __KVM_NVHE_HYPERVISOR__ 963 /* the nVHE hypervisor is always non-preemptible */ 964 #define __vcpu_flags_preempt_disable() 965 #define __vcpu_flags_preempt_enable() 966 #else 967 #define __vcpu_flags_preempt_disable() preempt_disable() 968 #define __vcpu_flags_preempt_enable() preempt_enable() 969 #endif 970 971 #define __vcpu_set_flag(v, flagset, f, m) \ 972 do { \ 973 typeof(v->arch.flagset) *fset; \ 974 \ 975 __build_check_flag(v, flagset, f, m); \ 976 \ 977 fset = &v->arch.flagset; \ 978 __vcpu_flags_preempt_disable(); \ 979 if (HWEIGHT(m) > 1) \ 980 *fset &= ~(m); \ 981 *fset |= (f); \ 982 __vcpu_flags_preempt_enable(); \ 983 } while (0) 984 985 #define __vcpu_clear_flag(v, flagset, f, m) \ 986 do { \ 987 typeof(v->arch.flagset) *fset; \ 988 \ 989 __build_check_flag(v, flagset, f, m); \ 990 \ 991 fset = &v->arch.flagset; \ 992 __vcpu_flags_preempt_disable(); \ 993 *fset &= ~(m); \ 994 __vcpu_flags_preempt_enable(); \ 995 } while (0) 996 997 #define __vcpu_test_and_clear_flag(v, flagset, f, m) \ 998 ({ \ 999 typeof(v->arch.flagset) set; \ 1000 \ 1001 set = __vcpu_get_flag(v, flagset, f, m); \ 1002 __vcpu_clear_flag(v, flagset, f, m); \ 1003 \ 1004 set; \ 1005 }) 1006 1007 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__) 1008 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__) 1009 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__) 1010 #define vcpu_test_and_clear_flag(v, ...) \ 1011 __vcpu_test_and_clear_flag((v), __VA_ARGS__) 1012 1013 /* KVM_ARM_VCPU_INIT completed */ 1014 #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(0)) 1015 /* SVE config completed */ 1016 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1)) 1017 /* pKVM VCPU setup completed */ 1018 #define VCPU_PKVM_FINALIZED __vcpu_single_flag(cflags, BIT(2)) 1019 1020 /* Exception pending */ 1021 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0)) 1022 /* 1023 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't 1024 * be set together with an exception... 1025 */ 1026 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1)) 1027 /* Target EL/MODE (not a single flag, but let's abuse the macro) */ 1028 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1)) 1029 1030 /* Helpers to encode exceptions with minimum fuss */ 1031 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK) 1032 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL) 1033 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL 1034 1035 /* 1036 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following 1037 * values: 1038 * 1039 * For AArch32 EL1: 1040 */ 1041 #define EXCEPT_AA32_UND __vcpu_except_flags(0) 1042 #define EXCEPT_AA32_IABT __vcpu_except_flags(1) 1043 #define EXCEPT_AA32_DABT __vcpu_except_flags(2) 1044 /* For AArch64: */ 1045 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0) 1046 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1) 1047 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2) 1048 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3) 1049 /* For AArch64 with NV: */ 1050 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4) 1051 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5) 1052 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6) 1053 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7) 1054 1055 /* Physical CPU not in supported_cpus */ 1056 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(0)) 1057 /* WFIT instruction trapped */ 1058 #define IN_WFIT __vcpu_single_flag(sflags, BIT(1)) 1059 /* vcpu system registers loaded on physical CPU */ 1060 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(2)) 1061 /* Software step state is Active-pending for external debug */ 1062 #define HOST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(3)) 1063 /* Software step state is Active pending for guest debug */ 1064 #define GUEST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(4)) 1065 /* PMUSERENR for the guest EL0 is on physical CPU */ 1066 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(5)) 1067 /* WFI instruction trapped */ 1068 #define IN_WFI __vcpu_single_flag(sflags, BIT(6)) 1069 /* KVM is currently emulating a nested ERET */ 1070 #define IN_NESTED_ERET __vcpu_single_flag(sflags, BIT(7)) 1071 /* SError pending for nested guest */ 1072 #define NESTED_SERROR_PENDING __vcpu_single_flag(sflags, BIT(8)) 1073 1074 1075 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 1076 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ 1077 sve_ffr_offset((vcpu)->arch.sve_max_vl)) 1078 1079 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) 1080 1081 #define vcpu_sve_zcr_elx(vcpu) \ 1082 (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1) 1083 1084 #define sve_state_size_from_vl(sve_max_vl) ({ \ 1085 size_t __size_ret; \ 1086 unsigned int __vq; \ 1087 \ 1088 if (WARN_ON(!sve_vl_valid(sve_max_vl))) { \ 1089 __size_ret = 0; \ 1090 } else { \ 1091 __vq = sve_vq_from_vl(sve_max_vl); \ 1092 __size_ret = SVE_SIG_REGS_SIZE(__vq); \ 1093 } \ 1094 \ 1095 __size_ret; \ 1096 }) 1097 1098 #define vcpu_sve_state_size(vcpu) sve_state_size_from_vl((vcpu)->arch.sve_max_vl) 1099 1100 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ 1101 KVM_GUESTDBG_USE_SW_BP | \ 1102 KVM_GUESTDBG_USE_HW | \ 1103 KVM_GUESTDBG_SINGLESTEP) 1104 1105 #define kvm_has_sve(kvm) (system_supports_sve() && \ 1106 test_bit(KVM_ARCH_FLAG_GUEST_HAS_SVE, &(kvm)->arch.flags)) 1107 1108 #ifdef __KVM_NVHE_HYPERVISOR__ 1109 #define vcpu_has_sve(vcpu) kvm_has_sve(kern_hyp_va((vcpu)->kvm)) 1110 #else 1111 #define vcpu_has_sve(vcpu) kvm_has_sve((vcpu)->kvm) 1112 #endif 1113 1114 #ifdef CONFIG_ARM64_PTR_AUTH 1115 #define vcpu_has_ptrauth(vcpu) \ 1116 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 1117 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 1118 (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_ADDRESS) || \ 1119 vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_GENERIC))) 1120 #else 1121 #define vcpu_has_ptrauth(vcpu) false 1122 #endif 1123 1124 #define vcpu_on_unsupported_cpu(vcpu) \ 1125 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU) 1126 1127 #define vcpu_set_on_unsupported_cpu(vcpu) \ 1128 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU) 1129 1130 #define vcpu_clear_on_unsupported_cpu(vcpu) \ 1131 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU) 1132 1133 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) 1134 1135 /* 1136 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the 1137 * memory backed version of a register, and not the one most recently 1138 * accessed by a running VCPU. For example, for userspace access or 1139 * for system registers that are never context switched, but only 1140 * emulated. 1141 * 1142 * Don't bother with VNCR-based accesses in the nVHE code, it has no 1143 * business dealing with NV. 1144 */ 1145 static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r) 1146 { 1147 #if !defined (__KVM_NVHE_HYPERVISOR__) 1148 if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) && 1149 r >= __VNCR_START__ && ctxt->vncr_array)) 1150 return &ctxt->vncr_array[r - __VNCR_START__]; 1151 #endif 1152 return (u64 *)&ctxt->sys_regs[r]; 1153 } 1154 1155 #define __ctxt_sys_reg(c,r) \ 1156 ({ \ 1157 BUILD_BUG_ON(__builtin_constant_p(r) && \ 1158 (r) >= NR_SYS_REGS); \ 1159 ___ctxt_sys_reg(c, r); \ 1160 }) 1161 1162 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) 1163 1164 u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64); 1165 1166 #define __vcpu_assign_sys_reg(v, r, val) \ 1167 do { \ 1168 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1169 u64 __v = (val); \ 1170 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1171 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1172 \ 1173 ctxt_sys_reg(ctxt, (r)) = __v; \ 1174 } while (0) 1175 1176 #define __vcpu_rmw_sys_reg(v, r, op, val) \ 1177 do { \ 1178 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1179 u64 __v = ctxt_sys_reg(ctxt, (r)); \ 1180 __v op (val); \ 1181 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1182 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1183 \ 1184 ctxt_sys_reg(ctxt, (r)) = __v; \ 1185 } while (0) 1186 1187 #define __vcpu_sys_reg(v,r) \ 1188 ({ \ 1189 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1190 u64 __v = ctxt_sys_reg(ctxt, (r)); \ 1191 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1192 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \ 1193 __v; \ 1194 }) 1195 1196 u64 vcpu_read_sys_reg(const struct kvm_vcpu *, enum vcpu_sysreg); 1197 void vcpu_write_sys_reg(struct kvm_vcpu *, u64, enum vcpu_sysreg); 1198 1199 struct kvm_vm_stat { 1200 struct kvm_vm_stat_generic generic; 1201 }; 1202 1203 struct kvm_vcpu_stat { 1204 struct kvm_vcpu_stat_generic generic; 1205 u64 hvc_exit_stat; 1206 u64 wfe_exit_stat; 1207 u64 wfi_exit_stat; 1208 u64 mmio_exit_user; 1209 u64 mmio_exit_kernel; 1210 u64 signal_exits; 1211 u64 exits; 1212 }; 1213 1214 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 1215 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 1216 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1217 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1218 1219 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu); 1220 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); 1221 1222 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 1223 struct kvm_vcpu_events *events); 1224 1225 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 1226 struct kvm_vcpu_events *events); 1227 1228 void kvm_arm_halt_guest(struct kvm *kvm); 1229 void kvm_arm_resume_guest(struct kvm *kvm); 1230 1231 #define vcpu_has_run_once(vcpu) (!!READ_ONCE((vcpu)->pid)) 1232 1233 #ifndef __KVM_NVHE_HYPERVISOR__ 1234 #define kvm_call_hyp_nvhe(f, ...) \ 1235 ({ \ 1236 struct arm_smccc_res res; \ 1237 \ 1238 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \ 1239 ##__VA_ARGS__, &res); \ 1240 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \ 1241 \ 1242 res.a1; \ 1243 }) 1244 1245 /* 1246 * The isb() below is there to guarantee the same behaviour on VHE as on !VHE, 1247 * where the eret to EL1 acts as a context synchronization event. 1248 */ 1249 #define kvm_call_hyp(f, ...) \ 1250 do { \ 1251 if (has_vhe()) { \ 1252 f(__VA_ARGS__); \ 1253 isb(); \ 1254 } else { \ 1255 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1256 } \ 1257 } while(0) 1258 1259 #define kvm_call_hyp_ret(f, ...) \ 1260 ({ \ 1261 typeof(f(__VA_ARGS__)) ret; \ 1262 \ 1263 if (has_vhe()) { \ 1264 ret = f(__VA_ARGS__); \ 1265 } else { \ 1266 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1267 } \ 1268 \ 1269 ret; \ 1270 }) 1271 #else /* __KVM_NVHE_HYPERVISOR__ */ 1272 #define kvm_call_hyp(f, ...) f(__VA_ARGS__) 1273 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__) 1274 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__) 1275 #endif /* __KVM_NVHE_HYPERVISOR__ */ 1276 1277 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 1278 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 1279 1280 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu); 1281 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); 1282 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); 1283 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); 1284 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); 1285 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); 1286 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); 1287 1288 void kvm_sys_regs_create_debugfs(struct kvm *kvm); 1289 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); 1290 1291 int __init kvm_sys_reg_table_init(void); 1292 struct sys_reg_desc; 1293 int __init populate_sysreg_config(const struct sys_reg_desc *sr, 1294 unsigned int idx); 1295 int __init populate_nv_trap_config(void); 1296 1297 void kvm_calculate_traps(struct kvm_vcpu *vcpu); 1298 1299 /* MMIO helpers */ 1300 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 1301 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 1302 1303 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 1304 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 1305 1306 /* 1307 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event, 1308 * arrived in guest context. For arm64, any event that arrives while a vCPU is 1309 * loaded is considered to be "in guest". 1310 */ 1311 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 1312 { 1313 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; 1314 } 1315 1316 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 1317 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 1318 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 1319 1320 bool kvm_arm_pvtime_supported(void); 1321 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 1322 struct kvm_device_attr *attr); 1323 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 1324 struct kvm_device_attr *attr); 1325 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 1326 struct kvm_device_attr *attr); 1327 1328 extern unsigned int __ro_after_init kvm_arm_vmid_bits; 1329 int __init kvm_arm_vmid_alloc_init(void); 1330 void __init kvm_arm_vmid_alloc_free(void); 1331 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid); 1332 void kvm_arm_vmid_clear_active(void); 1333 1334 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 1335 { 1336 vcpu_arch->steal.base = INVALID_GPA; 1337 } 1338 1339 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 1340 { 1341 return (vcpu_arch->steal.base != INVALID_GPA); 1342 } 1343 1344 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 1345 1346 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); 1347 1348 /* 1349 * How we access per-CPU host data depends on the where we access it from, 1350 * and the mode we're in: 1351 * 1352 * - VHE and nVHE hypervisor bits use their locally defined instance 1353 * 1354 * - the rest of the kernel use either the VHE or nVHE one, depending on 1355 * the mode we're running in. 1356 * 1357 * Unless we're in protected mode, fully deprivileged, and the nVHE 1358 * per-CPU stuff is exclusively accessible to the protected EL2 code. 1359 * In this case, the EL1 code uses the *VHE* data as its private state 1360 * (which makes sense in a way as there shouldn't be any shared state 1361 * between the host and the hypervisor). 1362 * 1363 * Yes, this is all totally trivial. Shoot me now. 1364 */ 1365 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__) 1366 #define host_data_ptr(f) (&this_cpu_ptr(&kvm_host_data)->f) 1367 #else 1368 #define host_data_ptr(f) \ 1369 (static_branch_unlikely(&kvm_protected_mode_initialized) ? \ 1370 &this_cpu_ptr(&kvm_host_data)->f : \ 1371 &this_cpu_ptr_hyp_sym(kvm_host_data)->f) 1372 #endif 1373 1374 #define host_data_test_flag(flag) \ 1375 (test_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags))) 1376 #define host_data_set_flag(flag) \ 1377 set_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)) 1378 #define host_data_clear_flag(flag) \ 1379 clear_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)) 1380 1381 /* Check whether the FP regs are owned by the guest */ 1382 static inline bool guest_owns_fp_regs(void) 1383 { 1384 return *host_data_ptr(fp_owner) == FP_STATE_GUEST_OWNED; 1385 } 1386 1387 /* Check whether the FP regs are owned by the host */ 1388 static inline bool host_owns_fp_regs(void) 1389 { 1390 return *host_data_ptr(fp_owner) == FP_STATE_HOST_OWNED; 1391 } 1392 1393 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 1394 { 1395 /* The host's MPIDR is immutable, so let's set it up at boot time */ 1396 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); 1397 } 1398 1399 static inline bool kvm_system_needs_idmapped_vectors(void) 1400 { 1401 return cpus_have_final_cap(ARM64_SPECTRE_V3A); 1402 } 1403 1404 void kvm_init_host_debug_data(void); 1405 void kvm_debug_init_vhe(void); 1406 void kvm_vcpu_load_debug(struct kvm_vcpu *vcpu); 1407 void kvm_vcpu_put_debug(struct kvm_vcpu *vcpu); 1408 void kvm_debug_set_guest_ownership(struct kvm_vcpu *vcpu); 1409 void kvm_debug_handle_oslar(struct kvm_vcpu *vcpu, u64 val); 1410 1411 #define kvm_vcpu_os_lock_enabled(vcpu) \ 1412 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK)) 1413 1414 #define kvm_debug_regs_in_use(vcpu) \ 1415 ((vcpu)->arch.debug_owner != VCPU_DEBUG_FREE) 1416 #define kvm_host_owns_debug_regs(vcpu) \ 1417 ((vcpu)->arch.debug_owner == VCPU_DEBUG_HOST_OWNED) 1418 #define kvm_guest_owns_debug_regs(vcpu) \ 1419 ((vcpu)->arch.debug_owner == VCPU_DEBUG_GUEST_OWNED) 1420 1421 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 1422 struct kvm_device_attr *attr); 1423 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 1424 struct kvm_device_attr *attr); 1425 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 1426 struct kvm_device_attr *attr); 1427 1428 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, 1429 struct kvm_arm_copy_mte_tags *copy_tags); 1430 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, 1431 struct kvm_arm_counter_offset *offset); 1432 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, 1433 struct reg_mask_range *range); 1434 1435 /* Guest/host FPSIMD coordination helpers */ 1436 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 1437 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu); 1438 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 1439 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 1440 1441 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 1442 { 1443 return (!has_vhe() && attr->exclude_host); 1444 } 1445 1446 #ifdef CONFIG_KVM 1447 void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr); 1448 void kvm_clr_pmu_events(u64 clr); 1449 bool kvm_set_pmuserenr(u64 val); 1450 void kvm_enable_trbe(void); 1451 void kvm_disable_trbe(void); 1452 void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest); 1453 #else 1454 static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) {} 1455 static inline void kvm_clr_pmu_events(u64 clr) {} 1456 static inline bool kvm_set_pmuserenr(u64 val) 1457 { 1458 return false; 1459 } 1460 static inline void kvm_enable_trbe(void) {} 1461 static inline void kvm_disable_trbe(void) {} 1462 static inline void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest) {} 1463 #endif 1464 1465 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu); 1466 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu); 1467 1468 int __init kvm_set_ipa_limit(void); 1469 u32 kvm_get_pa_bits(struct kvm *kvm); 1470 1471 #define __KVM_HAVE_ARCH_VM_ALLOC 1472 struct kvm *kvm_arch_alloc_vm(void); 1473 1474 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS 1475 1476 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE 1477 1478 #define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arch.pkvm.is_protected) 1479 1480 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) 1481 1482 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 1483 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 1484 1485 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED) 1486 1487 #define kvm_has_mte(kvm) \ 1488 (system_supports_mte() && \ 1489 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags)) 1490 1491 #define kvm_supports_32bit_el0() \ 1492 (system_supports_32bit_el0() && \ 1493 !static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1494 1495 #define kvm_vm_has_ran_once(kvm) \ 1496 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags)) 1497 1498 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature) 1499 { 1500 return test_bit(feature, ka->vcpu_features); 1501 } 1502 1503 #define kvm_vcpu_has_feature(k, f) __vcpu_has_feature(&(k)->arch, (f)) 1504 #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f)) 1505 1506 #define kvm_vcpu_initialized(v) vcpu_get_flag(vcpu, VCPU_INITIALIZED) 1507 1508 int kvm_trng_call(struct kvm_vcpu *vcpu); 1509 #ifdef CONFIG_KVM 1510 extern phys_addr_t hyp_mem_base; 1511 extern phys_addr_t hyp_mem_size; 1512 void __init kvm_hyp_reserve(void); 1513 #else 1514 static inline void kvm_hyp_reserve(void) { } 1515 #endif 1516 1517 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); 1518 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); 1519 1520 static inline u64 *__vm_id_reg(struct kvm_arch *ka, u32 reg) 1521 { 1522 switch (reg) { 1523 case sys_reg(3, 0, 0, 1, 0) ... sys_reg(3, 0, 0, 7, 7): 1524 return &ka->id_regs[IDREG_IDX(reg)]; 1525 case SYS_CTR_EL0: 1526 return &ka->ctr_el0; 1527 case SYS_MIDR_EL1: 1528 return &ka->midr_el1; 1529 case SYS_REVIDR_EL1: 1530 return &ka->revidr_el1; 1531 case SYS_AIDR_EL1: 1532 return &ka->aidr_el1; 1533 default: 1534 WARN_ON_ONCE(1); 1535 return NULL; 1536 } 1537 } 1538 1539 #define kvm_read_vm_id_reg(kvm, reg) \ 1540 ({ u64 __val = *__vm_id_reg(&(kvm)->arch, reg); __val; }) 1541 1542 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val); 1543 1544 #define __expand_field_sign_unsigned(id, fld, val) \ 1545 ((u64)SYS_FIELD_VALUE(id, fld, val)) 1546 1547 #define __expand_field_sign_signed(id, fld, val) \ 1548 ({ \ 1549 u64 __val = SYS_FIELD_VALUE(id, fld, val); \ 1550 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1551 }) 1552 1553 #define get_idreg_field_unsigned(kvm, id, fld) \ 1554 ({ \ 1555 u64 __val = kvm_read_vm_id_reg((kvm), SYS_##id); \ 1556 FIELD_GET(id##_##fld##_MASK, __val); \ 1557 }) 1558 1559 #define get_idreg_field_signed(kvm, id, fld) \ 1560 ({ \ 1561 u64 __val = get_idreg_field_unsigned(kvm, id, fld); \ 1562 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1563 }) 1564 1565 #define get_idreg_field_enum(kvm, id, fld) \ 1566 get_idreg_field_unsigned(kvm, id, fld) 1567 1568 #define kvm_cmp_feat_signed(kvm, id, fld, op, limit) \ 1569 (get_idreg_field_signed((kvm), id, fld) op __expand_field_sign_signed(id, fld, limit)) 1570 1571 #define kvm_cmp_feat_unsigned(kvm, id, fld, op, limit) \ 1572 (get_idreg_field_unsigned((kvm), id, fld) op __expand_field_sign_unsigned(id, fld, limit)) 1573 1574 #define kvm_cmp_feat(kvm, id, fld, op, limit) \ 1575 (id##_##fld##_SIGNED ? \ 1576 kvm_cmp_feat_signed(kvm, id, fld, op, limit) : \ 1577 kvm_cmp_feat_unsigned(kvm, id, fld, op, limit)) 1578 1579 #define __kvm_has_feat(kvm, id, fld, limit) \ 1580 kvm_cmp_feat(kvm, id, fld, >=, limit) 1581 1582 #define kvm_has_feat(kvm, ...) __kvm_has_feat(kvm, __VA_ARGS__) 1583 1584 #define __kvm_has_feat_enum(kvm, id, fld, val) \ 1585 kvm_cmp_feat_unsigned(kvm, id, fld, ==, val) 1586 1587 #define kvm_has_feat_enum(kvm, ...) __kvm_has_feat_enum(kvm, __VA_ARGS__) 1588 1589 #define kvm_has_feat_range(kvm, id, fld, min, max) \ 1590 (kvm_cmp_feat(kvm, id, fld, >=, min) && \ 1591 kvm_cmp_feat(kvm, id, fld, <=, max)) 1592 1593 /* Check for a given level of PAuth support */ 1594 #define kvm_has_pauth(k, l) \ 1595 ({ \ 1596 bool pa, pi, pa3; \ 1597 \ 1598 pa = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l); \ 1599 pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP); \ 1600 pi = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l); \ 1601 pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP); \ 1602 pa3 = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l); \ 1603 pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP); \ 1604 \ 1605 (pa + pi + pa3) == 1; \ 1606 }) 1607 1608 #define kvm_has_fpmr(k) \ 1609 (system_supports_fpmr() && \ 1610 kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP)) 1611 1612 #define kvm_has_tcr2(k) \ 1613 (kvm_has_feat((k), ID_AA64MMFR3_EL1, TCRX, IMP)) 1614 1615 #define kvm_has_s1pie(k) \ 1616 (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1PIE, IMP)) 1617 1618 #define kvm_has_s1poe(k) \ 1619 (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1POE, IMP)) 1620 1621 #define kvm_has_ras(k) \ 1622 (kvm_has_feat((k), ID_AA64PFR0_EL1, RAS, IMP)) 1623 1624 #define kvm_has_sctlr2(k) \ 1625 (kvm_has_feat((k), ID_AA64MMFR3_EL1, SCTLRX, IMP)) 1626 1627 static inline bool kvm_arch_has_irq_bypass(void) 1628 { 1629 return true; 1630 } 1631 1632 void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt); 1633 struct resx get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg); 1634 void check_feature_map(void); 1635 void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu); 1636 1637 static __always_inline enum fgt_group_id __fgt_reg_to_group_id(enum vcpu_sysreg reg) 1638 { 1639 switch (reg) { 1640 case HFGRTR_EL2: 1641 case HFGWTR_EL2: 1642 return HFGRTR_GROUP; 1643 case HFGITR_EL2: 1644 return HFGITR_GROUP; 1645 case HDFGRTR_EL2: 1646 case HDFGWTR_EL2: 1647 return HDFGRTR_GROUP; 1648 case HAFGRTR_EL2: 1649 return HAFGRTR_GROUP; 1650 case HFGRTR2_EL2: 1651 case HFGWTR2_EL2: 1652 return HFGRTR2_GROUP; 1653 case HFGITR2_EL2: 1654 return HFGITR2_GROUP; 1655 case HDFGRTR2_EL2: 1656 case HDFGWTR2_EL2: 1657 return HDFGRTR2_GROUP; 1658 default: 1659 BUILD_BUG_ON(1); 1660 } 1661 } 1662 1663 #define vcpu_fgt(vcpu, reg) \ 1664 ({ \ 1665 enum fgt_group_id id = __fgt_reg_to_group_id(reg); \ 1666 u64 *p; \ 1667 switch (reg) { \ 1668 case HFGWTR_EL2: \ 1669 case HDFGWTR_EL2: \ 1670 case HFGWTR2_EL2: \ 1671 case HDFGWTR2_EL2: \ 1672 p = &(vcpu)->arch.fgt[id].w; \ 1673 break; \ 1674 default: \ 1675 p = &(vcpu)->arch.fgt[id].r; \ 1676 break; \ 1677 } \ 1678 \ 1679 p; \ 1680 }) 1681 1682 long kvm_get_cap_for_kvm_ioctl(unsigned int ioctl, long *ext); 1683 1684 #endif /* __ARM64_KVM_HOST_H__ */ 1685