1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9 /**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34 #include <drm/display/drm_hdmi_audio_helper.h>
35 #include <drm/display/drm_hdmi_helper.h>
36 #include <drm/display/drm_hdmi_state_helper.h>
37 #include <drm/display/drm_scdc_helper.h>
38 #include <drm/drm_atomic_helper.h>
39 #include <drm/drm_drv.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_probe_helper.h>
42 #include <drm/drm_simple_kms_helper.h>
43 #include <linux/clk.h>
44 #include <linux/component.h>
45 #include <linux/gpio/consumer.h>
46 #include <linux/i2c.h>
47 #include <linux/of.h>
48 #include <linux/of_address.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/rational.h>
51 #include <linux/reset.h>
52 #include <sound/dmaengine_pcm.h>
53 #include <sound/hdmi-codec.h>
54 #include <sound/jack.h>
55 #include <sound/pcm_drm_eld.h>
56 #include <sound/pcm_params.h>
57 #include <sound/soc.h>
58 #include "media/cec.h"
59 #include "vc4_drv.h"
60 #include "vc4_hdmi.h"
61 #include "vc4_hdmi_regs.h"
62 #include "vc4_regs.h"
63
64 #define VC5_HDMI_HORZA_HFP_SHIFT 16
65 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
66 #define VC5_HDMI_HORZA_VPOS BIT(15)
67 #define VC5_HDMI_HORZA_HPOS BIT(14)
68 #define VC5_HDMI_HORZA_HAP_SHIFT 0
69 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
70
71 #define VC5_HDMI_HORZB_HBP_SHIFT 16
72 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
73 #define VC5_HDMI_HORZB_HSP_SHIFT 0
74 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
75
76 #define VC5_HDMI_VERTA_VSP_SHIFT 24
77 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
78 #define VC5_HDMI_VERTA_VFP_SHIFT 16
79 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
80 #define VC5_HDMI_VERTA_VAL_SHIFT 0
81 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
82
83 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
84 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
85
86 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
87 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
88 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
89 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
90
91 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
92
93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
94 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
95
96 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
97 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
98
99 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
100
101 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
102 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
103
104 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0)
105 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0)
106 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4)
107
108 # define VC4_HD_M_SW_RST BIT(2)
109 # define VC4_HD_M_ENABLE BIT(0)
110
111 #define HSM_MIN_CLOCK_FREQ 120000000
112 #define CEC_CLOCK_FREQ 40000
113
114 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
115
vc4_hdmi_supports_scrambling(struct vc4_hdmi * vc4_hdmi)116 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi)
117 {
118 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
119
120 lockdep_assert_held(&vc4_hdmi->mutex);
121
122 if (!display->is_hdmi)
123 return false;
124
125 if (!display->hdmi.scdc.supported ||
126 !display->hdmi.scdc.scrambling.supported)
127 return false;
128
129 return true;
130 }
131
vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode * mode,unsigned int bpc,enum hdmi_colorspace fmt)132 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
133 unsigned int bpc,
134 enum hdmi_colorspace fmt)
135 {
136 unsigned long long clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt);
137
138 return clock > HDMI_14_MAX_TMDS_CLK;
139 }
140
vc4_hdmi_debugfs_regs(struct seq_file * m,void * unused)141 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
142 {
143 struct drm_debugfs_entry *entry = m->private;
144 struct vc4_hdmi *vc4_hdmi = entry->file.data;
145 struct drm_device *drm = vc4_hdmi->connector.dev;
146 struct drm_printer p = drm_seq_file_printer(m);
147 int idx;
148
149 if (!drm_dev_enter(drm, &idx))
150 return -ENODEV;
151
152 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
153
154 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
155 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
156 drm_print_regset32(&p, &vc4_hdmi->cec_regset);
157 drm_print_regset32(&p, &vc4_hdmi->csc_regset);
158 drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
159 drm_print_regset32(&p, &vc4_hdmi->phy_regset);
160 drm_print_regset32(&p, &vc4_hdmi->ram_regset);
161 drm_print_regset32(&p, &vc4_hdmi->rm_regset);
162
163 pm_runtime_put(&vc4_hdmi->pdev->dev);
164
165 drm_dev_exit(idx);
166
167 return 0;
168 }
169
vc4_hdmi_reset(struct vc4_hdmi * vc4_hdmi)170 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
171 {
172 struct drm_device *drm = vc4_hdmi->connector.dev;
173 unsigned long flags;
174 int idx;
175
176 /*
177 * We can be called by our bind callback, when the
178 * connector->dev pointer might not be initialised yet.
179 */
180 if (drm && !drm_dev_enter(drm, &idx))
181 return;
182
183 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
184
185 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
186 udelay(1);
187 HDMI_WRITE(HDMI_M_CTL, 0);
188
189 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
190
191 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
192 VC4_HDMI_SW_RESET_HDMI |
193 VC4_HDMI_SW_RESET_FORMAT_DETECT);
194
195 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
196
197 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
198
199 if (drm)
200 drm_dev_exit(idx);
201 }
202
vc5_hdmi_reset(struct vc4_hdmi * vc4_hdmi)203 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
204 {
205 struct drm_device *drm = vc4_hdmi->connector.dev;
206 unsigned long flags;
207 int idx;
208
209 /*
210 * We can be called by our bind callback, when the
211 * connector->dev pointer might not be initialised yet.
212 */
213 if (drm && !drm_dev_enter(drm, &idx))
214 return;
215
216 reset_control_reset(vc4_hdmi->reset);
217
218 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
219
220 HDMI_WRITE(HDMI_DVP_CTL, 0);
221
222 HDMI_WRITE(HDMI_CLOCK_STOP,
223 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
224
225 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
226
227 if (drm)
228 drm_dev_exit(idx);
229 }
230
231 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)232 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
233 {
234 struct drm_device *drm = vc4_hdmi->connector.dev;
235 unsigned long cec_rate;
236 unsigned long flags;
237 u16 clk_cnt;
238 u32 value;
239 int idx;
240
241 /*
242 * This function is called by our runtime_resume implementation
243 * and thus at bind time, when we haven't registered our
244 * connector yet and thus don't have a pointer to the DRM
245 * device.
246 */
247 if (drm && !drm_dev_enter(drm, &idx))
248 return;
249
250 cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
251
252 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
253
254 value = HDMI_READ(HDMI_CEC_CNTRL_1);
255 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
256
257 /*
258 * Set the clock divider: the hsm_clock rate and this divider
259 * setting will give a 40 kHz CEC clock.
260 */
261 clk_cnt = cec_rate / CEC_CLOCK_FREQ;
262 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
263 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
264
265 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
266
267 if (drm)
268 drm_dev_exit(idx);
269 }
270 #else
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)271 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
272 #endif
273
vc4_hdmi_reset_link(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx)274 static int vc4_hdmi_reset_link(struct drm_connector *connector,
275 struct drm_modeset_acquire_ctx *ctx)
276 {
277 struct drm_device *drm;
278 struct vc4_hdmi *vc4_hdmi;
279 struct drm_connector_state *conn_state;
280 struct drm_crtc_state *crtc_state;
281 struct drm_crtc *crtc;
282 bool scrambling_needed;
283 u8 config;
284 int ret;
285
286 if (!connector)
287 return 0;
288
289 drm = connector->dev;
290 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
291 if (ret)
292 return ret;
293
294 conn_state = connector->state;
295 crtc = conn_state->crtc;
296 if (!crtc)
297 return 0;
298
299 ret = drm_modeset_lock(&crtc->mutex, ctx);
300 if (ret)
301 return ret;
302
303 crtc_state = crtc->state;
304 if (!crtc_state->active)
305 return 0;
306
307 vc4_hdmi = connector_to_vc4_hdmi(connector);
308 mutex_lock(&vc4_hdmi->mutex);
309
310 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
311 mutex_unlock(&vc4_hdmi->mutex);
312 return 0;
313 }
314
315 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
316 vc4_hdmi->output_bpc,
317 vc4_hdmi->output_format);
318 if (!scrambling_needed) {
319 mutex_unlock(&vc4_hdmi->mutex);
320 return 0;
321 }
322
323 if (conn_state->commit &&
324 !try_wait_for_completion(&conn_state->commit->hw_done)) {
325 mutex_unlock(&vc4_hdmi->mutex);
326 return 0;
327 }
328
329 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
330 if (ret < 0) {
331 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
332 mutex_unlock(&vc4_hdmi->mutex);
333 return 0;
334 }
335
336 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
337 mutex_unlock(&vc4_hdmi->mutex);
338 return 0;
339 }
340
341 mutex_unlock(&vc4_hdmi->mutex);
342
343 /*
344 * HDMI 2.0 says that one should not send scrambled data
345 * prior to configuring the sink scrambling, and that
346 * TMDS clock/data transmission should be suspended when
347 * changing the TMDS clock rate in the sink. So let's
348 * just do a full modeset here, even though some sinks
349 * would be perfectly happy if were to just reconfigure
350 * the SCDC settings on the fly.
351 */
352 return drm_atomic_helper_reset_crtc(crtc, ctx);
353 }
354
vc4_hdmi_handle_hotplug(struct vc4_hdmi * vc4_hdmi,struct drm_modeset_acquire_ctx * ctx,enum drm_connector_status status)355 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
356 struct drm_modeset_acquire_ctx *ctx,
357 enum drm_connector_status status)
358 {
359 struct drm_connector *connector = &vc4_hdmi->connector;
360 int ret;
361
362 /*
363 * NOTE: This function should really be called with vc4_hdmi->mutex
364 * held, but doing so results in reentrancy issues since
365 * cec_s_phys_addr() might call .adap_enable, which leads to that
366 * funtion being called with our mutex held.
367 *
368 * A similar situation occurs with vc4_hdmi_reset_link() that
369 * will call into our KMS hooks if the scrambling was enabled.
370 *
371 * Concurrency isn't an issue at the moment since we don't share
372 * any state with any of the other frameworks so we can ignore
373 * the lock for now.
374 */
375
376 drm_atomic_helper_connector_hdmi_hotplug(connector, status);
377
378 if (status == connector_status_disconnected) {
379 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
380 return;
381 }
382
383 cec_s_phys_addr(vc4_hdmi->cec_adap,
384 connector->display_info.source_physical_address, false);
385
386 if (status != connector_status_connected)
387 return;
388
389 for (;;) {
390 ret = vc4_hdmi_reset_link(connector, ctx);
391 if (ret == -EDEADLK) {
392 drm_modeset_backoff(ctx);
393 continue;
394 }
395
396 break;
397 }
398 }
399
vc4_hdmi_connector_detect_ctx(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)400 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
401 struct drm_modeset_acquire_ctx *ctx,
402 bool force)
403 {
404 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
405 enum drm_connector_status status = connector_status_disconnected;
406 int ret;
407
408 /*
409 * NOTE: This function should really take vc4_hdmi->mutex, but
410 * doing so results in reentrancy issues since
411 * vc4_hdmi_handle_hotplug() can call into other functions that
412 * would take the mutex while it's held here.
413 *
414 * Concurrency isn't an issue at the moment since we don't share
415 * any state with any of the other frameworks so we can ignore
416 * the lock for now.
417 */
418
419 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
420 if (ret) {
421 drm_err_once(connector->dev, "Failed to retain HDMI power domain: %d\n",
422 ret);
423 return connector_status_unknown;
424 }
425
426 if (vc4_hdmi->hpd_gpio) {
427 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
428 status = connector_status_connected;
429 } else {
430 if (vc4_hdmi->variant->hp_detect &&
431 vc4_hdmi->variant->hp_detect(vc4_hdmi))
432 status = connector_status_connected;
433 }
434
435 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
436 pm_runtime_put(&vc4_hdmi->pdev->dev);
437
438 return status;
439 }
440
vc4_hdmi_connector_get_modes(struct drm_connector * connector)441 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
442 {
443 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
444 int ret = 0;
445
446 ret = drm_edid_connector_add_modes(connector);
447
448 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
449 struct drm_device *drm = connector->dev;
450 const struct drm_display_mode *mode;
451
452 list_for_each_entry(mode, &connector->probed_modes, head) {
453 if (vc4_hdmi_mode_needs_scrambling(mode, 8, HDMI_COLORSPACE_RGB)) {
454 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
455 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
456 }
457 }
458 }
459
460 return ret;
461 }
462
vc4_hdmi_connector_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)463 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
464 struct drm_atomic_state *state)
465 {
466 struct drm_connector_state *old_state =
467 drm_atomic_get_old_connector_state(state, connector);
468 struct drm_connector_state *new_state =
469 drm_atomic_get_new_connector_state(state, connector);
470 struct drm_crtc *crtc = new_state->crtc;
471
472 if (!crtc)
473 return 0;
474
475 if (old_state->tv.margins.left != new_state->tv.margins.left ||
476 old_state->tv.margins.right != new_state->tv.margins.right ||
477 old_state->tv.margins.top != new_state->tv.margins.top ||
478 old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
479 struct drm_crtc_state *crtc_state;
480 int ret;
481
482 crtc_state = drm_atomic_get_crtc_state(state, crtc);
483 if (IS_ERR(crtc_state))
484 return PTR_ERR(crtc_state);
485
486 /*
487 * Strictly speaking, we should be calling
488 * drm_atomic_helper_check_planes() after our call to
489 * drm_atomic_add_affected_planes(). However, the
490 * connector atomic_check is called as part of
491 * drm_atomic_helper_check_modeset() that already
492 * happens before a call to
493 * drm_atomic_helper_check_planes() in
494 * drm_atomic_helper_check().
495 */
496 ret = drm_atomic_add_affected_planes(state, crtc);
497 if (ret)
498 return ret;
499 }
500
501 if (old_state->colorspace != new_state->colorspace) {
502 struct drm_crtc_state *crtc_state;
503
504 crtc_state = drm_atomic_get_crtc_state(state, crtc);
505 if (IS_ERR(crtc_state))
506 return PTR_ERR(crtc_state);
507
508 crtc_state->mode_changed = true;
509 }
510
511 return drm_atomic_helper_connector_hdmi_check(connector, state);
512 }
513
vc4_hdmi_connector_reset(struct drm_connector * connector)514 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
515 {
516 drm_atomic_helper_connector_reset(connector);
517 __drm_atomic_helper_connector_hdmi_reset(connector, connector->state);
518 drm_atomic_helper_connector_tv_margins_reset(connector);
519 }
520
521 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
522 .force = drm_atomic_helper_connector_hdmi_force,
523 .fill_modes = drm_helper_probe_single_connector_modes,
524 .reset = vc4_hdmi_connector_reset,
525 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
526 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
527 };
528
529 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
530 .detect_ctx = vc4_hdmi_connector_detect_ctx,
531 .get_modes = vc4_hdmi_connector_get_modes,
532 .atomic_check = vc4_hdmi_connector_atomic_check,
533 .mode_valid = drm_hdmi_connector_mode_valid,
534 };
535
536 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs;
537 static const struct drm_connector_hdmi_audio_funcs vc4_hdmi_audio_funcs;
538
vc4_hdmi_connector_init(struct drm_device * dev,struct vc4_hdmi * vc4_hdmi)539 static int vc4_hdmi_connector_init(struct drm_device *dev,
540 struct vc4_hdmi *vc4_hdmi)
541 {
542 struct drm_connector *connector = &vc4_hdmi->connector;
543 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
544 unsigned int max_bpc = 8;
545 int ret;
546
547 if (vc4_hdmi->variant->supports_hdr)
548 max_bpc = 12;
549
550 ret = drmm_connector_hdmi_init(dev, connector,
551 "Broadcom", "Videocore",
552 &vc4_hdmi_connector_funcs,
553 &vc4_hdmi_hdmi_connector_funcs,
554 DRM_MODE_CONNECTOR_HDMIA,
555 vc4_hdmi->ddc,
556 BIT(HDMI_COLORSPACE_RGB) |
557 BIT(HDMI_COLORSPACE_YUV422) |
558 BIT(HDMI_COLORSPACE_YUV444),
559 max_bpc);
560 if (ret)
561 return ret;
562
563 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
564
565 /*
566 * Some of the properties below require access to state, like bpc.
567 * Allocate some default initial connector state with our reset helper.
568 */
569 if (connector->funcs->reset)
570 connector->funcs->reset(connector);
571
572 /* Create and attach TV margin props to this connector. */
573 ret = drm_mode_create_tv_margin_properties(dev);
574 if (ret)
575 return ret;
576
577 ret = drm_mode_create_hdmi_colorspace_property(connector, 0);
578 if (ret)
579 return ret;
580
581 drm_connector_attach_colorspace_property(connector);
582 drm_connector_attach_tv_margin_properties(connector);
583
584 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
585 DRM_CONNECTOR_POLL_DISCONNECT);
586
587 connector->interlace_allowed = 1;
588 connector->doublescan_allowed = 0;
589 connector->stereo_allowed = 1;
590
591 ret = drm_connector_attach_broadcast_rgb_property(connector);
592 if (ret)
593 return ret;
594
595 drm_connector_attach_encoder(connector, encoder);
596
597 return 0;
598 }
599
vc4_hdmi_stop_packet(struct vc4_hdmi * vc4_hdmi,enum hdmi_infoframe_type type,bool poll)600 static int vc4_hdmi_stop_packet(struct vc4_hdmi *vc4_hdmi,
601 enum hdmi_infoframe_type type,
602 bool poll)
603 {
604 struct drm_device *drm = vc4_hdmi->connector.dev;
605 u32 packet_id = type - 0x80;
606 unsigned long flags;
607 int ret = 0;
608 int idx;
609
610 if (!drm_dev_enter(drm, &idx))
611 return -ENODEV;
612
613 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
614 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
615 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
616 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
617
618 if (poll) {
619 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
620 BIT(packet_id)), 100);
621 }
622
623 drm_dev_exit(idx);
624 return ret;
625 }
626
vc4_hdmi_write_infoframe(struct drm_connector * connector,enum hdmi_infoframe_type type,const u8 * infoframe,size_t len)627 static int vc4_hdmi_write_infoframe(struct drm_connector *connector,
628 enum hdmi_infoframe_type type,
629 const u8 *infoframe, size_t len)
630 {
631 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
632 struct drm_device *drm = connector->dev;
633 u32 packet_id = type - 0x80;
634 const struct vc4_hdmi_register *ram_packet_start =
635 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
636 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
637 u32 packet_reg_next = ram_packet_start->offset +
638 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
639 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
640 ram_packet_start->reg);
641 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
642 unsigned long flags;
643 ssize_t i;
644 int ret;
645 int idx;
646
647 if (!drm_dev_enter(drm, &idx))
648 return 0;
649
650 if (len > sizeof(buffer)) {
651 ret = -ENOMEM;
652 goto out;
653 }
654
655 memcpy(buffer, infoframe, len);
656
657 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
658 VC4_HDMI_RAM_PACKET_ENABLE),
659 "Packet RAM has to be on to store the packet.");
660
661 ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true);
662 if (ret) {
663 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret);
664 goto out;
665 }
666
667 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
668
669 for (i = 0; i < len; i += 7) {
670 writel(buffer[i + 0] << 0 |
671 buffer[i + 1] << 8 |
672 buffer[i + 2] << 16,
673 base + packet_reg);
674 packet_reg += 4;
675
676 writel(buffer[i + 3] << 0 |
677 buffer[i + 4] << 8 |
678 buffer[i + 5] << 16 |
679 buffer[i + 6] << 24,
680 base + packet_reg);
681 packet_reg += 4;
682 }
683
684 /*
685 * clear remainder of packet ram as it's included in the
686 * infoframe and triggers a checksum error on hdmi analyser
687 */
688 for (; packet_reg < packet_reg_next; packet_reg += 4)
689 writel(0, base + packet_reg);
690
691 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
692 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
693
694 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
695
696 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
697 BIT(packet_id)), 100);
698 if (ret)
699 drm_err(drm, "Failed to wait for infoframe to start: %d\n", ret);
700
701 out:
702 drm_dev_exit(idx);
703 return ret;
704 }
705
706 #define SCRAMBLING_POLLING_DELAY_MS 1000
707
vc4_hdmi_enable_scrambling(struct drm_encoder * encoder)708 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
709 {
710 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
711 struct drm_connector *connector = &vc4_hdmi->connector;
712 struct drm_device *drm = connector->dev;
713 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
714 unsigned long flags;
715 int idx;
716
717 lockdep_assert_held(&vc4_hdmi->mutex);
718
719 if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
720 return;
721
722 if (!vc4_hdmi_mode_needs_scrambling(mode,
723 vc4_hdmi->output_bpc,
724 vc4_hdmi->output_format))
725 return;
726
727 if (!drm_dev_enter(drm, &idx))
728 return;
729
730 drm_scdc_set_high_tmds_clock_ratio(connector, true);
731 drm_scdc_set_scrambling(connector, true);
732
733 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
734 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
735 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
736 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
737
738 drm_dev_exit(idx);
739
740 vc4_hdmi->scdc_enabled = true;
741
742 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
743 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
744 }
745
vc4_hdmi_disable_scrambling(struct drm_encoder * encoder)746 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
747 {
748 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
749 struct drm_connector *connector = &vc4_hdmi->connector;
750 struct drm_device *drm = connector->dev;
751 unsigned long flags;
752 int idx;
753
754 lockdep_assert_held(&vc4_hdmi->mutex);
755
756 if (!vc4_hdmi->scdc_enabled)
757 return;
758
759 vc4_hdmi->scdc_enabled = false;
760
761 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
762 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
763
764 if (!drm_dev_enter(drm, &idx))
765 return;
766
767 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
768 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
769 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
770 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
771
772 drm_scdc_set_scrambling(connector, false);
773 drm_scdc_set_high_tmds_clock_ratio(connector, false);
774
775 drm_dev_exit(idx);
776 }
777
vc4_hdmi_scrambling_wq(struct work_struct * work)778 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
779 {
780 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
781 struct vc4_hdmi,
782 scrambling_work);
783 struct drm_connector *connector = &vc4_hdmi->connector;
784
785 if (drm_scdc_get_scrambling_status(connector))
786 return;
787
788 drm_scdc_set_high_tmds_clock_ratio(connector, true);
789 drm_scdc_set_scrambling(connector, true);
790
791 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
792 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
793 }
794
vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)795 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
796 struct drm_atomic_state *state)
797 {
798 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
799 struct drm_device *drm = vc4_hdmi->connector.dev;
800 struct vc4_dev *vc4 = to_vc4_dev(drm);
801 unsigned long flags;
802 int idx;
803
804 mutex_lock(&vc4_hdmi->mutex);
805
806 vc4_hdmi->packet_ram_enabled = false;
807
808 if (!drm_dev_enter(drm, &idx))
809 goto out;
810
811 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
812
813 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
814
815 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
816
817 if (vc4->gen >= VC4_GEN_6_C)
818 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
819 VC4_HD_VID_CTL_BLANKPIX);
820
821 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
822
823 mdelay(1);
824
825 /*
826 * TODO: This should work on BCM2712, but doesn't for some
827 * reason and result in a system lockup.
828 */
829 if (vc4->gen < VC4_GEN_6_C) {
830 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
831 HDMI_WRITE(HDMI_VID_CTL,
832 HDMI_READ(HDMI_VID_CTL) &
833 ~VC4_HD_VID_CTL_ENABLE);
834 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
835 }
836
837 vc4_hdmi_disable_scrambling(encoder);
838
839 drm_dev_exit(idx);
840
841 out:
842 mutex_unlock(&vc4_hdmi->mutex);
843 }
844
vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder * encoder,struct drm_atomic_state * state)845 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
846 struct drm_atomic_state *state)
847 {
848 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
849 struct drm_device *drm = vc4_hdmi->connector.dev;
850 unsigned long flags;
851 int ret;
852 int idx;
853
854 mutex_lock(&vc4_hdmi->mutex);
855
856 if (!drm_dev_enter(drm, &idx))
857 goto out;
858
859 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
860 HDMI_WRITE(HDMI_VID_CTL,
861 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
862 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
863
864 if (vc4_hdmi->variant->phy_disable)
865 vc4_hdmi->variant->phy_disable(vc4_hdmi);
866
867 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
868 clk_disable_unprepare(vc4_hdmi->pixel_clock);
869
870 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
871 if (ret < 0)
872 drm_err(drm, "Failed to release power domain: %d\n", ret);
873
874 drm_dev_exit(idx);
875
876 out:
877 mutex_unlock(&vc4_hdmi->mutex);
878 }
879
vc4_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)880 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
881 struct drm_connector_state *state,
882 const struct drm_display_mode *mode)
883 {
884 struct drm_device *drm = vc4_hdmi->connector.dev;
885 unsigned long flags;
886 u32 csc_ctl;
887 int idx;
888
889 if (!drm_dev_enter(drm, &idx))
890 return;
891
892 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
893
894 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
895 VC4_HD_CSC_CTL_ORDER);
896
897 if (state->hdmi.is_limited_range) {
898 /* CEA VICs other than #1 requre limited range RGB
899 * output unless overridden by an AVI infoframe.
900 * Apply a colorspace conversion to squash 0-255 down
901 * to 16-235. The matrix here is:
902 *
903 * [ 0 0 0.8594 16]
904 * [ 0 0.8594 0 16]
905 * [ 0.8594 0 0 16]
906 * [ 0 0 0 1]
907 */
908 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
909 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
910 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
911 VC4_HD_CSC_CTL_MODE);
912
913 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
914 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
915 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
916 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
917 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
918 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
919 }
920
921 /* The RGB order applies even when CSC is disabled. */
922 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
923
924 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
925
926 drm_dev_exit(idx);
927 }
928
929 /*
930 * Matrices for (internal) RGB to RGB output.
931 *
932 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
933 */
934 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = {
935 {
936 /*
937 * Full range - unity
938 *
939 * [ 1 0 0 0]
940 * [ 0 1 0 0]
941 * [ 0 0 1 0]
942 */
943 { 0x2000, 0x0000, 0x0000, 0x0000 },
944 { 0x0000, 0x2000, 0x0000, 0x0000 },
945 { 0x0000, 0x0000, 0x2000, 0x0000 },
946 },
947 {
948 /*
949 * Limited range
950 *
951 * CEA VICs other than #1 require limited range RGB
952 * output unless overridden by an AVI infoframe. Apply a
953 * colorspace conversion to squash 0-255 down to 16-235.
954 * The matrix here is:
955 *
956 * [ 0.8594 0 0 16]
957 * [ 0 0.8594 0 16]
958 * [ 0 0 0.8594 16]
959 */
960 { 0x1b80, 0x0000, 0x0000, 0x0400 },
961 { 0x0000, 0x1b80, 0x0000, 0x0400 },
962 { 0x0000, 0x0000, 0x1b80, 0x0400 },
963 },
964 };
965
966 /*
967 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace
968 *
969 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
970 */
971 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = {
972 {
973 /*
974 * Full Range
975 *
976 * [ 0.299000 0.587000 0.114000 0 ]
977 * [ -0.168736 -0.331264 0.500000 128 ]
978 * [ 0.500000 -0.418688 -0.081312 128 ]
979 */
980 { 0x0991, 0x12c9, 0x03a6, 0x0000 },
981 { 0xfa9b, 0xf567, 0x1000, 0x2000 },
982 { 0x1000, 0xf29b, 0xfd67, 0x2000 },
983 },
984 {
985 /* Limited Range
986 *
987 * [ 0.255785 0.502160 0.097523 16 ]
988 * [ -0.147644 -0.289856 0.437500 128 ]
989 * [ 0.437500 -0.366352 -0.071148 128 ]
990 */
991 { 0x082f, 0x1012, 0x031f, 0x0400 },
992 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
993 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
994 },
995 };
996
997 /*
998 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace
999 *
1000 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1001 */
1002 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = {
1003 {
1004 /*
1005 * Full Range
1006 *
1007 * [ 0.212600 0.715200 0.072200 0 ]
1008 * [ -0.114572 -0.385428 0.500000 128 ]
1009 * [ 0.500000 -0.454153 -0.045847 128 ]
1010 */
1011 { 0x06ce, 0x16e3, 0x024f, 0x0000 },
1012 { 0xfc56, 0xf3ac, 0x1000, 0x2000 },
1013 { 0x1000, 0xf179, 0xfe89, 0x2000 },
1014 },
1015 {
1016 /*
1017 * Limited Range
1018 *
1019 * [ 0.181906 0.611804 0.061758 16 ]
1020 * [ -0.100268 -0.337232 0.437500 128 ]
1021 * [ 0.437500 -0.397386 -0.040114 128 ]
1022 */
1023 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1024 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1025 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1026 },
1027 };
1028
1029 /*
1030 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace
1031 *
1032 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1033 */
1034 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = {
1035 {
1036 /*
1037 * Full Range
1038 *
1039 * [ 0.262700 0.678000 0.059300 0 ]
1040 * [ -0.139630 -0.360370 0.500000 128 ]
1041 * [ 0.500000 -0.459786 -0.040214 128 ]
1042 */
1043 { 0x0868, 0x15b2, 0x01e6, 0x0000 },
1044 { 0xfb89, 0xf479, 0x1000, 0x2000 },
1045 { 0x1000, 0xf14a, 0xfeb8, 0x2000 },
1046 },
1047 {
1048 /* Limited Range
1049 *
1050 * [ 0.224732 0.580008 0.050729 16 ]
1051 * [ -0.122176 -0.315324 0.437500 128 ]
1052 * [ 0.437500 -0.402312 -0.035188 128 ]
1053 */
1054 { 0x082f, 0x1012, 0x031f, 0x0400 },
1055 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1056 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1057 },
1058 };
1059
vc5_hdmi_set_csc_coeffs(struct vc4_hdmi * vc4_hdmi,const u16 coeffs[3][4])1060 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1061 const u16 coeffs[3][4])
1062 {
1063 lockdep_assert_held(&vc4_hdmi->hw_lock);
1064
1065 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1066 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1067 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1068 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1069 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1070 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1071 }
1072
vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi * vc4_hdmi,const u16 coeffs[3][4])1073 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi,
1074 const u16 coeffs[3][4])
1075 {
1076 lockdep_assert_held(&vc4_hdmi->hw_lock);
1077
1078 /* YUV444 needs the CSC matrices using the channels in a different order */
1079 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]);
1080 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]);
1081 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]);
1082 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]);
1083 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]);
1084 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]);
1085 }
1086
1087 static const u16
vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi * vc4_hdmi,u32 colorspace,bool limited)1088 (*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4]
1089 {
1090 switch (colorspace) {
1091 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC:
1092 case DRM_MODE_COLORIMETRY_XVYCC_601:
1093 case DRM_MODE_COLORIMETRY_SYCC_601:
1094 case DRM_MODE_COLORIMETRY_OPYCC_601:
1095 case DRM_MODE_COLORIMETRY_BT601_YCC:
1096 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited];
1097
1098 default:
1099 case DRM_MODE_COLORIMETRY_NO_DATA:
1100 case DRM_MODE_COLORIMETRY_BT709_YCC:
1101 case DRM_MODE_COLORIMETRY_XVYCC_709:
1102 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED:
1103 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT:
1104 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited];
1105
1106 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1107 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1108 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1109 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1110 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1111 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited];
1112 }
1113 }
1114
vc5_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)1115 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1116 struct drm_connector_state *state,
1117 const struct drm_display_mode *mode)
1118 {
1119 struct drm_device *drm = vc4_hdmi->connector.dev;
1120 unsigned int lim_range = state->hdmi.is_limited_range ? 1 : 0;
1121 unsigned long flags;
1122 const u16 (*csc)[4];
1123 u32 if_cfg = 0;
1124 u32 if_xbar = 0x543210;
1125 u32 csc_chan_ctl = 0;
1126 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1127 VC5_MT_CP_CSC_CTL_MODE);
1128 int idx;
1129
1130 if (!drm_dev_enter(drm, &idx))
1131 return;
1132
1133 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1134
1135 switch (state->hdmi.output_format) {
1136 case HDMI_COLORSPACE_YUV444:
1137 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1138
1139 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc);
1140 break;
1141
1142 case HDMI_COLORSPACE_YUV422:
1143 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1144
1145 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1146 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1147 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1148 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1149
1150 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1151 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1152
1153 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1154 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1155
1156 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc);
1157 break;
1158
1159 case HDMI_COLORSPACE_RGB:
1160 if_xbar = 0x354021;
1161
1162 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]);
1163 break;
1164
1165 default:
1166 break;
1167 }
1168
1169 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1170 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1171 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1172 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1173
1174 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1175
1176 drm_dev_exit(idx);
1177 }
1178
vc4_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)1179 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1180 struct drm_connector_state *state,
1181 const struct drm_display_mode *mode)
1182 {
1183 struct drm_device *drm = vc4_hdmi->connector.dev;
1184 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1185 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1186 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1187 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1188 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1189 VC4_HDMI_VERTA_VSP) |
1190 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1191 VC4_HDMI_VERTA_VFP) |
1192 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1193 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1194 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1195 interlaced,
1196 VC4_HDMI_VERTB_VBP));
1197 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1198 VC4_SET_FIELD(mode->crtc_vtotal -
1199 mode->crtc_vsync_end,
1200 VC4_HDMI_VERTB_VBP));
1201 unsigned long flags;
1202 u32 reg;
1203 int idx;
1204
1205 if (!drm_dev_enter(drm, &idx))
1206 return;
1207
1208 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1209
1210 HDMI_WRITE(HDMI_HORZA,
1211 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1212 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1213 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1214 VC4_HDMI_HORZA_HAP));
1215
1216 HDMI_WRITE(HDMI_HORZB,
1217 VC4_SET_FIELD((mode->htotal -
1218 mode->hsync_end) * pixel_rep,
1219 VC4_HDMI_HORZB_HBP) |
1220 VC4_SET_FIELD((mode->hsync_end -
1221 mode->hsync_start) * pixel_rep,
1222 VC4_HDMI_HORZB_HSP) |
1223 VC4_SET_FIELD((mode->hsync_start -
1224 mode->hdisplay) * pixel_rep,
1225 VC4_HDMI_HORZB_HFP));
1226
1227 HDMI_WRITE(HDMI_VERTA0, verta);
1228 HDMI_WRITE(HDMI_VERTA1, verta);
1229
1230 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1231 HDMI_WRITE(HDMI_VERTB1, vertb);
1232
1233 reg = HDMI_READ(HDMI_MISC_CONTROL);
1234 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1235 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1236 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1237
1238 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1239
1240 drm_dev_exit(idx);
1241 }
1242
vc5_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)1243 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1244 struct drm_connector_state *state,
1245 const struct drm_display_mode *mode)
1246 {
1247 struct drm_device *drm = vc4_hdmi->connector.dev;
1248 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1249 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1250 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1251 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1252 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1253 VC5_HDMI_VERTA_VSP) |
1254 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1255 VC5_HDMI_VERTA_VFP) |
1256 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1257 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1258 VC5_HDMI_VERTB_VSPO) |
1259 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1260 interlaced,
1261 VC4_HDMI_VERTB_VBP));
1262 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1263 VC4_SET_FIELD(mode->crtc_vtotal -
1264 mode->crtc_vsync_end,
1265 VC4_HDMI_VERTB_VBP));
1266 unsigned long flags;
1267 unsigned char gcp;
1268 u32 reg;
1269 int idx;
1270
1271 if (!drm_dev_enter(drm, &idx))
1272 return;
1273
1274 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1275
1276 HDMI_WRITE(HDMI_HORZA,
1277 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1278 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1279 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1280 VC5_HDMI_HORZA_HAP) |
1281 VC4_SET_FIELD((mode->hsync_start -
1282 mode->hdisplay) * pixel_rep,
1283 VC5_HDMI_HORZA_HFP));
1284
1285 HDMI_WRITE(HDMI_HORZB,
1286 VC4_SET_FIELD((mode->htotal -
1287 mode->hsync_end) * pixel_rep,
1288 VC5_HDMI_HORZB_HBP) |
1289 VC4_SET_FIELD((mode->hsync_end -
1290 mode->hsync_start) * pixel_rep,
1291 VC5_HDMI_HORZB_HSP));
1292
1293 HDMI_WRITE(HDMI_VERTA0, verta);
1294 HDMI_WRITE(HDMI_VERTA1, verta);
1295
1296 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1297 HDMI_WRITE(HDMI_VERTB1, vertb);
1298
1299 switch (state->hdmi.output_bpc) {
1300 case 12:
1301 gcp = 6;
1302 break;
1303 case 10:
1304 gcp = 5;
1305 break;
1306 case 8:
1307 default:
1308 gcp = 0;
1309 break;
1310 }
1311
1312 /*
1313 * YCC422 is always 36-bit and not considered deep colour so
1314 * doesn't signal in GCP.
1315 */
1316 if (state->hdmi.output_format == HDMI_COLORSPACE_YUV422) {
1317 gcp = 0;
1318 }
1319
1320 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1321 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1322 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1323 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1324 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1325 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1326
1327 reg = HDMI_READ(HDMI_GCP_WORD_1);
1328 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1329 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1330 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;
1331 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;
1332 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1333
1334 reg = HDMI_READ(HDMI_GCP_CONFIG);
1335 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1336 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1337
1338 reg = HDMI_READ(HDMI_MISC_CONTROL);
1339 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1340 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1341 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1342
1343 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1344
1345 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1346
1347 drm_dev_exit(idx);
1348 }
1349
vc4_hdmi_recenter_fifo(struct vc4_hdmi * vc4_hdmi)1350 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1351 {
1352 struct drm_device *drm = vc4_hdmi->connector.dev;
1353 unsigned long flags;
1354 u32 drift;
1355 int ret;
1356 int idx;
1357
1358 if (!drm_dev_enter(drm, &idx))
1359 return;
1360
1361 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1362
1363 drift = HDMI_READ(HDMI_FIFO_CTL);
1364 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1365
1366 HDMI_WRITE(HDMI_FIFO_CTL,
1367 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1368 HDMI_WRITE(HDMI_FIFO_CTL,
1369 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1370
1371 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1372
1373 usleep_range(1000, 1100);
1374
1375 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1376
1377 HDMI_WRITE(HDMI_FIFO_CTL,
1378 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1379 HDMI_WRITE(HDMI_FIFO_CTL,
1380 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1381
1382 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1383
1384 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1385 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1386 WARN_ONCE(ret, "Timeout waiting for "
1387 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1388
1389 drm_dev_exit(idx);
1390 }
1391
vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder * encoder,struct drm_atomic_state * state)1392 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1393 struct drm_atomic_state *state)
1394 {
1395 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1396 struct drm_device *drm = vc4_hdmi->connector.dev;
1397 struct drm_connector *connector = &vc4_hdmi->connector;
1398 struct drm_connector_state *conn_state =
1399 drm_atomic_get_new_connector_state(state, connector);
1400 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1401 unsigned long long tmds_char_rate = conn_state->hdmi.tmds_char_rate;
1402 unsigned long bvb_rate, hsm_rate;
1403 unsigned long flags;
1404 int ret;
1405 int idx;
1406
1407 mutex_lock(&vc4_hdmi->mutex);
1408
1409 if (!drm_dev_enter(drm, &idx))
1410 goto out;
1411
1412 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1413 if (ret < 0) {
1414 drm_err(drm, "Failed to retain power domain: %d\n", ret);
1415 goto err_dev_exit;
1416 }
1417
1418 /*
1419 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1420 * be faster than pixel clock, infinitesimally faster, tested in
1421 * simulation. Otherwise, exact value is unimportant for HDMI
1422 * operation." This conflicts with bcm2835's vc4 documentation, which
1423 * states HSM's clock has to be at least 108% of the pixel clock.
1424 *
1425 * Real life tests reveal that vc4's firmware statement holds up, and
1426 * users are able to use pixel clocks closer to HSM's, namely for
1427 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1428 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1429 * 162MHz.
1430 *
1431 * Additionally, the AXI clock needs to be at least 25% of
1432 * pixel clock, but HSM ends up being the limiting factor.
1433 */
1434 hsm_rate = max_t(unsigned long,
1435 HSM_MIN_CLOCK_FREQ,
1436 div_u64(tmds_char_rate, 100) * 101);
1437 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1438 if (ret) {
1439 drm_err(drm, "Failed to set HSM clock rate: %d\n", ret);
1440 goto err_put_runtime_pm;
1441 }
1442
1443 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1444 if (ret) {
1445 drm_err(drm, "Failed to set pixel clock rate: %d\n", ret);
1446 goto err_put_runtime_pm;
1447 }
1448
1449 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1450 if (ret) {
1451 drm_err(drm, "Failed to turn on pixel clock: %d\n", ret);
1452 goto err_put_runtime_pm;
1453 }
1454
1455 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1456
1457 if (tmds_char_rate > 297000000)
1458 bvb_rate = 300000000;
1459 else if (tmds_char_rate > 148500000)
1460 bvb_rate = 150000000;
1461 else
1462 bvb_rate = 75000000;
1463
1464 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1465 if (ret) {
1466 drm_err(drm, "Failed to set pixel bvb clock rate: %d\n", ret);
1467 goto err_disable_pixel_clock;
1468 }
1469
1470 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1471 if (ret) {
1472 drm_err(drm, "Failed to turn on pixel bvb clock: %d\n", ret);
1473 goto err_disable_pixel_clock;
1474 }
1475
1476 if (vc4_hdmi->variant->phy_init)
1477 vc4_hdmi->variant->phy_init(vc4_hdmi, conn_state);
1478
1479 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1480
1481 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1482 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1483 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1484 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1485
1486 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1487
1488 if (vc4_hdmi->variant->set_timings)
1489 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1490
1491 drm_dev_exit(idx);
1492
1493 mutex_unlock(&vc4_hdmi->mutex);
1494
1495 return;
1496
1497 err_disable_pixel_clock:
1498 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1499 err_put_runtime_pm:
1500 pm_runtime_put(&vc4_hdmi->pdev->dev);
1501 err_dev_exit:
1502 drm_dev_exit(idx);
1503 out:
1504 mutex_unlock(&vc4_hdmi->mutex);
1505 return;
1506 }
1507
vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1508 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1509 struct drm_atomic_state *state)
1510 {
1511 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1512 struct drm_device *drm = vc4_hdmi->connector.dev;
1513 struct drm_connector *connector = &vc4_hdmi->connector;
1514 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1515 struct drm_connector_state *conn_state =
1516 drm_atomic_get_new_connector_state(state, connector);
1517 unsigned long flags;
1518 int idx;
1519
1520 mutex_lock(&vc4_hdmi->mutex);
1521
1522 if (!drm_dev_enter(drm, &idx))
1523 goto out;
1524
1525 if (vc4_hdmi->variant->csc_setup)
1526 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1527
1528 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1529 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1530 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1531
1532 drm_dev_exit(idx);
1533
1534 out:
1535 mutex_unlock(&vc4_hdmi->mutex);
1536 }
1537
vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1538 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1539 struct drm_atomic_state *state)
1540 {
1541 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1542 struct drm_connector *connector = &vc4_hdmi->connector;
1543 struct drm_device *drm = connector->dev;
1544 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1545 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1546 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1547 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1548 unsigned long flags;
1549 int ret;
1550 int idx;
1551
1552 mutex_lock(&vc4_hdmi->mutex);
1553
1554 if (!drm_dev_enter(drm, &idx))
1555 goto out;
1556
1557 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1558
1559 HDMI_WRITE(HDMI_VID_CTL,
1560 (HDMI_READ(HDMI_VID_CTL) &
1561 ~(VC4_HD_VID_CTL_VSYNC_LOW | VC4_HD_VID_CTL_HSYNC_LOW)) |
1562 VC4_HD_VID_CTL_ENABLE |
1563 VC4_HD_VID_CTL_CLRRGB |
1564 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1565 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1566 VC4_HD_VID_CTL_BLANK_INSERT_EN |
1567 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1568 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1569
1570 HDMI_WRITE(HDMI_VID_CTL,
1571 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1572
1573 if (display->is_hdmi) {
1574 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1575 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1576 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1577
1578 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1579
1580 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1581 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1582 WARN_ONCE(ret, "Timeout waiting for "
1583 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1584 } else {
1585 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1586 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1587 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1588 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1589 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1590 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1591
1592 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1593
1594 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1595 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1596 WARN_ONCE(ret, "Timeout waiting for "
1597 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1598 }
1599
1600 if (display->is_hdmi) {
1601 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1602
1603 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1604 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1605
1606 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1607 VC4_HDMI_RAM_PACKET_ENABLE);
1608
1609 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1610 vc4_hdmi->packet_ram_enabled = true;
1611
1612 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
1613 }
1614
1615 vc4_hdmi_recenter_fifo(vc4_hdmi);
1616 vc4_hdmi_enable_scrambling(encoder);
1617
1618 drm_dev_exit(idx);
1619
1620 out:
1621 mutex_unlock(&vc4_hdmi->mutex);
1622 }
1623
vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1624 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1625 struct drm_crtc_state *crtc_state,
1626 struct drm_connector_state *conn_state)
1627 {
1628 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1629
1630 mutex_lock(&vc4_hdmi->mutex);
1631 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1632 &crtc_state->adjusted_mode);
1633 vc4_hdmi->output_bpc = conn_state->hdmi.output_bpc;
1634 vc4_hdmi->output_format = conn_state->hdmi.output_format;
1635 mutex_unlock(&vc4_hdmi->mutex);
1636 }
1637
1638 static enum drm_mode_status
vc4_hdmi_connector_clock_valid(const struct drm_connector * connector,const struct drm_display_mode * mode,unsigned long long clock)1639 vc4_hdmi_connector_clock_valid(const struct drm_connector *connector,
1640 const struct drm_display_mode *mode,
1641 unsigned long long clock)
1642 {
1643 const struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
1644 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
1645
1646 if (clock > vc4_hdmi->variant->max_pixel_clock)
1647 return MODE_CLOCK_HIGH;
1648
1649 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
1650 return MODE_CLOCK_HIGH;
1651
1652 /* 4096x2160@60 is not reliable without overclocking core */
1653 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 &&
1654 mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
1655 drm_mode_vrefresh(mode) >= 50)
1656 return MODE_CLOCK_HIGH;
1657
1658 return MODE_OK;
1659 }
1660
1661 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs = {
1662 .tmds_char_rate_valid = vc4_hdmi_connector_clock_valid,
1663 .write_infoframe = vc4_hdmi_write_infoframe,
1664 };
1665
1666 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1667 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1668
vc4_hdmi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1669 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1670 struct drm_crtc_state *crtc_state,
1671 struct drm_connector_state *conn_state)
1672 {
1673 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1674 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1675 unsigned long long tmds_char_rate = mode->clock * 1000;
1676 unsigned long long tmds_bit_rate;
1677
1678 if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1679 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1680 /* Only try to fixup DBLCLK modes to get 480i and 576i
1681 * working.
1682 * A generic solution for all modes with odd horizontal
1683 * timing values seems impossible based on trying to
1684 * solve it for 1366x768 monitors.
1685 */
1686 if ((mode->hsync_start - mode->hdisplay) & 1)
1687 mode->hsync_start--;
1688 if ((mode->hsync_end - mode->hsync_start) & 1)
1689 mode->hsync_end--;
1690 }
1691
1692 /* Now check whether we still have odd values remaining */
1693 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1694 (mode->hsync_end % 2) || (mode->htotal % 2))
1695 return -EINVAL;
1696 }
1697
1698 /*
1699 * The 1440p@60 pixel rate is in the same range than the first
1700 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1701 * bandwidth). Slightly lower the frequency to bring it out of
1702 * the WiFi range.
1703 */
1704 tmds_bit_rate = tmds_char_rate * 10;
1705 if (vc4_hdmi->disable_wifi_frequencies &&
1706 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1707 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1708 mode->clock = 238560;
1709 tmds_char_rate = mode->clock * 1000;
1710 }
1711
1712 return 0;
1713 }
1714
1715 static enum drm_mode_status
vc4_hdmi_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)1716 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1717 const struct drm_display_mode *mode)
1718 {
1719 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1720
1721 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1722 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1723 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1724 (mode->hsync_end % 2) || (mode->htotal % 2)))
1725 return MODE_H_ILLEGAL;
1726
1727 return MODE_OK;
1728 }
1729
1730 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1731 .atomic_check = vc4_hdmi_encoder_atomic_check,
1732 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1733 .mode_valid = vc4_hdmi_encoder_mode_valid,
1734 };
1735
vc4_hdmi_late_register(struct drm_encoder * encoder)1736 static int vc4_hdmi_late_register(struct drm_encoder *encoder)
1737 {
1738 struct drm_device *drm = encoder->dev;
1739 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1740 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1741
1742 drm_debugfs_add_file(drm, variant->debugfs_name,
1743 vc4_hdmi_debugfs_regs, vc4_hdmi);
1744
1745 return 0;
1746 }
1747
1748 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
1749 .late_register = vc4_hdmi_late_register,
1750 };
1751
vc4_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)1752 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1753 {
1754 int i;
1755 u32 channel_map = 0;
1756
1757 for (i = 0; i < 8; i++) {
1758 if (channel_mask & BIT(i))
1759 channel_map |= i << (3 * i);
1760 }
1761 return channel_map;
1762 }
1763
vc5_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)1764 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1765 {
1766 int i;
1767 u32 channel_map = 0;
1768
1769 for (i = 0; i < 8; i++) {
1770 if (channel_mask & BIT(i))
1771 channel_map |= i << (4 * i);
1772 }
1773 return channel_map;
1774 }
1775
vc5_hdmi_hp_detect(struct vc4_hdmi * vc4_hdmi)1776 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1777 {
1778 struct drm_device *drm = vc4_hdmi->connector.dev;
1779 unsigned long flags;
1780 u32 hotplug;
1781 int idx;
1782
1783 if (!drm_dev_enter(drm, &idx))
1784 return false;
1785
1786 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1787 hotplug = HDMI_READ(HDMI_HOTPLUG);
1788 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1789
1790 drm_dev_exit(idx);
1791
1792 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1793 }
1794
1795 /* HDMI audio codec callbacks */
vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi * vc4_hdmi,unsigned int samplerate)1796 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1797 unsigned int samplerate)
1798 {
1799 struct drm_device *drm = vc4_hdmi->connector.dev;
1800 u32 hsm_clock;
1801 unsigned long flags;
1802 unsigned long n, m;
1803 int idx;
1804
1805 if (!drm_dev_enter(drm, &idx))
1806 return;
1807
1808 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1809 rational_best_approximation(hsm_clock, samplerate,
1810 VC4_HD_MAI_SMP_N_MASK >>
1811 VC4_HD_MAI_SMP_N_SHIFT,
1812 (VC4_HD_MAI_SMP_M_MASK >>
1813 VC4_HD_MAI_SMP_M_SHIFT) + 1,
1814 &n, &m);
1815
1816 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1817 HDMI_WRITE(HDMI_MAI_SMP,
1818 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1819 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1820 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1821
1822 drm_dev_exit(idx);
1823 }
1824
vc4_hdmi_set_n_cts(struct vc4_hdmi * vc4_hdmi,unsigned int samplerate)1825 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1826 {
1827 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1828 u32 n, cts;
1829 u64 tmp;
1830
1831 lockdep_assert_held(&vc4_hdmi->mutex);
1832 lockdep_assert_held(&vc4_hdmi->hw_lock);
1833
1834 n = 128 * samplerate / 1000;
1835 tmp = (u64)(mode->clock * 1000) * n;
1836 do_div(tmp, 128 * samplerate);
1837 cts = tmp;
1838
1839 HDMI_WRITE(HDMI_CRP_CFG,
1840 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1841 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1842
1843 /*
1844 * We could get slightly more accurate clocks in some cases by
1845 * providing a CTS_1 value. The two CTS values are alternated
1846 * between based on the period fields
1847 */
1848 HDMI_WRITE(HDMI_CTS_0, cts);
1849 HDMI_WRITE(HDMI_CTS_1, cts);
1850 }
1851
dai_to_hdmi(struct snd_soc_dai * dai)1852 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1853 {
1854 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1855
1856 return snd_soc_card_get_drvdata(card);
1857 }
1858
vc4_hdmi_audio_can_stream(struct vc4_hdmi * vc4_hdmi)1859 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1860 {
1861 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1862
1863 lockdep_assert_held(&vc4_hdmi->mutex);
1864
1865 /*
1866 * If the encoder is currently in DVI mode, treat the codec DAI
1867 * as missing.
1868 */
1869 if (!display->is_hdmi)
1870 return false;
1871
1872 return true;
1873 }
1874
vc4_hdmi_audio_startup(struct drm_connector * connector)1875 static int vc4_hdmi_audio_startup(struct drm_connector *connector)
1876 {
1877 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
1878 struct drm_device *drm = vc4_hdmi->connector.dev;
1879 unsigned long flags;
1880 int ret = 0;
1881 int idx;
1882
1883 mutex_lock(&vc4_hdmi->mutex);
1884
1885 if (!drm_dev_enter(drm, &idx)) {
1886 ret = -ENODEV;
1887 goto out;
1888 }
1889
1890 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1891 ret = -ENOTSUPP;
1892 goto out_dev_exit;
1893 }
1894
1895 vc4_hdmi->audio.streaming = true;
1896
1897 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1898 HDMI_WRITE(HDMI_MAI_CTL,
1899 VC4_HD_MAI_CTL_RESET |
1900 VC4_HD_MAI_CTL_FLUSH |
1901 VC4_HD_MAI_CTL_DLATE |
1902 VC4_HD_MAI_CTL_ERRORE |
1903 VC4_HD_MAI_CTL_ERRORF);
1904 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1905
1906 if (vc4_hdmi->variant->phy_rng_enable)
1907 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1908
1909 out_dev_exit:
1910 drm_dev_exit(idx);
1911 out:
1912 mutex_unlock(&vc4_hdmi->mutex);
1913
1914 return ret;
1915 }
1916
vc4_hdmi_audio_reset(struct vc4_hdmi * vc4_hdmi)1917 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1918 {
1919 struct device *dev = &vc4_hdmi->pdev->dev;
1920 unsigned long flags;
1921 int ret;
1922
1923 lockdep_assert_held(&vc4_hdmi->mutex);
1924
1925 vc4_hdmi->audio.streaming = false;
1926 ret = vc4_hdmi_stop_packet(vc4_hdmi, HDMI_INFOFRAME_TYPE_AUDIO, false);
1927 if (ret)
1928 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1929
1930 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1931
1932 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1933 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1934 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1935
1936 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1937 }
1938
vc4_hdmi_audio_shutdown(struct drm_connector * connector)1939 static void vc4_hdmi_audio_shutdown(struct drm_connector *connector)
1940 {
1941 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
1942 struct drm_device *drm = vc4_hdmi->connector.dev;
1943 unsigned long flags;
1944 int idx;
1945
1946 mutex_lock(&vc4_hdmi->mutex);
1947
1948 if (!drm_dev_enter(drm, &idx))
1949 goto out;
1950
1951 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1952
1953 HDMI_WRITE(HDMI_MAI_CTL,
1954 VC4_HD_MAI_CTL_DLATE |
1955 VC4_HD_MAI_CTL_ERRORE |
1956 VC4_HD_MAI_CTL_ERRORF);
1957
1958 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1959
1960 if (vc4_hdmi->variant->phy_rng_disable)
1961 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1962
1963 vc4_hdmi->audio.streaming = false;
1964 vc4_hdmi_audio_reset(vc4_hdmi);
1965
1966 drm_dev_exit(idx);
1967
1968 out:
1969 mutex_unlock(&vc4_hdmi->mutex);
1970 }
1971
sample_rate_to_mai_fmt(int samplerate)1972 static int sample_rate_to_mai_fmt(int samplerate)
1973 {
1974 switch (samplerate) {
1975 case 8000:
1976 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1977 case 11025:
1978 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1979 case 12000:
1980 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1981 case 16000:
1982 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1983 case 22050:
1984 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1985 case 24000:
1986 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1987 case 32000:
1988 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1989 case 44100:
1990 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1991 case 48000:
1992 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1993 case 64000:
1994 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1995 case 88200:
1996 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1997 case 96000:
1998 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1999 case 128000:
2000 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2001 case 176400:
2002 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2003 case 192000:
2004 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2005 default:
2006 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2007 }
2008 }
2009
2010 /* HDMI audio codec callbacks */
vc4_hdmi_audio_prepare(struct drm_connector * connector,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)2011 static int vc4_hdmi_audio_prepare(struct drm_connector *connector,
2012 struct hdmi_codec_daifmt *daifmt,
2013 struct hdmi_codec_params *params)
2014 {
2015 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
2016 struct drm_device *drm = vc4_hdmi->connector.dev;
2017 struct vc4_dev *vc4 = to_vc4_dev(drm);
2018 unsigned int sample_rate = params->sample_rate;
2019 unsigned int channels = params->channels;
2020 unsigned long flags;
2021 u32 audio_packet_config, channel_mask;
2022 u32 channel_map;
2023 u32 mai_audio_format;
2024 u32 mai_sample_rate;
2025 int ret = 0;
2026 int idx;
2027
2028 dev_dbg(&vc4_hdmi->pdev->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2029 sample_rate, params->sample_width, channels);
2030
2031 mutex_lock(&vc4_hdmi->mutex);
2032
2033 if (!drm_dev_enter(drm, &idx)) {
2034 ret = -ENODEV;
2035 goto out;
2036 }
2037
2038 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2039 ret = -EINVAL;
2040 goto out_dev_exit;
2041 }
2042
2043 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2044
2045 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2046 HDMI_WRITE(HDMI_MAI_CTL,
2047 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2048 VC4_HD_MAI_CTL_WHOLSMP |
2049 VC4_HD_MAI_CTL_CHALIGN |
2050 VC4_HD_MAI_CTL_ENABLE);
2051
2052 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2053 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2054 params->channels == 8)
2055 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2056 else
2057 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2058 HDMI_WRITE(HDMI_MAI_FMT,
2059 VC4_SET_FIELD(mai_sample_rate,
2060 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2061 VC4_SET_FIELD(mai_audio_format,
2062 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2063
2064 /* The B frame identifier should match the value used by alsa-lib (8) */
2065 audio_packet_config =
2066 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2067 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2068 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2069
2070 channel_mask = GENMASK(channels - 1, 0);
2071 audio_packet_config |= VC4_SET_FIELD(channel_mask,
2072 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2073
2074 /* Set the MAI threshold */
2075 switch (vc4->gen) {
2076 case VC4_GEN_6_D:
2077 HDMI_WRITE(HDMI_MAI_THR,
2078 VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICHIGH) |
2079 VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICLOW) |
2080 VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQHIGH) |
2081 VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQLOW));
2082 break;
2083 case VC4_GEN_6_C:
2084 case VC4_GEN_5:
2085 HDMI_WRITE(HDMI_MAI_THR,
2086 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
2087 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
2088 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) |
2089 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW));
2090 break;
2091 case VC4_GEN_4:
2092 HDMI_WRITE(HDMI_MAI_THR,
2093 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) |
2094 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) |
2095 VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) |
2096 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW));
2097 break;
2098 default:
2099 drm_err(drm, "Unknown VC4 generation: %d", vc4->gen);
2100 break;
2101 }
2102
2103 HDMI_WRITE(HDMI_MAI_CONFIG,
2104 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2105 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2106 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2107
2108 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2109 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2110 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2111
2112 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2113
2114 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2115
2116 ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector,
2117 ¶ms->cea);
2118 if (ret)
2119 goto out_dev_exit;
2120
2121 out_dev_exit:
2122 drm_dev_exit(idx);
2123 out:
2124 mutex_unlock(&vc4_hdmi->mutex);
2125
2126 return ret;
2127 }
2128
2129 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2130 .name = "vc4-hdmi-cpu-dai-component",
2131 .legacy_dai_naming = 1,
2132 };
2133
vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai * dai)2134 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2135 {
2136 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2137
2138 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2139
2140 return 0;
2141 }
2142
2143 static const struct snd_soc_dai_ops vc4_snd_dai_ops = {
2144 .probe = vc4_hdmi_audio_cpu_dai_probe,
2145 };
2146
2147 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2148 .name = "vc4-hdmi-cpu-dai",
2149 .ops = &vc4_snd_dai_ops,
2150 .playback = {
2151 .stream_name = "Playback",
2152 .channels_min = 1,
2153 .channels_max = 8,
2154 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2155 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2156 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2157 SNDRV_PCM_RATE_192000,
2158 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2159 },
2160 };
2161
2162 static const struct snd_dmaengine_pcm_config pcm_conf = {
2163 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2164 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2165 };
2166
2167 static const struct drm_connector_hdmi_audio_funcs vc4_hdmi_audio_funcs = {
2168 .startup = vc4_hdmi_audio_startup,
2169 .prepare = vc4_hdmi_audio_prepare,
2170 .shutdown = vc4_hdmi_audio_shutdown,
2171 };
2172
vc4_hdmi_codec_init(struct snd_soc_pcm_runtime * rtd)2173 static int vc4_hdmi_codec_init(struct snd_soc_pcm_runtime *rtd)
2174 {
2175 struct vc4_hdmi *vc4_hdmi = snd_soc_card_get_drvdata(rtd->card);
2176 struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component;
2177 int ret;
2178
2179 ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT,
2180 &vc4_hdmi->hdmi_jack);
2181 if (ret) {
2182 dev_err(rtd->dev, "HDMI Jack creation failed: %d\n", ret);
2183 return ret;
2184 }
2185
2186 return snd_soc_component_set_jack(component, &vc4_hdmi->hdmi_jack, NULL);
2187 }
2188
vc4_hdmi_audio_init(struct vc4_hdmi * vc4_hdmi)2189 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2190 {
2191 const struct vc4_hdmi_register *mai_data =
2192 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2193 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2194 struct snd_soc_card *card = &vc4_hdmi->audio.card;
2195 struct device *dev = &vc4_hdmi->pdev->dev;
2196 const __be32 *addr;
2197 int index, len;
2198 int ret;
2199
2200 /*
2201 * ASoC makes it a bit hard to retrieve a pointer to the
2202 * vc4_hdmi structure. Registering the card will overwrite our
2203 * device drvdata with a pointer to the snd_soc_card structure,
2204 * which can then be used to retrieve whatever drvdata we want
2205 * to associate.
2206 *
2207 * However, that doesn't fly in the case where we wouldn't
2208 * register an ASoC card (because of an old DT that is missing
2209 * the dmas properties for example), then the card isn't
2210 * registered and the device drvdata wouldn't be set.
2211 *
2212 * We can deal with both cases by making sure a snd_soc_card
2213 * pointer and a vc4_hdmi structure are pointing to the same
2214 * memory address, so we can treat them indistinctly without any
2215 * issue.
2216 */
2217 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2218 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2219
2220 if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2221 dev_warn(dev,
2222 "'dmas' DT property is missing or empty, no HDMI audio\n");
2223 return 0;
2224 }
2225
2226 if (mai_data->reg != VC4_HD) {
2227 WARN_ONCE(true, "MAI isn't in the HD block\n");
2228 return -EINVAL;
2229 }
2230
2231 /*
2232 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2233 * the bus address specified in the DT, because the physical address
2234 * (the one returned by platform_get_resource()) is not appropriate
2235 * for DMA transfers.
2236 * This VC/MMU should probably be exposed to avoid this kind of hacks.
2237 */
2238 index = of_property_match_string(dev->of_node, "reg-names", "hd");
2239 /* Before BCM2711, we don't have a named register range */
2240 if (index < 0)
2241 index = 1;
2242
2243 addr = of_get_address(dev->of_node, index, NULL, NULL);
2244 if (!addr)
2245 return -EINVAL;
2246
2247 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2248 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2249 vc4_hdmi->audio.dma_data.maxburst = 2;
2250
2251 /*
2252 * NOTE: Strictly speaking, we should probably use a DRM-managed
2253 * registration there to avoid removing all the audio components
2254 * by the time the driver doesn't have any user anymore.
2255 *
2256 * However, the ASoC core uses a number of devm_kzalloc calls
2257 * when registering, even when using non-device-managed
2258 * functions (such as in snd_soc_register_component()).
2259 *
2260 * If we call snd_soc_unregister_component() in a DRM-managed
2261 * action, the device-managed actions have already been executed
2262 * and thus we would access memory that has been freed.
2263 *
2264 * Using device-managed hooks here probably leaves us open to a
2265 * bunch of issues if userspace still has a handle on the ALSA
2266 * device when the device is removed. However, this is mitigated
2267 * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2268 * path to prevent the access to the device resources if it
2269 * isn't there anymore.
2270 *
2271 * Then, the vc4_hdmi structure is DRM-managed and thus only
2272 * freed whenever the last user has closed the DRM device file.
2273 * It should thus outlive ALSA in most situations.
2274 */
2275 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2276 if (ret) {
2277 dev_err(dev, "Could not register PCM component: %d\n", ret);
2278 return ret;
2279 }
2280
2281 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2282 &vc4_hdmi_audio_cpu_dai_drv, 1);
2283 if (ret) {
2284 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2285 return ret;
2286 }
2287
2288 ret = drm_connector_hdmi_audio_init(&vc4_hdmi->connector, dev,
2289 &vc4_hdmi_audio_funcs, 8, false,
2290 -1);
2291 if (ret)
2292 return ret;
2293
2294 dai_link->cpus = &vc4_hdmi->audio.cpu;
2295 dai_link->codecs = &vc4_hdmi->audio.codec;
2296 dai_link->platforms = &vc4_hdmi->audio.platform;
2297
2298 dai_link->num_cpus = 1;
2299 dai_link->num_codecs = 1;
2300 dai_link->num_platforms = 1;
2301
2302 dai_link->name = "MAI";
2303 dai_link->stream_name = "MAI PCM";
2304 dai_link->codecs->dai_name = "i2s-hifi";
2305 dai_link->cpus->dai_name = dev_name(dev);
2306 dai_link->codecs->name = dev_name(&vc4_hdmi->connector.hdmi_audio.codec_pdev->dev);
2307 dai_link->platforms->name = dev_name(dev);
2308 dai_link->init = vc4_hdmi_codec_init;
2309
2310 card->dai_link = dai_link;
2311 card->num_links = 1;
2312 card->name = vc4_hdmi->variant->card_name;
2313 card->driver_name = "vc4-hdmi";
2314 card->dev = dev;
2315 card->owner = THIS_MODULE;
2316
2317 /*
2318 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2319 * stores a pointer to the snd card object in dev->driver_data. This
2320 * means we cannot use it for something else. The hdmi back-pointer is
2321 * now stored in card->drvdata and should be retrieved with
2322 * snd_soc_card_get_drvdata() if needed.
2323 */
2324 snd_soc_card_set_drvdata(card, vc4_hdmi);
2325 ret = devm_snd_soc_register_card(dev, card);
2326 if (ret)
2327 dev_err_probe(dev, ret, "Could not register sound card\n");
2328
2329 return ret;
2330
2331 }
2332
vc4_hdmi_hpd_irq_thread(int irq,void * priv)2333 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2334 {
2335 struct vc4_hdmi *vc4_hdmi = priv;
2336 struct drm_connector *connector = &vc4_hdmi->connector;
2337 struct drm_device *dev = connector->dev;
2338
2339 if (dev && dev->registered)
2340 drm_connector_helper_hpd_irq_event(connector);
2341
2342 return IRQ_HANDLED;
2343 }
2344
vc4_hdmi_hotplug_init(struct vc4_hdmi * vc4_hdmi)2345 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2346 {
2347 struct drm_connector *connector = &vc4_hdmi->connector;
2348 struct platform_device *pdev = vc4_hdmi->pdev;
2349 int ret;
2350
2351 if (vc4_hdmi->variant->external_irq_controller) {
2352 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2353 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2354
2355 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2356 NULL,
2357 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2358 "vc4 hdmi hpd connected", vc4_hdmi);
2359 if (ret)
2360 return ret;
2361
2362 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2363 NULL,
2364 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2365 "vc4 hdmi hpd disconnected", vc4_hdmi);
2366 if (ret)
2367 return ret;
2368
2369 connector->polled = DRM_CONNECTOR_POLL_HPD;
2370 }
2371
2372 return 0;
2373 }
2374
2375 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_cec_irq_handler_rx_thread(int irq,void * priv)2376 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2377 {
2378 struct vc4_hdmi *vc4_hdmi = priv;
2379
2380 if (vc4_hdmi->cec_rx_msg.len)
2381 cec_received_msg(vc4_hdmi->cec_adap,
2382 &vc4_hdmi->cec_rx_msg);
2383
2384 return IRQ_HANDLED;
2385 }
2386
vc4_cec_irq_handler_tx_thread(int irq,void * priv)2387 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2388 {
2389 struct vc4_hdmi *vc4_hdmi = priv;
2390
2391 if (vc4_hdmi->cec_tx_ok) {
2392 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2393 0, 0, 0, 0);
2394 } else {
2395 /*
2396 * This CEC implementation makes 1 retry, so if we
2397 * get a NACK, then that means it made 2 attempts.
2398 */
2399 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2400 0, 2, 0, 0);
2401 }
2402 return IRQ_HANDLED;
2403 }
2404
vc4_cec_irq_handler_thread(int irq,void * priv)2405 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2406 {
2407 struct vc4_hdmi *vc4_hdmi = priv;
2408 irqreturn_t ret;
2409
2410 if (vc4_hdmi->cec_irq_was_rx)
2411 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2412 else
2413 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2414
2415 return ret;
2416 }
2417
vc4_cec_read_msg(struct vc4_hdmi * vc4_hdmi,u32 cntrl1)2418 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2419 {
2420 struct drm_device *dev = vc4_hdmi->connector.dev;
2421 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2422 unsigned int i;
2423
2424 lockdep_assert_held(&vc4_hdmi->hw_lock);
2425
2426 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2427 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2428
2429 if (msg->len > 16) {
2430 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2431 return;
2432 }
2433
2434 for (i = 0; i < msg->len; i += 4) {
2435 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2436
2437 msg->msg[i] = val & 0xff;
2438 msg->msg[i + 1] = (val >> 8) & 0xff;
2439 msg->msg[i + 2] = (val >> 16) & 0xff;
2440 msg->msg[i + 3] = (val >> 24) & 0xff;
2441 }
2442 }
2443
vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi * vc4_hdmi)2444 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2445 {
2446 u32 cntrl1;
2447
2448 /*
2449 * We don't need to protect the register access using
2450 * drm_dev_enter() there because the interrupt handler lifetime
2451 * is tied to the device itself, and not to the DRM device.
2452 *
2453 * So when the device will be gone, one of the first thing we
2454 * will be doing will be to unregister the interrupt handler,
2455 * and then unregister the DRM device. drm_dev_enter() would
2456 * thus always succeed if we are here.
2457 */
2458
2459 lockdep_assert_held(&vc4_hdmi->hw_lock);
2460
2461 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2462 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2463 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2464 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2465
2466 return IRQ_WAKE_THREAD;
2467 }
2468
vc4_cec_irq_handler_tx_bare(int irq,void * priv)2469 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2470 {
2471 struct vc4_hdmi *vc4_hdmi = priv;
2472 irqreturn_t ret;
2473
2474 spin_lock(&vc4_hdmi->hw_lock);
2475 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2476 spin_unlock(&vc4_hdmi->hw_lock);
2477
2478 return ret;
2479 }
2480
vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi * vc4_hdmi)2481 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2482 {
2483 u32 cntrl1;
2484
2485 lockdep_assert_held(&vc4_hdmi->hw_lock);
2486
2487 /*
2488 * We don't need to protect the register access using
2489 * drm_dev_enter() there because the interrupt handler lifetime
2490 * is tied to the device itself, and not to the DRM device.
2491 *
2492 * So when the device will be gone, one of the first thing we
2493 * will be doing will be to unregister the interrupt handler,
2494 * and then unregister the DRM device. drm_dev_enter() would
2495 * thus always succeed if we are here.
2496 */
2497
2498 vc4_hdmi->cec_rx_msg.len = 0;
2499 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2500 vc4_cec_read_msg(vc4_hdmi, cntrl1);
2501 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2502 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2503 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2504
2505 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2506
2507 return IRQ_WAKE_THREAD;
2508 }
2509
vc4_cec_irq_handler_rx_bare(int irq,void * priv)2510 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2511 {
2512 struct vc4_hdmi *vc4_hdmi = priv;
2513 irqreturn_t ret;
2514
2515 spin_lock(&vc4_hdmi->hw_lock);
2516 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2517 spin_unlock(&vc4_hdmi->hw_lock);
2518
2519 return ret;
2520 }
2521
vc4_cec_irq_handler(int irq,void * priv)2522 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2523 {
2524 struct vc4_hdmi *vc4_hdmi = priv;
2525 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2526 irqreturn_t ret;
2527 u32 cntrl5;
2528
2529 /*
2530 * We don't need to protect the register access using
2531 * drm_dev_enter() there because the interrupt handler lifetime
2532 * is tied to the device itself, and not to the DRM device.
2533 *
2534 * So when the device will be gone, one of the first thing we
2535 * will be doing will be to unregister the interrupt handler,
2536 * and then unregister the DRM device. drm_dev_enter() would
2537 * thus always succeed if we are here.
2538 */
2539
2540 if (!(stat & VC4_HDMI_CPU_CEC))
2541 return IRQ_NONE;
2542
2543 spin_lock(&vc4_hdmi->hw_lock);
2544 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2545 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2546 if (vc4_hdmi->cec_irq_was_rx)
2547 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2548 else
2549 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2550
2551 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2552 spin_unlock(&vc4_hdmi->hw_lock);
2553
2554 return ret;
2555 }
2556
vc4_hdmi_cec_enable(struct cec_adapter * adap)2557 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2558 {
2559 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2560 struct drm_device *drm = vc4_hdmi->connector.dev;
2561 /* clock period in microseconds */
2562 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2563 unsigned long flags;
2564 u32 val;
2565 int ret;
2566 int idx;
2567
2568 if (!drm_dev_enter(drm, &idx))
2569 /*
2570 * We can't return an error code, because the CEC
2571 * framework will emit WARN_ON messages at unbind
2572 * otherwise.
2573 */
2574 return 0;
2575
2576 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2577 if (ret) {
2578 drm_dev_exit(idx);
2579 return ret;
2580 }
2581
2582 mutex_lock(&vc4_hdmi->mutex);
2583
2584 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2585
2586 val = HDMI_READ(HDMI_CEC_CNTRL_5);
2587 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2588 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2589 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2590 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2591 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2592
2593 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2594 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2595 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2596 HDMI_WRITE(HDMI_CEC_CNTRL_2,
2597 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2598 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2599 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2600 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2601 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2602 HDMI_WRITE(HDMI_CEC_CNTRL_3,
2603 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2604 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2605 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2606 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2607 HDMI_WRITE(HDMI_CEC_CNTRL_4,
2608 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2609 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2610 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2611 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2612
2613 if (!vc4_hdmi->variant->external_irq_controller)
2614 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2615
2616 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2617
2618 mutex_unlock(&vc4_hdmi->mutex);
2619 drm_dev_exit(idx);
2620
2621 return 0;
2622 }
2623
vc4_hdmi_cec_disable(struct cec_adapter * adap)2624 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2625 {
2626 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2627 struct drm_device *drm = vc4_hdmi->connector.dev;
2628 unsigned long flags;
2629 int idx;
2630
2631 if (!drm_dev_enter(drm, &idx))
2632 /*
2633 * We can't return an error code, because the CEC
2634 * framework will emit WARN_ON messages at unbind
2635 * otherwise.
2636 */
2637 return 0;
2638
2639 mutex_lock(&vc4_hdmi->mutex);
2640
2641 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2642
2643 if (!vc4_hdmi->variant->external_irq_controller)
2644 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2645
2646 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2647 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2648
2649 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2650
2651 mutex_unlock(&vc4_hdmi->mutex);
2652
2653 pm_runtime_put(&vc4_hdmi->pdev->dev);
2654
2655 drm_dev_exit(idx);
2656
2657 return 0;
2658 }
2659
vc4_hdmi_cec_adap_enable(struct cec_adapter * adap,bool enable)2660 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2661 {
2662 if (enable)
2663 return vc4_hdmi_cec_enable(adap);
2664 else
2665 return vc4_hdmi_cec_disable(adap);
2666 }
2667
vc4_hdmi_cec_adap_log_addr(struct cec_adapter * adap,u8 log_addr)2668 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2669 {
2670 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2671 struct drm_device *drm = vc4_hdmi->connector.dev;
2672 unsigned long flags;
2673 int idx;
2674
2675 if (!drm_dev_enter(drm, &idx))
2676 /*
2677 * We can't return an error code, because the CEC
2678 * framework will emit WARN_ON messages at unbind
2679 * otherwise.
2680 */
2681 return 0;
2682
2683 mutex_lock(&vc4_hdmi->mutex);
2684 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2685 HDMI_WRITE(HDMI_CEC_CNTRL_1,
2686 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2687 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2688 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2689 mutex_unlock(&vc4_hdmi->mutex);
2690
2691 drm_dev_exit(idx);
2692
2693 return 0;
2694 }
2695
vc4_hdmi_cec_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)2696 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2697 u32 signal_free_time, struct cec_msg *msg)
2698 {
2699 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2700 struct drm_device *dev = vc4_hdmi->connector.dev;
2701 unsigned long flags;
2702 u32 val;
2703 unsigned int i;
2704 int idx;
2705
2706 if (!drm_dev_enter(dev, &idx))
2707 return -ENODEV;
2708
2709 if (msg->len > 16) {
2710 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2711 drm_dev_exit(idx);
2712 return -ENOMEM;
2713 }
2714
2715 mutex_lock(&vc4_hdmi->mutex);
2716
2717 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2718
2719 for (i = 0; i < msg->len; i += 4)
2720 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2721 (msg->msg[i]) |
2722 (msg->msg[i + 1] << 8) |
2723 (msg->msg[i + 2] << 16) |
2724 (msg->msg[i + 3] << 24));
2725
2726 val = HDMI_READ(HDMI_CEC_CNTRL_1);
2727 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2728 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2729 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2730 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2731 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2732
2733 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2734
2735 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2736 mutex_unlock(&vc4_hdmi->mutex);
2737 drm_dev_exit(idx);
2738
2739 return 0;
2740 }
2741
2742 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2743 .adap_enable = vc4_hdmi_cec_adap_enable,
2744 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2745 .adap_transmit = vc4_hdmi_cec_adap_transmit,
2746 };
2747
vc4_hdmi_cec_release(void * ptr)2748 static void vc4_hdmi_cec_release(void *ptr)
2749 {
2750 struct vc4_hdmi *vc4_hdmi = ptr;
2751
2752 cec_unregister_adapter(vc4_hdmi->cec_adap);
2753 vc4_hdmi->cec_adap = NULL;
2754 }
2755
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)2756 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2757 {
2758 struct cec_connector_info conn_info;
2759 struct platform_device *pdev = vc4_hdmi->pdev;
2760 struct device *dev = &pdev->dev;
2761 int ret;
2762
2763 if (!of_property_present(dev->of_node, "interrupts")) {
2764 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2765 return 0;
2766 }
2767
2768 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2769 vc4_hdmi,
2770 vc4_hdmi->variant->card_name,
2771 CEC_CAP_DEFAULTS |
2772 CEC_CAP_CONNECTOR_INFO, 1);
2773 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2774 if (ret < 0)
2775 return ret;
2776
2777 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2778 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2779
2780 if (vc4_hdmi->variant->external_irq_controller) {
2781 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
2782 vc4_cec_irq_handler_rx_bare,
2783 vc4_cec_irq_handler_rx_thread, 0,
2784 "vc4 hdmi cec rx", vc4_hdmi);
2785 if (ret)
2786 goto err_delete_cec_adap;
2787
2788 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
2789 vc4_cec_irq_handler_tx_bare,
2790 vc4_cec_irq_handler_tx_thread, 0,
2791 "vc4 hdmi cec tx", vc4_hdmi);
2792 if (ret)
2793 goto err_delete_cec_adap;
2794 } else {
2795 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
2796 vc4_cec_irq_handler,
2797 vc4_cec_irq_handler_thread, 0,
2798 "vc4 hdmi cec", vc4_hdmi);
2799 if (ret)
2800 goto err_delete_cec_adap;
2801 }
2802
2803 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2804 if (ret < 0)
2805 goto err_delete_cec_adap;
2806
2807 /*
2808 * NOTE: Strictly speaking, we should probably use a DRM-managed
2809 * registration there to avoid removing the CEC adapter by the
2810 * time the DRM driver doesn't have any user anymore.
2811 *
2812 * However, the CEC framework already cleans up the CEC adapter
2813 * only when the last user has closed its file descriptor, so we
2814 * don't need to handle it in DRM.
2815 *
2816 * By the time the device-managed hook is executed, we will give
2817 * up our reference to the CEC adapter and therefore don't
2818 * really care when it's actually freed.
2819 *
2820 * There's still a problematic sequence: if we unregister our
2821 * CEC adapter, but the userspace keeps a handle on the CEC
2822 * adapter but not the DRM device for some reason. In such a
2823 * case, our vc4_hdmi structure will be freed, but the
2824 * cec_adapter structure will have a dangling pointer to what
2825 * used to be our HDMI controller. If we get a CEC call at that
2826 * moment, we could end up with a use-after-free. Fortunately,
2827 * the CEC framework already handles this too, by calling
2828 * cec_is_registered() in cec_ioctl() and cec_poll().
2829 */
2830 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
2831 if (ret)
2832 return ret;
2833
2834 return 0;
2835
2836 err_delete_cec_adap:
2837 cec_delete_adapter(vc4_hdmi->cec_adap);
2838
2839 return ret;
2840 }
2841 #else
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)2842 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2843 {
2844 return 0;
2845 }
2846 #endif
2847
vc4_hdmi_free_regset(struct drm_device * drm,void * ptr)2848 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
2849 {
2850 struct debugfs_reg32 *regs = ptr;
2851
2852 kfree(regs);
2853 }
2854
vc4_hdmi_build_regset(struct drm_device * drm,struct vc4_hdmi * vc4_hdmi,struct debugfs_regset32 * regset,enum vc4_hdmi_regs reg)2855 static int vc4_hdmi_build_regset(struct drm_device *drm,
2856 struct vc4_hdmi *vc4_hdmi,
2857 struct debugfs_regset32 *regset,
2858 enum vc4_hdmi_regs reg)
2859 {
2860 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2861 struct debugfs_reg32 *regs, *new_regs;
2862 unsigned int count = 0;
2863 unsigned int i;
2864 int ret;
2865
2866 regs = kcalloc(variant->num_registers, sizeof(*regs),
2867 GFP_KERNEL);
2868 if (!regs)
2869 return -ENOMEM;
2870
2871 for (i = 0; i < variant->num_registers; i++) {
2872 const struct vc4_hdmi_register *field = &variant->registers[i];
2873
2874 if (field->reg != reg)
2875 continue;
2876
2877 regs[count].name = field->name;
2878 regs[count].offset = field->offset;
2879 count++;
2880 }
2881
2882 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2883 if (!new_regs)
2884 return -ENOMEM;
2885
2886 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2887 regset->regs = new_regs;
2888 regset->nregs = count;
2889
2890 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
2891 if (ret)
2892 return ret;
2893
2894 return 0;
2895 }
2896
vc4_hdmi_init_resources(struct drm_device * drm,struct vc4_hdmi * vc4_hdmi)2897 static int vc4_hdmi_init_resources(struct drm_device *drm,
2898 struct vc4_hdmi *vc4_hdmi)
2899 {
2900 struct platform_device *pdev = vc4_hdmi->pdev;
2901 struct device *dev = &pdev->dev;
2902 int ret;
2903
2904 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2905 if (IS_ERR(vc4_hdmi->hdmicore_regs))
2906 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2907
2908 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2909 if (IS_ERR(vc4_hdmi->hd_regs))
2910 return PTR_ERR(vc4_hdmi->hd_regs);
2911
2912 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2913 if (ret)
2914 return ret;
2915
2916 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2917 if (ret)
2918 return ret;
2919
2920 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2921 if (IS_ERR(vc4_hdmi->pixel_clock)) {
2922 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2923 if (ret != -EPROBE_DEFER)
2924 drm_err(drm, "Failed to get pixel clock\n");
2925 return ret;
2926 }
2927
2928 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2929 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2930 drm_err(drm, "Failed to get HDMI state machine clock\n");
2931 return PTR_ERR(vc4_hdmi->hsm_clock);
2932 }
2933 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2934 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2935
2936 return 0;
2937 }
2938
vc5_hdmi_init_resources(struct drm_device * drm,struct vc4_hdmi * vc4_hdmi)2939 static int vc5_hdmi_init_resources(struct drm_device *drm,
2940 struct vc4_hdmi *vc4_hdmi)
2941 {
2942 struct platform_device *pdev = vc4_hdmi->pdev;
2943 struct device *dev = &pdev->dev;
2944 struct resource *res;
2945 int ret;
2946
2947 vc4_hdmi->hdmicore_regs = devm_platform_ioremap_resource_byname(pdev,
2948 "hdmi");
2949 if (IS_ERR(vc4_hdmi->hdmicore_regs))
2950 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2951
2952 /* This is shared between both HDMI controllers. Cannot
2953 * claim for both instances. Lets not convert to using
2954 * devm_platform_ioremap_resource_byname() like
2955 * the rest
2956 */
2957 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2958 if (!res)
2959 return -ENODEV;
2960
2961 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2962 if (!vc4_hdmi->hd_regs)
2963 return -ENOMEM;
2964
2965 vc4_hdmi->cec_regs = devm_platform_ioremap_resource_byname(pdev,
2966 "cec");
2967 if (IS_ERR(vc4_hdmi->cec_regs))
2968 return PTR_ERR(vc4_hdmi->cec_regs);
2969
2970 vc4_hdmi->csc_regs = devm_platform_ioremap_resource_byname(pdev,
2971 "csc");
2972 if (IS_ERR(vc4_hdmi->csc_regs))
2973 return PTR_ERR(vc4_hdmi->csc_regs);
2974
2975 vc4_hdmi->dvp_regs = devm_platform_ioremap_resource_byname(pdev,
2976 "dvp");
2977 if (IS_ERR(vc4_hdmi->dvp_regs))
2978 return PTR_ERR(vc4_hdmi->dvp_regs);
2979
2980 vc4_hdmi->phy_regs = devm_platform_ioremap_resource_byname(pdev,
2981 "phy");
2982
2983 if (IS_ERR(vc4_hdmi->phy_regs))
2984 return PTR_ERR(vc4_hdmi->phy_regs);
2985
2986 vc4_hdmi->ram_regs = devm_platform_ioremap_resource_byname(pdev,
2987 "packet");
2988 if (IS_ERR(vc4_hdmi->ram_regs))
2989 return PTR_ERR(vc4_hdmi->ram_regs);
2990
2991 vc4_hdmi->rm_regs = devm_platform_ioremap_resource_byname(pdev, "rm");
2992 if (IS_ERR(vc4_hdmi->rm_regs))
2993 return PTR_ERR(vc4_hdmi->rm_regs);
2994
2995 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2996 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2997 drm_err(drm, "Failed to get HDMI state machine clock\n");
2998 return PTR_ERR(vc4_hdmi->hsm_clock);
2999 }
3000
3001 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3002 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3003 drm_err(drm, "Failed to get pixel bvb clock\n");
3004 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3005 }
3006
3007 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3008 if (IS_ERR(vc4_hdmi->audio_clock)) {
3009 drm_err(drm, "Failed to get audio clock\n");
3010 return PTR_ERR(vc4_hdmi->audio_clock);
3011 }
3012
3013 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3014 if (IS_ERR(vc4_hdmi->cec_clock)) {
3015 drm_err(drm, "Failed to get CEC clock\n");
3016 return PTR_ERR(vc4_hdmi->cec_clock);
3017 }
3018
3019 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3020 if (IS_ERR(vc4_hdmi->reset)) {
3021 drm_err(drm, "Failed to get HDMI reset line\n");
3022 return PTR_ERR(vc4_hdmi->reset);
3023 }
3024
3025 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3026 if (ret)
3027 return ret;
3028
3029 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3030 if (ret)
3031 return ret;
3032
3033 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3034 if (ret)
3035 return ret;
3036
3037 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3038 if (ret)
3039 return ret;
3040
3041 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3042 if (ret)
3043 return ret;
3044
3045 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3046 if (ret)
3047 return ret;
3048
3049 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3050 if (ret)
3051 return ret;
3052
3053 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3054 if (ret)
3055 return ret;
3056
3057 return 0;
3058 }
3059
vc4_hdmi_runtime_suspend(struct device * dev)3060 static int vc4_hdmi_runtime_suspend(struct device *dev)
3061 {
3062 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3063
3064 clk_disable_unprepare(vc4_hdmi->audio_clock);
3065 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3066
3067 return 0;
3068 }
3069
vc4_hdmi_runtime_resume(struct device * dev)3070 static int vc4_hdmi_runtime_resume(struct device *dev)
3071 {
3072 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3073 unsigned long __maybe_unused flags;
3074 u32 __maybe_unused value;
3075 unsigned long rate;
3076 int ret;
3077
3078 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3079 if (ret)
3080 return ret;
3081
3082 /*
3083 * Whenever the RaspberryPi boots without an HDMI monitor
3084 * plugged in, the firmware won't have initialized the HSM clock
3085 * rate and it will be reported as 0.
3086 *
3087 * If we try to access a register of the controller in such a
3088 * case, it will lead to a silent CPU stall. Let's make sure we
3089 * prevent such a case.
3090 */
3091 rate = clk_get_rate(vc4_hdmi->hsm_clock);
3092 if (!rate) {
3093 ret = -EINVAL;
3094 goto err_disable_clk;
3095 }
3096
3097 ret = clk_prepare_enable(vc4_hdmi->audio_clock);
3098 if (ret)
3099 goto err_disable_clk;
3100
3101 if (vc4_hdmi->variant->reset)
3102 vc4_hdmi->variant->reset(vc4_hdmi);
3103
3104 #ifdef CONFIG_DRM_VC4_HDMI_CEC
3105 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3106 value = HDMI_READ(HDMI_CEC_CNTRL_1);
3107 /* Set the logical address to Unregistered */
3108 value |= VC4_HDMI_CEC_ADDR_MASK;
3109 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3110 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3111
3112 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3113
3114 if (!vc4_hdmi->variant->external_irq_controller) {
3115 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3116 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3117 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3118 }
3119 #endif
3120
3121 return 0;
3122
3123 err_disable_clk:
3124 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3125 return ret;
3126 }
3127
vc4_hdmi_put_ddc_device(void * ptr)3128 static void vc4_hdmi_put_ddc_device(void *ptr)
3129 {
3130 struct vc4_hdmi *vc4_hdmi = ptr;
3131
3132 put_device(&vc4_hdmi->ddc->dev);
3133 }
3134
vc4_hdmi_bind(struct device * dev,struct device * master,void * data)3135 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3136 {
3137 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3138 struct platform_device *pdev = to_platform_device(dev);
3139 struct drm_device *drm = dev_get_drvdata(master);
3140 struct vc4_hdmi *vc4_hdmi;
3141 struct drm_encoder *encoder;
3142 struct device_node *ddc_node;
3143 int ret;
3144
3145 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3146 if (!vc4_hdmi)
3147 return -ENOMEM;
3148
3149 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3150 if (ret)
3151 return ret;
3152
3153 spin_lock_init(&vc4_hdmi->hw_lock);
3154 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3155
3156 dev_set_drvdata(dev, vc4_hdmi);
3157 encoder = &vc4_hdmi->encoder.base;
3158 vc4_hdmi->encoder.type = variant->encoder_type;
3159 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3160 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3161 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3162 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3163 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3164 vc4_hdmi->pdev = pdev;
3165 vc4_hdmi->variant = variant;
3166
3167 /*
3168 * Since we don't know the state of the controller and its
3169 * display (if any), let's assume it's always enabled.
3170 * vc4_hdmi_disable_scrambling() will thus run at boot, make
3171 * sure it's disabled, and avoid any inconsistency.
3172 */
3173 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3174 vc4_hdmi->scdc_enabled = true;
3175
3176 ret = variant->init_resources(drm, vc4_hdmi);
3177 if (ret)
3178 return ret;
3179
3180 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3181 if (!ddc_node) {
3182 drm_err(drm, "Failed to find ddc node in device tree\n");
3183 return -ENODEV;
3184 }
3185
3186 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3187 of_node_put(ddc_node);
3188 if (!vc4_hdmi->ddc) {
3189 drm_err(drm, "Failed to get ddc i2c adapter by node\n");
3190 return -EPROBE_DEFER;
3191 }
3192
3193 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3194 if (ret)
3195 return ret;
3196
3197 /* Only use the GPIO HPD pin if present in the DT, otherwise
3198 * we'll use the HDMI core's register.
3199 */
3200 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3201 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3202 return PTR_ERR(vc4_hdmi->hpd_gpio);
3203 }
3204
3205 vc4_hdmi->disable_wifi_frequencies =
3206 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3207
3208 ret = devm_pm_runtime_enable(dev);
3209 if (ret)
3210 return ret;
3211
3212 /*
3213 * We need to have the device powered up at this point to call
3214 * our reset hook and for the CEC init.
3215 */
3216 ret = pm_runtime_resume_and_get(dev);
3217 if (ret)
3218 return ret;
3219
3220 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3221 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1") ||
3222 of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi0") ||
3223 of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi1")) &&
3224 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3225 clk_prepare_enable(vc4_hdmi->pixel_clock);
3226 clk_prepare_enable(vc4_hdmi->hsm_clock);
3227 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3228 }
3229
3230 ret = drmm_encoder_init(drm, encoder,
3231 &vc4_hdmi_encoder_funcs,
3232 DRM_MODE_ENCODER_TMDS,
3233 NULL);
3234 if (ret)
3235 goto err_put_runtime_pm;
3236
3237 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3238
3239 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3240 if (ret)
3241 goto err_put_runtime_pm;
3242
3243 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3244 if (ret)
3245 goto err_put_runtime_pm;
3246
3247 ret = vc4_hdmi_cec_init(vc4_hdmi);
3248 if (ret)
3249 goto err_put_runtime_pm;
3250
3251 ret = vc4_hdmi_audio_init(vc4_hdmi);
3252 if (ret)
3253 goto err_put_runtime_pm;
3254
3255 pm_runtime_put_sync(dev);
3256
3257 return 0;
3258
3259 err_put_runtime_pm:
3260 pm_runtime_put_sync(dev);
3261
3262 return ret;
3263 }
3264
3265 static const struct component_ops vc4_hdmi_ops = {
3266 .bind = vc4_hdmi_bind,
3267 };
3268
vc4_hdmi_dev_probe(struct platform_device * pdev)3269 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3270 {
3271 return component_add(&pdev->dev, &vc4_hdmi_ops);
3272 }
3273
vc4_hdmi_dev_remove(struct platform_device * pdev)3274 static void vc4_hdmi_dev_remove(struct platform_device *pdev)
3275 {
3276 component_del(&pdev->dev, &vc4_hdmi_ops);
3277 }
3278
3279 static const struct vc4_hdmi_variant bcm2835_variant = {
3280 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3281 .debugfs_name = "hdmi_regs",
3282 .card_name = "vc4-hdmi",
3283 .max_pixel_clock = 162000000,
3284 .registers = vc4_hdmi_fields,
3285 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
3286
3287 .init_resources = vc4_hdmi_init_resources,
3288 .csc_setup = vc4_hdmi_csc_setup,
3289 .reset = vc4_hdmi_reset,
3290 .set_timings = vc4_hdmi_set_timings,
3291 .phy_init = vc4_hdmi_phy_init,
3292 .phy_disable = vc4_hdmi_phy_disable,
3293 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
3294 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
3295 .channel_map = vc4_hdmi_channel_map,
3296 .supports_hdr = false,
3297 };
3298
3299 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3300 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3301 .debugfs_name = "hdmi0_regs",
3302 .card_name = "vc4-hdmi-0",
3303 .max_pixel_clock = 600000000,
3304 .registers = vc5_hdmi_hdmi0_fields,
3305 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3306 .phy_lane_mapping = {
3307 PHY_LANE_0,
3308 PHY_LANE_1,
3309 PHY_LANE_2,
3310 PHY_LANE_CK,
3311 },
3312 .unsupported_odd_h_timings = true,
3313 .external_irq_controller = true,
3314
3315 .init_resources = vc5_hdmi_init_resources,
3316 .csc_setup = vc5_hdmi_csc_setup,
3317 .reset = vc5_hdmi_reset,
3318 .set_timings = vc5_hdmi_set_timings,
3319 .phy_init = vc5_hdmi_phy_init,
3320 .phy_disable = vc5_hdmi_phy_disable,
3321 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3322 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3323 .channel_map = vc5_hdmi_channel_map,
3324 .supports_hdr = true,
3325 .hp_detect = vc5_hdmi_hp_detect,
3326 };
3327
3328 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3329 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
3330 .debugfs_name = "hdmi1_regs",
3331 .card_name = "vc4-hdmi-1",
3332 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
3333 .registers = vc5_hdmi_hdmi1_fields,
3334 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3335 .phy_lane_mapping = {
3336 PHY_LANE_1,
3337 PHY_LANE_0,
3338 PHY_LANE_CK,
3339 PHY_LANE_2,
3340 },
3341 .unsupported_odd_h_timings = true,
3342 .external_irq_controller = true,
3343
3344 .init_resources = vc5_hdmi_init_resources,
3345 .csc_setup = vc5_hdmi_csc_setup,
3346 .reset = vc5_hdmi_reset,
3347 .set_timings = vc5_hdmi_set_timings,
3348 .phy_init = vc5_hdmi_phy_init,
3349 .phy_disable = vc5_hdmi_phy_disable,
3350 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3351 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3352 .channel_map = vc5_hdmi_channel_map,
3353 .supports_hdr = true,
3354 .hp_detect = vc5_hdmi_hp_detect,
3355 };
3356
3357 static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = {
3358 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3359 .debugfs_name = "hdmi0_regs",
3360 .card_name = "vc4-hdmi-0",
3361 .max_pixel_clock = 600000000,
3362 .registers = vc6_hdmi_hdmi0_fields,
3363 .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi0_fields),
3364 .phy_lane_mapping = {
3365 PHY_LANE_0,
3366 PHY_LANE_1,
3367 PHY_LANE_2,
3368 PHY_LANE_CK,
3369 },
3370 .unsupported_odd_h_timings = false,
3371 .external_irq_controller = true,
3372
3373 .init_resources = vc5_hdmi_init_resources,
3374 .csc_setup = vc5_hdmi_csc_setup,
3375 .reset = vc5_hdmi_reset,
3376 .set_timings = vc5_hdmi_set_timings,
3377 .phy_init = vc6_hdmi_phy_init,
3378 .phy_disable = vc6_hdmi_phy_disable,
3379 .channel_map = vc5_hdmi_channel_map,
3380 .supports_hdr = true,
3381 .hp_detect = vc5_hdmi_hp_detect,
3382 };
3383
3384 static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = {
3385 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
3386 .debugfs_name = "hdmi1_regs",
3387 .card_name = "vc4-hdmi-1",
3388 .max_pixel_clock = 600000000,
3389 .registers = vc6_hdmi_hdmi1_fields,
3390 .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi1_fields),
3391 .phy_lane_mapping = {
3392 PHY_LANE_0,
3393 PHY_LANE_1,
3394 PHY_LANE_2,
3395 PHY_LANE_CK,
3396 },
3397 .unsupported_odd_h_timings = false,
3398 .external_irq_controller = true,
3399
3400 .init_resources = vc5_hdmi_init_resources,
3401 .csc_setup = vc5_hdmi_csc_setup,
3402 .reset = vc5_hdmi_reset,
3403 .set_timings = vc5_hdmi_set_timings,
3404 .phy_init = vc6_hdmi_phy_init,
3405 .phy_disable = vc6_hdmi_phy_disable,
3406 .channel_map = vc5_hdmi_channel_map,
3407 .supports_hdr = true,
3408 .hp_detect = vc5_hdmi_hp_detect,
3409 };
3410
3411 static const struct of_device_id vc4_hdmi_dt_match[] = {
3412 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3413 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3414 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3415 { .compatible = "brcm,bcm2712-hdmi0", .data = &bcm2712_hdmi0_variant },
3416 { .compatible = "brcm,bcm2712-hdmi1", .data = &bcm2712_hdmi1_variant },
3417 {}
3418 };
3419
3420 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3421 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3422 vc4_hdmi_runtime_resume,
3423 NULL)
3424 };
3425
3426 struct platform_driver vc4_hdmi_driver = {
3427 .probe = vc4_hdmi_dev_probe,
3428 .remove = vc4_hdmi_dev_remove,
3429 .driver = {
3430 .name = "vc4_hdmi",
3431 .of_match_table = vc4_hdmi_dt_match,
3432 .pm = &vc4_hdmi_pm_ops,
3433 },
3434 };
3435