1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * tegra20_spdif.c - Tegra20 SPDIF driver
4 *
5 * Author: Stephen Warren <swarren@nvidia.com>
6 * Copyright (C) 2011-2012 - NVIDIA, Inc.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
18 #include <linux/slab.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/dmaengine_pcm.h>
24
25 #include "tegra20_spdif.h"
26
tegra20_spdif_runtime_suspend(struct device * dev)27 static int tegra20_spdif_runtime_suspend(struct device *dev)
28 {
29 struct tegra20_spdif *spdif = dev_get_drvdata(dev);
30
31 regcache_cache_only(spdif->regmap, true);
32
33 clk_disable_unprepare(spdif->clk_spdif_out);
34
35 return 0;
36 }
37
tegra20_spdif_runtime_resume(struct device * dev)38 static int tegra20_spdif_runtime_resume(struct device *dev)
39 {
40 struct tegra20_spdif *spdif = dev_get_drvdata(dev);
41 int ret;
42
43 ret = reset_control_assert(spdif->reset);
44 if (ret)
45 return ret;
46
47 ret = clk_prepare_enable(spdif->clk_spdif_out);
48 if (ret) {
49 dev_err(dev, "clk_enable failed: %d\n", ret);
50 return ret;
51 }
52
53 usleep_range(10, 100);
54
55 ret = reset_control_deassert(spdif->reset);
56 if (ret)
57 goto disable_clocks;
58
59 regcache_cache_only(spdif->regmap, false);
60 regcache_mark_dirty(spdif->regmap);
61
62 ret = regcache_sync(spdif->regmap);
63 if (ret)
64 goto disable_clocks;
65
66 return 0;
67
68 disable_clocks:
69 clk_disable_unprepare(spdif->clk_spdif_out);
70
71 return ret;
72 }
73
tegra20_spdif_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)74 static int tegra20_spdif_hw_params(struct snd_pcm_substream *substream,
75 struct snd_pcm_hw_params *params,
76 struct snd_soc_dai *dai)
77 {
78 struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
79 unsigned int mask = 0, val = 0;
80 int ret, spdifclock;
81 long rate;
82
83 mask |= TEGRA20_SPDIF_CTRL_PACK |
84 TEGRA20_SPDIF_CTRL_BIT_MODE_MASK;
85 switch (params_format(params)) {
86 case SNDRV_PCM_FORMAT_S16_LE:
87 val |= TEGRA20_SPDIF_CTRL_PACK |
88 TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT;
89 break;
90 default:
91 return -EINVAL;
92 }
93
94 regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val);
95
96 /*
97 * FIFO trigger level must be bigger than DMA burst or equal to it,
98 * otherwise data is discarded on overflow.
99 */
100 regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_DATA_FIFO_CSR,
101 TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK,
102 TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL);
103
104 switch (params_rate(params)) {
105 case 32000:
106 spdifclock = 4096000;
107 break;
108 case 44100:
109 spdifclock = 5644800;
110 break;
111 case 48000:
112 spdifclock = 6144000;
113 break;
114 case 88200:
115 spdifclock = 11289600;
116 break;
117 case 96000:
118 spdifclock = 12288000;
119 break;
120 case 176400:
121 spdifclock = 22579200;
122 break;
123 case 192000:
124 spdifclock = 24576000;
125 break;
126 default:
127 return -EINVAL;
128 }
129
130 ret = clk_set_rate(spdif->clk_spdif_out, spdifclock);
131 if (ret) {
132 dev_err(dai->dev, "Can't set SPDIF clock rate: %d\n", ret);
133 return ret;
134 }
135
136 rate = clk_get_rate(spdif->clk_spdif_out);
137 if (rate != spdifclock)
138 dev_warn_once(dai->dev,
139 "SPDIF clock rate %d doesn't match requested rate %lu\n",
140 spdifclock, rate);
141
142 return 0;
143 }
144
tegra20_spdif_start_playback(struct tegra20_spdif * spdif)145 static void tegra20_spdif_start_playback(struct tegra20_spdif *spdif)
146 {
147 regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
148 TEGRA20_SPDIF_CTRL_TX_EN,
149 TEGRA20_SPDIF_CTRL_TX_EN);
150 }
151
tegra20_spdif_stop_playback(struct tegra20_spdif * spdif)152 static void tegra20_spdif_stop_playback(struct tegra20_spdif *spdif)
153 {
154 regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
155 TEGRA20_SPDIF_CTRL_TX_EN, 0);
156 }
157
tegra20_spdif_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)158 static int tegra20_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
159 struct snd_soc_dai *dai)
160 {
161 struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
162
163 switch (cmd) {
164 case SNDRV_PCM_TRIGGER_START:
165 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
166 case SNDRV_PCM_TRIGGER_RESUME:
167 tegra20_spdif_start_playback(spdif);
168 break;
169 case SNDRV_PCM_TRIGGER_STOP:
170 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
171 case SNDRV_PCM_TRIGGER_SUSPEND:
172 tegra20_spdif_stop_playback(spdif);
173 break;
174 default:
175 return -EINVAL;
176 }
177
178 return 0;
179 }
180
tegra20_spdif_filter_rates(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)181 static int tegra20_spdif_filter_rates(struct snd_pcm_hw_params *params,
182 struct snd_pcm_hw_rule *rule)
183 {
184 struct snd_interval *r = hw_param_interval(params, rule->var);
185 struct snd_soc_dai *dai = rule->private;
186 struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
187 struct clk *parent = clk_get_parent(spdif->clk_spdif_out);
188 static const unsigned int rates[] = { 32000, 44100, 48000 };
189 unsigned long i, parent_rate, valid_rates = 0;
190
191 parent_rate = clk_get_rate(parent);
192 if (!parent_rate) {
193 dev_err(dai->dev, "Can't get parent clock rate\n");
194 return -EINVAL;
195 }
196
197 for (i = 0; i < ARRAY_SIZE(rates); i++) {
198 if (parent_rate % (rates[i] * 128) == 0)
199 valid_rates |= BIT(i);
200 }
201
202 /*
203 * At least one rate must be valid, otherwise the parent clock isn't
204 * audio PLL. Nothing should be filtered in this case.
205 */
206 if (!valid_rates)
207 valid_rates = BIT(ARRAY_SIZE(rates)) - 1;
208
209 return snd_interval_list(r, ARRAY_SIZE(rates), rates, valid_rates);
210 }
211
tegra20_spdif_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)212 static int tegra20_spdif_startup(struct snd_pcm_substream *substream,
213 struct snd_soc_dai *dai)
214 {
215 if (!device_property_read_bool(dai->dev, "nvidia,fixed-parent-rate"))
216 return 0;
217
218 /*
219 * SPDIF and I2S share audio PLL. HDMI takes audio packets from SPDIF
220 * and audio may not work on some TVs if clock rate isn't precise.
221 *
222 * PLL rate is controlled by I2S side. Filter out audio rates that
223 * don't match PLL rate at the start of stream to allow both SPDIF
224 * and I2S work simultaneously, assuming that PLL rate won't be
225 * changed later on.
226 */
227 return snd_pcm_hw_rule_add(substream->runtime, 0,
228 SNDRV_PCM_HW_PARAM_RATE,
229 tegra20_spdif_filter_rates, dai,
230 SNDRV_PCM_HW_PARAM_RATE, -1);
231 }
232
tegra20_spdif_probe(struct snd_soc_dai * dai)233 static int tegra20_spdif_probe(struct snd_soc_dai *dai)
234 {
235 struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
236
237 snd_soc_dai_init_dma_data(dai, &spdif->playback_dma_data, NULL);
238
239 return 0;
240 }
241
242 static const struct snd_soc_dai_ops tegra20_spdif_dai_ops = {
243 .probe = tegra20_spdif_probe,
244 .hw_params = tegra20_spdif_hw_params,
245 .trigger = tegra20_spdif_trigger,
246 .startup = tegra20_spdif_startup,
247 };
248
249 static struct snd_soc_dai_driver tegra20_spdif_dai = {
250 .name = "tegra20-spdif",
251 .playback = {
252 .stream_name = "Playback",
253 .channels_min = 2,
254 .channels_max = 2,
255 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
256 SNDRV_PCM_RATE_48000,
257 .formats = SNDRV_PCM_FMTBIT_S16_LE,
258 },
259 .ops = &tegra20_spdif_dai_ops,
260 };
261
262 static const struct snd_soc_component_driver tegra20_spdif_component = {
263 .name = "tegra20-spdif",
264 .legacy_dai_naming = 1,
265 };
266
tegra20_spdif_wr_rd_reg(struct device * dev,unsigned int reg)267 static bool tegra20_spdif_wr_rd_reg(struct device *dev, unsigned int reg)
268 {
269 switch (reg) {
270 case TEGRA20_SPDIF_CTRL:
271 case TEGRA20_SPDIF_STATUS:
272 case TEGRA20_SPDIF_STROBE_CTRL:
273 case TEGRA20_SPDIF_DATA_FIFO_CSR:
274 case TEGRA20_SPDIF_DATA_OUT:
275 case TEGRA20_SPDIF_DATA_IN:
276 case TEGRA20_SPDIF_CH_STA_RX_A:
277 case TEGRA20_SPDIF_CH_STA_RX_B:
278 case TEGRA20_SPDIF_CH_STA_RX_C:
279 case TEGRA20_SPDIF_CH_STA_RX_D:
280 case TEGRA20_SPDIF_CH_STA_RX_E:
281 case TEGRA20_SPDIF_CH_STA_RX_F:
282 case TEGRA20_SPDIF_CH_STA_TX_A:
283 case TEGRA20_SPDIF_CH_STA_TX_B:
284 case TEGRA20_SPDIF_CH_STA_TX_C:
285 case TEGRA20_SPDIF_CH_STA_TX_D:
286 case TEGRA20_SPDIF_CH_STA_TX_E:
287 case TEGRA20_SPDIF_CH_STA_TX_F:
288 case TEGRA20_SPDIF_USR_STA_RX_A:
289 case TEGRA20_SPDIF_USR_DAT_TX_A:
290 return true;
291 default:
292 return false;
293 }
294 }
295
tegra20_spdif_volatile_reg(struct device * dev,unsigned int reg)296 static bool tegra20_spdif_volatile_reg(struct device *dev, unsigned int reg)
297 {
298 switch (reg) {
299 case TEGRA20_SPDIF_STATUS:
300 case TEGRA20_SPDIF_DATA_FIFO_CSR:
301 case TEGRA20_SPDIF_DATA_OUT:
302 case TEGRA20_SPDIF_DATA_IN:
303 case TEGRA20_SPDIF_CH_STA_RX_A:
304 case TEGRA20_SPDIF_CH_STA_RX_B:
305 case TEGRA20_SPDIF_CH_STA_RX_C:
306 case TEGRA20_SPDIF_CH_STA_RX_D:
307 case TEGRA20_SPDIF_CH_STA_RX_E:
308 case TEGRA20_SPDIF_CH_STA_RX_F:
309 case TEGRA20_SPDIF_USR_STA_RX_A:
310 case TEGRA20_SPDIF_USR_DAT_TX_A:
311 return true;
312 default:
313 return false;
314 }
315 }
316
tegra20_spdif_precious_reg(struct device * dev,unsigned int reg)317 static bool tegra20_spdif_precious_reg(struct device *dev, unsigned int reg)
318 {
319 switch (reg) {
320 case TEGRA20_SPDIF_DATA_OUT:
321 case TEGRA20_SPDIF_DATA_IN:
322 case TEGRA20_SPDIF_USR_STA_RX_A:
323 case TEGRA20_SPDIF_USR_DAT_TX_A:
324 return true;
325 default:
326 return false;
327 }
328 }
329
330 static const struct regmap_config tegra20_spdif_regmap_config = {
331 .reg_bits = 32,
332 .reg_stride = 4,
333 .val_bits = 32,
334 .max_register = TEGRA20_SPDIF_USR_DAT_TX_A,
335 .writeable_reg = tegra20_spdif_wr_rd_reg,
336 .readable_reg = tegra20_spdif_wr_rd_reg,
337 .volatile_reg = tegra20_spdif_volatile_reg,
338 .precious_reg = tegra20_spdif_precious_reg,
339 .cache_type = REGCACHE_FLAT,
340 };
341
tegra20_spdif_platform_probe(struct platform_device * pdev)342 static int tegra20_spdif_platform_probe(struct platform_device *pdev)
343 {
344 struct tegra20_spdif *spdif;
345 struct resource *mem;
346 void __iomem *regs;
347 int ret;
348
349 spdif = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_spdif),
350 GFP_KERNEL);
351 if (!spdif)
352 return -ENOMEM;
353
354 dev_set_drvdata(&pdev->dev, spdif);
355
356 spdif->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
357 if (IS_ERR(spdif->reset)) {
358 dev_err(&pdev->dev, "Can't retrieve spdif reset\n");
359 return PTR_ERR(spdif->reset);
360 }
361
362 spdif->clk_spdif_out = devm_clk_get(&pdev->dev, "out");
363 if (IS_ERR(spdif->clk_spdif_out)) {
364 dev_err(&pdev->dev, "Could not retrieve spdif clock\n");
365 return PTR_ERR(spdif->clk_spdif_out);
366 }
367
368 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
369 if (IS_ERR(regs))
370 return PTR_ERR(regs);
371
372 spdif->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
373 &tegra20_spdif_regmap_config);
374 if (IS_ERR(spdif->regmap)) {
375 dev_err(&pdev->dev, "regmap init failed\n");
376 return PTR_ERR(spdif->regmap);
377 }
378
379 spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT;
380 spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
381 spdif->playback_dma_data.maxburst = 4;
382
383 ret = devm_pm_runtime_enable(&pdev->dev);
384 if (ret)
385 return ret;
386
387 ret = devm_snd_soc_register_component(&pdev->dev,
388 &tegra20_spdif_component,
389 &tegra20_spdif_dai, 1);
390 if (ret) {
391 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
392 return ret;
393 }
394
395 ret = devm_tegra_pcm_platform_register(&pdev->dev);
396 if (ret) {
397 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
398 return ret;
399 }
400
401 return 0;
402 }
403
404 static const struct dev_pm_ops tegra20_spdif_pm_ops = {
405 RUNTIME_PM_OPS(tegra20_spdif_runtime_suspend,
406 tegra20_spdif_runtime_resume, NULL)
407 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
408 };
409
410 static const struct of_device_id tegra20_spdif_of_match[] = {
411 { .compatible = "nvidia,tegra20-spdif", },
412 {},
413 };
414 MODULE_DEVICE_TABLE(of, tegra20_spdif_of_match);
415
416 static struct platform_driver tegra20_spdif_driver = {
417 .driver = {
418 .name = "tegra20-spdif",
419 .pm = pm_ptr(&tegra20_spdif_pm_ops),
420 .of_match_table = tegra20_spdif_of_match,
421 },
422 .probe = tegra20_spdif_platform_probe,
423 };
424 module_platform_driver(tegra20_spdif_driver);
425
426 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
427 MODULE_DESCRIPTION("Tegra20 SPDIF ASoC driver");
428 MODULE_LICENSE("GPL");
429