1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * mpl3115.c - Support for Freescale MPL3115A2 pressure/temperature sensor
4 *
5 * Copyright (c) 2013 Peter Meerwald <pmeerw@pmeerw.net>
6 *
7 * (7-bit I2C slave address 0x60)
8 *
9 * TODO: FIFO buffer, altimeter mode, oversampling, continuous mode,
10 * user offset correction, raw mode
11 */
12
13 #include <linux/bitfield.h>
14 #include <linux/cleanup.h>
15 #include <linux/delay.h>
16 #include <linux/i2c.h>
17 #include <linux/limits.h>
18 #include <linux/module.h>
19 #include <linux/property.h>
20 #include <linux/unaligned.h>
21
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/events.h>
24 #include <linux/iio/iio.h>
25 #include <linux/iio/sysfs.h>
26 #include <linux/iio/triggered_buffer.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/trigger.h>
29
30 #define MPL3115_STATUS 0x00
31 #define MPL3115_OUT_PRESS 0x01 /* MSB first, 20 bit */
32 #define MPL3115_OUT_TEMP 0x04 /* MSB first, 12 bit */
33 #define MPL3115_WHO_AM_I 0x0c
34 #define MPL3115_INT_SOURCE 0x12
35 #define MPL3115_PT_DATA_CFG 0x13
36 #define MPL3115_PRESS_TGT 0x16 /* MSB first, 16 bit */
37 #define MPL3115_TEMP_TGT 0x18
38 #define MPL3115_CTRL_REG1 0x26
39 #define MPL3115_CTRL_REG2 0x27
40 #define MPL3115_CTRL_REG3 0x28
41 #define MPL3115_CTRL_REG4 0x29
42 #define MPL3115_CTRL_REG5 0x2a
43
44 #define MPL3115_DEVICE_ID 0xc4
45
46 #define MPL3115_STATUS_PRESS_RDY BIT(2)
47 #define MPL3115_STATUS_TEMP_RDY BIT(1)
48
49 #define MPL3115_INT_SRC_DRDY BIT(7)
50 #define MPL3115_INT_SRC_PTH BIT(3)
51 #define MPL3115_INT_SRC_TTH BIT(2)
52
53 #define MPL3115_PT_DATA_EVENT_ALL GENMASK(2, 0)
54
55 #define MPL3115_CTRL1_RESET BIT(2) /* software reset */
56 #define MPL3115_CTRL1_OST BIT(1) /* initiate measurement */
57 #define MPL3115_CTRL1_ACTIVE BIT(0) /* continuous measurement */
58 #define MPL3115_CTRL1_OS_258MS GENMASK(5, 4) /* 64x oversampling */
59
60 #define MPL3115_CTRL2_ST GENMASK(3, 0)
61
62 #define MPL3115_CTRL3_IPOL1 BIT(5)
63 #define MPL3115_CTRL3_IPOL2 BIT(1)
64
65 #define MPL3115_CTRL4_INT_EN_DRDY BIT(7)
66 #define MPL3115_CTRL4_INT_EN_PTH BIT(3)
67 #define MPL3115_CTRL4_INT_EN_TTH BIT(2)
68
69 #define MPL3115_CTRL5_INT_CFG_DRDY BIT(7)
70
71 static const unsigned int mpl3115_samp_freq_table[][2] = {
72 { 1, 0 },
73 { 0, 500000 },
74 { 0, 250000 },
75 { 0, 125000 },
76 { 0, 62500 },
77 { 0, 31250 },
78 { 0, 15625 },
79 { 0, 7812 },
80 { 0, 3906 },
81 { 0, 1953 },
82 { 0, 976 },
83 { 0, 488 },
84 { 0, 244 },
85 { 0, 122 },
86 { 0, 61 },
87 { 0, 30 },
88 };
89
90 struct mpl3115_data {
91 struct i2c_client *client;
92 struct iio_trigger *drdy_trig;
93 struct mutex lock;
94 u8 ctrl_reg1;
95 u8 ctrl_reg4;
96 };
97
98 enum mpl3115_irq_pin {
99 MPL3115_IRQ_INT1,
100 MPL3115_IRQ_INT2,
101 };
102
mpl3115_request(struct mpl3115_data * data)103 static int mpl3115_request(struct mpl3115_data *data)
104 {
105 int ret, tries = 15;
106
107 /* trigger measurement */
108 ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG1,
109 data->ctrl_reg1 | MPL3115_CTRL1_OST);
110 if (ret < 0)
111 return ret;
112
113 while (tries-- > 0) {
114 ret = i2c_smbus_read_byte_data(data->client, MPL3115_CTRL_REG1);
115 if (ret < 0)
116 return ret;
117 /* wait for data ready, i.e. OST cleared */
118 if (!(ret & MPL3115_CTRL1_OST))
119 break;
120 msleep(20);
121 }
122
123 if (tries < 0) {
124 dev_err(&data->client->dev, "data not ready\n");
125 return -EIO;
126 }
127
128 return 0;
129 }
130
mpl3115_read_info_raw(struct mpl3115_data * data,struct iio_chan_spec const * chan,int * val)131 static int mpl3115_read_info_raw(struct mpl3115_data *data,
132 struct iio_chan_spec const *chan, int *val)
133 {
134 int ret;
135
136 switch (chan->type) {
137 case IIO_PRESSURE: { /* in 0.25 pascal / LSB */
138 u8 press_be24[3];
139
140 guard(mutex)(&data->lock);
141 ret = mpl3115_request(data);
142 if (ret < 0)
143 return ret;
144
145 ret = i2c_smbus_read_i2c_block_data(data->client,
146 MPL3115_OUT_PRESS,
147 sizeof(press_be24),
148 press_be24);
149 if (ret < 0)
150 return ret;
151
152 /*
153 * The pressure channel shift is applied in the case where the
154 * data (24-bit big endian) is read into a 32-bit buffer. Here
155 * the data is stored in a 24-bit buffer, so the shift is 4.
156 */
157 *val = get_unaligned_be24(press_be24) >> 4;
158 return IIO_VAL_INT;
159 }
160 case IIO_TEMP: { /* in 0.0625 celsius / LSB */
161 __be16 tmp;
162
163 guard(mutex)(&data->lock);
164 ret = mpl3115_request(data);
165 if (ret < 0)
166 return ret;
167
168 ret = i2c_smbus_read_i2c_block_data(data->client,
169 MPL3115_OUT_TEMP,
170 2, (u8 *) &tmp);
171 if (ret < 0)
172 return ret;
173
174 *val = sign_extend32(be16_to_cpu(tmp) >> chan->scan_type.shift,
175 chan->scan_type.realbits - 1);
176 return IIO_VAL_INT;
177 }
178 default:
179 return -EINVAL;
180 }
181 }
182
mpl3115_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)183 static int mpl3115_read_raw(struct iio_dev *indio_dev,
184 struct iio_chan_spec const *chan,
185 int *val, int *val2, long mask)
186 {
187 struct mpl3115_data *data = iio_priv(indio_dev);
188 int ret;
189
190 switch (mask) {
191 case IIO_CHAN_INFO_RAW:
192 if (!iio_device_claim_direct(indio_dev))
193 return -EBUSY;
194
195 ret = mpl3115_read_info_raw(data, chan, val);
196 iio_device_release_direct(indio_dev);
197 return ret;
198
199 case IIO_CHAN_INFO_SCALE:
200 switch (chan->type) {
201 case IIO_PRESSURE:
202 *val = 0;
203 *val2 = 250; /* want kilopascal */
204 return IIO_VAL_INT_PLUS_MICRO;
205 case IIO_TEMP:
206 *val = 0;
207 *val2 = 62500;
208 return IIO_VAL_INT_PLUS_MICRO;
209 default:
210 return -EINVAL;
211 }
212 case IIO_CHAN_INFO_SAMP_FREQ:
213 ret = i2c_smbus_read_byte_data(data->client, MPL3115_CTRL_REG2);
214 if (ret < 0)
215 return ret;
216
217 ret = FIELD_GET(MPL3115_CTRL2_ST, ret);
218
219 *val = mpl3115_samp_freq_table[ret][0];
220 *val2 = mpl3115_samp_freq_table[ret][1];
221 return IIO_VAL_INT_PLUS_MICRO;
222 }
223 return -EINVAL;
224 }
225
mpl3115_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)226 static int mpl3115_read_avail(struct iio_dev *indio_dev,
227 struct iio_chan_spec const *chan,
228 const int **vals, int *type, int *length,
229 long mask)
230 {
231 if (mask != IIO_CHAN_INFO_SAMP_FREQ)
232 return -EINVAL;
233
234 *type = IIO_VAL_INT_PLUS_MICRO;
235 *length = ARRAY_SIZE(mpl3115_samp_freq_table) * 2;
236 *vals = (int *)mpl3115_samp_freq_table;
237 return IIO_AVAIL_LIST;
238 }
239
mpl3115_write_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int val,int val2,long mask)240 static int mpl3115_write_raw(struct iio_dev *indio_dev,
241 const struct iio_chan_spec *chan,
242 int val, int val2, long mask)
243 {
244 struct mpl3115_data *data = iio_priv(indio_dev);
245 int i, ret;
246
247 if (mask != IIO_CHAN_INFO_SAMP_FREQ)
248 return -EINVAL;
249
250 for (i = 0; i < ARRAY_SIZE(mpl3115_samp_freq_table); i++)
251 if (val == mpl3115_samp_freq_table[i][0] &&
252 val2 == mpl3115_samp_freq_table[i][1])
253 break;
254
255 if (i == ARRAY_SIZE(mpl3115_samp_freq_table))
256 return -EINVAL;
257
258 if (!iio_device_claim_direct(indio_dev))
259 return -EBUSY;
260
261 ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG2,
262 FIELD_PREP(MPL3115_CTRL2_ST, i));
263 iio_device_release_direct(indio_dev);
264 return ret;
265 }
266
mpl3115_fill_trig_buffer(struct iio_dev * indio_dev,u8 * buffer)267 static int mpl3115_fill_trig_buffer(struct iio_dev *indio_dev, u8 *buffer)
268 {
269 struct mpl3115_data *data = iio_priv(indio_dev);
270 int ret, pos = 0;
271
272 if (!(data->ctrl_reg1 & MPL3115_CTRL1_ACTIVE)) {
273 ret = mpl3115_request(data);
274 if (ret < 0)
275 return ret;
276 }
277
278 if (test_bit(0, indio_dev->active_scan_mask)) {
279 ret = i2c_smbus_read_i2c_block_data(data->client,
280 MPL3115_OUT_PRESS, 3, &buffer[pos]);
281 if (ret < 0)
282 return ret;
283 pos += 4;
284 }
285
286 if (test_bit(1, indio_dev->active_scan_mask)) {
287 ret = i2c_smbus_read_i2c_block_data(data->client,
288 MPL3115_OUT_TEMP, 2, &buffer[pos]);
289 if (ret < 0)
290 return ret;
291 }
292
293 return 0;
294 }
295
mpl3115_trigger_handler(int irq,void * p)296 static irqreturn_t mpl3115_trigger_handler(int irq, void *p)
297 {
298 struct iio_poll_func *pf = p;
299 struct iio_dev *indio_dev = pf->indio_dev;
300 struct mpl3115_data *data = iio_priv(indio_dev);
301 /*
302 * 32-bit channel + 16-bit channel + padding + ts
303 * Note that it is possible for only one of the first 2
304 * channels to be enabled. If that happens, the first element
305 * of the buffer may be either 16 or 32-bits. As such we cannot
306 * use a simple structure definition to express this data layout.
307 */
308 u8 buffer[16] __aligned(8) = { };
309 int ret;
310
311 mutex_lock(&data->lock);
312 ret = mpl3115_fill_trig_buffer(indio_dev, buffer);
313 mutex_unlock(&data->lock);
314 if (ret)
315 goto done;
316
317 iio_push_to_buffers_with_ts(indio_dev, buffer, sizeof(buffer),
318 iio_get_time_ns(indio_dev));
319
320 done:
321 iio_trigger_notify_done(indio_dev->trig);
322 return IRQ_HANDLED;
323 }
324
325 static const struct iio_event_spec mpl3115_temp_press_event[] = {
326 {
327 .type = IIO_EV_TYPE_THRESH,
328 .dir = IIO_EV_DIR_RISING,
329 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
330 BIT(IIO_EV_INFO_VALUE),
331 },
332 };
333
334 static const struct iio_chan_spec mpl3115_channels[] = {
335 {
336 .type = IIO_PRESSURE,
337 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
338 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
339 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
340 .info_mask_shared_by_all_available =
341 BIT(IIO_CHAN_INFO_SAMP_FREQ),
342 .scan_index = 0,
343 .scan_type = {
344 .sign = 'u',
345 .realbits = 20,
346 .storagebits = 32,
347 .shift = 12,
348 .endianness = IIO_BE,
349 },
350 .event_spec = mpl3115_temp_press_event,
351 .num_event_specs = ARRAY_SIZE(mpl3115_temp_press_event),
352 },
353 {
354 .type = IIO_TEMP,
355 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
356 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
357 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
358 .info_mask_shared_by_all_available =
359 BIT(IIO_CHAN_INFO_SAMP_FREQ),
360 .scan_index = 1,
361 .scan_type = {
362 .sign = 's',
363 .realbits = 12,
364 .storagebits = 16,
365 .shift = 4,
366 .endianness = IIO_BE,
367 },
368 .event_spec = mpl3115_temp_press_event,
369 .num_event_specs = ARRAY_SIZE(mpl3115_temp_press_event),
370 },
371 IIO_CHAN_SOFT_TIMESTAMP(2),
372 };
373
mpl3115_interrupt_handler(int irq,void * private)374 static irqreturn_t mpl3115_interrupt_handler(int irq, void *private)
375 {
376 struct iio_dev *indio_dev = private;
377 struct mpl3115_data *data = iio_priv(indio_dev);
378 int ret;
379 u8 val_press[3];
380 __be16 val_temp;
381
382 ret = i2c_smbus_read_byte_data(data->client, MPL3115_INT_SOURCE);
383 if (ret < 0)
384 return IRQ_HANDLED;
385
386 if (!(ret & (MPL3115_INT_SRC_TTH | MPL3115_INT_SRC_PTH |
387 MPL3115_INT_SRC_DRDY)))
388 return IRQ_NONE;
389
390 if (ret & MPL3115_INT_SRC_DRDY)
391 iio_trigger_poll_nested(data->drdy_trig);
392
393 if (ret & MPL3115_INT_SRC_PTH) {
394 iio_push_event(indio_dev,
395 IIO_UNMOD_EVENT_CODE(IIO_PRESSURE, 0,
396 IIO_EV_TYPE_THRESH,
397 IIO_EV_DIR_RISING),
398 iio_get_time_ns(indio_dev));
399
400 /* Reset the SRC_PTH bit in INT_SOURCE */
401 i2c_smbus_read_i2c_block_data(data->client,
402 MPL3115_OUT_PRESS,
403 sizeof(val_press), val_press);
404 }
405
406 if (ret & MPL3115_INT_SRC_TTH) {
407 iio_push_event(indio_dev,
408 IIO_UNMOD_EVENT_CODE(IIO_TEMP, 0,
409 IIO_EV_TYPE_THRESH,
410 IIO_EV_DIR_RISING),
411 iio_get_time_ns(indio_dev));
412
413 /* Reset the SRC_TTH bit in INT_SOURCE */
414 i2c_smbus_read_i2c_block_data(data->client,
415 MPL3115_OUT_TEMP,
416 sizeof(val_temp),
417 (u8 *)&val_temp);
418 }
419
420 return IRQ_HANDLED;
421 }
422
mpl3115_config_interrupt(struct mpl3115_data * data,u8 ctrl_reg1,u8 ctrl_reg4)423 static int mpl3115_config_interrupt(struct mpl3115_data *data,
424 u8 ctrl_reg1, u8 ctrl_reg4)
425 {
426 int ret;
427
428 ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG1,
429 ctrl_reg1);
430 if (ret < 0)
431 return ret;
432
433 ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG4,
434 ctrl_reg4);
435 if (ret < 0)
436 goto reg1_cleanup;
437
438 data->ctrl_reg1 = ctrl_reg1;
439 data->ctrl_reg4 = ctrl_reg4;
440
441 return 0;
442
443 reg1_cleanup:
444 i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG1,
445 data->ctrl_reg1);
446 return ret;
447 }
448
mpl3115_set_trigger_state(struct iio_trigger * trig,bool state)449 static int mpl3115_set_trigger_state(struct iio_trigger *trig, bool state)
450 {
451 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
452 struct mpl3115_data *data = iio_priv(indio_dev);
453 u8 ctrl_reg1, ctrl_reg4;
454
455 guard(mutex)(&data->lock);
456
457 ctrl_reg1 = data->ctrl_reg1;
458 ctrl_reg4 = data->ctrl_reg4;
459
460 if (state) {
461 ctrl_reg1 |= MPL3115_CTRL1_ACTIVE;
462 ctrl_reg4 |= MPL3115_CTRL4_INT_EN_DRDY;
463 } else {
464 ctrl_reg4 &= ~MPL3115_CTRL4_INT_EN_DRDY;
465
466 if (!ctrl_reg4)
467 ctrl_reg1 &= ~MPL3115_CTRL1_ACTIVE;
468 }
469
470 return mpl3115_config_interrupt(data, ctrl_reg1, ctrl_reg4);
471 }
472
473 static const struct iio_trigger_ops mpl3115_trigger_ops = {
474 .set_trigger_state = mpl3115_set_trigger_state,
475 };
476
mpl3115_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)477 static int mpl3115_read_event_config(struct iio_dev *indio_dev,
478 const struct iio_chan_spec *chan,
479 enum iio_event_type type,
480 enum iio_event_direction dir)
481 {
482 struct mpl3115_data *data = iio_priv(indio_dev);
483
484 if (chan->type == IIO_PRESSURE)
485 return !!(data->ctrl_reg4 & MPL3115_CTRL4_INT_EN_PTH);
486
487 if (chan->type == IIO_TEMP)
488 return !!(data->ctrl_reg4 & MPL3115_CTRL4_INT_EN_TTH);
489
490 return -EINVAL;
491 }
492
mpl3115_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)493 static int mpl3115_write_event_config(struct iio_dev *indio_dev,
494 const struct iio_chan_spec *chan,
495 enum iio_event_type type,
496 enum iio_event_direction dir,
497 bool state)
498 {
499 struct mpl3115_data *data = iio_priv(indio_dev);
500 u8 int_en_mask;
501 u8 ctrl_reg1, ctrl_reg4;
502
503 switch (chan->type) {
504 case IIO_PRESSURE:
505 int_en_mask = MPL3115_CTRL4_INT_EN_PTH;
506 break;
507 case IIO_TEMP:
508 int_en_mask = MPL3115_CTRL4_INT_EN_TTH;
509 break;
510 default:
511 return -EINVAL;
512 }
513
514 guard(mutex)(&data->lock);
515
516 ctrl_reg1 = data->ctrl_reg1;
517 ctrl_reg4 = data->ctrl_reg4;
518
519 if (state) {
520 ctrl_reg1 |= MPL3115_CTRL1_ACTIVE;
521 ctrl_reg4 |= int_en_mask;
522 } else {
523 ctrl_reg4 &= ~int_en_mask;
524
525 if (!ctrl_reg4)
526 ctrl_reg1 &= ~MPL3115_CTRL1_ACTIVE;
527 }
528
529 return mpl3115_config_interrupt(data, ctrl_reg1, ctrl_reg4);
530 }
531
mpl3115_read_thresh(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)532 static int mpl3115_read_thresh(struct iio_dev *indio_dev,
533 const struct iio_chan_spec *chan,
534 enum iio_event_type type,
535 enum iio_event_direction dir,
536 enum iio_event_info info,
537 int *val, int *val2)
538 {
539 struct mpl3115_data *data = iio_priv(indio_dev);
540 int ret;
541 __be16 press_tgt;
542
543 if (info != IIO_EV_INFO_VALUE)
544 return -EINVAL;
545
546 switch (chan->type) {
547 case IIO_PRESSURE:
548 ret = i2c_smbus_read_i2c_block_data(data->client,
549 MPL3115_PRESS_TGT,
550 sizeof(press_tgt),
551 (u8 *)&press_tgt);
552 if (ret < 0)
553 return ret;
554
555 /*
556 * Target value for the pressure is 16-bit unsigned value,
557 * expressed in 2 Pa units
558 */
559 *val = be16_to_cpu(press_tgt) << 1;
560
561 return IIO_VAL_INT;
562 case IIO_TEMP:
563 ret = i2c_smbus_read_byte_data(data->client, MPL3115_TEMP_TGT);
564 if (ret < 0)
565 return ret;
566
567 /* Target value for the temperature is 8-bit 2's complement */
568 *val = sign_extend32(ret, 7);
569
570 return IIO_VAL_INT;
571 default:
572 return -EINVAL;
573 }
574 }
575
mpl3115_write_thresh(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)576 static int mpl3115_write_thresh(struct iio_dev *indio_dev,
577 const struct iio_chan_spec *chan,
578 enum iio_event_type type,
579 enum iio_event_direction dir,
580 enum iio_event_info info,
581 int val, int val2)
582 {
583 struct mpl3115_data *data = iio_priv(indio_dev);
584 __be16 press_tgt;
585
586 if (info != IIO_EV_INFO_VALUE)
587 return -EINVAL;
588
589 switch (chan->type) {
590 case IIO_PRESSURE:
591 val >>= 1;
592
593 if (val < 0 || val > U16_MAX)
594 return -EINVAL;
595
596 press_tgt = cpu_to_be16(val);
597
598 return i2c_smbus_write_i2c_block_data(data->client,
599 MPL3115_PRESS_TGT,
600 sizeof(press_tgt),
601 (u8 *)&press_tgt);
602 case IIO_TEMP:
603 if (val < S8_MIN || val > S8_MAX)
604 return -EINVAL;
605
606 return i2c_smbus_write_byte_data(data->client,
607 MPL3115_TEMP_TGT, val);
608 default:
609 return -EINVAL;
610 }
611 }
612
613 static const struct iio_info mpl3115_info = {
614 .read_raw = &mpl3115_read_raw,
615 .read_avail = &mpl3115_read_avail,
616 .write_raw = &mpl3115_write_raw,
617 .read_event_config = mpl3115_read_event_config,
618 .write_event_config = mpl3115_write_event_config,
619 .read_event_value = mpl3115_read_thresh,
620 .write_event_value = mpl3115_write_thresh,
621 };
622
mpl3115_trigger_probe(struct mpl3115_data * data,struct iio_dev * indio_dev)623 static int mpl3115_trigger_probe(struct mpl3115_data *data,
624 struct iio_dev *indio_dev)
625 {
626 struct fwnode_handle *fwnode = dev_fwnode(&data->client->dev);
627 int ret, irq, irq_type, irq_pin = MPL3115_IRQ_INT1;
628
629 irq = fwnode_irq_get_byname(fwnode, "INT1");
630 if (irq < 0) {
631 irq = fwnode_irq_get_byname(fwnode, "INT2");
632 if (irq < 0)
633 return 0;
634
635 irq_pin = MPL3115_IRQ_INT2;
636 }
637
638 irq_type = irq_get_trigger_type(irq);
639 if (irq_type != IRQF_TRIGGER_RISING && irq_type != IRQF_TRIGGER_FALLING)
640 return -EINVAL;
641
642 ret = i2c_smbus_write_byte_data(data->client, MPL3115_PT_DATA_CFG,
643 MPL3115_PT_DATA_EVENT_ALL);
644 if (ret < 0)
645 return ret;
646
647 if (irq_pin == MPL3115_IRQ_INT1) {
648 ret = i2c_smbus_write_byte_data(data->client,
649 MPL3115_CTRL_REG5,
650 MPL3115_CTRL5_INT_CFG_DRDY);
651 if (ret)
652 return ret;
653
654 if (irq_type == IRQF_TRIGGER_RISING) {
655 ret = i2c_smbus_write_byte_data(data->client,
656 MPL3115_CTRL_REG3,
657 MPL3115_CTRL3_IPOL1);
658 if (ret)
659 return ret;
660 }
661 } else if (irq_type == IRQF_TRIGGER_RISING) {
662 ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG3,
663 MPL3115_CTRL3_IPOL2);
664 if (ret)
665 return ret;
666 }
667
668 data->drdy_trig = devm_iio_trigger_alloc(&data->client->dev,
669 "%s-dev%d",
670 indio_dev->name,
671 iio_device_id(indio_dev));
672 if (!data->drdy_trig)
673 return -ENOMEM;
674
675 data->drdy_trig->ops = &mpl3115_trigger_ops;
676 iio_trigger_set_drvdata(data->drdy_trig, indio_dev);
677
678 ret = devm_request_threaded_irq(&data->client->dev, irq, NULL,
679 mpl3115_interrupt_handler,
680 IRQF_ONESHOT,
681 "mpl3115_irq", indio_dev);
682 if (ret)
683 return ret;
684
685 ret = devm_iio_trigger_register(&data->client->dev, data->drdy_trig);
686 if (ret)
687 return ret;
688
689 indio_dev->trig = iio_trigger_get(data->drdy_trig);
690
691 return 0;
692 }
693
mpl3115_probe(struct i2c_client * client)694 static int mpl3115_probe(struct i2c_client *client)
695 {
696 const struct i2c_device_id *id = i2c_client_get_device_id(client);
697 struct mpl3115_data *data;
698 struct iio_dev *indio_dev;
699 int ret;
700
701 ret = i2c_smbus_read_byte_data(client, MPL3115_WHO_AM_I);
702 if (ret < 0)
703 return ret;
704 if (ret != MPL3115_DEVICE_ID)
705 return -ENODEV;
706
707 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
708 if (!indio_dev)
709 return -ENOMEM;
710
711 data = iio_priv(indio_dev);
712 data->client = client;
713 mutex_init(&data->lock);
714
715 i2c_set_clientdata(client, indio_dev);
716 indio_dev->info = &mpl3115_info;
717 indio_dev->name = id->name;
718 indio_dev->modes = INDIO_DIRECT_MODE;
719 indio_dev->channels = mpl3115_channels;
720 indio_dev->num_channels = ARRAY_SIZE(mpl3115_channels);
721
722 /* software reset, I2C transfer is aborted (fails) */
723 i2c_smbus_write_byte_data(client, MPL3115_CTRL_REG1,
724 MPL3115_CTRL1_RESET);
725 msleep(50);
726
727 data->ctrl_reg1 = MPL3115_CTRL1_OS_258MS;
728 ret = i2c_smbus_write_byte_data(client, MPL3115_CTRL_REG1,
729 data->ctrl_reg1);
730 if (ret < 0)
731 return ret;
732
733 ret = mpl3115_trigger_probe(data, indio_dev);
734 if (ret)
735 return ret;
736
737 ret = iio_triggered_buffer_setup(indio_dev, NULL,
738 mpl3115_trigger_handler, NULL);
739 if (ret < 0)
740 return ret;
741
742 ret = iio_device_register(indio_dev);
743 if (ret < 0)
744 goto buffer_cleanup;
745 return 0;
746
747 buffer_cleanup:
748 iio_triggered_buffer_cleanup(indio_dev);
749 return ret;
750 }
751
mpl3115_standby(struct mpl3115_data * data)752 static int mpl3115_standby(struct mpl3115_data *data)
753 {
754 return i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG1,
755 data->ctrl_reg1 & ~MPL3115_CTRL1_ACTIVE);
756 }
757
mpl3115_remove(struct i2c_client * client)758 static void mpl3115_remove(struct i2c_client *client)
759 {
760 struct iio_dev *indio_dev = i2c_get_clientdata(client);
761
762 iio_device_unregister(indio_dev);
763 iio_triggered_buffer_cleanup(indio_dev);
764 mpl3115_standby(iio_priv(indio_dev));
765 }
766
mpl3115_suspend(struct device * dev)767 static int mpl3115_suspend(struct device *dev)
768 {
769 return mpl3115_standby(iio_priv(i2c_get_clientdata(
770 to_i2c_client(dev))));
771 }
772
mpl3115_resume(struct device * dev)773 static int mpl3115_resume(struct device *dev)
774 {
775 struct mpl3115_data *data = iio_priv(i2c_get_clientdata(
776 to_i2c_client(dev)));
777
778 return i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG1,
779 data->ctrl_reg1);
780 }
781
782 static DEFINE_SIMPLE_DEV_PM_OPS(mpl3115_pm_ops, mpl3115_suspend,
783 mpl3115_resume);
784
785 static const struct i2c_device_id mpl3115_id[] = {
786 { "mpl3115" },
787 { }
788 };
789 MODULE_DEVICE_TABLE(i2c, mpl3115_id);
790
791 static const struct of_device_id mpl3115_of_match[] = {
792 { .compatible = "fsl,mpl3115" },
793 { }
794 };
795 MODULE_DEVICE_TABLE(of, mpl3115_of_match);
796
797 static struct i2c_driver mpl3115_driver = {
798 .driver = {
799 .name = "mpl3115",
800 .of_match_table = mpl3115_of_match,
801 .pm = pm_sleep_ptr(&mpl3115_pm_ops),
802 },
803 .probe = mpl3115_probe,
804 .remove = mpl3115_remove,
805 .id_table = mpl3115_id,
806 };
807 module_i2c_driver(mpl3115_driver);
808
809 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
810 MODULE_DESCRIPTION("Freescale MPL3115 pressure/temperature driver");
811 MODULE_LICENSE("GPL");
812