1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright 2024 Fiona Klute
3 *
4 * Based on code originally in rtw8723d.[ch],
5 * Copyright(c) 2018-2019 Realtek Corporation
6 */
7
8 #include "main.h"
9 #include "debug.h"
10 #include "phy.h"
11 #include "reg.h"
12 #include "tx.h"
13 #include "rtw8723x.h"
14
15 static const struct rtw_hw_reg rtw8723x_txagc[] = {
16 [DESC_RATE1M] = { .addr = 0xe08, .mask = 0x0000ff00 },
17 [DESC_RATE2M] = { .addr = 0x86c, .mask = 0x0000ff00 },
18 [DESC_RATE5_5M] = { .addr = 0x86c, .mask = 0x00ff0000 },
19 [DESC_RATE11M] = { .addr = 0x86c, .mask = 0xff000000 },
20 [DESC_RATE6M] = { .addr = 0xe00, .mask = 0x000000ff },
21 [DESC_RATE9M] = { .addr = 0xe00, .mask = 0x0000ff00 },
22 [DESC_RATE12M] = { .addr = 0xe00, .mask = 0x00ff0000 },
23 [DESC_RATE18M] = { .addr = 0xe00, .mask = 0xff000000 },
24 [DESC_RATE24M] = { .addr = 0xe04, .mask = 0x000000ff },
25 [DESC_RATE36M] = { .addr = 0xe04, .mask = 0x0000ff00 },
26 [DESC_RATE48M] = { .addr = 0xe04, .mask = 0x00ff0000 },
27 [DESC_RATE54M] = { .addr = 0xe04, .mask = 0xff000000 },
28 [DESC_RATEMCS0] = { .addr = 0xe10, .mask = 0x000000ff },
29 [DESC_RATEMCS1] = { .addr = 0xe10, .mask = 0x0000ff00 },
30 [DESC_RATEMCS2] = { .addr = 0xe10, .mask = 0x00ff0000 },
31 [DESC_RATEMCS3] = { .addr = 0xe10, .mask = 0xff000000 },
32 [DESC_RATEMCS4] = { .addr = 0xe14, .mask = 0x000000ff },
33 [DESC_RATEMCS5] = { .addr = 0xe14, .mask = 0x0000ff00 },
34 [DESC_RATEMCS6] = { .addr = 0xe14, .mask = 0x00ff0000 },
35 [DESC_RATEMCS7] = { .addr = 0xe14, .mask = 0xff000000 },
36 };
37
__rtw8723x_lck(struct rtw_dev * rtwdev)38 static void __rtw8723x_lck(struct rtw_dev *rtwdev)
39 {
40 u32 lc_cal;
41 u8 val_ctx, rf_val;
42 int ret;
43
44 val_ctx = rtw_read8(rtwdev, REG_CTX);
45 if ((val_ctx & BIT_MASK_CTX_TYPE) != 0)
46 rtw_write8(rtwdev, REG_CTX, val_ctx & ~BIT_MASK_CTX_TYPE);
47 else
48 rtw_write8(rtwdev, REG_TXPAUSE, 0xFF);
49 lc_cal = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK);
50
51 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal | BIT_LCK);
52
53 ret = read_poll_timeout(rtw_read_rf, rf_val, rf_val != 0x1,
54 10000, 1000000, false,
55 rtwdev, RF_PATH_A, RF_CFGCH, BIT_LCK);
56 if (ret)
57 rtw_warn(rtwdev, "failed to poll LCK status bit\n");
58
59 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal);
60 if ((val_ctx & BIT_MASK_CTX_TYPE) != 0)
61 rtw_write8(rtwdev, REG_CTX, val_ctx);
62 else
63 rtw_write8(rtwdev, REG_TXPAUSE, 0x00);
64 }
65
66 #define DBG_EFUSE_VAL(rtwdev, map, name) \
67 rtw_dbg(rtwdev, RTW_DBG_EFUSE, # name "=0x%02x\n", \
68 (map)->name)
69 #define DBG_EFUSE_2BYTE(rtwdev, map, name) \
70 rtw_dbg(rtwdev, RTW_DBG_EFUSE, # name "=0x%02x%02x\n", \
71 (map)->name[0], (map)->name[1])
72 #define DBG_EFUSE_FIX(rtwdev, name) \
73 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "Fixed invalid EFUSE value: " \
74 # name "=0x%x\n", rtwdev->efuse.name)
75
rtw8723xe_efuse_debug(struct rtw_dev * rtwdev,struct rtw8723x_efuse * map)76 static void rtw8723xe_efuse_debug(struct rtw_dev *rtwdev,
77 struct rtw8723x_efuse *map)
78 {
79 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "mac_addr=%pM\n", map->e.mac_addr);
80 DBG_EFUSE_2BYTE(rtwdev, map, e.vendor_id);
81 DBG_EFUSE_2BYTE(rtwdev, map, e.device_id);
82 DBG_EFUSE_2BYTE(rtwdev, map, e.sub_vendor_id);
83 DBG_EFUSE_2BYTE(rtwdev, map, e.sub_device_id);
84 }
85
rtw8723xu_efuse_debug(struct rtw_dev * rtwdev,struct rtw8723x_efuse * map)86 static void rtw8723xu_efuse_debug(struct rtw_dev *rtwdev,
87 struct rtw8723x_efuse *map)
88 {
89 DBG_EFUSE_2BYTE(rtwdev, map, u.vendor_id);
90 DBG_EFUSE_2BYTE(rtwdev, map, u.product_id);
91 DBG_EFUSE_VAL(rtwdev, map, u.usb_option);
92 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "mac_addr=%pM\n", map->u.mac_addr);
93 }
94
rtw8723xs_efuse_debug(struct rtw_dev * rtwdev,struct rtw8723x_efuse * map)95 static void rtw8723xs_efuse_debug(struct rtw_dev *rtwdev,
96 struct rtw8723x_efuse *map)
97 {
98 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "mac_addr=%pM\n", map->s.mac_addr);
99 }
100
__rtw8723x_debug_txpwr_limit(struct rtw_dev * rtwdev,struct rtw_txpwr_idx * table,int tx_path_count)101 static void __rtw8723x_debug_txpwr_limit(struct rtw_dev *rtwdev,
102 struct rtw_txpwr_idx *table,
103 int tx_path_count)
104 {
105 if (!rtw_dbg_is_enabled(rtwdev, RTW_DBG_EFUSE))
106 return;
107
108 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
109 "Power index table (2.4G):\n");
110 /* CCK base */
111 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "CCK base\n");
112 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF G0 G1 G2 G3 G4 G5\n");
113 for (int i = 0; i < tx_path_count; i++)
114 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
115 "[%c]: %3u %3u %3u %3u %3u %3u\n",
116 'A' + i,
117 table[i].pwr_idx_2g.cck_base[0],
118 table[i].pwr_idx_2g.cck_base[1],
119 table[i].pwr_idx_2g.cck_base[2],
120 table[i].pwr_idx_2g.cck_base[3],
121 table[i].pwr_idx_2g.cck_base[4],
122 table[i].pwr_idx_2g.cck_base[5]);
123 /* CCK diff */
124 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "CCK diff\n");
125 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF 1S 2S 3S 4S\n");
126 for (int i = 0; i < tx_path_count; i++)
127 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
128 "[%c]: %2d %2d %2d %2d\n",
129 'A' + i, 0 /* no diff for 1S */,
130 table[i].pwr_idx_2g.ht_2s_diff.cck,
131 table[i].pwr_idx_2g.ht_3s_diff.cck,
132 table[i].pwr_idx_2g.ht_4s_diff.cck);
133 /* BW40-1S base */
134 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "BW40-1S base\n");
135 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF G0 G1 G2 G3 G4\n");
136 for (int i = 0; i < tx_path_count; i++)
137 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
138 "[%c]: %3u %3u %3u %3u %3u\n",
139 'A' + i,
140 table[i].pwr_idx_2g.bw40_base[0],
141 table[i].pwr_idx_2g.bw40_base[1],
142 table[i].pwr_idx_2g.bw40_base[2],
143 table[i].pwr_idx_2g.bw40_base[3],
144 table[i].pwr_idx_2g.bw40_base[4]);
145 /* OFDM diff */
146 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "OFDM diff\n");
147 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF 1S 2S 3S 4S\n");
148 for (int i = 0; i < tx_path_count; i++)
149 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
150 "[%c]: %2d %2d %2d %2d\n",
151 'A' + i,
152 table[i].pwr_idx_2g.ht_1s_diff.ofdm,
153 table[i].pwr_idx_2g.ht_2s_diff.ofdm,
154 table[i].pwr_idx_2g.ht_3s_diff.ofdm,
155 table[i].pwr_idx_2g.ht_4s_diff.ofdm);
156 /* BW20 diff */
157 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "BW20 diff\n");
158 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF 1S 2S 3S 4S\n");
159 for (int i = 0; i < tx_path_count; i++)
160 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
161 "[%c]: %2d %2d %2d %2d\n",
162 'A' + i,
163 table[i].pwr_idx_2g.ht_1s_diff.bw20,
164 table[i].pwr_idx_2g.ht_2s_diff.bw20,
165 table[i].pwr_idx_2g.ht_3s_diff.bw20,
166 table[i].pwr_idx_2g.ht_4s_diff.bw20);
167 /* BW40 diff */
168 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "BW40 diff\n");
169 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF 1S 2S 3S 4S\n");
170 for (int i = 0; i < tx_path_count; i++)
171 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
172 "[%c]: %2d %2d %2d %2d\n",
173 'A' + i, 0 /* no diff for 1S */,
174 table[i].pwr_idx_2g.ht_2s_diff.bw40,
175 table[i].pwr_idx_2g.ht_3s_diff.bw40,
176 table[i].pwr_idx_2g.ht_4s_diff.bw40);
177 }
178
efuse_debug_dump(struct rtw_dev * rtwdev,struct rtw8723x_efuse * map)179 static void efuse_debug_dump(struct rtw_dev *rtwdev,
180 struct rtw8723x_efuse *map)
181 {
182 if (!rtw_dbg_is_enabled(rtwdev, RTW_DBG_EFUSE))
183 return;
184
185 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "EFUSE raw logical map:\n");
186 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1,
187 (u8 *)map, sizeof(struct rtw8723x_efuse), false);
188 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "Parsed rtw8723x EFUSE data:\n");
189 DBG_EFUSE_VAL(rtwdev, map, rtl_id);
190 DBG_EFUSE_VAL(rtwdev, map, afe);
191 rtw8723x_debug_txpwr_limit(rtwdev, map->txpwr_idx_table, 4);
192 DBG_EFUSE_VAL(rtwdev, map, channel_plan);
193 DBG_EFUSE_VAL(rtwdev, map, xtal_k);
194 DBG_EFUSE_VAL(rtwdev, map, thermal_meter);
195 DBG_EFUSE_VAL(rtwdev, map, iqk_lck);
196 DBG_EFUSE_VAL(rtwdev, map, pa_type);
197 DBG_EFUSE_2BYTE(rtwdev, map, lna_type_2g);
198 DBG_EFUSE_2BYTE(rtwdev, map, lna_type_5g);
199 DBG_EFUSE_VAL(rtwdev, map, rf_board_option);
200 DBG_EFUSE_VAL(rtwdev, map, rf_feature_option);
201 DBG_EFUSE_VAL(rtwdev, map, rf_bt_setting);
202 DBG_EFUSE_VAL(rtwdev, map, eeprom_version);
203 DBG_EFUSE_VAL(rtwdev, map, eeprom_customer_id);
204 DBG_EFUSE_VAL(rtwdev, map, tx_bb_swing_setting_2g);
205 DBG_EFUSE_VAL(rtwdev, map, tx_pwr_calibrate_rate);
206 DBG_EFUSE_VAL(rtwdev, map, rf_antenna_option);
207 DBG_EFUSE_VAL(rtwdev, map, rfe_option);
208 DBG_EFUSE_2BYTE(rtwdev, map, country_code);
209
210 switch (rtw_hci_type(rtwdev)) {
211 case RTW_HCI_TYPE_PCIE:
212 rtw8723xe_efuse_debug(rtwdev, map);
213 break;
214 case RTW_HCI_TYPE_USB:
215 rtw8723xu_efuse_debug(rtwdev, map);
216 break;
217 case RTW_HCI_TYPE_SDIO:
218 rtw8723xs_efuse_debug(rtwdev, map);
219 break;
220 default:
221 /* unsupported now */
222 break;
223 }
224 }
225
rtw8723xe_efuse_parsing(struct rtw_efuse * efuse,struct rtw8723x_efuse * map)226 static void rtw8723xe_efuse_parsing(struct rtw_efuse *efuse,
227 struct rtw8723x_efuse *map)
228 {
229 ether_addr_copy(efuse->addr, map->e.mac_addr);
230 }
231
rtw8723xu_efuse_parsing(struct rtw_efuse * efuse,struct rtw8723x_efuse * map)232 static void rtw8723xu_efuse_parsing(struct rtw_efuse *efuse,
233 struct rtw8723x_efuse *map)
234 {
235 ether_addr_copy(efuse->addr, map->u.mac_addr);
236 }
237
rtw8723xs_efuse_parsing(struct rtw_efuse * efuse,struct rtw8723x_efuse * map)238 static void rtw8723xs_efuse_parsing(struct rtw_efuse *efuse,
239 struct rtw8723x_efuse *map)
240 {
241 ether_addr_copy(efuse->addr, map->s.mac_addr);
242 }
243
244 /* Default power index table for RTL8703B/RTL8723D, used if EFUSE does
245 * not contain valid data. Replaces EFUSE data from offset 0x10 (start
246 * of txpwr_idx_table).
247 */
248 static const u8 rtw8723x_txpwr_idx_table[] = {
249 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
250 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02
251 };
252
__rtw8723x_read_efuse(struct rtw_dev * rtwdev,u8 * log_map)253 static int __rtw8723x_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
254 {
255 struct rtw_efuse *efuse = &rtwdev->efuse;
256 u8 *pwr = (u8 *)efuse->txpwr_idx_table;
257 struct rtw8723x_efuse *map;
258 bool valid = false;
259 int i;
260
261 map = (struct rtw8723x_efuse *)log_map;
262 efuse_debug_dump(rtwdev, map);
263
264 efuse->rfe_option = 0;
265 efuse->rf_board_option = map->rf_board_option;
266 efuse->crystal_cap = map->xtal_k;
267 efuse->pa_type_2g = map->pa_type;
268 efuse->lna_type_2g = map->lna_type_2g[0];
269 efuse->channel_plan = map->channel_plan;
270 efuse->country_code[0] = map->country_code[0];
271 efuse->country_code[1] = map->country_code[1];
272 efuse->bt_setting = map->rf_bt_setting;
273 efuse->regd = map->rf_board_option & 0x7;
274 efuse->thermal_meter[0] = map->thermal_meter;
275 efuse->thermal_meter_k = map->thermal_meter;
276 efuse->afe = map->afe;
277
278 for (i = 0; i < 4; i++)
279 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
280
281 switch (rtw_hci_type(rtwdev)) {
282 case RTW_HCI_TYPE_PCIE:
283 rtw8723xe_efuse_parsing(efuse, map);
284 break;
285 case RTW_HCI_TYPE_USB:
286 rtw8723xu_efuse_parsing(efuse, map);
287 break;
288 case RTW_HCI_TYPE_SDIO:
289 rtw8723xs_efuse_parsing(efuse, map);
290 break;
291 default:
292 /* unsupported now */
293 return -EOPNOTSUPP;
294 }
295
296 /* If TX power index table in EFUSE is invalid, fall back to
297 * built-in table.
298 */
299 for (i = 0; i < ARRAY_SIZE(rtw8723x_txpwr_idx_table); i++)
300 if (pwr[i] != 0xff) {
301 valid = true;
302 break;
303 }
304 if (!valid) {
305 for (i = 0; i < ARRAY_SIZE(rtw8723x_txpwr_idx_table); i++)
306 pwr[i] = rtw8723x_txpwr_idx_table[i];
307 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
308 "Replaced invalid EFUSE TX power index table.");
309 rtw8723x_debug_txpwr_limit(rtwdev,
310 efuse->txpwr_idx_table, 2);
311 }
312
313 /* Override invalid antenna settings. */
314 if (efuse->bt_setting == 0xff) {
315 /* shared antenna */
316 efuse->bt_setting |= BIT(0);
317 /* RF path A */
318 efuse->bt_setting &= ~BIT(6);
319 DBG_EFUSE_FIX(rtwdev, bt_setting);
320 }
321
322 /* Override invalid board options: The coex code incorrectly
323 * assumes that if bits 6 & 7 are set the board doesn't
324 * support coex. Regd is also derived from rf_board_option and
325 * should be 0 if there's no valid data.
326 */
327 if (efuse->rf_board_option == 0xff) {
328 efuse->regd = 0;
329 efuse->rf_board_option &= GENMASK(5, 0);
330 DBG_EFUSE_FIX(rtwdev, rf_board_option);
331 }
332
333 /* Override invalid crystal cap setting, default comes from
334 * vendor driver. Chip specific.
335 */
336 if (efuse->crystal_cap == 0xff) {
337 efuse->crystal_cap = 0x20;
338 DBG_EFUSE_FIX(rtwdev, crystal_cap);
339 }
340
341 return 0;
342 }
343
344 #define BIT_CFENDFORM BIT(9)
345 #define BIT_WMAC_TCR_ERR0 BIT(12)
346 #define BIT_WMAC_TCR_ERR1 BIT(13)
347 #define BIT_TCR_CFG (BIT_CFENDFORM | BIT_WMAC_TCR_ERR0 | \
348 BIT_WMAC_TCR_ERR1)
349 #define WLAN_RX_FILTER0 0xFFFF
350 #define WLAN_RX_FILTER1 0x400
351 #define WLAN_RX_FILTER2 0xFFFF
352 #define WLAN_RCR_CFG 0x700060CE
353
__rtw8723x_mac_init(struct rtw_dev * rtwdev)354 static int __rtw8723x_mac_init(struct rtw_dev *rtwdev)
355 {
356 rtw_write32(rtwdev, REG_TCR, BIT_TCR_CFG);
357
358 rtw_write16(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
359 rtwdev->hal.rxfltmap1 = WLAN_RX_FILTER1;
360 rtw_write16(rtwdev, REG_RXFLTMAP1, rtwdev->hal.rxfltmap1);
361 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
362 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
363
364 rtw_write32(rtwdev, REG_INT_MIG, 0);
365 rtw_write32(rtwdev, REG_MCUTST_1, 0x0);
366
367 rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA);
368 rtw_write8(rtwdev, REG_2ND_CCA_CTRL, 0);
369
370 return 0;
371 }
372
__rtw8723x_mac_postinit(struct rtw_dev * rtwdev)373 static int __rtw8723x_mac_postinit(struct rtw_dev *rtwdev)
374 {
375 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);
376
377 return 0;
378 }
379
__rtw8723x_cfg_ldo25(struct rtw_dev * rtwdev,bool enable)380 static void __rtw8723x_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
381 {
382 u8 ldo_pwr;
383
384 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
385 if (enable) {
386 ldo_pwr &= ~BIT_MASK_LDO25_VOLTAGE;
387 ldo_pwr |= (BIT_LDO25_VOLTAGE_V25 << 4) | BIT_LDO25_EN;
388 } else {
389 ldo_pwr &= ~BIT_LDO25_EN;
390 }
391 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
392 }
393
394 static void
rtw8723x_set_tx_power_index_by_rate(struct rtw_dev * rtwdev,u8 path,u8 rs)395 rtw8723x_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs)
396 {
397 struct rtw_hal *hal = &rtwdev->hal;
398 const struct rtw_hw_reg *txagc;
399 u8 rate, pwr_index;
400 int j;
401
402 for (j = 0; j < rtw_rate_size[rs]; j++) {
403 rate = rtw_rate_section[rs][j];
404 pwr_index = hal->tx_pwr_tbl[path][rate];
405
406 if (rate >= ARRAY_SIZE(rtw8723x_txagc)) {
407 rtw_warn(rtwdev, "rate 0x%x isn't supported\n", rate);
408 continue;
409 }
410 txagc = &rtw8723x_txagc[rate];
411 if (!txagc->addr) {
412 rtw_warn(rtwdev, "rate 0x%x isn't defined\n", rate);
413 continue;
414 }
415
416 rtw_write32_mask(rtwdev, txagc->addr, txagc->mask, pwr_index);
417 }
418 }
419
__rtw8723x_set_tx_power_index(struct rtw_dev * rtwdev)420 static void __rtw8723x_set_tx_power_index(struct rtw_dev *rtwdev)
421 {
422 struct rtw_hal *hal = &rtwdev->hal;
423 int rs, path;
424
425 for (path = 0; path < hal->rf_path_num; path++) {
426 for (rs = 0; rs <= RTW_RATE_SECTION_HT_1S; rs++)
427 rtw8723x_set_tx_power_index_by_rate(rtwdev, path, rs);
428 }
429 }
430
__rtw8723x_efuse_grant(struct rtw_dev * rtwdev,bool on)431 static void __rtw8723x_efuse_grant(struct rtw_dev *rtwdev, bool on)
432 {
433 if (on) {
434 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
435
436 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR);
437 rtw_write16_set(rtwdev, REG_SYS_CLKR, BIT_LOADER_CLK_EN | BIT_ANA8M);
438 } else {
439 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
440 }
441 }
442
__rtw8723x_false_alarm_statistics(struct rtw_dev * rtwdev)443 static void __rtw8723x_false_alarm_statistics(struct rtw_dev *rtwdev)
444 {
445 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
446 u32 cck_fa_cnt;
447 u32 ofdm_fa_cnt;
448 u32 crc32_cnt;
449 u32 val32;
450
451 /* hold counter */
452 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 1);
453 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 1);
454 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KEEP, 1);
455 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KEEP, 1);
456
457 cck_fa_cnt = rtw_read32_mask(rtwdev, REG_CCK_FA_LSB_11N, MASKBYTE0);
458 cck_fa_cnt += rtw_read32_mask(rtwdev, REG_CCK_FA_MSB_11N, MASKBYTE3) << 8;
459
460 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE1_11N);
461 ofdm_fa_cnt = u32_get_bits(val32, BIT_MASK_OFDM_FF_CNT);
462 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_SF_CNT);
463 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE2_11N);
464 dm_info->ofdm_cca_cnt = u32_get_bits(val32, BIT_MASK_OFDM_CCA_CNT);
465 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_PF_CNT);
466 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE3_11N);
467 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_RI_CNT);
468 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_CRC_CNT);
469 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE4_11N);
470 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_MNS_CNT);
471
472 dm_info->cck_fa_cnt = cck_fa_cnt;
473 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
474 dm_info->total_fa_cnt = cck_fa_cnt + ofdm_fa_cnt;
475
476 dm_info->cck_err_cnt = rtw_read32(rtwdev, REG_IGI_C_11N);
477 dm_info->cck_ok_cnt = rtw_read32(rtwdev, REG_IGI_D_11N);
478 crc32_cnt = rtw_read32(rtwdev, REG_OFDM_CRC32_CNT_11N);
479 dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_ERR);
480 dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_OK);
481 crc32_cnt = rtw_read32(rtwdev, REG_HT_CRC32_CNT_11N);
482 dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_ERR);
483 dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_OK);
484 dm_info->vht_err_cnt = 0;
485 dm_info->vht_ok_cnt = 0;
486
487 val32 = rtw_read32(rtwdev, REG_CCK_CCA_CNT_11N);
488 dm_info->cck_cca_cnt = (u32_get_bits(val32, BIT_MASK_CCK_FA_MSB) << 8) |
489 u32_get_bits(val32, BIT_MASK_CCK_FA_LSB);
490 dm_info->total_cca_cnt = dm_info->cck_cca_cnt + dm_info->ofdm_cca_cnt;
491
492 /* reset counter */
493 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 1);
494 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0);
495 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 1);
496 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0);
497 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0);
498 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 0);
499 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 0);
500 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 2);
501 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 0);
502 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 2);
503 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 1);
504 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 0);
505 }
506
507 /* IQK (IQ calibration) */
508
509 static
__rtw8723x_iqk_backup_regs(struct rtw_dev * rtwdev,struct rtw8723x_iqk_backup_regs * backup)510 void __rtw8723x_iqk_backup_regs(struct rtw_dev *rtwdev,
511 struct rtw8723x_iqk_backup_regs *backup)
512 {
513 int i;
514
515 for (i = 0; i < RTW8723X_IQK_ADDA_REG_NUM; i++)
516 backup->adda[i] = rtw_read32(rtwdev,
517 rtw8723x_common.iqk_adda_regs[i]);
518
519 for (i = 0; i < RTW8723X_IQK_MAC8_REG_NUM; i++)
520 backup->mac8[i] = rtw_read8(rtwdev,
521 rtw8723x_common.iqk_mac8_regs[i]);
522 for (i = 0; i < RTW8723X_IQK_MAC32_REG_NUM; i++)
523 backup->mac32[i] = rtw_read32(rtwdev,
524 rtw8723x_common.iqk_mac32_regs[i]);
525
526 for (i = 0; i < RTW8723X_IQK_BB_REG_NUM; i++)
527 backup->bb[i] = rtw_read32(rtwdev,
528 rtw8723x_common.iqk_bb_regs[i]);
529
530 backup->igia = rtw_read32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0);
531 backup->igib = rtw_read32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0);
532
533 backup->bb_sel_btg = rtw_read32(rtwdev, REG_BB_SEL_BTG);
534 }
535
536 static
__rtw8723x_iqk_restore_regs(struct rtw_dev * rtwdev,const struct rtw8723x_iqk_backup_regs * backup)537 void __rtw8723x_iqk_restore_regs(struct rtw_dev *rtwdev,
538 const struct rtw8723x_iqk_backup_regs *backup)
539 {
540 int i;
541
542 for (i = 0; i < RTW8723X_IQK_ADDA_REG_NUM; i++)
543 rtw_write32(rtwdev, rtw8723x_common.iqk_adda_regs[i],
544 backup->adda[i]);
545
546 for (i = 0; i < RTW8723X_IQK_MAC8_REG_NUM; i++)
547 rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[i],
548 backup->mac8[i]);
549 for (i = 0; i < RTW8723X_IQK_MAC32_REG_NUM; i++)
550 rtw_write32(rtwdev, rtw8723x_common.iqk_mac32_regs[i],
551 backup->mac32[i]);
552
553 for (i = 0; i < RTW8723X_IQK_BB_REG_NUM; i++)
554 rtw_write32(rtwdev, rtw8723x_common.iqk_bb_regs[i],
555 backup->bb[i]);
556
557 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);
558 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, backup->igia);
559
560 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, 0x50);
561 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, backup->igib);
562
563 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x01008c00);
564 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x01008c00);
565 }
566
567 static
__rtw8723x_iqk_similarity_cmp(struct rtw_dev * rtwdev,s32 result[][IQK_NR],u8 c1,u8 c2)568 bool __rtw8723x_iqk_similarity_cmp(struct rtw_dev *rtwdev,
569 s32 result[][IQK_NR],
570 u8 c1, u8 c2)
571 {
572 u32 i, j, diff;
573 u32 bitmap = 0;
574 u8 candidate[PATH_NR] = {IQK_ROUND_INVALID, IQK_ROUND_INVALID};
575 bool ret = true;
576
577 s32 tmp1, tmp2;
578
579 for (i = 0; i < IQK_NR; i++) {
580 tmp1 = iqkxy_to_s32(result[c1][i]);
581 tmp2 = iqkxy_to_s32(result[c2][i]);
582
583 diff = abs(tmp1 - tmp2);
584
585 if (diff <= MAX_TOLERANCE)
586 continue;
587
588 if ((i == IQK_S1_RX_X || i == IQK_S0_RX_X) && !bitmap) {
589 if (result[c1][i] + result[c1][i + 1] == 0)
590 candidate[i / IQK_SX_NR] = c2;
591 else if (result[c2][i] + result[c2][i + 1] == 0)
592 candidate[i / IQK_SX_NR] = c1;
593 else
594 bitmap |= BIT(i);
595 } else {
596 bitmap |= BIT(i);
597 }
598 }
599
600 if (bitmap != 0)
601 goto check_sim;
602
603 for (i = 0; i < PATH_NR; i++) {
604 if (candidate[i] == IQK_ROUND_INVALID)
605 continue;
606
607 for (j = i * IQK_SX_NR; j < i * IQK_SX_NR + 2; j++)
608 result[IQK_ROUND_HYBRID][j] = result[candidate[i]][j];
609 ret = false;
610 }
611
612 return ret;
613
614 check_sim:
615 for (i = 0; i < IQK_NR; i++) {
616 j = i & ~1; /* 2 bits are a pair for IQ[X, Y] */
617 if (bitmap & GENMASK(j + 1, j))
618 continue;
619
620 result[IQK_ROUND_HYBRID][i] = result[c1][i];
621 }
622
623 return false;
624 }
625
__rtw8723x_pwrtrack_get_limit_ofdm(struct rtw_dev * rtwdev)626 static u8 __rtw8723x_pwrtrack_get_limit_ofdm(struct rtw_dev *rtwdev)
627 {
628 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
629 u8 tx_rate = dm_info->tx_rate;
630 u8 limit_ofdm = 30;
631
632 switch (tx_rate) {
633 case DESC_RATE1M...DESC_RATE5_5M:
634 case DESC_RATE11M:
635 break;
636 case DESC_RATE6M...DESC_RATE48M:
637 limit_ofdm = 36;
638 break;
639 case DESC_RATE54M:
640 limit_ofdm = 34;
641 break;
642 case DESC_RATEMCS0...DESC_RATEMCS2:
643 limit_ofdm = 38;
644 break;
645 case DESC_RATEMCS3...DESC_RATEMCS4:
646 limit_ofdm = 36;
647 break;
648 case DESC_RATEMCS5...DESC_RATEMCS7:
649 limit_ofdm = 34;
650 break;
651 default:
652 rtw_warn(rtwdev, "pwrtrack unhandled tx_rate 0x%x\n", tx_rate);
653 break;
654 }
655
656 return limit_ofdm;
657 }
658
659 static
__rtw8723x_pwrtrack_set_xtal(struct rtw_dev * rtwdev,u8 therm_path,u8 delta)660 void __rtw8723x_pwrtrack_set_xtal(struct rtw_dev *rtwdev, u8 therm_path,
661 u8 delta)
662 {
663 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
664 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
665 const struct rtw_pwr_track_tbl *tbl = rfe_def->pwr_track_tbl;
666 const s8 *pwrtrk_xtal;
667 s8 xtal_cap;
668
669 if (dm_info->thermal_avg[therm_path] >
670 rtwdev->efuse.thermal_meter[therm_path])
671 pwrtrk_xtal = tbl->pwrtrk_xtal_p;
672 else
673 pwrtrk_xtal = tbl->pwrtrk_xtal_n;
674
675 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F;
676 xtal_cap = clamp_t(s8, xtal_cap + pwrtrk_xtal[delta], 0, 0x3F);
677 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL,
678 xtal_cap | (xtal_cap << 6));
679 }
680
681 static
__rtw8723x_fill_txdesc_checksum(struct rtw_dev * rtwdev,struct rtw_tx_pkt_info * pkt_info,u8 * txdesc)682 void __rtw8723x_fill_txdesc_checksum(struct rtw_dev *rtwdev,
683 struct rtw_tx_pkt_info *pkt_info,
684 u8 *txdesc)
685 {
686 size_t words = 32 / 2; /* calculate the first 32 bytes (16 words) */
687 __le16 chksum = 0;
688 __le16 *data = (__le16 *)(txdesc);
689 struct rtw_tx_desc *tx_desc = (struct rtw_tx_desc *)txdesc;
690
691 le32p_replace_bits(&tx_desc->w7, 0, RTW_TX_DESC_W7_TXDESC_CHECKSUM);
692
693 while (words--)
694 chksum ^= *data++;
695
696 chksum = ~chksum;
697
698 le32p_replace_bits(&tx_desc->w7, __le16_to_cpu(chksum),
699 RTW_TX_DESC_W7_TXDESC_CHECKSUM);
700 }
701
__rtw8723x_coex_cfg_init(struct rtw_dev * rtwdev)702 static void __rtw8723x_coex_cfg_init(struct rtw_dev *rtwdev)
703 {
704 /* enable TBTT nterrupt */
705 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
706
707 /* BT report packet sample rate */
708 /* 0x790[5:0]=0x5 */
709 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
710
711 /* enable BT counter statistics */
712 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
713
714 /* enable PTA (3-wire function form BT side) */
715 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
716 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
717
718 /* enable PTA (tx/rx signal form WiFi side) */
719 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
720 }
721
722 const struct rtw8723x_common rtw8723x_common = {
723 .iqk_adda_regs = {
724 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84,
725 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec
726 },
727 .iqk_mac8_regs = {0x522, 0x550, 0x551},
728 .iqk_mac32_regs = {0x40},
729 .iqk_bb_regs = {
730 0xc04, 0xc08, 0x874, 0xb68, 0xb6c, 0x870, 0x860, 0x864, 0xa04
731 },
732
733 .ltecoex_addr = {
734 .ctrl = REG_LTECOEX_CTRL,
735 .wdata = REG_LTECOEX_WRITE_DATA,
736 .rdata = REG_LTECOEX_READ_DATA,
737 },
738 .rf_sipi_addr = {
739 [RF_PATH_A] = { .hssi_1 = 0x820, .lssi_read = 0x8a0,
740 .hssi_2 = 0x824, .lssi_read_pi = 0x8b8},
741 [RF_PATH_B] = { .hssi_1 = 0x828, .lssi_read = 0x8a4,
742 .hssi_2 = 0x82c, .lssi_read_pi = 0x8bc},
743 },
744 .dig = {
745 [0] = { .addr = 0xc50, .mask = 0x7f },
746 [1] = { .addr = 0xc50, .mask = 0x7f },
747 },
748 .dig_cck = {
749 [0] = { .addr = 0xa0c, .mask = 0x3f00 },
750 },
751 .prioq_addrs = {
752 .prio[RTW_DMA_MAPPING_EXTRA] = {
753 .rsvd = REG_RQPN_NPQ + 2, .avail = REG_RQPN_NPQ + 3,
754 },
755 .prio[RTW_DMA_MAPPING_LOW] = {
756 .rsvd = REG_RQPN + 1, .avail = REG_FIFOPAGE_CTRL_2 + 1,
757 },
758 .prio[RTW_DMA_MAPPING_NORMAL] = {
759 .rsvd = REG_RQPN_NPQ, .avail = REG_RQPN_NPQ + 1,
760 },
761 .prio[RTW_DMA_MAPPING_HIGH] = {
762 .rsvd = REG_RQPN, .avail = REG_FIFOPAGE_CTRL_2,
763 },
764 .wsize = false,
765 },
766
767 .lck = __rtw8723x_lck,
768 .read_efuse = __rtw8723x_read_efuse,
769 .mac_init = __rtw8723x_mac_init,
770 .mac_postinit = __rtw8723x_mac_postinit,
771 .cfg_ldo25 = __rtw8723x_cfg_ldo25,
772 .set_tx_power_index = __rtw8723x_set_tx_power_index,
773 .efuse_grant = __rtw8723x_efuse_grant,
774 .false_alarm_statistics = __rtw8723x_false_alarm_statistics,
775 .iqk_backup_regs = __rtw8723x_iqk_backup_regs,
776 .iqk_restore_regs = __rtw8723x_iqk_restore_regs,
777 .iqk_similarity_cmp = __rtw8723x_iqk_similarity_cmp,
778 .pwrtrack_get_limit_ofdm = __rtw8723x_pwrtrack_get_limit_ofdm,
779 .pwrtrack_set_xtal = __rtw8723x_pwrtrack_set_xtal,
780 .coex_cfg_init = __rtw8723x_coex_cfg_init,
781 .fill_txdesc_checksum = __rtw8723x_fill_txdesc_checksum,
782 .debug_txpwr_limit = __rtw8723x_debug_txpwr_limit,
783 };
784 EXPORT_SYMBOL(rtw8723x_common);
785
786 MODULE_AUTHOR("Realtek Corporation");
787 MODULE_AUTHOR("Fiona Klute <fiona.klute@gmx.de>");
788 MODULE_DESCRIPTION("Common functions for Realtek 802.11n wireless 8723x drivers");
789 MODULE_LICENSE("Dual BSD/GPL");
790