1 /* 2 * This file is part of the Emulex Linux Device Driver for Enterprise iSCSI 3 * Host Bus Adapters. Refer to the README file included with this package 4 * for driver version and adapter compatibility. 5 * 6 * Copyright (c) 2018 Broadcom. All Rights Reserved. 7 * The term “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of version 2 of the GNU General Public License as published 11 * by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful. ALL EXPRESS 14 * OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, INCLUDING ANY 15 * IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, 16 * OR NON-INFRINGEMENT, ARE DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH 17 * DISCLAIMERS ARE HELD TO BE LEGALLY INVALID. 18 * See the GNU General Public License for more details, a copy of which 19 * can be found in the file COPYING included with this package. 20 * 21 * Contact Information: 22 * linux-drivers@broadcom.com 23 * 24 */ 25 26 #include <linux/reboot.h> 27 #include <linux/delay.h> 28 #include <linux/slab.h> 29 #include <linux/interrupt.h> 30 #include <linux/blkdev.h> 31 #include <linux/pci.h> 32 #include <linux/string.h> 33 #include <linux/kernel.h> 34 #include <linux/semaphore.h> 35 #include <linux/iscsi_boot_sysfs.h> 36 #include <linux/module.h> 37 #include <linux/bsg-lib.h> 38 #include <linux/irq_poll.h> 39 40 #include <scsi/libiscsi.h> 41 #include <scsi/scsi_bsg_iscsi.h> 42 #include <scsi/scsi_netlink.h> 43 #include <scsi/scsi_transport_iscsi.h> 44 #include <scsi/scsi_transport.h> 45 #include <scsi/scsi_cmnd.h> 46 #include <scsi/scsi_device.h> 47 #include <scsi/scsi_host.h> 48 #include <scsi/scsi.h> 49 #include "be_main.h" 50 #include "be_iscsi.h" 51 #include "be_mgmt.h" 52 #include "be_cmds.h" 53 54 static unsigned int be_iopoll_budget = 10; 55 static unsigned int be_max_phys_size = 64; 56 static unsigned int enable_msix = 1; 57 58 MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR); 59 MODULE_VERSION(BUILD_STR); 60 MODULE_AUTHOR("Emulex Corporation"); 61 MODULE_LICENSE("GPL"); 62 module_param(be_iopoll_budget, int, 0); 63 module_param(enable_msix, int, 0); 64 module_param(be_max_phys_size, uint, S_IRUGO); 65 MODULE_PARM_DESC(be_max_phys_size, 66 "Maximum Size (In Kilobytes) of physically contiguous " 67 "memory that can be allocated. Range is 16 - 128"); 68 69 #define beiscsi_disp_param(_name)\ 70 static ssize_t \ 71 beiscsi_##_name##_disp(struct device *dev,\ 72 struct device_attribute *attrib, char *buf) \ 73 { \ 74 struct Scsi_Host *shost = class_to_shost(dev);\ 75 struct beiscsi_hba *phba = iscsi_host_priv(shost); \ 76 return snprintf(buf, PAGE_SIZE, "%d\n",\ 77 phba->attr_##_name);\ 78 } 79 80 #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\ 81 static int \ 82 beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\ 83 {\ 84 if (val >= _minval && val <= _maxval) {\ 85 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\ 86 "BA_%d : beiscsi_"#_name" updated "\ 87 "from 0x%x ==> 0x%x\n",\ 88 phba->attr_##_name, val); \ 89 phba->attr_##_name = val;\ 90 return 0;\ 91 } \ 92 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \ 93 "BA_%d beiscsi_"#_name" attribute "\ 94 "cannot be updated to 0x%x, "\ 95 "range allowed is ["#_minval" - "#_maxval"]\n", val);\ 96 return -EINVAL;\ 97 } 98 99 #define beiscsi_store_param(_name) \ 100 static ssize_t \ 101 beiscsi_##_name##_store(struct device *dev,\ 102 struct device_attribute *attr, const char *buf,\ 103 size_t count) \ 104 { \ 105 struct Scsi_Host *shost = class_to_shost(dev);\ 106 struct beiscsi_hba *phba = iscsi_host_priv(shost);\ 107 uint32_t param_val = 0;\ 108 if (!isdigit(buf[0]))\ 109 return -EINVAL;\ 110 if (sscanf(buf, "%i", ¶m_val) != 1)\ 111 return -EINVAL;\ 112 if (beiscsi_##_name##_change(phba, param_val) == 0) \ 113 return strlen(buf);\ 114 else \ 115 return -EINVAL;\ 116 } 117 118 #define beiscsi_init_param(_name, _minval, _maxval, _defval) \ 119 static int \ 120 beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \ 121 { \ 122 if (val >= _minval && val <= _maxval) {\ 123 phba->attr_##_name = val;\ 124 return 0;\ 125 } \ 126 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\ 127 "BA_%d beiscsi_"#_name" attribute " \ 128 "cannot be updated to 0x%x, "\ 129 "range allowed is ["#_minval" - "#_maxval"]\n", val);\ 130 phba->attr_##_name = _defval;\ 131 return -EINVAL;\ 132 } 133 134 #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \ 135 static uint beiscsi_##_name = _defval;\ 136 module_param(beiscsi_##_name, uint, S_IRUGO);\ 137 MODULE_PARM_DESC(beiscsi_##_name, _descp);\ 138 beiscsi_disp_param(_name)\ 139 beiscsi_change_param(_name, _minval, _maxval, _defval)\ 140 beiscsi_store_param(_name)\ 141 beiscsi_init_param(_name, _minval, _maxval, _defval)\ 142 static DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\ 143 beiscsi_##_name##_disp, beiscsi_##_name##_store) 144 145 /* 146 * When new log level added update MAX allowed value for log_enable 147 */ 148 BEISCSI_RW_ATTR(log_enable, 0x00, 149 0xFF, 0x00, "Enable logging Bit Mask\n" 150 "\t\t\t\tInitialization Events : 0x01\n" 151 "\t\t\t\tMailbox Events : 0x02\n" 152 "\t\t\t\tMiscellaneous Events : 0x04\n" 153 "\t\t\t\tError Handling : 0x08\n" 154 "\t\t\t\tIO Path Events : 0x10\n" 155 "\t\t\t\tConfiguration Path : 0x20\n" 156 "\t\t\t\tiSCSI Protocol : 0x40\n"); 157 158 static DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL); 159 static DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL); 160 static DEVICE_ATTR(beiscsi_fw_ver, S_IRUGO, beiscsi_fw_ver_disp, NULL); 161 static DEVICE_ATTR(beiscsi_phys_port, S_IRUGO, beiscsi_phys_port_disp, NULL); 162 static DEVICE_ATTR(beiscsi_active_session_count, S_IRUGO, 163 beiscsi_active_session_disp, NULL); 164 static DEVICE_ATTR(beiscsi_free_session_count, S_IRUGO, 165 beiscsi_free_session_disp, NULL); 166 167 static struct attribute *beiscsi_attrs[] = { 168 &dev_attr_beiscsi_log_enable.attr, 169 &dev_attr_beiscsi_drvr_ver.attr, 170 &dev_attr_beiscsi_adapter_family.attr, 171 &dev_attr_beiscsi_fw_ver.attr, 172 &dev_attr_beiscsi_active_session_count.attr, 173 &dev_attr_beiscsi_free_session_count.attr, 174 &dev_attr_beiscsi_phys_port.attr, 175 NULL, 176 }; 177 178 ATTRIBUTE_GROUPS(beiscsi); 179 180 static char const *cqe_desc[] = { 181 "RESERVED_DESC", 182 "SOL_CMD_COMPLETE", 183 "SOL_CMD_KILLED_DATA_DIGEST_ERR", 184 "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL", 185 "CXN_KILLED_BURST_LEN_MISMATCH", 186 "CXN_KILLED_AHS_RCVD", 187 "CXN_KILLED_HDR_DIGEST_ERR", 188 "CXN_KILLED_UNKNOWN_HDR", 189 "CXN_KILLED_STALE_ITT_TTT_RCVD", 190 "CXN_KILLED_INVALID_ITT_TTT_RCVD", 191 "CXN_KILLED_RST_RCVD", 192 "CXN_KILLED_TIMED_OUT", 193 "CXN_KILLED_RST_SENT", 194 "CXN_KILLED_FIN_RCVD", 195 "CXN_KILLED_BAD_UNSOL_PDU_RCVD", 196 "CXN_KILLED_BAD_WRB_INDEX_ERROR", 197 "CXN_KILLED_OVER_RUN_RESIDUAL", 198 "CXN_KILLED_UNDER_RUN_RESIDUAL", 199 "CMD_KILLED_INVALID_STATSN_RCVD", 200 "CMD_KILLED_INVALID_R2T_RCVD", 201 "CMD_CXN_KILLED_LUN_INVALID", 202 "CMD_CXN_KILLED_ICD_INVALID", 203 "CMD_CXN_KILLED_ITT_INVALID", 204 "CMD_CXN_KILLED_SEQ_OUTOFORDER", 205 "CMD_CXN_KILLED_INVALID_DATASN_RCVD", 206 "CXN_INVALIDATE_NOTIFY", 207 "CXN_INVALIDATE_INDEX_NOTIFY", 208 "CMD_INVALIDATED_NOTIFY", 209 "UNSOL_HDR_NOTIFY", 210 "UNSOL_DATA_NOTIFY", 211 "UNSOL_DATA_DIGEST_ERROR_NOTIFY", 212 "DRIVERMSG_NOTIFY", 213 "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN", 214 "SOL_CMD_KILLED_DIF_ERR", 215 "CXN_KILLED_SYN_RCVD", 216 "CXN_KILLED_IMM_DATA_RCVD" 217 }; 218 219 static int beiscsi_eh_abort(struct scsi_cmnd *sc) 220 { 221 struct iscsi_task *abrt_task = iscsi_cmd(sc)->task; 222 struct iscsi_cls_session *cls_session; 223 struct beiscsi_io_task *abrt_io_task; 224 struct beiscsi_conn *beiscsi_conn; 225 struct iscsi_session *session; 226 struct invldt_cmd_tbl inv_tbl; 227 struct beiscsi_hba *phba; 228 struct iscsi_conn *conn; 229 int rc; 230 231 cls_session = starget_to_session(scsi_target(sc->device)); 232 session = cls_session->dd_data; 233 234 completion_check: 235 /* check if we raced, task just got cleaned up under us */ 236 spin_lock_bh(&session->back_lock); 237 if (!abrt_task || !abrt_task->sc) { 238 spin_unlock_bh(&session->back_lock); 239 return SUCCESS; 240 } 241 /* get a task ref till FW processes the req for the ICD used */ 242 if (!iscsi_get_task(abrt_task)) { 243 spin_unlock(&session->back_lock); 244 /* We are just about to call iscsi_free_task so wait for it. */ 245 udelay(5); 246 goto completion_check; 247 } 248 249 abrt_io_task = abrt_task->dd_data; 250 conn = abrt_task->conn; 251 beiscsi_conn = conn->dd_data; 252 phba = beiscsi_conn->phba; 253 /* mark WRB invalid which have been not processed by FW yet */ 254 if (is_chip_be2_be3r(phba)) { 255 AMAP_SET_BITS(struct amap_iscsi_wrb, invld, 256 abrt_io_task->pwrb_handle->pwrb, 1); 257 } else { 258 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, invld, 259 abrt_io_task->pwrb_handle->pwrb, 1); 260 } 261 inv_tbl.cid = beiscsi_conn->beiscsi_conn_cid; 262 inv_tbl.icd = abrt_io_task->psgl_handle->sgl_index; 263 spin_unlock_bh(&session->back_lock); 264 265 rc = beiscsi_mgmt_invalidate_icds(phba, &inv_tbl, 1); 266 iscsi_put_task(abrt_task); 267 if (rc) { 268 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH, 269 "BM_%d : sc %p invalidation failed %d\n", 270 sc, rc); 271 return FAILED; 272 } 273 274 return iscsi_eh_abort(sc); 275 } 276 277 static int beiscsi_eh_device_reset(struct scsi_cmnd *sc) 278 { 279 struct beiscsi_invldt_cmd_tbl { 280 struct invldt_cmd_tbl tbl[BE_INVLDT_CMD_TBL_SZ]; 281 struct iscsi_task *task[BE_INVLDT_CMD_TBL_SZ]; 282 } *inv_tbl; 283 struct iscsi_cls_session *cls_session; 284 struct beiscsi_conn *beiscsi_conn; 285 struct beiscsi_io_task *io_task; 286 struct iscsi_session *session; 287 struct beiscsi_hba *phba; 288 struct iscsi_conn *conn; 289 struct iscsi_task *task; 290 unsigned int i, nents; 291 int rc, more = 0; 292 293 cls_session = starget_to_session(scsi_target(sc->device)); 294 session = cls_session->dd_data; 295 296 spin_lock_bh(&session->frwd_lock); 297 if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) { 298 spin_unlock_bh(&session->frwd_lock); 299 return FAILED; 300 } 301 302 conn = session->leadconn; 303 beiscsi_conn = conn->dd_data; 304 phba = beiscsi_conn->phba; 305 306 inv_tbl = kzalloc_obj(*inv_tbl, GFP_ATOMIC); 307 if (!inv_tbl) { 308 spin_unlock_bh(&session->frwd_lock); 309 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH, 310 "BM_%d : invldt_cmd_tbl alloc failed\n"); 311 return FAILED; 312 } 313 nents = 0; 314 /* take back_lock to prevent task from getting cleaned up under us */ 315 spin_lock(&session->back_lock); 316 for (i = 0; i < conn->session->cmds_max; i++) { 317 task = conn->session->cmds[i]; 318 if (!task->sc) 319 continue; 320 321 if (sc->device->lun != task->sc->device->lun) 322 continue; 323 /** 324 * Can't fit in more cmds? Normally this won't happen b'coz 325 * BEISCSI_CMD_PER_LUN is same as BE_INVLDT_CMD_TBL_SZ. 326 */ 327 if (nents == BE_INVLDT_CMD_TBL_SZ) { 328 more = 1; 329 break; 330 } 331 332 /* get a task ref till FW processes the req for the ICD used */ 333 if (!iscsi_get_task(task)) { 334 /* 335 * The task has completed in the driver and is 336 * completing in libiscsi. Just ignore it here. When we 337 * call iscsi_eh_device_reset, it will wait for us. 338 */ 339 continue; 340 } 341 342 io_task = task->dd_data; 343 /* mark WRB invalid which have been not processed by FW yet */ 344 if (is_chip_be2_be3r(phba)) { 345 AMAP_SET_BITS(struct amap_iscsi_wrb, invld, 346 io_task->pwrb_handle->pwrb, 1); 347 } else { 348 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, invld, 349 io_task->pwrb_handle->pwrb, 1); 350 } 351 352 inv_tbl->tbl[nents].cid = beiscsi_conn->beiscsi_conn_cid; 353 inv_tbl->tbl[nents].icd = io_task->psgl_handle->sgl_index; 354 inv_tbl->task[nents] = task; 355 nents++; 356 } 357 spin_unlock(&session->back_lock); 358 spin_unlock_bh(&session->frwd_lock); 359 360 rc = SUCCESS; 361 if (!nents) 362 goto end_reset; 363 364 if (more) { 365 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH, 366 "BM_%d : number of cmds exceeds size of invalidation table\n"); 367 rc = FAILED; 368 goto end_reset; 369 } 370 371 if (beiscsi_mgmt_invalidate_icds(phba, &inv_tbl->tbl[0], nents)) { 372 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH, 373 "BM_%d : cid %u scmds invalidation failed\n", 374 beiscsi_conn->beiscsi_conn_cid); 375 rc = FAILED; 376 } 377 378 end_reset: 379 for (i = 0; i < nents; i++) 380 iscsi_put_task(inv_tbl->task[i]); 381 kfree(inv_tbl); 382 383 if (rc == SUCCESS) 384 rc = iscsi_eh_device_reset(sc); 385 return rc; 386 } 387 388 /*------------------- PCI Driver operations and data ----------------- */ 389 static const struct pci_device_id beiscsi_pci_id_table[] = { 390 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) }, 391 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) }, 392 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) }, 393 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) }, 394 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) }, 395 { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) }, 396 { 0 } 397 }; 398 MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table); 399 400 401 static const struct scsi_host_template beiscsi_sht = { 402 .module = THIS_MODULE, 403 .name = "Emulex 10Gbe open-iscsi Initiator Driver", 404 .proc_name = DRV_NAME, 405 .queuecommand = iscsi_queuecommand, 406 .change_queue_depth = scsi_change_queue_depth, 407 .target_alloc = iscsi_target_alloc, 408 .eh_timed_out = iscsi_eh_cmd_timed_out, 409 .eh_abort_handler = beiscsi_eh_abort, 410 .eh_device_reset_handler = beiscsi_eh_device_reset, 411 .eh_target_reset_handler = iscsi_eh_session_reset, 412 .shost_groups = beiscsi_groups, 413 .sg_tablesize = BEISCSI_SGLIST_ELEMENTS, 414 .can_queue = BE2_IO_DEPTH, 415 .this_id = -1, 416 .max_sectors = BEISCSI_MAX_SECTORS, 417 .max_segment_size = 65536, 418 .cmd_per_lun = BEISCSI_CMD_PER_LUN, 419 .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID, 420 .track_queue_depth = 1, 421 .cmd_size = sizeof(struct iscsi_cmd), 422 }; 423 424 static struct scsi_transport_template *beiscsi_scsi_transport; 425 426 static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev) 427 { 428 struct beiscsi_hba *phba; 429 struct Scsi_Host *shost; 430 431 shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0); 432 if (!shost) { 433 dev_err(&pcidev->dev, 434 "beiscsi_hba_alloc - iscsi_host_alloc failed\n"); 435 return NULL; 436 } 437 shost->max_id = BE2_MAX_SESSIONS - 1; 438 shost->max_channel = 0; 439 shost->max_cmd_len = BEISCSI_MAX_CMD_LEN; 440 shost->max_lun = BEISCSI_NUM_MAX_LUN; 441 shost->transportt = beiscsi_scsi_transport; 442 phba = iscsi_host_priv(shost); 443 memset(phba, 0, sizeof(*phba)); 444 phba->shost = shost; 445 phba->pcidev = pci_dev_get(pcidev); 446 pci_set_drvdata(pcidev, phba); 447 phba->interface_handle = 0xFFFFFFFF; 448 449 return phba; 450 } 451 452 static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba) 453 { 454 if (phba->csr_va) { 455 iounmap(phba->csr_va); 456 phba->csr_va = NULL; 457 } 458 if (phba->db_va) { 459 iounmap(phba->db_va); 460 phba->db_va = NULL; 461 } 462 if (phba->pci_va) { 463 iounmap(phba->pci_va); 464 phba->pci_va = NULL; 465 } 466 } 467 468 static int beiscsi_map_pci_bars(struct beiscsi_hba *phba, 469 struct pci_dev *pcidev) 470 { 471 u8 __iomem *addr; 472 int pcicfg_reg; 473 474 addr = ioremap(pci_resource_start(pcidev, 2), 475 pci_resource_len(pcidev, 2)); 476 if (addr == NULL) 477 return -ENOMEM; 478 phba->ctrl.csr = addr; 479 phba->csr_va = addr; 480 481 addr = ioremap(pci_resource_start(pcidev, 4), 128 * 1024); 482 if (addr == NULL) 483 goto pci_map_err; 484 phba->ctrl.db = addr; 485 phba->db_va = addr; 486 487 if (phba->generation == BE_GEN2) 488 pcicfg_reg = 1; 489 else 490 pcicfg_reg = 0; 491 492 addr = ioremap(pci_resource_start(pcidev, pcicfg_reg), 493 pci_resource_len(pcidev, pcicfg_reg)); 494 495 if (addr == NULL) 496 goto pci_map_err; 497 phba->ctrl.pcicfg = addr; 498 phba->pci_va = addr; 499 return 0; 500 501 pci_map_err: 502 beiscsi_unmap_pci_function(phba); 503 return -ENOMEM; 504 } 505 506 static int beiscsi_enable_pci(struct pci_dev *pcidev) 507 { 508 int ret; 509 510 ret = pci_enable_device(pcidev); 511 if (ret) { 512 dev_err(&pcidev->dev, 513 "beiscsi_enable_pci - enable device failed\n"); 514 return ret; 515 } 516 517 ret = pci_request_regions(pcidev, DRV_NAME); 518 if (ret) { 519 dev_err(&pcidev->dev, 520 "beiscsi_enable_pci - request region failed\n"); 521 goto pci_dev_disable; 522 } 523 524 pci_set_master(pcidev); 525 ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(64)); 526 if (ret) { 527 ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)); 528 if (ret) { 529 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n"); 530 goto pci_region_release; 531 } 532 } 533 return 0; 534 535 pci_region_release: 536 pci_release_regions(pcidev); 537 pci_dev_disable: 538 pci_disable_device(pcidev); 539 540 return ret; 541 } 542 543 static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev) 544 { 545 struct be_ctrl_info *ctrl = &phba->ctrl; 546 struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced; 547 struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem; 548 int status = 0; 549 550 ctrl->pdev = pdev; 551 status = beiscsi_map_pci_bars(phba, pdev); 552 if (status) 553 return status; 554 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16; 555 mbox_mem_alloc->va = dma_alloc_coherent(&pdev->dev, 556 mbox_mem_alloc->size, &mbox_mem_alloc->dma, GFP_KERNEL); 557 if (!mbox_mem_alloc->va) { 558 beiscsi_unmap_pci_function(phba); 559 return -ENOMEM; 560 } 561 562 mbox_mem_align->size = sizeof(struct be_mcc_mailbox); 563 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16); 564 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16); 565 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox)); 566 mutex_init(&ctrl->mbox_lock); 567 spin_lock_init(&phba->ctrl.mcc_lock); 568 569 return status; 570 } 571 572 /** 573 * beiscsi_get_params()- Set the config paramters 574 * @phba: ptr device priv structure 575 **/ 576 static void beiscsi_get_params(struct beiscsi_hba *phba) 577 { 578 uint32_t total_cid_count = 0; 579 uint32_t total_icd_count = 0; 580 uint8_t ulp_num = 0; 581 582 total_cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) + 583 BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1); 584 585 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 586 uint32_t align_mask = 0; 587 uint32_t icd_post_per_page = 0; 588 uint32_t icd_count_unavailable = 0; 589 uint32_t icd_start = 0, icd_count = 0; 590 uint32_t icd_start_align = 0, icd_count_align = 0; 591 592 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 593 icd_start = phba->fw_config.iscsi_icd_start[ulp_num]; 594 icd_count = phba->fw_config.iscsi_icd_count[ulp_num]; 595 596 /* Get ICD count that can be posted on each page */ 597 icd_post_per_page = (PAGE_SIZE / (BE2_SGE * 598 sizeof(struct iscsi_sge))); 599 align_mask = (icd_post_per_page - 1); 600 601 /* Check if icd_start is aligned ICD per page posting */ 602 if (icd_start % icd_post_per_page) { 603 icd_start_align = ((icd_start + 604 icd_post_per_page) & 605 ~(align_mask)); 606 phba->fw_config. 607 iscsi_icd_start[ulp_num] = 608 icd_start_align; 609 } 610 611 icd_count_align = (icd_count & ~align_mask); 612 613 /* ICD discarded in the process of alignment */ 614 if (icd_start_align) 615 icd_count_unavailable = ((icd_start_align - 616 icd_start) + 617 (icd_count - 618 icd_count_align)); 619 620 /* Updated ICD count available */ 621 phba->fw_config.iscsi_icd_count[ulp_num] = (icd_count - 622 icd_count_unavailable); 623 624 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 625 "BM_%d : Aligned ICD values\n" 626 "\t ICD Start : %d\n" 627 "\t ICD Count : %d\n" 628 "\t ICD Discarded : %d\n", 629 phba->fw_config. 630 iscsi_icd_start[ulp_num], 631 phba->fw_config. 632 iscsi_icd_count[ulp_num], 633 icd_count_unavailable); 634 break; 635 } 636 } 637 638 total_icd_count = phba->fw_config.iscsi_icd_count[ulp_num]; 639 phba->params.ios_per_ctrl = (total_icd_count - 640 (total_cid_count + 641 BE2_TMFS + BE2_NOPOUT_REQ)); 642 phba->params.cxns_per_ctrl = total_cid_count; 643 phba->params.icds_per_ctrl = total_icd_count; 644 phba->params.num_sge_per_io = BE2_SGE; 645 phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ; 646 phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ; 647 phba->params.num_eq_entries = 1024; 648 phba->params.num_cq_entries = 1024; 649 phba->params.wrbs_per_cxn = 256; 650 } 651 652 static void hwi_ring_eq_db(struct beiscsi_hba *phba, 653 unsigned int id, unsigned int clr_interrupt, 654 unsigned int num_processed, 655 unsigned char rearm, unsigned char event) 656 { 657 u32 val = 0; 658 659 if (rearm) 660 val |= 1 << DB_EQ_REARM_SHIFT; 661 if (clr_interrupt) 662 val |= 1 << DB_EQ_CLR_SHIFT; 663 if (event) 664 val |= 1 << DB_EQ_EVNT_SHIFT; 665 666 val |= num_processed << DB_EQ_NUM_POPPED_SHIFT; 667 /* Setting lower order EQ_ID Bits */ 668 val |= (id & DB_EQ_RING_ID_LOW_MASK); 669 670 /* Setting Higher order EQ_ID Bits */ 671 val |= (((id >> DB_EQ_HIGH_FEILD_SHIFT) & 672 DB_EQ_RING_ID_HIGH_MASK) 673 << DB_EQ_HIGH_SET_SHIFT); 674 675 iowrite32(val, phba->db_va + DB_EQ_OFFSET); 676 } 677 678 /** 679 * be_isr_mcc - The isr routine of the driver. 680 * @irq: Not used 681 * @dev_id: Pointer to host adapter structure 682 */ 683 static irqreturn_t be_isr_mcc(int irq, void *dev_id) 684 { 685 struct beiscsi_hba *phba; 686 struct be_eq_entry *eqe; 687 struct be_queue_info *eq; 688 struct be_queue_info *mcc; 689 unsigned int mcc_events; 690 struct be_eq_obj *pbe_eq; 691 692 pbe_eq = dev_id; 693 eq = &pbe_eq->q; 694 phba = pbe_eq->phba; 695 mcc = &phba->ctrl.mcc_obj.cq; 696 eqe = queue_tail_node(eq); 697 698 mcc_events = 0; 699 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] 700 & EQE_VALID_MASK) { 701 if (((eqe->dw[offsetof(struct amap_eq_entry, 702 resource_id) / 32] & 703 EQE_RESID_MASK) >> 16) == mcc->id) { 704 mcc_events++; 705 } 706 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 707 queue_tail_inc(eq); 708 eqe = queue_tail_node(eq); 709 } 710 711 if (mcc_events) { 712 queue_work(phba->wq, &pbe_eq->mcc_work); 713 hwi_ring_eq_db(phba, eq->id, 1, mcc_events, 1, 1); 714 } 715 return IRQ_HANDLED; 716 } 717 718 /** 719 * be_isr_msix - The isr routine of the driver. 720 * @irq: Not used 721 * @dev_id: Pointer to host adapter structure 722 */ 723 static irqreturn_t be_isr_msix(int irq, void *dev_id) 724 { 725 struct beiscsi_hba *phba; 726 struct be_queue_info *eq; 727 struct be_eq_obj *pbe_eq; 728 729 pbe_eq = dev_id; 730 eq = &pbe_eq->q; 731 732 phba = pbe_eq->phba; 733 /* disable interrupt till iopoll completes */ 734 hwi_ring_eq_db(phba, eq->id, 1, 0, 0, 1); 735 irq_poll_sched(&pbe_eq->iopoll); 736 737 return IRQ_HANDLED; 738 } 739 740 /** 741 * be_isr - The isr routine of the driver. 742 * @irq: Not used 743 * @dev_id: Pointer to host adapter structure 744 */ 745 static irqreturn_t be_isr(int irq, void *dev_id) 746 { 747 struct beiscsi_hba *phba; 748 struct hwi_controller *phwi_ctrlr; 749 struct hwi_context_memory *phwi_context; 750 struct be_eq_entry *eqe; 751 struct be_queue_info *eq; 752 struct be_queue_info *mcc; 753 unsigned int mcc_events, io_events; 754 struct be_ctrl_info *ctrl; 755 struct be_eq_obj *pbe_eq; 756 int isr, rearm; 757 758 phba = dev_id; 759 ctrl = &phba->ctrl; 760 isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET + 761 (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE)); 762 if (!isr) 763 return IRQ_NONE; 764 765 phwi_ctrlr = phba->phwi_ctrlr; 766 phwi_context = phwi_ctrlr->phwi_ctxt; 767 pbe_eq = &phwi_context->be_eq[0]; 768 769 eq = &phwi_context->be_eq[0].q; 770 mcc = &phba->ctrl.mcc_obj.cq; 771 eqe = queue_tail_node(eq); 772 773 io_events = 0; 774 mcc_events = 0; 775 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] 776 & EQE_VALID_MASK) { 777 if (((eqe->dw[offsetof(struct amap_eq_entry, 778 resource_id) / 32] & EQE_RESID_MASK) >> 16) == mcc->id) 779 mcc_events++; 780 else 781 io_events++; 782 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 783 queue_tail_inc(eq); 784 eqe = queue_tail_node(eq); 785 } 786 if (!io_events && !mcc_events) 787 return IRQ_NONE; 788 789 /* no need to rearm if interrupt is only for IOs */ 790 rearm = 0; 791 if (mcc_events) { 792 queue_work(phba->wq, &pbe_eq->mcc_work); 793 /* rearm for MCCQ */ 794 rearm = 1; 795 } 796 if (io_events) 797 irq_poll_sched(&pbe_eq->iopoll); 798 hwi_ring_eq_db(phba, eq->id, 0, (io_events + mcc_events), rearm, 1); 799 return IRQ_HANDLED; 800 } 801 802 static void beiscsi_free_irqs(struct beiscsi_hba *phba) 803 { 804 struct hwi_context_memory *phwi_context; 805 int i; 806 807 if (!phba->pcidev->msix_enabled) { 808 if (phba->pcidev->irq) 809 free_irq(phba->pcidev->irq, phba); 810 return; 811 } 812 813 phwi_context = phba->phwi_ctrlr->phwi_ctxt; 814 for (i = 0; i <= phba->num_cpus; i++) { 815 free_irq(pci_irq_vector(phba->pcidev, i), 816 &phwi_context->be_eq[i]); 817 kfree(phba->msi_name[i]); 818 } 819 } 820 821 static int beiscsi_init_irqs(struct beiscsi_hba *phba) 822 { 823 struct pci_dev *pcidev = phba->pcidev; 824 struct hwi_controller *phwi_ctrlr; 825 struct hwi_context_memory *phwi_context; 826 int ret, i, j; 827 828 phwi_ctrlr = phba->phwi_ctrlr; 829 phwi_context = phwi_ctrlr->phwi_ctxt; 830 831 if (pcidev->msix_enabled) { 832 for (i = 0; i < phba->num_cpus; i++) { 833 phba->msi_name[i] = kasprintf(GFP_KERNEL, 834 "beiscsi_%02x_%02x", 835 phba->shost->host_no, i); 836 if (!phba->msi_name[i]) { 837 ret = -ENOMEM; 838 goto free_msix_irqs; 839 } 840 841 ret = request_irq(pci_irq_vector(pcidev, i), 842 be_isr_msix, 0, phba->msi_name[i], 843 &phwi_context->be_eq[i]); 844 if (ret) { 845 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 846 "BM_%d : %s-Failed to register msix for i = %d\n", 847 __func__, i); 848 kfree(phba->msi_name[i]); 849 goto free_msix_irqs; 850 } 851 } 852 phba->msi_name[i] = kasprintf(GFP_KERNEL, "beiscsi_mcc_%02x", 853 phba->shost->host_no); 854 if (!phba->msi_name[i]) { 855 ret = -ENOMEM; 856 goto free_msix_irqs; 857 } 858 ret = request_irq(pci_irq_vector(pcidev, i), be_isr_mcc, 0, 859 phba->msi_name[i], &phwi_context->be_eq[i]); 860 if (ret) { 861 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 862 "BM_%d : %s-Failed to register beiscsi_msix_mcc\n", 863 __func__); 864 kfree(phba->msi_name[i]); 865 goto free_msix_irqs; 866 } 867 868 } else { 869 ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED, 870 "beiscsi", phba); 871 if (ret) { 872 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 873 "BM_%d : %s-Failed to register irq\n", 874 __func__); 875 return ret; 876 } 877 } 878 return 0; 879 free_msix_irqs: 880 for (j = i - 1; j >= 0; j--) { 881 free_irq(pci_irq_vector(pcidev, i), &phwi_context->be_eq[j]); 882 kfree(phba->msi_name[j]); 883 } 884 return ret; 885 } 886 887 void hwi_ring_cq_db(struct beiscsi_hba *phba, 888 unsigned int id, unsigned int num_processed, 889 unsigned char rearm) 890 { 891 u32 val = 0; 892 893 if (rearm) 894 val |= 1 << DB_CQ_REARM_SHIFT; 895 896 val |= num_processed << DB_CQ_NUM_POPPED_SHIFT; 897 898 /* Setting lower order CQ_ID Bits */ 899 val |= (id & DB_CQ_RING_ID_LOW_MASK); 900 901 /* Setting Higher order CQ_ID Bits */ 902 val |= (((id >> DB_CQ_HIGH_FEILD_SHIFT) & 903 DB_CQ_RING_ID_HIGH_MASK) 904 << DB_CQ_HIGH_SET_SHIFT); 905 906 iowrite32(val, phba->db_va + DB_CQ_OFFSET); 907 } 908 909 static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba) 910 { 911 struct sgl_handle *psgl_handle; 912 unsigned long flags; 913 914 spin_lock_irqsave(&phba->io_sgl_lock, flags); 915 if (phba->io_sgl_hndl_avbl) { 916 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO, 917 "BM_%d : In alloc_io_sgl_handle," 918 " io_sgl_alloc_index=%d\n", 919 phba->io_sgl_alloc_index); 920 921 psgl_handle = phba->io_sgl_hndl_base[phba-> 922 io_sgl_alloc_index]; 923 phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL; 924 phba->io_sgl_hndl_avbl--; 925 if (phba->io_sgl_alloc_index == (phba->params. 926 ios_per_ctrl - 1)) 927 phba->io_sgl_alloc_index = 0; 928 else 929 phba->io_sgl_alloc_index++; 930 } else 931 psgl_handle = NULL; 932 spin_unlock_irqrestore(&phba->io_sgl_lock, flags); 933 return psgl_handle; 934 } 935 936 static void 937 free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle) 938 { 939 unsigned long flags; 940 941 spin_lock_irqsave(&phba->io_sgl_lock, flags); 942 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO, 943 "BM_%d : In free_,io_sgl_free_index=%d\n", 944 phba->io_sgl_free_index); 945 946 if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) { 947 /* 948 * this can happen if clean_task is called on a task that 949 * failed in xmit_task or alloc_pdu. 950 */ 951 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO, 952 "BM_%d : Double Free in IO SGL io_sgl_free_index=%d, value there=%p\n", 953 phba->io_sgl_free_index, 954 phba->io_sgl_hndl_base[phba->io_sgl_free_index]); 955 spin_unlock_irqrestore(&phba->io_sgl_lock, flags); 956 return; 957 } 958 phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle; 959 phba->io_sgl_hndl_avbl++; 960 if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1)) 961 phba->io_sgl_free_index = 0; 962 else 963 phba->io_sgl_free_index++; 964 spin_unlock_irqrestore(&phba->io_sgl_lock, flags); 965 } 966 967 static inline struct wrb_handle * 968 beiscsi_get_wrb_handle(struct hwi_wrb_context *pwrb_context, 969 unsigned int wrbs_per_cxn) 970 { 971 struct wrb_handle *pwrb_handle; 972 unsigned long flags; 973 974 spin_lock_irqsave(&pwrb_context->wrb_lock, flags); 975 if (!pwrb_context->wrb_handles_available) { 976 spin_unlock_irqrestore(&pwrb_context->wrb_lock, flags); 977 return NULL; 978 } 979 pwrb_handle = pwrb_context->pwrb_handle_base[pwrb_context->alloc_index]; 980 pwrb_context->wrb_handles_available--; 981 if (pwrb_context->alloc_index == (wrbs_per_cxn - 1)) 982 pwrb_context->alloc_index = 0; 983 else 984 pwrb_context->alloc_index++; 985 spin_unlock_irqrestore(&pwrb_context->wrb_lock, flags); 986 987 if (pwrb_handle) 988 memset(pwrb_handle->pwrb, 0, sizeof(*pwrb_handle->pwrb)); 989 990 return pwrb_handle; 991 } 992 993 /** 994 * alloc_wrb_handle - To allocate a wrb handle 995 * @phba: The hba pointer 996 * @cid: The cid to use for allocation 997 * @pcontext: ptr to ptr to wrb context 998 * 999 * This happens under session_lock until submission to chip 1000 */ 1001 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid, 1002 struct hwi_wrb_context **pcontext) 1003 { 1004 struct hwi_wrb_context *pwrb_context; 1005 struct hwi_controller *phwi_ctrlr; 1006 uint16_t cri_index = BE_GET_CRI_FROM_CID(cid); 1007 1008 phwi_ctrlr = phba->phwi_ctrlr; 1009 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 1010 /* return the context address */ 1011 *pcontext = pwrb_context; 1012 return beiscsi_get_wrb_handle(pwrb_context, phba->params.wrbs_per_cxn); 1013 } 1014 1015 static inline void 1016 beiscsi_put_wrb_handle(struct hwi_wrb_context *pwrb_context, 1017 struct wrb_handle *pwrb_handle, 1018 unsigned int wrbs_per_cxn) 1019 { 1020 unsigned long flags; 1021 1022 spin_lock_irqsave(&pwrb_context->wrb_lock, flags); 1023 pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle; 1024 pwrb_context->wrb_handles_available++; 1025 if (pwrb_context->free_index == (wrbs_per_cxn - 1)) 1026 pwrb_context->free_index = 0; 1027 else 1028 pwrb_context->free_index++; 1029 pwrb_handle->pio_handle = NULL; 1030 spin_unlock_irqrestore(&pwrb_context->wrb_lock, flags); 1031 } 1032 1033 /** 1034 * free_wrb_handle - To free the wrb handle back to pool 1035 * @phba: The hba pointer 1036 * @pwrb_context: The context to free from 1037 * @pwrb_handle: The wrb_handle to free 1038 * 1039 * This happens under session_lock until submission to chip 1040 */ 1041 static void 1042 free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context, 1043 struct wrb_handle *pwrb_handle) 1044 { 1045 beiscsi_put_wrb_handle(pwrb_context, 1046 pwrb_handle, 1047 phba->params.wrbs_per_cxn); 1048 beiscsi_log(phba, KERN_INFO, 1049 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 1050 "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x " 1051 "wrb_handles_available=%d\n", 1052 pwrb_handle, pwrb_context->free_index, 1053 pwrb_context->wrb_handles_available); 1054 } 1055 1056 static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba) 1057 { 1058 struct sgl_handle *psgl_handle; 1059 unsigned long flags; 1060 1061 spin_lock_irqsave(&phba->mgmt_sgl_lock, flags); 1062 if (phba->eh_sgl_hndl_avbl) { 1063 psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index]; 1064 phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL; 1065 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG, 1066 "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n", 1067 phba->eh_sgl_alloc_index, 1068 phba->eh_sgl_alloc_index); 1069 1070 phba->eh_sgl_hndl_avbl--; 1071 if (phba->eh_sgl_alloc_index == 1072 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1073 1)) 1074 phba->eh_sgl_alloc_index = 0; 1075 else 1076 phba->eh_sgl_alloc_index++; 1077 } else 1078 psgl_handle = NULL; 1079 spin_unlock_irqrestore(&phba->mgmt_sgl_lock, flags); 1080 return psgl_handle; 1081 } 1082 1083 void 1084 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle) 1085 { 1086 unsigned long flags; 1087 1088 spin_lock_irqsave(&phba->mgmt_sgl_lock, flags); 1089 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG, 1090 "BM_%d : In free_mgmt_sgl_handle," 1091 "eh_sgl_free_index=%d\n", 1092 phba->eh_sgl_free_index); 1093 1094 if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) { 1095 /* 1096 * this can happen if clean_task is called on a task that 1097 * failed in xmit_task or alloc_pdu. 1098 */ 1099 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG, 1100 "BM_%d : Double Free in eh SGL ," 1101 "eh_sgl_free_index=%d\n", 1102 phba->eh_sgl_free_index); 1103 spin_unlock_irqrestore(&phba->mgmt_sgl_lock, flags); 1104 return; 1105 } 1106 phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle; 1107 phba->eh_sgl_hndl_avbl++; 1108 if (phba->eh_sgl_free_index == 1109 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1)) 1110 phba->eh_sgl_free_index = 0; 1111 else 1112 phba->eh_sgl_free_index++; 1113 spin_unlock_irqrestore(&phba->mgmt_sgl_lock, flags); 1114 } 1115 1116 static void 1117 be_complete_io(struct beiscsi_conn *beiscsi_conn, 1118 struct iscsi_task *task, 1119 struct common_sol_cqe *csol_cqe) 1120 __must_hold(&beiscsi_conn->conn->session->back_lock) 1121 { 1122 struct beiscsi_io_task *io_task = task->dd_data; 1123 struct be_status_bhs *sts_bhs = 1124 (struct be_status_bhs *)io_task->cmd_bhs; 1125 struct iscsi_conn *conn = beiscsi_conn->conn; 1126 unsigned char *sense; 1127 u32 resid = 0, exp_cmdsn, max_cmdsn; 1128 u8 rsp, status, flags; 1129 1130 exp_cmdsn = csol_cqe->exp_cmdsn; 1131 max_cmdsn = (csol_cqe->exp_cmdsn + 1132 csol_cqe->cmd_wnd - 1); 1133 rsp = csol_cqe->i_resp; 1134 status = csol_cqe->i_sts; 1135 flags = csol_cqe->i_flags; 1136 resid = csol_cqe->res_cnt; 1137 1138 if (!task->sc) { 1139 if (io_task->scsi_cmnd) { 1140 scsi_dma_unmap(io_task->scsi_cmnd); 1141 io_task->scsi_cmnd = NULL; 1142 } 1143 1144 return; 1145 } 1146 task->sc->result = (DID_OK << 16) | status; 1147 if (rsp != ISCSI_STATUS_CMD_COMPLETED) { 1148 task->sc->result = DID_ERROR << 16; 1149 goto unmap; 1150 } 1151 1152 /* bidi not initially supported */ 1153 if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) { 1154 if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW)) 1155 task->sc->result = DID_ERROR << 16; 1156 1157 if (flags & ISCSI_FLAG_CMD_UNDERFLOW) { 1158 scsi_set_resid(task->sc, resid); 1159 if (!status && (scsi_bufflen(task->sc) - resid < 1160 task->sc->underflow)) 1161 task->sc->result = DID_ERROR << 16; 1162 } 1163 } 1164 1165 if (status == SAM_STAT_CHECK_CONDITION) { 1166 u16 sense_len; 1167 unsigned short *slen = (unsigned short *)sts_bhs->sense_info; 1168 1169 sense = sts_bhs->sense_info + sizeof(unsigned short); 1170 sense_len = be16_to_cpu(*slen); 1171 memcpy(task->sc->sense_buffer, sense, 1172 min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE)); 1173 } 1174 1175 if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ) 1176 conn->rxdata_octets += resid; 1177 unmap: 1178 if (io_task->scsi_cmnd) { 1179 scsi_dma_unmap(io_task->scsi_cmnd); 1180 io_task->scsi_cmnd = NULL; 1181 } 1182 iscsi_complete_scsi_task(conn->session, task, exp_cmdsn, max_cmdsn); 1183 } 1184 1185 static void 1186 be_complete_logout(struct beiscsi_conn *beiscsi_conn, 1187 struct iscsi_task *task, 1188 struct common_sol_cqe *csol_cqe) 1189 __must_hold(&beiscsi_conn->conn->session->back_lock) 1190 { 1191 struct iscsi_logout_rsp *hdr; 1192 struct beiscsi_io_task *io_task = task->dd_data; 1193 struct iscsi_conn *conn = beiscsi_conn->conn; 1194 1195 hdr = (struct iscsi_logout_rsp *)task->hdr; 1196 hdr->opcode = ISCSI_OP_LOGOUT_RSP; 1197 hdr->t2wait = 5; 1198 hdr->t2retain = 0; 1199 hdr->flags = csol_cqe->i_flags; 1200 hdr->response = csol_cqe->i_resp; 1201 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn); 1202 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn + 1203 csol_cqe->cmd_wnd - 1); 1204 1205 hdr->dlength[0] = 0; 1206 hdr->dlength[1] = 0; 1207 hdr->dlength[2] = 0; 1208 hdr->hlength = 0; 1209 hdr->itt = io_task->libiscsi_itt; 1210 __iscsi_complete_pdu(conn->session, conn, (struct iscsi_hdr *)hdr, NULL, 0); 1211 } 1212 1213 static void 1214 be_complete_tmf(struct beiscsi_conn *beiscsi_conn, 1215 struct iscsi_task *task, 1216 struct common_sol_cqe *csol_cqe) 1217 __must_hold(&beiscsi_conn->conn->session->back_lock) 1218 { 1219 struct iscsi_tm_rsp *hdr; 1220 struct iscsi_conn *conn = beiscsi_conn->conn; 1221 struct beiscsi_io_task *io_task = task->dd_data; 1222 1223 hdr = (struct iscsi_tm_rsp *)task->hdr; 1224 hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP; 1225 hdr->flags = csol_cqe->i_flags; 1226 hdr->response = csol_cqe->i_resp; 1227 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn); 1228 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn + 1229 csol_cqe->cmd_wnd - 1); 1230 1231 hdr->itt = io_task->libiscsi_itt; 1232 __iscsi_complete_pdu(conn->session, conn, (struct iscsi_hdr *)hdr, NULL, 0); 1233 } 1234 1235 static void 1236 hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn, 1237 struct beiscsi_hba *phba, struct sol_cqe *psol) 1238 { 1239 struct hwi_wrb_context *pwrb_context; 1240 uint16_t wrb_index, cid, cri_index; 1241 struct hwi_controller *phwi_ctrlr; 1242 struct wrb_handle *pwrb_handle; 1243 struct iscsi_session *session; 1244 struct iscsi_task *task; 1245 1246 phwi_ctrlr = phba->phwi_ctrlr; 1247 if (is_chip_be2_be3r(phba)) { 1248 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe, 1249 wrb_idx, psol); 1250 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe, 1251 cid, psol); 1252 } else { 1253 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2, 1254 wrb_idx, psol); 1255 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2, 1256 cid, psol); 1257 } 1258 1259 cri_index = BE_GET_CRI_FROM_CID(cid); 1260 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 1261 pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index]; 1262 session = beiscsi_conn->conn->session; 1263 spin_lock_bh(&session->back_lock); 1264 task = pwrb_handle->pio_handle; 1265 if (task) 1266 __iscsi_put_task(session, task); 1267 spin_unlock_bh(&session->back_lock); 1268 } 1269 1270 static void 1271 be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn, 1272 struct iscsi_task *task, 1273 struct common_sol_cqe *csol_cqe) 1274 __must_hold(&beiscsi_conn->conn->session->back_lock) 1275 { 1276 struct iscsi_nopin *hdr; 1277 struct iscsi_conn *conn = beiscsi_conn->conn; 1278 struct beiscsi_io_task *io_task = task->dd_data; 1279 1280 hdr = (struct iscsi_nopin *)task->hdr; 1281 hdr->flags = csol_cqe->i_flags; 1282 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn); 1283 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn + 1284 csol_cqe->cmd_wnd - 1); 1285 1286 hdr->opcode = ISCSI_OP_NOOP_IN; 1287 hdr->itt = io_task->libiscsi_itt; 1288 __iscsi_complete_pdu(conn->session, conn, (struct iscsi_hdr *)hdr, NULL, 0); 1289 } 1290 1291 static void adapter_get_sol_cqe(struct beiscsi_hba *phba, 1292 struct sol_cqe *psol, 1293 struct common_sol_cqe *csol_cqe) 1294 { 1295 if (is_chip_be2_be3r(phba)) { 1296 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe, 1297 i_exp_cmd_sn, psol); 1298 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe, 1299 i_res_cnt, psol); 1300 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe, 1301 i_cmd_wnd, psol); 1302 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe, 1303 wrb_index, psol); 1304 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe, 1305 cid, psol); 1306 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe, 1307 hw_sts, psol); 1308 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe, 1309 i_resp, psol); 1310 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe, 1311 i_sts, psol); 1312 csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe, 1313 i_flags, psol); 1314 } else { 1315 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1316 i_exp_cmd_sn, psol); 1317 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1318 i_res_cnt, psol); 1319 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1320 wrb_index, psol); 1321 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1322 cid, psol); 1323 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1324 hw_sts, psol); 1325 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1326 i_cmd_wnd, psol); 1327 if (AMAP_GET_BITS(struct amap_sol_cqe_v2, 1328 cmd_cmpl, psol)) 1329 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1330 i_sts, psol); 1331 else 1332 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1333 i_sts, psol); 1334 if (AMAP_GET_BITS(struct amap_sol_cqe_v2, 1335 u, psol)) 1336 csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW; 1337 1338 if (AMAP_GET_BITS(struct amap_sol_cqe_v2, 1339 o, psol)) 1340 csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW; 1341 } 1342 } 1343 1344 1345 static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn, 1346 struct beiscsi_hba *phba, struct sol_cqe *psol) 1347 { 1348 struct iscsi_conn *conn = beiscsi_conn->conn; 1349 struct iscsi_session *session = conn->session; 1350 struct common_sol_cqe csol_cqe = {0}; 1351 struct hwi_wrb_context *pwrb_context; 1352 struct hwi_controller *phwi_ctrlr; 1353 struct wrb_handle *pwrb_handle; 1354 struct iscsi_task *task; 1355 uint16_t cri_index = 0; 1356 uint8_t type; 1357 1358 phwi_ctrlr = phba->phwi_ctrlr; 1359 1360 /* Copy the elements to a common structure */ 1361 adapter_get_sol_cqe(phba, psol, &csol_cqe); 1362 1363 cri_index = BE_GET_CRI_FROM_CID(csol_cqe.cid); 1364 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 1365 1366 pwrb_handle = pwrb_context->pwrb_handle_basestd[ 1367 csol_cqe.wrb_index]; 1368 1369 spin_lock_bh(&session->back_lock); 1370 task = pwrb_handle->pio_handle; 1371 if (!task) { 1372 spin_unlock_bh(&session->back_lock); 1373 return; 1374 } 1375 type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type; 1376 1377 switch (type) { 1378 case HWH_TYPE_IO: 1379 case HWH_TYPE_IO_RD: 1380 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == 1381 ISCSI_OP_NOOP_OUT) 1382 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe); 1383 else 1384 be_complete_io(beiscsi_conn, task, &csol_cqe); 1385 break; 1386 1387 case HWH_TYPE_LOGOUT: 1388 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT) 1389 be_complete_logout(beiscsi_conn, task, &csol_cqe); 1390 else 1391 be_complete_tmf(beiscsi_conn, task, &csol_cqe); 1392 break; 1393 1394 case HWH_TYPE_LOGIN: 1395 beiscsi_log(phba, KERN_ERR, 1396 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 1397 "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in" 1398 " %s- Solicited path\n", __func__); 1399 break; 1400 1401 case HWH_TYPE_NOP: 1402 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe); 1403 break; 1404 1405 default: 1406 beiscsi_log(phba, KERN_WARNING, 1407 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 1408 "BM_%d : In %s, unknown type = %d " 1409 "wrb_index 0x%x CID 0x%x\n", __func__, type, 1410 csol_cqe.wrb_index, 1411 csol_cqe.cid); 1412 break; 1413 } 1414 1415 spin_unlock_bh(&session->back_lock); 1416 } 1417 1418 /* 1419 * ASYNC PDUs include 1420 * a. Unsolicited NOP-In (target initiated NOP-In) 1421 * b. ASYNC Messages 1422 * c. Reject PDU 1423 * d. Login response 1424 * These headers arrive unprocessed by the EP firmware. 1425 * iSCSI layer processes them. 1426 */ 1427 static unsigned int 1428 beiscsi_complete_pdu(struct beiscsi_conn *beiscsi_conn, 1429 struct pdu_base *phdr, void *pdata, unsigned int dlen) 1430 __must_hold(&beiscsi_conn->conn->session->back_lock) 1431 { 1432 struct beiscsi_hba *phba = beiscsi_conn->phba; 1433 struct iscsi_conn *conn = beiscsi_conn->conn; 1434 struct beiscsi_io_task *io_task; 1435 struct iscsi_hdr *login_hdr; 1436 struct iscsi_task *task; 1437 u8 code; 1438 1439 code = AMAP_GET_BITS(struct amap_pdu_base, opcode, phdr); 1440 switch (code) { 1441 case ISCSI_OP_NOOP_IN: 1442 pdata = NULL; 1443 dlen = 0; 1444 break; 1445 case ISCSI_OP_ASYNC_EVENT: 1446 break; 1447 case ISCSI_OP_REJECT: 1448 WARN_ON(!pdata); 1449 WARN_ON(!(dlen == 48)); 1450 beiscsi_log(phba, KERN_ERR, 1451 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 1452 "BM_%d : In ISCSI_OP_REJECT\n"); 1453 break; 1454 case ISCSI_OP_LOGIN_RSP: 1455 case ISCSI_OP_TEXT_RSP: 1456 task = conn->login_task; 1457 io_task = task->dd_data; 1458 login_hdr = (struct iscsi_hdr *)phdr; 1459 login_hdr->itt = io_task->libiscsi_itt; 1460 break; 1461 default: 1462 beiscsi_log(phba, KERN_WARNING, 1463 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 1464 "BM_%d : unrecognized async PDU opcode 0x%x\n", 1465 code); 1466 return 1; 1467 } 1468 __iscsi_complete_pdu(conn->session, conn, (struct iscsi_hdr *)phdr, pdata, 1469 dlen); 1470 return 0; 1471 } 1472 1473 static inline void 1474 beiscsi_hdl_put_handle(struct hd_async_context *pasync_ctx, 1475 struct hd_async_handle *pasync_handle) 1476 { 1477 pasync_handle->is_final = 0; 1478 pasync_handle->buffer_len = 0; 1479 pasync_handle->in_use = 0; 1480 list_del_init(&pasync_handle->link); 1481 } 1482 1483 static void 1484 beiscsi_hdl_purge_handles(struct beiscsi_hba *phba, 1485 struct hd_async_context *pasync_ctx, 1486 u16 cri) 1487 { 1488 struct hd_async_handle *pasync_handle, *tmp_handle; 1489 struct list_head *plist; 1490 1491 plist = &pasync_ctx->async_entry[cri].wq.list; 1492 list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) 1493 beiscsi_hdl_put_handle(pasync_ctx, pasync_handle); 1494 1495 INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wq.list); 1496 pasync_ctx->async_entry[cri].wq.hdr_len = 0; 1497 pasync_ctx->async_entry[cri].wq.bytes_received = 0; 1498 pasync_ctx->async_entry[cri].wq.bytes_needed = 0; 1499 } 1500 1501 static struct hd_async_handle * 1502 beiscsi_hdl_get_handle(struct beiscsi_conn *beiscsi_conn, 1503 struct hd_async_context *pasync_ctx, 1504 struct i_t_dpdu_cqe *pdpdu_cqe, 1505 u8 *header) 1506 { 1507 struct beiscsi_hba *phba = beiscsi_conn->phba; 1508 struct hd_async_handle *pasync_handle; 1509 struct be_bus_address phys_addr; 1510 u16 cid, code, ci, cri; 1511 u8 final, error = 0; 1512 u32 dpl; 1513 1514 cid = beiscsi_conn->beiscsi_conn_cid; 1515 cri = BE_GET_ASYNC_CRI_FROM_CID(cid); 1516 /** 1517 * This function is invoked to get the right async_handle structure 1518 * from a given DEF PDU CQ entry. 1519 * 1520 * - index in CQ entry gives the vertical index 1521 * - address in CQ entry is the offset where the DMA last ended 1522 * - final - no more notifications for this PDU 1523 */ 1524 if (is_chip_be2_be3r(phba)) { 1525 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, 1526 dpl, pdpdu_cqe); 1527 ci = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, 1528 index, pdpdu_cqe); 1529 final = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, 1530 final, pdpdu_cqe); 1531 } else { 1532 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2, 1533 dpl, pdpdu_cqe); 1534 ci = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2, 1535 index, pdpdu_cqe); 1536 final = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2, 1537 final, pdpdu_cqe); 1538 } 1539 1540 /** 1541 * DB addr Hi/Lo is same for BE and SKH. 1542 * Subtract the dataplacementlength to get to the base. 1543 */ 1544 phys_addr.u.a32.address_lo = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, 1545 db_addr_lo, pdpdu_cqe); 1546 phys_addr.u.a32.address_lo -= dpl; 1547 phys_addr.u.a32.address_hi = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, 1548 db_addr_hi, pdpdu_cqe); 1549 1550 code = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, code, pdpdu_cqe); 1551 switch (code) { 1552 case UNSOL_HDR_NOTIFY: 1553 pasync_handle = pasync_ctx->async_entry[ci].header; 1554 *header = 1; 1555 break; 1556 case UNSOL_DATA_DIGEST_ERROR_NOTIFY: 1557 error = 1; 1558 fallthrough; 1559 case UNSOL_DATA_NOTIFY: 1560 pasync_handle = pasync_ctx->async_entry[ci].data; 1561 break; 1562 /* called only for above codes */ 1563 default: 1564 return NULL; 1565 } 1566 1567 if (pasync_handle->pa.u.a64.address != phys_addr.u.a64.address || 1568 pasync_handle->index != ci) { 1569 /* driver bug - if ci does not match async handle index */ 1570 error = 1; 1571 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI, 1572 "BM_%d : cid %u async PDU handle mismatch - addr in %cQE %llx at %u:addr in CQE %llx ci %u\n", 1573 cid, pasync_handle->is_header ? 'H' : 'D', 1574 pasync_handle->pa.u.a64.address, 1575 pasync_handle->index, 1576 phys_addr.u.a64.address, ci); 1577 /* FW has stale address - attempt continuing by dropping */ 1578 } 1579 1580 /** 1581 * DEF PDU header and data buffers with errors should be simply 1582 * dropped as there are no consumers for it. 1583 */ 1584 if (error) { 1585 beiscsi_hdl_put_handle(pasync_ctx, pasync_handle); 1586 return NULL; 1587 } 1588 1589 if (pasync_handle->in_use || !list_empty(&pasync_handle->link)) { 1590 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI, 1591 "BM_%d : cid %d async PDU handle in use - code %d ci %d addr %llx\n", 1592 cid, code, ci, phys_addr.u.a64.address); 1593 beiscsi_hdl_purge_handles(phba, pasync_ctx, cri); 1594 } 1595 1596 list_del_init(&pasync_handle->link); 1597 /** 1598 * Each CID is associated with unique CRI. 1599 * ASYNC_CRI_FROM_CID mapping and CRI_FROM_CID are totaly different. 1600 **/ 1601 pasync_handle->cri = cri; 1602 pasync_handle->is_final = final; 1603 pasync_handle->buffer_len = dpl; 1604 pasync_handle->in_use = 1; 1605 1606 return pasync_handle; 1607 } 1608 1609 static unsigned int 1610 beiscsi_hdl_fwd_pdu(struct beiscsi_conn *beiscsi_conn, 1611 struct hd_async_context *pasync_ctx, 1612 u16 cri) 1613 { 1614 struct iscsi_session *session = beiscsi_conn->conn->session; 1615 struct hd_async_handle *pasync_handle, *plast_handle; 1616 struct beiscsi_hba *phba = beiscsi_conn->phba; 1617 void *phdr = NULL, *pdata = NULL; 1618 u32 dlen = 0, status = 0; 1619 struct list_head *plist; 1620 1621 plist = &pasync_ctx->async_entry[cri].wq.list; 1622 plast_handle = NULL; 1623 list_for_each_entry(pasync_handle, plist, link) { 1624 plast_handle = pasync_handle; 1625 /* get the header, the first entry */ 1626 if (!phdr) { 1627 phdr = pasync_handle->pbuffer; 1628 continue; 1629 } 1630 /* use first buffer to collect all the data */ 1631 if (!pdata) { 1632 pdata = pasync_handle->pbuffer; 1633 dlen = pasync_handle->buffer_len; 1634 continue; 1635 } 1636 if (!pasync_handle->buffer_len || 1637 (dlen + pasync_handle->buffer_len) > 1638 pasync_ctx->async_data.buffer_size) 1639 break; 1640 memcpy(pdata + dlen, pasync_handle->pbuffer, 1641 pasync_handle->buffer_len); 1642 dlen += pasync_handle->buffer_len; 1643 } 1644 1645 if (!plast_handle->is_final) { 1646 /* last handle should have final PDU notification from FW */ 1647 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI, 1648 "BM_%d : cid %u %p fwd async PDU opcode %x with last handle missing - HL%u:DN%u:DR%u\n", 1649 beiscsi_conn->beiscsi_conn_cid, plast_handle, 1650 AMAP_GET_BITS(struct amap_pdu_base, opcode, phdr), 1651 pasync_ctx->async_entry[cri].wq.hdr_len, 1652 pasync_ctx->async_entry[cri].wq.bytes_needed, 1653 pasync_ctx->async_entry[cri].wq.bytes_received); 1654 } 1655 spin_lock_bh(&session->back_lock); 1656 status = beiscsi_complete_pdu(beiscsi_conn, phdr, pdata, dlen); 1657 spin_unlock_bh(&session->back_lock); 1658 beiscsi_hdl_purge_handles(phba, pasync_ctx, cri); 1659 return status; 1660 } 1661 1662 static unsigned int 1663 beiscsi_hdl_gather_pdu(struct beiscsi_conn *beiscsi_conn, 1664 struct hd_async_context *pasync_ctx, 1665 struct hd_async_handle *pasync_handle) 1666 { 1667 unsigned int bytes_needed = 0, status = 0; 1668 u16 cri = pasync_handle->cri; 1669 struct cri_wait_queue *wq; 1670 struct beiscsi_hba *phba; 1671 struct pdu_base *ppdu; 1672 char *err = ""; 1673 1674 phba = beiscsi_conn->phba; 1675 wq = &pasync_ctx->async_entry[cri].wq; 1676 if (pasync_handle->is_header) { 1677 /* check if PDU hdr is rcv'd when old hdr not completed */ 1678 if (wq->hdr_len) { 1679 err = "incomplete"; 1680 goto drop_pdu; 1681 } 1682 ppdu = pasync_handle->pbuffer; 1683 bytes_needed = AMAP_GET_BITS(struct amap_pdu_base, 1684 data_len_hi, ppdu); 1685 bytes_needed <<= 16; 1686 bytes_needed |= be16_to_cpu(AMAP_GET_BITS(struct amap_pdu_base, 1687 data_len_lo, ppdu)); 1688 wq->hdr_len = pasync_handle->buffer_len; 1689 wq->bytes_received = 0; 1690 wq->bytes_needed = bytes_needed; 1691 list_add_tail(&pasync_handle->link, &wq->list); 1692 if (!bytes_needed) 1693 status = beiscsi_hdl_fwd_pdu(beiscsi_conn, 1694 pasync_ctx, cri); 1695 } else { 1696 /* check if data received has header and is needed */ 1697 if (!wq->hdr_len || !wq->bytes_needed) { 1698 err = "header less"; 1699 goto drop_pdu; 1700 } 1701 wq->bytes_received += pasync_handle->buffer_len; 1702 /* Something got overwritten? Better catch it here. */ 1703 if (wq->bytes_received > wq->bytes_needed) { 1704 err = "overflow"; 1705 goto drop_pdu; 1706 } 1707 list_add_tail(&pasync_handle->link, &wq->list); 1708 if (wq->bytes_received == wq->bytes_needed) 1709 status = beiscsi_hdl_fwd_pdu(beiscsi_conn, 1710 pasync_ctx, cri); 1711 } 1712 return status; 1713 1714 drop_pdu: 1715 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI, 1716 "BM_%d : cid %u async PDU %s - def-%c:HL%u:DN%u:DR%u\n", 1717 beiscsi_conn->beiscsi_conn_cid, err, 1718 pasync_handle->is_header ? 'H' : 'D', 1719 wq->hdr_len, wq->bytes_needed, 1720 pasync_handle->buffer_len); 1721 /* discard this handle */ 1722 beiscsi_hdl_put_handle(pasync_ctx, pasync_handle); 1723 /* free all the other handles in cri_wait_queue */ 1724 beiscsi_hdl_purge_handles(phba, pasync_ctx, cri); 1725 /* try continuing */ 1726 return status; 1727 } 1728 1729 static void 1730 beiscsi_hdq_post_handles(struct beiscsi_hba *phba, 1731 u8 header, u8 ulp_num, u16 nbuf) 1732 { 1733 struct hd_async_handle *pasync_handle; 1734 struct hd_async_context *pasync_ctx; 1735 struct hwi_controller *phwi_ctrlr; 1736 struct phys_addr *pasync_sge; 1737 u32 ring_id, doorbell = 0; 1738 u32 doorbell_offset; 1739 u16 prod, pi; 1740 1741 phwi_ctrlr = phba->phwi_ctrlr; 1742 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num); 1743 if (header) { 1744 pasync_sge = pasync_ctx->async_header.ring_base; 1745 pi = pasync_ctx->async_header.pi; 1746 ring_id = phwi_ctrlr->default_pdu_hdr[ulp_num].id; 1747 doorbell_offset = phwi_ctrlr->default_pdu_hdr[ulp_num]. 1748 doorbell_offset; 1749 } else { 1750 pasync_sge = pasync_ctx->async_data.ring_base; 1751 pi = pasync_ctx->async_data.pi; 1752 ring_id = phwi_ctrlr->default_pdu_data[ulp_num].id; 1753 doorbell_offset = phwi_ctrlr->default_pdu_data[ulp_num]. 1754 doorbell_offset; 1755 } 1756 1757 for (prod = 0; prod < nbuf; prod++) { 1758 if (header) 1759 pasync_handle = pasync_ctx->async_entry[pi].header; 1760 else 1761 pasync_handle = pasync_ctx->async_entry[pi].data; 1762 WARN_ON(pasync_handle->is_header != header); 1763 WARN_ON(pasync_handle->index != pi); 1764 /* setup the ring only once */ 1765 if (nbuf == pasync_ctx->num_entries) { 1766 /* note hi is lo */ 1767 pasync_sge[pi].hi = pasync_handle->pa.u.a32.address_lo; 1768 pasync_sge[pi].lo = pasync_handle->pa.u.a32.address_hi; 1769 } 1770 if (++pi == pasync_ctx->num_entries) 1771 pi = 0; 1772 } 1773 1774 if (header) 1775 pasync_ctx->async_header.pi = pi; 1776 else 1777 pasync_ctx->async_data.pi = pi; 1778 1779 doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK; 1780 doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT; 1781 doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT; 1782 doorbell |= (prod & DB_DEF_PDU_CQPROC_MASK) << DB_DEF_PDU_CQPROC_SHIFT; 1783 iowrite32(doorbell, phba->db_va + doorbell_offset); 1784 } 1785 1786 static void 1787 beiscsi_hdq_process_compl(struct beiscsi_conn *beiscsi_conn, 1788 struct i_t_dpdu_cqe *pdpdu_cqe) 1789 { 1790 struct beiscsi_hba *phba = beiscsi_conn->phba; 1791 struct hd_async_handle *pasync_handle = NULL; 1792 struct hd_async_context *pasync_ctx; 1793 struct hwi_controller *phwi_ctrlr; 1794 u8 ulp_num, consumed, header = 0; 1795 u16 cid_cri; 1796 1797 phwi_ctrlr = phba->phwi_ctrlr; 1798 cid_cri = BE_GET_CRI_FROM_CID(beiscsi_conn->beiscsi_conn_cid); 1799 ulp_num = BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cid_cri); 1800 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num); 1801 pasync_handle = beiscsi_hdl_get_handle(beiscsi_conn, pasync_ctx, 1802 pdpdu_cqe, &header); 1803 if (is_chip_be2_be3r(phba)) 1804 consumed = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, 1805 num_cons, pdpdu_cqe); 1806 else 1807 consumed = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2, 1808 num_cons, pdpdu_cqe); 1809 if (pasync_handle) 1810 beiscsi_hdl_gather_pdu(beiscsi_conn, pasync_ctx, pasync_handle); 1811 /* num_cons indicates number of 8 RQEs consumed */ 1812 if (consumed) 1813 beiscsi_hdq_post_handles(phba, header, ulp_num, 8 * consumed); 1814 } 1815 1816 void beiscsi_process_mcc_cq(struct beiscsi_hba *phba) 1817 { 1818 struct be_queue_info *mcc_cq; 1819 struct be_mcc_compl *mcc_compl; 1820 unsigned int num_processed = 0; 1821 1822 mcc_cq = &phba->ctrl.mcc_obj.cq; 1823 mcc_compl = queue_tail_node(mcc_cq); 1824 mcc_compl->flags = le32_to_cpu(mcc_compl->flags); 1825 while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) { 1826 if (beiscsi_hba_in_error(phba)) 1827 return; 1828 1829 if (num_processed >= 32) { 1830 hwi_ring_cq_db(phba, mcc_cq->id, 1831 num_processed, 0); 1832 num_processed = 0; 1833 } 1834 if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) { 1835 beiscsi_process_async_event(phba, mcc_compl); 1836 } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) { 1837 beiscsi_process_mcc_compl(&phba->ctrl, mcc_compl); 1838 } 1839 1840 mcc_compl->flags = 0; 1841 queue_tail_inc(mcc_cq); 1842 mcc_compl = queue_tail_node(mcc_cq); 1843 mcc_compl->flags = le32_to_cpu(mcc_compl->flags); 1844 num_processed++; 1845 } 1846 1847 if (num_processed > 0) 1848 hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1); 1849 } 1850 1851 static void beiscsi_mcc_work(struct work_struct *work) 1852 { 1853 struct be_eq_obj *pbe_eq; 1854 struct beiscsi_hba *phba; 1855 1856 pbe_eq = container_of(work, struct be_eq_obj, mcc_work); 1857 phba = pbe_eq->phba; 1858 beiscsi_process_mcc_cq(phba); 1859 /* rearm EQ for further interrupts */ 1860 if (!beiscsi_hba_in_error(phba)) 1861 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1); 1862 } 1863 1864 /** 1865 * beiscsi_process_cq()- Process the Completion Queue 1866 * @pbe_eq: Event Q on which the Completion has come 1867 * @budget: Max number of events to processed 1868 * 1869 * return 1870 * Number of Completion Entries processed. 1871 **/ 1872 unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget) 1873 { 1874 struct be_queue_info *cq; 1875 struct sol_cqe *sol; 1876 unsigned int total = 0; 1877 unsigned int num_processed = 0; 1878 unsigned short code = 0, cid = 0; 1879 uint16_t cri_index = 0; 1880 struct beiscsi_conn *beiscsi_conn; 1881 struct beiscsi_endpoint *beiscsi_ep; 1882 struct iscsi_endpoint *ep; 1883 struct beiscsi_hba *phba; 1884 1885 cq = pbe_eq->cq; 1886 sol = queue_tail_node(cq); 1887 phba = pbe_eq->phba; 1888 1889 while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] & 1890 CQE_VALID_MASK) { 1891 if (beiscsi_hba_in_error(phba)) 1892 return 0; 1893 1894 be_dws_le_to_cpu(sol, sizeof(struct sol_cqe)); 1895 1896 code = (sol->dw[offsetof(struct amap_sol_cqe, code) / 32] & 1897 CQE_CODE_MASK); 1898 1899 /* Get the CID */ 1900 if (is_chip_be2_be3r(phba)) { 1901 cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol); 1902 } else { 1903 if ((code == DRIVERMSG_NOTIFY) || 1904 (code == UNSOL_HDR_NOTIFY) || 1905 (code == UNSOL_DATA_NOTIFY)) 1906 cid = AMAP_GET_BITS( 1907 struct amap_i_t_dpdu_cqe_v2, 1908 cid, sol); 1909 else 1910 cid = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1911 cid, sol); 1912 } 1913 1914 cri_index = BE_GET_CRI_FROM_CID(cid); 1915 ep = phba->ep_array[cri_index]; 1916 1917 if (ep == NULL) { 1918 /* connection has already been freed 1919 * just move on to next one 1920 */ 1921 beiscsi_log(phba, KERN_WARNING, 1922 BEISCSI_LOG_INIT, 1923 "BM_%d : proc cqe of disconn ep: cid %d\n", 1924 cid); 1925 goto proc_next_cqe; 1926 } 1927 1928 beiscsi_ep = ep->dd_data; 1929 beiscsi_conn = beiscsi_ep->conn; 1930 1931 /* replenish cq */ 1932 if (num_processed == 32) { 1933 hwi_ring_cq_db(phba, cq->id, 32, 0); 1934 num_processed = 0; 1935 } 1936 total++; 1937 1938 switch (code) { 1939 case SOL_CMD_COMPLETE: 1940 hwi_complete_cmd(beiscsi_conn, phba, sol); 1941 break; 1942 case DRIVERMSG_NOTIFY: 1943 beiscsi_log(phba, KERN_INFO, 1944 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 1945 "BM_%d : Received %s[%d] on CID : %d\n", 1946 cqe_desc[code], code, cid); 1947 1948 hwi_complete_drvr_msgs(beiscsi_conn, phba, sol); 1949 break; 1950 case UNSOL_HDR_NOTIFY: 1951 beiscsi_log(phba, KERN_INFO, 1952 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 1953 "BM_%d : Received %s[%d] on CID : %d\n", 1954 cqe_desc[code], code, cid); 1955 1956 spin_lock_bh(&phba->async_pdu_lock); 1957 beiscsi_hdq_process_compl(beiscsi_conn, 1958 (struct i_t_dpdu_cqe *)sol); 1959 spin_unlock_bh(&phba->async_pdu_lock); 1960 break; 1961 case UNSOL_DATA_NOTIFY: 1962 beiscsi_log(phba, KERN_INFO, 1963 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 1964 "BM_%d : Received %s[%d] on CID : %d\n", 1965 cqe_desc[code], code, cid); 1966 1967 spin_lock_bh(&phba->async_pdu_lock); 1968 beiscsi_hdq_process_compl(beiscsi_conn, 1969 (struct i_t_dpdu_cqe *)sol); 1970 spin_unlock_bh(&phba->async_pdu_lock); 1971 break; 1972 case CXN_INVALIDATE_INDEX_NOTIFY: 1973 case CMD_INVALIDATED_NOTIFY: 1974 case CXN_INVALIDATE_NOTIFY: 1975 beiscsi_log(phba, KERN_ERR, 1976 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 1977 "BM_%d : Ignoring %s[%d] on CID : %d\n", 1978 cqe_desc[code], code, cid); 1979 break; 1980 case CXN_KILLED_HDR_DIGEST_ERR: 1981 case SOL_CMD_KILLED_DATA_DIGEST_ERR: 1982 beiscsi_log(phba, KERN_ERR, 1983 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 1984 "BM_%d : Cmd Notification %s[%d] on CID : %d\n", 1985 cqe_desc[code], code, cid); 1986 break; 1987 case CMD_KILLED_INVALID_STATSN_RCVD: 1988 case CMD_KILLED_INVALID_R2T_RCVD: 1989 case CMD_CXN_KILLED_LUN_INVALID: 1990 case CMD_CXN_KILLED_ICD_INVALID: 1991 case CMD_CXN_KILLED_ITT_INVALID: 1992 case CMD_CXN_KILLED_SEQ_OUTOFORDER: 1993 case CMD_CXN_KILLED_INVALID_DATASN_RCVD: 1994 beiscsi_log(phba, KERN_ERR, 1995 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 1996 "BM_%d : Cmd Notification %s[%d] on CID : %d\n", 1997 cqe_desc[code], code, cid); 1998 break; 1999 case UNSOL_DATA_DIGEST_ERROR_NOTIFY: 2000 beiscsi_log(phba, KERN_ERR, 2001 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 2002 "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n", 2003 cqe_desc[code], code, cid); 2004 spin_lock_bh(&phba->async_pdu_lock); 2005 /* driver consumes the entry and drops the contents */ 2006 beiscsi_hdq_process_compl(beiscsi_conn, 2007 (struct i_t_dpdu_cqe *)sol); 2008 spin_unlock_bh(&phba->async_pdu_lock); 2009 break; 2010 case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL: 2011 case CXN_KILLED_BURST_LEN_MISMATCH: 2012 case CXN_KILLED_AHS_RCVD: 2013 case CXN_KILLED_UNKNOWN_HDR: 2014 case CXN_KILLED_STALE_ITT_TTT_RCVD: 2015 case CXN_KILLED_INVALID_ITT_TTT_RCVD: 2016 case CXN_KILLED_TIMED_OUT: 2017 case CXN_KILLED_FIN_RCVD: 2018 case CXN_KILLED_RST_SENT: 2019 case CXN_KILLED_RST_RCVD: 2020 case CXN_KILLED_BAD_UNSOL_PDU_RCVD: 2021 case CXN_KILLED_BAD_WRB_INDEX_ERROR: 2022 case CXN_KILLED_OVER_RUN_RESIDUAL: 2023 case CXN_KILLED_UNDER_RUN_RESIDUAL: 2024 case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN: 2025 beiscsi_log(phba, KERN_ERR, 2026 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 2027 "BM_%d : Event %s[%d] received on CID : %d\n", 2028 cqe_desc[code], code, cid); 2029 if (beiscsi_conn) 2030 iscsi_conn_failure(beiscsi_conn->conn, 2031 ISCSI_ERR_CONN_FAILED); 2032 break; 2033 default: 2034 beiscsi_log(phba, KERN_ERR, 2035 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 2036 "BM_%d : Invalid CQE Event Received Code : %d CID 0x%x...\n", 2037 code, cid); 2038 break; 2039 } 2040 2041 proc_next_cqe: 2042 AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0); 2043 queue_tail_inc(cq); 2044 sol = queue_tail_node(cq); 2045 num_processed++; 2046 if (total == budget) 2047 break; 2048 } 2049 2050 hwi_ring_cq_db(phba, cq->id, num_processed, 1); 2051 return total; 2052 } 2053 2054 static int be_iopoll(struct irq_poll *iop, int budget) 2055 { 2056 unsigned int ret, io_events; 2057 struct beiscsi_hba *phba; 2058 struct be_eq_obj *pbe_eq; 2059 struct be_eq_entry *eqe = NULL; 2060 struct be_queue_info *eq; 2061 2062 pbe_eq = container_of(iop, struct be_eq_obj, iopoll); 2063 phba = pbe_eq->phba; 2064 if (beiscsi_hba_in_error(phba)) { 2065 irq_poll_complete(iop); 2066 return 0; 2067 } 2068 2069 io_events = 0; 2070 eq = &pbe_eq->q; 2071 eqe = queue_tail_node(eq); 2072 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] & 2073 EQE_VALID_MASK) { 2074 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 2075 queue_tail_inc(eq); 2076 eqe = queue_tail_node(eq); 2077 io_events++; 2078 } 2079 hwi_ring_eq_db(phba, eq->id, 1, io_events, 0, 1); 2080 2081 ret = beiscsi_process_cq(pbe_eq, budget); 2082 pbe_eq->cq_count += ret; 2083 if (ret < budget) { 2084 irq_poll_complete(iop); 2085 beiscsi_log(phba, KERN_INFO, 2086 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 2087 "BM_%d : rearm pbe_eq->q.id =%d ret %d\n", 2088 pbe_eq->q.id, ret); 2089 if (!beiscsi_hba_in_error(phba)) 2090 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1); 2091 } 2092 return ret; 2093 } 2094 2095 static void 2096 hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg, 2097 unsigned int num_sg, struct beiscsi_io_task *io_task) 2098 { 2099 struct iscsi_sge *psgl; 2100 unsigned int sg_len, index; 2101 unsigned int sge_len = 0; 2102 unsigned long long addr; 2103 struct scatterlist *l_sg; 2104 unsigned int offset; 2105 2106 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb, 2107 io_task->bhs_pa.u.a32.address_lo); 2108 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb, 2109 io_task->bhs_pa.u.a32.address_hi); 2110 2111 l_sg = sg; 2112 for (index = 0; (index < num_sg) && (index < 2); index++, 2113 sg = sg_next(sg)) { 2114 if (index == 0) { 2115 sg_len = sg_dma_len(sg); 2116 addr = (u64) sg_dma_address(sg); 2117 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2118 sge0_addr_lo, pwrb, 2119 lower_32_bits(addr)); 2120 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2121 sge0_addr_hi, pwrb, 2122 upper_32_bits(addr)); 2123 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2124 sge0_len, pwrb, 2125 sg_len); 2126 sge_len = sg_len; 2127 } else { 2128 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset, 2129 pwrb, sge_len); 2130 sg_len = sg_dma_len(sg); 2131 addr = (u64) sg_dma_address(sg); 2132 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2133 sge1_addr_lo, pwrb, 2134 lower_32_bits(addr)); 2135 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2136 sge1_addr_hi, pwrb, 2137 upper_32_bits(addr)); 2138 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2139 sge1_len, pwrb, 2140 sg_len); 2141 } 2142 } 2143 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; 2144 memset(psgl, 0, sizeof(*psgl) * BE2_SGE); 2145 2146 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2); 2147 2148 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2149 io_task->bhs_pa.u.a32.address_hi); 2150 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2151 io_task->bhs_pa.u.a32.address_lo); 2152 2153 if (num_sg == 1) { 2154 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb, 2155 1); 2156 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb, 2157 0); 2158 } else if (num_sg == 2) { 2159 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb, 2160 0); 2161 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb, 2162 1); 2163 } else { 2164 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb, 2165 0); 2166 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb, 2167 0); 2168 } 2169 2170 sg = l_sg; 2171 psgl++; 2172 psgl++; 2173 offset = 0; 2174 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) { 2175 sg_len = sg_dma_len(sg); 2176 addr = (u64) sg_dma_address(sg); 2177 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2178 lower_32_bits(addr)); 2179 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2180 upper_32_bits(addr)); 2181 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len); 2182 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset); 2183 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); 2184 offset += sg_len; 2185 } 2186 psgl--; 2187 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); 2188 } 2189 2190 static void 2191 hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg, 2192 unsigned int num_sg, struct beiscsi_io_task *io_task) 2193 { 2194 struct iscsi_sge *psgl; 2195 unsigned int sg_len, index; 2196 unsigned int sge_len = 0; 2197 unsigned long long addr; 2198 struct scatterlist *l_sg; 2199 unsigned int offset; 2200 2201 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb, 2202 io_task->bhs_pa.u.a32.address_lo); 2203 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb, 2204 io_task->bhs_pa.u.a32.address_hi); 2205 2206 l_sg = sg; 2207 for (index = 0; (index < num_sg) && (index < 2); index++, 2208 sg = sg_next(sg)) { 2209 if (index == 0) { 2210 sg_len = sg_dma_len(sg); 2211 addr = (u64) sg_dma_address(sg); 2212 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb, 2213 ((u32)(addr & 0xFFFFFFFF))); 2214 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb, 2215 ((u32)(addr >> 32))); 2216 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb, 2217 sg_len); 2218 sge_len = sg_len; 2219 } else { 2220 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset, 2221 pwrb, sge_len); 2222 sg_len = sg_dma_len(sg); 2223 addr = (u64) sg_dma_address(sg); 2224 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb, 2225 ((u32)(addr & 0xFFFFFFFF))); 2226 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb, 2227 ((u32)(addr >> 32))); 2228 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb, 2229 sg_len); 2230 } 2231 } 2232 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; 2233 memset(psgl, 0, sizeof(*psgl) * BE2_SGE); 2234 2235 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2); 2236 2237 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2238 io_task->bhs_pa.u.a32.address_hi); 2239 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2240 io_task->bhs_pa.u.a32.address_lo); 2241 2242 if (num_sg == 1) { 2243 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 2244 1); 2245 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, 2246 0); 2247 } else if (num_sg == 2) { 2248 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 2249 0); 2250 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, 2251 1); 2252 } else { 2253 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 2254 0); 2255 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, 2256 0); 2257 } 2258 sg = l_sg; 2259 psgl++; 2260 psgl++; 2261 offset = 0; 2262 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) { 2263 sg_len = sg_dma_len(sg); 2264 addr = (u64) sg_dma_address(sg); 2265 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2266 (addr & 0xFFFFFFFF)); 2267 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2268 (addr >> 32)); 2269 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len); 2270 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset); 2271 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); 2272 offset += sg_len; 2273 } 2274 psgl--; 2275 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); 2276 } 2277 2278 /** 2279 * hwi_write_buffer()- Populate the WRB with task info 2280 * @pwrb: ptr to the WRB entry 2281 * @task: iscsi task which is to be executed 2282 **/ 2283 static int hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task) 2284 { 2285 struct iscsi_sge *psgl; 2286 struct beiscsi_io_task *io_task = task->dd_data; 2287 struct beiscsi_conn *beiscsi_conn = io_task->conn; 2288 struct beiscsi_hba *phba = beiscsi_conn->phba; 2289 uint8_t dsp_value = 0; 2290 2291 io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2; 2292 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb, 2293 io_task->bhs_pa.u.a32.address_lo); 2294 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb, 2295 io_task->bhs_pa.u.a32.address_hi); 2296 2297 if (task->data) { 2298 2299 /* Check for the data_count */ 2300 dsp_value = (task->data_count) ? 1 : 0; 2301 2302 if (is_chip_be2_be3r(phba)) 2303 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, 2304 pwrb, dsp_value); 2305 else 2306 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, 2307 pwrb, dsp_value); 2308 2309 /* Map addr only if there is data_count */ 2310 if (dsp_value) { 2311 io_task->mtask_addr = dma_map_single(&phba->pcidev->dev, 2312 task->data, 2313 task->data_count, 2314 DMA_TO_DEVICE); 2315 if (dma_mapping_error(&phba->pcidev->dev, 2316 io_task->mtask_addr)) 2317 return -ENOMEM; 2318 io_task->mtask_data_count = task->data_count; 2319 } else 2320 io_task->mtask_addr = 0; 2321 2322 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb, 2323 lower_32_bits(io_task->mtask_addr)); 2324 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb, 2325 upper_32_bits(io_task->mtask_addr)); 2326 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb, 2327 task->data_count); 2328 2329 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1); 2330 } else { 2331 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0); 2332 io_task->mtask_addr = 0; 2333 } 2334 2335 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; 2336 2337 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len); 2338 2339 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2340 io_task->bhs_pa.u.a32.address_hi); 2341 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2342 io_task->bhs_pa.u.a32.address_lo); 2343 if (task->data) { 2344 psgl++; 2345 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0); 2346 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0); 2347 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0); 2348 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0); 2349 AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0); 2350 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); 2351 2352 psgl++; 2353 if (task->data) { 2354 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2355 lower_32_bits(io_task->mtask_addr)); 2356 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2357 upper_32_bits(io_task->mtask_addr)); 2358 } 2359 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106); 2360 } 2361 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); 2362 return 0; 2363 } 2364 2365 /** 2366 * beiscsi_find_mem_req()- Find mem needed 2367 * @phba: ptr to HBA struct 2368 **/ 2369 static void beiscsi_find_mem_req(struct beiscsi_hba *phba) 2370 { 2371 uint8_t mem_descr_index, ulp_num; 2372 unsigned int num_async_pdu_buf_pages; 2373 unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn; 2374 unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages; 2375 2376 phba->params.hwi_ws_sz = sizeof(struct hwi_controller); 2377 2378 phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 * 2379 BE_ISCSI_PDU_HEADER_SIZE; 2380 phba->mem_req[HWI_MEM_ADDN_CONTEXT] = 2381 sizeof(struct hwi_context_memory); 2382 2383 2384 phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb) 2385 * (phba->params.wrbs_per_cxn) 2386 * phba->params.cxns_per_ctrl; 2387 wrb_sz_per_cxn = sizeof(struct wrb_handle) * 2388 (phba->params.wrbs_per_cxn); 2389 phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) * 2390 phba->params.cxns_per_ctrl); 2391 2392 phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) * 2393 phba->params.icds_per_ctrl; 2394 phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) * 2395 phba->params.num_sge_per_io * phba->params.icds_per_ctrl; 2396 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 2397 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 2398 2399 num_async_pdu_buf_sgl_pages = 2400 PAGES_REQUIRED(BEISCSI_ASYNC_HDQ_SIZE( 2401 phba, ulp_num) * 2402 sizeof(struct phys_addr)); 2403 2404 num_async_pdu_buf_pages = 2405 PAGES_REQUIRED(BEISCSI_ASYNC_HDQ_SIZE( 2406 phba, ulp_num) * 2407 phba->params.defpdu_hdr_sz); 2408 2409 num_async_pdu_data_pages = 2410 PAGES_REQUIRED(BEISCSI_ASYNC_HDQ_SIZE( 2411 phba, ulp_num) * 2412 phba->params.defpdu_data_sz); 2413 2414 num_async_pdu_data_sgl_pages = 2415 PAGES_REQUIRED(BEISCSI_ASYNC_HDQ_SIZE( 2416 phba, ulp_num) * 2417 sizeof(struct phys_addr)); 2418 2419 mem_descr_index = (HWI_MEM_TEMPLATE_HDR_ULP0 + 2420 (ulp_num * MEM_DESCR_OFFSET)); 2421 phba->mem_req[mem_descr_index] = 2422 BEISCSI_GET_CID_COUNT(phba, ulp_num) * 2423 BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE; 2424 2425 mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 + 2426 (ulp_num * MEM_DESCR_OFFSET)); 2427 phba->mem_req[mem_descr_index] = 2428 num_async_pdu_buf_pages * 2429 PAGE_SIZE; 2430 2431 mem_descr_index = (HWI_MEM_ASYNC_DATA_BUF_ULP0 + 2432 (ulp_num * MEM_DESCR_OFFSET)); 2433 phba->mem_req[mem_descr_index] = 2434 num_async_pdu_data_pages * 2435 PAGE_SIZE; 2436 2437 mem_descr_index = (HWI_MEM_ASYNC_HEADER_RING_ULP0 + 2438 (ulp_num * MEM_DESCR_OFFSET)); 2439 phba->mem_req[mem_descr_index] = 2440 num_async_pdu_buf_sgl_pages * 2441 PAGE_SIZE; 2442 2443 mem_descr_index = (HWI_MEM_ASYNC_DATA_RING_ULP0 + 2444 (ulp_num * MEM_DESCR_OFFSET)); 2445 phba->mem_req[mem_descr_index] = 2446 num_async_pdu_data_sgl_pages * 2447 PAGE_SIZE; 2448 2449 mem_descr_index = (HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 + 2450 (ulp_num * MEM_DESCR_OFFSET)); 2451 phba->mem_req[mem_descr_index] = 2452 BEISCSI_ASYNC_HDQ_SIZE(phba, ulp_num) * 2453 sizeof(struct hd_async_handle); 2454 2455 mem_descr_index = (HWI_MEM_ASYNC_DATA_HANDLE_ULP0 + 2456 (ulp_num * MEM_DESCR_OFFSET)); 2457 phba->mem_req[mem_descr_index] = 2458 BEISCSI_ASYNC_HDQ_SIZE(phba, ulp_num) * 2459 sizeof(struct hd_async_handle); 2460 2461 mem_descr_index = (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 + 2462 (ulp_num * MEM_DESCR_OFFSET)); 2463 phba->mem_req[mem_descr_index] = 2464 sizeof(struct hd_async_context) + 2465 (BEISCSI_ASYNC_HDQ_SIZE(phba, ulp_num) * 2466 sizeof(struct hd_async_entry)); 2467 } 2468 } 2469 } 2470 2471 static int beiscsi_alloc_mem(struct beiscsi_hba *phba) 2472 { 2473 dma_addr_t bus_add; 2474 struct hwi_controller *phwi_ctrlr; 2475 struct be_mem_descriptor *mem_descr; 2476 struct mem_array *mem_arr, *mem_arr_orig; 2477 unsigned int i, j, alloc_size, curr_alloc_size; 2478 2479 phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL); 2480 if (!phba->phwi_ctrlr) 2481 return -ENOMEM; 2482 2483 /* Allocate memory for wrb_context */ 2484 phwi_ctrlr = phba->phwi_ctrlr; 2485 phwi_ctrlr->wrb_context = kzalloc_objs(struct hwi_wrb_context, 2486 phba->params.cxns_per_ctrl); 2487 if (!phwi_ctrlr->wrb_context) { 2488 kfree(phba->phwi_ctrlr); 2489 return -ENOMEM; 2490 } 2491 2492 phba->init_mem = kzalloc_objs(*mem_descr, SE_MEM_MAX); 2493 if (!phba->init_mem) { 2494 kfree(phwi_ctrlr->wrb_context); 2495 kfree(phba->phwi_ctrlr); 2496 return -ENOMEM; 2497 } 2498 2499 mem_arr_orig = kmalloc_objs(*mem_arr_orig, BEISCSI_MAX_FRAGS_INIT); 2500 if (!mem_arr_orig) { 2501 kfree(phba->init_mem); 2502 kfree(phwi_ctrlr->wrb_context); 2503 kfree(phba->phwi_ctrlr); 2504 return -ENOMEM; 2505 } 2506 2507 mem_descr = phba->init_mem; 2508 for (i = 0; i < SE_MEM_MAX; i++) { 2509 if (!phba->mem_req[i]) { 2510 mem_descr->mem_array = NULL; 2511 mem_descr++; 2512 continue; 2513 } 2514 2515 j = 0; 2516 mem_arr = mem_arr_orig; 2517 alloc_size = phba->mem_req[i]; 2518 memset(mem_arr, 0, sizeof(struct mem_array) * 2519 BEISCSI_MAX_FRAGS_INIT); 2520 curr_alloc_size = min(be_max_phys_size * 1024, alloc_size); 2521 do { 2522 mem_arr->virtual_address = 2523 dma_alloc_coherent(&phba->pcidev->dev, 2524 curr_alloc_size, &bus_add, GFP_KERNEL); 2525 if (!mem_arr->virtual_address) { 2526 if (curr_alloc_size <= BE_MIN_MEM_SIZE) 2527 goto free_mem; 2528 if (curr_alloc_size - 2529 rounddown_pow_of_two(curr_alloc_size)) 2530 curr_alloc_size = rounddown_pow_of_two 2531 (curr_alloc_size); 2532 else 2533 curr_alloc_size = curr_alloc_size / 2; 2534 } else { 2535 mem_arr->bus_address.u. 2536 a64.address = (__u64) bus_add; 2537 mem_arr->size = curr_alloc_size; 2538 alloc_size -= curr_alloc_size; 2539 curr_alloc_size = min(be_max_phys_size * 2540 1024, alloc_size); 2541 j++; 2542 mem_arr++; 2543 } 2544 } while (alloc_size); 2545 mem_descr->num_elements = j; 2546 mem_descr->size_in_bytes = phba->mem_req[i]; 2547 mem_descr->mem_array = kmalloc_objs(*mem_arr, j); 2548 if (!mem_descr->mem_array) 2549 goto free_mem; 2550 2551 memcpy(mem_descr->mem_array, mem_arr_orig, 2552 sizeof(struct mem_array) * j); 2553 mem_descr++; 2554 } 2555 kfree(mem_arr_orig); 2556 return 0; 2557 free_mem: 2558 mem_descr->num_elements = j; 2559 while ((i) || (j)) { 2560 for (j = mem_descr->num_elements; j > 0; j--) { 2561 dma_free_coherent(&phba->pcidev->dev, 2562 mem_descr->mem_array[j - 1].size, 2563 mem_descr->mem_array[j - 1]. 2564 virtual_address, 2565 (unsigned long)mem_descr-> 2566 mem_array[j - 1]. 2567 bus_address.u.a64.address); 2568 } 2569 if (i) { 2570 i--; 2571 kfree(mem_descr->mem_array); 2572 mem_descr--; 2573 } 2574 } 2575 kfree(mem_arr_orig); 2576 kfree(phba->init_mem); 2577 kfree(phba->phwi_ctrlr->wrb_context); 2578 kfree(phba->phwi_ctrlr); 2579 return -ENOMEM; 2580 } 2581 2582 static int beiscsi_get_memory(struct beiscsi_hba *phba) 2583 { 2584 beiscsi_find_mem_req(phba); 2585 return beiscsi_alloc_mem(phba); 2586 } 2587 2588 static void iscsi_init_global_templates(struct beiscsi_hba *phba) 2589 { 2590 struct pdu_data_out *pdata_out; 2591 struct pdu_nop_out *pnop_out; 2592 struct be_mem_descriptor *mem_descr; 2593 2594 mem_descr = phba->init_mem; 2595 mem_descr += ISCSI_MEM_GLOBAL_HEADER; 2596 pdata_out = 2597 (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address; 2598 memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE); 2599 2600 AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out, 2601 IIOC_SCSI_DATA); 2602 2603 pnop_out = 2604 (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0]. 2605 virtual_address + BE_ISCSI_PDU_HEADER_SIZE); 2606 2607 memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE); 2608 AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF); 2609 AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1); 2610 AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0); 2611 } 2612 2613 static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba) 2614 { 2615 struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb; 2616 struct hwi_context_memory *phwi_ctxt; 2617 struct wrb_handle *pwrb_handle = NULL; 2618 struct hwi_controller *phwi_ctrlr; 2619 struct hwi_wrb_context *pwrb_context; 2620 struct iscsi_wrb *pwrb = NULL; 2621 unsigned int num_cxn_wrbh = 0; 2622 unsigned int num_cxn_wrb = 0, j, idx = 0, index; 2623 2624 mem_descr_wrbh = phba->init_mem; 2625 mem_descr_wrbh += HWI_MEM_WRBH; 2626 2627 mem_descr_wrb = phba->init_mem; 2628 mem_descr_wrb += HWI_MEM_WRB; 2629 phwi_ctrlr = phba->phwi_ctrlr; 2630 2631 /* Allocate memory for WRBQ */ 2632 phwi_ctxt = phwi_ctrlr->phwi_ctxt; 2633 phwi_ctxt->be_wrbq = kzalloc_objs(struct be_queue_info, 2634 phba->params.cxns_per_ctrl); 2635 if (!phwi_ctxt->be_wrbq) { 2636 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 2637 "BM_%d : WRBQ Mem Alloc Failed\n"); 2638 return -ENOMEM; 2639 } 2640 2641 for (index = 0; index < phba->params.cxns_per_ctrl; index++) { 2642 pwrb_context = &phwi_ctrlr->wrb_context[index]; 2643 pwrb_context->pwrb_handle_base = 2644 kzalloc_objs(struct wrb_handle *, 2645 phba->params.wrbs_per_cxn); 2646 if (!pwrb_context->pwrb_handle_base) { 2647 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 2648 "BM_%d : Mem Alloc Failed. Failing to load\n"); 2649 goto init_wrb_hndl_failed; 2650 } 2651 pwrb_context->pwrb_handle_basestd = 2652 kzalloc_objs(struct wrb_handle *, 2653 phba->params.wrbs_per_cxn); 2654 if (!pwrb_context->pwrb_handle_basestd) { 2655 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 2656 "BM_%d : Mem Alloc Failed. Failing to load\n"); 2657 goto init_wrb_hndl_failed; 2658 } 2659 if (!num_cxn_wrbh) { 2660 pwrb_handle = 2661 mem_descr_wrbh->mem_array[idx].virtual_address; 2662 num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) / 2663 ((sizeof(struct wrb_handle)) * 2664 phba->params.wrbs_per_cxn)); 2665 idx++; 2666 } 2667 pwrb_context->alloc_index = 0; 2668 pwrb_context->wrb_handles_available = 0; 2669 pwrb_context->free_index = 0; 2670 2671 if (num_cxn_wrbh) { 2672 for (j = 0; j < phba->params.wrbs_per_cxn; j++) { 2673 pwrb_context->pwrb_handle_base[j] = pwrb_handle; 2674 pwrb_context->pwrb_handle_basestd[j] = 2675 pwrb_handle; 2676 pwrb_context->wrb_handles_available++; 2677 pwrb_handle->wrb_index = j; 2678 pwrb_handle++; 2679 } 2680 num_cxn_wrbh--; 2681 } 2682 spin_lock_init(&pwrb_context->wrb_lock); 2683 } 2684 idx = 0; 2685 for (index = 0; index < phba->params.cxns_per_ctrl; index++) { 2686 pwrb_context = &phwi_ctrlr->wrb_context[index]; 2687 if (!num_cxn_wrb) { 2688 pwrb = mem_descr_wrb->mem_array[idx].virtual_address; 2689 num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) / 2690 ((sizeof(struct iscsi_wrb) * 2691 phba->params.wrbs_per_cxn)); 2692 idx++; 2693 } 2694 2695 if (num_cxn_wrb) { 2696 for (j = 0; j < phba->params.wrbs_per_cxn; j++) { 2697 pwrb_handle = pwrb_context->pwrb_handle_base[j]; 2698 pwrb_handle->pwrb = pwrb; 2699 pwrb++; 2700 } 2701 num_cxn_wrb--; 2702 } 2703 } 2704 return 0; 2705 init_wrb_hndl_failed: 2706 for (j = index; j > 0; j--) { 2707 pwrb_context = &phwi_ctrlr->wrb_context[j]; 2708 kfree(pwrb_context->pwrb_handle_base); 2709 kfree(pwrb_context->pwrb_handle_basestd); 2710 } 2711 kfree(phwi_ctxt->be_wrbq); 2712 return -ENOMEM; 2713 } 2714 2715 static int hwi_init_async_pdu_ctx(struct beiscsi_hba *phba) 2716 { 2717 uint8_t ulp_num; 2718 struct hwi_controller *phwi_ctrlr; 2719 struct hba_parameters *p = &phba->params; 2720 struct hd_async_context *pasync_ctx; 2721 struct hd_async_handle *pasync_header_h, *pasync_data_h; 2722 unsigned int index, idx, num_per_mem, num_async_data; 2723 struct be_mem_descriptor *mem_descr; 2724 2725 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 2726 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 2727 /* get async_ctx for each ULP */ 2728 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2729 mem_descr += (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 + 2730 (ulp_num * MEM_DESCR_OFFSET)); 2731 2732 phwi_ctrlr = phba->phwi_ctrlr; 2733 phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num] = 2734 (struct hd_async_context *) 2735 mem_descr->mem_array[0].virtual_address; 2736 2737 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num]; 2738 memset(pasync_ctx, 0, sizeof(*pasync_ctx)); 2739 2740 pasync_ctx->async_entry = 2741 (struct hd_async_entry *) 2742 ((long unsigned int)pasync_ctx + 2743 sizeof(struct hd_async_context)); 2744 2745 pasync_ctx->num_entries = BEISCSI_ASYNC_HDQ_SIZE(phba, 2746 ulp_num); 2747 /* setup header buffers */ 2748 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2749 mem_descr += HWI_MEM_ASYNC_HEADER_BUF_ULP0 + 2750 (ulp_num * MEM_DESCR_OFFSET); 2751 if (mem_descr->mem_array[0].virtual_address) { 2752 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 2753 "BM_%d : hwi_init_async_pdu_ctx" 2754 " HWI_MEM_ASYNC_HEADER_BUF_ULP%d va=%p\n", 2755 ulp_num, 2756 mem_descr->mem_array[0]. 2757 virtual_address); 2758 } else 2759 beiscsi_log(phba, KERN_WARNING, 2760 BEISCSI_LOG_INIT, 2761 "BM_%d : No Virtual address for ULP : %d\n", 2762 ulp_num); 2763 2764 pasync_ctx->async_header.pi = 0; 2765 pasync_ctx->async_header.buffer_size = p->defpdu_hdr_sz; 2766 pasync_ctx->async_header.va_base = 2767 mem_descr->mem_array[0].virtual_address; 2768 2769 pasync_ctx->async_header.pa_base.u.a64.address = 2770 mem_descr->mem_array[0]. 2771 bus_address.u.a64.address; 2772 2773 /* setup header buffer sgls */ 2774 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2775 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 + 2776 (ulp_num * MEM_DESCR_OFFSET); 2777 if (mem_descr->mem_array[0].virtual_address) { 2778 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 2779 "BM_%d : hwi_init_async_pdu_ctx" 2780 " HWI_MEM_ASYNC_HEADER_RING_ULP%d va=%p\n", 2781 ulp_num, 2782 mem_descr->mem_array[0]. 2783 virtual_address); 2784 } else 2785 beiscsi_log(phba, KERN_WARNING, 2786 BEISCSI_LOG_INIT, 2787 "BM_%d : No Virtual address for ULP : %d\n", 2788 ulp_num); 2789 2790 pasync_ctx->async_header.ring_base = 2791 mem_descr->mem_array[0].virtual_address; 2792 2793 /* setup header buffer handles */ 2794 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2795 mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 + 2796 (ulp_num * MEM_DESCR_OFFSET); 2797 if (mem_descr->mem_array[0].virtual_address) { 2798 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 2799 "BM_%d : hwi_init_async_pdu_ctx" 2800 " HWI_MEM_ASYNC_HEADER_HANDLE_ULP%d va=%p\n", 2801 ulp_num, 2802 mem_descr->mem_array[0]. 2803 virtual_address); 2804 } else 2805 beiscsi_log(phba, KERN_WARNING, 2806 BEISCSI_LOG_INIT, 2807 "BM_%d : No Virtual address for ULP : %d\n", 2808 ulp_num); 2809 2810 pasync_ctx->async_header.handle_base = 2811 mem_descr->mem_array[0].virtual_address; 2812 2813 /* setup data buffer sgls */ 2814 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2815 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 + 2816 (ulp_num * MEM_DESCR_OFFSET); 2817 if (mem_descr->mem_array[0].virtual_address) { 2818 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 2819 "BM_%d : hwi_init_async_pdu_ctx" 2820 " HWI_MEM_ASYNC_DATA_RING_ULP%d va=%p\n", 2821 ulp_num, 2822 mem_descr->mem_array[0]. 2823 virtual_address); 2824 } else 2825 beiscsi_log(phba, KERN_WARNING, 2826 BEISCSI_LOG_INIT, 2827 "BM_%d : No Virtual address for ULP : %d\n", 2828 ulp_num); 2829 2830 pasync_ctx->async_data.ring_base = 2831 mem_descr->mem_array[0].virtual_address; 2832 2833 /* setup data buffer handles */ 2834 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2835 mem_descr += HWI_MEM_ASYNC_DATA_HANDLE_ULP0 + 2836 (ulp_num * MEM_DESCR_OFFSET); 2837 if (!mem_descr->mem_array[0].virtual_address) 2838 beiscsi_log(phba, KERN_WARNING, 2839 BEISCSI_LOG_INIT, 2840 "BM_%d : No Virtual address for ULP : %d\n", 2841 ulp_num); 2842 2843 pasync_ctx->async_data.handle_base = 2844 mem_descr->mem_array[0].virtual_address; 2845 2846 pasync_header_h = 2847 (struct hd_async_handle *) 2848 pasync_ctx->async_header.handle_base; 2849 pasync_data_h = 2850 (struct hd_async_handle *) 2851 pasync_ctx->async_data.handle_base; 2852 2853 /* setup data buffers */ 2854 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2855 mem_descr += HWI_MEM_ASYNC_DATA_BUF_ULP0 + 2856 (ulp_num * MEM_DESCR_OFFSET); 2857 if (mem_descr->mem_array[0].virtual_address) { 2858 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 2859 "BM_%d : hwi_init_async_pdu_ctx" 2860 " HWI_MEM_ASYNC_DATA_BUF_ULP%d va=%p\n", 2861 ulp_num, 2862 mem_descr->mem_array[0]. 2863 virtual_address); 2864 } else 2865 beiscsi_log(phba, KERN_WARNING, 2866 BEISCSI_LOG_INIT, 2867 "BM_%d : No Virtual address for ULP : %d\n", 2868 ulp_num); 2869 2870 idx = 0; 2871 pasync_ctx->async_data.pi = 0; 2872 pasync_ctx->async_data.buffer_size = p->defpdu_data_sz; 2873 pasync_ctx->async_data.va_base = 2874 mem_descr->mem_array[idx].virtual_address; 2875 pasync_ctx->async_data.pa_base.u.a64.address = 2876 mem_descr->mem_array[idx]. 2877 bus_address.u.a64.address; 2878 2879 num_async_data = ((mem_descr->mem_array[idx].size) / 2880 phba->params.defpdu_data_sz); 2881 num_per_mem = 0; 2882 2883 for (index = 0; index < BEISCSI_ASYNC_HDQ_SIZE 2884 (phba, ulp_num); index++) { 2885 pasync_header_h->cri = -1; 2886 pasync_header_h->is_header = 1; 2887 pasync_header_h->index = index; 2888 INIT_LIST_HEAD(&pasync_header_h->link); 2889 pasync_header_h->pbuffer = 2890 (void *)((unsigned long) 2891 (pasync_ctx-> 2892 async_header.va_base) + 2893 (p->defpdu_hdr_sz * index)); 2894 2895 pasync_header_h->pa.u.a64.address = 2896 pasync_ctx->async_header.pa_base.u.a64. 2897 address + (p->defpdu_hdr_sz * index); 2898 2899 pasync_ctx->async_entry[index].header = 2900 pasync_header_h; 2901 pasync_header_h++; 2902 INIT_LIST_HEAD(&pasync_ctx->async_entry[index]. 2903 wq.list); 2904 2905 pasync_data_h->cri = -1; 2906 pasync_data_h->is_header = 0; 2907 pasync_data_h->index = index; 2908 INIT_LIST_HEAD(&pasync_data_h->link); 2909 2910 if (!num_async_data) { 2911 num_per_mem = 0; 2912 idx++; 2913 pasync_ctx->async_data.va_base = 2914 mem_descr->mem_array[idx]. 2915 virtual_address; 2916 pasync_ctx->async_data.pa_base.u. 2917 a64.address = 2918 mem_descr->mem_array[idx]. 2919 bus_address.u.a64.address; 2920 num_async_data = 2921 ((mem_descr->mem_array[idx]. 2922 size) / 2923 phba->params.defpdu_data_sz); 2924 } 2925 pasync_data_h->pbuffer = 2926 (void *)((unsigned long) 2927 (pasync_ctx->async_data.va_base) + 2928 (p->defpdu_data_sz * num_per_mem)); 2929 2930 pasync_data_h->pa.u.a64.address = 2931 pasync_ctx->async_data.pa_base.u.a64. 2932 address + (p->defpdu_data_sz * 2933 num_per_mem); 2934 num_per_mem++; 2935 num_async_data--; 2936 2937 pasync_ctx->async_entry[index].data = 2938 pasync_data_h; 2939 pasync_data_h++; 2940 } 2941 } 2942 } 2943 2944 return 0; 2945 } 2946 2947 static int 2948 be_sgl_create_contiguous(void *virtual_address, 2949 u64 physical_address, u32 length, 2950 struct be_dma_mem *sgl) 2951 { 2952 WARN_ON(!virtual_address); 2953 WARN_ON(!physical_address); 2954 WARN_ON(!length); 2955 WARN_ON(!sgl); 2956 2957 sgl->va = virtual_address; 2958 sgl->dma = (unsigned long)physical_address; 2959 sgl->size = length; 2960 2961 return 0; 2962 } 2963 2964 static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl) 2965 { 2966 memset(sgl, 0, sizeof(*sgl)); 2967 } 2968 2969 static void 2970 hwi_build_be_sgl_arr(struct beiscsi_hba *phba, 2971 struct mem_array *pmem, struct be_dma_mem *sgl) 2972 { 2973 if (sgl->va) 2974 be_sgl_destroy_contiguous(sgl); 2975 2976 be_sgl_create_contiguous(pmem->virtual_address, 2977 pmem->bus_address.u.a64.address, 2978 pmem->size, sgl); 2979 } 2980 2981 static void 2982 hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba, 2983 struct mem_array *pmem, struct be_dma_mem *sgl) 2984 { 2985 if (sgl->va) 2986 be_sgl_destroy_contiguous(sgl); 2987 2988 be_sgl_create_contiguous((unsigned char *)pmem->virtual_address, 2989 pmem->bus_address.u.a64.address, 2990 pmem->size, sgl); 2991 } 2992 2993 static int be_fill_queue(struct be_queue_info *q, 2994 u16 len, u16 entry_size, void *vaddress) 2995 { 2996 struct be_dma_mem *mem = &q->dma_mem; 2997 2998 memset(q, 0, sizeof(*q)); 2999 q->len = len; 3000 q->entry_size = entry_size; 3001 mem->size = len * entry_size; 3002 mem->va = vaddress; 3003 if (!mem->va) 3004 return -ENOMEM; 3005 memset(mem->va, 0, mem->size); 3006 return 0; 3007 } 3008 3009 static int beiscsi_create_eqs(struct beiscsi_hba *phba, 3010 struct hwi_context_memory *phwi_context) 3011 { 3012 int ret = -ENOMEM, eq_for_mcc; 3013 unsigned int i, num_eq_pages; 3014 struct be_queue_info *eq; 3015 struct be_dma_mem *mem; 3016 void *eq_vaddress; 3017 dma_addr_t paddr; 3018 3019 num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * 3020 sizeof(struct be_eq_entry)); 3021 3022 if (phba->pcidev->msix_enabled) 3023 eq_for_mcc = 1; 3024 else 3025 eq_for_mcc = 0; 3026 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) { 3027 eq = &phwi_context->be_eq[i].q; 3028 mem = &eq->dma_mem; 3029 phwi_context->be_eq[i].phba = phba; 3030 eq_vaddress = dma_alloc_coherent(&phba->pcidev->dev, 3031 num_eq_pages * PAGE_SIZE, 3032 &paddr, GFP_KERNEL); 3033 if (!eq_vaddress) { 3034 ret = -ENOMEM; 3035 goto create_eq_error; 3036 } 3037 3038 mem->va = eq_vaddress; 3039 ret = be_fill_queue(eq, phba->params.num_eq_entries, 3040 sizeof(struct be_eq_entry), eq_vaddress); 3041 if (ret) { 3042 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3043 "BM_%d : be_fill_queue Failed for EQ\n"); 3044 goto create_eq_error; 3045 } 3046 3047 mem->dma = paddr; 3048 ret = beiscsi_cmd_eq_create(&phba->ctrl, eq, 3049 BEISCSI_EQ_DELAY_DEF); 3050 if (ret) { 3051 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3052 "BM_%d : beiscsi_cmd_eq_create Failed for EQ\n"); 3053 goto create_eq_error; 3054 } 3055 3056 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3057 "BM_%d : eqid = %d\n", 3058 phwi_context->be_eq[i].q.id); 3059 } 3060 return 0; 3061 3062 create_eq_error: 3063 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) { 3064 eq = &phwi_context->be_eq[i].q; 3065 mem = &eq->dma_mem; 3066 if (mem->va) 3067 dma_free_coherent(&phba->pcidev->dev, num_eq_pages 3068 * PAGE_SIZE, 3069 mem->va, mem->dma); 3070 } 3071 return ret; 3072 } 3073 3074 static int beiscsi_create_cqs(struct beiscsi_hba *phba, 3075 struct hwi_context_memory *phwi_context) 3076 { 3077 unsigned int i, num_cq_pages; 3078 struct be_queue_info *cq, *eq; 3079 struct be_dma_mem *mem; 3080 struct be_eq_obj *pbe_eq; 3081 void *cq_vaddress; 3082 int ret = -ENOMEM; 3083 dma_addr_t paddr; 3084 3085 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * 3086 sizeof(struct sol_cqe)); 3087 3088 for (i = 0; i < phba->num_cpus; i++) { 3089 cq = &phwi_context->be_cq[i]; 3090 eq = &phwi_context->be_eq[i].q; 3091 pbe_eq = &phwi_context->be_eq[i]; 3092 pbe_eq->cq = cq; 3093 pbe_eq->phba = phba; 3094 mem = &cq->dma_mem; 3095 cq_vaddress = dma_alloc_coherent(&phba->pcidev->dev, 3096 num_cq_pages * PAGE_SIZE, 3097 &paddr, GFP_KERNEL); 3098 if (!cq_vaddress) { 3099 ret = -ENOMEM; 3100 goto create_cq_error; 3101 } 3102 3103 ret = be_fill_queue(cq, phba->params.num_cq_entries, 3104 sizeof(struct sol_cqe), cq_vaddress); 3105 if (ret) { 3106 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3107 "BM_%d : be_fill_queue Failed for ISCSI CQ\n"); 3108 goto create_cq_error; 3109 } 3110 3111 mem->dma = paddr; 3112 ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false, 3113 false, 0); 3114 if (ret) { 3115 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3116 "BM_%d : beiscsi_cmd_eq_create Failed for ISCSI CQ\n"); 3117 goto create_cq_error; 3118 } 3119 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3120 "BM_%d : iscsi cq_id is %d for eq_id %d\n" 3121 "iSCSI CQ CREATED\n", cq->id, eq->id); 3122 } 3123 return 0; 3124 3125 create_cq_error: 3126 for (i = 0; i < phba->num_cpus; i++) { 3127 cq = &phwi_context->be_cq[i]; 3128 mem = &cq->dma_mem; 3129 if (mem->va) 3130 dma_free_coherent(&phba->pcidev->dev, num_cq_pages 3131 * PAGE_SIZE, 3132 mem->va, mem->dma); 3133 } 3134 return ret; 3135 } 3136 3137 static int 3138 beiscsi_create_def_hdr(struct beiscsi_hba *phba, 3139 struct hwi_context_memory *phwi_context, 3140 struct hwi_controller *phwi_ctrlr, 3141 unsigned int def_pdu_ring_sz, uint8_t ulp_num) 3142 { 3143 unsigned int idx; 3144 int ret; 3145 struct be_queue_info *dq, *cq; 3146 struct be_dma_mem *mem; 3147 struct be_mem_descriptor *mem_descr; 3148 void *dq_vaddress; 3149 3150 idx = 0; 3151 dq = &phwi_context->be_def_hdrq[ulp_num]; 3152 cq = &phwi_context->be_cq[0]; 3153 mem = &dq->dma_mem; 3154 mem_descr = phba->init_mem; 3155 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 + 3156 (ulp_num * MEM_DESCR_OFFSET); 3157 dq_vaddress = mem_descr->mem_array[idx].virtual_address; 3158 ret = be_fill_queue(dq, mem_descr->mem_array[0].size / 3159 sizeof(struct phys_addr), 3160 sizeof(struct phys_addr), dq_vaddress); 3161 if (ret) { 3162 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3163 "BM_%d : be_fill_queue Failed for DEF PDU HDR on ULP : %d\n", 3164 ulp_num); 3165 3166 return ret; 3167 } 3168 mem->dma = (unsigned long)mem_descr->mem_array[idx]. 3169 bus_address.u.a64.address; 3170 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq, 3171 def_pdu_ring_sz, 3172 phba->params.defpdu_hdr_sz, 3173 BEISCSI_DEFQ_HDR, ulp_num); 3174 if (ret) { 3175 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3176 "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR on ULP : %d\n", 3177 ulp_num); 3178 3179 return ret; 3180 } 3181 3182 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3183 "BM_%d : iscsi hdr def pdu id for ULP : %d is %d\n", 3184 ulp_num, 3185 phwi_context->be_def_hdrq[ulp_num].id); 3186 return 0; 3187 } 3188 3189 static int 3190 beiscsi_create_def_data(struct beiscsi_hba *phba, 3191 struct hwi_context_memory *phwi_context, 3192 struct hwi_controller *phwi_ctrlr, 3193 unsigned int def_pdu_ring_sz, uint8_t ulp_num) 3194 { 3195 unsigned int idx; 3196 int ret; 3197 struct be_queue_info *dataq, *cq; 3198 struct be_dma_mem *mem; 3199 struct be_mem_descriptor *mem_descr; 3200 void *dq_vaddress; 3201 3202 idx = 0; 3203 dataq = &phwi_context->be_def_dataq[ulp_num]; 3204 cq = &phwi_context->be_cq[0]; 3205 mem = &dataq->dma_mem; 3206 mem_descr = phba->init_mem; 3207 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 + 3208 (ulp_num * MEM_DESCR_OFFSET); 3209 dq_vaddress = mem_descr->mem_array[idx].virtual_address; 3210 ret = be_fill_queue(dataq, mem_descr->mem_array[0].size / 3211 sizeof(struct phys_addr), 3212 sizeof(struct phys_addr), dq_vaddress); 3213 if (ret) { 3214 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3215 "BM_%d : be_fill_queue Failed for DEF PDU " 3216 "DATA on ULP : %d\n", 3217 ulp_num); 3218 3219 return ret; 3220 } 3221 mem->dma = (unsigned long)mem_descr->mem_array[idx]. 3222 bus_address.u.a64.address; 3223 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq, 3224 def_pdu_ring_sz, 3225 phba->params.defpdu_data_sz, 3226 BEISCSI_DEFQ_DATA, ulp_num); 3227 if (ret) { 3228 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3229 "BM_%d be_cmd_create_default_pdu_queue" 3230 " Failed for DEF PDU DATA on ULP : %d\n", 3231 ulp_num); 3232 return ret; 3233 } 3234 3235 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3236 "BM_%d : iscsi def data id on ULP : %d is %d\n", 3237 ulp_num, 3238 phwi_context->be_def_dataq[ulp_num].id); 3239 3240 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3241 "BM_%d : DEFAULT PDU DATA RING CREATED on ULP : %d\n", 3242 ulp_num); 3243 return 0; 3244 } 3245 3246 3247 static int 3248 beiscsi_post_template_hdr(struct beiscsi_hba *phba) 3249 { 3250 struct be_mem_descriptor *mem_descr; 3251 struct mem_array *pm_arr; 3252 struct be_dma_mem sgl; 3253 int status, ulp_num; 3254 3255 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 3256 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 3257 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 3258 mem_descr += HWI_MEM_TEMPLATE_HDR_ULP0 + 3259 (ulp_num * MEM_DESCR_OFFSET); 3260 pm_arr = mem_descr->mem_array; 3261 3262 hwi_build_be_sgl_arr(phba, pm_arr, &sgl); 3263 status = be_cmd_iscsi_post_template_hdr( 3264 &phba->ctrl, &sgl); 3265 3266 if (status != 0) { 3267 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3268 "BM_%d : Post Template HDR Failed for " 3269 "ULP_%d\n", ulp_num); 3270 return status; 3271 } 3272 3273 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3274 "BM_%d : Template HDR Pages Posted for " 3275 "ULP_%d\n", ulp_num); 3276 } 3277 } 3278 return 0; 3279 } 3280 3281 static int 3282 beiscsi_post_pages(struct beiscsi_hba *phba) 3283 { 3284 struct be_mem_descriptor *mem_descr; 3285 struct mem_array *pm_arr; 3286 unsigned int page_offset, i; 3287 struct be_dma_mem sgl; 3288 int status, ulp_num = 0; 3289 3290 mem_descr = phba->init_mem; 3291 mem_descr += HWI_MEM_SGE; 3292 pm_arr = mem_descr->mem_array; 3293 3294 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) 3295 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) 3296 break; 3297 3298 page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io * 3299 phba->fw_config.iscsi_icd_start[ulp_num]) / PAGE_SIZE; 3300 for (i = 0; i < mem_descr->num_elements; i++) { 3301 hwi_build_be_sgl_arr(phba, pm_arr, &sgl); 3302 status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl, 3303 page_offset, 3304 (pm_arr->size / PAGE_SIZE)); 3305 page_offset += pm_arr->size / PAGE_SIZE; 3306 if (status != 0) { 3307 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3308 "BM_%d : post sgl failed.\n"); 3309 return status; 3310 } 3311 pm_arr++; 3312 } 3313 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3314 "BM_%d : POSTED PAGES\n"); 3315 return 0; 3316 } 3317 3318 static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q) 3319 { 3320 struct be_dma_mem *mem = &q->dma_mem; 3321 if (mem->va) { 3322 dma_free_coherent(&phba->pcidev->dev, mem->size, 3323 mem->va, mem->dma); 3324 mem->va = NULL; 3325 } 3326 } 3327 3328 static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q, 3329 u16 len, u16 entry_size) 3330 { 3331 struct be_dma_mem *mem = &q->dma_mem; 3332 3333 memset(q, 0, sizeof(*q)); 3334 q->len = len; 3335 q->entry_size = entry_size; 3336 mem->size = len * entry_size; 3337 mem->va = dma_alloc_coherent(&phba->pcidev->dev, mem->size, &mem->dma, 3338 GFP_KERNEL); 3339 if (!mem->va) 3340 return -ENOMEM; 3341 return 0; 3342 } 3343 3344 static int 3345 beiscsi_create_wrb_rings(struct beiscsi_hba *phba, 3346 struct hwi_context_memory *phwi_context, 3347 struct hwi_controller *phwi_ctrlr) 3348 { 3349 unsigned int num_wrb_rings; 3350 u64 pa_addr_lo; 3351 unsigned int idx, num, i, ulp_num; 3352 struct mem_array *pwrb_arr; 3353 void *wrb_vaddr; 3354 struct be_dma_mem sgl; 3355 struct be_mem_descriptor *mem_descr; 3356 struct hwi_wrb_context *pwrb_context; 3357 int status; 3358 uint8_t ulp_count = 0, ulp_base_num = 0; 3359 uint16_t cid_count_ulp[BEISCSI_ULP_COUNT] = { 0 }; 3360 3361 idx = 0; 3362 mem_descr = phba->init_mem; 3363 mem_descr += HWI_MEM_WRB; 3364 pwrb_arr = kmalloc_objs(*pwrb_arr, phba->params.cxns_per_ctrl); 3365 if (!pwrb_arr) { 3366 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3367 "BM_%d : Memory alloc failed in create wrb ring.\n"); 3368 return -ENOMEM; 3369 } 3370 wrb_vaddr = mem_descr->mem_array[idx].virtual_address; 3371 pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address; 3372 num_wrb_rings = mem_descr->mem_array[idx].size / 3373 (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb)); 3374 3375 for (num = 0; num < phba->params.cxns_per_ctrl; num++) { 3376 if (num_wrb_rings) { 3377 pwrb_arr[num].virtual_address = wrb_vaddr; 3378 pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo; 3379 pwrb_arr[num].size = phba->params.wrbs_per_cxn * 3380 sizeof(struct iscsi_wrb); 3381 wrb_vaddr += pwrb_arr[num].size; 3382 pa_addr_lo += pwrb_arr[num].size; 3383 num_wrb_rings--; 3384 } else { 3385 idx++; 3386 wrb_vaddr = mem_descr->mem_array[idx].virtual_address; 3387 pa_addr_lo = mem_descr->mem_array[idx]. 3388 bus_address.u.a64.address; 3389 num_wrb_rings = mem_descr->mem_array[idx].size / 3390 (phba->params.wrbs_per_cxn * 3391 sizeof(struct iscsi_wrb)); 3392 pwrb_arr[num].virtual_address = wrb_vaddr; 3393 pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo; 3394 pwrb_arr[num].size = phba->params.wrbs_per_cxn * 3395 sizeof(struct iscsi_wrb); 3396 wrb_vaddr += pwrb_arr[num].size; 3397 pa_addr_lo += pwrb_arr[num].size; 3398 num_wrb_rings--; 3399 } 3400 } 3401 3402 /* Get the ULP Count */ 3403 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) 3404 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 3405 ulp_count++; 3406 ulp_base_num = ulp_num; 3407 cid_count_ulp[ulp_num] = 3408 BEISCSI_GET_CID_COUNT(phba, ulp_num); 3409 } 3410 3411 for (i = 0; i < phba->params.cxns_per_ctrl; i++) { 3412 if (ulp_count > 1) { 3413 ulp_base_num = (ulp_base_num + 1) % BEISCSI_ULP_COUNT; 3414 3415 if (!cid_count_ulp[ulp_base_num]) 3416 ulp_base_num = (ulp_base_num + 1) % 3417 BEISCSI_ULP_COUNT; 3418 3419 cid_count_ulp[ulp_base_num]--; 3420 } 3421 3422 3423 hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl); 3424 status = be_cmd_wrbq_create(&phba->ctrl, &sgl, 3425 &phwi_context->be_wrbq[i], 3426 &phwi_ctrlr->wrb_context[i], 3427 ulp_base_num); 3428 if (status != 0) { 3429 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3430 "BM_%d : wrbq create failed."); 3431 kfree(pwrb_arr); 3432 return status; 3433 } 3434 pwrb_context = &phwi_ctrlr->wrb_context[i]; 3435 BE_SET_CID_TO_CRI(i, pwrb_context->cid); 3436 } 3437 kfree(pwrb_arr); 3438 return 0; 3439 } 3440 3441 static void free_wrb_handles(struct beiscsi_hba *phba) 3442 { 3443 unsigned int index; 3444 struct hwi_controller *phwi_ctrlr; 3445 struct hwi_wrb_context *pwrb_context; 3446 3447 phwi_ctrlr = phba->phwi_ctrlr; 3448 for (index = 0; index < phba->params.cxns_per_ctrl; index++) { 3449 pwrb_context = &phwi_ctrlr->wrb_context[index]; 3450 kfree(pwrb_context->pwrb_handle_base); 3451 kfree(pwrb_context->pwrb_handle_basestd); 3452 } 3453 } 3454 3455 static void be_mcc_queues_destroy(struct beiscsi_hba *phba) 3456 { 3457 struct be_ctrl_info *ctrl = &phba->ctrl; 3458 struct be_dma_mem *ptag_mem; 3459 struct be_queue_info *q; 3460 int i, tag; 3461 3462 q = &phba->ctrl.mcc_obj.q; 3463 for (i = 0; i < MAX_MCC_CMD; i++) { 3464 tag = i + 1; 3465 if (!test_bit(MCC_TAG_STATE_RUNNING, 3466 &ctrl->ptag_state[tag].tag_state)) 3467 continue; 3468 3469 if (test_bit(MCC_TAG_STATE_TIMEOUT, 3470 &ctrl->ptag_state[tag].tag_state)) { 3471 ptag_mem = &ctrl->ptag_state[tag].tag_mem_state; 3472 if (ptag_mem->size) { 3473 dma_free_coherent(&ctrl->pdev->dev, 3474 ptag_mem->size, 3475 ptag_mem->va, 3476 ptag_mem->dma); 3477 ptag_mem->size = 0; 3478 } 3479 continue; 3480 } 3481 /** 3482 * If MCC is still active and waiting then wake up the process. 3483 * We are here only because port is going offline. The process 3484 * sees that (BEISCSI_HBA_ONLINE is cleared) and EIO error is 3485 * returned for the operation and allocated memory cleaned up. 3486 */ 3487 if (waitqueue_active(&ctrl->mcc_wait[tag])) { 3488 ctrl->mcc_tag_status[tag] = MCC_STATUS_FAILED; 3489 ctrl->mcc_tag_status[tag] |= CQE_VALID_MASK; 3490 wake_up_interruptible(&ctrl->mcc_wait[tag]); 3491 /* 3492 * Control tag info gets reinitialized in enable 3493 * so wait for the process to clear running state. 3494 */ 3495 while (test_bit(MCC_TAG_STATE_RUNNING, 3496 &ctrl->ptag_state[tag].tag_state)) 3497 schedule_timeout_uninterruptible(HZ); 3498 } 3499 /** 3500 * For MCC with tag_states MCC_TAG_STATE_ASYNC and 3501 * MCC_TAG_STATE_IGNORE nothing needs to done. 3502 */ 3503 } 3504 if (q->created) { 3505 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ); 3506 be_queue_free(phba, q); 3507 } 3508 3509 q = &phba->ctrl.mcc_obj.cq; 3510 if (q->created) { 3511 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ); 3512 be_queue_free(phba, q); 3513 } 3514 } 3515 3516 static int be_mcc_queues_create(struct beiscsi_hba *phba, 3517 struct hwi_context_memory *phwi_context) 3518 { 3519 struct be_queue_info *q, *cq; 3520 struct be_ctrl_info *ctrl = &phba->ctrl; 3521 3522 /* Alloc MCC compl queue */ 3523 cq = &phba->ctrl.mcc_obj.cq; 3524 if (be_queue_alloc(phba, cq, MCC_CQ_LEN, 3525 sizeof(struct be_mcc_compl))) 3526 goto err; 3527 /* Ask BE to create MCC compl queue; */ 3528 if (phba->pcidev->msix_enabled) { 3529 if (beiscsi_cmd_cq_create(ctrl, cq, 3530 &phwi_context->be_eq[phba->num_cpus].q, 3531 false, true, 0)) 3532 goto mcc_cq_free; 3533 } else { 3534 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q, 3535 false, true, 0)) 3536 goto mcc_cq_free; 3537 } 3538 3539 /* Alloc MCC queue */ 3540 q = &phba->ctrl.mcc_obj.q; 3541 if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb))) 3542 goto mcc_cq_destroy; 3543 3544 /* Ask BE to create MCC queue */ 3545 if (beiscsi_cmd_mccq_create(phba, q, cq)) 3546 goto mcc_q_free; 3547 3548 return 0; 3549 3550 mcc_q_free: 3551 be_queue_free(phba, q); 3552 mcc_cq_destroy: 3553 beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ); 3554 mcc_cq_free: 3555 be_queue_free(phba, cq); 3556 err: 3557 return -ENOMEM; 3558 } 3559 3560 static void be2iscsi_enable_msix(struct beiscsi_hba *phba) 3561 { 3562 int nvec = 1; 3563 3564 switch (phba->generation) { 3565 case BE_GEN2: 3566 case BE_GEN3: 3567 nvec = BEISCSI_MAX_NUM_CPUS + 1; 3568 break; 3569 case BE_GEN4: 3570 nvec = phba->fw_config.eqid_count; 3571 break; 3572 default: 3573 nvec = 2; 3574 break; 3575 } 3576 3577 /* if eqid_count == 1 fall back to INTX */ 3578 if (enable_msix && nvec > 1) { 3579 struct irq_affinity desc = { .post_vectors = 1 }; 3580 3581 if (pci_alloc_irq_vectors_affinity(phba->pcidev, 2, nvec, 3582 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc) < 0) { 3583 phba->num_cpus = nvec - 1; 3584 return; 3585 } 3586 } 3587 3588 phba->num_cpus = 1; 3589 } 3590 3591 static void hwi_purge_eq(struct beiscsi_hba *phba) 3592 { 3593 struct hwi_controller *phwi_ctrlr; 3594 struct hwi_context_memory *phwi_context; 3595 struct be_queue_info *eq; 3596 struct be_eq_entry *eqe = NULL; 3597 int i, eq_msix; 3598 unsigned int num_processed; 3599 3600 if (beiscsi_hba_in_error(phba)) 3601 return; 3602 3603 phwi_ctrlr = phba->phwi_ctrlr; 3604 phwi_context = phwi_ctrlr->phwi_ctxt; 3605 if (phba->pcidev->msix_enabled) 3606 eq_msix = 1; 3607 else 3608 eq_msix = 0; 3609 3610 for (i = 0; i < (phba->num_cpus + eq_msix); i++) { 3611 eq = &phwi_context->be_eq[i].q; 3612 eqe = queue_tail_node(eq); 3613 num_processed = 0; 3614 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] 3615 & EQE_VALID_MASK) { 3616 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 3617 queue_tail_inc(eq); 3618 eqe = queue_tail_node(eq); 3619 num_processed++; 3620 } 3621 3622 if (num_processed) 3623 hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1); 3624 } 3625 } 3626 3627 static void hwi_cleanup_port(struct beiscsi_hba *phba) 3628 { 3629 struct be_queue_info *q; 3630 struct be_ctrl_info *ctrl = &phba->ctrl; 3631 struct hwi_controller *phwi_ctrlr; 3632 struct hwi_context_memory *phwi_context; 3633 int i, eq_for_mcc, ulp_num; 3634 3635 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) 3636 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) 3637 beiscsi_cmd_iscsi_cleanup(phba, ulp_num); 3638 3639 /** 3640 * Purge all EQ entries that may have been left out. This is to 3641 * workaround a problem we've seen occasionally where driver gets an 3642 * interrupt with EQ entry bit set after stopping the controller. 3643 */ 3644 hwi_purge_eq(phba); 3645 3646 phwi_ctrlr = phba->phwi_ctrlr; 3647 phwi_context = phwi_ctrlr->phwi_ctxt; 3648 3649 be_cmd_iscsi_remove_template_hdr(ctrl); 3650 3651 for (i = 0; i < phba->params.cxns_per_ctrl; i++) { 3652 q = &phwi_context->be_wrbq[i]; 3653 if (q->created) 3654 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ); 3655 } 3656 kfree(phwi_context->be_wrbq); 3657 free_wrb_handles(phba); 3658 3659 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 3660 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 3661 3662 q = &phwi_context->be_def_hdrq[ulp_num]; 3663 if (q->created) 3664 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ); 3665 3666 q = &phwi_context->be_def_dataq[ulp_num]; 3667 if (q->created) 3668 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ); 3669 } 3670 } 3671 3672 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL); 3673 3674 for (i = 0; i < (phba->num_cpus); i++) { 3675 q = &phwi_context->be_cq[i]; 3676 if (q->created) { 3677 be_queue_free(phba, q); 3678 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ); 3679 } 3680 } 3681 3682 be_mcc_queues_destroy(phba); 3683 if (phba->pcidev->msix_enabled) 3684 eq_for_mcc = 1; 3685 else 3686 eq_for_mcc = 0; 3687 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) { 3688 q = &phwi_context->be_eq[i].q; 3689 if (q->created) { 3690 be_queue_free(phba, q); 3691 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ); 3692 } 3693 } 3694 /* this ensures complete FW cleanup */ 3695 beiscsi_cmd_function_reset(phba); 3696 /* last communication, indicate driver is unloading */ 3697 beiscsi_cmd_special_wrb(&phba->ctrl, 0); 3698 } 3699 3700 static int hwi_init_port(struct beiscsi_hba *phba) 3701 { 3702 struct hwi_controller *phwi_ctrlr; 3703 struct hwi_context_memory *phwi_context; 3704 unsigned int def_pdu_ring_sz; 3705 struct be_ctrl_info *ctrl = &phba->ctrl; 3706 int status, ulp_num; 3707 u16 nbufs; 3708 3709 phwi_ctrlr = phba->phwi_ctrlr; 3710 phwi_context = phwi_ctrlr->phwi_ctxt; 3711 /* set port optic state to unknown */ 3712 phba->optic_state = 0xff; 3713 3714 status = beiscsi_create_eqs(phba, phwi_context); 3715 if (status != 0) { 3716 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3717 "BM_%d : EQ not created\n"); 3718 goto error; 3719 } 3720 3721 status = be_mcc_queues_create(phba, phwi_context); 3722 if (status != 0) 3723 goto error; 3724 3725 status = beiscsi_check_supported_fw(ctrl, phba); 3726 if (status != 0) { 3727 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3728 "BM_%d : Unsupported fw version\n"); 3729 goto error; 3730 } 3731 3732 status = beiscsi_create_cqs(phba, phwi_context); 3733 if (status != 0) { 3734 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3735 "BM_%d : CQ not created\n"); 3736 goto error; 3737 } 3738 3739 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 3740 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 3741 nbufs = phwi_context->pasync_ctx[ulp_num]->num_entries; 3742 def_pdu_ring_sz = nbufs * sizeof(struct phys_addr); 3743 3744 status = beiscsi_create_def_hdr(phba, phwi_context, 3745 phwi_ctrlr, 3746 def_pdu_ring_sz, 3747 ulp_num); 3748 if (status != 0) { 3749 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3750 "BM_%d : Default Header not created for ULP : %d\n", 3751 ulp_num); 3752 goto error; 3753 } 3754 3755 status = beiscsi_create_def_data(phba, phwi_context, 3756 phwi_ctrlr, 3757 def_pdu_ring_sz, 3758 ulp_num); 3759 if (status != 0) { 3760 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3761 "BM_%d : Default Data not created for ULP : %d\n", 3762 ulp_num); 3763 goto error; 3764 } 3765 /** 3766 * Now that the default PDU rings have been created, 3767 * let EP know about it. 3768 */ 3769 beiscsi_hdq_post_handles(phba, BEISCSI_DEFQ_HDR, 3770 ulp_num, nbufs); 3771 beiscsi_hdq_post_handles(phba, BEISCSI_DEFQ_DATA, 3772 ulp_num, nbufs); 3773 } 3774 } 3775 3776 status = beiscsi_post_pages(phba); 3777 if (status != 0) { 3778 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3779 "BM_%d : Post SGL Pages Failed\n"); 3780 goto error; 3781 } 3782 3783 status = beiscsi_post_template_hdr(phba); 3784 if (status != 0) { 3785 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3786 "BM_%d : Template HDR Posting for CXN Failed\n"); 3787 } 3788 3789 status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr); 3790 if (status != 0) { 3791 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3792 "BM_%d : WRB Rings not created\n"); 3793 goto error; 3794 } 3795 3796 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 3797 uint16_t async_arr_idx = 0; 3798 3799 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 3800 uint16_t cri = 0; 3801 struct hd_async_context *pasync_ctx; 3802 3803 pasync_ctx = HWI_GET_ASYNC_PDU_CTX( 3804 phwi_ctrlr, ulp_num); 3805 for (cri = 0; cri < 3806 phba->params.cxns_per_ctrl; cri++) { 3807 if (ulp_num == BEISCSI_GET_ULP_FROM_CRI 3808 (phwi_ctrlr, cri)) 3809 pasync_ctx->cid_to_async_cri_map[ 3810 phwi_ctrlr->wrb_context[cri].cid] = 3811 async_arr_idx++; 3812 } 3813 } 3814 } 3815 3816 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3817 "BM_%d : hwi_init_port success\n"); 3818 return 0; 3819 3820 error: 3821 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3822 "BM_%d : hwi_init_port failed"); 3823 hwi_cleanup_port(phba); 3824 return status; 3825 } 3826 3827 static int hwi_init_controller(struct beiscsi_hba *phba) 3828 { 3829 struct hwi_controller *phwi_ctrlr; 3830 3831 phwi_ctrlr = phba->phwi_ctrlr; 3832 if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) { 3833 phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba-> 3834 init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address; 3835 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3836 "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n", 3837 phwi_ctrlr->phwi_ctxt); 3838 } else { 3839 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3840 "BM_%d : HWI_MEM_ADDN_CONTEXT is more " 3841 "than one element.Failing to load\n"); 3842 return -ENOMEM; 3843 } 3844 3845 iscsi_init_global_templates(phba); 3846 if (beiscsi_init_wrb_handle(phba)) 3847 return -ENOMEM; 3848 3849 if (hwi_init_async_pdu_ctx(phba)) { 3850 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3851 "BM_%d : hwi_init_async_pdu_ctx failed\n"); 3852 return -ENOMEM; 3853 } 3854 3855 if (hwi_init_port(phba) != 0) { 3856 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3857 "BM_%d : hwi_init_controller failed\n"); 3858 3859 return -ENOMEM; 3860 } 3861 return 0; 3862 } 3863 3864 static void beiscsi_free_mem(struct beiscsi_hba *phba) 3865 { 3866 struct be_mem_descriptor *mem_descr; 3867 int i, j; 3868 3869 mem_descr = phba->init_mem; 3870 for (i = 0; i < SE_MEM_MAX; i++) { 3871 for (j = mem_descr->num_elements; j > 0; j--) { 3872 dma_free_coherent(&phba->pcidev->dev, 3873 mem_descr->mem_array[j - 1].size, 3874 mem_descr->mem_array[j - 1].virtual_address, 3875 (unsigned long)mem_descr->mem_array[j - 1]. 3876 bus_address.u.a64.address); 3877 } 3878 3879 kfree(mem_descr->mem_array); 3880 mem_descr++; 3881 } 3882 kfree(phba->init_mem); 3883 kfree(phba->phwi_ctrlr->wrb_context); 3884 kfree(phba->phwi_ctrlr); 3885 } 3886 3887 static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba) 3888 { 3889 struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg; 3890 struct sgl_handle *psgl_handle; 3891 struct iscsi_sge *pfrag; 3892 unsigned int arr_index, i, idx; 3893 unsigned int ulp_icd_start, ulp_num = 0; 3894 3895 phba->io_sgl_hndl_avbl = 0; 3896 phba->eh_sgl_hndl_avbl = 0; 3897 3898 mem_descr_sglh = phba->init_mem; 3899 mem_descr_sglh += HWI_MEM_SGLH; 3900 if (1 == mem_descr_sglh->num_elements) { 3901 phba->io_sgl_hndl_base = kzalloc_objs(struct sgl_handle *, 3902 phba->params.ios_per_ctrl); 3903 if (!phba->io_sgl_hndl_base) { 3904 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3905 "BM_%d : Mem Alloc Failed. Failing to load\n"); 3906 return -ENOMEM; 3907 } 3908 phba->eh_sgl_hndl_base = 3909 kzalloc_objs(struct sgl_handle *, 3910 phba->params.icds_per_ctrl - phba->params.ios_per_ctrl); 3911 if (!phba->eh_sgl_hndl_base) { 3912 kfree(phba->io_sgl_hndl_base); 3913 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3914 "BM_%d : Mem Alloc Failed. Failing to load\n"); 3915 return -ENOMEM; 3916 } 3917 } else { 3918 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3919 "BM_%d : HWI_MEM_SGLH is more than one element." 3920 "Failing to load\n"); 3921 return -ENOMEM; 3922 } 3923 3924 arr_index = 0; 3925 idx = 0; 3926 while (idx < mem_descr_sglh->num_elements) { 3927 psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address; 3928 3929 for (i = 0; i < (mem_descr_sglh->mem_array[idx].size / 3930 sizeof(struct sgl_handle)); i++) { 3931 if (arr_index < phba->params.ios_per_ctrl) { 3932 phba->io_sgl_hndl_base[arr_index] = psgl_handle; 3933 phba->io_sgl_hndl_avbl++; 3934 arr_index++; 3935 } else { 3936 phba->eh_sgl_hndl_base[arr_index - 3937 phba->params.ios_per_ctrl] = 3938 psgl_handle; 3939 arr_index++; 3940 phba->eh_sgl_hndl_avbl++; 3941 } 3942 psgl_handle++; 3943 } 3944 idx++; 3945 } 3946 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3947 "BM_%d : phba->io_sgl_hndl_avbl=%d " 3948 "phba->eh_sgl_hndl_avbl=%d\n", 3949 phba->io_sgl_hndl_avbl, 3950 phba->eh_sgl_hndl_avbl); 3951 3952 mem_descr_sg = phba->init_mem; 3953 mem_descr_sg += HWI_MEM_SGE; 3954 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3955 "\n BM_%d : mem_descr_sg->num_elements=%d\n", 3956 mem_descr_sg->num_elements); 3957 3958 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) 3959 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) 3960 break; 3961 3962 ulp_icd_start = phba->fw_config.iscsi_icd_start[ulp_num]; 3963 3964 arr_index = 0; 3965 idx = 0; 3966 while (idx < mem_descr_sg->num_elements) { 3967 pfrag = mem_descr_sg->mem_array[idx].virtual_address; 3968 3969 for (i = 0; 3970 i < (mem_descr_sg->mem_array[idx].size) / 3971 (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io); 3972 i++) { 3973 if (arr_index < phba->params.ios_per_ctrl) 3974 psgl_handle = phba->io_sgl_hndl_base[arr_index]; 3975 else 3976 psgl_handle = phba->eh_sgl_hndl_base[arr_index - 3977 phba->params.ios_per_ctrl]; 3978 psgl_handle->pfrag = pfrag; 3979 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0); 3980 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0); 3981 pfrag += phba->params.num_sge_per_io; 3982 psgl_handle->sgl_index = ulp_icd_start + arr_index++; 3983 } 3984 idx++; 3985 } 3986 phba->io_sgl_free_index = 0; 3987 phba->io_sgl_alloc_index = 0; 3988 phba->eh_sgl_free_index = 0; 3989 phba->eh_sgl_alloc_index = 0; 3990 return 0; 3991 } 3992 3993 static int hba_setup_cid_tbls(struct beiscsi_hba *phba) 3994 { 3995 int ret; 3996 uint16_t i, ulp_num; 3997 struct ulp_cid_info *ptr_cid_info = NULL; 3998 3999 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 4000 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { 4001 ptr_cid_info = kzalloc_obj(struct ulp_cid_info); 4002 4003 if (!ptr_cid_info) { 4004 ret = -ENOMEM; 4005 goto free_memory; 4006 } 4007 4008 /* Allocate memory for CID array */ 4009 ptr_cid_info->cid_array = 4010 kcalloc(BEISCSI_GET_CID_COUNT(phba, ulp_num), 4011 sizeof(*ptr_cid_info->cid_array), 4012 GFP_KERNEL); 4013 if (!ptr_cid_info->cid_array) { 4014 kfree(ptr_cid_info); 4015 ptr_cid_info = NULL; 4016 ret = -ENOMEM; 4017 4018 goto free_memory; 4019 } 4020 ptr_cid_info->avlbl_cids = BEISCSI_GET_CID_COUNT( 4021 phba, ulp_num); 4022 4023 /* Save the cid_info_array ptr */ 4024 phba->cid_array_info[ulp_num] = ptr_cid_info; 4025 } 4026 } 4027 phba->ep_array = kzalloc_objs(struct iscsi_endpoint *, 4028 phba->params.cxns_per_ctrl); 4029 if (!phba->ep_array) { 4030 ret = -ENOMEM; 4031 4032 goto free_memory; 4033 } 4034 4035 phba->conn_table = kzalloc_objs(struct beiscsi_conn *, 4036 phba->params.cxns_per_ctrl); 4037 if (!phba->conn_table) { 4038 kfree(phba->ep_array); 4039 phba->ep_array = NULL; 4040 ret = -ENOMEM; 4041 4042 goto free_memory; 4043 } 4044 4045 for (i = 0; i < phba->params.cxns_per_ctrl; i++) { 4046 ulp_num = phba->phwi_ctrlr->wrb_context[i].ulp_num; 4047 4048 ptr_cid_info = phba->cid_array_info[ulp_num]; 4049 ptr_cid_info->cid_array[ptr_cid_info->cid_alloc++] = 4050 phba->phwi_ctrlr->wrb_context[i].cid; 4051 4052 } 4053 4054 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 4055 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { 4056 ptr_cid_info = phba->cid_array_info[ulp_num]; 4057 4058 ptr_cid_info->cid_alloc = 0; 4059 ptr_cid_info->cid_free = 0; 4060 } 4061 } 4062 return 0; 4063 4064 free_memory: 4065 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 4066 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { 4067 ptr_cid_info = phba->cid_array_info[ulp_num]; 4068 4069 if (ptr_cid_info) { 4070 kfree(ptr_cid_info->cid_array); 4071 kfree(ptr_cid_info); 4072 phba->cid_array_info[ulp_num] = NULL; 4073 } 4074 } 4075 } 4076 4077 return ret; 4078 } 4079 4080 static void hwi_enable_intr(struct beiscsi_hba *phba) 4081 { 4082 struct be_ctrl_info *ctrl = &phba->ctrl; 4083 struct hwi_controller *phwi_ctrlr; 4084 struct hwi_context_memory *phwi_context; 4085 struct be_queue_info *eq; 4086 u8 __iomem *addr; 4087 u32 reg, i; 4088 u32 enabled; 4089 4090 phwi_ctrlr = phba->phwi_ctrlr; 4091 phwi_context = phwi_ctrlr->phwi_ctxt; 4092 4093 addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg + 4094 PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET); 4095 reg = ioread32(addr); 4096 4097 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 4098 if (!enabled) { 4099 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 4100 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 4101 "BM_%d : reg =x%08x addr=%p\n", reg, addr); 4102 iowrite32(reg, addr); 4103 } 4104 4105 if (!phba->pcidev->msix_enabled) { 4106 eq = &phwi_context->be_eq[0].q; 4107 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 4108 "BM_%d : eq->id=%d\n", eq->id); 4109 4110 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1); 4111 } else { 4112 for (i = 0; i <= phba->num_cpus; i++) { 4113 eq = &phwi_context->be_eq[i].q; 4114 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 4115 "BM_%d : eq->id=%d\n", eq->id); 4116 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1); 4117 } 4118 } 4119 } 4120 4121 static void hwi_disable_intr(struct beiscsi_hba *phba) 4122 { 4123 struct be_ctrl_info *ctrl = &phba->ctrl; 4124 4125 u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET; 4126 u32 reg = ioread32(addr); 4127 4128 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 4129 if (enabled) { 4130 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 4131 iowrite32(reg, addr); 4132 } else 4133 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, 4134 "BM_%d : In hwi_disable_intr, Already Disabled\n"); 4135 } 4136 4137 static int beiscsi_init_port(struct beiscsi_hba *phba) 4138 { 4139 int ret; 4140 4141 ret = hwi_init_controller(phba); 4142 if (ret < 0) { 4143 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4144 "BM_%d : init controller failed\n"); 4145 return ret; 4146 } 4147 ret = beiscsi_init_sgl_handle(phba); 4148 if (ret < 0) { 4149 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4150 "BM_%d : init sgl handles failed\n"); 4151 goto cleanup_port; 4152 } 4153 4154 ret = hba_setup_cid_tbls(phba); 4155 if (ret < 0) { 4156 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4157 "BM_%d : setup CID table failed\n"); 4158 kfree(phba->io_sgl_hndl_base); 4159 kfree(phba->eh_sgl_hndl_base); 4160 goto cleanup_port; 4161 } 4162 return ret; 4163 4164 cleanup_port: 4165 hwi_cleanup_port(phba); 4166 return ret; 4167 } 4168 4169 static void beiscsi_cleanup_port(struct beiscsi_hba *phba) 4170 { 4171 struct ulp_cid_info *ptr_cid_info = NULL; 4172 int ulp_num; 4173 4174 kfree(phba->io_sgl_hndl_base); 4175 kfree(phba->eh_sgl_hndl_base); 4176 kfree(phba->ep_array); 4177 kfree(phba->conn_table); 4178 4179 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 4180 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { 4181 ptr_cid_info = phba->cid_array_info[ulp_num]; 4182 4183 if (ptr_cid_info) { 4184 kfree(ptr_cid_info->cid_array); 4185 kfree(ptr_cid_info); 4186 phba->cid_array_info[ulp_num] = NULL; 4187 } 4188 } 4189 } 4190 } 4191 4192 /** 4193 * beiscsi_free_mgmt_task_handles()- Free driver CXN resources 4194 * @beiscsi_conn: ptr to the conn to be cleaned up 4195 * @task: ptr to iscsi_task resource to be freed. 4196 * 4197 * Free driver mgmt resources binded to CXN. 4198 **/ 4199 void 4200 beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn, 4201 struct iscsi_task *task) 4202 { 4203 struct beiscsi_io_task *io_task; 4204 struct beiscsi_hba *phba = beiscsi_conn->phba; 4205 struct hwi_wrb_context *pwrb_context; 4206 struct hwi_controller *phwi_ctrlr; 4207 uint16_t cri_index = BE_GET_CRI_FROM_CID( 4208 beiscsi_conn->beiscsi_conn_cid); 4209 4210 phwi_ctrlr = phba->phwi_ctrlr; 4211 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 4212 4213 io_task = task->dd_data; 4214 4215 if (io_task->pwrb_handle) { 4216 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle); 4217 io_task->pwrb_handle = NULL; 4218 } 4219 4220 if (io_task->psgl_handle) { 4221 free_mgmt_sgl_handle(phba, io_task->psgl_handle); 4222 io_task->psgl_handle = NULL; 4223 } 4224 4225 if (io_task->mtask_addr) { 4226 dma_unmap_single(&phba->pcidev->dev, 4227 io_task->mtask_addr, 4228 io_task->mtask_data_count, 4229 DMA_TO_DEVICE); 4230 io_task->mtask_addr = 0; 4231 } 4232 } 4233 4234 /** 4235 * beiscsi_cleanup_task()- Free driver resources of the task 4236 * @task: ptr to the iscsi task 4237 * 4238 **/ 4239 static void beiscsi_cleanup_task(struct iscsi_task *task) 4240 { 4241 struct beiscsi_io_task *io_task = task->dd_data; 4242 struct iscsi_conn *conn = task->conn; 4243 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 4244 struct beiscsi_hba *phba = beiscsi_conn->phba; 4245 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess; 4246 struct hwi_wrb_context *pwrb_context; 4247 struct hwi_controller *phwi_ctrlr; 4248 uint16_t cri_index = BE_GET_CRI_FROM_CID( 4249 beiscsi_conn->beiscsi_conn_cid); 4250 4251 phwi_ctrlr = phba->phwi_ctrlr; 4252 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 4253 4254 if (io_task->cmd_bhs) { 4255 dma_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs, 4256 io_task->bhs_pa.u.a64.address); 4257 io_task->cmd_bhs = NULL; 4258 task->hdr = NULL; 4259 } 4260 4261 if (task->sc) { 4262 if (io_task->pwrb_handle) { 4263 free_wrb_handle(phba, pwrb_context, 4264 io_task->pwrb_handle); 4265 io_task->pwrb_handle = NULL; 4266 } 4267 4268 if (io_task->psgl_handle) { 4269 free_io_sgl_handle(phba, io_task->psgl_handle); 4270 io_task->psgl_handle = NULL; 4271 } 4272 4273 if (io_task->scsi_cmnd) { 4274 if (io_task->num_sg) 4275 scsi_dma_unmap(io_task->scsi_cmnd); 4276 io_task->scsi_cmnd = NULL; 4277 } 4278 } else { 4279 if (!beiscsi_conn->login_in_progress) 4280 beiscsi_free_mgmt_task_handles(beiscsi_conn, task); 4281 } 4282 } 4283 4284 void 4285 beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn, 4286 struct beiscsi_offload_params *params) 4287 { 4288 struct wrb_handle *pwrb_handle; 4289 struct hwi_wrb_context *pwrb_context = NULL; 4290 struct beiscsi_hba *phba = beiscsi_conn->phba; 4291 struct iscsi_task *task = beiscsi_conn->task; 4292 struct iscsi_session *session = task->conn->session; 4293 u32 doorbell = 0; 4294 4295 /* 4296 * We can always use 0 here because it is reserved by libiscsi for 4297 * login/startup related tasks. 4298 */ 4299 beiscsi_conn->login_in_progress = 0; 4300 spin_lock_bh(&session->back_lock); 4301 beiscsi_cleanup_task(task); 4302 spin_unlock_bh(&session->back_lock); 4303 4304 pwrb_handle = alloc_wrb_handle(phba, beiscsi_conn->beiscsi_conn_cid, 4305 &pwrb_context); 4306 4307 /* Check for the adapter family */ 4308 if (is_chip_be2_be3r(phba)) 4309 beiscsi_offload_cxn_v0(params, pwrb_handle, 4310 phba->init_mem, 4311 pwrb_context); 4312 else 4313 beiscsi_offload_cxn_v2(params, pwrb_handle, 4314 pwrb_context); 4315 4316 be_dws_le_to_cpu(pwrb_handle->pwrb, 4317 sizeof(struct iscsi_target_context_update_wrb)); 4318 4319 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; 4320 doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK) 4321 << DB_DEF_PDU_WRB_INDEX_SHIFT; 4322 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; 4323 iowrite32(doorbell, phba->db_va + 4324 beiscsi_conn->doorbell_offset); 4325 4326 /* 4327 * There is no completion for CONTEXT_UPDATE. The completion of next 4328 * WRB posted guarantees FW's processing and DMA'ing of it. 4329 * Use beiscsi_put_wrb_handle to put it back in the pool which makes 4330 * sure zero'ing or reuse of the WRB only after wrbs_per_cxn. 4331 */ 4332 beiscsi_put_wrb_handle(pwrb_context, pwrb_handle, 4333 phba->params.wrbs_per_cxn); 4334 beiscsi_log(phba, KERN_INFO, 4335 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 4336 "BM_%d : put CONTEXT_UPDATE pwrb_handle=%p free_index=0x%x wrb_handles_available=%d\n", 4337 pwrb_handle, pwrb_context->free_index, 4338 pwrb_context->wrb_handles_available); 4339 } 4340 4341 static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt, 4342 int *index, int *age) 4343 { 4344 *index = (int)itt; 4345 if (age) 4346 *age = conn->session->age; 4347 } 4348 4349 /** 4350 * beiscsi_alloc_pdu - allocates pdu and related resources 4351 * @task: libiscsi task 4352 * @opcode: opcode of pdu for task 4353 * 4354 * This is called with the session lock held. It will allocate 4355 * the wrb and sgl if needed for the command. And it will prep 4356 * the pdu's itt. beiscsi_parse_pdu will later translate 4357 * the pdu itt to the libiscsi task itt. 4358 */ 4359 static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode) 4360 { 4361 struct beiscsi_io_task *io_task = task->dd_data; 4362 struct iscsi_conn *conn = task->conn; 4363 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 4364 struct beiscsi_hba *phba = beiscsi_conn->phba; 4365 struct hwi_wrb_context *pwrb_context; 4366 struct hwi_controller *phwi_ctrlr; 4367 itt_t itt; 4368 uint16_t cri_index = 0; 4369 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess; 4370 dma_addr_t paddr; 4371 4372 io_task->cmd_bhs = dma_pool_alloc(beiscsi_sess->bhs_pool, 4373 GFP_ATOMIC, &paddr); 4374 if (!io_task->cmd_bhs) 4375 return -ENOMEM; 4376 io_task->bhs_pa.u.a64.address = paddr; 4377 io_task->libiscsi_itt = (itt_t)task->itt; 4378 io_task->conn = beiscsi_conn; 4379 4380 task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr; 4381 task->hdr_max = sizeof(struct be_cmd_bhs); 4382 io_task->psgl_handle = NULL; 4383 io_task->pwrb_handle = NULL; 4384 4385 if (task->sc) { 4386 io_task->psgl_handle = alloc_io_sgl_handle(phba); 4387 if (!io_task->psgl_handle) { 4388 beiscsi_log(phba, KERN_ERR, 4389 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 4390 "BM_%d : Alloc of IO_SGL_ICD Failed " 4391 "for the CID : %d\n", 4392 beiscsi_conn->beiscsi_conn_cid); 4393 goto free_hndls; 4394 } 4395 io_task->pwrb_handle = alloc_wrb_handle(phba, 4396 beiscsi_conn->beiscsi_conn_cid, 4397 &io_task->pwrb_context); 4398 if (!io_task->pwrb_handle) { 4399 beiscsi_log(phba, KERN_ERR, 4400 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 4401 "BM_%d : Alloc of WRB_HANDLE Failed " 4402 "for the CID : %d\n", 4403 beiscsi_conn->beiscsi_conn_cid); 4404 goto free_io_hndls; 4405 } 4406 } else { 4407 io_task->scsi_cmnd = NULL; 4408 if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) { 4409 beiscsi_conn->task = task; 4410 if (!beiscsi_conn->login_in_progress) { 4411 io_task->psgl_handle = (struct sgl_handle *) 4412 alloc_mgmt_sgl_handle(phba); 4413 if (!io_task->psgl_handle) { 4414 beiscsi_log(phba, KERN_ERR, 4415 BEISCSI_LOG_IO | 4416 BEISCSI_LOG_CONFIG, 4417 "BM_%d : Alloc of MGMT_SGL_ICD Failed " 4418 "for the CID : %d\n", 4419 beiscsi_conn->beiscsi_conn_cid); 4420 goto free_hndls; 4421 } 4422 4423 beiscsi_conn->login_in_progress = 1; 4424 beiscsi_conn->plogin_sgl_handle = 4425 io_task->psgl_handle; 4426 io_task->pwrb_handle = 4427 alloc_wrb_handle(phba, 4428 beiscsi_conn->beiscsi_conn_cid, 4429 &io_task->pwrb_context); 4430 if (!io_task->pwrb_handle) { 4431 beiscsi_log(phba, KERN_ERR, 4432 BEISCSI_LOG_IO | 4433 BEISCSI_LOG_CONFIG, 4434 "BM_%d : Alloc of WRB_HANDLE Failed " 4435 "for the CID : %d\n", 4436 beiscsi_conn->beiscsi_conn_cid); 4437 goto free_mgmt_hndls; 4438 } 4439 beiscsi_conn->plogin_wrb_handle = 4440 io_task->pwrb_handle; 4441 4442 } else { 4443 io_task->psgl_handle = 4444 beiscsi_conn->plogin_sgl_handle; 4445 io_task->pwrb_handle = 4446 beiscsi_conn->plogin_wrb_handle; 4447 } 4448 } else { 4449 io_task->psgl_handle = alloc_mgmt_sgl_handle(phba); 4450 if (!io_task->psgl_handle) { 4451 beiscsi_log(phba, KERN_ERR, 4452 BEISCSI_LOG_IO | 4453 BEISCSI_LOG_CONFIG, 4454 "BM_%d : Alloc of MGMT_SGL_ICD Failed " 4455 "for the CID : %d\n", 4456 beiscsi_conn->beiscsi_conn_cid); 4457 goto free_hndls; 4458 } 4459 io_task->pwrb_handle = 4460 alloc_wrb_handle(phba, 4461 beiscsi_conn->beiscsi_conn_cid, 4462 &io_task->pwrb_context); 4463 if (!io_task->pwrb_handle) { 4464 beiscsi_log(phba, KERN_ERR, 4465 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 4466 "BM_%d : Alloc of WRB_HANDLE Failed " 4467 "for the CID : %d\n", 4468 beiscsi_conn->beiscsi_conn_cid); 4469 goto free_mgmt_hndls; 4470 } 4471 4472 } 4473 } 4474 itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle-> 4475 wrb_index << 16) | (unsigned int) 4476 (io_task->psgl_handle->sgl_index)); 4477 io_task->pwrb_handle->pio_handle = task; 4478 4479 io_task->cmd_bhs->iscsi_hdr.itt = itt; 4480 return 0; 4481 4482 free_io_hndls: 4483 free_io_sgl_handle(phba, io_task->psgl_handle); 4484 goto free_hndls; 4485 free_mgmt_hndls: 4486 free_mgmt_sgl_handle(phba, io_task->psgl_handle); 4487 io_task->psgl_handle = NULL; 4488 free_hndls: 4489 phwi_ctrlr = phba->phwi_ctrlr; 4490 cri_index = BE_GET_CRI_FROM_CID( 4491 beiscsi_conn->beiscsi_conn_cid); 4492 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 4493 if (io_task->pwrb_handle) 4494 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle); 4495 io_task->pwrb_handle = NULL; 4496 dma_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs, 4497 io_task->bhs_pa.u.a64.address); 4498 io_task->cmd_bhs = NULL; 4499 return -ENOMEM; 4500 } 4501 static int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg, 4502 unsigned int num_sg, unsigned int xferlen, 4503 unsigned int writedir) 4504 { 4505 4506 struct beiscsi_io_task *io_task = task->dd_data; 4507 struct iscsi_conn *conn = task->conn; 4508 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 4509 struct beiscsi_hba *phba = beiscsi_conn->phba; 4510 struct iscsi_wrb *pwrb = NULL; 4511 unsigned int doorbell = 0; 4512 4513 pwrb = io_task->pwrb_handle->pwrb; 4514 4515 io_task->bhs_len = sizeof(struct be_cmd_bhs); 4516 4517 if (writedir) { 4518 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb, 4519 INI_WR_CMD); 4520 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1); 4521 } else { 4522 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb, 4523 INI_RD_CMD); 4524 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0); 4525 } 4526 4527 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2, 4528 type, pwrb); 4529 4530 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb, 4531 cpu_to_be16(*(unsigned short *) 4532 &io_task->cmd_bhs->iscsi_hdr.lun)); 4533 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen); 4534 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb, 4535 io_task->pwrb_handle->wrb_index); 4536 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb, 4537 be32_to_cpu(task->cmdsn)); 4538 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb, 4539 io_task->psgl_handle->sgl_index); 4540 4541 hwi_write_sgl_v2(pwrb, sg, num_sg, io_task); 4542 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb, 4543 io_task->pwrb_handle->wrb_index); 4544 if (io_task->pwrb_context->plast_wrb) 4545 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, 4546 io_task->pwrb_context->plast_wrb, 4547 io_task->pwrb_handle->wrb_index); 4548 io_task->pwrb_context->plast_wrb = pwrb; 4549 4550 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb)); 4551 4552 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; 4553 doorbell |= (io_task->pwrb_handle->wrb_index & 4554 DB_DEF_PDU_WRB_INDEX_MASK) << 4555 DB_DEF_PDU_WRB_INDEX_SHIFT; 4556 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; 4557 iowrite32(doorbell, phba->db_va + 4558 beiscsi_conn->doorbell_offset); 4559 return 0; 4560 } 4561 4562 static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg, 4563 unsigned int num_sg, unsigned int xferlen, 4564 unsigned int writedir) 4565 { 4566 4567 struct beiscsi_io_task *io_task = task->dd_data; 4568 struct iscsi_conn *conn = task->conn; 4569 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 4570 struct beiscsi_hba *phba = beiscsi_conn->phba; 4571 struct iscsi_wrb *pwrb = NULL; 4572 unsigned int doorbell = 0; 4573 4574 pwrb = io_task->pwrb_handle->pwrb; 4575 io_task->bhs_len = sizeof(struct be_cmd_bhs); 4576 4577 if (writedir) { 4578 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, 4579 INI_WR_CMD); 4580 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1); 4581 } else { 4582 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, 4583 INI_RD_CMD); 4584 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0); 4585 } 4586 4587 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb, 4588 type, pwrb); 4589 4590 AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb, 4591 cpu_to_be16(*(unsigned short *) 4592 &io_task->cmd_bhs->iscsi_hdr.lun)); 4593 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen); 4594 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb, 4595 io_task->pwrb_handle->wrb_index); 4596 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 4597 be32_to_cpu(task->cmdsn)); 4598 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb, 4599 io_task->psgl_handle->sgl_index); 4600 4601 hwi_write_sgl(pwrb, sg, num_sg, io_task); 4602 4603 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb, 4604 io_task->pwrb_handle->wrb_index); 4605 if (io_task->pwrb_context->plast_wrb) 4606 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, 4607 io_task->pwrb_context->plast_wrb, 4608 io_task->pwrb_handle->wrb_index); 4609 io_task->pwrb_context->plast_wrb = pwrb; 4610 4611 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb)); 4612 4613 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; 4614 doorbell |= (io_task->pwrb_handle->wrb_index & 4615 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT; 4616 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; 4617 4618 iowrite32(doorbell, phba->db_va + 4619 beiscsi_conn->doorbell_offset); 4620 return 0; 4621 } 4622 4623 static int beiscsi_mtask(struct iscsi_task *task) 4624 { 4625 struct beiscsi_io_task *io_task = task->dd_data; 4626 struct iscsi_conn *conn = task->conn; 4627 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 4628 struct beiscsi_hba *phba = beiscsi_conn->phba; 4629 struct iscsi_wrb *pwrb = NULL; 4630 unsigned int doorbell = 0; 4631 unsigned int cid; 4632 unsigned int pwrb_typeoffset = 0; 4633 int ret = 0; 4634 4635 cid = beiscsi_conn->beiscsi_conn_cid; 4636 pwrb = io_task->pwrb_handle->pwrb; 4637 4638 if (is_chip_be2_be3r(phba)) { 4639 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 4640 be32_to_cpu(task->cmdsn)); 4641 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb, 4642 io_task->pwrb_handle->wrb_index); 4643 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb, 4644 io_task->psgl_handle->sgl_index); 4645 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, 4646 task->data_count); 4647 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb, 4648 io_task->pwrb_handle->wrb_index); 4649 if (io_task->pwrb_context->plast_wrb) 4650 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, 4651 io_task->pwrb_context->plast_wrb, 4652 io_task->pwrb_handle->wrb_index); 4653 io_task->pwrb_context->plast_wrb = pwrb; 4654 4655 pwrb_typeoffset = BE_WRB_TYPE_OFFSET; 4656 } else { 4657 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb, 4658 be32_to_cpu(task->cmdsn)); 4659 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb, 4660 io_task->pwrb_handle->wrb_index); 4661 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb, 4662 io_task->psgl_handle->sgl_index); 4663 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, 4664 task->data_count); 4665 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb, 4666 io_task->pwrb_handle->wrb_index); 4667 if (io_task->pwrb_context->plast_wrb) 4668 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, 4669 io_task->pwrb_context->plast_wrb, 4670 io_task->pwrb_handle->wrb_index); 4671 io_task->pwrb_context->plast_wrb = pwrb; 4672 4673 pwrb_typeoffset = SKH_WRB_TYPE_OFFSET; 4674 } 4675 4676 4677 switch (task->hdr->opcode & ISCSI_OPCODE_MASK) { 4678 case ISCSI_OP_LOGIN: 4679 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1); 4680 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset); 4681 ret = hwi_write_buffer(pwrb, task); 4682 break; 4683 case ISCSI_OP_NOOP_OUT: 4684 if (task->hdr->ttt != ISCSI_RESERVED_TAG) { 4685 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset); 4686 if (is_chip_be2_be3r(phba)) 4687 AMAP_SET_BITS(struct amap_iscsi_wrb, 4688 dmsg, pwrb, 1); 4689 else 4690 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 4691 dmsg, pwrb, 1); 4692 } else { 4693 ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset); 4694 if (is_chip_be2_be3r(phba)) 4695 AMAP_SET_BITS(struct amap_iscsi_wrb, 4696 dmsg, pwrb, 0); 4697 else 4698 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 4699 dmsg, pwrb, 0); 4700 } 4701 ret = hwi_write_buffer(pwrb, task); 4702 break; 4703 case ISCSI_OP_TEXT: 4704 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset); 4705 ret = hwi_write_buffer(pwrb, task); 4706 break; 4707 case ISCSI_OP_SCSI_TMFUNC: 4708 ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset); 4709 ret = hwi_write_buffer(pwrb, task); 4710 break; 4711 case ISCSI_OP_LOGOUT: 4712 ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset); 4713 ret = hwi_write_buffer(pwrb, task); 4714 break; 4715 4716 default: 4717 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, 4718 "BM_%d : opcode =%d Not supported\n", 4719 task->hdr->opcode & ISCSI_OPCODE_MASK); 4720 4721 return -EINVAL; 4722 } 4723 4724 if (ret) 4725 return ret; 4726 4727 /* Set the task type */ 4728 io_task->wrb_type = (is_chip_be2_be3r(phba)) ? 4729 AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb) : 4730 AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb); 4731 4732 doorbell |= cid & DB_WRB_POST_CID_MASK; 4733 doorbell |= (io_task->pwrb_handle->wrb_index & 4734 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT; 4735 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; 4736 iowrite32(doorbell, phba->db_va + 4737 beiscsi_conn->doorbell_offset); 4738 return 0; 4739 } 4740 4741 static int beiscsi_task_xmit(struct iscsi_task *task) 4742 { 4743 struct beiscsi_io_task *io_task = task->dd_data; 4744 struct scsi_cmnd *sc = task->sc; 4745 struct beiscsi_hba *phba; 4746 struct scatterlist *sg; 4747 int num_sg; 4748 unsigned int writedir = 0, xferlen = 0; 4749 4750 phba = io_task->conn->phba; 4751 /** 4752 * HBA in error includes BEISCSI_HBA_FW_TIMEOUT. IO path might be 4753 * operational if FW still gets heartbeat from EP FW. Is management 4754 * path really needed to continue further? 4755 */ 4756 if (!beiscsi_hba_is_online(phba)) 4757 return -EIO; 4758 4759 if (!io_task->conn->login_in_progress) 4760 task->hdr->exp_statsn = 0; 4761 4762 if (!sc) 4763 return beiscsi_mtask(task); 4764 4765 io_task->scsi_cmnd = sc; 4766 io_task->num_sg = 0; 4767 num_sg = scsi_dma_map(sc); 4768 if (num_sg < 0) { 4769 beiscsi_log(phba, KERN_ERR, 4770 BEISCSI_LOG_IO | BEISCSI_LOG_ISCSI, 4771 "BM_%d : scsi_dma_map Failed " 4772 "Driver_ITT : 0x%x ITT : 0x%x Xferlen : 0x%x\n", 4773 be32_to_cpu(io_task->cmd_bhs->iscsi_hdr.itt), 4774 io_task->libiscsi_itt, scsi_bufflen(sc)); 4775 4776 return num_sg; 4777 } 4778 /** 4779 * For scsi cmd task, check num_sg before unmapping in cleanup_task. 4780 * For management task, cleanup_task checks mtask_addr before unmapping. 4781 */ 4782 io_task->num_sg = num_sg; 4783 xferlen = scsi_bufflen(sc); 4784 sg = scsi_sglist(sc); 4785 if (sc->sc_data_direction == DMA_TO_DEVICE) 4786 writedir = 1; 4787 else 4788 writedir = 0; 4789 4790 return phba->iotask_fn(task, sg, num_sg, xferlen, writedir); 4791 } 4792 4793 /** 4794 * beiscsi_bsg_request - handle bsg request from ISCSI transport 4795 * @job: job to handle 4796 */ 4797 static int beiscsi_bsg_request(struct bsg_job *job) 4798 { 4799 struct Scsi_Host *shost; 4800 struct beiscsi_hba *phba; 4801 struct iscsi_bsg_request *bsg_req = job->request; 4802 int rc = -EINVAL; 4803 unsigned int tag; 4804 struct be_dma_mem nonemb_cmd; 4805 struct be_cmd_resp_hdr *resp; 4806 struct iscsi_bsg_reply *bsg_reply = job->reply; 4807 unsigned short status, extd_status; 4808 4809 shost = iscsi_job_to_shost(job); 4810 phba = iscsi_host_priv(shost); 4811 4812 if (!beiscsi_hba_is_online(phba)) { 4813 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG, 4814 "BM_%d : HBA in error 0x%lx\n", phba->state); 4815 return -ENXIO; 4816 } 4817 4818 switch (bsg_req->msgcode) { 4819 case ISCSI_BSG_HST_VENDOR: 4820 nonemb_cmd.va = dma_alloc_coherent(&phba->ctrl.pdev->dev, 4821 job->request_payload.payload_len, 4822 &nonemb_cmd.dma, GFP_KERNEL); 4823 if (nonemb_cmd.va == NULL) { 4824 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, 4825 "BM_%d : Failed to allocate memory for " 4826 "beiscsi_bsg_request\n"); 4827 return -ENOMEM; 4828 } 4829 tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job, 4830 &nonemb_cmd); 4831 if (!tag) { 4832 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, 4833 "BM_%d : MBX Tag Allocation Failed\n"); 4834 4835 dma_free_coherent(&phba->ctrl.pdev->dev, nonemb_cmd.size, 4836 nonemb_cmd.va, nonemb_cmd.dma); 4837 return -EAGAIN; 4838 } 4839 4840 rc = wait_event_interruptible_timeout( 4841 phba->ctrl.mcc_wait[tag], 4842 phba->ctrl.mcc_tag_status[tag], 4843 msecs_to_jiffies( 4844 BEISCSI_HOST_MBX_TIMEOUT)); 4845 4846 if (!test_bit(BEISCSI_HBA_ONLINE, &phba->state)) { 4847 clear_bit(MCC_TAG_STATE_RUNNING, 4848 &phba->ctrl.ptag_state[tag].tag_state); 4849 dma_free_coherent(&phba->ctrl.pdev->dev, nonemb_cmd.size, 4850 nonemb_cmd.va, nonemb_cmd.dma); 4851 return -EIO; 4852 } 4853 extd_status = (phba->ctrl.mcc_tag_status[tag] & 4854 CQE_STATUS_ADDL_MASK) >> CQE_STATUS_ADDL_SHIFT; 4855 status = phba->ctrl.mcc_tag_status[tag] & CQE_STATUS_MASK; 4856 free_mcc_wrb(&phba->ctrl, tag); 4857 resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va; 4858 sg_copy_from_buffer(job->reply_payload.sg_list, 4859 job->reply_payload.sg_cnt, 4860 nonemb_cmd.va, (resp->response_length 4861 + sizeof(*resp))); 4862 bsg_reply->reply_payload_rcv_len = resp->response_length; 4863 bsg_reply->result = status; 4864 bsg_job_done(job, bsg_reply->result, 4865 bsg_reply->reply_payload_rcv_len); 4866 dma_free_coherent(&phba->ctrl.pdev->dev, nonemb_cmd.size, 4867 nonemb_cmd.va, nonemb_cmd.dma); 4868 if (status || extd_status) { 4869 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, 4870 "BM_%d : MBX Cmd Failed" 4871 " status = %d extd_status = %d\n", 4872 status, extd_status); 4873 4874 return -EIO; 4875 } else { 4876 rc = 0; 4877 } 4878 break; 4879 4880 default: 4881 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, 4882 "BM_%d : Unsupported bsg command: 0x%x\n", 4883 bsg_req->msgcode); 4884 break; 4885 } 4886 4887 return rc; 4888 } 4889 4890 static void beiscsi_hba_attrs_init(struct beiscsi_hba *phba) 4891 { 4892 /* Set the logging parameter */ 4893 beiscsi_log_enable_init(phba, beiscsi_log_enable); 4894 } 4895 4896 void beiscsi_start_boot_work(struct beiscsi_hba *phba, unsigned int s_handle) 4897 { 4898 if (phba->boot_struct.boot_kset) 4899 return; 4900 4901 /* skip if boot work is already in progress */ 4902 if (test_and_set_bit(BEISCSI_HBA_BOOT_WORK, &phba->state)) 4903 return; 4904 4905 phba->boot_struct.retry = 3; 4906 phba->boot_struct.tag = 0; 4907 phba->boot_struct.s_handle = s_handle; 4908 phba->boot_struct.action = BEISCSI_BOOT_GET_SHANDLE; 4909 schedule_work(&phba->boot_work); 4910 } 4911 4912 #define BEISCSI_SYSFS_ISCSI_BOOT_FLAGS 3 4913 /* 4914 * beiscsi_show_boot_tgt_info() 4915 * Boot flag info for iscsi-utilities 4916 * Bit 0 Block valid flag 4917 * Bit 1 Firmware booting selected 4918 */ 4919 static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf) 4920 { 4921 struct beiscsi_hba *phba = data; 4922 struct mgmt_session_info *boot_sess = &phba->boot_struct.boot_sess; 4923 struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0]; 4924 char *str = buf; 4925 int rc = -EPERM; 4926 4927 switch (type) { 4928 case ISCSI_BOOT_TGT_NAME: 4929 rc = sprintf(buf, "%.*s\n", 4930 (int)strlen(boot_sess->target_name), 4931 (char *)&boot_sess->target_name); 4932 break; 4933 case ISCSI_BOOT_TGT_IP_ADDR: 4934 if (boot_conn->dest_ipaddr.ip_type == BEISCSI_IP_TYPE_V4) 4935 rc = sprintf(buf, "%pI4\n", 4936 (char *)&boot_conn->dest_ipaddr.addr); 4937 else 4938 rc = sprintf(str, "%pI6\n", 4939 (char *)&boot_conn->dest_ipaddr.addr); 4940 break; 4941 case ISCSI_BOOT_TGT_PORT: 4942 rc = sprintf(str, "%d\n", boot_conn->dest_port); 4943 break; 4944 4945 case ISCSI_BOOT_TGT_CHAP_NAME: 4946 rc = sprintf(str, "%.*s\n", 4947 boot_conn->negotiated_login_options.auth_data.chap. 4948 target_chap_name_length, 4949 (char *)&boot_conn->negotiated_login_options. 4950 auth_data.chap.target_chap_name); 4951 break; 4952 case ISCSI_BOOT_TGT_CHAP_SECRET: 4953 rc = sprintf(str, "%.*s\n", 4954 boot_conn->negotiated_login_options.auth_data.chap. 4955 target_secret_length, 4956 (char *)&boot_conn->negotiated_login_options. 4957 auth_data.chap.target_secret); 4958 break; 4959 case ISCSI_BOOT_TGT_REV_CHAP_NAME: 4960 rc = sprintf(str, "%.*s\n", 4961 boot_conn->negotiated_login_options.auth_data.chap. 4962 intr_chap_name_length, 4963 (char *)&boot_conn->negotiated_login_options. 4964 auth_data.chap.intr_chap_name); 4965 break; 4966 case ISCSI_BOOT_TGT_REV_CHAP_SECRET: 4967 rc = sprintf(str, "%.*s\n", 4968 boot_conn->negotiated_login_options.auth_data.chap. 4969 intr_secret_length, 4970 (char *)&boot_conn->negotiated_login_options. 4971 auth_data.chap.intr_secret); 4972 break; 4973 case ISCSI_BOOT_TGT_FLAGS: 4974 rc = sprintf(str, "%d\n", BEISCSI_SYSFS_ISCSI_BOOT_FLAGS); 4975 break; 4976 case ISCSI_BOOT_TGT_NIC_ASSOC: 4977 rc = sprintf(str, "0\n"); 4978 break; 4979 } 4980 return rc; 4981 } 4982 4983 static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf) 4984 { 4985 struct beiscsi_hba *phba = data; 4986 char *str = buf; 4987 int rc = -EPERM; 4988 4989 switch (type) { 4990 case ISCSI_BOOT_INI_INITIATOR_NAME: 4991 rc = sprintf(str, "%s\n", 4992 phba->boot_struct.boot_sess.initiator_iscsiname); 4993 break; 4994 } 4995 return rc; 4996 } 4997 4998 static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf) 4999 { 5000 struct beiscsi_hba *phba = data; 5001 char *str = buf; 5002 int rc = -EPERM; 5003 5004 switch (type) { 5005 case ISCSI_BOOT_ETH_FLAGS: 5006 rc = sprintf(str, "%d\n", BEISCSI_SYSFS_ISCSI_BOOT_FLAGS); 5007 break; 5008 case ISCSI_BOOT_ETH_INDEX: 5009 rc = sprintf(str, "0\n"); 5010 break; 5011 case ISCSI_BOOT_ETH_MAC: 5012 rc = beiscsi_get_macaddr(str, phba); 5013 break; 5014 } 5015 return rc; 5016 } 5017 5018 static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type) 5019 { 5020 umode_t rc = 0; 5021 5022 switch (type) { 5023 case ISCSI_BOOT_TGT_NAME: 5024 case ISCSI_BOOT_TGT_IP_ADDR: 5025 case ISCSI_BOOT_TGT_PORT: 5026 case ISCSI_BOOT_TGT_CHAP_NAME: 5027 case ISCSI_BOOT_TGT_CHAP_SECRET: 5028 case ISCSI_BOOT_TGT_REV_CHAP_NAME: 5029 case ISCSI_BOOT_TGT_REV_CHAP_SECRET: 5030 case ISCSI_BOOT_TGT_NIC_ASSOC: 5031 case ISCSI_BOOT_TGT_FLAGS: 5032 rc = S_IRUGO; 5033 break; 5034 } 5035 return rc; 5036 } 5037 5038 static umode_t beiscsi_ini_get_attr_visibility(void *data, int type) 5039 { 5040 umode_t rc = 0; 5041 5042 switch (type) { 5043 case ISCSI_BOOT_INI_INITIATOR_NAME: 5044 rc = S_IRUGO; 5045 break; 5046 } 5047 return rc; 5048 } 5049 5050 static umode_t beiscsi_eth_get_attr_visibility(void *data, int type) 5051 { 5052 umode_t rc = 0; 5053 5054 switch (type) { 5055 case ISCSI_BOOT_ETH_FLAGS: 5056 case ISCSI_BOOT_ETH_MAC: 5057 case ISCSI_BOOT_ETH_INDEX: 5058 rc = S_IRUGO; 5059 break; 5060 } 5061 return rc; 5062 } 5063 5064 static void beiscsi_boot_kobj_release(void *data) 5065 { 5066 struct beiscsi_hba *phba = data; 5067 5068 scsi_host_put(phba->shost); 5069 } 5070 5071 static int beiscsi_boot_create_kset(struct beiscsi_hba *phba) 5072 { 5073 struct boot_struct *bs = &phba->boot_struct; 5074 struct iscsi_boot_kobj *boot_kobj; 5075 5076 if (bs->boot_kset) { 5077 __beiscsi_log(phba, KERN_ERR, 5078 "BM_%d: boot_kset already created\n"); 5079 return 0; 5080 } 5081 5082 bs->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no); 5083 if (!bs->boot_kset) { 5084 __beiscsi_log(phba, KERN_ERR, 5085 "BM_%d: boot_kset alloc failed\n"); 5086 return -ENOMEM; 5087 } 5088 5089 /* get shost ref because the show function will refer phba */ 5090 if (!scsi_host_get(phba->shost)) 5091 goto free_kset; 5092 5093 boot_kobj = iscsi_boot_create_target(bs->boot_kset, 0, phba, 5094 beiscsi_show_boot_tgt_info, 5095 beiscsi_tgt_get_attr_visibility, 5096 beiscsi_boot_kobj_release); 5097 if (!boot_kobj) 5098 goto put_shost; 5099 5100 if (!scsi_host_get(phba->shost)) 5101 goto free_kset; 5102 5103 boot_kobj = iscsi_boot_create_initiator(bs->boot_kset, 0, phba, 5104 beiscsi_show_boot_ini_info, 5105 beiscsi_ini_get_attr_visibility, 5106 beiscsi_boot_kobj_release); 5107 if (!boot_kobj) 5108 goto put_shost; 5109 5110 if (!scsi_host_get(phba->shost)) 5111 goto free_kset; 5112 5113 boot_kobj = iscsi_boot_create_ethernet(bs->boot_kset, 0, phba, 5114 beiscsi_show_boot_eth_info, 5115 beiscsi_eth_get_attr_visibility, 5116 beiscsi_boot_kobj_release); 5117 if (!boot_kobj) 5118 goto put_shost; 5119 5120 return 0; 5121 5122 put_shost: 5123 scsi_host_put(phba->shost); 5124 free_kset: 5125 iscsi_boot_destroy_kset(bs->boot_kset); 5126 bs->boot_kset = NULL; 5127 return -ENOMEM; 5128 } 5129 5130 static void beiscsi_boot_work(struct work_struct *work) 5131 { 5132 struct beiscsi_hba *phba = 5133 container_of(work, struct beiscsi_hba, boot_work); 5134 struct boot_struct *bs = &phba->boot_struct; 5135 unsigned int tag = 0; 5136 5137 if (!beiscsi_hba_is_online(phba)) 5138 return; 5139 5140 beiscsi_log(phba, KERN_INFO, 5141 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, 5142 "BM_%d : %s action %d\n", 5143 __func__, phba->boot_struct.action); 5144 5145 switch (phba->boot_struct.action) { 5146 case BEISCSI_BOOT_REOPEN_SESS: 5147 tag = beiscsi_boot_reopen_sess(phba); 5148 break; 5149 case BEISCSI_BOOT_GET_SHANDLE: 5150 tag = __beiscsi_boot_get_shandle(phba, 1); 5151 break; 5152 case BEISCSI_BOOT_GET_SINFO: 5153 tag = beiscsi_boot_get_sinfo(phba); 5154 break; 5155 case BEISCSI_BOOT_LOGOUT_SESS: 5156 tag = beiscsi_boot_logout_sess(phba); 5157 break; 5158 case BEISCSI_BOOT_CREATE_KSET: 5159 beiscsi_boot_create_kset(phba); 5160 /** 5161 * updated boot_kset is made visible to all before 5162 * ending the boot work. 5163 */ 5164 mb(); 5165 clear_bit(BEISCSI_HBA_BOOT_WORK, &phba->state); 5166 return; 5167 } 5168 if (!tag) { 5169 if (bs->retry--) 5170 schedule_work(&phba->boot_work); 5171 else 5172 clear_bit(BEISCSI_HBA_BOOT_WORK, &phba->state); 5173 } 5174 } 5175 5176 static void beiscsi_eqd_update_work(struct work_struct *work) 5177 { 5178 struct hwi_context_memory *phwi_context; 5179 struct be_set_eqd set_eqd[MAX_CPUS]; 5180 struct hwi_controller *phwi_ctrlr; 5181 struct be_eq_obj *pbe_eq; 5182 struct beiscsi_hba *phba; 5183 unsigned int pps, delta; 5184 struct be_aic_obj *aic; 5185 int eqd, i, num = 0; 5186 unsigned long now; 5187 5188 phba = container_of(work, struct beiscsi_hba, eqd_update.work); 5189 if (!beiscsi_hba_is_online(phba)) 5190 return; 5191 5192 phwi_ctrlr = phba->phwi_ctrlr; 5193 phwi_context = phwi_ctrlr->phwi_ctxt; 5194 5195 for (i = 0; i <= phba->num_cpus; i++) { 5196 aic = &phba->aic_obj[i]; 5197 pbe_eq = &phwi_context->be_eq[i]; 5198 now = jiffies; 5199 if (!aic->jiffies || time_before(now, aic->jiffies) || 5200 pbe_eq->cq_count < aic->eq_prev) { 5201 aic->jiffies = now; 5202 aic->eq_prev = pbe_eq->cq_count; 5203 continue; 5204 } 5205 delta = jiffies_to_msecs(now - aic->jiffies); 5206 pps = (((u32)(pbe_eq->cq_count - aic->eq_prev) * 1000) / delta); 5207 eqd = (pps / 1500) << 2; 5208 5209 if (eqd < 8) 5210 eqd = 0; 5211 eqd = min_t(u32, eqd, BEISCSI_EQ_DELAY_MAX); 5212 eqd = max_t(u32, eqd, BEISCSI_EQ_DELAY_MIN); 5213 5214 aic->jiffies = now; 5215 aic->eq_prev = pbe_eq->cq_count; 5216 5217 if (eqd != aic->prev_eqd) { 5218 set_eqd[num].delay_multiplier = (eqd * 65)/100; 5219 set_eqd[num].eq_id = pbe_eq->q.id; 5220 aic->prev_eqd = eqd; 5221 num++; 5222 } 5223 } 5224 if (num) 5225 /* completion of this is ignored */ 5226 beiscsi_modify_eq_delay(phba, set_eqd, num); 5227 5228 schedule_delayed_work(&phba->eqd_update, 5229 msecs_to_jiffies(BEISCSI_EQD_UPDATE_INTERVAL)); 5230 } 5231 5232 static void beiscsi_hw_tpe_check(struct timer_list *t) 5233 { 5234 struct beiscsi_hba *phba = timer_container_of(phba, t, hw_check); 5235 u32 wait; 5236 5237 /* if not TPE, do nothing */ 5238 if (!beiscsi_detect_tpe(phba)) 5239 return; 5240 5241 /* wait default 4000ms before recovering */ 5242 wait = 4000; 5243 if (phba->ue2rp > BEISCSI_UE_DETECT_INTERVAL) 5244 wait = phba->ue2rp - BEISCSI_UE_DETECT_INTERVAL; 5245 queue_delayed_work(phba->wq, &phba->recover_port, 5246 msecs_to_jiffies(wait)); 5247 } 5248 5249 static void beiscsi_hw_health_check(struct timer_list *t) 5250 { 5251 struct beiscsi_hba *phba = timer_container_of(phba, t, hw_check); 5252 5253 beiscsi_detect_ue(phba); 5254 if (beiscsi_detect_ue(phba)) { 5255 __beiscsi_log(phba, KERN_ERR, 5256 "BM_%d : port in error: %lx\n", phba->state); 5257 /* sessions are no longer valid, so first fail the sessions */ 5258 queue_work(phba->wq, &phba->sess_work); 5259 5260 /* detect UER supported */ 5261 if (!test_bit(BEISCSI_HBA_UER_SUPP, &phba->state)) 5262 return; 5263 /* modify this timer to check TPE */ 5264 phba->hw_check.function = beiscsi_hw_tpe_check; 5265 } 5266 5267 mod_timer(&phba->hw_check, 5268 jiffies + msecs_to_jiffies(BEISCSI_UE_DETECT_INTERVAL)); 5269 } 5270 5271 /* 5272 * beiscsi_enable_port()- Enables the disabled port. 5273 * Only port resources freed in disable function are reallocated. 5274 * This is called in HBA error handling path. 5275 * 5276 * @phba: Instance of driver private structure 5277 * 5278 **/ 5279 static int beiscsi_enable_port(struct beiscsi_hba *phba) 5280 { 5281 struct hwi_context_memory *phwi_context; 5282 struct hwi_controller *phwi_ctrlr; 5283 struct be_eq_obj *pbe_eq; 5284 int ret, i; 5285 5286 if (test_bit(BEISCSI_HBA_ONLINE, &phba->state)) { 5287 __beiscsi_log(phba, KERN_ERR, 5288 "BM_%d : %s : port is online %lx\n", 5289 __func__, phba->state); 5290 return 0; 5291 } 5292 5293 ret = beiscsi_init_sliport(phba); 5294 if (ret) 5295 return ret; 5296 5297 be2iscsi_enable_msix(phba); 5298 5299 beiscsi_get_params(phba); 5300 beiscsi_set_host_data(phba); 5301 /* Re-enable UER. If different TPE occurs then it is recoverable. */ 5302 beiscsi_set_uer_feature(phba); 5303 5304 phba->shost->max_id = phba->params.cxns_per_ctrl - 1; 5305 phba->shost->can_queue = phba->params.ios_per_ctrl; 5306 ret = beiscsi_init_port(phba); 5307 if (ret < 0) { 5308 __beiscsi_log(phba, KERN_ERR, 5309 "BM_%d : init port failed\n"); 5310 goto disable_msix; 5311 } 5312 5313 for (i = 0; i < MAX_MCC_CMD; i++) { 5314 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]); 5315 phba->ctrl.mcc_tag[i] = i + 1; 5316 phba->ctrl.mcc_tag_status[i + 1] = 0; 5317 phba->ctrl.mcc_tag_available++; 5318 } 5319 5320 phwi_ctrlr = phba->phwi_ctrlr; 5321 phwi_context = phwi_ctrlr->phwi_ctxt; 5322 for (i = 0; i < phba->num_cpus; i++) { 5323 pbe_eq = &phwi_context->be_eq[i]; 5324 irq_poll_init(&pbe_eq->iopoll, be_iopoll_budget, be_iopoll); 5325 } 5326 5327 i = (phba->pcidev->msix_enabled) ? i : 0; 5328 /* Work item for MCC handling */ 5329 pbe_eq = &phwi_context->be_eq[i]; 5330 INIT_WORK(&pbe_eq->mcc_work, beiscsi_mcc_work); 5331 5332 ret = beiscsi_init_irqs(phba); 5333 if (ret < 0) { 5334 __beiscsi_log(phba, KERN_ERR, 5335 "BM_%d : setup IRQs failed %d\n", ret); 5336 goto cleanup_port; 5337 } 5338 hwi_enable_intr(phba); 5339 /* port operational: clear all error bits */ 5340 set_bit(BEISCSI_HBA_ONLINE, &phba->state); 5341 __beiscsi_log(phba, KERN_INFO, 5342 "BM_%d : port online: 0x%lx\n", phba->state); 5343 5344 /* start hw_check timer and eqd_update work */ 5345 schedule_delayed_work(&phba->eqd_update, 5346 msecs_to_jiffies(BEISCSI_EQD_UPDATE_INTERVAL)); 5347 5348 /** 5349 * Timer function gets modified for TPE detection. 5350 * Always reinit to do health check first. 5351 */ 5352 phba->hw_check.function = beiscsi_hw_health_check; 5353 mod_timer(&phba->hw_check, 5354 jiffies + msecs_to_jiffies(BEISCSI_UE_DETECT_INTERVAL)); 5355 return 0; 5356 5357 cleanup_port: 5358 for (i = 0; i < phba->num_cpus; i++) { 5359 pbe_eq = &phwi_context->be_eq[i]; 5360 irq_poll_disable(&pbe_eq->iopoll); 5361 } 5362 hwi_cleanup_port(phba); 5363 5364 disable_msix: 5365 pci_free_irq_vectors(phba->pcidev); 5366 return ret; 5367 } 5368 5369 /* 5370 * beiscsi_disable_port()- Disable port and cleanup driver resources. 5371 * This is called in HBA error handling and driver removal. 5372 * @phba: Instance Priv structure 5373 * @unload: indicate driver is unloading 5374 * 5375 * Free the OS and HW resources held by the driver 5376 **/ 5377 static void beiscsi_disable_port(struct beiscsi_hba *phba, int unload) 5378 { 5379 struct hwi_context_memory *phwi_context; 5380 struct hwi_controller *phwi_ctrlr; 5381 struct be_eq_obj *pbe_eq; 5382 unsigned int i; 5383 5384 if (!test_and_clear_bit(BEISCSI_HBA_ONLINE, &phba->state)) 5385 return; 5386 5387 phwi_ctrlr = phba->phwi_ctrlr; 5388 phwi_context = phwi_ctrlr->phwi_ctxt; 5389 hwi_disable_intr(phba); 5390 beiscsi_free_irqs(phba); 5391 pci_free_irq_vectors(phba->pcidev); 5392 5393 for (i = 0; i < phba->num_cpus; i++) { 5394 pbe_eq = &phwi_context->be_eq[i]; 5395 irq_poll_disable(&pbe_eq->iopoll); 5396 } 5397 cancel_delayed_work_sync(&phba->eqd_update); 5398 cancel_work_sync(&phba->boot_work); 5399 /* WQ might be running cancel queued mcc_work if we are not exiting */ 5400 if (!unload && beiscsi_hba_in_error(phba)) { 5401 pbe_eq = &phwi_context->be_eq[i]; 5402 cancel_work_sync(&pbe_eq->mcc_work); 5403 } 5404 hwi_cleanup_port(phba); 5405 beiscsi_cleanup_port(phba); 5406 } 5407 5408 static void beiscsi_sess_work(struct work_struct *work) 5409 { 5410 struct beiscsi_hba *phba; 5411 5412 phba = container_of(work, struct beiscsi_hba, sess_work); 5413 /* 5414 * This work gets scheduled only in case of HBA error. 5415 * Old sessions are gone so need to be re-established. 5416 * iscsi_session_failure needs process context hence this work. 5417 */ 5418 iscsi_host_for_each_session(phba->shost, beiscsi_session_fail); 5419 } 5420 5421 static void beiscsi_recover_port(struct work_struct *work) 5422 { 5423 struct beiscsi_hba *phba; 5424 5425 phba = container_of(work, struct beiscsi_hba, recover_port.work); 5426 beiscsi_disable_port(phba, 0); 5427 beiscsi_enable_port(phba); 5428 } 5429 5430 static pci_ers_result_t beiscsi_eeh_err_detected(struct pci_dev *pdev, 5431 pci_channel_state_t state) 5432 { 5433 struct beiscsi_hba *phba = NULL; 5434 5435 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev); 5436 set_bit(BEISCSI_HBA_PCI_ERR, &phba->state); 5437 5438 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5439 "BM_%d : EEH error detected\n"); 5440 5441 /* first stop UE detection when PCI error detected */ 5442 timer_delete_sync(&phba->hw_check); 5443 cancel_delayed_work_sync(&phba->recover_port); 5444 5445 /* sessions are no longer valid, so first fail the sessions */ 5446 iscsi_host_for_each_session(phba->shost, beiscsi_session_fail); 5447 beiscsi_disable_port(phba, 0); 5448 5449 if (state == pci_channel_io_perm_failure) { 5450 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5451 "BM_%d : EEH : State PERM Failure"); 5452 return PCI_ERS_RESULT_DISCONNECT; 5453 } 5454 5455 pci_disable_device(pdev); 5456 5457 /* The error could cause the FW to trigger a flash debug dump. 5458 * Resetting the card while flash dump is in progress 5459 * can cause it not to recover; wait for it to finish. 5460 * Wait only for first function as it is needed only once per 5461 * adapter. 5462 **/ 5463 if (pdev->devfn == 0) 5464 ssleep(30); 5465 5466 return PCI_ERS_RESULT_NEED_RESET; 5467 } 5468 5469 static pci_ers_result_t beiscsi_eeh_reset(struct pci_dev *pdev) 5470 { 5471 struct beiscsi_hba *phba = NULL; 5472 int status = 0; 5473 5474 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev); 5475 5476 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5477 "BM_%d : EEH Reset\n"); 5478 5479 status = pci_enable_device(pdev); 5480 if (status) 5481 return PCI_ERS_RESULT_DISCONNECT; 5482 5483 pci_set_master(pdev); 5484 pci_set_power_state(pdev, PCI_D0); 5485 pci_restore_state(pdev); 5486 5487 status = beiscsi_check_fw_rdy(phba); 5488 if (status) { 5489 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, 5490 "BM_%d : EEH Reset Completed\n"); 5491 } else { 5492 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, 5493 "BM_%d : EEH Reset Completion Failure\n"); 5494 return PCI_ERS_RESULT_DISCONNECT; 5495 } 5496 5497 return PCI_ERS_RESULT_RECOVERED; 5498 } 5499 5500 static void beiscsi_eeh_resume(struct pci_dev *pdev) 5501 { 5502 struct beiscsi_hba *phba; 5503 int ret; 5504 5505 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev); 5506 pci_save_state(pdev); 5507 5508 ret = beiscsi_enable_port(phba); 5509 if (ret) 5510 __beiscsi_log(phba, KERN_ERR, 5511 "BM_%d : AER EEH resume failed\n"); 5512 } 5513 5514 static int beiscsi_dev_probe(struct pci_dev *pcidev, 5515 const struct pci_device_id *id) 5516 { 5517 struct hwi_context_memory *phwi_context; 5518 struct hwi_controller *phwi_ctrlr; 5519 struct beiscsi_hba *phba = NULL; 5520 struct be_eq_obj *pbe_eq; 5521 unsigned int s_handle; 5522 int ret, i; 5523 5524 ret = beiscsi_enable_pci(pcidev); 5525 if (ret < 0) { 5526 dev_err(&pcidev->dev, 5527 "beiscsi_dev_probe - Failed to enable pci device\n"); 5528 return ret; 5529 } 5530 5531 phba = beiscsi_hba_alloc(pcidev); 5532 if (!phba) { 5533 dev_err(&pcidev->dev, 5534 "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n"); 5535 ret = -ENOMEM; 5536 goto disable_pci; 5537 } 5538 5539 pci_save_state(pcidev); 5540 5541 /* Initialize Driver configuration Paramters */ 5542 beiscsi_hba_attrs_init(phba); 5543 5544 phba->mac_addr_set = false; 5545 5546 switch (pcidev->device) { 5547 case BE_DEVICE_ID1: 5548 case OC_DEVICE_ID1: 5549 case OC_DEVICE_ID2: 5550 phba->generation = BE_GEN2; 5551 phba->iotask_fn = beiscsi_iotask; 5552 dev_warn(&pcidev->dev, 5553 "Obsolete/Unsupported BE2 Adapter Family\n"); 5554 break; 5555 case BE_DEVICE_ID2: 5556 case OC_DEVICE_ID3: 5557 phba->generation = BE_GEN3; 5558 phba->iotask_fn = beiscsi_iotask; 5559 break; 5560 case OC_SKH_ID1: 5561 phba->generation = BE_GEN4; 5562 phba->iotask_fn = beiscsi_iotask_v2; 5563 break; 5564 default: 5565 phba->generation = 0; 5566 } 5567 5568 ret = be_ctrl_init(phba, pcidev); 5569 if (ret) { 5570 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5571 "BM_%d : be_ctrl_init failed\n"); 5572 goto free_hba; 5573 } 5574 5575 ret = beiscsi_init_sliport(phba); 5576 if (ret) 5577 goto free_hba; 5578 5579 spin_lock_init(&phba->io_sgl_lock); 5580 spin_lock_init(&phba->mgmt_sgl_lock); 5581 spin_lock_init(&phba->async_pdu_lock); 5582 ret = beiscsi_get_fw_config(&phba->ctrl, phba); 5583 if (ret != 0) { 5584 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5585 "BM_%d : Error getting fw config\n"); 5586 goto free_port; 5587 } 5588 beiscsi_get_port_name(&phba->ctrl, phba); 5589 beiscsi_get_params(phba); 5590 beiscsi_set_host_data(phba); 5591 beiscsi_set_uer_feature(phba); 5592 5593 be2iscsi_enable_msix(phba); 5594 5595 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 5596 "BM_%d : num_cpus = %d\n", 5597 phba->num_cpus); 5598 5599 phba->shost->max_id = phba->params.cxns_per_ctrl; 5600 phba->shost->can_queue = phba->params.ios_per_ctrl; 5601 ret = beiscsi_get_memory(phba); 5602 if (ret < 0) { 5603 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5604 "BM_%d : alloc host mem failed\n"); 5605 goto free_port; 5606 } 5607 5608 ret = beiscsi_init_port(phba); 5609 if (ret < 0) { 5610 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5611 "BM_%d : init port failed\n"); 5612 beiscsi_free_mem(phba); 5613 goto free_port; 5614 } 5615 5616 for (i = 0; i < MAX_MCC_CMD; i++) { 5617 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]); 5618 phba->ctrl.mcc_tag[i] = i + 1; 5619 phba->ctrl.mcc_tag_status[i + 1] = 0; 5620 phba->ctrl.mcc_tag_available++; 5621 memset(&phba->ctrl.ptag_state[i].tag_mem_state, 0, 5622 sizeof(struct be_dma_mem)); 5623 } 5624 5625 phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0; 5626 5627 phba->wq = alloc_workqueue("beiscsi_%02x_wq", 5628 WQ_MEM_RECLAIM | WQ_PERCPU, 1, 5629 phba->shost->host_no); 5630 if (!phba->wq) { 5631 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5632 "BM_%d : beiscsi_dev_probe-" 5633 "Failed to allocate work queue\n"); 5634 ret = -ENOMEM; 5635 goto free_twq; 5636 } 5637 5638 INIT_DELAYED_WORK(&phba->eqd_update, beiscsi_eqd_update_work); 5639 5640 phwi_ctrlr = phba->phwi_ctrlr; 5641 phwi_context = phwi_ctrlr->phwi_ctxt; 5642 5643 for (i = 0; i < phba->num_cpus; i++) { 5644 pbe_eq = &phwi_context->be_eq[i]; 5645 irq_poll_init(&pbe_eq->iopoll, be_iopoll_budget, be_iopoll); 5646 } 5647 5648 i = (phba->pcidev->msix_enabled) ? i : 0; 5649 /* Work item for MCC handling */ 5650 pbe_eq = &phwi_context->be_eq[i]; 5651 INIT_WORK(&pbe_eq->mcc_work, beiscsi_mcc_work); 5652 5653 ret = beiscsi_init_irqs(phba); 5654 if (ret < 0) { 5655 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5656 "BM_%d : beiscsi_dev_probe-" 5657 "Failed to beiscsi_init_irqs\n"); 5658 goto disable_iopoll; 5659 } 5660 hwi_enable_intr(phba); 5661 5662 ret = iscsi_host_add(phba->shost, &phba->pcidev->dev); 5663 if (ret) 5664 goto free_irqs; 5665 5666 /* set online bit after port is operational */ 5667 set_bit(BEISCSI_HBA_ONLINE, &phba->state); 5668 __beiscsi_log(phba, KERN_INFO, 5669 "BM_%d : port online: 0x%lx\n", phba->state); 5670 5671 INIT_WORK(&phba->boot_work, beiscsi_boot_work); 5672 ret = beiscsi_boot_get_shandle(phba, &s_handle); 5673 if (ret > 0) { 5674 beiscsi_start_boot_work(phba, s_handle); 5675 /** 5676 * Set this bit after starting the work to let 5677 * probe handle it first. 5678 * ASYNC event can too schedule this work. 5679 */ 5680 set_bit(BEISCSI_HBA_BOOT_FOUND, &phba->state); 5681 } 5682 5683 beiscsi_iface_create_default(phba); 5684 schedule_delayed_work(&phba->eqd_update, 5685 msecs_to_jiffies(BEISCSI_EQD_UPDATE_INTERVAL)); 5686 5687 INIT_WORK(&phba->sess_work, beiscsi_sess_work); 5688 INIT_DELAYED_WORK(&phba->recover_port, beiscsi_recover_port); 5689 /** 5690 * Start UE detection here. UE before this will cause stall in probe 5691 * and eventually fail the probe. 5692 */ 5693 timer_setup(&phba->hw_check, beiscsi_hw_health_check, 0); 5694 mod_timer(&phba->hw_check, 5695 jiffies + msecs_to_jiffies(BEISCSI_UE_DETECT_INTERVAL)); 5696 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 5697 "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n"); 5698 return 0; 5699 5700 free_irqs: 5701 hwi_disable_intr(phba); 5702 beiscsi_free_irqs(phba); 5703 disable_iopoll: 5704 for (i = 0; i < phba->num_cpus; i++) { 5705 pbe_eq = &phwi_context->be_eq[i]; 5706 irq_poll_disable(&pbe_eq->iopoll); 5707 } 5708 destroy_workqueue(phba->wq); 5709 free_twq: 5710 hwi_cleanup_port(phba); 5711 beiscsi_cleanup_port(phba); 5712 beiscsi_free_mem(phba); 5713 free_port: 5714 dma_free_coherent(&phba->pcidev->dev, 5715 phba->ctrl.mbox_mem_alloced.size, 5716 phba->ctrl.mbox_mem_alloced.va, 5717 phba->ctrl.mbox_mem_alloced.dma); 5718 beiscsi_unmap_pci_function(phba); 5719 free_hba: 5720 pci_disable_msix(phba->pcidev); 5721 pci_dev_put(phba->pcidev); 5722 iscsi_host_free(phba->shost); 5723 pci_set_drvdata(pcidev, NULL); 5724 disable_pci: 5725 pci_release_regions(pcidev); 5726 pci_disable_device(pcidev); 5727 return ret; 5728 } 5729 5730 static void beiscsi_remove(struct pci_dev *pcidev) 5731 { 5732 struct beiscsi_hba *phba = NULL; 5733 5734 phba = pci_get_drvdata(pcidev); 5735 if (!phba) { 5736 dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n"); 5737 return; 5738 } 5739 5740 /* first stop UE detection before unloading */ 5741 timer_delete_sync(&phba->hw_check); 5742 cancel_delayed_work_sync(&phba->recover_port); 5743 cancel_work_sync(&phba->sess_work); 5744 5745 beiscsi_iface_destroy_default(phba); 5746 iscsi_host_remove(phba->shost, false); 5747 beiscsi_disable_port(phba, 1); 5748 5749 /* after cancelling boot_work */ 5750 iscsi_boot_destroy_kset(phba->boot_struct.boot_kset); 5751 5752 /* free all resources */ 5753 destroy_workqueue(phba->wq); 5754 beiscsi_free_mem(phba); 5755 5756 /* ctrl uninit */ 5757 beiscsi_unmap_pci_function(phba); 5758 dma_free_coherent(&phba->pcidev->dev, 5759 phba->ctrl.mbox_mem_alloced.size, 5760 phba->ctrl.mbox_mem_alloced.va, 5761 phba->ctrl.mbox_mem_alloced.dma); 5762 5763 pci_dev_put(phba->pcidev); 5764 iscsi_host_free(phba->shost); 5765 pci_set_drvdata(pcidev, NULL); 5766 pci_release_regions(pcidev); 5767 pci_disable_device(pcidev); 5768 } 5769 5770 5771 static const struct pci_error_handlers beiscsi_eeh_handlers = { 5772 .error_detected = beiscsi_eeh_err_detected, 5773 .slot_reset = beiscsi_eeh_reset, 5774 .resume = beiscsi_eeh_resume, 5775 }; 5776 5777 struct iscsi_transport beiscsi_iscsi_transport = { 5778 .owner = THIS_MODULE, 5779 .name = DRV_NAME, 5780 .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO | 5781 CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD, 5782 .create_session = beiscsi_session_create, 5783 .destroy_session = beiscsi_session_destroy, 5784 .create_conn = beiscsi_conn_create, 5785 .bind_conn = beiscsi_conn_bind, 5786 .unbind_conn = iscsi_conn_unbind, 5787 .destroy_conn = iscsi_conn_teardown, 5788 .attr_is_visible = beiscsi_attr_is_visible, 5789 .set_iface_param = beiscsi_iface_set_param, 5790 .get_iface_param = beiscsi_iface_get_param, 5791 .set_param = beiscsi_set_param, 5792 .get_conn_param = iscsi_conn_get_param, 5793 .get_session_param = iscsi_session_get_param, 5794 .get_host_param = beiscsi_get_host_param, 5795 .start_conn = beiscsi_conn_start, 5796 .stop_conn = iscsi_conn_stop, 5797 .send_pdu = iscsi_conn_send_pdu, 5798 .xmit_task = beiscsi_task_xmit, 5799 .cleanup_task = beiscsi_cleanup_task, 5800 .alloc_pdu = beiscsi_alloc_pdu, 5801 .parse_pdu_itt = beiscsi_parse_pdu, 5802 .get_stats = beiscsi_conn_get_stats, 5803 .get_ep_param = beiscsi_ep_get_param, 5804 .ep_connect = beiscsi_ep_connect, 5805 .ep_poll = beiscsi_ep_poll, 5806 .ep_disconnect = beiscsi_ep_disconnect, 5807 .session_recovery_timedout = iscsi_session_recovery_timedout, 5808 .bsg_request = beiscsi_bsg_request, 5809 }; 5810 5811 static struct pci_driver beiscsi_pci_driver = { 5812 .name = DRV_NAME, 5813 .probe = beiscsi_dev_probe, 5814 .remove = beiscsi_remove, 5815 .id_table = beiscsi_pci_id_table, 5816 .err_handler = &beiscsi_eeh_handlers 5817 }; 5818 5819 static int __init beiscsi_module_init(void) 5820 { 5821 int ret; 5822 5823 beiscsi_scsi_transport = 5824 iscsi_register_transport(&beiscsi_iscsi_transport); 5825 if (!beiscsi_scsi_transport) { 5826 printk(KERN_ERR 5827 "beiscsi_module_init - Unable to register beiscsi transport.\n"); 5828 return -ENOMEM; 5829 } 5830 printk(KERN_INFO "In beiscsi_module_init, tt=%p\n", 5831 &beiscsi_iscsi_transport); 5832 5833 ret = pci_register_driver(&beiscsi_pci_driver); 5834 if (ret) { 5835 printk(KERN_ERR 5836 "beiscsi_module_init - Unable to register beiscsi pci driver.\n"); 5837 goto unregister_iscsi_transport; 5838 } 5839 return 0; 5840 5841 unregister_iscsi_transport: 5842 iscsi_unregister_transport(&beiscsi_iscsi_transport); 5843 return ret; 5844 } 5845 5846 static void __exit beiscsi_module_exit(void) 5847 { 5848 pci_unregister_driver(&beiscsi_pci_driver); 5849 iscsi_unregister_transport(&beiscsi_iscsi_transport); 5850 } 5851 5852 module_init(beiscsi_module_init); 5853 module_exit(beiscsi_module_exit); 5854