1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef AMDGPU_USERQ_H_ 26 #define AMDGPU_USERQ_H_ 27 #include "amdgpu_eviction_fence.h" 28 29 #define AMDGPU_MAX_USERQ_COUNT 512 30 31 #define to_ev_fence(f) container_of(f, struct amdgpu_eviction_fence, base) 32 #define uq_mgr_to_fpriv(u) container_of(u, struct amdgpu_fpriv, userq_mgr) 33 #define work_to_uq_mgr(w, name) container_of(w, struct amdgpu_userq_mgr, name) 34 35 enum amdgpu_userq_state { 36 AMDGPU_USERQ_STATE_UNMAPPED = 0, 37 AMDGPU_USERQ_STATE_MAPPED, 38 AMDGPU_USERQ_STATE_PREEMPTED, 39 AMDGPU_USERQ_STATE_HUNG, 40 AMDGPU_USERQ_STATE_INVALID_VA, 41 }; 42 43 struct amdgpu_mqd_prop; 44 45 struct amdgpu_userq_obj { 46 void *cpu_ptr; 47 uint64_t gpu_addr; 48 struct amdgpu_bo *obj; 49 }; 50 51 struct amdgpu_usermode_queue { 52 int queue_type; 53 enum amdgpu_userq_state state; 54 uint64_t doorbell_handle; 55 uint64_t doorbell_index; 56 uint64_t flags; 57 struct amdgpu_mqd_prop *userq_prop; 58 struct amdgpu_userq_mgr *userq_mgr; 59 struct amdgpu_vm *vm; 60 struct amdgpu_userq_obj mqd; 61 struct amdgpu_userq_obj db_obj; 62 struct amdgpu_userq_obj fw_obj; 63 struct amdgpu_userq_obj wptr_obj; 64 65 /** 66 * @fence_drv_lock: Protecting @fence_drv_xa. 67 */ 68 struct mutex fence_drv_lock; 69 70 /** 71 * @fence_drv_xa: 72 * 73 * References to the external fence drivers returned by wait_ioctl. 74 * Dropped on the next signaled dma_fence or queue destruction. 75 */ 76 struct xarray fence_drv_xa; 77 struct amdgpu_userq_fence_driver *fence_drv; 78 struct dma_fence *last_fence; 79 u32 xcp_id; 80 int priority; 81 struct dentry *debugfs_queue; 82 83 /** 84 * @hang_detect_work: 85 * 86 * Delayed work which runs when userq_fences time out. 87 */ 88 struct delayed_work hang_detect_work; 89 struct kref refcount; 90 91 union { 92 struct { 93 u64 queue_rb; 94 u64 wptr; 95 u64 rptr; 96 u64 eop; 97 u64 shadow; 98 u64 csa; 99 } va; 100 u64 va_array[6]; 101 } userq_vas; 102 }; 103 104 struct amdgpu_userq_funcs { 105 int (*mqd_create)(struct amdgpu_usermode_queue *queue, 106 struct drm_amdgpu_userq_in *args); 107 int (*mqd_update)(struct amdgpu_usermode_queue *queue, 108 struct drm_amdgpu_userq_in *args); 109 void (*mqd_destroy)(struct amdgpu_usermode_queue *uq); 110 int (*unmap)(struct amdgpu_usermode_queue *queue); 111 int (*map)(struct amdgpu_usermode_queue *queue); 112 int (*preempt)(struct amdgpu_usermode_queue *queue); 113 int (*restore)(struct amdgpu_usermode_queue *queue); 114 int (*detect_and_reset)(struct amdgpu_device *adev, 115 int queue_type); 116 }; 117 118 /* Usermode queues for gfx */ 119 struct amdgpu_userq_mgr { 120 /** 121 * @userq_xa: Per-process user queue map (queue ID → queue) 122 * Key: queue_id (unique ID within the process's userq manager) 123 * Value: struct amdgpu_usermode_queue 124 */ 125 struct xarray userq_xa; 126 struct mutex userq_mutex; 127 struct amdgpu_device *adev; 128 struct delayed_work resume_work; 129 struct drm_file *file; 130 131 /** 132 * @reset_work: 133 * 134 * Reset work which is used when eviction fails. 135 */ 136 struct work_struct reset_work; 137 atomic_t userq_count[AMDGPU_RING_TYPE_MAX]; 138 }; 139 140 struct amdgpu_db_info { 141 uint64_t doorbell_handle; 142 uint32_t queue_type; 143 uint32_t doorbell_offset; 144 struct amdgpu_userq_obj *db_obj; 145 }; 146 147 struct amdgpu_usermode_queue *amdgpu_userq_get(struct amdgpu_userq_mgr *uq_mgr, u32 qid); 148 void amdgpu_userq_put(struct amdgpu_usermode_queue *queue); 149 150 int amdgpu_userq_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 151 152 int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *file_priv, 153 struct amdgpu_device *adev); 154 155 void amdgpu_userq_mgr_cancel_reset_work(struct amdgpu_device *adev); 156 void amdgpu_userq_mgr_cancel_resume(struct amdgpu_userq_mgr *userq_mgr); 157 void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr); 158 159 void amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr); 160 161 void amdgpu_userq_ensure_ev_fence(struct amdgpu_userq_mgr *userq_mgr, 162 struct amdgpu_eviction_fence_mgr *evf_mgr); 163 164 u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev); 165 bool amdgpu_userq_enabled(struct drm_device *dev); 166 167 int amdgpu_userq_suspend(struct amdgpu_device *adev); 168 int amdgpu_userq_resume(struct amdgpu_device *adev); 169 170 int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev, 171 u32 idx); 172 int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev, 173 u32 idx); 174 void amdgpu_userq_reset_work(struct work_struct *work); 175 void amdgpu_userq_pre_reset(struct amdgpu_device *adev); 176 int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost); 177 void amdgpu_userq_start_hang_detect_work(struct amdgpu_usermode_queue *queue); 178 void amdgpu_userq_process_fence_irq(struct amdgpu_device *adev, u32 doorbell); 179 180 int amdgpu_userq_input_va_validate(struct amdgpu_device *adev, 181 struct amdgpu_usermode_queue *queue, 182 u64 addr, u64 expected_size, u64 *va_out); 183 184 void amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev, 185 struct amdgpu_bo_va_mapping *mapping, 186 uint64_t saddr); 187 #endif 188