1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/drm_fixed.h> 28 #include <drm/drm_fourcc.h> 29 #include <drm/drm_framebuffer.h> 30 #include <drm/drm_modeset_helper_vtables.h> 31 #include <drm/drm_vblank.h> 32 #include <drm/radeon_drm.h> 33 34 #include "atom.h" 35 #include "radeon.h" 36 37 static void radeon_overscan_setup(struct drm_crtc *crtc, 38 struct drm_display_mode *mode) 39 { 40 struct drm_device *dev = crtc->dev; 41 struct radeon_device *rdev = dev->dev_private; 42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 43 44 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); 45 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); 46 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); 47 } 48 49 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, 50 struct drm_display_mode *mode) 51 { 52 struct drm_device *dev = crtc->dev; 53 struct radeon_device *rdev = dev->dev_private; 54 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 55 int xres = mode->hdisplay; 56 int yres = mode->vdisplay; 57 bool hscale = true, vscale = true; 58 int hsync_wid; 59 int vsync_wid; 60 int hsync_start; 61 int blank_width; 62 u32 scale, inc, crtc_more_cntl; 63 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; 64 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; 65 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; 66 struct drm_display_mode *native_mode = &radeon_crtc->native_mode; 67 68 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & 69 (RADEON_VERT_STRETCH_RESERVED | 70 RADEON_VERT_AUTO_RATIO_INC); 71 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & 72 (RADEON_HORZ_FP_LOOP_STRETCH | 73 RADEON_HORZ_AUTO_RATIO_INC); 74 75 crtc_more_cntl = 0; 76 if ((rdev->family == CHIP_RS100) || 77 (rdev->family == CHIP_RS200)) { 78 /* This is to workaround the asic bug for RMX, some versions 79 of BIOS dosen't have this register initialized correctly. */ 80 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; 81 } 82 83 84 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 85 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 86 87 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 88 if (!hsync_wid) 89 hsync_wid = 1; 90 hsync_start = mode->crtc_hsync_start - 8; 91 92 fp_h_sync_strt_wid = ((hsync_start & 0x1fff) 93 | ((hsync_wid & 0x3f) << 16) 94 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 95 ? RADEON_CRTC_H_SYNC_POL 96 : 0)); 97 98 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 99 | ((mode->crtc_vdisplay - 1) << 16)); 100 101 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 102 if (!vsync_wid) 103 vsync_wid = 1; 104 105 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 106 | ((vsync_wid & 0x1f) << 16) 107 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 108 ? RADEON_CRTC_V_SYNC_POL 109 : 0)); 110 111 fp_horz_vert_active = 0; 112 113 if (native_mode->hdisplay == 0 || 114 native_mode->vdisplay == 0) { 115 hscale = false; 116 vscale = false; 117 } else { 118 if (xres > native_mode->hdisplay) 119 xres = native_mode->hdisplay; 120 if (yres > native_mode->vdisplay) 121 yres = native_mode->vdisplay; 122 123 if (xres == native_mode->hdisplay) 124 hscale = false; 125 if (yres == native_mode->vdisplay) 126 vscale = false; 127 } 128 129 switch (radeon_crtc->rmx_type) { 130 case RMX_FULL: 131 case RMX_ASPECT: 132 if (!hscale) 133 fp_horz_stretch |= ((xres/8-1) << 16); 134 else { 135 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; 136 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) 137 / native_mode->hdisplay + 1; 138 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | 139 RADEON_HORZ_STRETCH_BLEND | 140 RADEON_HORZ_STRETCH_ENABLE | 141 ((native_mode->hdisplay/8-1) << 16)); 142 } 143 144 if (!vscale) 145 fp_vert_stretch |= ((yres-1) << 12); 146 else { 147 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; 148 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) 149 / native_mode->vdisplay + 1; 150 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | 151 RADEON_VERT_STRETCH_ENABLE | 152 RADEON_VERT_STRETCH_BLEND | 153 ((native_mode->vdisplay-1) << 12)); 154 } 155 break; 156 case RMX_CENTER: 157 fp_horz_stretch |= ((xres/8-1) << 16); 158 fp_vert_stretch |= ((yres-1) << 12); 159 160 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | 161 RADEON_CRTC_AUTO_VERT_CENTER_EN); 162 163 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; 164 if (blank_width > 110) 165 blank_width = 110; 166 167 fp_crtc_h_total_disp = (((blank_width) & 0x3ff) 168 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 169 170 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 171 if (!hsync_wid) 172 hsync_wid = 1; 173 174 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) 175 | ((hsync_wid & 0x3f) << 16) 176 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 177 ? RADEON_CRTC_H_SYNC_POL 178 : 0)); 179 180 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) 181 | ((mode->crtc_vdisplay - 1) << 16)); 182 183 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 184 if (!vsync_wid) 185 vsync_wid = 1; 186 187 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) 188 | ((vsync_wid & 0x1f) << 16) 189 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 190 ? RADEON_CRTC_V_SYNC_POL 191 : 0))); 192 193 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) | 194 (((native_mode->hdisplay / 8) & 0x1ff) << 16)); 195 break; 196 case RMX_OFF: 197 default: 198 fp_horz_stretch |= ((xres/8-1) << 16); 199 fp_vert_stretch |= ((yres-1) << 12); 200 break; 201 } 202 203 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); 204 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); 205 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); 206 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); 207 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); 208 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); 209 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); 210 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); 211 } 212 213 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) 214 { 215 struct radeon_device *rdev = dev->dev_private; 216 int i = 0; 217 218 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 219 the cause yet, but this workaround will mask the problem for now. 220 Other chips usually will pass at the very first test, so the 221 workaround shouldn't have any effect on them. */ 222 for (i = 0; 223 (i < 10000 && 224 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 225 i++); 226 } 227 228 static void radeon_pll_write_update(struct drm_device *dev) 229 { 230 struct radeon_device *rdev = dev->dev_private; 231 232 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 233 234 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 235 RADEON_PPLL_ATOMIC_UPDATE_W, 236 ~(RADEON_PPLL_ATOMIC_UPDATE_W)); 237 } 238 239 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) 240 { 241 struct radeon_device *rdev = dev->dev_private; 242 int i = 0; 243 244 245 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 246 the cause yet, but this workaround will mask the problem for now. 247 Other chips usually will pass at the very first test, so the 248 workaround shouldn't have any effect on them. */ 249 for (i = 0; 250 (i < 10000 && 251 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 252 i++); 253 } 254 255 static void radeon_pll2_write_update(struct drm_device *dev) 256 { 257 struct radeon_device *rdev = dev->dev_private; 258 259 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 260 261 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 262 RADEON_P2PLL_ATOMIC_UPDATE_W, 263 ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); 264 } 265 266 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, 267 uint16_t fb_div) 268 { 269 unsigned int vcoFreq; 270 271 if (!ref_div) 272 return 1; 273 274 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; 275 276 /* 277 * This is horribly crude: the VCO frequency range is divided into 278 * 3 parts, each part having a fixed PLL gain value. 279 */ 280 if (vcoFreq >= 30000) 281 /* 282 * [300..max] MHz : 7 283 */ 284 return 7; 285 else if (vcoFreq >= 18000) 286 /* 287 * [180..300) MHz : 4 288 */ 289 return 4; 290 else 291 /* 292 * [0..180) MHz : 1 293 */ 294 return 1; 295 } 296 297 static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) 298 { 299 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 300 struct drm_device *dev = crtc->dev; 301 struct radeon_device *rdev = dev->dev_private; 302 uint32_t crtc_ext_cntl = 0; 303 uint32_t mask; 304 305 if (radeon_crtc->crtc_id) 306 mask = (RADEON_CRTC2_DISP_DIS | 307 RADEON_CRTC2_VSYNC_DIS | 308 RADEON_CRTC2_HSYNC_DIS | 309 RADEON_CRTC2_DISP_REQ_EN_B); 310 else 311 mask = (RADEON_CRTC_DISPLAY_DIS | 312 RADEON_CRTC_VSYNC_DIS | 313 RADEON_CRTC_HSYNC_DIS); 314 315 /* 316 * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC. 317 * Therefore it is set in the DAC DMPS function. 318 * This is different for GPU's with a single CRTC but a primary and a 319 * TV DAC: here it controls the single CRTC no matter where it is 320 * routed. Therefore we set it here. 321 */ 322 if (rdev->flags & RADEON_SINGLE_CRTC) 323 crtc_ext_cntl = RADEON_CRTC_CRT_ON; 324 325 switch (mode) { 326 case DRM_MODE_DPMS_ON: 327 radeon_crtc->enabled = true; 328 /* adjust pm to dpms changes BEFORE enabling crtcs */ 329 radeon_pm_compute_clocks(rdev); 330 if (radeon_crtc->crtc_id) 331 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); 332 else { 333 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | 334 RADEON_CRTC_DISP_REQ_EN_B)); 335 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); 336 } 337 if (dev->num_crtcs > radeon_crtc->crtc_id) 338 drm_crtc_vblank_on(crtc); 339 radeon_crtc_load_lut(crtc); 340 break; 341 case DRM_MODE_DPMS_STANDBY: 342 case DRM_MODE_DPMS_SUSPEND: 343 case DRM_MODE_DPMS_OFF: 344 if (dev->num_crtcs > radeon_crtc->crtc_id) 345 drm_crtc_vblank_off(crtc); 346 if (radeon_crtc->crtc_id) 347 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); 348 else { 349 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | 350 RADEON_CRTC_DISP_REQ_EN_B)); 351 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); 352 } 353 radeon_crtc->enabled = false; 354 /* adjust pm to dpms changes AFTER disabling crtcs */ 355 radeon_pm_compute_clocks(rdev); 356 break; 357 } 358 } 359 360 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 361 struct drm_framebuffer *old_fb) 362 { 363 return radeon_crtc_do_set_base(crtc, old_fb, x, y); 364 } 365 366 int radeon_crtc_do_set_base(struct drm_crtc *crtc, 367 struct drm_framebuffer *fb, 368 int x, int y) 369 { 370 struct drm_device *dev = crtc->dev; 371 struct radeon_device *rdev = dev->dev_private; 372 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 373 struct drm_framebuffer *target_fb; 374 struct drm_gem_object *obj; 375 struct radeon_bo *rbo; 376 uint64_t base; 377 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; 378 uint32_t crtc_pitch, pitch_pixels; 379 uint32_t tiling_flags; 380 int format; 381 uint32_t gen_cntl_reg, gen_cntl_val; 382 int r; 383 384 DRM_DEBUG_KMS("\n"); 385 /* no fb bound */ 386 if (!crtc->primary->fb) { 387 DRM_DEBUG_KMS("No FB bound\n"); 388 return 0; 389 } 390 391 target_fb = crtc->primary->fb; 392 393 switch (target_fb->format->cpp[0] * 8) { 394 case 8: 395 format = 2; 396 break; 397 case 15: /* 555 */ 398 format = 3; 399 break; 400 case 16: /* 565 */ 401 format = 4; 402 break; 403 case 24: /* RGB */ 404 format = 5; 405 break; 406 case 32: /* xRGB */ 407 format = 6; 408 break; 409 default: 410 return false; 411 } 412 413 /* Pin framebuffer & get tilling informations */ 414 obj = target_fb->obj[0]; 415 rbo = gem_to_radeon_bo(obj); 416 retry: 417 r = radeon_bo_reserve(rbo, false); 418 if (unlikely(r != 0)) 419 return r; 420 /* Only 27 bit offset for legacy CRTC */ 421 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27, 422 &base); 423 if (unlikely(r != 0)) { 424 radeon_bo_unreserve(rbo); 425 426 /* On old GPU like RN50 with little vram pining can fails because 427 * current fb is taking all space needed. So instead of unpining 428 * the old buffer after pining the new one, first unpin old one 429 * and then retry pining new one. 430 * 431 * As only master can set mode only master can pin and it is 432 * unlikely the master client will race with itself especialy 433 * on those old gpu with single crtc. 434 * 435 * We don't shutdown the display controller because new buffer 436 * will end up in same spot. 437 */ 438 if (fb && fb != crtc->primary->fb) { 439 struct radeon_bo *old_rbo; 440 unsigned long nsize, osize; 441 442 old_rbo = gem_to_radeon_bo(fb->obj[0]); 443 osize = radeon_bo_size(old_rbo); 444 nsize = radeon_bo_size(rbo); 445 if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) { 446 radeon_bo_unpin(old_rbo); 447 radeon_bo_unreserve(old_rbo); 448 fb = NULL; 449 goto retry; 450 } 451 } 452 return -EINVAL; 453 } 454 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 455 radeon_bo_unreserve(rbo); 456 if (tiling_flags & RADEON_TILING_MICRO) 457 DRM_ERROR("trying to scanout microtiled buffer\n"); 458 459 /* if scanout was in GTT this really wouldn't work */ 460 /* crtc offset is from display base addr not FB location */ 461 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; 462 463 base -= radeon_crtc->legacy_display_base_addr; 464 465 crtc_offset_cntl = 0; 466 467 pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 468 crtc_pitch = DIV_ROUND_UP(pitch_pixels * target_fb->format->cpp[0] * 8, 469 target_fb->format->cpp[0] * 8 * 8); 470 crtc_pitch |= crtc_pitch << 16; 471 472 crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; 473 if (tiling_flags & RADEON_TILING_MACRO) { 474 if (ASIC_IS_R300(rdev)) 475 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | 476 R300_CRTC_MICRO_TILE_BUFFER_DIS | 477 R300_CRTC_MACRO_TILE_EN); 478 else 479 crtc_offset_cntl |= RADEON_CRTC_TILE_EN; 480 } else { 481 if (ASIC_IS_R300(rdev)) 482 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | 483 R300_CRTC_MICRO_TILE_BUFFER_DIS | 484 R300_CRTC_MACRO_TILE_EN); 485 else 486 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; 487 } 488 489 if (tiling_flags & RADEON_TILING_MACRO) { 490 if (ASIC_IS_R300(rdev)) { 491 crtc_tile_x0_y0 = x | (y << 16); 492 base &= ~0x7ff; 493 } else { 494 int byteshift = target_fb->format->cpp[0] * 8 >> 4; 495 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; 496 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 497 crtc_offset_cntl |= (y % 16); 498 } 499 } else { 500 int offset = y * pitch_pixels + x; 501 switch (target_fb->format->cpp[0] * 8) { 502 case 8: 503 offset *= 1; 504 break; 505 case 15: 506 case 16: 507 offset *= 2; 508 break; 509 case 24: 510 offset *= 3; 511 break; 512 case 32: 513 offset *= 4; 514 break; 515 default: 516 return false; 517 } 518 base += offset; 519 } 520 521 base &= ~7; 522 523 if (radeon_crtc->crtc_id == 1) 524 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; 525 else 526 gen_cntl_reg = RADEON_CRTC_GEN_CNTL; 527 528 gen_cntl_val = RREG32(gen_cntl_reg); 529 gen_cntl_val &= ~(0xf << 8); 530 gen_cntl_val |= (format << 8); 531 gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK; 532 WREG32(gen_cntl_reg, gen_cntl_val); 533 534 crtc_offset = (u32)base; 535 536 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); 537 538 if (ASIC_IS_R300(rdev)) { 539 if (radeon_crtc->crtc_id) 540 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); 541 else 542 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); 543 } 544 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); 545 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); 546 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); 547 548 if (fb && fb != crtc->primary->fb) { 549 rbo = gem_to_radeon_bo(fb->obj[0]); 550 r = radeon_bo_reserve(rbo, false); 551 if (unlikely(r != 0)) 552 return r; 553 radeon_bo_unpin(rbo); 554 radeon_bo_unreserve(rbo); 555 } 556 557 /* Bytes per pixel may have changed */ 558 radeon_bandwidth_update(rdev); 559 560 return 0; 561 } 562 563 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) 564 { 565 struct drm_device *dev = crtc->dev; 566 struct radeon_device *rdev = dev->dev_private; 567 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 568 const struct drm_framebuffer *fb = crtc->primary->fb; 569 struct drm_encoder *encoder; 570 int format; 571 int hsync_start; 572 int hsync_wid; 573 int vsync_wid; 574 uint32_t crtc_h_total_disp; 575 uint32_t crtc_h_sync_strt_wid; 576 uint32_t crtc_v_total_disp; 577 uint32_t crtc_v_sync_strt_wid; 578 bool is_tv = false; 579 580 DRM_DEBUG_KMS("\n"); 581 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 582 if (encoder->crtc == crtc) { 583 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 584 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 585 is_tv = true; 586 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); 587 break; 588 } 589 } 590 } 591 592 switch (fb->format->cpp[0] * 8) { 593 case 8: 594 format = 2; 595 break; 596 case 15: /* 555 */ 597 format = 3; 598 break; 599 case 16: /* 565 */ 600 format = 4; 601 break; 602 case 24: /* RGB */ 603 format = 5; 604 break; 605 case 32: /* xRGB */ 606 format = 6; 607 break; 608 default: 609 return false; 610 } 611 612 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 613 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 614 615 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 616 if (!hsync_wid) 617 hsync_wid = 1; 618 hsync_start = mode->crtc_hsync_start - 8; 619 620 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) 621 | ((hsync_wid & 0x3f) << 16) 622 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 623 ? RADEON_CRTC_H_SYNC_POL 624 : 0)); 625 626 /* This works for double scan mode. */ 627 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 628 | ((mode->crtc_vdisplay - 1) << 16)); 629 630 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 631 if (!vsync_wid) 632 vsync_wid = 1; 633 634 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 635 | ((vsync_wid & 0x1f) << 16) 636 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 637 ? RADEON_CRTC_V_SYNC_POL 638 : 0)); 639 640 if (radeon_crtc->crtc_id) { 641 uint32_t crtc2_gen_cntl; 642 uint32_t disp2_merge_cntl; 643 644 /* if TV DAC is enabled for another crtc and keep it enabled */ 645 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; 646 crtc2_gen_cntl |= ((format << 8) 647 | RADEON_CRTC2_VSYNC_DIS 648 | RADEON_CRTC2_HSYNC_DIS 649 | RADEON_CRTC2_DISP_DIS 650 | RADEON_CRTC2_DISP_REQ_EN_B 651 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 652 ? RADEON_CRTC2_DBL_SCAN_EN 653 : 0) 654 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 655 ? RADEON_CRTC2_CSYNC_EN 656 : 0) 657 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 658 ? RADEON_CRTC2_INTERLACE_EN 659 : 0)); 660 661 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 662 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 663 crtc2_gen_cntl |= RADEON_CRTC2_EN; 664 665 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 666 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 667 668 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); 669 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 670 671 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); 672 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); 673 } else { 674 uint32_t crtc_gen_cntl; 675 uint32_t crtc_ext_cntl; 676 uint32_t disp_merge_cntl; 677 678 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000; 679 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN 680 | (format << 8) 681 | RADEON_CRTC_DISP_REQ_EN_B 682 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 683 ? RADEON_CRTC_DBL_SCAN_EN 684 : 0) 685 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 686 ? RADEON_CRTC_CSYNC_EN 687 : 0) 688 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 689 ? RADEON_CRTC_INTERLACE_EN 690 : 0)); 691 692 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 693 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 694 crtc_gen_cntl |= RADEON_CRTC_EN; 695 696 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 697 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | 698 RADEON_CRTC_VSYNC_DIS | 699 RADEON_CRTC_HSYNC_DIS | 700 RADEON_CRTC_DISPLAY_DIS); 701 702 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 703 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 704 705 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 706 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 707 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 708 } 709 710 if (is_tv) 711 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, 712 &crtc_h_sync_strt_wid, &crtc_v_total_disp, 713 &crtc_v_sync_strt_wid); 714 715 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); 716 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); 717 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); 718 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); 719 720 return true; 721 } 722 723 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 724 { 725 struct drm_device *dev = crtc->dev; 726 struct radeon_device *rdev = dev->dev_private; 727 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 728 struct drm_encoder *encoder; 729 uint32_t feedback_div = 0; 730 uint32_t frac_fb_div = 0; 731 uint32_t reference_div = 0; 732 uint32_t post_divider = 0; 733 uint32_t freq = 0; 734 uint8_t pll_gain; 735 bool use_bios_divs = false; 736 /* PLL registers */ 737 uint32_t pll_ref_div = 0; 738 uint32_t pll_fb_post_div = 0; 739 uint32_t htotal_cntl = 0; 740 bool is_tv = false; 741 struct radeon_pll *pll; 742 743 struct { 744 int divider; 745 int bitvalue; 746 } *post_div, post_divs[] = { 747 /* From RAGE 128 VR/RAGE 128 GL Register 748 * Reference Manual (Technical Reference 749 * Manual P/N RRG-G04100-C Rev. 0.04), page 750 * 3-17 (PLL_DIV_[3:0]). 751 */ 752 { 1, 0 }, /* VCLK_SRC */ 753 { 2, 1 }, /* VCLK_SRC/2 */ 754 { 4, 2 }, /* VCLK_SRC/4 */ 755 { 8, 3 }, /* VCLK_SRC/8 */ 756 { 3, 4 }, /* VCLK_SRC/3 */ 757 { 16, 5 }, /* VCLK_SRC/16 */ 758 { 6, 6 }, /* VCLK_SRC/6 */ 759 { 12, 7 }, /* VCLK_SRC/12 */ 760 { 0, 0 } 761 }; 762 763 if (radeon_crtc->crtc_id) 764 pll = &rdev->clock.p2pll; 765 else 766 pll = &rdev->clock.p1pll; 767 768 pll->flags = RADEON_PLL_LEGACY; 769 770 if (mode->clock > 200000) /* range limits??? */ 771 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 772 else 773 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 774 775 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 776 if (encoder->crtc == crtc) { 777 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 778 779 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 780 is_tv = true; 781 break; 782 } 783 784 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 785 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 786 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { 787 if (!rdev->is_atom_bios) { 788 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 789 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; 790 if (lvds) { 791 if (lvds->use_bios_dividers) { 792 pll_ref_div = lvds->panel_ref_divider; 793 pll_fb_post_div = (lvds->panel_fb_divider | 794 (lvds->panel_post_divider << 16)); 795 htotal_cntl = 0; 796 use_bios_divs = true; 797 } 798 } 799 } 800 pll->flags |= RADEON_PLL_USE_REF_DIV; 801 } 802 } 803 } 804 805 DRM_DEBUG_KMS("\n"); 806 807 if (!use_bios_divs) { 808 radeon_compute_pll_legacy(pll, mode->clock, 809 &freq, &feedback_div, &frac_fb_div, 810 &reference_div, &post_divider); 811 812 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 813 if (post_div->divider == post_divider) 814 break; 815 } 816 817 if (!post_div->divider) 818 post_div = &post_divs[0]; 819 820 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n", 821 (unsigned)freq, 822 feedback_div, 823 reference_div, 824 post_divider); 825 826 pll_ref_div = reference_div; 827 #if defined(__powerpc__) && (0) /* TODO */ 828 /* apparently programming this otherwise causes a hang??? */ 829 if (info->MacModel == RADEON_MAC_IBOOK) 830 pll_fb_post_div = 0x000600ad; 831 else 832 #endif 833 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); 834 835 htotal_cntl = mode->htotal & 0x7; 836 837 } 838 839 pll_gain = radeon_compute_pll_gain(pll->reference_freq, 840 pll_ref_div & 0x3ff, 841 pll_fb_post_div & 0x7ff); 842 843 if (radeon_crtc->crtc_id) { 844 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & 845 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | 846 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); 847 848 if (is_tv) { 849 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, 850 &pll_ref_div, &pll_fb_post_div, 851 &pixclks_cntl); 852 } 853 854 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 855 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 856 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 857 858 WREG32_PLL_P(RADEON_P2PLL_CNTL, 859 RADEON_P2PLL_RESET 860 | RADEON_P2PLL_ATOMIC_UPDATE_EN 861 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), 862 ~(RADEON_P2PLL_RESET 863 | RADEON_P2PLL_ATOMIC_UPDATE_EN 864 | RADEON_P2PLL_PVG_MASK)); 865 866 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 867 pll_ref_div, 868 ~RADEON_P2PLL_REF_DIV_MASK); 869 870 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 871 pll_fb_post_div, 872 ~RADEON_P2PLL_FB0_DIV_MASK); 873 874 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 875 pll_fb_post_div, 876 ~RADEON_P2PLL_POST0_DIV_MASK); 877 878 radeon_pll2_write_update(dev); 879 radeon_pll2_wait_for_read_update_complete(dev); 880 881 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); 882 883 WREG32_PLL_P(RADEON_P2PLL_CNTL, 884 0, 885 ~(RADEON_P2PLL_RESET 886 | RADEON_P2PLL_SLEEP 887 | RADEON_P2PLL_ATOMIC_UPDATE_EN)); 888 889 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 890 (unsigned)pll_ref_div, 891 (unsigned)pll_fb_post_div, 892 (unsigned)htotal_cntl, 893 RREG32_PLL(RADEON_P2PLL_CNTL)); 894 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n", 895 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 896 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, 897 (unsigned)((pll_fb_post_div & 898 RADEON_P2PLL_POST0_DIV_MASK) >> 16)); 899 900 mdelay(50); /* Let the clock to lock */ 901 902 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 903 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 904 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 905 906 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 907 } else { 908 uint32_t pixclks_cntl; 909 910 911 if (is_tv) { 912 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 913 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, 914 &pll_fb_post_div, &pixclks_cntl); 915 } 916 917 if (rdev->flags & RADEON_IS_MOBILITY) { 918 /* A temporal workaround for the occasional blanking on certain laptop panels. 919 This appears to related to the PLL divider registers (fail to lock?). 920 It occurs even when all dividers are the same with their old settings. 921 In this case we really don't need to fiddle with PLL registers. 922 By doing this we can avoid the blanking problem with some panels. 923 */ 924 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && 925 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & 926 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { 927 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 928 RADEON_PLL_DIV_SEL, 929 ~(RADEON_PLL_DIV_SEL)); 930 r100_pll_errata_after_index(rdev); 931 return; 932 } 933 } 934 935 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 936 RADEON_VCLK_SRC_SEL_CPUCLK, 937 ~(RADEON_VCLK_SRC_SEL_MASK)); 938 WREG32_PLL_P(RADEON_PPLL_CNTL, 939 RADEON_PPLL_RESET 940 | RADEON_PPLL_ATOMIC_UPDATE_EN 941 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 942 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), 943 ~(RADEON_PPLL_RESET 944 | RADEON_PPLL_ATOMIC_UPDATE_EN 945 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 946 | RADEON_PPLL_PVG_MASK)); 947 948 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 949 RADEON_PLL_DIV_SEL, 950 ~(RADEON_PLL_DIV_SEL)); 951 r100_pll_errata_after_index(rdev); 952 953 if (ASIC_IS_R300(rdev) || 954 (rdev->family == CHIP_RS300) || 955 (rdev->family == CHIP_RS400) || 956 (rdev->family == CHIP_RS480)) { 957 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 958 /* When restoring console mode, use saved PPLL_REF_DIV 959 * setting. 960 */ 961 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 962 pll_ref_div, 963 0); 964 } else { 965 /* R300 uses ref_div_acc field as real ref divider */ 966 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 967 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 968 ~R300_PPLL_REF_DIV_ACC_MASK); 969 } 970 } else 971 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 972 pll_ref_div, 973 ~RADEON_PPLL_REF_DIV_MASK); 974 975 WREG32_PLL_P(RADEON_PPLL_DIV_3, 976 pll_fb_post_div, 977 ~RADEON_PPLL_FB3_DIV_MASK); 978 979 WREG32_PLL_P(RADEON_PPLL_DIV_3, 980 pll_fb_post_div, 981 ~RADEON_PPLL_POST3_DIV_MASK); 982 983 radeon_pll_write_update(dev); 984 radeon_pll_wait_for_read_update_complete(dev); 985 986 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); 987 988 WREG32_PLL_P(RADEON_PPLL_CNTL, 989 0, 990 ~(RADEON_PPLL_RESET 991 | RADEON_PPLL_SLEEP 992 | RADEON_PPLL_ATOMIC_UPDATE_EN 993 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); 994 995 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 996 pll_ref_div, 997 pll_fb_post_div, 998 (unsigned)htotal_cntl, 999 RREG32_PLL(RADEON_PPLL_CNTL)); 1000 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n", 1001 pll_ref_div & RADEON_PPLL_REF_DIV_MASK, 1002 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, 1003 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); 1004 1005 mdelay(50); /* Let the clock to lock */ 1006 1007 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 1008 RADEON_VCLK_SRC_SEL_PPLLCLK, 1009 ~(RADEON_VCLK_SRC_SEL_MASK)); 1010 1011 if (is_tv) 1012 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 1013 } 1014 } 1015 1016 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, 1017 const struct drm_display_mode *mode, 1018 struct drm_display_mode *adjusted_mode) 1019 { 1020 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1021 return false; 1022 return true; 1023 } 1024 1025 static int radeon_crtc_mode_set(struct drm_crtc *crtc, 1026 struct drm_display_mode *mode, 1027 struct drm_display_mode *adjusted_mode, 1028 int x, int y, struct drm_framebuffer *old_fb) 1029 { 1030 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1031 1032 /* TODO TV */ 1033 radeon_crtc_set_base(crtc, x, y, old_fb); 1034 radeon_set_crtc_timing(crtc, adjusted_mode); 1035 radeon_set_pll(crtc, adjusted_mode); 1036 radeon_overscan_setup(crtc, adjusted_mode); 1037 if (radeon_crtc->crtc_id == 0) { 1038 radeon_legacy_rmx_mode_set(crtc, adjusted_mode); 1039 } else { 1040 if (radeon_crtc->rmx_type != RMX_OFF) { 1041 /* FIXME: only first crtc has rmx what should we 1042 * do ? 1043 */ 1044 DRM_ERROR("Mode need scaling but only first crtc can do that.\n"); 1045 } 1046 } 1047 radeon_cursor_reset(crtc); 1048 return 0; 1049 } 1050 1051 static void radeon_crtc_prepare(struct drm_crtc *crtc) 1052 { 1053 struct drm_device *dev = crtc->dev; 1054 struct drm_crtc *crtci; 1055 1056 /* 1057 * The hardware wedges sometimes if you reconfigure one CRTC 1058 * whilst another is running (see fdo bug #24611). 1059 */ 1060 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) 1061 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF); 1062 } 1063 1064 static void radeon_crtc_commit(struct drm_crtc *crtc) 1065 { 1066 struct drm_device *dev = crtc->dev; 1067 struct drm_crtc *crtci; 1068 1069 /* 1070 * Reenable the CRTCs that should be running. 1071 */ 1072 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) { 1073 if (crtci->enabled) 1074 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); 1075 } 1076 } 1077 1078 static void radeon_crtc_disable(struct drm_crtc *crtc) 1079 { 1080 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1081 if (crtc->primary->fb) { 1082 int r; 1083 struct radeon_bo *rbo; 1084 1085 rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]); 1086 r = radeon_bo_reserve(rbo, false); 1087 if (unlikely(r)) 1088 DRM_ERROR("failed to reserve rbo before unpin\n"); 1089 else { 1090 radeon_bo_unpin(rbo); 1091 radeon_bo_unreserve(rbo); 1092 } 1093 } 1094 } 1095 1096 static const struct drm_crtc_helper_funcs legacy_helper_funcs = { 1097 .dpms = radeon_crtc_dpms, 1098 .mode_fixup = radeon_crtc_mode_fixup, 1099 .mode_set = radeon_crtc_mode_set, 1100 .mode_set_base = radeon_crtc_set_base, 1101 .prepare = radeon_crtc_prepare, 1102 .commit = radeon_crtc_commit, 1103 .disable = radeon_crtc_disable, 1104 .get_scanout_position = radeon_get_crtc_scanout_position, 1105 }; 1106 1107 1108 void radeon_legacy_init_crtc(struct drm_device *dev, 1109 struct radeon_crtc *radeon_crtc) 1110 { 1111 if (radeon_crtc->crtc_id == 1) 1112 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; 1113 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); 1114 } 1115