1 /* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __MLX5_EN_H__ 33 #define __MLX5_EN_H__ 34 35 #include <linux/if_vlan.h> 36 #include <linux/etherdevice.h> 37 #include <linux/timecounter.h> 38 #include <linux/net_tstamp.h> 39 #include <linux/crash_dump.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/qp.h> 42 #include <linux/mlx5/cq.h> 43 #include <linux/mlx5/port.h> 44 #include <linux/mlx5/vport.h> 45 #include <linux/mlx5/transobj.h> 46 #include <linux/mlx5/fs.h> 47 #include <linux/rhashtable.h> 48 #include <net/udp_tunnel.h> 49 #include <net/switchdev.h> 50 #include <net/psp/types.h> 51 #include <net/xdp.h> 52 #include <linux/dim.h> 53 #include <linux/bits.h> 54 #include "wq.h" 55 #include "mlx5_core.h" 56 #include "en_stats.h" 57 #include "en/dcbnl.h" 58 #include "en/fs.h" 59 #include "en/qos.h" 60 #include "lib/hv_vhca.h" 61 #include "lib/clock.h" 62 #include "en/rx_res.h" 63 #include "en/selq.h" 64 #include "lib/sd.h" 65 66 extern const struct net_device_ops mlx5e_netdev_ops; 67 struct page_pool; 68 69 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) 70 #define MLX5E_METADATA_ETHER_LEN 8 71 72 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 73 74 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) 75 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) 76 77 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE 78 79 #define MLX5_RX_HEADROOM NET_SKB_PAD 80 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ 81 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 82 83 #define MLX5E_RX_MAX_HEAD (256) 84 #define MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE (8) 85 #define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9) 86 #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE) 87 #define MLX5E_SHAMPO_LOG_WQ_HEADER_PER_PAGE (PAGE_SHIFT - MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE) 88 #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE_SHIFT (6) 89 #define MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT (12) 90 #define MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE (16) 91 #define MLX5E_SHAMPO_WQ_RESRV_SIZE BIT(MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE) 92 93 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ 94 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ 95 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ 96 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) 97 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \ 98 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD)) 99 100 /* Keep in sync with mlx5e_mpwrq_log_wqe_sz. 101 * These are theoretical maximums, which can be further restricted by 102 * capabilities. These values are used for static resource allocations and 103 * sanity checks. 104 * MLX5_SEND_WQE_MAX_SIZE is a bit bigger than the maximum cacheline-aligned WQE 105 * size actually used at runtime, but it's not a problem when calculating static 106 * array sizes. 107 */ 108 #define MLX5_UMR_MAX_FLEX_SPACE \ 109 (ALIGN_DOWN(MLX5_SEND_WQE_MAX_SIZE - sizeof(struct mlx5e_umr_wqe), \ 110 MLX5_UMR_FLEX_ALIGNMENT)) 111 #define MLX5_MPWRQ_MAX_PAGES_PER_WQE \ 112 rounddown_pow_of_two(MLX5_UMR_MAX_FLEX_SPACE / sizeof(struct mlx5_mtt)) 113 114 #define MLX5E_MAX_RQ_NUM_MTTS \ 115 (ALIGN_DOWN(U16_MAX, 4) * 2) /* Fits into u16 and aligned by WQEBB. */ 116 #define MLX5E_MAX_RQ_NUM_KSMS (U16_MAX - 1) /* So that num_ksms fits into u16. */ 117 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) 118 119 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) 120 #define MLX5E_LOG_MAX_RX_WQE_BULK \ 121 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) 122 123 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 124 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 125 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd 126 127 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) 128 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 129 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd 130 131 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 132 133 #define MLX5E_DEFAULT_LRO_TIMEOUT 32 134 #define MLX5E_DEFAULT_SHAMPO_TIMEOUT 1024 135 136 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 137 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 138 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 139 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 140 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 141 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 142 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 143 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 144 145 #define MLX5E_MIN_NUM_CHANNELS 0x1 146 #define MLX5E_MAX_NUM_CHANNELS 256 147 #define MLX5E_TX_CQ_POLL_BUDGET 128 148 #define MLX5E_TX_XSK_POLL_BUDGET 64 149 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ 150 151 #define mlx5e_state_dereference(priv, p) \ 152 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock)) 153 154 enum mlx5e_devcom_events { 155 MPV_DEVCOM_MASTER_UP, 156 MPV_DEVCOM_MASTER_DOWN, 157 MPV_DEVCOM_IPSEC_MASTER_UP, 158 MPV_DEVCOM_IPSEC_MASTER_DOWN, 159 }; 160 161 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev) 162 { 163 if (mlx5_lag_is_lacp_owner(mdev)) 164 return 1; 165 166 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS); 167 } 168 169 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) 170 { 171 switch (wq_type) { 172 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 173 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, 174 wq_size / 2); 175 default: 176 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, 177 wq_size / 2); 178 } 179 } 180 181 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */ 182 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) 183 { 184 return is_kdump_kernel() ? 185 MLX5E_MIN_NUM_CHANNELS : 186 min3(mlx5_comp_vectors_max(mdev), (u32)MLX5E_MAX_NUM_CHANNELS, 187 (u32)(1 << MLX5_CAP_GEN(mdev, log_max_rqt_size))); 188 } 189 190 /* The maximum WQE size can be retrieved by max_wqe_sz_sq in 191 * bytes units. Driver hardens the limitation to 1KB (16 192 * WQEBBs), unless firmware capability is stricter. 193 */ 194 static inline u8 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev) 195 { 196 BUILD_BUG_ON(MLX5_SEND_WQE_MAX_WQEBBS > U8_MAX); 197 198 return (u8)min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS, 199 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB); 200 } 201 202 static inline u8 mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev *mdev) 203 { 204 /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS. 205 * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16, 206 * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64) 207 * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower 208 * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be 209 * cache-aligned. 210 */ 211 u8 wqebbs = mlx5e_get_max_sq_wqebbs(mdev); 212 213 wqebbs = min_t(u8, wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1); 214 #if L1_CACHE_BYTES >= 128 215 wqebbs = ALIGN_DOWN(wqebbs, 2); 216 #endif 217 return wqebbs; 218 } 219 220 struct mlx5e_tx_wqe { 221 struct mlx5_wqe_ctrl_seg ctrl; 222 struct mlx5_wqe_eth_seg eth; 223 struct mlx5_wqe_data_seg data[]; 224 }; 225 226 struct mlx5e_rx_wqe_ll { 227 struct mlx5_wqe_srq_next_seg next; 228 struct mlx5_wqe_data_seg data[]; 229 }; 230 231 struct mlx5e_rx_wqe_cyc { 232 DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, data); 233 }; 234 235 struct mlx5e_umr_wqe_hdr { 236 struct mlx5_wqe_ctrl_seg ctrl; 237 struct mlx5_wqe_umr_ctrl_seg uctrl; 238 struct mlx5_mkey_seg mkc; 239 }; 240 241 struct mlx5e_umr_wqe { 242 struct mlx5e_umr_wqe_hdr hdr; 243 union { 244 DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts); 245 DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms); 246 DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms); 247 }; 248 }; 249 static_assert(offsetof(struct mlx5e_umr_wqe, inline_mtts) == sizeof(struct mlx5e_umr_wqe_hdr), 250 "struct members should be included in struct mlx5e_umr_wqe_hdr, not in struct mlx5e_umr_wqe"); 251 252 enum mlx5e_priv_flag { 253 MLX5E_PFLAG_RX_CQE_BASED_MODER, 254 MLX5E_PFLAG_TX_CQE_BASED_MODER, 255 MLX5E_PFLAG_RX_CQE_COMPRESS, 256 MLX5E_PFLAG_RX_STRIDING_RQ, 257 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, 258 MLX5E_PFLAG_XDP_TX_MPWQE, 259 MLX5E_PFLAG_SKB_TX_MPWQE, 260 MLX5E_PFLAG_TX_PORT_TS, 261 MLX5E_NUM_PFLAGS, /* Keep last */ 262 }; 263 264 #define MLX5E_SET_PFLAG(params, pflag, enable) \ 265 do { \ 266 if (enable) \ 267 (params)->pflags |= BIT(pflag); \ 268 else \ 269 (params)->pflags &= ~(BIT(pflag)); \ 270 } while (0) 271 272 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag)))) 273 274 enum packet_merge { 275 MLX5E_PACKET_MERGE_NONE, 276 MLX5E_PACKET_MERGE_LRO, 277 MLX5E_PACKET_MERGE_SHAMPO, 278 }; 279 280 struct mlx5e_packet_merge_param { 281 enum packet_merge type; 282 u32 timeout; 283 }; 284 285 struct mlx5e_params { 286 u8 log_sq_size; 287 u8 rq_wq_type; 288 u8 log_rq_mtu_frames; 289 u16 num_channels; 290 struct { 291 u16 mode; 292 u8 num_tc; 293 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE]; 294 struct { 295 u64 max_rate[TC_MAX_QUEUE]; 296 u32 hw_id[TC_MAX_QUEUE]; 297 } channel; 298 } mqprio; 299 bool rx_cqe_compress_def; 300 struct dim_cq_moder rx_cq_moderation; 301 struct dim_cq_moder tx_cq_moderation; 302 struct mlx5e_packet_merge_param packet_merge; 303 u8 tx_min_inline_mode; 304 bool vlan_strip_disable; 305 bool scatter_fcs_en; 306 bool rx_dim_enabled; 307 bool tx_dim_enabled; 308 bool rx_moder_use_cqe_mode; 309 bool tx_moder_use_cqe_mode; 310 u32 pflags; 311 struct bpf_prog *xdp_prog; 312 struct mlx5e_xsk *xsk; 313 unsigned int sw_mtu; 314 int hard_mtu; 315 bool ptp_rx; 316 __be32 terminate_lkey_be; 317 }; 318 319 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params) 320 { 321 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ? 322 params->mqprio.num_tc : 1; 323 } 324 325 /* Keep this enum consistent with the corresponding strings array 326 * declared in en/reporter_rx.c 327 */ 328 enum { 329 MLX5E_RQ_STATE_ENABLED = 0, 330 MLX5E_RQ_STATE_RECOVERING, 331 MLX5E_RQ_STATE_DIM, 332 MLX5E_RQ_STATE_NO_CSUM_COMPLETE, 333 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */ 334 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */ 335 MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */ 336 MLX5E_RQ_STATE_MINI_CQE_ENHANCED, /* set when enhanced mini_cqe_cap is used */ 337 MLX5E_RQ_STATE_XSK, /* set to indicate an xsk rq */ 338 MLX5E_NUM_RQ_STATES, /* Must be kept last */ 339 }; 340 341 struct mlx5e_cq { 342 /* data path - accessed per cqe */ 343 struct mlx5_cqwq wq; 344 345 /* data path - accessed per napi poll */ 346 u16 event_ctr; 347 struct napi_struct *napi; 348 struct mlx5_uars_page *uar; 349 struct mlx5_core_cq mcq; 350 struct mlx5e_ch_stats *ch_stats; 351 352 /* control */ 353 struct net_device *netdev; 354 struct mlx5_core_dev *mdev; 355 struct workqueue_struct *workqueue; 356 struct mlx5_wq_ctrl wq_ctrl; 357 } ____cacheline_aligned_in_smp; 358 359 struct mlx5e_cq_decomp { 360 /* cqe decompression */ 361 struct mlx5_cqe64 title; 362 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; 363 u8 mini_arr_idx; 364 u16 left; 365 u16 wqe_counter; 366 bool last_cqe_title; 367 } ____cacheline_aligned_in_smp; 368 369 enum mlx5e_dma_map_type { 370 MLX5E_DMA_MAP_SINGLE, 371 MLX5E_DMA_MAP_PAGE 372 }; 373 374 struct mlx5e_sq_dma { 375 dma_addr_t addr; 376 u32 size; 377 enum mlx5e_dma_map_type type; 378 }; 379 380 /* Keep this enum consistent with the corresponding strings array 381 * declared in en/reporter_tx.c 382 */ 383 enum { 384 MLX5E_SQ_STATE_ENABLED = 0, 385 MLX5E_SQ_STATE_MPWQE, 386 MLX5E_SQ_STATE_RECOVERING, 387 MLX5E_SQ_STATE_IPSEC, 388 MLX5E_SQ_STATE_DIM, 389 MLX5E_SQ_STATE_PENDING_XSK_TX, 390 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, 391 MLX5E_NUM_SQ_STATES, /* Must be kept last */ 392 }; 393 394 struct mlx5e_tx_mpwqe { 395 /* Current MPWQE session */ 396 struct mlx5e_tx_wqe *wqe; 397 u32 bytes_count; 398 u8 ds_count; 399 u8 ds_count_max; 400 u8 pkt_count; 401 u8 inline_on; 402 }; 403 404 struct mlx5e_skb_fifo { 405 struct sk_buff **fifo; 406 u16 *pc; 407 u16 *cc; 408 u16 mask; 409 }; 410 411 struct mlx5e_ptpsq; 412 413 struct mlx5e_txqsq { 414 /* data path */ 415 416 /* dirtied @completion */ 417 u16 cc; 418 u16 skb_fifo_cc; 419 u32 dma_fifo_cc; 420 struct dim *dim; /* Adaptive Moderation */ 421 422 /* dirtied @xmit */ 423 u16 pc ____cacheline_aligned_in_smp; 424 u16 skb_fifo_pc; 425 u32 dma_fifo_pc; 426 struct mlx5e_tx_mpwqe mpwqe; 427 428 struct mlx5e_cq cq; 429 430 /* read only */ 431 struct mlx5_wq_cyc wq; 432 u32 dma_fifo_mask; 433 struct mlx5e_sq_stats *stats; 434 struct { 435 struct mlx5e_sq_dma *dma_fifo; 436 struct mlx5e_skb_fifo skb_fifo; 437 struct mlx5e_tx_wqe_info *wqe_info; 438 } db; 439 void __iomem *uar_map; 440 struct netdev_queue *txq; 441 u32 sqn; 442 u16 stop_room; 443 u8 max_sq_mpw_wqebbs; 444 u8 min_inline_mode; 445 struct device *pdev; 446 __be32 mkey_be; 447 unsigned long state; 448 unsigned int hw_mtu; 449 struct mlx5_clock *clock; 450 struct net_device *netdev; 451 struct mlx5_core_dev *mdev; 452 struct mlx5e_channel *channel; 453 struct mlx5e_priv *priv; 454 455 /* control path */ 456 struct mlx5_wq_ctrl wq_ctrl; 457 int ch_ix; 458 int txq_ix; 459 u32 rate_limit; 460 struct work_struct recover_work; 461 struct mlx5e_ptpsq *ptpsq; 462 cqe_ts_to_ns ptp_cyc2time; 463 } ____cacheline_aligned_in_smp; 464 465 struct mlx5e_xdp_info_fifo { 466 union mlx5e_xdp_info *xi; 467 u32 *cc; 468 u32 *pc; 469 u32 mask; 470 }; 471 472 struct mlx5e_xdpsq; 473 struct mlx5e_xmit_data; 474 struct xsk_tx_metadata; 475 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *); 476 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *, 477 struct mlx5e_xmit_data *, 478 int, 479 struct xsk_tx_metadata *); 480 481 struct mlx5e_xdpsq { 482 /* data path */ 483 484 /* dirtied @completion */ 485 u32 xdpi_fifo_cc; 486 u16 cc; 487 488 /* dirtied @xmit */ 489 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp; 490 u16 pc; 491 struct mlx5_wqe_ctrl_seg *doorbell_cseg; 492 struct mlx5e_tx_mpwqe mpwqe; 493 494 struct mlx5e_cq cq; 495 496 /* read only */ 497 struct xsk_buff_pool *xsk_pool; 498 struct mlx5_wq_cyc wq; 499 struct mlx5e_xdpsq_stats *stats; 500 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check; 501 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame; 502 struct { 503 struct mlx5e_xdp_wqe_info *wqe_info; 504 struct mlx5e_xdp_info_fifo xdpi_fifo; 505 } db; 506 void __iomem *uar_map; 507 u32 sqn; 508 struct device *pdev; 509 __be32 mkey_be; 510 u16 stop_room; 511 u8 max_sq_mpw_wqebbs; 512 u8 min_inline_mode; 513 unsigned long state; 514 unsigned int hw_mtu; 515 516 /* control path */ 517 struct mlx5_wq_ctrl wq_ctrl; 518 struct mlx5e_channel *channel; 519 } ____cacheline_aligned_in_smp; 520 521 struct mlx5e_xdp_buff { 522 struct xdp_buff xdp; 523 struct mlx5_cqe64 *cqe; 524 struct mlx5e_rq *rq; 525 }; 526 527 struct mlx5e_ktls_resync_resp; 528 529 struct mlx5e_icosq { 530 /* data path */ 531 u16 cc; 532 u16 pc; 533 534 struct mlx5_wqe_ctrl_seg *doorbell_cseg; 535 struct mlx5e_cq cq; 536 537 /* write@xmit, read@completion */ 538 struct { 539 struct mlx5e_icosq_wqe_info *wqe_info; 540 } db; 541 542 /* read only */ 543 struct mlx5_wq_cyc wq; 544 void __iomem *uar_map; 545 u32 sqn; 546 u16 reserved_room; 547 unsigned long state; 548 struct mlx5e_ktls_resync_resp *ktls_resync; 549 550 /* control path */ 551 struct mlx5_wq_ctrl wq_ctrl; 552 struct mlx5e_channel *channel; 553 554 struct work_struct recover_work; 555 } ____cacheline_aligned_in_smp; 556 557 struct mlx5e_frag_page { 558 netmem_ref netmem; 559 u16 frags; 560 }; 561 562 enum mlx5e_wqe_frag_flag { 563 MLX5E_WQE_FRAG_LAST_IN_PAGE, 564 MLX5E_WQE_FRAG_SKIP_RELEASE, 565 }; 566 567 struct mlx5e_wqe_frag_info { 568 union { 569 struct mlx5e_frag_page *frag_page; 570 struct xdp_buff **xskp; 571 }; 572 u32 offset; 573 u8 flags; 574 }; 575 576 union mlx5e_alloc_units { 577 DECLARE_FLEX_ARRAY(struct mlx5e_frag_page, frag_pages); 578 DECLARE_FLEX_ARRAY(struct page *, pages); 579 DECLARE_FLEX_ARRAY(struct xdp_buff *, xsk_buffs); 580 }; 581 582 struct mlx5e_mpw_info { 583 u16 consumed_strides; 584 DECLARE_BITMAP(skip_release_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE); 585 struct mlx5e_frag_page linear_page; 586 union mlx5e_alloc_units alloc_units; 587 }; 588 589 #define MLX5E_MAX_RX_FRAGS 4 590 591 struct mlx5e_rq; 592 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); 593 typedef struct sk_buff * 594 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 595 struct mlx5_cqe64 *cqe, u16 cqe_bcnt, 596 u32 head_offset, u32 page_idx); 597 typedef struct sk_buff * 598 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi, 599 struct mlx5_cqe64 *cqe, u32 cqe_bcnt); 600 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); 601 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); 602 typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool); 603 604 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk); 605 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params); 606 607 enum mlx5e_rq_flag { 608 MLX5E_RQ_FLAG_XDP_XMIT, 609 MLX5E_RQ_FLAG_XDP_REDIRECT, 610 }; 611 612 struct mlx5e_rq_frag_info { 613 int frag_size; 614 int frag_stride; 615 }; 616 617 struct mlx5e_rq_frags_info { 618 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; 619 u8 num_frags; 620 u8 log_num_frags; 621 u16 wqe_bulk; 622 u16 refill_unit; 623 u8 wqe_index_mask; 624 }; 625 626 struct mlx5e_dma_info { 627 dma_addr_t addr; 628 union { 629 struct mlx5e_frag_page *frag_page; 630 struct page *page; 631 }; 632 }; 633 634 struct mlx5e_shampo_hd { 635 struct mlx5e_frag_page *pages; 636 u32 hd_per_wq; 637 u32 hd_per_page; 638 u16 hd_per_wqe; 639 u8 log_hd_per_page; 640 u8 log_hd_entry_size; 641 unsigned long *bitmap; 642 u16 pi; 643 u16 ci; 644 __be32 mkey_be; 645 }; 646 647 struct mlx5e_hw_gro_data { 648 struct sk_buff *skb; 649 struct flow_keys fk; 650 int second_ip_id; 651 }; 652 653 enum mlx5e_mpwrq_umr_mode { 654 MLX5E_MPWRQ_UMR_MODE_ALIGNED, 655 MLX5E_MPWRQ_UMR_MODE_UNALIGNED, 656 MLX5E_MPWRQ_UMR_MODE_OVERSIZED, 657 MLX5E_MPWRQ_UMR_MODE_TRIPLE, 658 }; 659 660 struct mlx5e_rq { 661 /* data path */ 662 union { 663 struct { 664 struct mlx5_wq_cyc wq; 665 struct mlx5e_wqe_frag_info *frags; 666 union mlx5e_alloc_units *alloc_units; 667 struct mlx5e_rq_frags_info info; 668 mlx5e_fp_skb_from_cqe skb_from_cqe; 669 } wqe; 670 struct { 671 struct mlx5_wq_ll wq; 672 struct mlx5e_umr_wqe_hdr umr_wqe; 673 struct mlx5e_mpw_info *info; 674 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; 675 __be32 umr_mkey_be; 676 u16 num_strides; 677 u16 actual_wq_head; 678 u8 log_stride_sz; 679 u8 umr_in_progress; 680 u8 umr_last_bulk; 681 u8 umr_completed; 682 u8 min_wqe_bulk; 683 u8 page_shift; 684 u8 pages_per_wqe; 685 u8 umr_wqebbs; 686 u8 mtts_per_wqe; 687 u8 umr_mode; 688 struct mlx5e_shampo_hd *shampo; 689 } mpwqe; 690 }; 691 struct { 692 u16 headroom; 693 u32 frame0_sz; 694 u8 map_dir; /* dma map direction */ 695 } buff; 696 697 struct device *pdev; 698 struct net_device *netdev; 699 struct mlx5e_rq_stats *stats; 700 struct mlx5e_cq cq; 701 struct mlx5e_cq_decomp cqd; 702 struct kernel_hwtstamp_config *hwtstamp_config; 703 struct mlx5_clock *clock; 704 struct mlx5e_icosq *icosq; 705 struct mlx5e_priv *priv; 706 707 struct mlx5e_hw_gro_data *hw_gro_data; 708 709 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 710 mlx5e_fp_post_rx_wqes post_wqes; 711 mlx5e_fp_dealloc_wqe dealloc_wqe; 712 713 unsigned long state; 714 int ix; 715 unsigned int hw_mtu; 716 717 struct dim *dim; /* Dynamic Interrupt Moderation */ 718 719 /* XDP */ 720 struct bpf_prog __rcu *xdp_prog; 721 struct mlx5e_xdpsq *xdpsq; 722 DECLARE_BITMAP(flags, 8); 723 724 /* page pools */ 725 struct page_pool *page_pool; 726 struct page_pool *hd_page_pool; 727 728 struct mlx5e_xdp_buff mxbuf; 729 730 /* AF_XDP zero-copy */ 731 struct xsk_buff_pool *xsk_pool; 732 733 struct work_struct recover_work; 734 struct work_struct rx_timeout_work; 735 736 /* control */ 737 struct mlx5_wq_ctrl wq_ctrl; 738 __be32 mkey_be; 739 u8 wq_type; 740 u32 rqn; 741 struct mlx5_core_dev *mdev; 742 struct mlx5e_channel *channel; 743 struct mlx5e_dma_info wqe_overflow; 744 745 /* XDP read-mostly */ 746 struct xdp_rxq_info xdp_rxq; 747 cqe_ts_to_ns ptp_cyc2time; 748 } ____cacheline_aligned_in_smp; 749 750 enum mlx5e_channel_state { 751 MLX5E_CHANNEL_STATE_XSK, 752 MLX5E_CHANNEL_NUM_STATES 753 }; 754 755 struct mlx5e_channel { 756 /* data path */ 757 struct mlx5e_rq rq; 758 struct mlx5e_xdpsq rq_xdpsq; 759 struct mlx5e_txqsq sq[MLX5_MAX_NUM_TC]; 760 struct mlx5e_icosq icosq; /* internal control operations */ 761 struct mlx5e_txqsq __rcu * __rcu *qos_sqs; 762 bool xdp; 763 struct napi_struct napi; 764 struct device *pdev; 765 struct net_device *netdev; 766 __be32 mkey_be; 767 u16 qos_sqs_size; 768 u8 num_tc; 769 u8 lag_port; 770 771 /* XDP_REDIRECT */ 772 struct mlx5e_xdpsq *xdpsq; 773 774 /* AF_XDP zero-copy */ 775 struct mlx5e_rq xskrq; 776 struct mlx5e_xdpsq xsksq; 777 778 /* Async ICOSQ */ 779 struct mlx5e_icosq async_icosq; 780 /* async_icosq can be accessed from any CPU - the spinlock protects it. */ 781 spinlock_t async_icosq_lock; 782 783 /* data path - accessed per napi poll */ 784 const struct cpumask *aff_mask; 785 struct mlx5e_ch_stats *stats; 786 787 /* control */ 788 struct mlx5e_priv *priv; 789 struct mlx5_core_dev *mdev; 790 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES); 791 int ix; 792 int vec_ix; 793 int sd_ix; 794 int cpu; 795 struct mlx5_sq_bfreg *bfreg; 796 /* Sync between icosq recovery and XSK enable/disable. */ 797 struct mutex icosq_recovery_lock; 798 799 /* coalescing configuration */ 800 struct dim_cq_moder rx_cq_moder; 801 struct dim_cq_moder tx_cq_moder; 802 }; 803 804 struct mlx5e_ptp; 805 806 struct mlx5e_channels { 807 struct mlx5e_channel **c; 808 struct mlx5e_ptp *ptp; 809 unsigned int num; 810 struct mlx5e_params params; 811 }; 812 813 struct mlx5e_channel_stats { 814 struct mlx5e_ch_stats ch; 815 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC]; 816 struct mlx5e_rq_stats rq; 817 struct mlx5e_rq_stats xskrq; 818 struct mlx5e_xdpsq_stats rq_xdpsq; 819 struct mlx5e_xdpsq_stats xdpsq; 820 struct mlx5e_xdpsq_stats xsksq; 821 } ____cacheline_aligned_in_smp; 822 823 struct mlx5e_ptp_stats { 824 struct mlx5e_ch_stats ch; 825 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC]; 826 struct mlx5e_ptp_cq_stats cq[MLX5_MAX_NUM_TC]; 827 struct mlx5e_rq_stats rq; 828 } ____cacheline_aligned_in_smp; 829 830 enum { 831 MLX5E_STATE_OPENED, 832 MLX5E_STATE_DESTROYING, 833 MLX5E_STATE_XDP_TX_ENABLED, 834 MLX5E_STATE_XDP_ACTIVE, 835 MLX5E_STATE_CHANNELS_ACTIVE, 836 }; 837 838 struct mlx5e_modify_sq_param { 839 int curr_state; 840 int next_state; 841 int rl_update; 842 int rl_index; 843 bool qos_update; 844 u16 qos_queue_group_id; 845 }; 846 847 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) 848 struct mlx5e_hv_vhca_stats_agent { 849 struct mlx5_hv_vhca_agent *agent; 850 struct delayed_work work; 851 u16 delay; 852 void *buf; 853 }; 854 #endif 855 856 struct mlx5e_xsk { 857 /* XSK buffer pools are stored separately from channels, 858 * because we don't want to lose them when channels are 859 * recreated. The kernel also stores buffer pool, but it doesn't 860 * distinguish between zero-copy and non-zero-copy UMEMs, so 861 * rely on our mechanism. 862 */ 863 struct xsk_buff_pool **pools; 864 u16 refcnt; 865 bool ever_used; 866 }; 867 868 /* Temporary storage for variables that are allocated when struct mlx5e_priv is 869 * initialized, and used where we can't allocate them because that functions 870 * must not fail. Use with care and make sure the same variable is not used 871 * simultaneously by multiple users. 872 */ 873 struct mlx5e_scratchpad { 874 cpumask_var_t cpumask; 875 }; 876 877 struct mlx5e_trap; 878 struct mlx5e_htb; 879 880 struct mlx5e_priv { 881 /* priv data path fields - start */ 882 struct mlx5e_selq selq; 883 struct mlx5e_txqsq **txq2sq; 884 struct mlx5e_sq_stats **txq2sq_stats; 885 886 #ifdef CONFIG_MLX5_CORE_EN_DCB 887 struct mlx5e_dcbx_dp dcbx_dp; 888 #endif 889 /* priv data path fields - end */ 890 891 unsigned long state; 892 struct mutex state_lock; /* Protects Interface state */ 893 struct mlx5e_rq drop_rq; 894 895 struct mlx5e_channels channels; 896 struct mlx5e_rx_res *rx_res; 897 u32 *tx_rates; 898 899 struct mlx5e_flow_steering *fs; 900 901 struct workqueue_struct *wq; 902 struct work_struct update_carrier_work; 903 struct work_struct set_rx_mode_work; 904 struct work_struct tx_timeout_work; 905 struct work_struct update_stats_work; 906 struct work_struct monitor_counters_work; 907 struct mlx5_nb monitor_counters_nb; 908 909 struct mlx5_core_dev *mdev; 910 struct net_device *netdev; 911 struct mlx5e_trap *en_trap; 912 struct mlx5e_stats stats; 913 struct mlx5e_channel_stats **channel_stats; 914 struct mlx5e_channel_stats trap_stats; 915 struct mlx5e_ptp_stats ptp_stats; 916 struct mlx5e_sq_stats **htb_qos_sq_stats; 917 u16 htb_max_qos_sqs; 918 u16 stats_nch; 919 u16 max_nch; 920 u8 max_opened_tc; 921 bool tx_ptp_opened; 922 bool rx_ptp_opened; 923 struct kernel_hwtstamp_config hwtstamp_config; 924 u16 q_counter[MLX5_SD_MAX_GROUP_SZ]; 925 u16 drop_rq_q_counter; 926 struct notifier_block events_nb; 927 struct notifier_block blocking_events_nb; 928 929 struct mlx5e_pcie_cong_event *cong_event; 930 931 struct udp_tunnel_nic_info nic_info; 932 #ifdef CONFIG_MLX5_CORE_EN_DCB 933 struct mlx5e_dcbx dcbx; 934 #endif 935 936 const struct mlx5e_profile *profile; 937 void *ppriv; 938 #ifdef CONFIG_MLX5_MACSEC 939 struct mlx5e_macsec *macsec; 940 #endif 941 #ifdef CONFIG_MLX5_EN_IPSEC 942 struct mlx5e_ipsec *ipsec; 943 #endif 944 #ifdef CONFIG_MLX5_EN_PSP 945 struct mlx5e_psp *psp; 946 #endif 947 #ifdef CONFIG_MLX5_EN_TLS 948 struct mlx5e_tls *tls; 949 #endif 950 struct devlink_health_reporter *tx_reporter; 951 struct devlink_health_reporter *rx_reporter; 952 struct mlx5e_xsk xsk; 953 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) 954 struct mlx5e_hv_vhca_stats_agent stats_agent; 955 #endif 956 struct mlx5e_scratchpad scratchpad; 957 struct mlx5e_htb *htb; 958 struct mlx5e_mqprio_rl *mqprio_rl; 959 struct dentry *dfs_root; 960 struct mlx5_devcom_comp_dev *devcom; 961 struct ethtool_fec_hist_range *fec_ranges; 962 }; 963 964 struct mlx5e_dev { 965 struct mlx5e_priv *priv; 966 struct devlink_port dl_port; 967 }; 968 969 struct mlx5e_rx_handlers { 970 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 971 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; 972 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo; 973 }; 974 975 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic; 976 977 enum mlx5e_profile_feature { 978 MLX5E_PROFILE_FEATURE_PTP_RX, 979 MLX5E_PROFILE_FEATURE_PTP_TX, 980 MLX5E_PROFILE_FEATURE_QOS_HTB, 981 MLX5E_PROFILE_FEATURE_FS_VLAN, 982 MLX5E_PROFILE_FEATURE_FS_TC, 983 }; 984 985 struct mlx5e_profile { 986 int (*init)(struct mlx5_core_dev *mdev, 987 struct net_device *netdev); 988 void (*cleanup)(struct mlx5e_priv *priv); 989 int (*init_rx)(struct mlx5e_priv *priv); 990 void (*cleanup_rx)(struct mlx5e_priv *priv); 991 int (*init_tx)(struct mlx5e_priv *priv); 992 void (*cleanup_tx)(struct mlx5e_priv *priv); 993 void (*enable)(struct mlx5e_priv *priv); 994 void (*disable)(struct mlx5e_priv *priv); 995 int (*update_rx)(struct mlx5e_priv *priv); 996 void (*update_stats)(struct mlx5e_priv *priv); 997 void (*update_carrier)(struct mlx5e_priv *priv); 998 int (*max_nch_limit)(struct mlx5_core_dev *mdev); 999 u32 (*get_tisn)(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv, 1000 u8 lag_port, u8 tc); 1001 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv); 1002 mlx5e_stats_grp_t *stats_grps; 1003 const struct mlx5e_rx_handlers *rx_handlers; 1004 int max_tc; 1005 u32 features; 1006 }; 1007 1008 u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev, 1009 struct mlx5e_priv *priv, 1010 const struct mlx5e_profile *profile, 1011 u8 lag_port, u8 tc); 1012 1013 #define mlx5e_profile_feature_cap(profile, feature) \ 1014 ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature)) 1015 1016 void mlx5e_build_ptys2ethtool_map(void); 1017 1018 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift, 1019 enum mlx5e_mpwrq_umr_mode umr_mode); 1020 1021 void mlx5e_shampo_fill_umr(struct mlx5e_rq *rq, int len); 1022 void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq); 1023 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); 1024 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s); 1025 1026 int mlx5e_self_test_num(struct mlx5e_priv *priv); 1027 int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data); 1028 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, 1029 u64 *buf); 1030 void mlx5e_set_rx_mode_work(struct work_struct *work); 1031 1032 int mlx5e_hwtstamp_set(struct mlx5e_priv *priv, 1033 struct kernel_hwtstamp_config *config, 1034 struct netlink_ext_ack *extack); 1035 int mlx5e_hwtstamp_get(struct mlx5e_priv *priv, 1036 struct kernel_hwtstamp_config *config); 1037 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter); 1038 1039 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, 1040 u16 vid); 1041 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, 1042 u16 vid); 1043 void mlx5e_timestamp_init(struct mlx5e_priv *priv); 1044 1045 struct mlx5e_xsk_param; 1046 1047 struct mlx5e_rq_param; 1048 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param, 1049 struct mlx5e_xsk_param *xsk, int node, u16 q_counter, 1050 struct mlx5e_rq *rq); 1051 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */ 1052 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time); 1053 void mlx5e_close_rq(struct mlx5e_rq *rq); 1054 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param, u16 q_counter); 1055 void mlx5e_destroy_rq(struct mlx5e_rq *rq); 1056 1057 bool mlx5e_reset_rx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode, 1058 bool dim_enabled); 1059 bool mlx5e_reset_rx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode, 1060 bool dim_enabled, bool keep_dim_state); 1061 1062 struct mlx5e_sq_param; 1063 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, 1064 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, 1065 struct mlx5e_xdpsq *sq, bool is_redirect); 1066 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq); 1067 1068 struct mlx5e_create_cq_param { 1069 struct net_device *netdev; 1070 struct workqueue_struct *wq; 1071 struct napi_struct *napi; 1072 struct mlx5e_ch_stats *ch_stats; 1073 int node; 1074 int ix; 1075 struct mlx5_uars_page *uar; 1076 }; 1077 1078 struct mlx5e_cq_param; 1079 int mlx5e_open_cq(struct mlx5_core_dev *mdev, struct dim_cq_moder moder, 1080 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp, 1081 struct mlx5e_cq *cq); 1082 void mlx5e_close_cq(struct mlx5e_cq *cq); 1083 int mlx5e_modify_cq_period_mode(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, 1084 u8 cq_period_mode); 1085 int mlx5e_modify_cq_moderation(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, 1086 u16 cq_period, u16 cq_max_count, u8 cq_period_mode); 1087 1088 int mlx5e_open_locked(struct net_device *netdev); 1089 int mlx5e_close_locked(struct net_device *netdev); 1090 1091 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c); 1092 void mlx5e_trigger_napi_sched(struct napi_struct *napi); 1093 1094 int mlx5e_open_channels(struct mlx5e_priv *priv, 1095 struct mlx5e_channels *chs); 1096 void mlx5e_close_channels(struct mlx5e_channels *chs); 1097 1098 /* Function pointer to be used to modify HW or kernel settings while 1099 * switching channels 1100 */ 1101 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context); 1102 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \ 1103 int fn##_ctx(struct mlx5e_priv *priv, void *context) \ 1104 { \ 1105 return fn(priv); \ 1106 } 1107 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv); 1108 int mlx5e_safe_switch_params(struct mlx5e_priv *priv, 1109 struct mlx5e_params *new_params, 1110 mlx5e_fp_preactivate preactivate, 1111 void *context, bool reset); 1112 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv); 1113 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context); 1114 int mlx5e_update_tc_and_tx_queues_ctx(struct mlx5e_priv *priv, void *context); 1115 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); 1116 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); 1117 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx); 1118 1119 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state); 1120 void mlx5e_activate_rq(struct mlx5e_rq *rq); 1121 void mlx5e_deactivate_rq(struct mlx5e_rq *rq); 1122 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq); 1123 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq); 1124 1125 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, 1126 struct mlx5e_modify_sq_param *p); 1127 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix, 1128 struct mlx5e_params *params, struct mlx5e_sq_param *param, 1129 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, 1130 struct mlx5e_sq_stats *sq_stats); 1131 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq); 1132 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq); 1133 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq); 1134 void mlx5e_tx_disable_queue(struct netdev_queue *txq); 1135 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa); 1136 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq); 1137 struct mlx5e_create_sq_param; 1138 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, 1139 struct mlx5e_sq_param *param, 1140 struct mlx5e_create_sq_param *csp, 1141 u16 qos_queue_group_id, 1142 u32 *sqn); 1143 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work); 1144 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq); 1145 1146 bool mlx5e_reset_tx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode, 1147 bool dim_enabled); 1148 bool mlx5e_reset_tx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode, 1149 bool dim_enabled, bool keep_dim_state); 1150 1151 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev) 1152 { 1153 return MLX5_CAP_ETH(mdev, swp) && 1154 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso); 1155 } 1156 1157 extern const struct ethtool_ops mlx5e_ethtool_ops; 1158 1159 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey); 1160 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_tises); 1161 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); 1162 int mlx5e_modify_tirs_lb(struct mlx5_core_dev *mdev, bool enable_uc_lb, 1163 bool enable_mc_lb); 1164 int mlx5e_refresh_tirs(struct mlx5_core_dev *mdev, bool enable_uc_lb, 1165 bool enable_mc_lb); 1166 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc); 1167 1168 /* common netdev helpers */ 1169 void mlx5e_create_q_counters(struct mlx5e_priv *priv); 1170 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv); 1171 int mlx5e_open_drop_rq(struct mlx5e_priv *priv, 1172 struct mlx5e_rq *drop_rq); 1173 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq); 1174 1175 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn); 1176 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); 1177 1178 void mlx5e_update_carrier(struct mlx5e_priv *priv); 1179 int mlx5e_close(struct net_device *netdev); 1180 int mlx5e_open(struct net_device *netdev); 1181 1182 void mlx5e_queue_update_stats(struct mlx5e_priv *priv); 1183 1184 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv); 1185 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context); 1186 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, 1187 mlx5e_fp_preactivate preactivate); 1188 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv); 1189 1190 /* ethtool helpers */ 1191 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, 1192 struct ethtool_drvinfo *drvinfo); 1193 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, 1194 u32 stringset, u8 *data); 1195 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); 1196 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, 1197 struct ethtool_stats *stats, u64 *data); 1198 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, 1199 struct ethtool_ringparam *param, 1200 struct kernel_ethtool_ringparam *kernel_param); 1201 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, 1202 struct ethtool_ringparam *param, 1203 struct netlink_ext_ack *extack); 1204 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, 1205 struct ethtool_channels *ch); 1206 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, 1207 struct ethtool_channels *ch); 1208 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, 1209 struct ethtool_coalesce *coal, 1210 struct kernel_ethtool_coalesce *kernel_coal, 1211 struct netlink_ext_ack *extack); 1212 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, 1213 struct ethtool_coalesce *coal, 1214 struct kernel_ethtool_coalesce *kernel_coal, 1215 struct netlink_ext_ack *extack); 1216 int mlx5e_get_per_queue_coalesce(struct net_device *dev, u32 queue, 1217 struct ethtool_coalesce *coal); 1218 int mlx5e_set_per_queue_coalesce(struct net_device *dev, u32 queue, 1219 struct ethtool_coalesce *coal); 1220 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv); 1221 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv); 1222 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, 1223 struct kernel_ethtool_ts_info *info); 1224 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, 1225 struct ethtool_flash *flash); 1226 1227 /* mlx5e generic netdev management API */ 1228 static inline bool 1229 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev) 1230 { 1231 return !is_kdump_kernel() && 1232 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe); 1233 } 1234 1235 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev); 1236 int mlx5e_priv_init(struct mlx5e_priv *priv, 1237 const struct mlx5e_profile *profile, 1238 struct net_device *netdev, 1239 struct mlx5_core_dev *mdev); 1240 void mlx5e_priv_cleanup(struct mlx5e_priv *priv); 1241 struct net_device * 1242 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile); 1243 int mlx5e_attach_netdev(struct mlx5e_priv *priv); 1244 void mlx5e_detach_netdev(struct mlx5e_priv *priv); 1245 void mlx5e_destroy_netdev(struct mlx5e_priv *priv); 1246 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv, 1247 const struct mlx5e_profile *new_profile, void *new_ppriv); 1248 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv); 1249 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv); 1250 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu); 1251 1252 void mlx5e_set_xdp_feature(struct mlx5e_priv *priv); 1253 netdev_features_t mlx5e_features_check(struct sk_buff *skb, 1254 struct net_device *netdev, 1255 netdev_features_t features); 1256 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features); 1257 #ifdef CONFIG_MLX5_ESWITCH 1258 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac); 1259 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate); 1260 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi); 1261 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats); 1262 #endif 1263 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey); 1264 #endif /* __MLX5_EN_H__ */ 1265