1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/crash_dump.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/mlx5/fs.h>
47 #include <linux/rhashtable.h>
48 #include <net/udp_tunnel.h>
49 #include <net/switchdev.h>
50 #include <net/psp/types.h>
51 #include <net/xdp.h>
52 #include <linux/dim.h>
53 #include <linux/bits.h>
54 #include "wq.h"
55 #include "mlx5_core.h"
56 #include "en_stats.h"
57 #include "en/dcbnl.h"
58 #include "en/fs.h"
59 #include "en/qos.h"
60 #include "lib/hv_vhca.h"
61 #include "lib/clock.h"
62 #include "en/rx_res.h"
63 #include "en/selq.h"
64 #include "lib/sd.h"
65
66 extern const struct net_device_ops mlx5e_netdev_ops;
67 struct page_pool;
68
69 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
70 #define MLX5E_METADATA_ETHER_LEN 8
71
72 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
73
74 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
75 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
76
77 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE
78
79 #define MLX5_RX_HEADROOM NET_SKB_PAD
80 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
81 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
82
83 #define MLX5E_RX_MAX_HEAD (256)
84 #define MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE (8)
85 #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE \
86 (PAGE_SIZE >> MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE)
87 #define MLX5E_SHAMPO_LOG_WQ_HEADER_PER_PAGE \
88 (PAGE_SHIFT - MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE)
89 #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE_SHIFT (6)
90 #define MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT (12)
91 #define MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE (16)
92 #define MLX5E_SHAMPO_WQ_RESRV_SIZE BIT(MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE)
93
94 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
95 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
96 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
97 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
98 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
99 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
100
101 /* Keep in sync with mlx5e_mpwrq_log_wqe_sz.
102 * These are theoretical maximums, which can be further restricted by
103 * capabilities. These values are used for static resource allocations and
104 * sanity checks.
105 * MLX5_SEND_WQE_MAX_SIZE is a bit bigger than the maximum cacheline-aligned WQE
106 * size actually used at runtime, but it's not a problem when calculating static
107 * array sizes.
108 */
109 #define MLX5_UMR_MAX_FLEX_SPACE \
110 (ALIGN_DOWN(MLX5_SEND_WQE_MAX_SIZE - sizeof(struct mlx5e_umr_wqe), \
111 MLX5_UMR_FLEX_ALIGNMENT))
112 #define MLX5_MPWRQ_MAX_PAGES_PER_WQE \
113 rounddown_pow_of_two(MLX5_UMR_MAX_FLEX_SPACE / sizeof(struct mlx5_mtt))
114
115 #define MLX5E_MAX_RQ_NUM_MTTS \
116 (ALIGN_DOWN(U16_MAX, 4) * 2) /* Fits into u16 and aligned by WQEBB. */
117 #define MLX5E_MAX_RQ_NUM_KSMS (U16_MAX - 1) /* So that num_ksms fits into u16. */
118 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
119
120 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
121 #define MLX5E_LOG_MAX_RX_WQE_BULK \
122 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
123
124 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
125 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
126 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
127
128 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
129 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
130 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
131
132 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
133
134 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
135 #define MLX5E_DEFAULT_SHAMPO_TIMEOUT 1024
136
137 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
138 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
139 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
140 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
141 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
142 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
143 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
144 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
145
146 #define MLX5E_MIN_NUM_CHANNELS 0x1
147 #define MLX5E_MAX_NUM_CHANNELS 256
148 #define MLX5E_TX_CQ_POLL_BUDGET 128
149 #define MLX5E_TX_XSK_POLL_BUDGET 64
150 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
151
152 #define mlx5e_state_dereference(priv, p) \
153 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock))
154
155 enum mlx5e_devcom_events {
156 MPV_DEVCOM_MASTER_UP,
157 MPV_DEVCOM_MASTER_DOWN,
158 MPV_DEVCOM_IPSEC_MASTER_UP,
159 MPV_DEVCOM_IPSEC_MASTER_DOWN,
160 };
161
mlx5e_get_num_lag_ports(struct mlx5_core_dev * mdev)162 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
163 {
164 if (mlx5_lag_is_lacp_owner(mdev))
165 return 1;
166
167 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
168 }
169
mlx5_min_rx_wqes(int wq_type,u32 wq_size)170 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
171 {
172 switch (wq_type) {
173 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
174 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
175 wq_size / 2);
176 default:
177 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
178 wq_size / 2);
179 }
180 }
181
182 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
183 static inline unsigned int
mlx5e_get_max_num_channels(struct mlx5_core_dev * mdev)184 mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
185 {
186 return is_kdump_kernel() ?
187 MLX5E_MIN_NUM_CHANNELS :
188 min3(mlx5_comp_vectors_max(mdev), (u32)MLX5E_MAX_NUM_CHANNELS,
189 (u32)(1 << MLX5_CAP_GEN(mdev, log_max_rqt_size)));
190 }
191
192 /* The maximum WQE size can be retrieved by max_wqe_sz_sq in
193 * bytes units. Driver hardens the limitation to 1KB (16
194 * WQEBBs), unless firmware capability is stricter.
195 */
mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev * mdev)196 static inline u8 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev)
197 {
198 BUILD_BUG_ON(MLX5_SEND_WQE_MAX_WQEBBS > U8_MAX);
199
200 return (u8)min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS,
201 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB);
202 }
203
mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev * mdev)204 static inline u8 mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev *mdev)
205 {
206 /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS.
207 * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16,
208 * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64)
209 * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower
210 * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be
211 * cache-aligned.
212 */
213 u8 wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
214
215 wqebbs = min_t(u8, wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1);
216 #if L1_CACHE_BYTES >= 128
217 wqebbs = ALIGN_DOWN(wqebbs, 2);
218 #endif
219 return wqebbs;
220 }
221
222 struct mlx5e_tx_wqe {
223 struct mlx5_wqe_ctrl_seg ctrl;
224 struct mlx5_wqe_eth_seg eth;
225 struct mlx5_wqe_data_seg data[];
226 };
227
228 struct mlx5e_rx_wqe_ll {
229 struct mlx5_wqe_srq_next_seg next;
230 struct mlx5_wqe_data_seg data[];
231 };
232
233 struct mlx5e_rx_wqe_cyc {
234 DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, data);
235 };
236
237 struct mlx5e_umr_wqe_hdr {
238 struct mlx5_wqe_ctrl_seg ctrl;
239 struct mlx5_wqe_umr_ctrl_seg uctrl;
240 struct mlx5_mkey_seg mkc;
241 };
242
243 struct mlx5e_umr_wqe {
244 struct mlx5e_umr_wqe_hdr hdr;
245 union {
246 DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts);
247 DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms);
248 DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms);
249 };
250 };
251 static_assert(offsetof(struct mlx5e_umr_wqe, inline_mtts) == sizeof(struct mlx5e_umr_wqe_hdr),
252 "struct members should be included in struct mlx5e_umr_wqe_hdr, not in struct mlx5e_umr_wqe");
253
254 enum mlx5e_priv_flag {
255 MLX5E_PFLAG_RX_CQE_BASED_MODER,
256 MLX5E_PFLAG_TX_CQE_BASED_MODER,
257 MLX5E_PFLAG_RX_CQE_COMPRESS,
258 MLX5E_PFLAG_RX_STRIDING_RQ,
259 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
260 MLX5E_PFLAG_XDP_TX_MPWQE,
261 MLX5E_PFLAG_SKB_TX_MPWQE,
262 MLX5E_PFLAG_TX_PORT_TS,
263 MLX5E_NUM_PFLAGS, /* Keep last */
264 };
265
266 #define MLX5E_SET_PFLAG(params, pflag, enable) \
267 do { \
268 if (enable) \
269 (params)->pflags |= BIT(pflag); \
270 else \
271 (params)->pflags &= ~(BIT(pflag)); \
272 } while (0)
273
274 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
275
276 enum packet_merge {
277 MLX5E_PACKET_MERGE_NONE,
278 MLX5E_PACKET_MERGE_LRO,
279 MLX5E_PACKET_MERGE_SHAMPO,
280 };
281
282 struct mlx5e_packet_merge_param {
283 enum packet_merge type;
284 u32 timeout;
285 };
286
287 struct mlx5e_params {
288 u8 log_sq_size;
289 u8 rq_wq_type;
290 u8 log_rq_mtu_frames;
291 u16 num_channels;
292 struct {
293 u16 mode;
294 u8 num_tc;
295 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE];
296 struct {
297 u64 max_rate[TC_MAX_QUEUE];
298 u32 hw_id[TC_MAX_QUEUE];
299 } channel;
300 } mqprio;
301 bool rx_cqe_compress_def;
302 struct dim_cq_moder rx_cq_moderation;
303 struct dim_cq_moder tx_cq_moderation;
304 struct mlx5e_packet_merge_param packet_merge;
305 u8 tx_min_inline_mode;
306 bool vlan_strip_disable;
307 bool scatter_fcs_en;
308 bool rx_dim_enabled;
309 bool tx_dim_enabled;
310 bool rx_moder_use_cqe_mode;
311 bool tx_moder_use_cqe_mode;
312 u32 pflags;
313 struct bpf_prog *xdp_prog;
314 struct mlx5e_xsk *xsk;
315 unsigned int sw_mtu;
316 int hard_mtu;
317 bool ptp_rx;
318 __be32 terminate_lkey_be;
319 };
320
mlx5e_get_dcb_num_tc(struct mlx5e_params * params)321 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params)
322 {
323 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ?
324 params->mqprio.num_tc : 1;
325 }
326
327 /* Keep this enum consistent with the corresponding strings array
328 * declared in en/reporter_rx.c
329 */
330 enum {
331 MLX5E_RQ_STATE_ENABLED = 0,
332 MLX5E_RQ_STATE_RECOVERING,
333 MLX5E_RQ_STATE_DIM,
334 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
335 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
336 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */
337 MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */
338 MLX5E_RQ_STATE_MINI_CQE_ENHANCED, /* set when enhanced mini_cqe_cap is used */
339 MLX5E_RQ_STATE_XSK, /* set to indicate an xsk rq */
340 MLX5E_NUM_RQ_STATES, /* Must be kept last */
341 };
342
343 struct mlx5e_cq {
344 /* data path - accessed per cqe */
345 struct mlx5_cqwq wq;
346
347 /* data path - accessed per napi poll */
348 u16 event_ctr;
349 struct napi_struct *napi;
350 struct mlx5_uars_page *uar;
351 struct mlx5_core_cq mcq;
352 struct mlx5e_ch_stats *ch_stats;
353
354 /* control */
355 struct net_device *netdev;
356 struct mlx5_core_dev *mdev;
357 struct workqueue_struct *workqueue;
358 struct mlx5_wq_ctrl wq_ctrl;
359 } ____cacheline_aligned_in_smp;
360
361 struct mlx5e_cq_decomp {
362 /* cqe decompression */
363 struct mlx5_cqe64 title;
364 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
365 u8 mini_arr_idx;
366 u16 left;
367 u16 wqe_counter;
368 bool last_cqe_title;
369 } ____cacheline_aligned_in_smp;
370
371 enum mlx5e_dma_map_type {
372 MLX5E_DMA_MAP_SINGLE,
373 MLX5E_DMA_MAP_PAGE
374 };
375
376 struct mlx5e_sq_dma {
377 dma_addr_t addr;
378 u32 size;
379 enum mlx5e_dma_map_type type;
380 };
381
382 /* Keep this enum consistent with the corresponding strings array
383 * declared in en/reporter_tx.c
384 */
385 enum {
386 MLX5E_SQ_STATE_ENABLED = 0,
387 MLX5E_SQ_STATE_MPWQE,
388 MLX5E_SQ_STATE_RECOVERING,
389 MLX5E_SQ_STATE_IPSEC,
390 MLX5E_SQ_STATE_DIM,
391 MLX5E_SQ_STATE_PENDING_XSK_TX,
392 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC,
393 MLX5E_SQ_STATE_LOCK_NEEDED,
394 MLX5E_NUM_SQ_STATES, /* Must be kept last */
395 };
396
397 struct mlx5e_tx_mpwqe {
398 /* Current MPWQE session */
399 struct mlx5e_tx_wqe *wqe;
400 u32 bytes_count;
401 u8 ds_count;
402 u8 ds_count_max;
403 u8 pkt_count;
404 u8 inline_on;
405 };
406
407 struct mlx5e_skb_fifo {
408 struct sk_buff **fifo;
409 u16 *pc;
410 u16 *cc;
411 u16 mask;
412 };
413
414 struct mlx5e_ptpsq;
415
416 struct mlx5e_txqsq {
417 /* data path */
418
419 /* dirtied @completion */
420 u16 cc;
421 u16 skb_fifo_cc;
422 u32 dma_fifo_cc;
423 struct dim *dim; /* Adaptive Moderation */
424
425 /* dirtied @xmit */
426 u16 pc ____cacheline_aligned_in_smp;
427 u16 skb_fifo_pc;
428 u32 dma_fifo_pc;
429 struct mlx5e_tx_mpwqe mpwqe;
430
431 struct mlx5e_cq cq;
432
433 /* read only */
434 struct mlx5_wq_cyc wq;
435 u32 dma_fifo_mask;
436 struct mlx5e_sq_stats *stats;
437 struct {
438 struct mlx5e_sq_dma *dma_fifo;
439 struct mlx5e_skb_fifo skb_fifo;
440 struct mlx5e_tx_wqe_info *wqe_info;
441 } db;
442 void __iomem *uar_map;
443 struct netdev_queue *txq;
444 u32 sqn;
445 u16 stop_room;
446 u8 max_sq_mpw_wqebbs;
447 u8 min_inline_mode;
448 struct device *pdev;
449 __be32 mkey_be;
450 unsigned long state;
451 unsigned int hw_mtu;
452 struct mlx5_clock *clock;
453 struct net_device *netdev;
454 struct mlx5_core_dev *mdev;
455 struct mlx5e_channel *channel;
456 struct mlx5e_priv *priv;
457
458 /* control path */
459 struct mlx5_wq_ctrl wq_ctrl;
460 int ch_ix;
461 int txq_ix;
462 u32 rate_limit;
463 struct work_struct recover_work;
464 struct mlx5e_ptpsq *ptpsq;
465 cqe_ts_to_ns ptp_cyc2time;
466 } ____cacheline_aligned_in_smp;
467
468 struct mlx5e_xdp_info_fifo {
469 union mlx5e_xdp_info *xi;
470 u32 *cc;
471 u32 *pc;
472 u32 mask;
473 };
474
475 struct mlx5e_xdpsq;
476 struct mlx5e_xmit_data;
477 struct xsk_tx_metadata;
478 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
479 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
480 struct mlx5e_xmit_data *,
481 int,
482 struct xsk_tx_metadata *);
483
484 struct mlx5e_xdpsq {
485 /* data path */
486
487 /* dirtied @completion */
488 u32 xdpi_fifo_cc;
489 u16 cc;
490
491 /* dirtied @xmit */
492 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
493 u16 pc;
494 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
495 struct mlx5e_tx_mpwqe mpwqe;
496
497 struct mlx5e_cq cq;
498
499 /* read only */
500 struct xsk_buff_pool *xsk_pool;
501 struct mlx5_wq_cyc wq;
502 struct mlx5e_xdpsq_stats *stats;
503 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
504 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
505 struct {
506 struct mlx5e_xdp_wqe_info *wqe_info;
507 struct mlx5e_xdp_info_fifo xdpi_fifo;
508 } db;
509 void __iomem *uar_map;
510 u32 sqn;
511 struct device *pdev;
512 __be32 mkey_be;
513 u16 stop_room;
514 u8 max_sq_mpw_wqebbs;
515 u8 min_inline_mode;
516 unsigned long state;
517 unsigned int hw_mtu;
518
519 /* control path */
520 struct mlx5_wq_ctrl wq_ctrl;
521 struct mlx5e_channel *channel;
522 } ____cacheline_aligned_in_smp;
523
524 struct mlx5e_xdp_buff {
525 struct xdp_buff xdp;
526 struct mlx5_cqe64 *cqe;
527 struct mlx5e_rq *rq;
528 };
529
530 struct mlx5e_ktls_resync_resp;
531
532 struct mlx5e_icosq {
533 /* data path */
534 u16 cc;
535 u16 pc;
536
537 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
538 struct mlx5e_cq cq;
539
540 /* write@xmit, read@completion */
541 struct {
542 struct mlx5e_icosq_wqe_info *wqe_info;
543 } db;
544
545 /* read only */
546 struct mlx5_wq_cyc wq;
547 void __iomem *uar_map;
548 u32 sqn;
549 u16 reserved_room;
550 unsigned long state;
551 /* icosq can be accessed from any CPU and from different contexts
552 * (NAPI softirq or process/workqueue). Always use spin_lock_bh for
553 * simplicity and correctness across all contexts.
554 */
555 spinlock_t lock;
556 struct mlx5e_ktls_resync_resp *ktls_resync;
557
558 /* control path */
559 struct mlx5_wq_ctrl wq_ctrl;
560 struct mlx5e_channel *channel;
561
562 struct work_struct recover_work;
563 } ____cacheline_aligned_in_smp;
564
565 struct mlx5e_frag_page {
566 netmem_ref netmem;
567 u16 frags;
568 };
569
570 enum mlx5e_wqe_frag_flag {
571 MLX5E_WQE_FRAG_LAST_IN_PAGE,
572 MLX5E_WQE_FRAG_SKIP_RELEASE,
573 };
574
575 struct mlx5e_wqe_frag_info {
576 union {
577 struct mlx5e_frag_page *frag_page;
578 struct xdp_buff **xskp;
579 };
580 u32 offset;
581 u8 flags;
582 };
583
584 union mlx5e_alloc_units {
585 DECLARE_FLEX_ARRAY(struct mlx5e_frag_page, frag_pages);
586 DECLARE_FLEX_ARRAY(struct page *, pages);
587 DECLARE_FLEX_ARRAY(struct xdp_buff *, xsk_buffs);
588 };
589
590 struct mlx5e_mpw_info {
591 u16 consumed_strides;
592 DECLARE_BITMAP(skip_release_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE);
593 struct mlx5e_frag_page linear_page;
594 union mlx5e_alloc_units alloc_units;
595 };
596
597 #define MLX5E_MAX_RX_FRAGS 4
598
599 struct mlx5e_rq;
600 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
601 typedef struct sk_buff *
602 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
603 struct mlx5_cqe64 *cqe, u16 cqe_bcnt,
604 u32 head_offset, u32 page_idx);
605 typedef struct sk_buff *
606 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi,
607 struct mlx5_cqe64 *cqe, u32 cqe_bcnt);
608 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
609 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
610 typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool);
611
612 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);
613 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params);
614
615 enum mlx5e_rq_flag {
616 MLX5E_RQ_FLAG_XDP_XMIT,
617 MLX5E_RQ_FLAG_XDP_REDIRECT,
618 };
619
620 struct mlx5e_rq_frag_info {
621 int frag_size;
622 int frag_stride;
623 };
624
625 struct mlx5e_rq_frags_info {
626 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
627 u8 num_frags;
628 u8 log_num_frags;
629 u16 wqe_bulk;
630 u16 refill_unit;
631 u8 wqe_index_mask;
632 };
633
634 struct mlx5e_dma_info {
635 dma_addr_t addr;
636 union {
637 struct mlx5e_frag_page *frag_page;
638 struct page *page;
639 };
640 };
641
642 struct mlx5e_shampo_hd {
643 u32 hd_per_wq;
644 u32 hd_buf_size;
645 u32 mkey;
646 u32 nentries;
647 DECLARE_FLEX_ARRAY(struct mlx5e_dma_info, hd_buf_pages);
648 };
649
650 struct mlx5e_hw_gro_data {
651 struct sk_buff *skb;
652 struct flow_keys fk;
653 int second_ip_id;
654 };
655
656 enum mlx5e_mpwrq_umr_mode {
657 MLX5E_MPWRQ_UMR_MODE_ALIGNED,
658 MLX5E_MPWRQ_UMR_MODE_UNALIGNED,
659 MLX5E_MPWRQ_UMR_MODE_OVERSIZED,
660 MLX5E_MPWRQ_UMR_MODE_TRIPLE,
661 };
662
663 struct mlx5e_rq {
664 /* data path */
665 union {
666 struct {
667 struct mlx5_wq_cyc wq;
668 struct mlx5e_wqe_frag_info *frags;
669 union mlx5e_alloc_units *alloc_units;
670 struct mlx5e_rq_frags_info info;
671 mlx5e_fp_skb_from_cqe skb_from_cqe;
672 } wqe;
673 struct {
674 struct mlx5_wq_ll wq;
675 struct mlx5e_umr_wqe_hdr umr_wqe;
676 struct mlx5e_mpw_info *info;
677 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
678 __be32 umr_mkey_be;
679 u16 num_strides;
680 u16 actual_wq_head;
681 u8 log_stride_sz;
682 u8 umr_in_progress;
683 u8 umr_last_bulk;
684 u8 umr_completed;
685 u8 min_wqe_bulk;
686 u8 page_shift;
687 u8 pages_per_wqe;
688 u8 umr_wqebbs;
689 u8 mtts_per_wqe;
690 u8 umr_mode;
691 struct mlx5e_shampo_hd *shampo;
692 } mpwqe;
693 };
694 struct {
695 u16 headroom;
696 u32 frame0_sz;
697 u8 map_dir; /* dma map direction */
698 } buff;
699
700 struct device *pdev;
701 struct net_device *netdev;
702 struct mlx5e_rq_stats *stats;
703 struct mlx5e_cq cq;
704 struct mlx5e_cq_decomp cqd;
705 struct kernel_hwtstamp_config *hwtstamp_config;
706 struct mlx5_clock *clock;
707 struct mlx5e_icosq *icosq;
708 struct mlx5e_priv *priv;
709
710 struct mlx5e_hw_gro_data *hw_gro_data;
711
712 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
713 mlx5e_fp_post_rx_wqes post_wqes;
714 mlx5e_fp_dealloc_wqe dealloc_wqe;
715
716 unsigned long state;
717 int ix;
718 unsigned int hw_mtu;
719
720 struct dim *dim; /* Dynamic Interrupt Moderation */
721
722 /* XDP */
723 struct bpf_prog __rcu *xdp_prog;
724 struct mlx5e_xdpsq *xdpsq;
725 DECLARE_BITMAP(flags, 8);
726
727 /* page pools */
728 struct page_pool *page_pool;
729 struct page_pool *hd_page_pool;
730
731 struct mlx5e_xdp_buff mxbuf;
732
733 /* AF_XDP zero-copy */
734 struct xsk_buff_pool *xsk_pool;
735
736 struct work_struct recover_work;
737 struct work_struct rx_timeout_work;
738
739 /* control */
740 struct mlx5_wq_ctrl wq_ctrl;
741 __be32 mkey_be;
742 u8 wq_type;
743 u32 rqn;
744 struct mlx5_core_dev *mdev;
745 struct mlx5e_channel *channel;
746 struct mlx5e_dma_info wqe_overflow;
747
748 /* XDP read-mostly */
749 struct xdp_rxq_info xdp_rxq;
750 cqe_ts_to_ns ptp_cyc2time;
751 } ____cacheline_aligned_in_smp;
752
753 enum mlx5e_channel_state {
754 MLX5E_CHANNEL_STATE_XSK,
755 MLX5E_CHANNEL_NUM_STATES
756 };
757
758 struct mlx5e_channel {
759 /* data path */
760 struct mlx5e_rq rq;
761 struct mlx5e_xdpsq rq_xdpsq;
762 struct mlx5e_txqsq sq[MLX5_MAX_NUM_TC];
763 struct mlx5e_icosq icosq; /* internal control operations */
764 struct mlx5e_txqsq __rcu * __rcu *qos_sqs;
765 bool xdp;
766 struct napi_struct napi;
767 struct device *pdev;
768 struct net_device *netdev;
769 __be32 mkey_be;
770 u16 qos_sqs_size;
771 u8 num_tc;
772 u8 lag_port;
773
774 /* XDP_REDIRECT */
775 struct mlx5e_xdpsq *xdpsq;
776
777 /* AF_XDP zero-copy */
778 struct mlx5e_rq xskrq;
779 struct mlx5e_xdpsq xsksq;
780
781 /* Async ICOSQ */
782 struct mlx5e_icosq *async_icosq;
783
784 /* data path - accessed per napi poll */
785 const struct cpumask *aff_mask;
786 struct mlx5e_ch_stats *stats;
787
788 /* control */
789 struct mlx5e_priv *priv;
790 struct mlx5_core_dev *mdev;
791 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
792 int ix;
793 int vec_ix;
794 int sd_ix;
795 int cpu;
796 struct mlx5_sq_bfreg *bfreg;
797 /* Sync between icosq recovery and XSK enable/disable. */
798 struct mutex icosq_recovery_lock;
799
800 /* coalescing configuration */
801 struct dim_cq_moder rx_cq_moder;
802 struct dim_cq_moder tx_cq_moder;
803 };
804
mlx5e_icosq_sync_lock(struct mlx5e_icosq * sq)805 static inline bool mlx5e_icosq_sync_lock(struct mlx5e_icosq *sq)
806 {
807 if (likely(!test_bit(MLX5E_SQ_STATE_LOCK_NEEDED, &sq->state)))
808 return false;
809
810 spin_lock_bh(&sq->lock);
811 return true;
812 }
813
mlx5e_icosq_sync_unlock(struct mlx5e_icosq * sq,bool locked)814 static inline void mlx5e_icosq_sync_unlock(struct mlx5e_icosq *sq, bool locked)
815 {
816 if (unlikely(locked))
817 spin_unlock_bh(&sq->lock);
818 }
819
820 struct mlx5e_ptp;
821
822 struct mlx5e_channels {
823 struct mlx5e_channel **c;
824 struct mlx5e_ptp *ptp;
825 unsigned int num;
826 struct mlx5e_params params;
827 };
828
829 struct mlx5e_channel_stats {
830 struct mlx5e_ch_stats ch;
831 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC];
832 struct mlx5e_rq_stats rq;
833 struct mlx5e_rq_stats xskrq;
834 struct mlx5e_xdpsq_stats rq_xdpsq;
835 struct mlx5e_xdpsq_stats xdpsq;
836 struct mlx5e_xdpsq_stats xsksq;
837 } ____cacheline_aligned_in_smp;
838
839 struct mlx5e_ptp_stats {
840 struct mlx5e_ch_stats ch;
841 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC];
842 struct mlx5e_ptp_cq_stats cq[MLX5_MAX_NUM_TC];
843 struct mlx5e_rq_stats rq;
844 } ____cacheline_aligned_in_smp;
845
846 enum {
847 MLX5E_STATE_OPENED,
848 MLX5E_STATE_DESTROYING,
849 MLX5E_STATE_XDP_TX_ENABLED,
850 MLX5E_STATE_XDP_ACTIVE,
851 MLX5E_STATE_CHANNELS_ACTIVE,
852 };
853
854 struct mlx5e_modify_sq_param {
855 int curr_state;
856 int next_state;
857 int rl_update;
858 int rl_index;
859 bool qos_update;
860 u16 qos_queue_group_id;
861 };
862
863 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
864 struct mlx5e_hv_vhca_stats_agent {
865 struct mlx5_hv_vhca_agent *agent;
866 struct delayed_work work;
867 u16 delay;
868 void *buf;
869 };
870 #endif
871
872 struct mlx5e_xsk {
873 /* XSK buffer pools are stored separately from channels,
874 * because we don't want to lose them when channels are
875 * recreated. The kernel also stores buffer pool, but it doesn't
876 * distinguish between zero-copy and non-zero-copy UMEMs, so
877 * rely on our mechanism.
878 */
879 struct xsk_buff_pool **pools;
880 u16 refcnt;
881 bool ever_used;
882 };
883
884 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
885 * initialized, and used where we can't allocate them because that functions
886 * must not fail. Use with care and make sure the same variable is not used
887 * simultaneously by multiple users.
888 */
889 struct mlx5e_scratchpad {
890 cpumask_var_t cpumask;
891 };
892
893 struct mlx5e_trap;
894 struct mlx5e_htb;
895
896 struct mlx5e_priv {
897 /* priv data path fields - start */
898 struct mlx5e_selq selq;
899 struct mlx5e_txqsq **txq2sq;
900 struct mlx5e_sq_stats **txq2sq_stats;
901
902 #ifdef CONFIG_MLX5_CORE_EN_DCB
903 struct mlx5e_dcbx_dp dcbx_dp;
904 #endif
905 /* priv data path fields - end */
906
907 unsigned long state;
908 struct mutex state_lock; /* Protects Interface state */
909 struct mlx5e_rq drop_rq;
910
911 struct mlx5e_channels channels;
912 struct mlx5e_rx_res *rx_res;
913 u32 *tx_rates;
914
915 struct mlx5e_flow_steering *fs;
916
917 struct workqueue_struct *wq;
918 struct work_struct update_carrier_work;
919 struct work_struct set_rx_mode_work;
920 struct work_struct tx_timeout_work;
921 struct work_struct update_stats_work;
922 struct work_struct monitor_counters_work;
923 struct mlx5_nb monitor_counters_nb;
924
925 struct mlx5_core_dev *mdev;
926 struct net_device *netdev;
927 struct mlx5e_trap *en_trap;
928 struct mlx5e_stats stats;
929 struct mlx5e_channel_stats **channel_stats;
930 struct mlx5e_channel_stats trap_stats;
931 struct mlx5e_ptp_stats ptp_stats;
932 struct mlx5e_sq_stats **htb_qos_sq_stats;
933 u16 htb_max_qos_sqs;
934 u16 stats_nch;
935 u16 max_nch;
936 u8 max_opened_tc;
937 bool tx_ptp_opened;
938 bool rx_ptp_opened;
939 bool ktls_rx_was_enabled;
940 struct kernel_hwtstamp_config hwtstamp_config;
941 u16 q_counter[MLX5_SD_MAX_GROUP_SZ];
942 u16 drop_rq_q_counter;
943 struct notifier_block events_nb;
944 struct notifier_block blocking_events_nb;
945
946 struct mlx5e_pcie_cong_event *cong_event;
947
948 struct udp_tunnel_nic_info nic_info;
949 #ifdef CONFIG_MLX5_CORE_EN_DCB
950 struct mlx5e_dcbx dcbx;
951 #endif
952
953 const struct mlx5e_profile *profile;
954 void *ppriv;
955 #ifdef CONFIG_MLX5_MACSEC
956 struct mlx5e_macsec *macsec;
957 #endif
958 #ifdef CONFIG_MLX5_EN_IPSEC
959 struct mlx5e_ipsec *ipsec;
960 #endif
961 #ifdef CONFIG_MLX5_EN_PSP
962 struct mlx5e_psp *psp;
963 #endif
964 #ifdef CONFIG_MLX5_EN_TLS
965 struct mlx5e_tls *tls;
966 #endif
967 struct devlink_health_reporter *tx_reporter;
968 struct devlink_health_reporter *rx_reporter;
969 struct mlx5e_xsk xsk;
970 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
971 struct mlx5e_hv_vhca_stats_agent stats_agent;
972 #endif
973 struct mlx5e_scratchpad scratchpad;
974 struct mlx5e_htb *htb;
975 struct mlx5e_mqprio_rl *mqprio_rl;
976 struct dentry *dfs_root;
977 struct mlx5_devcom_comp_dev *devcom;
978 struct ethtool_fec_hist_range *fec_ranges;
979 };
980
981 struct mlx5e_dev {
982 struct net_device *netdev;
983 struct devlink_port dl_port;
984 };
985
986 struct mlx5e_rx_handlers {
987 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
988 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
989 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo;
990 };
991
992 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;
993
994 enum mlx5e_profile_feature {
995 MLX5E_PROFILE_FEATURE_PTP_RX,
996 MLX5E_PROFILE_FEATURE_PTP_TX,
997 MLX5E_PROFILE_FEATURE_QOS_HTB,
998 MLX5E_PROFILE_FEATURE_FS_VLAN,
999 MLX5E_PROFILE_FEATURE_FS_TC,
1000 };
1001
1002 struct mlx5e_profile {
1003 int (*init)(struct mlx5_core_dev *mdev,
1004 struct net_device *netdev);
1005 void (*cleanup)(struct mlx5e_priv *priv);
1006 int (*init_rx)(struct mlx5e_priv *priv);
1007 void (*cleanup_rx)(struct mlx5e_priv *priv);
1008 int (*init_tx)(struct mlx5e_priv *priv);
1009 void (*cleanup_tx)(struct mlx5e_priv *priv);
1010 void (*enable)(struct mlx5e_priv *priv);
1011 void (*disable)(struct mlx5e_priv *priv);
1012 int (*update_rx)(struct mlx5e_priv *priv);
1013 void (*update_stats)(struct mlx5e_priv *priv);
1014 void (*update_carrier)(struct mlx5e_priv *priv);
1015 int (*max_nch_limit)(struct mlx5_core_dev *mdev);
1016 u32 (*get_tisn)(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv,
1017 u8 lag_port, u8 tc);
1018 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
1019 mlx5e_stats_grp_t *stats_grps;
1020 const struct mlx5e_rx_handlers *rx_handlers;
1021 int max_tc;
1022 u32 features;
1023 };
1024
1025 u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev,
1026 struct mlx5e_priv *priv,
1027 const struct mlx5e_profile *profile,
1028 u8 lag_port, u8 tc);
1029
1030 #define mlx5e_profile_feature_cap(profile, feature) \
1031 ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature))
1032
1033 void mlx5e_build_ptys2ethtool_map(void);
1034
1035 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift,
1036 enum mlx5e_mpwrq_umr_mode umr_mode);
1037
1038 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
1039 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
1040
1041 int mlx5e_self_test_num(struct mlx5e_priv *priv);
1042 int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data);
1043 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
1044 u64 *buf);
1045 void mlx5e_set_rx_mode_work(struct work_struct *work);
1046
1047 int mlx5e_hwtstamp_set(struct mlx5e_priv *priv,
1048 struct kernel_hwtstamp_config *config,
1049 struct netlink_ext_ack *extack);
1050 int mlx5e_hwtstamp_get(struct mlx5e_priv *priv,
1051 struct kernel_hwtstamp_config *config);
1052 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter);
1053
1054 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
1055 u16 vid);
1056 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
1057 u16 vid);
1058 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
1059
1060 struct mlx5e_xsk_param;
1061
1062 struct mlx5e_rq_param;
1063 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1064 struct mlx5e_xsk_param *xsk, int node, u16 q_counter,
1065 struct mlx5e_rq *rq);
1066 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
1067 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
1068 void mlx5e_close_rq(struct mlx5e_rq *rq);
1069 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param, u16 q_counter);
1070 void mlx5e_destroy_rq(struct mlx5e_rq *rq);
1071
1072 bool mlx5e_reset_rx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode,
1073 bool dim_enabled);
1074 bool mlx5e_reset_rx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode,
1075 bool dim_enabled, bool keep_dim_state);
1076
1077 struct mlx5e_sq_param;
1078 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1079 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1080 struct mlx5e_xdpsq *sq, bool is_redirect);
1081 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
1082
1083 struct mlx5e_create_cq_param {
1084 struct net_device *netdev;
1085 struct workqueue_struct *wq;
1086 struct napi_struct *napi;
1087 struct mlx5e_ch_stats *ch_stats;
1088 int node;
1089 int ix;
1090 struct mlx5_uars_page *uar;
1091 };
1092
1093 struct mlx5e_cq_param;
1094 int mlx5e_open_cq(struct mlx5_core_dev *mdev, struct dim_cq_moder moder,
1095 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1096 struct mlx5e_cq *cq);
1097 void mlx5e_close_cq(struct mlx5e_cq *cq);
1098 int mlx5e_modify_cq_period_mode(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
1099 u8 cq_period_mode);
1100 int mlx5e_modify_cq_moderation(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
1101 u16 cq_period, u16 cq_max_count, u8 cq_period_mode);
1102
1103 int mlx5e_open_locked(struct net_device *netdev);
1104 int mlx5e_close_locked(struct net_device *netdev);
1105
1106 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c);
1107 void mlx5e_trigger_napi_async_icosq(struct mlx5e_channel *c);
1108 void mlx5e_trigger_napi_sched(struct napi_struct *napi);
1109
1110 int mlx5e_open_channels(struct mlx5e_priv *priv,
1111 struct mlx5e_channels *chs);
1112 void mlx5e_close_channels(struct mlx5e_channels *chs);
1113
1114 /* Function pointer to be used to modify HW or kernel settings while
1115 * switching channels
1116 */
1117 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
1118 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
1119 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
1120 { \
1121 return fn(priv); \
1122 }
1123 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
1124 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
1125 struct mlx5e_params *new_params,
1126 mlx5e_fp_preactivate preactivate,
1127 void *context, bool reset);
1128 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv);
1129 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
1130 int mlx5e_update_tc_and_tx_queues_ctx(struct mlx5e_priv *priv, void *context);
1131 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
1132 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1133 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx);
1134
1135 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state);
1136 void mlx5e_activate_rq(struct mlx5e_rq *rq);
1137 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1138 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
1139 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
1140
1141 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1142 struct mlx5e_modify_sq_param *p);
1143 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1144 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1145 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1146 struct mlx5e_sq_stats *sq_stats);
1147 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1148 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq);
1149 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq);
1150 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1151 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa);
1152 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq);
1153 struct mlx5e_create_sq_param;
1154 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1155 struct mlx5e_sq_param *param,
1156 struct mlx5e_create_sq_param *csp,
1157 u16 qos_queue_group_id,
1158 u32 *sqn);
1159 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1160 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq);
1161
1162 bool mlx5e_reset_tx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode,
1163 bool dim_enabled);
1164 bool mlx5e_reset_tx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode,
1165 bool dim_enabled, bool keep_dim_state);
1166
mlx5_tx_swp_supported(struct mlx5_core_dev * mdev)1167 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1168 {
1169 return MLX5_CAP_ETH(mdev, swp) &&
1170 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1171 }
1172
1173 extern const struct ethtool_ops mlx5e_ethtool_ops;
1174
1175 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);
1176 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_tises);
1177 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1178 int mlx5e_modify_tirs_lb(struct mlx5_core_dev *mdev, bool enable_uc_lb,
1179 bool enable_mc_lb);
1180 int mlx5e_refresh_tirs(struct mlx5_core_dev *mdev, bool enable_uc_lb,
1181 bool enable_mc_lb);
1182 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
1183
1184 /* common netdev helpers */
1185 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1186 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1187 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1188 struct mlx5e_rq *drop_rq);
1189 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1190
1191 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1192 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1193
1194 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1195 int mlx5e_close(struct net_device *netdev);
1196 int mlx5e_open(struct net_device *netdev);
1197
1198 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1199
1200 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1201 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
1202 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1203 mlx5e_fp_preactivate preactivate);
1204 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);
1205
1206 /* ethtool helpers */
1207 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1208 struct ethtool_drvinfo *drvinfo);
1209 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1210 u32 stringset, u8 *data);
1211 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1212 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1213 struct ethtool_stats *stats, u64 *data);
1214 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1215 struct ethtool_ringparam *param,
1216 struct kernel_ethtool_ringparam *kernel_param);
1217 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1218 struct ethtool_ringparam *param,
1219 struct netlink_ext_ack *extack);
1220 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1221 struct ethtool_channels *ch);
1222 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1223 struct ethtool_channels *ch);
1224 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1225 struct ethtool_coalesce *coal,
1226 struct kernel_ethtool_coalesce *kernel_coal,
1227 struct netlink_ext_ack *extack);
1228 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1229 struct ethtool_coalesce *coal,
1230 struct kernel_ethtool_coalesce *kernel_coal,
1231 struct netlink_ext_ack *extack);
1232 int mlx5e_get_per_queue_coalesce(struct net_device *dev, u32 queue,
1233 struct ethtool_coalesce *coal);
1234 int mlx5e_set_per_queue_coalesce(struct net_device *dev, u32 queue,
1235 struct ethtool_coalesce *coal);
1236 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1237 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1238 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1239 struct kernel_ethtool_ts_info *info);
1240 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1241 struct ethtool_flash *flash);
1242
1243 /* mlx5e generic netdev management API */
1244 static inline bool
mlx5e_tx_mpwqe_supported(struct mlx5_core_dev * mdev)1245 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev)
1246 {
1247 return !is_kdump_kernel() &&
1248 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe);
1249 }
1250
1251 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev);
1252 int mlx5e_priv_init(struct mlx5e_priv *priv,
1253 const struct mlx5e_profile *profile,
1254 struct net_device *netdev,
1255 struct mlx5_core_dev *mdev);
1256 void mlx5e_priv_cleanup(struct mlx5e_priv *priv);
1257 struct net_device *
1258 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile);
1259 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1260 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1261 void mlx5e_destroy_netdev(struct net_device *netdev);
1262 int mlx5e_netdev_change_profile(struct net_device *netdev,
1263 struct mlx5_core_dev *mdev,
1264 const struct mlx5e_profile *new_profile,
1265 void *new_ppriv);
1266 void mlx5e_netdev_attach_nic_profile(struct net_device *netdev,
1267 struct mlx5_core_dev *mdev);
1268 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1269 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu);
1270
1271 void mlx5e_set_xdp_feature(struct mlx5e_priv *priv);
1272 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1273 struct net_device *netdev,
1274 netdev_features_t features);
1275 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1276 #ifdef CONFIG_MLX5_ESWITCH
1277 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1278 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1279 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1280 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1281 #endif
1282 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);
1283 #endif /* __MLX5_EN_H__ */
1284