1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
3
4 #include <linux/acpi.h>
5 #include <linux/clk.h>
6 #include <linux/dmaengine.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/dma/qcom-gpi-dma.h>
9 #include <linux/err.h>
10 #include <linux/i2c.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/soc/qcom/geni-se.h>
18 #include <linux/spinlock.h>
19 #include <linux/units.h>
20
21 #define SE_I2C_TX_TRANS_LEN 0x26c
22 #define SE_I2C_RX_TRANS_LEN 0x270
23 #define SE_I2C_SCL_COUNTERS 0x278
24
25 #define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
26 M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
27 #define SE_I2C_ABORT BIT(1)
28
29 /* M_CMD OP codes for I2C */
30 #define I2C_WRITE 0x1
31 #define I2C_READ 0x2
32 #define I2C_WRITE_READ 0x3
33 #define I2C_ADDR_ONLY 0x4
34 #define I2C_BUS_CLEAR 0x6
35 #define I2C_STOP_ON_BUS 0x7
36 /* M_CMD params for I2C */
37 #define PRE_CMD_DELAY BIT(0)
38 #define TIMESTAMP_BEFORE BIT(1)
39 #define STOP_STRETCH BIT(2)
40 #define TIMESTAMP_AFTER BIT(3)
41 #define POST_COMMAND_DELAY BIT(4)
42 #define IGNORE_ADD_NACK BIT(6)
43 #define READ_FINISHED_WITH_ACK BIT(7)
44 #define BYPASS_ADDR_PHASE BIT(8)
45 #define SLV_ADDR_MSK GENMASK(15, 9)
46 #define SLV_ADDR_SHFT 9
47 /* I2C SCL COUNTER fields */
48 #define HIGH_COUNTER_MSK GENMASK(29, 20)
49 #define HIGH_COUNTER_SHFT 20
50 #define LOW_COUNTER_MSK GENMASK(19, 10)
51 #define LOW_COUNTER_SHFT 10
52 #define CYCLE_COUNTER_MSK GENMASK(9, 0)
53
54 #define I2C_PACK_TX BIT(0)
55 #define I2C_PACK_RX BIT(1)
56
57 enum geni_i2c_err_code {
58 GP_IRQ0,
59 NACK,
60 GP_IRQ2,
61 BUS_PROTO,
62 ARB_LOST,
63 GP_IRQ5,
64 GENI_OVERRUN,
65 GENI_ILLEGAL_CMD,
66 GENI_ABORT_DONE,
67 GENI_TIMEOUT,
68 };
69
70 #define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
71 << 5)
72
73 #define I2C_AUTO_SUSPEND_DELAY 250
74 #define PACKING_BYTES_PW 4
75
76 #define ABORT_TIMEOUT HZ
77 #define XFER_TIMEOUT HZ
78 #define RST_TIMEOUT HZ
79
80 #define QCOM_I2C_MIN_NUM_OF_MSGS_MULTI_DESC 2
81
82 /**
83 * struct geni_i2c_gpi_multi_desc_xfer - Structure for multi transfer support
84 *
85 * @msg_idx_cnt: Current message index being processed in the transfer
86 * @unmap_msg_cnt: Number of messages that have been unmapped
87 * @irq_cnt: Number of transfer completion interrupts received
88 * @dma_buf: Array of virtual addresses for DMA-safe buffers
89 * @dma_addr: Array of DMA addresses corresponding to the buffers
90 */
91 struct geni_i2c_gpi_multi_desc_xfer {
92 u32 msg_idx_cnt;
93 u32 unmap_msg_cnt;
94 u32 irq_cnt;
95 void **dma_buf;
96 dma_addr_t *dma_addr;
97 };
98
99 struct geni_i2c_dev {
100 struct geni_se se;
101 u32 tx_wm;
102 int irq;
103 int err;
104 struct i2c_adapter adap;
105 struct completion done;
106 struct i2c_msg *cur;
107 int cur_wr;
108 int cur_rd;
109 spinlock_t lock;
110 struct clk *core_clk;
111 u32 clk_freq_out;
112 const struct geni_i2c_clk_fld *clk_fld;
113 int suspended;
114 void *dma_buf;
115 size_t xfer_len;
116 dma_addr_t dma_addr;
117 struct dma_chan *tx_c;
118 struct dma_chan *rx_c;
119 bool no_dma;
120 bool gpi_mode;
121 bool abort_done;
122 bool is_tx_multi_desc_xfer;
123 u32 num_msgs;
124 struct geni_i2c_gpi_multi_desc_xfer i2c_multi_desc_config;
125 };
126
127 struct geni_i2c_desc {
128 bool has_core_clk;
129 char *icc_ddr;
130 bool no_dma_support;
131 unsigned int tx_fifo_depth;
132 };
133
134 struct geni_i2c_err_log {
135 int err;
136 const char *msg;
137 };
138
139 static const struct geni_i2c_err_log gi2c_log[] = {
140 [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"},
141 [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"},
142 [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"},
143 [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unexpected start/stop"},
144 [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"},
145 [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"},
146 [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"},
147 [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"},
148 [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"},
149 [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"},
150 };
151
152 struct geni_i2c_clk_fld {
153 u32 clk_freq_out;
154 u8 clk_div;
155 u8 t_high_cnt;
156 u8 t_low_cnt;
157 u8 t_cycle_cnt;
158 };
159
160 /*
161 * Hardware uses the underlying formula to calculate time periods of
162 * SCL clock cycle. Firmware uses some additional cycles excluded from the
163 * below formula and it is confirmed that the time periods are within
164 * specification limits.
165 *
166 * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock
167 * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock
168 * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock
169 * clk_freq_out = t / t_cycle
170 * source_clock = 19.2 MHz
171 */
172 static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = {
173 { I2C_MAX_STANDARD_MODE_FREQ, 7, 10, 12, 26 },
174 { I2C_MAX_FAST_MODE_FREQ, 2, 5, 11, 22 },
175 { I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 2, 8, 18 },
176 {}
177 };
178
179 /* source_clock = 32 MHz */
180 static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = {
181 { I2C_MAX_STANDARD_MODE_FREQ, 8, 14, 18, 38 },
182 { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 },
183 { I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 },
184 {}
185 };
186
geni_i2c_clk_map_idx(struct geni_i2c_dev * gi2c)187 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
188 {
189 const struct geni_i2c_clk_fld *itr;
190
191 if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ)
192 itr = geni_i2c_clk_map_32mhz;
193 else
194 itr = geni_i2c_clk_map_19p2mhz;
195
196 while (itr->clk_freq_out != 0) {
197 if (itr->clk_freq_out == gi2c->clk_freq_out) {
198 gi2c->clk_fld = itr;
199 return 0;
200 }
201 itr++;
202 }
203 return -EINVAL;
204 }
205
qcom_geni_i2c_conf(struct geni_i2c_dev * gi2c)206 static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
207 {
208 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
209 u32 val;
210
211 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
212
213 val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN;
214 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
215
216 val = itr->t_high_cnt << HIGH_COUNTER_SHFT;
217 val |= itr->t_low_cnt << LOW_COUNTER_SHFT;
218 val |= itr->t_cycle_cnt;
219 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
220 }
221
geni_i2c_err_misc(struct geni_i2c_dev * gi2c)222 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
223 {
224 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
225 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
226 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
227 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS);
228 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);
229 u32 rx_st, tx_st;
230
231 if (dma) {
232 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
233 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
234 } else {
235 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);
236 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS);
237 }
238 dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
239 dma, tx_st, rx_st, m_stat);
240 dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
241 m_cmd, geni_s, geni_ios);
242 }
243
geni_i2c_err(struct geni_i2c_dev * gi2c,int err)244 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
245 {
246 if (!gi2c->err)
247 gi2c->err = gi2c_log[err].err;
248 if (gi2c->cur)
249 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n",
250 gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags);
251
252 switch (err) {
253 case GENI_ABORT_DONE:
254 gi2c->abort_done = true;
255 break;
256 case NACK:
257 case GENI_TIMEOUT:
258 dev_dbg(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
259 break;
260 default:
261 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
262 geni_i2c_err_misc(gi2c);
263 break;
264 }
265 }
266
geni_i2c_irq(int irq,void * dev)267 static irqreturn_t geni_i2c_irq(int irq, void *dev)
268 {
269 struct geni_i2c_dev *gi2c = dev;
270 void __iomem *base = gi2c->se.base;
271 int j, p;
272 u32 m_stat;
273 u32 rx_st;
274 u32 dm_tx_st;
275 u32 dm_rx_st;
276 u32 dma;
277 u32 val;
278 struct i2c_msg *cur;
279
280 spin_lock(&gi2c->lock);
281 m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS);
282 rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS);
283 dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT);
284 dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT);
285 dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
286 cur = gi2c->cur;
287
288 if (!cur ||
289 m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) ||
290 dm_rx_st & (DM_I2C_CB_ERR)) {
291 if (m_stat & M_GP_IRQ_1_EN)
292 geni_i2c_err(gi2c, NACK);
293 if (m_stat & M_GP_IRQ_3_EN)
294 geni_i2c_err(gi2c, BUS_PROTO);
295 if (m_stat & M_GP_IRQ_4_EN)
296 geni_i2c_err(gi2c, ARB_LOST);
297 if (m_stat & M_CMD_OVERRUN_EN)
298 geni_i2c_err(gi2c, GENI_OVERRUN);
299 if (m_stat & M_ILLEGAL_CMD_EN)
300 geni_i2c_err(gi2c, GENI_ILLEGAL_CMD);
301 if (m_stat & M_CMD_ABORT_EN)
302 geni_i2c_err(gi2c, GENI_ABORT_DONE);
303 if (m_stat & M_GP_IRQ_0_EN)
304 geni_i2c_err(gi2c, GP_IRQ0);
305
306 /* Disable the TX Watermark interrupt to stop TX */
307 if (!dma)
308 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
309 } else if (dma) {
310 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n",
311 dm_tx_st, dm_rx_st);
312 } else if (cur->flags & I2C_M_RD &&
313 m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) {
314 u32 rxcnt = rx_st & RX_FIFO_WC_MSK;
315
316 for (j = 0; j < rxcnt; j++) {
317 p = 0;
318 val = readl_relaxed(base + SE_GENI_RX_FIFOn);
319 while (gi2c->cur_rd < cur->len && p < sizeof(val)) {
320 cur->buf[gi2c->cur_rd++] = val & 0xff;
321 val >>= 8;
322 p++;
323 }
324 if (gi2c->cur_rd == cur->len)
325 break;
326 }
327 } else if (!(cur->flags & I2C_M_RD) &&
328 m_stat & M_TX_FIFO_WATERMARK_EN) {
329 for (j = 0; j < gi2c->tx_wm; j++) {
330 u32 temp;
331
332 val = 0;
333 p = 0;
334 while (gi2c->cur_wr < cur->len && p < sizeof(val)) {
335 temp = cur->buf[gi2c->cur_wr++];
336 val |= temp << (p * 8);
337 p++;
338 }
339 writel_relaxed(val, base + SE_GENI_TX_FIFOn);
340 /* TX Complete, Disable the TX Watermark interrupt */
341 if (gi2c->cur_wr == cur->len) {
342 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
343 break;
344 }
345 }
346 }
347
348 if (m_stat)
349 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR);
350
351 if (dma && dm_tx_st)
352 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR);
353 if (dma && dm_rx_st)
354 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR);
355
356 /* if this is err with done-bit not set, handle that through timeout. */
357 if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN ||
358 dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE ||
359 dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE)
360 complete(&gi2c->done);
361
362 spin_unlock(&gi2c->lock);
363
364 return IRQ_HANDLED;
365 }
366
geni_i2c_abort_xfer(struct geni_i2c_dev * gi2c)367 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c)
368 {
369 unsigned long time_left = ABORT_TIMEOUT;
370 unsigned long flags;
371
372 spin_lock_irqsave(&gi2c->lock, flags);
373 geni_i2c_err(gi2c, GENI_TIMEOUT);
374 gi2c->cur = NULL;
375 gi2c->abort_done = false;
376 geni_se_abort_m_cmd(&gi2c->se);
377 spin_unlock_irqrestore(&gi2c->lock, flags);
378
379 do {
380 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
381 } while (!gi2c->abort_done && time_left);
382
383 if (!time_left)
384 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n");
385 }
386
geni_i2c_rx_fsm_rst(struct geni_i2c_dev * gi2c)387 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c)
388 {
389 u32 val;
390 unsigned long time_left = RST_TIMEOUT;
391
392 writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST);
393 do {
394 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
395 val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
396 } while (!(val & RX_RESET_DONE) && time_left);
397
398 if (!(val & RX_RESET_DONE))
399 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n");
400 }
401
geni_i2c_tx_fsm_rst(struct geni_i2c_dev * gi2c)402 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c)
403 {
404 u32 val;
405 unsigned long time_left = RST_TIMEOUT;
406
407 writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST);
408 do {
409 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
410 val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
411 } while (!(val & TX_RESET_DONE) && time_left);
412
413 if (!(val & TX_RESET_DONE))
414 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n");
415 }
416
geni_i2c_rx_msg_cleanup(struct geni_i2c_dev * gi2c,struct i2c_msg * cur)417 static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c,
418 struct i2c_msg *cur)
419 {
420 gi2c->cur_rd = 0;
421 if (gi2c->dma_buf) {
422 if (gi2c->err)
423 geni_i2c_rx_fsm_rst(gi2c);
424 geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
425 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
426 }
427 }
428
geni_i2c_tx_msg_cleanup(struct geni_i2c_dev * gi2c,struct i2c_msg * cur)429 static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c,
430 struct i2c_msg *cur)
431 {
432 gi2c->cur_wr = 0;
433 if (gi2c->dma_buf) {
434 if (gi2c->err)
435 geni_i2c_tx_fsm_rst(gi2c);
436 geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
437 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
438 }
439 }
440
geni_i2c_rx_one_msg(struct geni_i2c_dev * gi2c,struct i2c_msg * msg,u32 m_param)441 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
442 u32 m_param)
443 {
444 dma_addr_t rx_dma = 0;
445 unsigned long time_left;
446 void *dma_buf;
447 struct geni_se *se = &gi2c->se;
448 size_t len = msg->len;
449 struct i2c_msg *cur;
450
451 dma_buf = gi2c->no_dma ? NULL : i2c_get_dma_safe_msg_buf(msg, 32);
452 if (dma_buf)
453 geni_se_select_mode(se, GENI_SE_DMA);
454 else
455 geni_se_select_mode(se, GENI_SE_FIFO);
456
457 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN);
458 geni_se_setup_m_cmd(se, I2C_READ, m_param);
459
460 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) {
461 geni_se_select_mode(se, GENI_SE_FIFO);
462 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
463 dma_buf = NULL;
464 } else {
465 gi2c->xfer_len = len;
466 gi2c->dma_addr = rx_dma;
467 gi2c->dma_buf = dma_buf;
468 }
469
470 cur = gi2c->cur;
471 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
472 if (!time_left)
473 geni_i2c_abort_xfer(gi2c);
474
475 geni_i2c_rx_msg_cleanup(gi2c, cur);
476
477 return gi2c->err;
478 }
479
geni_i2c_tx_one_msg(struct geni_i2c_dev * gi2c,struct i2c_msg * msg,u32 m_param)480 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
481 u32 m_param)
482 {
483 dma_addr_t tx_dma = 0;
484 unsigned long time_left;
485 void *dma_buf;
486 struct geni_se *se = &gi2c->se;
487 size_t len = msg->len;
488 struct i2c_msg *cur;
489
490 dma_buf = gi2c->no_dma ? NULL : i2c_get_dma_safe_msg_buf(msg, 32);
491 if (dma_buf)
492 geni_se_select_mode(se, GENI_SE_DMA);
493 else
494 geni_se_select_mode(se, GENI_SE_FIFO);
495
496 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN);
497 geni_se_setup_m_cmd(se, I2C_WRITE, m_param);
498
499 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) {
500 geni_se_select_mode(se, GENI_SE_FIFO);
501 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
502 dma_buf = NULL;
503 } else {
504 gi2c->xfer_len = len;
505 gi2c->dma_addr = tx_dma;
506 gi2c->dma_buf = dma_buf;
507 }
508
509 if (!dma_buf) /* Get FIFO IRQ */
510 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);
511
512 cur = gi2c->cur;
513 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
514 if (!time_left)
515 geni_i2c_abort_xfer(gi2c);
516
517 geni_i2c_tx_msg_cleanup(gi2c, cur);
518
519 return gi2c->err;
520 }
521
i2c_gpi_cb_result(void * cb,const struct dmaengine_result * result)522 static void i2c_gpi_cb_result(void *cb, const struct dmaengine_result *result)
523 {
524 struct geni_i2c_dev *gi2c = cb;
525 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer;
526
527 if (result->result != DMA_TRANS_NOERROR) {
528 dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result);
529 gi2c->err = -EIO;
530 } else if (result->residue) {
531 dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue);
532 }
533
534 if (gi2c->is_tx_multi_desc_xfer) {
535 tx_multi_xfer = &gi2c->i2c_multi_desc_config;
536 tx_multi_xfer->irq_cnt++;
537 }
538
539 complete(&gi2c->done);
540 }
541
geni_i2c_gpi_unmap(struct geni_i2c_dev * gi2c,struct i2c_msg * msg,void * tx_buf,dma_addr_t tx_addr,void * rx_buf,dma_addr_t rx_addr)542 static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
543 void *tx_buf, dma_addr_t tx_addr,
544 void *rx_buf, dma_addr_t rx_addr)
545 {
546 if (tx_buf) {
547 dma_unmap_single(gi2c->se.dev->parent, tx_addr, msg->len, DMA_TO_DEVICE);
548 i2c_put_dma_safe_msg_buf(tx_buf, msg, !gi2c->err);
549 }
550
551 if (rx_buf) {
552 dma_unmap_single(gi2c->se.dev->parent, rx_addr, msg->len, DMA_FROM_DEVICE);
553 i2c_put_dma_safe_msg_buf(rx_buf, msg, !gi2c->err);
554 }
555 }
556
557 /**
558 * geni_i2c_gpi_multi_desc_unmap() - Unmaps DMA buffers post multi message TX transfers
559 * @gi2c: I2C dev handle
560 * @msgs: Array of I2C messages
561 * @peripheral: Pointer to gpi_i2c_config
562 */
geni_i2c_gpi_multi_desc_unmap(struct geni_i2c_dev * gi2c,struct i2c_msg msgs[],struct gpi_i2c_config * peripheral)563 static void geni_i2c_gpi_multi_desc_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[],
564 struct gpi_i2c_config *peripheral)
565 {
566 u32 msg_xfer_cnt, wr_idx = 0;
567 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer = &gi2c->i2c_multi_desc_config;
568
569 msg_xfer_cnt = gi2c->err ? tx_multi_xfer->msg_idx_cnt : tx_multi_xfer->irq_cnt;
570
571 /* Unmap the processed DMA buffers based on the received interrupt count */
572 for (; tx_multi_xfer->unmap_msg_cnt < msg_xfer_cnt; tx_multi_xfer->unmap_msg_cnt++) {
573 wr_idx = tx_multi_xfer->unmap_msg_cnt;
574 geni_i2c_gpi_unmap(gi2c, &msgs[wr_idx],
575 tx_multi_xfer->dma_buf[wr_idx],
576 tx_multi_xfer->dma_addr[wr_idx],
577 NULL, 0);
578
579 if (tx_multi_xfer->unmap_msg_cnt == gi2c->num_msgs - 1) {
580 kfree(tx_multi_xfer->dma_buf);
581 kfree(tx_multi_xfer->dma_addr);
582 break;
583 }
584 }
585 }
586
587 /**
588 * geni_i2c_gpi_multi_xfer_timeout_handler() - Handles multi message transfer timeout
589 * @dev: Pointer to the corresponding dev node
590 * @multi_xfer: Pointer to the geni_i2c_gpi_multi_desc_xfer
591 * @transfer_timeout_msecs: Timeout value in milliseconds
592 * @transfer_comp: Completion object of the transfer
593 *
594 * This function waits for the completion of each processed transfer messages
595 * based on the interrupts generated upon transfer completion.
596 *
597 * Return: On success returns 0, -ETIMEDOUT on timeout.
598 */
geni_i2c_gpi_multi_xfer_timeout_handler(struct device * dev,struct geni_i2c_gpi_multi_desc_xfer * multi_xfer,u32 transfer_timeout_msecs,struct completion * transfer_comp)599 static int geni_i2c_gpi_multi_xfer_timeout_handler(struct device *dev,
600 struct geni_i2c_gpi_multi_desc_xfer *multi_xfer,
601 u32 transfer_timeout_msecs,
602 struct completion *transfer_comp)
603 {
604 int i;
605 u32 time_left;
606
607 for (i = 0; i < multi_xfer->msg_idx_cnt - 1; i++) {
608 reinit_completion(transfer_comp);
609
610 if (multi_xfer->msg_idx_cnt != multi_xfer->irq_cnt) {
611 time_left = wait_for_completion_timeout(transfer_comp,
612 transfer_timeout_msecs);
613 if (!time_left) {
614 dev_err(dev, "%s: Transfer timeout\n", __func__);
615 return -ETIMEDOUT;
616 }
617 }
618 }
619 return 0;
620 }
621
geni_i2c_gpi(struct geni_i2c_dev * gi2c,struct i2c_msg msgs[],struct dma_slave_config * config,dma_addr_t * dma_addr_p,void ** buf,unsigned int op,struct dma_chan * dma_chan)622 static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[],
623 struct dma_slave_config *config, dma_addr_t *dma_addr_p,
624 void **buf, unsigned int op, struct dma_chan *dma_chan)
625 {
626 struct gpi_i2c_config *peripheral;
627 unsigned int flags;
628 void *dma_buf;
629 dma_addr_t addr;
630 enum dma_data_direction map_dirn;
631 enum dma_transfer_direction dma_dirn;
632 struct dma_async_tx_descriptor *desc;
633 int ret;
634 struct geni_i2c_gpi_multi_desc_xfer *gi2c_gpi_xfer;
635 dma_cookie_t cookie;
636 u32 msg_idx;
637
638 peripheral = config->peripheral_config;
639 gi2c_gpi_xfer = &gi2c->i2c_multi_desc_config;
640 msg_idx = gi2c_gpi_xfer->msg_idx_cnt;
641
642 dma_buf = i2c_get_dma_safe_msg_buf(&msgs[msg_idx], 1);
643 if (!dma_buf) {
644 ret = -ENOMEM;
645 goto out;
646 }
647
648 if (op == I2C_WRITE)
649 map_dirn = DMA_TO_DEVICE;
650 else
651 map_dirn = DMA_FROM_DEVICE;
652
653 addr = dma_map_single(gi2c->se.dev->parent, dma_buf,
654 msgs[msg_idx].len, map_dirn);
655 if (dma_mapping_error(gi2c->se.dev->parent, addr)) {
656 i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false);
657 ret = -ENOMEM;
658 goto out;
659 }
660
661 if (gi2c->is_tx_multi_desc_xfer) {
662 flags = DMA_CTRL_ACK;
663
664 /* BEI bit to be cleared for last TRE */
665 if (msg_idx == gi2c->num_msgs - 1)
666 flags |= DMA_PREP_INTERRUPT;
667 } else {
668 flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
669 }
670
671 /* set the length as message for rx txn */
672 peripheral->rx_len = msgs[msg_idx].len;
673 peripheral->op = op;
674
675 ret = dmaengine_slave_config(dma_chan, config);
676 if (ret) {
677 dev_err(gi2c->se.dev, "dma config error: %d for op:%d\n", ret, op);
678 goto err_config;
679 }
680
681 peripheral->set_config = 0;
682 peripheral->multi_msg = true;
683
684 if (op == I2C_WRITE)
685 dma_dirn = DMA_MEM_TO_DEV;
686 else
687 dma_dirn = DMA_DEV_TO_MEM;
688
689 desc = dmaengine_prep_slave_single(dma_chan, addr, msgs[msg_idx].len,
690 dma_dirn, flags);
691 if (!desc && !(flags & DMA_PREP_INTERRUPT)) {
692 /* Retry with interrupt if not enough TREs */
693 flags |= DMA_PREP_INTERRUPT;
694 desc = dmaengine_prep_slave_single(dma_chan, addr, msgs[msg_idx].len,
695 dma_dirn, flags);
696 }
697
698 if (!desc) {
699 dev_err(gi2c->se.dev, "prep_slave_sg failed\n");
700 ret = -EIO;
701 goto err_config;
702 }
703
704 desc->callback_result = i2c_gpi_cb_result;
705 desc->callback_param = gi2c;
706
707 if (!((msgs[msg_idx].flags & I2C_M_RD) && op == I2C_WRITE))
708 gi2c_gpi_xfer->msg_idx_cnt++;
709
710 cookie = dmaengine_submit(desc);
711 if (dma_submit_error(cookie)) {
712 dev_err(gi2c->se.dev,
713 "%s: dmaengine_submit failed (%d)\n", __func__, cookie);
714 ret = -EINVAL;
715 goto err_config;
716 }
717
718 if (gi2c->is_tx_multi_desc_xfer) {
719 gi2c_gpi_xfer->dma_buf[msg_idx] = dma_buf;
720 gi2c_gpi_xfer->dma_addr[msg_idx] = addr;
721
722 dma_async_issue_pending(gi2c->tx_c);
723
724 if ((msg_idx == (gi2c->num_msgs - 1)) || flags & DMA_PREP_INTERRUPT) {
725 ret = geni_i2c_gpi_multi_xfer_timeout_handler(gi2c->se.dev, gi2c_gpi_xfer,
726 XFER_TIMEOUT, &gi2c->done);
727 if (ret) {
728 dev_err(gi2c->se.dev,
729 "I2C multi write msg transfer timeout: %d\n",
730 ret);
731 gi2c->err = ret;
732 return ret;
733 }
734 }
735 } else {
736 /* Non multi descriptor message transfer */
737 *buf = dma_buf;
738 *dma_addr_p = addr;
739 }
740 return 0;
741
742 err_config:
743 dma_unmap_single(gi2c->se.dev->parent, addr,
744 msgs[msg_idx].len, map_dirn);
745 i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false);
746
747 out:
748 gi2c->err = ret;
749 return ret;
750 }
751
geni_i2c_gpi_xfer(struct geni_i2c_dev * gi2c,struct i2c_msg msgs[],int num)752 static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], int num)
753 {
754 struct dma_slave_config config = {};
755 struct gpi_i2c_config peripheral = {};
756 int i, ret = 0;
757 unsigned long time_left;
758 dma_addr_t tx_addr, rx_addr;
759 void *tx_buf = NULL, *rx_buf = NULL;
760 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer;
761 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
762
763 config.peripheral_config = &peripheral;
764 config.peripheral_size = sizeof(peripheral);
765
766 peripheral.pack_enable = I2C_PACK_TX | I2C_PACK_RX;
767 peripheral.cycle_count = itr->t_cycle_cnt;
768 peripheral.high_count = itr->t_high_cnt;
769 peripheral.low_count = itr->t_low_cnt;
770 peripheral.clk_div = itr->clk_div;
771 peripheral.set_config = 1;
772 peripheral.multi_msg = false;
773
774 gi2c->num_msgs = num;
775 gi2c->is_tx_multi_desc_xfer = false;
776
777 tx_multi_xfer = &gi2c->i2c_multi_desc_config;
778 memset(tx_multi_xfer, 0, sizeof(struct geni_i2c_gpi_multi_desc_xfer));
779
780 /*
781 * If number of write messages are two and higher then
782 * configure hardware for multi descriptor transfers with BEI.
783 */
784 if (num >= QCOM_I2C_MIN_NUM_OF_MSGS_MULTI_DESC) {
785 gi2c->is_tx_multi_desc_xfer = true;
786 for (i = 0; i < num; i++) {
787 if (msgs[i].flags & I2C_M_RD) {
788 /*
789 * Multi descriptor transfer with BEI
790 * support is enabled for write transfers.
791 * TODO: Add BEI optimization support for
792 * read transfers later.
793 */
794 gi2c->is_tx_multi_desc_xfer = false;
795 break;
796 }
797 }
798 }
799
800 if (gi2c->is_tx_multi_desc_xfer) {
801 tx_multi_xfer->dma_buf = kcalloc(num, sizeof(void *), GFP_KERNEL);
802 tx_multi_xfer->dma_addr = kcalloc(num, sizeof(dma_addr_t), GFP_KERNEL);
803 if (!tx_multi_xfer->dma_buf || !tx_multi_xfer->dma_addr) {
804 ret = -ENOMEM;
805 goto err;
806 }
807 }
808
809 for (i = 0; i < num; i++) {
810 gi2c->cur = &msgs[i];
811 gi2c->err = 0;
812 dev_dbg(gi2c->se.dev, "msg[%d].len:%d\n", i, gi2c->cur->len);
813
814 peripheral.stretch = 0;
815 if (i < num - 1)
816 peripheral.stretch = 1;
817
818 peripheral.addr = msgs[i].addr;
819 if (i > 0 && (!(msgs[i].flags & I2C_M_RD)))
820 peripheral.multi_msg = false;
821
822 ret = geni_i2c_gpi(gi2c, msgs, &config,
823 &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c);
824 if (ret)
825 goto err;
826
827 if (msgs[i].flags & I2C_M_RD) {
828 ret = geni_i2c_gpi(gi2c, msgs, &config,
829 &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c);
830 if (ret)
831 goto err;
832
833 dma_async_issue_pending(gi2c->rx_c);
834 }
835
836 if (!gi2c->is_tx_multi_desc_xfer) {
837 dma_async_issue_pending(gi2c->tx_c);
838 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
839 if (!time_left) {
840 dev_err(gi2c->se.dev, "%s:I2C timeout\n", __func__);
841 gi2c->err = -ETIMEDOUT;
842 }
843 }
844
845 if (gi2c->err) {
846 ret = gi2c->err;
847 goto err;
848 }
849
850 if (!gi2c->is_tx_multi_desc_xfer)
851 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr);
852 else if (tx_multi_xfer->unmap_msg_cnt != tx_multi_xfer->irq_cnt)
853 geni_i2c_gpi_multi_desc_unmap(gi2c, msgs, &peripheral);
854 }
855
856 return num;
857
858 err:
859 dev_err(gi2c->se.dev, "GPI transfer failed: %d\n", ret);
860 dmaengine_terminate_sync(gi2c->rx_c);
861 dmaengine_terminate_sync(gi2c->tx_c);
862 if (gi2c->is_tx_multi_desc_xfer)
863 geni_i2c_gpi_multi_desc_unmap(gi2c, msgs, &peripheral);
864 else
865 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr);
866
867 return ret;
868 }
869
geni_i2c_fifo_xfer(struct geni_i2c_dev * gi2c,struct i2c_msg msgs[],int num)870 static int geni_i2c_fifo_xfer(struct geni_i2c_dev *gi2c,
871 struct i2c_msg msgs[], int num)
872 {
873 int i, ret = 0;
874
875 for (i = 0; i < num; i++) {
876 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0;
877
878 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK);
879
880 gi2c->cur = &msgs[i];
881 if (msgs[i].flags & I2C_M_RD)
882 ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param);
883 else
884 ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param);
885
886 if (ret)
887 return ret;
888 }
889
890 return num;
891 }
892
geni_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)893 static int geni_i2c_xfer(struct i2c_adapter *adap,
894 struct i2c_msg msgs[],
895 int num)
896 {
897 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap);
898 int ret;
899
900 gi2c->err = 0;
901 reinit_completion(&gi2c->done);
902 ret = pm_runtime_get_sync(gi2c->se.dev);
903 if (ret < 0) {
904 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret);
905 pm_runtime_put_noidle(gi2c->se.dev);
906 /* Set device in suspended since resume failed */
907 pm_runtime_set_suspended(gi2c->se.dev);
908 return ret;
909 }
910
911 qcom_geni_i2c_conf(gi2c);
912
913 if (gi2c->gpi_mode)
914 ret = geni_i2c_gpi_xfer(gi2c, msgs, num);
915 else
916 ret = geni_i2c_fifo_xfer(gi2c, msgs, num);
917
918 pm_runtime_put_autosuspend(gi2c->se.dev);
919 gi2c->cur = NULL;
920 gi2c->err = 0;
921 return ret;
922 }
923
geni_i2c_func(struct i2c_adapter * adap)924 static u32 geni_i2c_func(struct i2c_adapter *adap)
925 {
926 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
927 }
928
929 static const struct i2c_algorithm geni_i2c_algo = {
930 .xfer = geni_i2c_xfer,
931 .functionality = geni_i2c_func,
932 };
933
934 #ifdef CONFIG_ACPI
935 static const struct acpi_device_id geni_i2c_acpi_match[] = {
936 { "QCOM0220"},
937 { "QCOM0411" },
938 { }
939 };
940 MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match);
941 #endif
942
release_gpi_dma(struct geni_i2c_dev * gi2c)943 static void release_gpi_dma(struct geni_i2c_dev *gi2c)
944 {
945 if (gi2c->rx_c)
946 dma_release_channel(gi2c->rx_c);
947
948 if (gi2c->tx_c)
949 dma_release_channel(gi2c->tx_c);
950 }
951
setup_gpi_dma(struct geni_i2c_dev * gi2c)952 static int setup_gpi_dma(struct geni_i2c_dev *gi2c)
953 {
954 int ret;
955
956 geni_se_select_mode(&gi2c->se, GENI_GPI_DMA);
957 gi2c->tx_c = dma_request_chan(gi2c->se.dev, "tx");
958 if (IS_ERR(gi2c->tx_c)) {
959 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->tx_c),
960 "Failed to get tx DMA ch\n");
961 goto err_tx;
962 }
963
964 gi2c->rx_c = dma_request_chan(gi2c->se.dev, "rx");
965 if (IS_ERR(gi2c->rx_c)) {
966 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->rx_c),
967 "Failed to get rx DMA ch\n");
968 goto err_rx;
969 }
970
971 dev_dbg(gi2c->se.dev, "Grabbed GPI dma channels\n");
972 return 0;
973
974 err_rx:
975 dma_release_channel(gi2c->tx_c);
976 err_tx:
977 return ret;
978 }
979
geni_i2c_probe(struct platform_device * pdev)980 static int geni_i2c_probe(struct platform_device *pdev)
981 {
982 struct geni_i2c_dev *gi2c;
983 u32 proto, tx_depth, fifo_disable;
984 int ret;
985 struct device *dev = &pdev->dev;
986 const struct geni_i2c_desc *desc = NULL;
987
988 gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL);
989 if (!gi2c)
990 return -ENOMEM;
991
992 gi2c->se.dev = dev;
993 gi2c->se.wrapper = dev_get_drvdata(dev->parent);
994 gi2c->se.base = devm_platform_ioremap_resource(pdev, 0);
995 if (IS_ERR(gi2c->se.base))
996 return PTR_ERR(gi2c->se.base);
997
998 desc = device_get_match_data(&pdev->dev);
999
1000 if (desc && desc->has_core_clk) {
1001 gi2c->core_clk = devm_clk_get(dev, "core");
1002 if (IS_ERR(gi2c->core_clk))
1003 return PTR_ERR(gi2c->core_clk);
1004 }
1005
1006 gi2c->se.clk = devm_clk_get(dev, "se");
1007 if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev))
1008 return PTR_ERR(gi2c->se.clk);
1009
1010 ret = device_property_read_u32(dev, "clock-frequency",
1011 &gi2c->clk_freq_out);
1012 if (ret) {
1013 dev_info(dev, "Bus frequency not specified, default to 100kHz.\n");
1014 gi2c->clk_freq_out = I2C_MAX_STANDARD_MODE_FREQ;
1015 }
1016
1017 if (has_acpi_companion(dev))
1018 ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev));
1019
1020 gi2c->irq = platform_get_irq(pdev, 0);
1021 if (gi2c->irq < 0)
1022 return gi2c->irq;
1023
1024 ret = geni_i2c_clk_map_idx(gi2c);
1025 if (ret)
1026 return dev_err_probe(dev, ret, "Invalid clk frequency %d Hz\n",
1027 gi2c->clk_freq_out);
1028
1029 gi2c->adap.algo = &geni_i2c_algo;
1030 init_completion(&gi2c->done);
1031 spin_lock_init(&gi2c->lock);
1032 platform_set_drvdata(pdev, gi2c);
1033
1034 /* Keep interrupts disabled initially to allow for low-power modes */
1035 ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, IRQF_NO_AUTOEN,
1036 dev_name(dev), gi2c);
1037 if (ret)
1038 return dev_err_probe(dev, ret,
1039 "Request_irq failed: %d\n", gi2c->irq);
1040
1041 i2c_set_adapdata(&gi2c->adap, gi2c);
1042 gi2c->adap.dev.parent = dev;
1043 gi2c->adap.dev.of_node = dev->of_node;
1044 strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
1045
1046 ret = geni_icc_get(&gi2c->se, desc ? desc->icc_ddr : "qup-memory");
1047 if (ret)
1048 return ret;
1049 /*
1050 * Set the bus quota for core and cpu to a reasonable value for
1051 * register access.
1052 * Set quota for DDR based on bus speed.
1053 */
1054 gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1055 gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1056 if (!desc || desc->icc_ddr)
1057 gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out);
1058
1059 ret = geni_icc_set_bw(&gi2c->se);
1060 if (ret)
1061 return ret;
1062
1063 ret = clk_prepare_enable(gi2c->core_clk);
1064 if (ret)
1065 return ret;
1066
1067 ret = geni_se_resources_on(&gi2c->se);
1068 if (ret) {
1069 dev_err_probe(dev, ret, "Error turning on resources\n");
1070 goto err_clk;
1071 }
1072 proto = geni_se_read_proto(&gi2c->se);
1073 if (proto == GENI_SE_INVALID_PROTO) {
1074 ret = geni_load_se_firmware(&gi2c->se, GENI_SE_I2C);
1075 if (ret) {
1076 dev_err_probe(dev, ret, "i2c firmware load failed ret: %d\n", ret);
1077 goto err_resources;
1078 }
1079 } else if (proto != GENI_SE_I2C) {
1080 ret = dev_err_probe(dev, -ENXIO, "Invalid proto %d\n", proto);
1081 goto err_resources;
1082 }
1083
1084 if (desc && desc->no_dma_support) {
1085 fifo_disable = false;
1086 gi2c->no_dma = true;
1087 } else {
1088 fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
1089 }
1090
1091 if (fifo_disable) {
1092 /* FIFO is disabled, so we can only use GPI DMA */
1093 gi2c->gpi_mode = true;
1094 ret = setup_gpi_dma(gi2c);
1095 if (ret)
1096 goto err_resources;
1097
1098 dev_dbg(dev, "Using GPI DMA mode for I2C\n");
1099 } else {
1100 gi2c->gpi_mode = false;
1101 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
1102
1103 /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */
1104 if (!tx_depth && desc)
1105 tx_depth = desc->tx_fifo_depth;
1106
1107 if (!tx_depth) {
1108 ret = dev_err_probe(dev, -EINVAL,
1109 "Invalid TX FIFO depth\n");
1110 goto err_resources;
1111 }
1112
1113 gi2c->tx_wm = tx_depth - 1;
1114 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
1115 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE,
1116 PACKING_BYTES_PW, true, true, true);
1117
1118 dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
1119 }
1120
1121 clk_disable_unprepare(gi2c->core_clk);
1122 ret = geni_se_resources_off(&gi2c->se);
1123 if (ret) {
1124 dev_err_probe(dev, ret, "Error turning off resources\n");
1125 goto err_dma;
1126 }
1127
1128 ret = geni_icc_disable(&gi2c->se);
1129 if (ret)
1130 goto err_dma;
1131
1132 gi2c->suspended = 1;
1133 pm_runtime_set_suspended(gi2c->se.dev);
1134 pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);
1135 pm_runtime_use_autosuspend(gi2c->se.dev);
1136 pm_runtime_enable(gi2c->se.dev);
1137
1138 ret = i2c_add_adapter(&gi2c->adap);
1139 if (ret) {
1140 dev_err_probe(dev, ret, "Error adding i2c adapter\n");
1141 pm_runtime_disable(gi2c->se.dev);
1142 goto err_dma;
1143 }
1144
1145 dev_dbg(dev, "Geni-I2C adaptor successfully added\n");
1146
1147 return ret;
1148
1149 err_resources:
1150 geni_se_resources_off(&gi2c->se);
1151 err_clk:
1152 clk_disable_unprepare(gi2c->core_clk);
1153
1154 return ret;
1155
1156 err_dma:
1157 release_gpi_dma(gi2c);
1158
1159 return ret;
1160 }
1161
geni_i2c_remove(struct platform_device * pdev)1162 static void geni_i2c_remove(struct platform_device *pdev)
1163 {
1164 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
1165
1166 i2c_del_adapter(&gi2c->adap);
1167 release_gpi_dma(gi2c);
1168 pm_runtime_disable(gi2c->se.dev);
1169 }
1170
geni_i2c_shutdown(struct platform_device * pdev)1171 static void geni_i2c_shutdown(struct platform_device *pdev)
1172 {
1173 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
1174
1175 /* Make client i2c transfers start failing */
1176 i2c_mark_adapter_suspended(&gi2c->adap);
1177 }
1178
geni_i2c_runtime_suspend(struct device * dev)1179 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
1180 {
1181 int ret;
1182 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
1183
1184 disable_irq(gi2c->irq);
1185 ret = geni_se_resources_off(&gi2c->se);
1186 if (ret) {
1187 enable_irq(gi2c->irq);
1188 return ret;
1189
1190 } else {
1191 gi2c->suspended = 1;
1192 }
1193
1194 clk_disable_unprepare(gi2c->core_clk);
1195
1196 return geni_icc_disable(&gi2c->se);
1197 }
1198
geni_i2c_runtime_resume(struct device * dev)1199 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
1200 {
1201 int ret;
1202 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
1203
1204 ret = geni_icc_enable(&gi2c->se);
1205 if (ret)
1206 return ret;
1207
1208 ret = clk_prepare_enable(gi2c->core_clk);
1209 if (ret)
1210 goto out_icc_disable;
1211
1212 ret = geni_se_resources_on(&gi2c->se);
1213 if (ret)
1214 goto out_clk_disable;
1215
1216 enable_irq(gi2c->irq);
1217 gi2c->suspended = 0;
1218
1219 return 0;
1220
1221 out_clk_disable:
1222 clk_disable_unprepare(gi2c->core_clk);
1223 out_icc_disable:
1224 geni_icc_disable(&gi2c->se);
1225
1226 return ret;
1227 }
1228
geni_i2c_suspend_noirq(struct device * dev)1229 static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev)
1230 {
1231 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
1232
1233 i2c_mark_adapter_suspended(&gi2c->adap);
1234
1235 if (!gi2c->suspended) {
1236 geni_i2c_runtime_suspend(dev);
1237 pm_runtime_disable(dev);
1238 pm_runtime_set_suspended(dev);
1239 pm_runtime_enable(dev);
1240 }
1241 return 0;
1242 }
1243
geni_i2c_resume_noirq(struct device * dev)1244 static int __maybe_unused geni_i2c_resume_noirq(struct device *dev)
1245 {
1246 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
1247
1248 i2c_mark_adapter_resumed(&gi2c->adap);
1249 return 0;
1250 }
1251
1252 static const struct dev_pm_ops geni_i2c_pm_ops = {
1253 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, geni_i2c_resume_noirq)
1254 SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume,
1255 NULL)
1256 };
1257
1258 static const struct geni_i2c_desc i2c_master_hub = {
1259 .has_core_clk = true,
1260 .icc_ddr = NULL,
1261 .no_dma_support = true,
1262 .tx_fifo_depth = 16,
1263 };
1264
1265 static const struct of_device_id geni_i2c_dt_match[] = {
1266 { .compatible = "qcom,geni-i2c" },
1267 { .compatible = "qcom,geni-i2c-master-hub", .data = &i2c_master_hub },
1268 {}
1269 };
1270 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match);
1271
1272 static struct platform_driver geni_i2c_driver = {
1273 .probe = geni_i2c_probe,
1274 .remove = geni_i2c_remove,
1275 .shutdown = geni_i2c_shutdown,
1276 .driver = {
1277 .name = "geni_i2c",
1278 .pm = &geni_i2c_pm_ops,
1279 .of_match_table = geni_i2c_dt_match,
1280 .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match),
1281 },
1282 };
1283
1284 module_platform_driver(geni_i2c_driver);
1285
1286 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores");
1287 MODULE_LICENSE("GPL v2");
1288