1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI support in ACPI 4 * 5 * Copyright (C) 2005 David Shaohua Li <shaohua.li@intel.com> 6 * Copyright (C) 2004 Tom Long Nguyen <tom.l.nguyen@intel.com> 7 * Copyright (C) 2004 Intel Corp. 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/init.h> 12 #include <linux/iommu.h> 13 #include <linux/irqdomain.h> 14 #include <linux/pci.h> 15 #include <linux/msi.h> 16 #include <linux/pci_hotplug.h> 17 #include <linux/module.h> 18 #include <linux/pci-acpi.h> 19 #include <linux/pci-ecam.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/pm_qos.h> 22 #include <linux/rwsem.h> 23 #include "pci.h" 24 25 /* 26 * The GUID is defined in the PCI Firmware Specification available 27 * here to PCI-SIG members: 28 * https://members.pcisig.com/wg/PCI-SIG/document/15350 29 */ 30 const guid_t pci_acpi_dsm_guid = 31 GUID_INIT(0xe5c937d0, 0x3553, 0x4d7a, 32 0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d); 33 34 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 35 static int acpi_get_rc_addr(struct acpi_device *adev, struct resource *res) 36 { 37 struct device *dev = &adev->dev; 38 struct resource_entry *entry; 39 struct list_head list; 40 unsigned long flags; 41 int ret; 42 43 INIT_LIST_HEAD(&list); 44 flags = IORESOURCE_MEM; 45 ret = acpi_dev_get_resources(adev, &list, 46 acpi_dev_filter_resource_type_cb, 47 (void *) flags); 48 if (ret < 0) { 49 dev_err(dev, "failed to parse _CRS method, error code %d\n", 50 ret); 51 return ret; 52 } 53 54 if (ret == 0) { 55 dev_err(dev, "no IO and memory resources present in _CRS\n"); 56 return -EINVAL; 57 } 58 59 entry = list_first_entry(&list, struct resource_entry, node); 60 *res = *entry->res; 61 acpi_dev_free_resource_list(&list); 62 return 0; 63 } 64 65 static acpi_status acpi_match_rc(acpi_handle handle, u32 lvl, void *context, 66 void **retval) 67 { 68 u16 *segment = context; 69 unsigned long long uid; 70 acpi_status status; 71 72 status = acpi_evaluate_integer(handle, METHOD_NAME__UID, NULL, &uid); 73 if (ACPI_FAILURE(status) || uid != *segment) 74 return AE_CTRL_DEPTH; 75 76 *(acpi_handle *)retval = handle; 77 return AE_CTRL_TERMINATE; 78 } 79 80 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 81 struct resource *res) 82 { 83 struct acpi_device *adev; 84 acpi_status status; 85 acpi_handle handle; 86 int ret; 87 88 status = acpi_get_devices(hid, acpi_match_rc, &segment, &handle); 89 if (ACPI_FAILURE(status)) { 90 dev_err(dev, "can't find _HID %s device to locate resources\n", 91 hid); 92 return -ENODEV; 93 } 94 95 adev = acpi_fetch_acpi_dev(handle); 96 if (!adev) 97 return -ENODEV; 98 99 ret = acpi_get_rc_addr(adev, res); 100 if (ret) { 101 dev_err(dev, "can't get resource from %s\n", 102 dev_name(&adev->dev)); 103 return ret; 104 } 105 106 return 0; 107 } 108 #endif 109 110 phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle) 111 { 112 acpi_status status = AE_NOT_EXIST; 113 unsigned long long mcfg_addr; 114 115 if (handle) 116 status = acpi_evaluate_integer(handle, METHOD_NAME__CBA, 117 NULL, &mcfg_addr); 118 if (ACPI_FAILURE(status)) 119 return 0; 120 121 return (phys_addr_t)mcfg_addr; 122 } 123 124 bool pci_acpi_preserve_config(struct pci_host_bridge *host_bridge) 125 { 126 bool ret = false; 127 128 if (ACPI_HANDLE(&host_bridge->dev)) { 129 union acpi_object *obj; 130 131 /* 132 * Evaluate the "PCI Boot Configuration" _DSM Function. If it 133 * exists and returns 0, we must preserve any PCI resource 134 * assignments made by firmware for this host bridge. 135 */ 136 obj = acpi_evaluate_dsm_typed(ACPI_HANDLE(&host_bridge->dev), 137 &pci_acpi_dsm_guid, 138 1, DSM_PCI_PRESERVE_BOOT_CONFIG, 139 NULL, ACPI_TYPE_INTEGER); 140 if (obj && obj->integer.value == 0) 141 ret = true; 142 ACPI_FREE(obj); 143 } 144 145 return ret; 146 } 147 148 /* _HPX PCI Setting Record (Type 0); same as _HPP */ 149 struct hpx_type0 { 150 u32 revision; /* Not present in _HPP */ 151 u8 cache_line_size; /* Not applicable to PCIe */ 152 u8 latency_timer; /* Not applicable to PCIe */ 153 u8 enable_serr; 154 u8 enable_perr; 155 }; 156 157 static struct hpx_type0 pci_default_type0 = { 158 .revision = 1, 159 .cache_line_size = 8, 160 .latency_timer = 0x40, 161 .enable_serr = 0, 162 .enable_perr = 0, 163 }; 164 165 static void program_hpx_type0(struct pci_dev *dev, struct hpx_type0 *hpx) 166 { 167 u16 pci_cmd, pci_bctl; 168 169 if (!hpx) 170 hpx = &pci_default_type0; 171 172 if (hpx->revision > 1) { 173 pci_warn(dev, "PCI settings rev %d not supported; using defaults\n", 174 hpx->revision); 175 hpx = &pci_default_type0; 176 } 177 178 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpx->cache_line_size); 179 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpx->latency_timer); 180 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); 181 if (hpx->enable_serr) 182 pci_cmd |= PCI_COMMAND_SERR; 183 if (hpx->enable_perr) 184 pci_cmd |= PCI_COMMAND_PARITY; 185 pci_write_config_word(dev, PCI_COMMAND, pci_cmd); 186 187 /* Program bridge control value */ 188 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 189 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 190 hpx->latency_timer); 191 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl); 192 if (hpx->enable_perr) 193 pci_bctl |= PCI_BRIDGE_CTL_PARITY; 194 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl); 195 } 196 } 197 198 static acpi_status decode_type0_hpx_record(union acpi_object *record, 199 struct hpx_type0 *hpx0) 200 { 201 int i; 202 union acpi_object *fields = record->package.elements; 203 u32 revision = fields[1].integer.value; 204 205 switch (revision) { 206 case 1: 207 if (record->package.count != 6) 208 return AE_ERROR; 209 for (i = 2; i < 6; i++) 210 if (fields[i].type != ACPI_TYPE_INTEGER) 211 return AE_ERROR; 212 hpx0->revision = revision; 213 hpx0->cache_line_size = fields[2].integer.value; 214 hpx0->latency_timer = fields[3].integer.value; 215 hpx0->enable_serr = fields[4].integer.value; 216 hpx0->enable_perr = fields[5].integer.value; 217 break; 218 default: 219 pr_warn("%s: Type 0 Revision %d record not supported\n", 220 __func__, revision); 221 return AE_ERROR; 222 } 223 return AE_OK; 224 } 225 226 /* _HPX PCI-X Setting Record (Type 1) */ 227 struct hpx_type1 { 228 u32 revision; 229 u8 max_mem_read; 230 u8 avg_max_split; 231 u16 tot_max_split; 232 }; 233 234 static void program_hpx_type1(struct pci_dev *dev, struct hpx_type1 *hpx) 235 { 236 int pos; 237 238 if (!hpx) 239 return; 240 241 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 242 if (!pos) 243 return; 244 245 pci_warn(dev, "PCI-X settings not supported\n"); 246 } 247 248 static acpi_status decode_type1_hpx_record(union acpi_object *record, 249 struct hpx_type1 *hpx1) 250 { 251 int i; 252 union acpi_object *fields = record->package.elements; 253 u32 revision = fields[1].integer.value; 254 255 switch (revision) { 256 case 1: 257 if (record->package.count != 5) 258 return AE_ERROR; 259 for (i = 2; i < 5; i++) 260 if (fields[i].type != ACPI_TYPE_INTEGER) 261 return AE_ERROR; 262 hpx1->revision = revision; 263 hpx1->max_mem_read = fields[2].integer.value; 264 hpx1->avg_max_split = fields[3].integer.value; 265 hpx1->tot_max_split = fields[4].integer.value; 266 break; 267 default: 268 pr_warn("%s: Type 1 Revision %d record not supported\n", 269 __func__, revision); 270 return AE_ERROR; 271 } 272 return AE_OK; 273 } 274 275 /* _HPX PCI Express Setting Record (Type 2) */ 276 struct hpx_type2 { 277 u32 revision; 278 u32 unc_err_mask_and; 279 u32 unc_err_mask_or; 280 u32 unc_err_sever_and; 281 u32 unc_err_sever_or; 282 u32 cor_err_mask_and; 283 u32 cor_err_mask_or; 284 u32 adv_err_cap_and; 285 u32 adv_err_cap_or; 286 u16 pci_exp_devctl_and; 287 u16 pci_exp_devctl_or; 288 u16 pci_exp_lnkctl_and; 289 u16 pci_exp_lnkctl_or; 290 u32 sec_unc_err_sever_and; 291 u32 sec_unc_err_sever_or; 292 u32 sec_unc_err_mask_and; 293 u32 sec_unc_err_mask_or; 294 }; 295 296 static void program_hpx_type2(struct pci_dev *dev, struct hpx_type2 *hpx) 297 { 298 int pos; 299 u32 reg32; 300 const struct pci_host_bridge *host; 301 302 if (!hpx) 303 return; 304 305 if (!pci_is_pcie(dev)) 306 return; 307 308 host = pci_find_host_bridge(dev->bus); 309 310 /* 311 * Only do the _HPX Type 2 programming if OS owns PCIe native 312 * hotplug but not AER. 313 */ 314 if (!host->native_pcie_hotplug || host->native_aer) 315 return; 316 317 if (hpx->revision > 1) { 318 pci_warn(dev, "PCIe settings rev %d not supported\n", 319 hpx->revision); 320 return; 321 } 322 323 /* 324 * We only allow _HPX to program DEVCTL bits related to AER, namely 325 * PCI_EXP_DEVCTL_CERE, PCI_EXP_DEVCTL_NFERE, PCI_EXP_DEVCTL_FERE, 326 * and PCI_EXP_DEVCTL_URRE. 327 * 328 * The rest of DEVCTL is managed by the OS to make sure it's 329 * consistent with the rest of the platform. 330 */ 331 hpx->pci_exp_devctl_and |= ~PCI_EXP_AER_FLAGS; 332 hpx->pci_exp_devctl_or &= PCI_EXP_AER_FLAGS; 333 334 /* Initialize Device Control Register */ 335 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, 336 ~hpx->pci_exp_devctl_and, hpx->pci_exp_devctl_or); 337 338 /* Log if _HPX attempts to modify Link Control Register */ 339 if (pcie_cap_has_lnkctl(dev)) { 340 if (hpx->pci_exp_lnkctl_and != 0xffff || 341 hpx->pci_exp_lnkctl_or != 0) 342 pci_info(dev, "_HPX attempts Link Control setting (AND %#06x OR %#06x)\n", 343 hpx->pci_exp_lnkctl_and, 344 hpx->pci_exp_lnkctl_or); 345 } 346 347 /* Find Advanced Error Reporting Enhanced Capability */ 348 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 349 if (!pos) 350 return; 351 352 /* Initialize Uncorrectable Error Mask Register */ 353 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32); 354 reg32 = (reg32 & hpx->unc_err_mask_and) | hpx->unc_err_mask_or; 355 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); 356 357 /* Initialize Uncorrectable Error Severity Register */ 358 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32); 359 reg32 = (reg32 & hpx->unc_err_sever_and) | hpx->unc_err_sever_or; 360 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); 361 362 /* Initialize Correctable Error Mask Register */ 363 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32); 364 reg32 = (reg32 & hpx->cor_err_mask_and) | hpx->cor_err_mask_or; 365 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); 366 367 /* Initialize Advanced Error Capabilities and Control Register */ 368 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32); 369 reg32 = (reg32 & hpx->adv_err_cap_and) | hpx->adv_err_cap_or; 370 371 /* Don't enable ECRC generation or checking if unsupported */ 372 if (!(reg32 & PCI_ERR_CAP_ECRC_GENC)) 373 reg32 &= ~PCI_ERR_CAP_ECRC_GENE; 374 if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC)) 375 reg32 &= ~PCI_ERR_CAP_ECRC_CHKE; 376 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32); 377 378 /* 379 * FIXME: The following two registers are not supported yet. 380 * 381 * o Secondary Uncorrectable Error Severity Register 382 * o Secondary Uncorrectable Error Mask Register 383 */ 384 } 385 386 static acpi_status decode_type2_hpx_record(union acpi_object *record, 387 struct hpx_type2 *hpx2) 388 { 389 int i; 390 union acpi_object *fields = record->package.elements; 391 u32 revision = fields[1].integer.value; 392 393 switch (revision) { 394 case 1: 395 if (record->package.count != 18) 396 return AE_ERROR; 397 for (i = 2; i < 18; i++) 398 if (fields[i].type != ACPI_TYPE_INTEGER) 399 return AE_ERROR; 400 hpx2->revision = revision; 401 hpx2->unc_err_mask_and = fields[2].integer.value; 402 hpx2->unc_err_mask_or = fields[3].integer.value; 403 hpx2->unc_err_sever_and = fields[4].integer.value; 404 hpx2->unc_err_sever_or = fields[5].integer.value; 405 hpx2->cor_err_mask_and = fields[6].integer.value; 406 hpx2->cor_err_mask_or = fields[7].integer.value; 407 hpx2->adv_err_cap_and = fields[8].integer.value; 408 hpx2->adv_err_cap_or = fields[9].integer.value; 409 hpx2->pci_exp_devctl_and = fields[10].integer.value; 410 hpx2->pci_exp_devctl_or = fields[11].integer.value; 411 hpx2->pci_exp_lnkctl_and = fields[12].integer.value; 412 hpx2->pci_exp_lnkctl_or = fields[13].integer.value; 413 hpx2->sec_unc_err_sever_and = fields[14].integer.value; 414 hpx2->sec_unc_err_sever_or = fields[15].integer.value; 415 hpx2->sec_unc_err_mask_and = fields[16].integer.value; 416 hpx2->sec_unc_err_mask_or = fields[17].integer.value; 417 break; 418 default: 419 pr_warn("%s: Type 2 Revision %d record not supported\n", 420 __func__, revision); 421 return AE_ERROR; 422 } 423 return AE_OK; 424 } 425 426 /* _HPX PCI Express Setting Record (Type 3) */ 427 struct hpx_type3 { 428 u16 device_type; 429 u16 function_type; 430 u16 config_space_location; 431 u16 pci_exp_cap_id; 432 u16 pci_exp_cap_ver; 433 u16 pci_exp_vendor_id; 434 u16 dvsec_id; 435 u16 dvsec_rev; 436 u16 match_offset; 437 u32 match_mask_and; 438 u32 match_value; 439 u16 reg_offset; 440 u32 reg_mask_and; 441 u32 reg_mask_or; 442 }; 443 444 enum hpx_type3_dev_type { 445 HPX_TYPE_ENDPOINT = BIT(0), 446 HPX_TYPE_LEG_END = BIT(1), 447 HPX_TYPE_RC_END = BIT(2), 448 HPX_TYPE_RC_EC = BIT(3), 449 HPX_TYPE_ROOT_PORT = BIT(4), 450 HPX_TYPE_UPSTREAM = BIT(5), 451 HPX_TYPE_DOWNSTREAM = BIT(6), 452 HPX_TYPE_PCI_BRIDGE = BIT(7), 453 HPX_TYPE_PCIE_BRIDGE = BIT(8), 454 }; 455 456 static u16 hpx3_device_type(struct pci_dev *dev) 457 { 458 u16 pcie_type = pci_pcie_type(dev); 459 static const int pcie_to_hpx3_type[] = { 460 [PCI_EXP_TYPE_ENDPOINT] = HPX_TYPE_ENDPOINT, 461 [PCI_EXP_TYPE_LEG_END] = HPX_TYPE_LEG_END, 462 [PCI_EXP_TYPE_RC_END] = HPX_TYPE_RC_END, 463 [PCI_EXP_TYPE_RC_EC] = HPX_TYPE_RC_EC, 464 [PCI_EXP_TYPE_ROOT_PORT] = HPX_TYPE_ROOT_PORT, 465 [PCI_EXP_TYPE_UPSTREAM] = HPX_TYPE_UPSTREAM, 466 [PCI_EXP_TYPE_DOWNSTREAM] = HPX_TYPE_DOWNSTREAM, 467 [PCI_EXP_TYPE_PCI_BRIDGE] = HPX_TYPE_PCI_BRIDGE, 468 [PCI_EXP_TYPE_PCIE_BRIDGE] = HPX_TYPE_PCIE_BRIDGE, 469 }; 470 471 if (pcie_type >= ARRAY_SIZE(pcie_to_hpx3_type)) 472 return 0; 473 474 return pcie_to_hpx3_type[pcie_type]; 475 } 476 477 enum hpx_type3_fn_type { 478 HPX_FN_NORMAL = BIT(0), 479 HPX_FN_SRIOV_PHYS = BIT(1), 480 HPX_FN_SRIOV_VIRT = BIT(2), 481 }; 482 483 static u8 hpx3_function_type(struct pci_dev *dev) 484 { 485 if (dev->is_virtfn) 486 return HPX_FN_SRIOV_VIRT; 487 else if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV) > 0) 488 return HPX_FN_SRIOV_PHYS; 489 else 490 return HPX_FN_NORMAL; 491 } 492 493 static bool hpx3_cap_ver_matches(u8 pcie_cap_id, u8 hpx3_cap_id) 494 { 495 u8 cap_ver = hpx3_cap_id & 0xf; 496 497 if ((hpx3_cap_id & BIT(4)) && cap_ver >= pcie_cap_id) 498 return true; 499 else if (cap_ver == pcie_cap_id) 500 return true; 501 502 return false; 503 } 504 505 enum hpx_type3_cfg_loc { 506 HPX_CFG_PCICFG = 0, 507 HPX_CFG_PCIE_CAP = 1, 508 HPX_CFG_PCIE_CAP_EXT = 2, 509 HPX_CFG_VEND_CAP = 3, 510 HPX_CFG_DVSEC = 4, 511 HPX_CFG_MAX, 512 }; 513 514 static void program_hpx_type3_register(struct pci_dev *dev, 515 const struct hpx_type3 *reg) 516 { 517 u32 match_reg, write_reg, header, orig_value; 518 u16 pos; 519 520 if (!(hpx3_device_type(dev) & reg->device_type)) 521 return; 522 523 if (!(hpx3_function_type(dev) & reg->function_type)) 524 return; 525 526 switch (reg->config_space_location) { 527 case HPX_CFG_PCICFG: 528 pos = 0; 529 break; 530 case HPX_CFG_PCIE_CAP: 531 pos = pci_find_capability(dev, reg->pci_exp_cap_id); 532 if (pos == 0) 533 return; 534 535 break; 536 case HPX_CFG_PCIE_CAP_EXT: 537 pos = pci_find_ext_capability(dev, reg->pci_exp_cap_id); 538 if (pos == 0) 539 return; 540 541 pci_read_config_dword(dev, pos, &header); 542 if (!hpx3_cap_ver_matches(PCI_EXT_CAP_VER(header), 543 reg->pci_exp_cap_ver)) 544 return; 545 546 break; 547 case HPX_CFG_VEND_CAP: 548 case HPX_CFG_DVSEC: 549 default: 550 pci_warn(dev, "Encountered _HPX type 3 with unsupported config space location"); 551 return; 552 } 553 554 pci_read_config_dword(dev, pos + reg->match_offset, &match_reg); 555 556 if ((match_reg & reg->match_mask_and) != reg->match_value) 557 return; 558 559 pci_read_config_dword(dev, pos + reg->reg_offset, &write_reg); 560 orig_value = write_reg; 561 write_reg &= reg->reg_mask_and; 562 write_reg |= reg->reg_mask_or; 563 564 if (orig_value == write_reg) 565 return; 566 567 pci_write_config_dword(dev, pos + reg->reg_offset, write_reg); 568 569 pci_dbg(dev, "Applied _HPX3 at [0x%x]: 0x%08x -> 0x%08x", 570 pos, orig_value, write_reg); 571 } 572 573 static void program_hpx_type3(struct pci_dev *dev, struct hpx_type3 *hpx) 574 { 575 if (!hpx) 576 return; 577 578 if (!pci_is_pcie(dev)) 579 return; 580 581 program_hpx_type3_register(dev, hpx); 582 } 583 584 static void parse_hpx3_register(struct hpx_type3 *hpx3_reg, 585 union acpi_object *reg_fields) 586 { 587 hpx3_reg->device_type = reg_fields[0].integer.value; 588 hpx3_reg->function_type = reg_fields[1].integer.value; 589 hpx3_reg->config_space_location = reg_fields[2].integer.value; 590 hpx3_reg->pci_exp_cap_id = reg_fields[3].integer.value; 591 hpx3_reg->pci_exp_cap_ver = reg_fields[4].integer.value; 592 hpx3_reg->pci_exp_vendor_id = reg_fields[5].integer.value; 593 hpx3_reg->dvsec_id = reg_fields[6].integer.value; 594 hpx3_reg->dvsec_rev = reg_fields[7].integer.value; 595 hpx3_reg->match_offset = reg_fields[8].integer.value; 596 hpx3_reg->match_mask_and = reg_fields[9].integer.value; 597 hpx3_reg->match_value = reg_fields[10].integer.value; 598 hpx3_reg->reg_offset = reg_fields[11].integer.value; 599 hpx3_reg->reg_mask_and = reg_fields[12].integer.value; 600 hpx3_reg->reg_mask_or = reg_fields[13].integer.value; 601 } 602 603 static acpi_status program_type3_hpx_record(struct pci_dev *dev, 604 union acpi_object *record) 605 { 606 union acpi_object *fields = record->package.elements; 607 u32 desc_count, expected_length, revision; 608 union acpi_object *reg_fields; 609 struct hpx_type3 hpx3; 610 int i; 611 612 revision = fields[1].integer.value; 613 switch (revision) { 614 case 1: 615 desc_count = fields[2].integer.value; 616 expected_length = 3 + desc_count * 14; 617 618 if (record->package.count != expected_length) 619 return AE_ERROR; 620 621 for (i = 2; i < expected_length; i++) 622 if (fields[i].type != ACPI_TYPE_INTEGER) 623 return AE_ERROR; 624 625 for (i = 0; i < desc_count; i++) { 626 reg_fields = fields + 3 + i * 14; 627 parse_hpx3_register(&hpx3, reg_fields); 628 program_hpx_type3(dev, &hpx3); 629 } 630 631 break; 632 default: 633 printk(KERN_WARNING 634 "%s: Type 3 Revision %d record not supported\n", 635 __func__, revision); 636 return AE_ERROR; 637 } 638 return AE_OK; 639 } 640 641 static acpi_status acpi_run_hpx(struct pci_dev *dev, acpi_handle handle) 642 { 643 acpi_status status; 644 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; 645 union acpi_object *package, *record, *fields; 646 struct hpx_type0 hpx0; 647 struct hpx_type1 hpx1; 648 struct hpx_type2 hpx2; 649 u32 type; 650 int i; 651 652 status = acpi_evaluate_object(handle, "_HPX", NULL, &buffer); 653 if (ACPI_FAILURE(status)) 654 return status; 655 656 package = (union acpi_object *)buffer.pointer; 657 if (package->type != ACPI_TYPE_PACKAGE) { 658 status = AE_ERROR; 659 goto exit; 660 } 661 662 for (i = 0; i < package->package.count; i++) { 663 record = &package->package.elements[i]; 664 if (record->type != ACPI_TYPE_PACKAGE) { 665 status = AE_ERROR; 666 goto exit; 667 } 668 669 fields = record->package.elements; 670 if (fields[0].type != ACPI_TYPE_INTEGER || 671 fields[1].type != ACPI_TYPE_INTEGER) { 672 status = AE_ERROR; 673 goto exit; 674 } 675 676 type = fields[0].integer.value; 677 switch (type) { 678 case 0: 679 memset(&hpx0, 0, sizeof(hpx0)); 680 status = decode_type0_hpx_record(record, &hpx0); 681 if (ACPI_FAILURE(status)) 682 goto exit; 683 program_hpx_type0(dev, &hpx0); 684 break; 685 case 1: 686 memset(&hpx1, 0, sizeof(hpx1)); 687 status = decode_type1_hpx_record(record, &hpx1); 688 if (ACPI_FAILURE(status)) 689 goto exit; 690 program_hpx_type1(dev, &hpx1); 691 break; 692 case 2: 693 memset(&hpx2, 0, sizeof(hpx2)); 694 status = decode_type2_hpx_record(record, &hpx2); 695 if (ACPI_FAILURE(status)) 696 goto exit; 697 program_hpx_type2(dev, &hpx2); 698 break; 699 case 3: 700 status = program_type3_hpx_record(dev, record); 701 if (ACPI_FAILURE(status)) 702 goto exit; 703 break; 704 default: 705 pr_err("%s: Type %d record not supported\n", 706 __func__, type); 707 status = AE_ERROR; 708 goto exit; 709 } 710 } 711 exit: 712 kfree(buffer.pointer); 713 return status; 714 } 715 716 static acpi_status acpi_run_hpp(struct pci_dev *dev, acpi_handle handle) 717 { 718 acpi_status status; 719 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 720 union acpi_object *package, *fields; 721 struct hpx_type0 hpx0; 722 int i; 723 724 memset(&hpx0, 0, sizeof(hpx0)); 725 726 status = acpi_evaluate_object(handle, "_HPP", NULL, &buffer); 727 if (ACPI_FAILURE(status)) 728 return status; 729 730 package = (union acpi_object *) buffer.pointer; 731 if (package->type != ACPI_TYPE_PACKAGE || 732 package->package.count != 4) { 733 status = AE_ERROR; 734 goto exit; 735 } 736 737 fields = package->package.elements; 738 for (i = 0; i < 4; i++) { 739 if (fields[i].type != ACPI_TYPE_INTEGER) { 740 status = AE_ERROR; 741 goto exit; 742 } 743 } 744 745 hpx0.revision = 1; 746 hpx0.cache_line_size = fields[0].integer.value; 747 hpx0.latency_timer = fields[1].integer.value; 748 hpx0.enable_serr = fields[2].integer.value; 749 hpx0.enable_perr = fields[3].integer.value; 750 751 program_hpx_type0(dev, &hpx0); 752 753 exit: 754 kfree(buffer.pointer); 755 return status; 756 } 757 758 /* pci_acpi_program_hp_params 759 * 760 * @dev - the pci_dev for which we want parameters 761 */ 762 int pci_acpi_program_hp_params(struct pci_dev *dev) 763 { 764 acpi_status status; 765 acpi_handle handle, phandle; 766 struct pci_bus *pbus; 767 768 if (acpi_pci_disabled) 769 return -ENODEV; 770 771 handle = NULL; 772 for (pbus = dev->bus; pbus; pbus = pbus->parent) { 773 handle = acpi_pci_get_bridge_handle(pbus); 774 if (handle) 775 break; 776 } 777 778 /* 779 * _HPP settings apply to all child buses, until another _HPP is 780 * encountered. If we don't find an _HPP for the input pci dev, 781 * look for it in the parent device scope since that would apply to 782 * this pci dev. 783 */ 784 while (handle) { 785 status = acpi_run_hpx(dev, handle); 786 if (ACPI_SUCCESS(status)) 787 return 0; 788 status = acpi_run_hpp(dev, handle); 789 if (ACPI_SUCCESS(status)) 790 return 0; 791 if (acpi_is_root_bridge(handle)) 792 break; 793 status = acpi_get_parent(handle, &phandle); 794 if (ACPI_FAILURE(status)) 795 break; 796 handle = phandle; 797 } 798 return -ENODEV; 799 } 800 801 /** 802 * pciehp_is_native - Check whether a hotplug port is handled by the OS 803 * @bridge: Hotplug port to check 804 * 805 * Returns true if the given @bridge is handled by the native PCIe hotplug 806 * driver. 807 */ 808 bool pciehp_is_native(struct pci_dev *bridge) 809 { 810 const struct pci_host_bridge *host; 811 812 if (!IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)) 813 return false; 814 815 if (pcie_ports_native) 816 return true; 817 818 host = pci_find_host_bridge(bridge->bus); 819 return host->native_pcie_hotplug; 820 } 821 822 /** 823 * shpchp_is_native - Check whether a hotplug port is handled by the OS 824 * @bridge: Hotplug port to check 825 * 826 * Returns true if the given @bridge is handled by the native SHPC hotplug 827 * driver. 828 */ 829 bool shpchp_is_native(struct pci_dev *bridge) 830 { 831 return bridge->shpc_managed; 832 } 833 834 /** 835 * pci_acpi_wake_bus - Root bus wakeup notification fork function. 836 * @context: Device wakeup context. 837 */ 838 static void pci_acpi_wake_bus(struct acpi_device_wakeup_context *context) 839 { 840 pci_pme_wakeup_bus(to_pci_host_bridge(context->dev)->bus); 841 } 842 843 /** 844 * pci_acpi_wake_dev - PCI device wakeup notification work function. 845 * @context: Device wakeup context. 846 */ 847 static void pci_acpi_wake_dev(struct acpi_device_wakeup_context *context) 848 { 849 struct pci_dev *pci_dev; 850 851 pci_dev = to_pci_dev(context->dev); 852 853 if (pci_dev->pme_poll) 854 pci_dev->pme_poll = false; 855 856 if (pci_dev->current_state == PCI_D3cold) { 857 pci_wakeup_event(pci_dev); 858 pm_request_resume(&pci_dev->dev); 859 return; 860 } 861 862 /* Clear PME Status if set. */ 863 if (pci_dev->pme_support) 864 pci_check_pme_status(pci_dev); 865 866 pci_wakeup_event(pci_dev); 867 pm_request_resume(&pci_dev->dev); 868 869 pci_pme_wakeup_bus(pci_dev->subordinate); 870 } 871 872 /** 873 * pci_acpi_add_root_pm_notifier - Register PM notifier for root PCI bus. 874 * @dev: PCI root bridge ACPI device. 875 * @root: PCI root corresponding to @dev. 876 */ 877 acpi_status pci_acpi_add_root_pm_notifier(struct acpi_device *dev, 878 struct acpi_pci_root *root) 879 { 880 return acpi_add_pm_notifier(dev, root->bus->bridge, pci_acpi_wake_bus); 881 } 882 883 /** 884 * pci_acpi_add_pm_notifier - Register PM notifier for given PCI device. 885 * @dev: ACPI device to add the notifier for. 886 * @pci_dev: PCI device to check for the PME status if an event is signaled. 887 */ 888 acpi_status pci_acpi_add_pm_notifier(struct acpi_device *dev, 889 struct pci_dev *pci_dev) 890 { 891 return acpi_add_pm_notifier(dev, &pci_dev->dev, pci_acpi_wake_dev); 892 } 893 894 /* 895 * _SxD returns the D-state with the highest power 896 * (lowest D-state number) supported in the S-state "x". 897 * 898 * If the devices does not have a _PRW 899 * (Power Resources for Wake) supporting system wakeup from "x" 900 * then the OS is free to choose a lower power (higher number 901 * D-state) than the return value from _SxD. 902 * 903 * But if _PRW is enabled at S-state "x", the OS 904 * must not choose a power lower than _SxD -- 905 * unless the device has an _SxW method specifying 906 * the lowest power (highest D-state number) the device 907 * may enter while still able to wake the system. 908 * 909 * ie. depending on global OS policy: 910 * 911 * if (_PRW at S-state x) 912 * choose from highest power _SxD to lowest power _SxW 913 * else // no _PRW at S-state x 914 * choose highest power _SxD or any lower power 915 */ 916 917 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 918 { 919 int acpi_state, d_max; 920 921 if (pdev->no_d3cold || !pdev->d3cold_allowed) 922 d_max = ACPI_STATE_D3_HOT; 923 else 924 d_max = ACPI_STATE_D3_COLD; 925 acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL, d_max); 926 if (acpi_state < 0) 927 return PCI_POWER_ERROR; 928 929 switch (acpi_state) { 930 case ACPI_STATE_D0: 931 return PCI_D0; 932 case ACPI_STATE_D1: 933 return PCI_D1; 934 case ACPI_STATE_D2: 935 return PCI_D2; 936 case ACPI_STATE_D3_HOT: 937 return PCI_D3hot; 938 case ACPI_STATE_D3_COLD: 939 return PCI_D3cold; 940 } 941 return PCI_POWER_ERROR; 942 } 943 944 static struct acpi_device *acpi_pci_find_companion(struct device *dev); 945 946 void pci_set_acpi_fwnode(struct pci_dev *dev) 947 { 948 if (!dev_fwnode(&dev->dev) && !pci_dev_is_added(dev)) 949 ACPI_COMPANION_SET(&dev->dev, 950 acpi_pci_find_companion(&dev->dev)); 951 } 952 953 /** 954 * pci_dev_acpi_reset - do a function level reset using _RST method 955 * @dev: device to reset 956 * @probe: if true, return 0 if device supports _RST 957 */ 958 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 959 { 960 acpi_handle handle = ACPI_HANDLE(&dev->dev); 961 int ret; 962 963 if (!handle || !acpi_has_method(handle, "_RST")) 964 return -ENOTTY; 965 966 if (probe) 967 return 0; 968 969 ret = pci_dev_reset_iommu_prepare(dev); 970 if (ret) { 971 pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); 972 return ret; 973 } 974 975 if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { 976 pci_warn(dev, "ACPI _RST failed\n"); 977 ret = -ENOTTY; 978 } 979 980 pci_dev_reset_iommu_done(dev); 981 return ret; 982 } 983 984 bool acpi_pci_power_manageable(struct pci_dev *dev) 985 { 986 struct acpi_device *adev = ACPI_COMPANION(&dev->dev); 987 988 return adev && acpi_device_power_manageable(adev); 989 } 990 991 bool acpi_pci_bridge_d3(struct pci_dev *dev) 992 { 993 struct pci_dev *rpdev; 994 struct acpi_device *adev, *rpadev; 995 const union acpi_object *obj; 996 997 if (acpi_pci_disabled || !dev->is_pciehp) 998 return false; 999 1000 adev = ACPI_COMPANION(&dev->dev); 1001 if (adev) { 1002 /* 1003 * If the bridge has _S0W, whether or not it can go into D3 1004 * depends on what is returned by that object. In particular, 1005 * if the power state returned by _S0W is D2 or shallower, 1006 * entering D3 should not be allowed. 1007 */ 1008 if (acpi_dev_power_state_for_wake(adev) <= ACPI_STATE_D2) 1009 return false; 1010 1011 /* 1012 * Otherwise, assume that the bridge can enter D3 so long as it 1013 * is power-manageable via ACPI. 1014 */ 1015 if (acpi_device_power_manageable(adev)) 1016 return true; 1017 } 1018 1019 rpdev = pcie_find_root_port(dev); 1020 if (!rpdev) 1021 return false; 1022 1023 if (rpdev == dev) 1024 rpadev = adev; 1025 else 1026 rpadev = ACPI_COMPANION(&rpdev->dev); 1027 1028 if (!rpadev) 1029 return false; 1030 1031 /* 1032 * If the Root Port cannot signal wakeup signals at all, i.e., it 1033 * doesn't supply a wakeup GPE via _PRW, it cannot signal hotplug 1034 * events from low-power states including D3hot and D3cold. 1035 */ 1036 if (!rpadev->wakeup.flags.valid) 1037 return false; 1038 1039 /* 1040 * In the bridge-below-a-Root-Port case, evaluate _S0W for the Root Port 1041 * to verify whether or not it can signal wakeup from D3. 1042 */ 1043 if (rpadev != adev && 1044 acpi_dev_power_state_for_wake(rpadev) <= ACPI_STATE_D2) 1045 return false; 1046 1047 /* 1048 * The "HotPlugSupportInD3" property in a Root Port _DSD indicates 1049 * the Port can signal hotplug events while in D3. We assume any 1050 * bridges *below* that Root Port can also signal hotplug events 1051 * while in D3. 1052 */ 1053 if (!acpi_dev_get_property(rpadev, "HotPlugSupportInD3", 1054 ACPI_TYPE_INTEGER, &obj) && 1055 obj->integer.value == 1) 1056 return true; 1057 1058 return false; 1059 } 1060 1061 static void acpi_pci_config_space_access(struct pci_dev *dev, bool enable) 1062 { 1063 int val = enable ? ACPI_REG_CONNECT : ACPI_REG_DISCONNECT; 1064 int ret = acpi_evaluate_reg(ACPI_HANDLE(&dev->dev), 1065 ACPI_ADR_SPACE_PCI_CONFIG, val); 1066 if (ret) 1067 pci_dbg(dev, "ACPI _REG %s evaluation failed (%d)\n", 1068 enable ? "connect" : "disconnect", ret); 1069 } 1070 1071 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1072 { 1073 struct acpi_device *adev = ACPI_COMPANION(&dev->dev); 1074 static const u8 state_conv[] = { 1075 [PCI_D0] = ACPI_STATE_D0, 1076 [PCI_D1] = ACPI_STATE_D1, 1077 [PCI_D2] = ACPI_STATE_D2, 1078 [PCI_D3hot] = ACPI_STATE_D3_HOT, 1079 [PCI_D3cold] = ACPI_STATE_D3_COLD, 1080 }; 1081 int error; 1082 1083 /* If the ACPI device has _EJ0, ignore the device */ 1084 if (!adev || acpi_has_method(adev->handle, "_EJ0")) 1085 return -ENODEV; 1086 1087 switch (state) { 1088 case PCI_D0: 1089 case PCI_D1: 1090 case PCI_D2: 1091 case PCI_D3hot: 1092 case PCI_D3cold: 1093 break; 1094 default: 1095 return -EINVAL; 1096 } 1097 1098 if (state == PCI_D3cold) { 1099 if (dev_pm_qos_flags(&dev->dev, PM_QOS_FLAG_NO_POWER_OFF) == 1100 PM_QOS_FLAGS_ALL) 1101 return -EBUSY; 1102 1103 /* Notify AML lack of PCI config space availability */ 1104 acpi_pci_config_space_access(dev, false); 1105 } 1106 1107 error = acpi_device_set_power(adev, state_conv[state]); 1108 if (error) 1109 return error; 1110 1111 pci_dbg(dev, "power state changed by ACPI to %s\n", 1112 acpi_power_state_string(adev->power.state)); 1113 1114 /* 1115 * Notify AML of PCI config space availability. Config space is 1116 * accessible in all states except D3cold; the only transitions 1117 * that change availability are transitions to D3cold and from 1118 * D3cold to D0. 1119 */ 1120 if (state == PCI_D0) 1121 acpi_pci_config_space_access(dev, true); 1122 1123 return 0; 1124 } 1125 1126 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 1127 { 1128 struct acpi_device *adev = ACPI_COMPANION(&dev->dev); 1129 static const pci_power_t state_conv[] = { 1130 [ACPI_STATE_D0] = PCI_D0, 1131 [ACPI_STATE_D1] = PCI_D1, 1132 [ACPI_STATE_D2] = PCI_D2, 1133 [ACPI_STATE_D3_HOT] = PCI_D3hot, 1134 [ACPI_STATE_D3_COLD] = PCI_D3cold, 1135 }; 1136 int state; 1137 1138 if (!adev || !acpi_device_power_manageable(adev)) 1139 return PCI_UNKNOWN; 1140 1141 state = adev->power.state; 1142 if (state == ACPI_STATE_UNKNOWN) 1143 return PCI_UNKNOWN; 1144 1145 return state_conv[state]; 1146 } 1147 1148 void acpi_pci_refresh_power_state(struct pci_dev *dev) 1149 { 1150 struct acpi_device *adev = ACPI_COMPANION(&dev->dev); 1151 1152 if (adev && acpi_device_power_manageable(adev)) 1153 acpi_device_update_power(adev, NULL); 1154 } 1155 1156 static int acpi_pci_propagate_wakeup(struct pci_bus *bus, bool enable) 1157 { 1158 while (bus->parent) { 1159 if (acpi_pm_device_can_wakeup(&bus->self->dev)) 1160 return acpi_pm_set_device_wakeup(&bus->self->dev, enable); 1161 1162 bus = bus->parent; 1163 } 1164 1165 /* We have reached the root bus. */ 1166 if (bus->bridge) { 1167 if (acpi_pm_device_can_wakeup(bus->bridge)) 1168 return acpi_pm_set_device_wakeup(bus->bridge, enable); 1169 } 1170 return 0; 1171 } 1172 1173 int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 1174 { 1175 if (acpi_pci_disabled) 1176 return 0; 1177 1178 if (acpi_pm_device_can_wakeup(&dev->dev)) 1179 return acpi_pm_set_device_wakeup(&dev->dev, enable); 1180 1181 return acpi_pci_propagate_wakeup(dev->bus, enable); 1182 } 1183 1184 bool acpi_pci_need_resume(struct pci_dev *dev) 1185 { 1186 struct acpi_device *adev; 1187 1188 if (acpi_pci_disabled) 1189 return false; 1190 1191 /* 1192 * In some cases (eg. Samsung 305V4A) leaving a bridge in suspend over 1193 * system-wide suspend/resume confuses the platform firmware, so avoid 1194 * doing that. According to Section 16.1.6 of ACPI 6.2, endpoint 1195 * devices are expected to be in D3 before invoking the S3 entry path 1196 * from the firmware, so they should not be affected by this issue. 1197 */ 1198 if (pci_is_bridge(dev) && acpi_target_system_state() != ACPI_STATE_S0) 1199 return true; 1200 1201 adev = ACPI_COMPANION(&dev->dev); 1202 if (!adev || !acpi_device_power_manageable(adev)) 1203 return false; 1204 1205 if (adev->wakeup.flags.valid && 1206 device_may_wakeup(&dev->dev) != !!adev->wakeup.prepare_count) 1207 return true; 1208 1209 if (acpi_target_system_state() == ACPI_STATE_S0) 1210 return false; 1211 1212 return !!adev->power.flags.dsw_present; 1213 } 1214 1215 void acpi_pci_add_bus(struct pci_bus *bus) 1216 { 1217 union acpi_object *obj; 1218 struct pci_host_bridge *bridge; 1219 1220 if (acpi_pci_disabled || !bus->bridge || !ACPI_HANDLE(bus->bridge)) 1221 return; 1222 1223 acpi_pci_slot_enumerate(bus); 1224 acpiphp_enumerate_slots(bus); 1225 1226 /* 1227 * For a host bridge, check its _DSM for function 8 and if 1228 * that is available, mark it in pci_host_bridge. 1229 */ 1230 if (!pci_is_root_bus(bus)) 1231 return; 1232 1233 obj = acpi_evaluate_dsm_typed(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 3, 1234 DSM_PCI_POWER_ON_RESET_DELAY, NULL, ACPI_TYPE_INTEGER); 1235 if (!obj) 1236 return; 1237 1238 if (obj->integer.value == 1) { 1239 bridge = pci_find_host_bridge(bus); 1240 bridge->ignore_reset_delay = 1; 1241 } 1242 ACPI_FREE(obj); 1243 } 1244 1245 void acpi_pci_remove_bus(struct pci_bus *bus) 1246 { 1247 if (acpi_pci_disabled || !bus->bridge) 1248 return; 1249 1250 acpiphp_remove_slots(bus); 1251 acpi_pci_slot_remove(bus); 1252 } 1253 1254 /* ACPI bus type */ 1255 1256 1257 static DECLARE_RWSEM(pci_acpi_companion_lookup_sem); 1258 static struct acpi_device *(*pci_acpi_find_companion_hook)(struct pci_dev *); 1259 1260 /** 1261 * pci_acpi_set_companion_lookup_hook - Set ACPI companion lookup callback. 1262 * @func: ACPI companion lookup callback pointer or NULL. 1263 * 1264 * Set a special ACPI companion lookup callback for PCI devices whose companion 1265 * objects in the ACPI namespace have _ADR with non-standard bus-device-function 1266 * encodings. 1267 * 1268 * Return 0 on success or a negative error code on failure (in which case no 1269 * changes are made). 1270 * 1271 * The caller is responsible for the appropriate ordering of the invocations of 1272 * this function with respect to the enumeration of the PCI devices needing the 1273 * callback installed by it. 1274 */ 1275 int pci_acpi_set_companion_lookup_hook(struct acpi_device *(*func)(struct pci_dev *)) 1276 { 1277 int ret; 1278 1279 if (!func) 1280 return -EINVAL; 1281 1282 down_write(&pci_acpi_companion_lookup_sem); 1283 1284 if (pci_acpi_find_companion_hook) { 1285 ret = -EBUSY; 1286 } else { 1287 pci_acpi_find_companion_hook = func; 1288 ret = 0; 1289 } 1290 1291 up_write(&pci_acpi_companion_lookup_sem); 1292 1293 return ret; 1294 } 1295 EXPORT_SYMBOL_GPL(pci_acpi_set_companion_lookup_hook); 1296 1297 /** 1298 * pci_acpi_clear_companion_lookup_hook - Clear ACPI companion lookup callback. 1299 * 1300 * Clear the special ACPI companion lookup callback previously set by 1301 * pci_acpi_set_companion_lookup_hook(). Block until the last running instance 1302 * of the callback returns before clearing it. 1303 * 1304 * The caller is responsible for the appropriate ordering of the invocations of 1305 * this function with respect to the enumeration of the PCI devices needing the 1306 * callback cleared by it. 1307 */ 1308 void pci_acpi_clear_companion_lookup_hook(void) 1309 { 1310 down_write(&pci_acpi_companion_lookup_sem); 1311 1312 pci_acpi_find_companion_hook = NULL; 1313 1314 up_write(&pci_acpi_companion_lookup_sem); 1315 } 1316 EXPORT_SYMBOL_GPL(pci_acpi_clear_companion_lookup_hook); 1317 1318 static struct acpi_device *acpi_pci_find_companion(struct device *dev) 1319 { 1320 struct pci_dev *pci_dev = to_pci_dev(dev); 1321 struct acpi_device *adev; 1322 bool check_children; 1323 u64 addr; 1324 1325 if (!dev->parent) 1326 return NULL; 1327 1328 down_read(&pci_acpi_companion_lookup_sem); 1329 1330 adev = pci_acpi_find_companion_hook ? 1331 pci_acpi_find_companion_hook(pci_dev) : NULL; 1332 1333 up_read(&pci_acpi_companion_lookup_sem); 1334 1335 if (adev) 1336 return adev; 1337 1338 check_children = pci_is_bridge(pci_dev); 1339 /* Please ref to ACPI spec for the syntax of _ADR */ 1340 addr = (PCI_SLOT(pci_dev->devfn) << 16) | PCI_FUNC(pci_dev->devfn); 1341 adev = acpi_find_child_device(ACPI_COMPANION(dev->parent), addr, 1342 check_children); 1343 1344 /* 1345 * There may be ACPI device objects in the ACPI namespace that are 1346 * children of the device object representing the host bridge, but don't 1347 * represent PCI devices. Both _HID and _ADR may be present for them, 1348 * even though that is against the specification (for example, see 1349 * Section 6.1 of ACPI 6.3), but in many cases the _ADR returns 0 which 1350 * appears to indicate that they should not be taken into consideration 1351 * as potential companions of PCI devices on the root bus. 1352 * 1353 * To catch this special case, disregard the returned device object if 1354 * it has a valid _HID, addr is 0 and the PCI device at hand is on the 1355 * root bus. 1356 */ 1357 if (adev && adev->pnp.type.platform_id && !addr && 1358 pci_is_root_bus(pci_dev->bus)) 1359 return NULL; 1360 1361 return adev; 1362 } 1363 1364 /** 1365 * pci_acpi_optimize_delay - optimize PCI D3 and D3cold delay from ACPI 1366 * @pdev: the PCI device whose delay is to be updated 1367 * @handle: ACPI handle of this device 1368 * 1369 * Update the d3hot_delay and d3cold_delay of a PCI device from the ACPI _DSM 1370 * control method of either the device itself or the PCI host bridge. 1371 * 1372 * Function 8, "Reset Delay," applies to the entire hierarchy below a PCI 1373 * host bridge. If it returns one, the OS may assume that all devices in 1374 * the hierarchy have already completed power-on reset delays. 1375 * 1376 * Function 9, "Device Readiness Durations," applies only to the object 1377 * where it is located. It returns delay durations required after various 1378 * events if the device requires less time than the spec requires. Delays 1379 * from this function take precedence over the Reset Delay function. 1380 * 1381 * These _DSM functions are defined by the draft ECN of January 28, 2014, 1382 * titled "ACPI additions for FW latency optimizations." 1383 */ 1384 static void pci_acpi_optimize_delay(struct pci_dev *pdev, 1385 acpi_handle handle) 1386 { 1387 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 1388 int value; 1389 union acpi_object *obj, *elements; 1390 1391 if (bridge->ignore_reset_delay) 1392 pdev->d3cold_delay = 0; 1393 1394 obj = acpi_evaluate_dsm_typed(handle, &pci_acpi_dsm_guid, 3, 1395 DSM_PCI_DEVICE_READINESS_DURATIONS, NULL, 1396 ACPI_TYPE_PACKAGE); 1397 if (!obj) 1398 return; 1399 1400 if (obj->package.count == 5) { 1401 elements = obj->package.elements; 1402 if (elements[0].type == ACPI_TYPE_INTEGER) { 1403 value = (int)elements[0].integer.value / 1000; 1404 if (value < PCI_PM_D3COLD_WAIT) 1405 pdev->d3cold_delay = value; 1406 } 1407 if (elements[3].type == ACPI_TYPE_INTEGER) { 1408 value = (int)elements[3].integer.value / 1000; 1409 if (value < PCI_PM_D3HOT_WAIT) 1410 pdev->d3hot_delay = value; 1411 } 1412 } 1413 ACPI_FREE(obj); 1414 } 1415 1416 static void pci_acpi_set_external_facing(struct pci_dev *dev) 1417 { 1418 u8 val; 1419 1420 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 1421 return; 1422 if (device_property_read_u8(&dev->dev, "ExternalFacingPort", &val)) 1423 return; 1424 1425 /* 1426 * These root ports expose PCIe (including DMA) outside of the 1427 * system. Everything downstream from them is external. 1428 */ 1429 if (val) 1430 dev->external_facing = 1; 1431 } 1432 1433 void pci_acpi_setup(struct device *dev, struct acpi_device *adev) 1434 { 1435 struct pci_dev *pci_dev = to_pci_dev(dev); 1436 1437 pci_acpi_optimize_delay(pci_dev, adev->handle); 1438 pci_acpi_set_external_facing(pci_dev); 1439 pci_acpi_add_edr_notifier(pci_dev); 1440 1441 pci_acpi_add_pm_notifier(adev, pci_dev); 1442 if (!adev->wakeup.flags.valid) 1443 return; 1444 1445 device_set_wakeup_capable(dev, true); 1446 /* 1447 * For bridges that can do D3 we enable wake automatically (as 1448 * we do for the power management itself in that case). The 1449 * reason is that the bridge may have additional methods such as 1450 * _DSW that need to be called. 1451 */ 1452 if (pci_dev->bridge_d3) 1453 device_wakeup_enable(dev); 1454 1455 acpi_pci_wakeup(pci_dev, false); 1456 acpi_device_power_add_dependent(adev, dev); 1457 1458 if (pci_is_bridge(pci_dev)) 1459 acpi_dev_power_up_children_with_adr(adev); 1460 } 1461 1462 void pci_acpi_cleanup(struct device *dev, struct acpi_device *adev) 1463 { 1464 struct pci_dev *pci_dev = to_pci_dev(dev); 1465 1466 pci_acpi_remove_edr_notifier(pci_dev); 1467 pci_acpi_remove_pm_notifier(adev); 1468 if (adev->wakeup.flags.valid) { 1469 acpi_device_power_remove_dependent(adev, dev); 1470 if (pci_dev->bridge_d3) 1471 device_wakeup_disable(dev); 1472 1473 device_set_wakeup_capable(dev, false); 1474 } 1475 } 1476 1477 static struct fwnode_handle *(*pci_msi_get_fwnode_cb)(struct device *dev); 1478 1479 /** 1480 * pci_msi_register_fwnode_provider - Register callback to retrieve fwnode 1481 * @fn: Callback matching a device to a fwnode that identifies a PCI 1482 * MSI domain. 1483 * 1484 * This should be called by irqchip driver, which is the parent of 1485 * the MSI domain to provide callback interface to query fwnode. 1486 */ 1487 void 1488 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)) 1489 { 1490 pci_msi_get_fwnode_cb = fn; 1491 } 1492 1493 /** 1494 * pci_host_bridge_acpi_msi_domain - Retrieve MSI domain of a PCI host bridge 1495 * @bus: The PCI host bridge bus. 1496 * 1497 * This function uses the callback function registered by 1498 * pci_msi_register_fwnode_provider() to retrieve the irq_domain with 1499 * type DOMAIN_BUS_PCI_MSI of the specified host bridge bus. 1500 * This returns NULL on error or when the domain is not found. 1501 */ 1502 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) 1503 { 1504 struct fwnode_handle *fwnode; 1505 1506 if (!pci_msi_get_fwnode_cb) 1507 return NULL; 1508 1509 fwnode = pci_msi_get_fwnode_cb(&bus->dev); 1510 if (!fwnode) 1511 return NULL; 1512 1513 return irq_find_matching_fwnode(fwnode, DOMAIN_BUS_PCI_MSI); 1514 } 1515 1516 static int __init acpi_pci_init(void) 1517 { 1518 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_MSI) { 1519 pr_info("ACPI FADT declares the system doesn't support MSI, so disable it\n"); 1520 pci_no_msi(); 1521 } 1522 1523 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) { 1524 pr_info("ACPI FADT declares the system doesn't support PCIe ASPM, so disable it\n"); 1525 pcie_no_aspm(); 1526 } 1527 1528 if (acpi_pci_disabled) 1529 return 0; 1530 1531 acpi_pci_slot_init(); 1532 acpiphp_init(); 1533 1534 return 0; 1535 } 1536 arch_initcall(acpi_pci_init); 1537 1538 #if defined(CONFIG_ARM64) || defined(CONFIG_RISCV) 1539 1540 /* 1541 * Try to assign the IRQ number when probing a new device 1542 */ 1543 int pcibios_alloc_irq(struct pci_dev *dev) 1544 { 1545 if (!acpi_disabled) 1546 acpi_pci_irq_enable(dev); 1547 1548 return 0; 1549 } 1550 1551 struct acpi_pci_generic_root_info { 1552 struct acpi_pci_root_info common; 1553 struct pci_config_window *cfg; /* config space mapping */ 1554 }; 1555 1556 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1557 { 1558 struct pci_config_window *cfg = bus->sysdata; 1559 struct acpi_device *adev = to_acpi_device(cfg->parent); 1560 struct acpi_pci_root *root = acpi_driver_data(adev); 1561 1562 return root->segment; 1563 } 1564 1565 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 1566 { 1567 struct pci_config_window *cfg; 1568 struct acpi_device *adev; 1569 struct device *bus_dev; 1570 1571 if (acpi_disabled) 1572 return 0; 1573 1574 cfg = bridge->bus->sysdata; 1575 1576 /* 1577 * On Hyper-V there is no corresponding ACPI device for a root bridge, 1578 * therefore ->parent is set as NULL by the driver. And set 'adev' as 1579 * NULL in this case because there is no proper ACPI device. 1580 */ 1581 if (!cfg->parent) 1582 adev = NULL; 1583 else 1584 adev = to_acpi_device(cfg->parent); 1585 1586 bus_dev = &bridge->bus->dev; 1587 1588 ACPI_COMPANION_SET(&bridge->dev, adev); 1589 set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev))); 1590 1591 return 0; 1592 } 1593 1594 static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci) 1595 { 1596 struct resource_entry *entry, *tmp; 1597 int status; 1598 1599 status = acpi_pci_probe_root_resources(ci); 1600 resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { 1601 if (!(entry->res->flags & IORESOURCE_WINDOW)) 1602 resource_list_destroy_entry(entry); 1603 } 1604 return status; 1605 } 1606 1607 /* 1608 * Lookup the bus range for the domain in MCFG, and set up config space 1609 * mapping. 1610 */ 1611 static struct pci_config_window * 1612 pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root) 1613 { 1614 struct device *dev = &root->device->dev; 1615 struct resource *bus_res = &root->secondary; 1616 u16 seg = root->segment; 1617 const struct pci_ecam_ops *ecam_ops; 1618 struct resource cfgres; 1619 struct acpi_device *adev; 1620 struct pci_config_window *cfg; 1621 int ret; 1622 1623 ret = pci_mcfg_lookup(root, &cfgres, &ecam_ops); 1624 if (ret) { 1625 dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res); 1626 return NULL; 1627 } 1628 1629 adev = acpi_resource_consumer(&cfgres); 1630 if (adev) 1631 dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres, 1632 dev_name(&adev->dev)); 1633 else 1634 dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n", 1635 &cfgres); 1636 1637 cfg = pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); 1638 if (IS_ERR(cfg)) { 1639 dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res, 1640 PTR_ERR(cfg)); 1641 return NULL; 1642 } 1643 1644 return cfg; 1645 } 1646 1647 /* release_info: free resources allocated by init_info */ 1648 static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci) 1649 { 1650 struct acpi_pci_generic_root_info *ri; 1651 1652 ri = container_of(ci, struct acpi_pci_generic_root_info, common); 1653 pci_ecam_free(ri->cfg); 1654 kfree(ci->ops); 1655 kfree(ri); 1656 } 1657 1658 /* Interface called from ACPI code to setup PCI host controller */ 1659 struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) 1660 { 1661 struct acpi_pci_generic_root_info *ri; 1662 struct pci_bus *bus, *child; 1663 struct acpi_pci_root_ops *root_ops; 1664 struct pci_host_bridge *host; 1665 1666 ri = kzalloc(sizeof(*ri), GFP_KERNEL); 1667 if (!ri) 1668 return NULL; 1669 1670 root_ops = kzalloc(sizeof(*root_ops), GFP_KERNEL); 1671 if (!root_ops) { 1672 kfree(ri); 1673 return NULL; 1674 } 1675 1676 ri->cfg = pci_acpi_setup_ecam_mapping(root); 1677 if (!ri->cfg) { 1678 kfree(ri); 1679 kfree(root_ops); 1680 return NULL; 1681 } 1682 1683 root_ops->release_info = pci_acpi_generic_release_info; 1684 root_ops->prepare_resources = pci_acpi_root_prepare_resources; 1685 root_ops->pci_ops = (struct pci_ops *)&ri->cfg->ops->pci_ops; 1686 bus = acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg); 1687 if (!bus) 1688 return NULL; 1689 1690 /* If we must preserve the resource configuration, claim now */ 1691 host = pci_find_host_bridge(bus); 1692 if (host->preserve_config) 1693 pci_bus_claim_resources(bus); 1694 1695 /* 1696 * Assign whatever was left unassigned. If we didn't claim above, 1697 * this will reassign everything. 1698 */ 1699 pci_assign_unassigned_root_bus_resources(bus); 1700 1701 list_for_each_entry(child, &bus->children, node) 1702 pcie_bus_configure_settings(child); 1703 1704 return bus; 1705 } 1706 1707 void pcibios_add_bus(struct pci_bus *bus) 1708 { 1709 acpi_pci_add_bus(bus); 1710 } 1711 1712 void pcibios_remove_bus(struct pci_bus *bus) 1713 { 1714 acpi_pci_remove_bus(bus); 1715 } 1716 1717 #endif 1718