1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Freescale QUICC Engine HDLC Device Driver
3 *
4 * Copyright 2016 Freescale Semiconductor Inc.
5 */
6
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/hdlc.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/netdevice.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_platform.h>
20 #include <linux/platform_device.h>
21 #include <linux/sched.h>
22 #include <linux/skbuff.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/stddef.h>
26 #include <soc/fsl/qe/qe_tdm.h>
27 #include <uapi/linux/if_arp.h>
28
29 #include "fsl_ucc_hdlc.h"
30
31 #define DRV_DESC "Freescale QE UCC HDLC Driver"
32 #define DRV_NAME "ucc_hdlc"
33
34 #define TDM_PPPOHT_SLIC_MAXIN
35 #define RX_BD_ERRORS (R_CD_S | R_OV_S | R_CR_S | R_AB_S | R_NO_S | R_LG_S)
36
37 static int uhdlc_close(struct net_device *dev);
38
39 static struct ucc_tdm_info utdm_primary_info = {
40 .uf_info = {
41 .tsa = 0,
42 .cdp = 0,
43 .cds = 1,
44 .ctsp = 1,
45 .ctss = 1,
46 .revd = 0,
47 .urfs = 256,
48 .utfs = 256,
49 .urfet = 128,
50 .urfset = 192,
51 .utfet = 128,
52 .utftt = 0x40,
53 .ufpt = 256,
54 .mode = UCC_FAST_PROTOCOL_MODE_HDLC,
55 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
56 .tenc = UCC_FAST_TX_ENCODING_NRZ,
57 .renc = UCC_FAST_RX_ENCODING_NRZ,
58 .tcrc = UCC_FAST_16_BIT_CRC,
59 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
60 },
61
62 .si_info = {
63 #ifdef TDM_PPPOHT_SLIC_MAXIN
64 .simr_rfsd = 1,
65 .simr_tfsd = 2,
66 #else
67 .simr_rfsd = 0,
68 .simr_tfsd = 0,
69 #endif
70 .simr_crt = 0,
71 .simr_sl = 0,
72 .simr_ce = 1,
73 .simr_fe = 1,
74 .simr_gm = 0,
75 },
76 };
77
78 static struct ucc_tdm_info utdm_info[UCC_MAX_NUM];
79
uhdlc_init(struct ucc_hdlc_private * priv)80 static int uhdlc_init(struct ucc_hdlc_private *priv)
81 {
82 struct ucc_tdm_info *ut_info;
83 struct ucc_fast_info *uf_info;
84 u32 cecr_subblock;
85 u16 bd_status;
86 int ret, i;
87 void *bd_buffer;
88 dma_addr_t bd_dma_addr;
89 s32 riptr;
90 s32 tiptr;
91 u32 gumr;
92
93 ut_info = priv->ut_info;
94 uf_info = &ut_info->uf_info;
95
96 if (priv->tsa) {
97 uf_info->tsa = 1;
98 uf_info->ctsp = 1;
99 uf_info->cds = 1;
100 uf_info->ctss = 1;
101 } else {
102 uf_info->cds = 0;
103 uf_info->ctsp = 0;
104 uf_info->ctss = 0;
105 }
106
107 /* This sets HPM register in CMXUCR register which configures a
108 * open drain connected HDLC bus
109 */
110 if (priv->hdlc_bus)
111 uf_info->brkpt_support = 1;
112
113 uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF |
114 UCC_HDLC_UCCE_TXB) << 16);
115
116 ret = ucc_fast_init(uf_info, &priv->uccf);
117 if (ret) {
118 dev_err(priv->dev, "Failed to init uccf.");
119 return ret;
120 }
121
122 priv->uf_regs = priv->uccf->uf_regs;
123 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
124
125 /* Loopback mode */
126 if (priv->loopback) {
127 dev_info(priv->dev, "Loopback Mode\n");
128 /* use the same clock when work in loopback */
129 qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1);
130
131 gumr = ioread32be(&priv->uf_regs->gumr);
132 gumr |= (UCC_FAST_GUMR_LOOPBACK | UCC_FAST_GUMR_CDS |
133 UCC_FAST_GUMR_TCI);
134 gumr &= ~(UCC_FAST_GUMR_CTSP | UCC_FAST_GUMR_RSYN);
135 iowrite32be(gumr, &priv->uf_regs->gumr);
136 }
137
138 /* Initialize SI */
139 if (priv->tsa)
140 ucc_tdm_init(priv->utdm, priv->ut_info);
141
142 /* Write to QE CECR, UCCx channel to Stop Transmission */
143 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
144 ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
145 QE_CR_PROTOCOL_UNSPECIFIED, 0);
146
147 /* Set UPSMR normal mode (need fixed)*/
148 iowrite32be(0, &priv->uf_regs->upsmr);
149
150 /* hdlc_bus mode */
151 if (priv->hdlc_bus) {
152 u32 upsmr;
153
154 dev_info(priv->dev, "HDLC bus Mode\n");
155 upsmr = ioread32be(&priv->uf_regs->upsmr);
156
157 /* bus mode and retransmit enable, with collision window
158 * set to 8 bytes
159 */
160 upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS |
161 UCC_HDLC_UPSMR_CW8;
162 iowrite32be(upsmr, &priv->uf_regs->upsmr);
163
164 /* explicitly disable CDS & CTSP */
165 gumr = ioread32be(&priv->uf_regs->gumr);
166 gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP);
167 /* set automatic sync to explicitly ignore CD signal */
168 gumr |= UCC_FAST_GUMR_SYNL_AUTO;
169 iowrite32be(gumr, &priv->uf_regs->gumr);
170 }
171
172 priv->rx_ring_size = RX_BD_RING_LEN;
173 priv->tx_ring_size = TX_BD_RING_LEN;
174 /* Alloc Rx BD */
175 priv->rx_bd_base = dma_alloc_coherent(priv->dev,
176 RX_BD_RING_LEN * sizeof(struct qe_bd),
177 &priv->dma_rx_bd, GFP_KERNEL);
178
179 if (!priv->rx_bd_base) {
180 dev_err(priv->dev, "Cannot allocate MURAM memory for RxBDs\n");
181 ret = -ENOMEM;
182 goto free_uccf;
183 }
184
185 /* Alloc Tx BD */
186 priv->tx_bd_base = dma_alloc_coherent(priv->dev,
187 TX_BD_RING_LEN * sizeof(struct qe_bd),
188 &priv->dma_tx_bd, GFP_KERNEL);
189
190 if (!priv->tx_bd_base) {
191 dev_err(priv->dev, "Cannot allocate MURAM memory for TxBDs\n");
192 ret = -ENOMEM;
193 goto free_rx_bd;
194 }
195
196 /* Alloc parameter ram for ucc hdlc */
197 priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param),
198 ALIGNMENT_OF_UCC_HDLC_PRAM);
199
200 if (priv->ucc_pram_offset < 0) {
201 dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n");
202 ret = -ENOMEM;
203 goto free_tx_bd;
204 }
205
206 priv->rx_skbuff = kzalloc_objs(*priv->rx_skbuff, priv->rx_ring_size);
207 if (!priv->rx_skbuff) {
208 ret = -ENOMEM;
209 goto free_ucc_pram;
210 }
211
212 priv->tx_skbuff = kzalloc_objs(*priv->tx_skbuff, priv->tx_ring_size);
213 if (!priv->tx_skbuff) {
214 ret = -ENOMEM;
215 goto free_rx_skbuff;
216 }
217
218 priv->skb_curtx = 0;
219 priv->skb_dirtytx = 0;
220 priv->curtx_bd = priv->tx_bd_base;
221 priv->dirty_tx = priv->tx_bd_base;
222 priv->currx_bd = priv->rx_bd_base;
223 priv->currx_bdnum = 0;
224
225 /* init parameter base */
226 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
227 ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
228 QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
229
230 priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
231 qe_muram_addr(priv->ucc_pram_offset);
232
233 /* Zero out parameter ram */
234 memset_io(priv->ucc_pram, 0, sizeof(struct ucc_hdlc_param));
235
236 /* Alloc riptr, tiptr */
237 riptr = qe_muram_alloc(32, 32);
238 if (riptr < 0) {
239 dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n");
240 ret = -ENOMEM;
241 goto free_tx_skbuff;
242 }
243
244 tiptr = qe_muram_alloc(32, 32);
245 if (tiptr < 0) {
246 dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n");
247 ret = -ENOMEM;
248 goto free_riptr;
249 }
250 if (riptr != (u16)riptr || tiptr != (u16)tiptr) {
251 dev_err(priv->dev, "MURAM allocation out of addressable range\n");
252 ret = -ENOMEM;
253 goto free_tiptr;
254 }
255
256 /* Set RIPTR, TIPTR */
257 iowrite16be(riptr, &priv->ucc_pram->riptr);
258 iowrite16be(tiptr, &priv->ucc_pram->tiptr);
259
260 /* Set MRBLR */
261 iowrite16be(MAX_RX_BUF_LENGTH, &priv->ucc_pram->mrblr);
262
263 /* Set RBASE, TBASE */
264 iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase);
265 iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase);
266
267 /* Set RSTATE, TSTATE */
268 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate);
269 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate);
270
271 /* Set C_MASK, C_PRES for 16bit CRC */
272 iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask);
273 iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres);
274
275 iowrite16be(MAX_FRAME_LENGTH, &priv->ucc_pram->mflr);
276 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfthr);
277 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfcnt);
278 iowrite16be(priv->hmask, &priv->ucc_pram->hmask);
279 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1);
280 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr2);
281 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3);
282 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4);
283
284 /* Get BD buffer */
285 bd_buffer = dma_alloc_coherent(priv->dev,
286 (RX_BD_RING_LEN + TX_BD_RING_LEN) * MAX_RX_BUF_LENGTH,
287 &bd_dma_addr, GFP_KERNEL);
288
289 if (!bd_buffer) {
290 dev_err(priv->dev, "Could not allocate buffer descriptors\n");
291 ret = -ENOMEM;
292 goto free_tiptr;
293 }
294
295 priv->rx_buffer = bd_buffer;
296 priv->tx_buffer = bd_buffer + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
297
298 priv->dma_rx_addr = bd_dma_addr;
299 priv->dma_tx_addr = bd_dma_addr + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
300
301 for (i = 0; i < RX_BD_RING_LEN; i++) {
302 if (i < (RX_BD_RING_LEN - 1))
303 bd_status = R_E_S | R_I_S;
304 else
305 bd_status = R_E_S | R_I_S | R_W_S;
306
307 priv->rx_bd_base[i].status = cpu_to_be16(bd_status);
308 priv->rx_bd_base[i].buf = cpu_to_be32(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH);
309 }
310
311 for (i = 0; i < TX_BD_RING_LEN; i++) {
312 if (i < (TX_BD_RING_LEN - 1))
313 bd_status = T_I_S | T_TC_S;
314 else
315 bd_status = T_I_S | T_TC_S | T_W_S;
316
317 priv->tx_bd_base[i].status = cpu_to_be16(bd_status);
318 priv->tx_bd_base[i].buf = cpu_to_be32(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH);
319 }
320 dma_wmb();
321
322 return 0;
323
324 free_tiptr:
325 qe_muram_free(tiptr);
326 free_riptr:
327 qe_muram_free(riptr);
328 free_tx_skbuff:
329 kfree(priv->tx_skbuff);
330 free_rx_skbuff:
331 kfree(priv->rx_skbuff);
332 free_ucc_pram:
333 qe_muram_free(priv->ucc_pram_offset);
334 free_tx_bd:
335 dma_free_coherent(priv->dev,
336 TX_BD_RING_LEN * sizeof(struct qe_bd),
337 priv->tx_bd_base, priv->dma_tx_bd);
338 free_rx_bd:
339 dma_free_coherent(priv->dev,
340 RX_BD_RING_LEN * sizeof(struct qe_bd),
341 priv->rx_bd_base, priv->dma_rx_bd);
342 free_uccf:
343 ucc_fast_free(priv->uccf);
344
345 return ret;
346 }
347
ucc_hdlc_tx(struct sk_buff * skb,struct net_device * dev)348 static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev)
349 {
350 hdlc_device *hdlc = dev_to_hdlc(dev);
351 struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)hdlc->priv;
352 struct qe_bd *bd;
353 u16 bd_status;
354 unsigned long flags;
355 __be16 *proto_head;
356
357 switch (dev->type) {
358 case ARPHRD_RAWHDLC:
359 if (skb_headroom(skb) < HDLC_HEAD_LEN) {
360 dev->stats.tx_dropped++;
361 dev_kfree_skb(skb);
362 netdev_err(dev, "No enough space for hdlc head\n");
363 return -ENOMEM;
364 }
365
366 skb_push(skb, HDLC_HEAD_LEN);
367
368 proto_head = (__be16 *)skb->data;
369 *proto_head = htons(DEFAULT_HDLC_HEAD);
370
371 dev->stats.tx_bytes += skb->len;
372 break;
373
374 case ARPHRD_PPP:
375 proto_head = (__be16 *)skb->data;
376 if (*proto_head != htons(DEFAULT_PPP_HEAD)) {
377 dev->stats.tx_dropped++;
378 dev_kfree_skb(skb);
379 netdev_err(dev, "Wrong ppp header\n");
380 return -ENOMEM;
381 }
382
383 dev->stats.tx_bytes += skb->len;
384 break;
385
386 case ARPHRD_ETHER:
387 dev->stats.tx_bytes += skb->len;
388 break;
389
390 default:
391 dev->stats.tx_dropped++;
392 dev_kfree_skb(skb);
393 return -ENOMEM;
394 }
395 netdev_sent_queue(dev, skb->len);
396 spin_lock_irqsave(&priv->lock, flags);
397
398 dma_rmb();
399 /* Start from the next BD that should be filled */
400 bd = priv->curtx_bd;
401 bd_status = be16_to_cpu(bd->status);
402 /* Save the skb pointer so we can free it later */
403 priv->tx_skbuff[priv->skb_curtx] = skb;
404
405 /* Update the current skb pointer (wrapping if this was the last) */
406 priv->skb_curtx =
407 (priv->skb_curtx + 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
408
409 /* copy skb data to tx buffer for sdma processing */
410 memcpy(priv->tx_buffer + (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
411 skb->data, skb->len);
412
413 /* set bd status and length */
414 bd_status = (bd_status & T_W_S) | T_R_S | T_I_S | T_L_S | T_TC_S;
415
416 bd->length = cpu_to_be16(skb->len);
417 bd->status = cpu_to_be16(bd_status);
418
419 /* Move to next BD in the ring */
420 if (!(bd_status & T_W_S))
421 bd += 1;
422 else
423 bd = priv->tx_bd_base;
424
425 if (bd == priv->dirty_tx) {
426 if (!netif_queue_stopped(dev))
427 netif_stop_queue(dev);
428 }
429
430 priv->curtx_bd = bd;
431
432 spin_unlock_irqrestore(&priv->lock, flags);
433
434 return NETDEV_TX_OK;
435 }
436
hdlc_tx_restart(struct ucc_hdlc_private * priv)437 static int hdlc_tx_restart(struct ucc_hdlc_private *priv)
438 {
439 u32 cecr_subblock;
440
441 cecr_subblock =
442 ucc_fast_get_qe_cr_subblock(priv->ut_info->uf_info.ucc_num);
443
444 qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
445 QE_CR_PROTOCOL_UNSPECIFIED, 0);
446 return 0;
447 }
448
hdlc_tx_done(struct ucc_hdlc_private * priv)449 static int hdlc_tx_done(struct ucc_hdlc_private *priv)
450 {
451 /* Start from the next BD that should be filled */
452 struct net_device *dev = priv->ndev;
453 unsigned int bytes_sent = 0;
454 int howmany = 0;
455 struct qe_bd *bd; /* BD pointer */
456 u16 bd_status;
457 int tx_restart = 0;
458
459 dma_rmb();
460 bd = priv->dirty_tx;
461 bd_status = be16_to_cpu(bd->status);
462
463 /* Normal processing. */
464 while ((bd_status & T_R_S) == 0) {
465 struct sk_buff *skb;
466
467 if (bd_status & T_UN_S) { /* Underrun */
468 dev->stats.tx_fifo_errors++;
469 tx_restart = 1;
470 }
471 if (bd_status & T_CT_S) { /* Carrier lost */
472 dev->stats.tx_carrier_errors++;
473 tx_restart = 1;
474 }
475
476 /* BD contains already transmitted buffer. */
477 /* Handle the transmitted buffer and release */
478 /* the BD to be used with the current frame */
479
480 skb = priv->tx_skbuff[priv->skb_dirtytx];
481 if (!skb)
482 break;
483 howmany++;
484 bytes_sent += skb->len;
485 dev->stats.tx_packets++;
486 memset(priv->tx_buffer +
487 (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
488 0, skb->len);
489 dev_consume_skb_irq(skb);
490
491 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
492 priv->skb_dirtytx =
493 (priv->skb_dirtytx +
494 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
495
496 /* We freed a buffer, so now we can restart transmission */
497 if (netif_queue_stopped(dev))
498 netif_wake_queue(dev);
499
500 /* Advance the confirmation BD pointer */
501 if (!(bd_status & T_W_S))
502 bd += 1;
503 else
504 bd = priv->tx_bd_base;
505 bd_status = be16_to_cpu(bd->status);
506 }
507 priv->dirty_tx = bd;
508
509 if (tx_restart)
510 hdlc_tx_restart(priv);
511
512 netdev_completed_queue(dev, howmany, bytes_sent);
513 return 0;
514 }
515
hdlc_rx_done(struct ucc_hdlc_private * priv,int rx_work_limit)516 static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit)
517 {
518 struct net_device *dev = priv->ndev;
519 struct sk_buff *skb = NULL;
520 hdlc_device *hdlc = dev_to_hdlc(dev);
521 struct qe_bd *bd;
522 u16 bd_status;
523 u16 length, howmany = 0;
524 u8 *bdbuffer;
525
526 dma_rmb();
527 bd = priv->currx_bd;
528 bd_status = be16_to_cpu(bd->status);
529
530 /* while there are received buffers and BD is full (~R_E) */
531 while (!((bd_status & (R_E_S)) || (--rx_work_limit < 0))) {
532 if (bd_status & (RX_BD_ERRORS)) {
533 dev->stats.rx_errors++;
534
535 if (bd_status & R_CD_S)
536 dev->stats.collisions++;
537 if (bd_status & R_OV_S)
538 dev->stats.rx_fifo_errors++;
539 if (bd_status & R_CR_S)
540 dev->stats.rx_crc_errors++;
541 if (bd_status & R_AB_S)
542 dev->stats.rx_over_errors++;
543 if (bd_status & R_NO_S)
544 dev->stats.rx_frame_errors++;
545 if (bd_status & R_LG_S)
546 dev->stats.rx_length_errors++;
547
548 goto recycle;
549 }
550 bdbuffer = priv->rx_buffer +
551 (priv->currx_bdnum * MAX_RX_BUF_LENGTH);
552 length = be16_to_cpu(bd->length);
553
554 switch (dev->type) {
555 case ARPHRD_RAWHDLC:
556 bdbuffer += HDLC_HEAD_LEN;
557 length -= (HDLC_HEAD_LEN + HDLC_CRC_SIZE);
558
559 skb = dev_alloc_skb(length);
560 if (!skb) {
561 dev->stats.rx_dropped++;
562 return -ENOMEM;
563 }
564
565 skb_put(skb, length);
566 skb->len = length;
567 skb->dev = dev;
568 memcpy(skb->data, bdbuffer, length);
569 break;
570
571 case ARPHRD_PPP:
572 case ARPHRD_ETHER:
573 length -= HDLC_CRC_SIZE;
574
575 skb = dev_alloc_skb(length);
576 if (!skb) {
577 dev->stats.rx_dropped++;
578 return -ENOMEM;
579 }
580
581 skb_put(skb, length);
582 skb->len = length;
583 skb->dev = dev;
584 memcpy(skb->data, bdbuffer, length);
585 break;
586 }
587
588 dev->stats.rx_packets++;
589 dev->stats.rx_bytes += skb->len;
590 howmany++;
591 if (hdlc->proto)
592 skb->protocol = hdlc_type_trans(skb, dev);
593 netif_receive_skb(skb);
594
595 recycle:
596 bd->status = cpu_to_be16((bd_status & R_W_S) | R_E_S | R_I_S);
597
598 /* update to point at the next bd */
599 if (bd_status & R_W_S) {
600 priv->currx_bdnum = 0;
601 bd = priv->rx_bd_base;
602 } else {
603 if (priv->currx_bdnum < (RX_BD_RING_LEN - 1))
604 priv->currx_bdnum += 1;
605 else
606 priv->currx_bdnum = RX_BD_RING_LEN - 1;
607
608 bd += 1;
609 }
610
611 bd_status = be16_to_cpu(bd->status);
612 }
613 dma_rmb();
614
615 priv->currx_bd = bd;
616 return howmany;
617 }
618
ucc_hdlc_poll(struct napi_struct * napi,int budget)619 static int ucc_hdlc_poll(struct napi_struct *napi, int budget)
620 {
621 struct ucc_hdlc_private *priv = container_of(napi,
622 struct ucc_hdlc_private,
623 napi);
624 int howmany;
625
626 /* Tx event processing */
627 spin_lock(&priv->lock);
628 hdlc_tx_done(priv);
629 spin_unlock(&priv->lock);
630
631 howmany = hdlc_rx_done(priv, budget);
632
633 if (howmany < budget) {
634 napi_complete_done(napi, howmany);
635 qe_setbits_be32(priv->uccf->p_uccm,
636 (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);
637 }
638
639 return howmany;
640 }
641
ucc_hdlc_irq_handler(int irq,void * dev_id)642 static irqreturn_t ucc_hdlc_irq_handler(int irq, void *dev_id)
643 {
644 struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)dev_id;
645 struct net_device *dev = priv->ndev;
646 struct ucc_fast_private *uccf;
647 u32 ucce;
648 u32 uccm;
649
650 uccf = priv->uccf;
651
652 ucce = ioread32be(uccf->p_ucce);
653 uccm = ioread32be(uccf->p_uccm);
654 ucce &= uccm;
655 iowrite32be(ucce, uccf->p_ucce);
656 if (!ucce)
657 return IRQ_NONE;
658
659 if ((ucce >> 16) & (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)) {
660 if (napi_schedule_prep(&priv->napi)) {
661 uccm &= ~((UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)
662 << 16);
663 iowrite32be(uccm, uccf->p_uccm);
664 __napi_schedule(&priv->napi);
665 }
666 }
667
668 /* Errors and other events */
669 if (ucce >> 16 & UCC_HDLC_UCCE_BSY)
670 dev->stats.rx_missed_errors++;
671 if (ucce >> 16 & UCC_HDLC_UCCE_TXE)
672 dev->stats.tx_errors++;
673
674 return IRQ_HANDLED;
675 }
676
uhdlc_ioctl(struct net_device * dev,struct if_settings * ifs)677 static int uhdlc_ioctl(struct net_device *dev, struct if_settings *ifs)
678 {
679 const size_t size = sizeof(te1_settings);
680 te1_settings line;
681 struct ucc_hdlc_private *priv = netdev_priv(dev);
682
683 switch (ifs->type) {
684 case IF_GET_IFACE:
685 ifs->type = IF_IFACE_E1;
686 if (ifs->size < size) {
687 ifs->size = size; /* data size wanted */
688 return -ENOBUFS;
689 }
690 memset(&line, 0, sizeof(line));
691 line.clock_type = priv->clocking;
692
693 if (copy_to_user(ifs->ifs_ifsu.sync, &line, size))
694 return -EFAULT;
695 return 0;
696
697 default:
698 return hdlc_ioctl(dev, ifs);
699 }
700 }
701
uhdlc_open(struct net_device * dev)702 static int uhdlc_open(struct net_device *dev)
703 {
704 u32 cecr_subblock;
705 hdlc_device *hdlc = dev_to_hdlc(dev);
706 struct ucc_hdlc_private *priv = hdlc->priv;
707 struct ucc_tdm *utdm = priv->utdm;
708 int rc = 0;
709
710 if (priv->hdlc_busy != 1) {
711 if (request_irq(priv->ut_info->uf_info.irq,
712 ucc_hdlc_irq_handler, 0, "hdlc", priv))
713 return -ENODEV;
714
715 cecr_subblock = ucc_fast_get_qe_cr_subblock(
716 priv->ut_info->uf_info.ucc_num);
717
718 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
719 QE_CR_PROTOCOL_UNSPECIFIED, 0);
720
721 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
722
723 /* Enable the TDM port */
724 if (priv->tsa)
725 qe_setbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port);
726
727 priv->hdlc_busy = 1;
728 netif_device_attach(priv->ndev);
729 napi_enable(&priv->napi);
730 netdev_reset_queue(dev);
731 netif_start_queue(dev);
732
733 rc = hdlc_open(dev);
734 if (rc)
735 uhdlc_close(dev);
736 }
737
738 return rc;
739 }
740
uhdlc_memclean(struct ucc_hdlc_private * priv)741 static void uhdlc_memclean(struct ucc_hdlc_private *priv)
742 {
743 int i;
744
745 qe_muram_free(ioread16be(&priv->ucc_pram->riptr));
746 qe_muram_free(ioread16be(&priv->ucc_pram->tiptr));
747
748 if (priv->rx_bd_base) {
749 dma_free_coherent(priv->dev,
750 RX_BD_RING_LEN * sizeof(struct qe_bd),
751 priv->rx_bd_base, priv->dma_rx_bd);
752
753 priv->rx_bd_base = NULL;
754 priv->dma_rx_bd = 0;
755 }
756
757 if (priv->tx_bd_base) {
758 dma_free_coherent(priv->dev,
759 TX_BD_RING_LEN * sizeof(struct qe_bd),
760 priv->tx_bd_base, priv->dma_tx_bd);
761
762 priv->tx_bd_base = NULL;
763 priv->dma_tx_bd = 0;
764 }
765
766 if (priv->ucc_pram) {
767 qe_muram_free(priv->ucc_pram_offset);
768 priv->ucc_pram = NULL;
769 priv->ucc_pram_offset = 0;
770 }
771
772 kfree(priv->rx_skbuff);
773 priv->rx_skbuff = NULL;
774
775 for (i = 0; i < TX_BD_RING_LEN; i++) {
776 dev_kfree_skb(priv->tx_skbuff[i]);
777 priv->tx_skbuff[i] = NULL;
778 }
779
780 kfree(priv->tx_skbuff);
781 priv->tx_skbuff = NULL;
782
783 if (priv->uccf) {
784 ucc_fast_free(priv->uccf);
785 priv->uccf = NULL;
786 }
787
788 if (priv->rx_buffer) {
789 dma_free_coherent(priv->dev,
790 (RX_BD_RING_LEN + TX_BD_RING_LEN) * MAX_RX_BUF_LENGTH,
791 priv->rx_buffer, priv->dma_rx_addr);
792 priv->rx_buffer = NULL;
793 priv->dma_rx_addr = 0;
794
795 priv->tx_buffer = NULL;
796 priv->dma_tx_addr = 0;
797
798 }
799 }
800
uhdlc_close(struct net_device * dev)801 static int uhdlc_close(struct net_device *dev)
802 {
803 struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv;
804 struct ucc_tdm *utdm = priv->utdm;
805 u32 cecr_subblock;
806
807 napi_disable(&priv->napi);
808 cecr_subblock = ucc_fast_get_qe_cr_subblock(
809 priv->ut_info->uf_info.ucc_num);
810
811 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
812 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
813 qe_issue_cmd(QE_CLOSE_RX_BD, cecr_subblock,
814 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
815
816 if (priv->tsa)
817 qe_clrbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port);
818
819 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
820
821 free_irq(priv->ut_info->uf_info.irq, priv);
822 netif_stop_queue(dev);
823 netdev_reset_queue(dev);
824 priv->hdlc_busy = 0;
825
826 hdlc_close(dev);
827
828 return 0;
829 }
830
ucc_hdlc_attach(struct net_device * dev,unsigned short encoding,unsigned short parity)831 static int ucc_hdlc_attach(struct net_device *dev, unsigned short encoding,
832 unsigned short parity)
833 {
834 struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv;
835
836 if (encoding != ENCODING_NRZ &&
837 encoding != ENCODING_NRZI)
838 return -EINVAL;
839
840 if (parity != PARITY_NONE &&
841 parity != PARITY_CRC32_PR1_CCITT &&
842 parity != PARITY_CRC16_PR0_CCITT &&
843 parity != PARITY_CRC16_PR1_CCITT)
844 return -EINVAL;
845
846 priv->encoding = encoding;
847 priv->parity = parity;
848
849 return 0;
850 }
851
852 #ifdef CONFIG_PM
store_clk_config(struct ucc_hdlc_private * priv)853 static void store_clk_config(struct ucc_hdlc_private *priv)
854 {
855 struct qe_mux __iomem *qe_mux_reg = &qe_immr->qmx;
856
857 /* store si clk */
858 priv->cmxsi1cr_h = ioread32be(&qe_mux_reg->cmxsi1cr_h);
859 priv->cmxsi1cr_l = ioread32be(&qe_mux_reg->cmxsi1cr_l);
860
861 /* store si sync */
862 priv->cmxsi1syr = ioread32be(&qe_mux_reg->cmxsi1syr);
863
864 /* store ucc clk */
865 memcpy_fromio(priv->cmxucr, qe_mux_reg->cmxucr, 4 * sizeof(u32));
866 }
867
resume_clk_config(struct ucc_hdlc_private * priv)868 static void resume_clk_config(struct ucc_hdlc_private *priv)
869 {
870 struct qe_mux __iomem *qe_mux_reg = &qe_immr->qmx;
871
872 memcpy_toio(qe_mux_reg->cmxucr, priv->cmxucr, 4 * sizeof(u32));
873
874 iowrite32be(priv->cmxsi1cr_h, &qe_mux_reg->cmxsi1cr_h);
875 iowrite32be(priv->cmxsi1cr_l, &qe_mux_reg->cmxsi1cr_l);
876
877 iowrite32be(priv->cmxsi1syr, &qe_mux_reg->cmxsi1syr);
878 }
879
uhdlc_suspend(struct device * dev)880 static int uhdlc_suspend(struct device *dev)
881 {
882 struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
883 struct ucc_fast __iomem *uf_regs;
884
885 if (!priv)
886 return -EINVAL;
887
888 if (!netif_running(priv->ndev))
889 return 0;
890
891 netif_device_detach(priv->ndev);
892 napi_disable(&priv->napi);
893
894 uf_regs = priv->uf_regs;
895
896 /* backup gumr guemr*/
897 priv->gumr = ioread32be(&uf_regs->gumr);
898 priv->guemr = ioread8(&uf_regs->guemr);
899
900 priv->ucc_pram_bak = kmalloc_obj(*priv->ucc_pram_bak);
901 if (!priv->ucc_pram_bak)
902 return -ENOMEM;
903
904 /* backup HDLC parameter */
905 memcpy_fromio(priv->ucc_pram_bak, priv->ucc_pram,
906 sizeof(struct ucc_hdlc_param));
907
908 /* store the clk configuration */
909 store_clk_config(priv);
910
911 /* save power */
912 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
913
914 return 0;
915 }
916
uhdlc_resume(struct device * dev)917 static int uhdlc_resume(struct device *dev)
918 {
919 struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
920 struct ucc_tdm *utdm;
921 struct ucc_tdm_info *ut_info;
922 struct ucc_fast __iomem *uf_regs;
923 struct ucc_fast_private *uccf;
924 struct ucc_fast_info *uf_info;
925 int i;
926 u32 cecr_subblock;
927 u16 bd_status;
928
929 if (!priv)
930 return -EINVAL;
931
932 if (!netif_running(priv->ndev))
933 return 0;
934
935 utdm = priv->utdm;
936 ut_info = priv->ut_info;
937 uf_info = &ut_info->uf_info;
938 uf_regs = priv->uf_regs;
939 uccf = priv->uccf;
940
941 /* restore gumr guemr */
942 iowrite8(priv->guemr, &uf_regs->guemr);
943 iowrite32be(priv->gumr, &uf_regs->gumr);
944
945 /* Set Virtual Fifo registers */
946 iowrite16be(uf_info->urfs, &uf_regs->urfs);
947 iowrite16be(uf_info->urfet, &uf_regs->urfet);
948 iowrite16be(uf_info->urfset, &uf_regs->urfset);
949 iowrite16be(uf_info->utfs, &uf_regs->utfs);
950 iowrite16be(uf_info->utfet, &uf_regs->utfet);
951 iowrite16be(uf_info->utftt, &uf_regs->utftt);
952 /* utfb, urfb are offsets from MURAM base */
953 iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb);
954 iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb);
955
956 /* Rx Tx and sync clock routing */
957 resume_clk_config(priv);
958
959 iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
960 iowrite32be(0xffffffff, &uf_regs->ucce);
961
962 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
963
964 /* rebuild SIRAM */
965 if (priv->tsa)
966 ucc_tdm_init(priv->utdm, priv->ut_info);
967
968 /* Write to QE CECR, UCCx channel to Stop Transmission */
969 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
970 qe_issue_cmd(QE_STOP_TX, cecr_subblock,
971 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
972
973 /* Set UPSMR normal mode */
974 iowrite32be(0, &uf_regs->upsmr);
975
976 /* init parameter base */
977 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
978 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
979 QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
980
981 priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
982 qe_muram_addr(priv->ucc_pram_offset);
983
984 /* restore ucc parameter */
985 memcpy_toio(priv->ucc_pram, priv->ucc_pram_bak,
986 sizeof(struct ucc_hdlc_param));
987 kfree(priv->ucc_pram_bak);
988
989 /* rebuild BD entry */
990 for (i = 0; i < RX_BD_RING_LEN; i++) {
991 if (i < (RX_BD_RING_LEN - 1))
992 bd_status = R_E_S | R_I_S;
993 else
994 bd_status = R_E_S | R_I_S | R_W_S;
995
996 priv->rx_bd_base[i].status = cpu_to_be16(bd_status);
997 priv->rx_bd_base[i].buf = cpu_to_be32(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH);
998 }
999
1000 for (i = 0; i < TX_BD_RING_LEN; i++) {
1001 if (i < (TX_BD_RING_LEN - 1))
1002 bd_status = T_I_S | T_TC_S;
1003 else
1004 bd_status = T_I_S | T_TC_S | T_W_S;
1005
1006 priv->tx_bd_base[i].status = cpu_to_be16(bd_status);
1007 priv->tx_bd_base[i].buf = cpu_to_be32(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH);
1008 }
1009 dma_wmb();
1010
1011 /* if hdlc is busy enable TX and RX */
1012 if (priv->hdlc_busy == 1) {
1013 cecr_subblock = ucc_fast_get_qe_cr_subblock(
1014 priv->ut_info->uf_info.ucc_num);
1015
1016 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
1017 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
1018
1019 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
1020
1021 /* Enable the TDM port */
1022 if (priv->tsa)
1023 qe_setbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port);
1024 }
1025
1026 napi_enable(&priv->napi);
1027 netif_device_attach(priv->ndev);
1028
1029 return 0;
1030 }
1031
1032 static const struct dev_pm_ops uhdlc_pm_ops = {
1033 .suspend = uhdlc_suspend,
1034 .resume = uhdlc_resume,
1035 .freeze = uhdlc_suspend,
1036 .thaw = uhdlc_resume,
1037 };
1038
1039 #define HDLC_PM_OPS (&uhdlc_pm_ops)
1040
1041 #else
1042
1043 #define HDLC_PM_OPS NULL
1044
1045 #endif
uhdlc_tx_timeout(struct net_device * ndev,unsigned int txqueue)1046 static void uhdlc_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1047 {
1048 netdev_err(ndev, "%s\n", __func__);
1049 }
1050
1051 static const struct net_device_ops uhdlc_ops = {
1052 .ndo_open = uhdlc_open,
1053 .ndo_stop = uhdlc_close,
1054 .ndo_start_xmit = hdlc_start_xmit,
1055 .ndo_siocwandev = uhdlc_ioctl,
1056 .ndo_tx_timeout = uhdlc_tx_timeout,
1057 };
1058
hdlc_map_iomem(char * name,int init_flag,void __iomem ** ptr)1059 static int hdlc_map_iomem(char *name, int init_flag, void __iomem **ptr)
1060 {
1061 struct device_node *np;
1062 struct platform_device *pdev;
1063 struct resource *res;
1064 static int siram_init_flag;
1065 int ret = 0;
1066
1067 np = of_find_compatible_node(NULL, NULL, name);
1068 if (!np)
1069 return -EINVAL;
1070
1071 pdev = of_find_device_by_node(np);
1072 if (!pdev) {
1073 pr_err("%pOFn: failed to lookup pdev\n", np);
1074 of_node_put(np);
1075 return -EINVAL;
1076 }
1077
1078 of_node_put(np);
1079 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1080 if (!res) {
1081 ret = -EINVAL;
1082 goto error_put_device;
1083 }
1084 *ptr = ioremap(res->start, resource_size(res));
1085 if (!*ptr) {
1086 ret = -ENOMEM;
1087 goto error_put_device;
1088 }
1089
1090 /* We've remapped the addresses, and we don't need the device any
1091 * more, so we should release it.
1092 */
1093 put_device(&pdev->dev);
1094
1095 if (init_flag && siram_init_flag == 0) {
1096 memset_io(*ptr, 0, resource_size(res));
1097 siram_init_flag = 1;
1098 }
1099 return 0;
1100
1101 error_put_device:
1102 put_device(&pdev->dev);
1103
1104 return ret;
1105 }
1106
ucc_hdlc_probe(struct platform_device * pdev)1107 static int ucc_hdlc_probe(struct platform_device *pdev)
1108 {
1109 struct device_node *np = pdev->dev.of_node;
1110 struct ucc_hdlc_private *uhdlc_priv = NULL;
1111 struct ucc_tdm_info *ut_info;
1112 struct ucc_tdm *utdm = NULL;
1113 struct resource res;
1114 struct net_device *dev;
1115 hdlc_device *hdlc;
1116 int ucc_num;
1117 const char *sprop;
1118 int ret;
1119 u32 val;
1120
1121 ret = of_property_read_u32_index(np, "cell-index", 0, &val);
1122 if (ret) {
1123 dev_err(&pdev->dev, "Invalid ucc property\n");
1124 return -ENODEV;
1125 }
1126
1127 ucc_num = val - 1;
1128 if (ucc_num > (UCC_MAX_NUM - 1) || ucc_num < 0) {
1129 dev_err(&pdev->dev, ": Invalid UCC num\n");
1130 return -EINVAL;
1131 }
1132
1133 memcpy(&utdm_info[ucc_num], &utdm_primary_info,
1134 sizeof(utdm_primary_info));
1135
1136 ut_info = &utdm_info[ucc_num];
1137 ut_info->uf_info.ucc_num = ucc_num;
1138
1139 sprop = of_get_property(np, "rx-clock-name", NULL);
1140 if (sprop) {
1141 ut_info->uf_info.rx_clock = qe_clock_source(sprop);
1142 if ((ut_info->uf_info.rx_clock < QE_CLK_NONE) ||
1143 (ut_info->uf_info.rx_clock > QE_CLK24)) {
1144 dev_err(&pdev->dev, "Invalid rx-clock-name property\n");
1145 return -EINVAL;
1146 }
1147 } else {
1148 dev_err(&pdev->dev, "Invalid rx-clock-name property\n");
1149 return -EINVAL;
1150 }
1151
1152 sprop = of_get_property(np, "tx-clock-name", NULL);
1153 if (sprop) {
1154 ut_info->uf_info.tx_clock = qe_clock_source(sprop);
1155 if ((ut_info->uf_info.tx_clock < QE_CLK_NONE) ||
1156 (ut_info->uf_info.tx_clock > QE_CLK24)) {
1157 dev_err(&pdev->dev, "Invalid tx-clock-name property\n");
1158 return -EINVAL;
1159 }
1160 } else {
1161 dev_err(&pdev->dev, "Invalid tx-clock-name property\n");
1162 return -EINVAL;
1163 }
1164
1165 ret = of_address_to_resource(np, 0, &res);
1166 if (ret)
1167 return -EINVAL;
1168
1169 ut_info->uf_info.regs = res.start;
1170 ut_info->uf_info.irq = irq_of_parse_and_map(np, 0);
1171
1172 uhdlc_priv = kzalloc_obj(*uhdlc_priv);
1173 if (!uhdlc_priv)
1174 return -ENOMEM;
1175
1176 dev_set_drvdata(&pdev->dev, uhdlc_priv);
1177 uhdlc_priv->dev = &pdev->dev;
1178 uhdlc_priv->ut_info = ut_info;
1179
1180 uhdlc_priv->tsa = of_property_read_bool(np, "fsl,tdm-interface");
1181 uhdlc_priv->loopback = of_property_read_bool(np, "fsl,ucc-internal-loopback");
1182 uhdlc_priv->hdlc_bus = of_property_read_bool(np, "fsl,hdlc-bus");
1183
1184 if (uhdlc_priv->tsa == 1) {
1185 utdm = kzalloc_obj(*utdm);
1186 if (!utdm) {
1187 ret = -ENOMEM;
1188 dev_err(&pdev->dev, "No mem to alloc ucc tdm data\n");
1189 goto free_uhdlc_priv;
1190 }
1191 uhdlc_priv->utdm = utdm;
1192 ret = ucc_of_parse_tdm(np, utdm, ut_info);
1193 if (ret)
1194 goto free_utdm;
1195
1196 ret = hdlc_map_iomem("fsl,t1040-qe-si", 0,
1197 (void __iomem **)&utdm->si_regs);
1198 if (ret)
1199 goto free_utdm;
1200 ret = hdlc_map_iomem("fsl,t1040-qe-siram", 1,
1201 (void __iomem **)&utdm->siram);
1202 if (ret)
1203 goto unmap_si_regs;
1204 }
1205
1206 if (of_property_read_u16(np, "fsl,hmask", &uhdlc_priv->hmask))
1207 uhdlc_priv->hmask = DEFAULT_ADDR_MASK;
1208
1209 ret = uhdlc_init(uhdlc_priv);
1210 if (ret) {
1211 dev_err(&pdev->dev, "Failed to init uhdlc\n");
1212 goto undo_uhdlc_init;
1213 }
1214
1215 dev = alloc_hdlcdev(uhdlc_priv);
1216 if (!dev) {
1217 ret = -ENOMEM;
1218 pr_err("ucc_hdlc: unable to allocate memory\n");
1219 goto undo_uhdlc_init;
1220 }
1221
1222 uhdlc_priv->ndev = dev;
1223 hdlc = dev_to_hdlc(dev);
1224 dev->tx_queue_len = 16;
1225 dev->netdev_ops = &uhdlc_ops;
1226 dev->watchdog_timeo = 2 * HZ;
1227 hdlc->attach = ucc_hdlc_attach;
1228 hdlc->xmit = ucc_hdlc_tx;
1229 netif_napi_add_weight(dev, &uhdlc_priv->napi, ucc_hdlc_poll, 32);
1230 if (register_hdlc_device(dev)) {
1231 ret = -ENOBUFS;
1232 pr_err("ucc_hdlc: unable to register hdlc device\n");
1233 goto free_dev;
1234 }
1235
1236 return 0;
1237
1238 free_dev:
1239 free_netdev(dev);
1240 undo_uhdlc_init:
1241 if (utdm)
1242 iounmap(utdm->siram);
1243 unmap_si_regs:
1244 if (utdm)
1245 iounmap(utdm->si_regs);
1246 free_utdm:
1247 if (uhdlc_priv->tsa)
1248 kfree(utdm);
1249 free_uhdlc_priv:
1250 kfree(uhdlc_priv);
1251 return ret;
1252 }
1253
ucc_hdlc_remove(struct platform_device * pdev)1254 static void ucc_hdlc_remove(struct platform_device *pdev)
1255 {
1256 struct ucc_hdlc_private *priv = dev_get_drvdata(&pdev->dev);
1257
1258 uhdlc_memclean(priv);
1259
1260 if (priv->utdm && priv->utdm->si_regs) {
1261 iounmap(priv->utdm->si_regs);
1262 priv->utdm->si_regs = NULL;
1263 }
1264
1265 if (priv->utdm && priv->utdm->siram) {
1266 iounmap(priv->utdm->siram);
1267 priv->utdm->siram = NULL;
1268 }
1269 kfree(priv);
1270
1271 dev_info(&pdev->dev, "UCC based hdlc module removed\n");
1272 }
1273
1274 static const struct of_device_id fsl_ucc_hdlc_of_match[] = {
1275 {
1276 .compatible = "fsl,ucc-hdlc",
1277 },
1278 {},
1279 };
1280
1281 MODULE_DEVICE_TABLE(of, fsl_ucc_hdlc_of_match);
1282
1283 static struct platform_driver ucc_hdlc_driver = {
1284 .probe = ucc_hdlc_probe,
1285 .remove = ucc_hdlc_remove,
1286 .driver = {
1287 .name = DRV_NAME,
1288 .pm = HDLC_PM_OPS,
1289 .of_match_table = fsl_ucc_hdlc_of_match,
1290 },
1291 };
1292
1293 module_platform_driver(ucc_hdlc_driver);
1294 MODULE_LICENSE("GPL");
1295 MODULE_DESCRIPTION(DRV_DESC);
1296