1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Universal Flash Storage Host controller driver Core 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #include <linux/async.h> 13 #include <linux/devfreq.h> 14 #include <linux/nls.h> 15 #include <linux/of.h> 16 #include <linux/bitfield.h> 17 #include <linux/blk-pm.h> 18 #include <linux/blkdev.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/pm_opp.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/sched/clock.h> 26 #include <linux/iopoll.h> 27 #include <scsi/scsi_cmnd.h> 28 #include <scsi/scsi_dbg.h> 29 #include <scsi/scsi_driver.h> 30 #include <scsi/scsi_eh.h> 31 #include "ufshcd-priv.h" 32 #include <ufs/ufs_quirks.h> 33 #include <ufs/unipro.h> 34 #include "ufs-sysfs.h" 35 #include "ufs-debugfs.h" 36 #include "ufs-fault-injection.h" 37 #include "ufs_bsg.h" 38 #include "ufshcd-crypto.h" 39 #include <linux/unaligned.h> 40 41 #define CREATE_TRACE_POINTS 42 #include "ufs_trace.h" 43 44 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 45 UTP_TASK_REQ_COMPL |\ 46 UFSHCD_ERROR_MASK) 47 48 #define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\ 49 UFSHCD_ERROR_MASK |\ 50 MCQ_CQ_EVENT_STATUS) 51 52 53 /* UIC command timeout, unit: ms */ 54 enum { 55 UIC_CMD_TIMEOUT_DEFAULT = 500, 56 UIC_CMD_TIMEOUT_MAX = 2000, 57 }; 58 /* NOP OUT retries waiting for NOP IN response */ 59 #define NOP_OUT_RETRIES 10 60 /* Timeout after 50 msecs if NOP OUT hangs without response */ 61 #define NOP_OUT_TIMEOUT 50 /* msecs */ 62 63 /* Query request retries */ 64 #define QUERY_REQ_RETRIES 3 65 /* Query request timeout */ 66 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 67 68 /* Advanced RPMB request timeout */ 69 #define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */ 70 71 /* Task management command timeout */ 72 #define TM_CMD_TIMEOUT 100 /* msecs */ 73 74 /* maximum number of retries for a general UIC command */ 75 #define UFS_UIC_COMMAND_RETRIES 3 76 77 /* maximum number of link-startup retries */ 78 #define DME_LINKSTARTUP_RETRIES 3 79 80 /* maximum number of reset retries before giving up */ 81 #define MAX_HOST_RESET_RETRIES 5 82 83 /* Maximum number of error handler retries before giving up */ 84 #define MAX_ERR_HANDLER_RETRIES 5 85 86 /* Expose the flag value from utp_upiu_query.value */ 87 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 88 89 /* Interrupt aggregation default timeout, unit: 40us */ 90 #define INT_AGGR_DEF_TO 0x02 91 92 /* default delay of autosuspend: 2000 ms */ 93 #define RPM_AUTOSUSPEND_DELAY_MS 2000 94 95 /* Default delay of RPM device flush delayed work */ 96 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000 97 98 /* Default value of wait time before gating device ref clock */ 99 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */ 100 101 /* Polling time to wait for fDeviceInit */ 102 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */ 103 104 /* Default RTC update every 10 seconds */ 105 #define UFS_RTC_UPDATE_INTERVAL_MS (10 * MSEC_PER_SEC) 106 107 /* bMaxNumOfRTT is equal to two after device manufacturing */ 108 #define DEFAULT_MAX_NUM_RTT 2 109 110 /* UFSHC 4.0 compliant HC support this mode. */ 111 static bool use_mcq_mode = true; 112 is_mcq_supported(struct ufs_hba * hba)113 static bool is_mcq_supported(struct ufs_hba *hba) 114 { 115 return hba->mcq_sup && use_mcq_mode; 116 } 117 118 module_param(use_mcq_mode, bool, 0644); 119 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default"); 120 121 static unsigned int uic_cmd_timeout = UIC_CMD_TIMEOUT_DEFAULT; 122 uic_cmd_timeout_set(const char * val,const struct kernel_param * kp)123 static int uic_cmd_timeout_set(const char *val, const struct kernel_param *kp) 124 { 125 return param_set_uint_minmax(val, kp, UIC_CMD_TIMEOUT_DEFAULT, 126 UIC_CMD_TIMEOUT_MAX); 127 } 128 129 static const struct kernel_param_ops uic_cmd_timeout_ops = { 130 .set = uic_cmd_timeout_set, 131 .get = param_get_uint, 132 }; 133 134 module_param_cb(uic_cmd_timeout, &uic_cmd_timeout_ops, &uic_cmd_timeout, 0644); 135 MODULE_PARM_DESC(uic_cmd_timeout, 136 "UFS UIC command timeout in milliseconds. Defaults to 500ms. Supported values range from 500ms to 2 seconds inclusively"); 137 138 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ 139 ({ \ 140 int _ret; \ 141 if (_on) \ 142 _ret = ufshcd_enable_vreg(_dev, _vreg); \ 143 else \ 144 _ret = ufshcd_disable_vreg(_dev, _vreg); \ 145 _ret; \ 146 }) 147 148 #define ufshcd_hex_dump(prefix_str, buf, len) do { \ 149 size_t __len = (len); \ 150 print_hex_dump(KERN_ERR, prefix_str, \ 151 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\ 152 16, 4, buf, __len, false); \ 153 } while (0) 154 ufshcd_dump_regs(struct ufs_hba * hba,size_t offset,size_t len,const char * prefix)155 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 156 const char *prefix) 157 { 158 u32 *regs; 159 size_t pos; 160 161 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */ 162 return -EINVAL; 163 164 regs = kzalloc(len, GFP_ATOMIC); 165 if (!regs) 166 return -ENOMEM; 167 168 for (pos = 0; pos < len; pos += 4) { 169 if (offset == 0 && 170 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER && 171 pos <= REG_UIC_ERROR_CODE_DME) 172 continue; 173 regs[pos / 4] = ufshcd_readl(hba, offset + pos); 174 } 175 176 ufshcd_hex_dump(prefix, regs, len); 177 kfree(regs); 178 179 return 0; 180 } 181 EXPORT_SYMBOL_GPL(ufshcd_dump_regs); 182 183 enum { 184 UFSHCD_MAX_CHANNEL = 0, 185 UFSHCD_MAX_ID = 1, 186 }; 187 188 static const char *const ufshcd_state_name[] = { 189 [UFSHCD_STATE_RESET] = "reset", 190 [UFSHCD_STATE_OPERATIONAL] = "operational", 191 [UFSHCD_STATE_ERROR] = "error", 192 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal", 193 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal", 194 }; 195 196 /* UFSHCD error handling flags */ 197 enum { 198 UFSHCD_EH_IN_PROGRESS = (1 << 0), 199 }; 200 201 /* UFSHCD UIC layer error flags */ 202 enum { 203 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */ 204 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */ 205 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */ 206 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */ 207 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */ 208 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */ 209 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */ 210 }; 211 212 #define ufshcd_set_eh_in_progress(h) \ 213 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS) 214 #define ufshcd_eh_in_progress(h) \ 215 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS) 216 #define ufshcd_clear_eh_in_progress(h) \ 217 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS) 218 219 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = { 220 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 221 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 222 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 223 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 224 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 225 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE}, 226 /* 227 * For DeepSleep, the link is first put in hibern8 and then off. 228 * Leaving the link in hibern8 is not supported. 229 */ 230 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE}, 231 }; 232 233 static inline enum ufs_dev_pwr_mode ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)234 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl) 235 { 236 return ufs_pm_lvl_states[lvl].dev_state; 237 } 238 239 static inline enum uic_link_state ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)240 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl) 241 { 242 return ufs_pm_lvl_states[lvl].link_state; 243 } 244 245 static inline enum ufs_pm_level ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,enum uic_link_state link_state)246 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state, 247 enum uic_link_state link_state) 248 { 249 enum ufs_pm_level lvl; 250 251 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) { 252 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) && 253 (ufs_pm_lvl_states[lvl].link_state == link_state)) 254 return lvl; 255 } 256 257 /* if no match found, return the level 0 */ 258 return UFS_PM_LVL_0; 259 } 260 ufshcd_has_pending_tasks(struct ufs_hba * hba)261 static bool ufshcd_has_pending_tasks(struct ufs_hba *hba) 262 { 263 return hba->outstanding_tasks || hba->active_uic_cmd || 264 hba->uic_async_done; 265 } 266 ufshcd_is_ufs_dev_busy(struct ufs_hba * hba)267 static bool ufshcd_is_ufs_dev_busy(struct ufs_hba *hba) 268 { 269 return scsi_host_busy(hba->host) || ufshcd_has_pending_tasks(hba); 270 } 271 272 static const struct ufs_dev_quirk ufs_fixups[] = { 273 /* UFS cards deviations table */ 274 { .wmanufacturerid = UFS_VENDOR_MICRON, 275 .model = UFS_ANY_MODEL, 276 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 277 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 278 .model = UFS_ANY_MODEL, 279 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM | 280 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE | 281 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS }, 282 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 283 .model = UFS_ANY_MODEL, 284 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME }, 285 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 286 .model = "hB8aL1" /*H28U62301AMR*/, 287 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME }, 288 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 289 .model = UFS_ANY_MODEL, 290 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 291 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 292 .model = "THGLF2G9C8KBADG", 293 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 294 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 295 .model = "THGLF2G9D8KBADG", 296 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 297 {} 298 }; 299 300 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba); 301 static void ufshcd_async_scan(void *data, async_cookie_t cookie); 302 static int ufshcd_reset_and_restore(struct ufs_hba *hba); 303 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd); 304 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag); 305 static void ufshcd_hba_exit(struct ufs_hba *hba); 306 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params); 307 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params); 308 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on); 309 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); 310 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); 311 static void ufshcd_resume_clkscaling(struct ufs_hba *hba); 312 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); 313 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 314 bool scale_up); 315 static irqreturn_t ufshcd_intr(int irq, void *__hba); 316 static int ufshcd_change_power_mode(struct ufs_hba *hba, 317 struct ufs_pa_layer_attr *pwr_mode); 318 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); 319 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); 320 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 321 struct ufs_vreg *vreg); 322 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 323 bool enable); 324 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba); 325 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba); 326 ufshcd_enable_irq(struct ufs_hba * hba)327 void ufshcd_enable_irq(struct ufs_hba *hba) 328 { 329 if (!hba->is_irq_enabled) { 330 enable_irq(hba->irq); 331 hba->is_irq_enabled = true; 332 } 333 } 334 EXPORT_SYMBOL_GPL(ufshcd_enable_irq); 335 ufshcd_disable_irq(struct ufs_hba * hba)336 void ufshcd_disable_irq(struct ufs_hba *hba) 337 { 338 if (hba->is_irq_enabled) { 339 disable_irq(hba->irq); 340 hba->is_irq_enabled = false; 341 } 342 } 343 EXPORT_SYMBOL_GPL(ufshcd_disable_irq); 344 ufshcd_configure_wb(struct ufs_hba * hba)345 static void ufshcd_configure_wb(struct ufs_hba *hba) 346 { 347 if (!ufshcd_is_wb_allowed(hba)) 348 return; 349 350 ufshcd_wb_toggle(hba, true); 351 352 ufshcd_wb_toggle_buf_flush_during_h8(hba, true); 353 354 if (ufshcd_is_wb_buf_flush_allowed(hba)) 355 ufshcd_wb_toggle_buf_flush(hba, true); 356 } 357 ufshcd_add_cmd_upiu_trace(struct ufs_hba * hba,unsigned int tag,enum ufs_trace_str_t str_t)358 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag, 359 enum ufs_trace_str_t str_t) 360 { 361 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr; 362 struct utp_upiu_header *header; 363 364 if (!trace_ufshcd_upiu_enabled()) 365 return; 366 367 if (str_t == UFS_CMD_SEND) 368 header = &rq->header; 369 else 370 header = &hba->lrb[tag].ucd_rsp_ptr->header; 371 372 trace_ufshcd_upiu(hba, str_t, header, &rq->sc.cdb, 373 UFS_TSF_CDB); 374 } 375 ufshcd_add_query_upiu_trace(struct ufs_hba * hba,enum ufs_trace_str_t str_t,struct utp_upiu_req * rq_rsp)376 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, 377 enum ufs_trace_str_t str_t, 378 struct utp_upiu_req *rq_rsp) 379 { 380 if (!trace_ufshcd_upiu_enabled()) 381 return; 382 383 trace_ufshcd_upiu(hba, str_t, &rq_rsp->header, 384 &rq_rsp->qr, UFS_TSF_OSF); 385 } 386 ufshcd_add_tm_upiu_trace(struct ufs_hba * hba,unsigned int tag,enum ufs_trace_str_t str_t)387 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag, 388 enum ufs_trace_str_t str_t) 389 { 390 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag]; 391 392 if (!trace_ufshcd_upiu_enabled()) 393 return; 394 395 if (str_t == UFS_TM_SEND) 396 trace_ufshcd_upiu(hba, str_t, 397 &descp->upiu_req.req_header, 398 &descp->upiu_req.input_param1, 399 UFS_TSF_TM_INPUT); 400 else 401 trace_ufshcd_upiu(hba, str_t, 402 &descp->upiu_rsp.rsp_header, 403 &descp->upiu_rsp.output_param1, 404 UFS_TSF_TM_OUTPUT); 405 } 406 ufshcd_add_uic_command_trace(struct ufs_hba * hba,const struct uic_command * ucmd,enum ufs_trace_str_t str_t)407 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba, 408 const struct uic_command *ucmd, 409 enum ufs_trace_str_t str_t) 410 { 411 u32 cmd; 412 413 if (!trace_ufshcd_uic_command_enabled()) 414 return; 415 416 if (str_t == UFS_CMD_SEND) 417 cmd = ucmd->command; 418 else 419 cmd = ufshcd_readl(hba, REG_UIC_COMMAND); 420 421 trace_ufshcd_uic_command(hba, str_t, cmd, 422 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1), 423 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2), 424 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3)); 425 } 426 ufshcd_add_command_trace(struct ufs_hba * hba,unsigned int tag,enum ufs_trace_str_t str_t)427 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag, 428 enum ufs_trace_str_t str_t) 429 { 430 u64 lba = 0; 431 u8 opcode = 0, group_id = 0; 432 u32 doorbell = 0; 433 u32 intr; 434 int hwq_id = -1; 435 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 436 struct scsi_cmnd *cmd = lrbp->cmd; 437 struct request *rq = scsi_cmd_to_rq(cmd); 438 int transfer_len = -1; 439 440 if (!cmd) 441 return; 442 443 /* trace UPIU also */ 444 ufshcd_add_cmd_upiu_trace(hba, tag, str_t); 445 if (!trace_ufshcd_command_enabled()) 446 return; 447 448 opcode = cmd->cmnd[0]; 449 450 if (opcode == READ_10 || opcode == WRITE_10) { 451 /* 452 * Currently we only fully trace read(10) and write(10) commands 453 */ 454 transfer_len = 455 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len); 456 lba = scsi_get_lba(cmd); 457 if (opcode == WRITE_10) 458 group_id = lrbp->cmd->cmnd[6]; 459 } else if (opcode == UNMAP) { 460 /* 461 * The number of Bytes to be unmapped beginning with the lba. 462 */ 463 transfer_len = blk_rq_bytes(rq); 464 lba = scsi_get_lba(cmd); 465 } 466 467 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 468 469 if (hba->mcq_enabled) { 470 struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq); 471 472 hwq_id = hwq->id; 473 } else { 474 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 475 } 476 trace_ufshcd_command(cmd->device, hba, str_t, tag, doorbell, hwq_id, 477 transfer_len, intr, lba, opcode, group_id); 478 } 479 ufshcd_print_clk_freqs(struct ufs_hba * hba)480 static void ufshcd_print_clk_freqs(struct ufs_hba *hba) 481 { 482 struct ufs_clk_info *clki; 483 struct list_head *head = &hba->clk_list_head; 484 485 if (list_empty(head)) 486 return; 487 488 list_for_each_entry(clki, head, list) { 489 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq && 490 clki->max_freq) 491 dev_err(hba->dev, "clk: %s, rate: %u\n", 492 clki->name, clki->curr_freq); 493 } 494 } 495 ufshcd_print_evt(struct ufs_hba * hba,u32 id,const char * err_name)496 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id, 497 const char *err_name) 498 { 499 int i; 500 bool found = false; 501 const struct ufs_event_hist *e; 502 503 if (id >= UFS_EVT_CNT) 504 return; 505 506 e = &hba->ufs_stats.event[id]; 507 508 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) { 509 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH; 510 511 if (e->tstamp[p] == 0) 512 continue; 513 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p, 514 e->val[p], div_u64(e->tstamp[p], 1000)); 515 found = true; 516 } 517 518 if (!found) 519 dev_err(hba->dev, "No record of %s\n", err_name); 520 else 521 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt); 522 } 523 ufshcd_print_evt_hist(struct ufs_hba * hba)524 static void ufshcd_print_evt_hist(struct ufs_hba *hba) 525 { 526 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 527 528 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err"); 529 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err"); 530 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err"); 531 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err"); 532 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err"); 533 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR, 534 "auto_hibern8_err"); 535 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err"); 536 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL, 537 "link_startup_fail"); 538 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail"); 539 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR, 540 "suspend_fail"); 541 ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail"); 542 ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR, 543 "wlun suspend_fail"); 544 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset"); 545 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset"); 546 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort"); 547 548 ufshcd_vops_dbg_register_dump(hba); 549 } 550 551 static ufshcd_print_tr(struct ufs_hba * hba,int tag,bool pr_prdt)552 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt) 553 { 554 const struct ufshcd_lrb *lrbp; 555 int prdt_length; 556 557 lrbp = &hba->lrb[tag]; 558 559 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n", 560 tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000)); 561 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n", 562 tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000)); 563 dev_err(hba->dev, 564 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n", 565 tag, (u64)lrbp->utrd_dma_addr); 566 567 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr, 568 sizeof(struct utp_transfer_req_desc)); 569 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag, 570 (u64)lrbp->ucd_req_dma_addr); 571 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr, 572 sizeof(struct utp_upiu_req)); 573 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag, 574 (u64)lrbp->ucd_rsp_dma_addr); 575 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr, 576 sizeof(struct utp_upiu_rsp)); 577 578 prdt_length = le16_to_cpu( 579 lrbp->utr_descriptor_ptr->prd_table_length); 580 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 581 prdt_length /= ufshcd_sg_entry_size(hba); 582 583 dev_err(hba->dev, 584 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n", 585 tag, prdt_length, 586 (u64)lrbp->ucd_prdt_dma_addr); 587 588 if (pr_prdt) 589 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr, 590 ufshcd_sg_entry_size(hba) * prdt_length); 591 } 592 ufshcd_print_tr_iter(struct request * req,void * priv)593 static bool ufshcd_print_tr_iter(struct request *req, void *priv) 594 { 595 struct scsi_device *sdev = req->q->queuedata; 596 struct Scsi_Host *shost = sdev->host; 597 struct ufs_hba *hba = shost_priv(shost); 598 599 ufshcd_print_tr(hba, req->tag, *(bool *)priv); 600 601 return true; 602 } 603 604 /** 605 * ufshcd_print_trs_all - print trs for all started requests. 606 * @hba: per-adapter instance. 607 * @pr_prdt: need to print prdt or not. 608 */ ufshcd_print_trs_all(struct ufs_hba * hba,bool pr_prdt)609 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt) 610 { 611 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt); 612 } 613 ufshcd_print_tmrs(struct ufs_hba * hba,unsigned long bitmap)614 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap) 615 { 616 int tag; 617 618 for_each_set_bit(tag, &bitmap, hba->nutmrs) { 619 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag]; 620 621 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag); 622 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp)); 623 } 624 } 625 ufshcd_print_host_state(struct ufs_hba * hba)626 static void ufshcd_print_host_state(struct ufs_hba *hba) 627 { 628 const struct scsi_device *sdev_ufs = hba->ufs_device_wlun; 629 630 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state); 631 dev_err(hba->dev, "%d outstanding reqs, tasks=0x%lx\n", 632 scsi_host_busy(hba->host), hba->outstanding_tasks); 633 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n", 634 hba->saved_err, hba->saved_uic_err); 635 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n", 636 hba->curr_dev_pwr_mode, hba->uic_link_state); 637 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n", 638 hba->pm_op_in_progress, hba->is_sys_suspended); 639 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n", 640 hba->auto_bkops_enabled, hba->host->host_self_blocked); 641 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state); 642 dev_err(hba->dev, 643 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n", 644 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000), 645 hba->ufs_stats.hibern8_exit_cnt); 646 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n", 647 div_u64(hba->ufs_stats.last_intr_ts, 1000), 648 hba->ufs_stats.last_intr_status); 649 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n", 650 hba->eh_flags, hba->req_abort_count); 651 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n", 652 hba->ufs_version, hba->capabilities, hba->caps); 653 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks, 654 hba->dev_quirks); 655 if (sdev_ufs) 656 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n", 657 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev); 658 659 ufshcd_print_clk_freqs(hba); 660 } 661 662 /** 663 * ufshcd_print_pwr_info - print power params as saved in hba 664 * power info 665 * @hba: per-adapter instance 666 */ ufshcd_print_pwr_info(struct ufs_hba * hba)667 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 668 { 669 static const char * const names[] = { 670 "INVALID MODE", 671 "FAST MODE", 672 "SLOW_MODE", 673 "INVALID MODE", 674 "FASTAUTO_MODE", 675 "SLOWAUTO_MODE", 676 "INVALID MODE", 677 }; 678 679 /* 680 * Using dev_dbg to avoid messages during runtime PM to avoid 681 * never-ending cycles of messages written back to storage by user space 682 * causing runtime resume, causing more messages and so on. 683 */ 684 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 685 __func__, 686 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 687 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 688 names[hba->pwr_info.pwr_rx], 689 names[hba->pwr_info.pwr_tx], 690 hba->pwr_info.hs_rate); 691 } 692 ufshcd_device_reset(struct ufs_hba * hba)693 static void ufshcd_device_reset(struct ufs_hba *hba) 694 { 695 int err; 696 697 err = ufshcd_vops_device_reset(hba); 698 699 if (!err) { 700 ufshcd_set_ufs_dev_active(hba); 701 if (ufshcd_is_wb_allowed(hba)) { 702 hba->dev_info.wb_enabled = false; 703 hba->dev_info.wb_buf_flush_enabled = false; 704 } 705 if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE) 706 hba->dev_info.rtc_time_baseline = 0; 707 } 708 if (err != -EOPNOTSUPP) 709 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err); 710 } 711 ufshcd_delay_us(unsigned long us,unsigned long tolerance)712 void ufshcd_delay_us(unsigned long us, unsigned long tolerance) 713 { 714 if (!us) 715 return; 716 717 if (us < 10) 718 udelay(us); 719 else 720 usleep_range(us, us + tolerance); 721 } 722 EXPORT_SYMBOL_GPL(ufshcd_delay_us); 723 724 /** 725 * ufshcd_wait_for_register - wait for register value to change 726 * @hba: per-adapter interface 727 * @reg: mmio register offset 728 * @mask: mask to apply to the read register value 729 * @val: value to wait for 730 * @interval_us: polling interval in microseconds 731 * @timeout_ms: timeout in milliseconds 732 * 733 * Return: -ETIMEDOUT on error, zero on success. 734 */ ufshcd_wait_for_register(struct ufs_hba * hba,u32 reg,u32 mask,u32 val,unsigned long interval_us,unsigned long timeout_ms)735 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 736 u32 val, unsigned long interval_us, 737 unsigned long timeout_ms) 738 { 739 u32 v; 740 741 val &= mask; /* ignore bits that we don't intend to wait on */ 742 743 return read_poll_timeout(ufshcd_readl, v, (v & mask) == val, 744 interval_us, timeout_ms * 1000, false, hba, reg); 745 } 746 747 /** 748 * ufshcd_get_intr_mask - Get the interrupt bit mask 749 * @hba: Pointer to adapter instance 750 * 751 * Return: interrupt bit mask per version 752 */ ufshcd_get_intr_mask(struct ufs_hba * hba)753 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 754 { 755 if (hba->ufs_version <= ufshci_version(2, 0)) 756 return INTERRUPT_MASK_ALL_VER_11; 757 758 return INTERRUPT_MASK_ALL_VER_21; 759 } 760 761 /** 762 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 763 * @hba: Pointer to adapter instance 764 * 765 * Return: UFSHCI version supported by the controller 766 */ ufshcd_get_ufs_version(struct ufs_hba * hba)767 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 768 { 769 u32 ufshci_ver; 770 771 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION) 772 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba); 773 else 774 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION); 775 776 /* 777 * UFSHCI v1.x uses a different version scheme, in order 778 * to allow the use of comparisons with the ufshci_version 779 * function, we convert it to the same scheme as ufs 2.0+. 780 */ 781 if (ufshci_ver & 0x00010000) 782 return ufshci_version(1, ufshci_ver & 0x00000100); 783 784 return ufshci_ver; 785 } 786 787 /** 788 * ufshcd_is_device_present - Check if any device connected to 789 * the host controller 790 * @hba: pointer to adapter instance 791 * 792 * Return: true if device present, false if no device detected 793 */ ufshcd_is_device_present(struct ufs_hba * hba)794 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 795 { 796 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT; 797 } 798 799 /** 800 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 801 * @lrbp: pointer to local command reference block 802 * @cqe: pointer to the completion queue entry 803 * 804 * This function is used to get the OCS field from UTRD 805 * 806 * Return: the OCS field in the UTRD. 807 */ ufshcd_get_tr_ocs(struct ufshcd_lrb * lrbp,struct cq_entry * cqe)808 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp, 809 struct cq_entry *cqe) 810 { 811 if (cqe) 812 return le32_to_cpu(cqe->status) & MASK_OCS; 813 814 return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS; 815 } 816 817 /** 818 * ufshcd_utrl_clear() - Clear requests from the controller request list. 819 * @hba: per adapter instance 820 * @mask: mask with one bit set for each request to be cleared 821 */ ufshcd_utrl_clear(struct ufs_hba * hba,u32 mask)822 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask) 823 { 824 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 825 mask = ~mask; 826 /* 827 * From the UFSHCI specification: "UTP Transfer Request List CLear 828 * Register (UTRLCLR): This field is bit significant. Each bit 829 * corresponds to a slot in the UTP Transfer Request List, where bit 0 830 * corresponds to request slot 0. A bit in this field is set to ‘0’ 831 * by host software to indicate to the host controller that a transfer 832 * request slot is cleared. The host controller 833 * shall free up any resources associated to the request slot 834 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The 835 * host software indicates no change to request slots by setting the 836 * associated bits in this field to ‘1’. Bits in this field shall only 837 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’." 838 */ 839 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR); 840 } 841 842 /** 843 * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register 844 * @hba: per adapter instance 845 * @pos: position of the bit to be cleared 846 */ ufshcd_utmrl_clear(struct ufs_hba * hba,u32 pos)847 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos) 848 { 849 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 850 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 851 else 852 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 853 } 854 855 /** 856 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 857 * @reg: Register value of host controller status 858 * 859 * Return: 0 on success; a positive value if failed. 860 */ ufshcd_get_lists_status(u32 reg)861 static inline int ufshcd_get_lists_status(u32 reg) 862 { 863 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 864 } 865 866 /** 867 * ufshcd_get_uic_cmd_result - Get the UIC command result 868 * @hba: Pointer to adapter instance 869 * 870 * This function gets the result of UIC command completion 871 * 872 * Return: 0 on success; non-zero value on error. 873 */ ufshcd_get_uic_cmd_result(struct ufs_hba * hba)874 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 875 { 876 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 877 MASK_UIC_COMMAND_RESULT; 878 } 879 880 /** 881 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 882 * @hba: Pointer to adapter instance 883 * 884 * This function gets UIC command argument3 885 * 886 * Return: 0 on success; non-zero value on error. 887 */ ufshcd_get_dme_attr_val(struct ufs_hba * hba)888 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 889 { 890 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 891 } 892 893 /** 894 * ufshcd_get_req_rsp - returns the TR response transaction type 895 * @ucd_rsp_ptr: pointer to response UPIU 896 * 897 * Return: UPIU type. 898 */ 899 static inline enum upiu_response_transaction ufshcd_get_req_rsp(struct utp_upiu_rsp * ucd_rsp_ptr)900 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 901 { 902 return ucd_rsp_ptr->header.transaction_code; 903 } 904 905 /** 906 * ufshcd_is_exception_event - Check if the device raised an exception event 907 * @ucd_rsp_ptr: pointer to response UPIU 908 * 909 * The function checks if the device raised an exception event indicated in 910 * the Device Information field of response UPIU. 911 * 912 * Return: true if exception is raised, false otherwise. 913 */ ufshcd_is_exception_event(struct utp_upiu_rsp * ucd_rsp_ptr)914 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr) 915 { 916 return ucd_rsp_ptr->header.device_information & 1; 917 } 918 919 /** 920 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values. 921 * @hba: per adapter instance 922 */ 923 static inline void ufshcd_reset_intr_aggr(struct ufs_hba * hba)924 ufshcd_reset_intr_aggr(struct ufs_hba *hba) 925 { 926 ufshcd_writel(hba, INT_AGGR_ENABLE | 927 INT_AGGR_COUNTER_AND_TIMER_RESET, 928 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 929 } 930 931 /** 932 * ufshcd_config_intr_aggr - Configure interrupt aggregation values. 933 * @hba: per adapter instance 934 * @cnt: Interrupt aggregation counter threshold 935 * @tmout: Interrupt aggregation timeout value 936 */ 937 static inline void ufshcd_config_intr_aggr(struct ufs_hba * hba,u8 cnt,u8 tmout)938 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout) 939 { 940 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | 941 INT_AGGR_COUNTER_THLD_VAL(cnt) | 942 INT_AGGR_TIMEOUT_VAL(tmout), 943 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 944 } 945 946 /** 947 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 948 * @hba: per adapter instance 949 */ ufshcd_disable_intr_aggr(struct ufs_hba * hba)950 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 951 { 952 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 953 } 954 955 /** 956 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 957 * When run-stop registers are set to 1, it indicates the 958 * host controller that it can process the requests 959 * @hba: per adapter instance 960 */ ufshcd_enable_run_stop_reg(struct ufs_hba * hba)961 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 962 { 963 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 964 REG_UTP_TASK_REQ_LIST_RUN_STOP); 965 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 966 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 967 } 968 969 /** 970 * ufshcd_hba_start - Start controller initialization sequence 971 * @hba: per adapter instance 972 */ ufshcd_hba_start(struct ufs_hba * hba)973 static inline void ufshcd_hba_start(struct ufs_hba *hba) 974 { 975 u32 val = CONTROLLER_ENABLE; 976 977 if (ufshcd_crypto_enable(hba)) 978 val |= CRYPTO_GENERAL_ENABLE; 979 980 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); 981 } 982 983 /** 984 * ufshcd_is_hba_active - Get controller state 985 * @hba: per adapter instance 986 * 987 * Return: true if and only if the controller is active. 988 */ ufshcd_is_hba_active(struct ufs_hba * hba)989 bool ufshcd_is_hba_active(struct ufs_hba *hba) 990 { 991 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE; 992 } 993 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active); 994 995 /** 996 * ufshcd_pm_qos_init - initialize PM QoS request 997 * @hba: per adapter instance 998 */ ufshcd_pm_qos_init(struct ufs_hba * hba)999 void ufshcd_pm_qos_init(struct ufs_hba *hba) 1000 { 1001 1002 if (hba->pm_qos_enabled) 1003 return; 1004 1005 cpu_latency_qos_add_request(&hba->pm_qos_req, PM_QOS_DEFAULT_VALUE); 1006 1007 if (cpu_latency_qos_request_active(&hba->pm_qos_req)) 1008 hba->pm_qos_enabled = true; 1009 } 1010 1011 /** 1012 * ufshcd_pm_qos_exit - remove request from PM QoS 1013 * @hba: per adapter instance 1014 */ ufshcd_pm_qos_exit(struct ufs_hba * hba)1015 void ufshcd_pm_qos_exit(struct ufs_hba *hba) 1016 { 1017 if (!hba->pm_qos_enabled) 1018 return; 1019 1020 cpu_latency_qos_remove_request(&hba->pm_qos_req); 1021 hba->pm_qos_enabled = false; 1022 } 1023 1024 /** 1025 * ufshcd_pm_qos_update - update PM QoS request 1026 * @hba: per adapter instance 1027 * @on: If True, vote for perf PM QoS mode otherwise power save mode 1028 */ ufshcd_pm_qos_update(struct ufs_hba * hba,bool on)1029 static void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on) 1030 { 1031 if (!hba->pm_qos_enabled) 1032 return; 1033 1034 cpu_latency_qos_update_request(&hba->pm_qos_req, on ? 0 : PM_QOS_DEFAULT_VALUE); 1035 } 1036 1037 /** 1038 * ufshcd_set_clk_freq - set UFS controller clock frequencies 1039 * @hba: per adapter instance 1040 * @scale_up: If True, set max possible frequency othewise set low frequency 1041 * 1042 * Return: 0 if successful; < 0 upon failure. 1043 */ ufshcd_set_clk_freq(struct ufs_hba * hba,bool scale_up)1044 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up) 1045 { 1046 int ret = 0; 1047 struct ufs_clk_info *clki; 1048 struct list_head *head = &hba->clk_list_head; 1049 1050 if (list_empty(head)) 1051 goto out; 1052 1053 list_for_each_entry(clki, head, list) { 1054 if (!IS_ERR_OR_NULL(clki->clk)) { 1055 if (scale_up && clki->max_freq) { 1056 if (clki->curr_freq == clki->max_freq) 1057 continue; 1058 1059 ret = clk_set_rate(clki->clk, clki->max_freq); 1060 if (ret) { 1061 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1062 __func__, clki->name, 1063 clki->max_freq, ret); 1064 break; 1065 } 1066 trace_ufshcd_clk_scaling(hba, 1067 "scaled up", clki->name, 1068 clki->curr_freq, 1069 clki->max_freq); 1070 1071 clki->curr_freq = clki->max_freq; 1072 1073 } else if (!scale_up && clki->min_freq) { 1074 if (clki->curr_freq == clki->min_freq) 1075 continue; 1076 1077 ret = clk_set_rate(clki->clk, clki->min_freq); 1078 if (ret) { 1079 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1080 __func__, clki->name, 1081 clki->min_freq, ret); 1082 break; 1083 } 1084 trace_ufshcd_clk_scaling(hba, 1085 "scaled down", clki->name, 1086 clki->curr_freq, 1087 clki->min_freq); 1088 clki->curr_freq = clki->min_freq; 1089 } 1090 } 1091 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__, 1092 clki->name, clk_get_rate(clki->clk)); 1093 } 1094 1095 out: 1096 return ret; 1097 } 1098 ufshcd_opp_config_clks(struct device * dev,struct opp_table * opp_table,struct dev_pm_opp * opp,void * data,bool scaling_down)1099 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, 1100 struct dev_pm_opp *opp, void *data, 1101 bool scaling_down) 1102 { 1103 struct ufs_hba *hba = dev_get_drvdata(dev); 1104 struct list_head *head = &hba->clk_list_head; 1105 struct ufs_clk_info *clki; 1106 unsigned long freq; 1107 u8 idx = 0; 1108 int ret; 1109 1110 list_for_each_entry(clki, head, list) { 1111 if (!IS_ERR_OR_NULL(clki->clk)) { 1112 freq = dev_pm_opp_get_freq_indexed(opp, idx++); 1113 1114 /* Do not set rate for clocks having frequency as 0 */ 1115 if (!freq) 1116 continue; 1117 1118 ret = clk_set_rate(clki->clk, freq); 1119 if (ret) { 1120 dev_err(dev, "%s: %s clk set rate(%ldHz) failed, %d\n", 1121 __func__, clki->name, freq, ret); 1122 return ret; 1123 } 1124 1125 trace_ufshcd_clk_scaling(hba, 1126 (scaling_down ? "scaled down" : "scaled up"), 1127 clki->name, hba->clk_scaling.target_freq, freq); 1128 } 1129 } 1130 1131 return 0; 1132 } 1133 EXPORT_SYMBOL_GPL(ufshcd_opp_config_clks); 1134 ufshcd_opp_set_rate(struct ufs_hba * hba,unsigned long freq)1135 static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq) 1136 { 1137 struct dev_pm_opp *opp; 1138 int ret; 1139 1140 opp = dev_pm_opp_find_freq_floor_indexed(hba->dev, 1141 &freq, 0); 1142 if (IS_ERR(opp)) 1143 return PTR_ERR(opp); 1144 1145 ret = dev_pm_opp_set_opp(hba->dev, opp); 1146 dev_pm_opp_put(opp); 1147 1148 return ret; 1149 } 1150 1151 /** 1152 * ufshcd_scale_clks - scale up or scale down UFS controller clocks 1153 * @hba: per adapter instance 1154 * @freq: frequency to scale 1155 * @scale_up: True if scaling up and false if scaling down 1156 * 1157 * Return: 0 if successful; < 0 upon failure. 1158 */ ufshcd_scale_clks(struct ufs_hba * hba,unsigned long freq,bool scale_up)1159 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 1160 bool scale_up) 1161 { 1162 int ret = 0; 1163 ktime_t start = ktime_get(); 1164 1165 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, freq, PRE_CHANGE); 1166 if (ret) 1167 goto out; 1168 1169 if (hba->use_pm_opp) 1170 ret = ufshcd_opp_set_rate(hba, freq); 1171 else 1172 ret = ufshcd_set_clk_freq(hba, scale_up); 1173 if (ret) 1174 goto out; 1175 1176 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, freq, POST_CHANGE); 1177 if (ret) { 1178 if (hba->use_pm_opp) 1179 ufshcd_opp_set_rate(hba, 1180 hba->devfreq->previous_freq); 1181 else 1182 ufshcd_set_clk_freq(hba, !scale_up); 1183 goto out; 1184 } 1185 1186 ufshcd_pm_qos_update(hba, scale_up); 1187 1188 out: 1189 trace_ufshcd_profile_clk_scaling(hba, 1190 (scale_up ? "up" : "down"), 1191 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1192 return ret; 1193 } 1194 1195 /** 1196 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not 1197 * @hba: per adapter instance 1198 * @freq: frequency to scale 1199 * @scale_up: True if scaling up and false if scaling down 1200 * 1201 * Return: true if scaling is required, false otherwise. 1202 */ ufshcd_is_devfreq_scaling_required(struct ufs_hba * hba,unsigned long freq,bool scale_up)1203 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba, 1204 unsigned long freq, bool scale_up) 1205 { 1206 struct ufs_clk_info *clki; 1207 struct list_head *head = &hba->clk_list_head; 1208 1209 if (list_empty(head)) 1210 return false; 1211 1212 if (hba->use_pm_opp) 1213 return freq != hba->clk_scaling.target_freq; 1214 1215 list_for_each_entry(clki, head, list) { 1216 if (!IS_ERR_OR_NULL(clki->clk)) { 1217 if (scale_up && clki->max_freq) { 1218 if (clki->curr_freq == clki->max_freq) 1219 continue; 1220 return true; 1221 } else if (!scale_up && clki->min_freq) { 1222 if (clki->curr_freq == clki->min_freq) 1223 continue; 1224 return true; 1225 } 1226 } 1227 } 1228 1229 return false; 1230 } 1231 1232 /* 1233 * Determine the number of pending commands by counting the bits in the SCSI 1234 * device budget maps. This approach has been selected because a bit is set in 1235 * the budget map before scsi_host_queue_ready() checks the host_self_blocked 1236 * flag. The host_self_blocked flag can be modified by calling 1237 * scsi_block_requests() or scsi_unblock_requests(). 1238 */ ufshcd_pending_cmds(struct ufs_hba * hba)1239 static u32 ufshcd_pending_cmds(struct ufs_hba *hba) 1240 { 1241 const struct scsi_device *sdev; 1242 unsigned long flags; 1243 u32 pending = 0; 1244 1245 spin_lock_irqsave(hba->host->host_lock, flags); 1246 __shost_for_each_device(sdev, hba->host) 1247 pending += sbitmap_weight(&sdev->budget_map); 1248 spin_unlock_irqrestore(hba->host->host_lock, flags); 1249 1250 return pending; 1251 } 1252 1253 /* 1254 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1255 * has expired. 1256 * 1257 * Return: 0 upon success; -EBUSY upon timeout. 1258 */ ufshcd_wait_for_doorbell_clr(struct ufs_hba * hba,u64 wait_timeout_us)1259 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, 1260 u64 wait_timeout_us) 1261 { 1262 int ret = 0; 1263 u32 tm_doorbell; 1264 u32 tr_pending; 1265 bool timeout = false, do_last_check = false; 1266 ktime_t start; 1267 1268 ufshcd_hold(hba); 1269 /* 1270 * Wait for all the outstanding tasks/transfer requests. 1271 * Verify by checking the doorbell registers are clear. 1272 */ 1273 start = ktime_get(); 1274 do { 1275 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) { 1276 ret = -EBUSY; 1277 goto out; 1278 } 1279 1280 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 1281 tr_pending = ufshcd_pending_cmds(hba); 1282 if (!tm_doorbell && !tr_pending) { 1283 timeout = false; 1284 break; 1285 } else if (do_last_check) { 1286 break; 1287 } 1288 1289 io_schedule_timeout(msecs_to_jiffies(20)); 1290 if (ktime_to_us(ktime_sub(ktime_get(), start)) > 1291 wait_timeout_us) { 1292 timeout = true; 1293 /* 1294 * We might have scheduled out for long time so make 1295 * sure to check if doorbells are cleared by this time 1296 * or not. 1297 */ 1298 do_last_check = true; 1299 } 1300 } while (tm_doorbell || tr_pending); 1301 1302 if (timeout) { 1303 dev_err(hba->dev, 1304 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n", 1305 __func__, tm_doorbell, tr_pending); 1306 ret = -EBUSY; 1307 } 1308 out: 1309 ufshcd_release(hba); 1310 return ret; 1311 } 1312 1313 /** 1314 * ufshcd_scale_gear - scale up/down UFS gear 1315 * @hba: per adapter instance 1316 * @target_gear: target gear to scale to 1317 * @scale_up: True for scaling up gear and false for scaling down 1318 * 1319 * Return: 0 for success; -EBUSY if scaling can't happen at this time; 1320 * non-zero for any other errors. 1321 */ ufshcd_scale_gear(struct ufs_hba * hba,u32 target_gear,bool scale_up)1322 static int ufshcd_scale_gear(struct ufs_hba *hba, u32 target_gear, bool scale_up) 1323 { 1324 int ret = 0; 1325 struct ufs_pa_layer_attr new_pwr_info; 1326 1327 if (target_gear) { 1328 new_pwr_info = hba->pwr_info; 1329 new_pwr_info.gear_tx = target_gear; 1330 new_pwr_info.gear_rx = target_gear; 1331 1332 goto config_pwr_mode; 1333 } 1334 1335 /* Legacy gear scaling, in case vops_freq_to_gear_speed() is not implemented */ 1336 if (scale_up) { 1337 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info, 1338 sizeof(struct ufs_pa_layer_attr)); 1339 } else { 1340 memcpy(&new_pwr_info, &hba->pwr_info, 1341 sizeof(struct ufs_pa_layer_attr)); 1342 1343 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear || 1344 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) { 1345 /* save the current power mode */ 1346 memcpy(&hba->clk_scaling.saved_pwr_info, 1347 &hba->pwr_info, 1348 sizeof(struct ufs_pa_layer_attr)); 1349 1350 /* scale down gear */ 1351 new_pwr_info.gear_tx = hba->clk_scaling.min_gear; 1352 new_pwr_info.gear_rx = hba->clk_scaling.min_gear; 1353 } 1354 } 1355 1356 config_pwr_mode: 1357 /* check if the power mode needs to be changed or not? */ 1358 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info); 1359 if (ret) 1360 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)", 1361 __func__, ret, 1362 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx, 1363 new_pwr_info.gear_tx, new_pwr_info.gear_rx); 1364 1365 return ret; 1366 } 1367 1368 /* 1369 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1370 * has expired. 1371 * 1372 * Return: 0 upon success; -EBUSY upon timeout. 1373 */ ufshcd_clock_scaling_prepare(struct ufs_hba * hba,u64 timeout_us)1374 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us) 1375 { 1376 int ret = 0; 1377 /* 1378 * make sure that there are no outstanding requests when 1379 * clock scaling is in progress 1380 */ 1381 blk_mq_quiesce_tagset(&hba->host->tag_set); 1382 mutex_lock(&hba->wb_mutex); 1383 down_write(&hba->clk_scaling_lock); 1384 1385 if (!hba->clk_scaling.is_allowed || 1386 ufshcd_wait_for_doorbell_clr(hba, timeout_us)) { 1387 ret = -EBUSY; 1388 up_write(&hba->clk_scaling_lock); 1389 mutex_unlock(&hba->wb_mutex); 1390 blk_mq_unquiesce_tagset(&hba->host->tag_set); 1391 goto out; 1392 } 1393 1394 /* let's not get into low power until clock scaling is completed */ 1395 ufshcd_hold(hba); 1396 1397 out: 1398 return ret; 1399 } 1400 ufshcd_clock_scaling_unprepare(struct ufs_hba * hba,int err)1401 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err) 1402 { 1403 up_write(&hba->clk_scaling_lock); 1404 1405 /* Enable Write Booster if current gear requires it else disable it */ 1406 if (ufshcd_enable_wb_if_scaling_up(hba) && !err) 1407 ufshcd_wb_toggle(hba, hba->pwr_info.gear_rx >= hba->clk_scaling.wb_gear); 1408 1409 mutex_unlock(&hba->wb_mutex); 1410 1411 blk_mq_unquiesce_tagset(&hba->host->tag_set); 1412 ufshcd_release(hba); 1413 } 1414 1415 /** 1416 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear 1417 * @hba: per adapter instance 1418 * @freq: frequency to scale 1419 * @scale_up: True for scaling up and false for scalin down 1420 * 1421 * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero 1422 * for any other errors. 1423 */ ufshcd_devfreq_scale(struct ufs_hba * hba,unsigned long freq,bool scale_up)1424 static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq, 1425 bool scale_up) 1426 { 1427 u32 old_gear = hba->pwr_info.gear_rx; 1428 u32 new_gear = 0; 1429 int ret = 0; 1430 1431 new_gear = ufshcd_vops_freq_to_gear_speed(hba, freq); 1432 1433 ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC); 1434 if (ret) 1435 return ret; 1436 1437 /* scale down the gear before scaling down clocks */ 1438 if (!scale_up) { 1439 ret = ufshcd_scale_gear(hba, new_gear, false); 1440 if (ret) 1441 goto out_unprepare; 1442 } 1443 1444 ret = ufshcd_scale_clks(hba, freq, scale_up); 1445 if (ret) { 1446 if (!scale_up) 1447 ufshcd_scale_gear(hba, old_gear, true); 1448 goto out_unprepare; 1449 } 1450 1451 /* scale up the gear after scaling up clocks */ 1452 if (scale_up) { 1453 ret = ufshcd_scale_gear(hba, new_gear, true); 1454 if (ret) { 1455 ufshcd_scale_clks(hba, hba->devfreq->previous_freq, 1456 false); 1457 goto out_unprepare; 1458 } 1459 } 1460 1461 out_unprepare: 1462 ufshcd_clock_scaling_unprepare(hba, ret); 1463 return ret; 1464 } 1465 ufshcd_clk_scaling_suspend_work(struct work_struct * work)1466 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work) 1467 { 1468 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1469 clk_scaling.suspend_work); 1470 1471 scoped_guard(spinlock_irqsave, &hba->clk_scaling.lock) 1472 { 1473 if (hba->clk_scaling.active_reqs || 1474 hba->clk_scaling.is_suspended) 1475 return; 1476 1477 hba->clk_scaling.is_suspended = true; 1478 hba->clk_scaling.window_start_t = 0; 1479 } 1480 1481 devfreq_suspend_device(hba->devfreq); 1482 } 1483 ufshcd_clk_scaling_resume_work(struct work_struct * work)1484 static void ufshcd_clk_scaling_resume_work(struct work_struct *work) 1485 { 1486 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1487 clk_scaling.resume_work); 1488 1489 scoped_guard(spinlock_irqsave, &hba->clk_scaling.lock) 1490 { 1491 if (!hba->clk_scaling.is_suspended) 1492 return; 1493 hba->clk_scaling.is_suspended = false; 1494 } 1495 1496 devfreq_resume_device(hba->devfreq); 1497 } 1498 ufshcd_devfreq_target(struct device * dev,unsigned long * freq,u32 flags)1499 static int ufshcd_devfreq_target(struct device *dev, 1500 unsigned long *freq, u32 flags) 1501 { 1502 int ret = 0; 1503 struct ufs_hba *hba = dev_get_drvdata(dev); 1504 ktime_t start; 1505 bool scale_up = false, sched_clk_scaling_suspend_work = false; 1506 struct list_head *clk_list = &hba->clk_list_head; 1507 struct ufs_clk_info *clki; 1508 1509 if (!ufshcd_is_clkscaling_supported(hba)) 1510 return -EINVAL; 1511 1512 if (hba->use_pm_opp) { 1513 struct dev_pm_opp *opp; 1514 1515 /* Get the recommended frequency from OPP framework */ 1516 opp = devfreq_recommended_opp(dev, freq, flags); 1517 if (IS_ERR(opp)) 1518 return PTR_ERR(opp); 1519 1520 dev_pm_opp_put(opp); 1521 } else { 1522 /* Override with the closest supported frequency */ 1523 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, 1524 list); 1525 *freq = (unsigned long) clk_round_rate(clki->clk, *freq); 1526 } 1527 1528 scoped_guard(spinlock_irqsave, &hba->clk_scaling.lock) 1529 { 1530 if (ufshcd_eh_in_progress(hba)) 1531 return 0; 1532 1533 /* Skip scaling clock when clock scaling is suspended */ 1534 if (hba->clk_scaling.is_suspended) { 1535 dev_warn(hba->dev, "clock scaling is suspended, skip"); 1536 return 0; 1537 } 1538 1539 if (!hba->clk_scaling.active_reqs) 1540 sched_clk_scaling_suspend_work = true; 1541 1542 if (list_empty(clk_list)) 1543 goto out; 1544 1545 /* Decide based on the target or rounded-off frequency and update */ 1546 if (hba->use_pm_opp) 1547 scale_up = *freq > hba->clk_scaling.target_freq; 1548 else 1549 scale_up = *freq == clki->max_freq; 1550 1551 if (!hba->use_pm_opp && !scale_up) 1552 *freq = clki->min_freq; 1553 1554 /* Update the frequency */ 1555 if (!ufshcd_is_devfreq_scaling_required(hba, *freq, scale_up)) { 1556 ret = 0; 1557 goto out; /* no state change required */ 1558 } 1559 } 1560 1561 start = ktime_get(); 1562 ret = ufshcd_devfreq_scale(hba, *freq, scale_up); 1563 if (!ret) 1564 hba->clk_scaling.target_freq = *freq; 1565 1566 trace_ufshcd_profile_clk_scaling(hba, 1567 (scale_up ? "up" : "down"), 1568 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1569 1570 out: 1571 if (sched_clk_scaling_suspend_work && 1572 (!scale_up || hba->clk_scaling.suspend_on_no_request)) 1573 queue_work(hba->clk_scaling.workq, 1574 &hba->clk_scaling.suspend_work); 1575 1576 return ret; 1577 } 1578 ufshcd_devfreq_get_dev_status(struct device * dev,struct devfreq_dev_status * stat)1579 static int ufshcd_devfreq_get_dev_status(struct device *dev, 1580 struct devfreq_dev_status *stat) 1581 { 1582 struct ufs_hba *hba = dev_get_drvdata(dev); 1583 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 1584 ktime_t curr_t; 1585 1586 if (!ufshcd_is_clkscaling_supported(hba)) 1587 return -EINVAL; 1588 1589 memset(stat, 0, sizeof(*stat)); 1590 1591 guard(spinlock_irqsave)(&hba->clk_scaling.lock); 1592 1593 curr_t = ktime_get(); 1594 if (!scaling->window_start_t) 1595 goto start_window; 1596 1597 /* 1598 * If current frequency is 0, then the ondemand governor considers 1599 * there's no initial frequency set. And it always requests to set 1600 * to max. frequency. 1601 */ 1602 if (hba->use_pm_opp) { 1603 stat->current_frequency = hba->clk_scaling.target_freq; 1604 } else { 1605 struct list_head *clk_list = &hba->clk_list_head; 1606 struct ufs_clk_info *clki; 1607 1608 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1609 stat->current_frequency = clki->curr_freq; 1610 } 1611 1612 if (scaling->is_busy_started) 1613 scaling->tot_busy_t += ktime_us_delta(curr_t, 1614 scaling->busy_start_t); 1615 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t); 1616 stat->busy_time = scaling->tot_busy_t; 1617 start_window: 1618 scaling->window_start_t = curr_t; 1619 scaling->tot_busy_t = 0; 1620 1621 if (scaling->active_reqs) { 1622 scaling->busy_start_t = curr_t; 1623 scaling->is_busy_started = true; 1624 } else { 1625 scaling->busy_start_t = 0; 1626 scaling->is_busy_started = false; 1627 } 1628 1629 return 0; 1630 } 1631 ufshcd_devfreq_init(struct ufs_hba * hba)1632 static int ufshcd_devfreq_init(struct ufs_hba *hba) 1633 { 1634 struct list_head *clk_list = &hba->clk_list_head; 1635 struct ufs_clk_info *clki; 1636 struct devfreq *devfreq; 1637 int ret; 1638 1639 /* Skip devfreq if we don't have any clocks in the list */ 1640 if (list_empty(clk_list)) 1641 return 0; 1642 1643 if (!hba->use_pm_opp) { 1644 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1645 dev_pm_opp_add(hba->dev, clki->min_freq, 0); 1646 dev_pm_opp_add(hba->dev, clki->max_freq, 0); 1647 } 1648 1649 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile, 1650 &hba->vps->ondemand_data); 1651 devfreq = devfreq_add_device(hba->dev, 1652 &hba->vps->devfreq_profile, 1653 DEVFREQ_GOV_SIMPLE_ONDEMAND, 1654 &hba->vps->ondemand_data); 1655 if (IS_ERR(devfreq)) { 1656 ret = PTR_ERR(devfreq); 1657 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret); 1658 1659 if (!hba->use_pm_opp) { 1660 dev_pm_opp_remove(hba->dev, clki->min_freq); 1661 dev_pm_opp_remove(hba->dev, clki->max_freq); 1662 } 1663 return ret; 1664 } 1665 1666 hba->devfreq = devfreq; 1667 1668 return 0; 1669 } 1670 ufshcd_devfreq_remove(struct ufs_hba * hba)1671 static void ufshcd_devfreq_remove(struct ufs_hba *hba) 1672 { 1673 struct list_head *clk_list = &hba->clk_list_head; 1674 1675 if (!hba->devfreq) 1676 return; 1677 1678 devfreq_remove_device(hba->devfreq); 1679 hba->devfreq = NULL; 1680 1681 if (!hba->use_pm_opp) { 1682 struct ufs_clk_info *clki; 1683 1684 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1685 dev_pm_opp_remove(hba->dev, clki->min_freq); 1686 dev_pm_opp_remove(hba->dev, clki->max_freq); 1687 } 1688 } 1689 ufshcd_suspend_clkscaling(struct ufs_hba * hba)1690 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba) 1691 { 1692 bool suspend = false; 1693 1694 cancel_work_sync(&hba->clk_scaling.suspend_work); 1695 cancel_work_sync(&hba->clk_scaling.resume_work); 1696 1697 scoped_guard(spinlock_irqsave, &hba->clk_scaling.lock) 1698 { 1699 if (!hba->clk_scaling.is_suspended) { 1700 suspend = true; 1701 hba->clk_scaling.is_suspended = true; 1702 hba->clk_scaling.window_start_t = 0; 1703 } 1704 } 1705 1706 if (suspend) 1707 devfreq_suspend_device(hba->devfreq); 1708 } 1709 ufshcd_resume_clkscaling(struct ufs_hba * hba)1710 static void ufshcd_resume_clkscaling(struct ufs_hba *hba) 1711 { 1712 bool resume = false; 1713 1714 scoped_guard(spinlock_irqsave, &hba->clk_scaling.lock) 1715 { 1716 if (hba->clk_scaling.is_suspended) { 1717 resume = true; 1718 hba->clk_scaling.is_suspended = false; 1719 } 1720 } 1721 1722 if (resume) 1723 devfreq_resume_device(hba->devfreq); 1724 } 1725 ufshcd_clkscale_enable_show(struct device * dev,struct device_attribute * attr,char * buf)1726 static ssize_t ufshcd_clkscale_enable_show(struct device *dev, 1727 struct device_attribute *attr, char *buf) 1728 { 1729 struct ufs_hba *hba = dev_get_drvdata(dev); 1730 1731 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled); 1732 } 1733 ufshcd_clkscale_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1734 static ssize_t ufshcd_clkscale_enable_store(struct device *dev, 1735 struct device_attribute *attr, const char *buf, size_t count) 1736 { 1737 struct ufs_hba *hba = dev_get_drvdata(dev); 1738 struct ufs_clk_info *clki; 1739 unsigned long freq; 1740 u32 value; 1741 int err = 0; 1742 1743 if (kstrtou32(buf, 0, &value)) 1744 return -EINVAL; 1745 1746 down(&hba->host_sem); 1747 if (!ufshcd_is_user_access_allowed(hba)) { 1748 err = -EBUSY; 1749 goto out; 1750 } 1751 1752 value = !!value; 1753 if (value == hba->clk_scaling.is_enabled) 1754 goto out; 1755 1756 ufshcd_rpm_get_sync(hba); 1757 ufshcd_hold(hba); 1758 1759 hba->clk_scaling.is_enabled = value; 1760 1761 if (value) { 1762 ufshcd_resume_clkscaling(hba); 1763 goto out_rel; 1764 } 1765 1766 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list); 1767 freq = clki->max_freq; 1768 1769 ufshcd_suspend_clkscaling(hba); 1770 1771 if (!ufshcd_is_devfreq_scaling_required(hba, freq, true)) 1772 goto out_rel; 1773 1774 err = ufshcd_devfreq_scale(hba, freq, true); 1775 if (err) 1776 dev_err(hba->dev, "%s: failed to scale clocks up %d\n", 1777 __func__, err); 1778 else 1779 hba->clk_scaling.target_freq = freq; 1780 1781 out_rel: 1782 ufshcd_release(hba); 1783 ufshcd_rpm_put_sync(hba); 1784 out: 1785 up(&hba->host_sem); 1786 return err ? err : count; 1787 } 1788 ufshcd_init_clk_scaling_sysfs(struct ufs_hba * hba)1789 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba) 1790 { 1791 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show; 1792 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store; 1793 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr); 1794 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable"; 1795 hba->clk_scaling.enable_attr.attr.mode = 0644; 1796 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr)) 1797 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n"); 1798 } 1799 ufshcd_remove_clk_scaling_sysfs(struct ufs_hba * hba)1800 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba) 1801 { 1802 if (hba->clk_scaling.enable_attr.attr.name) 1803 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr); 1804 } 1805 ufshcd_init_clk_scaling(struct ufs_hba * hba)1806 static void ufshcd_init_clk_scaling(struct ufs_hba *hba) 1807 { 1808 if (!ufshcd_is_clkscaling_supported(hba)) 1809 return; 1810 1811 if (!hba->clk_scaling.min_gear) 1812 hba->clk_scaling.min_gear = UFS_HS_G1; 1813 1814 if (!hba->clk_scaling.wb_gear) 1815 /* Use intermediate gear speed HS_G3 as the default wb_gear */ 1816 hba->clk_scaling.wb_gear = UFS_HS_G3; 1817 1818 INIT_WORK(&hba->clk_scaling.suspend_work, 1819 ufshcd_clk_scaling_suspend_work); 1820 INIT_WORK(&hba->clk_scaling.resume_work, 1821 ufshcd_clk_scaling_resume_work); 1822 1823 spin_lock_init(&hba->clk_scaling.lock); 1824 1825 hba->clk_scaling.workq = alloc_ordered_workqueue( 1826 "ufs_clkscaling_%d", WQ_MEM_RECLAIM, hba->host->host_no); 1827 1828 hba->clk_scaling.is_initialized = true; 1829 } 1830 ufshcd_exit_clk_scaling(struct ufs_hba * hba)1831 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba) 1832 { 1833 if (!hba->clk_scaling.is_initialized) 1834 return; 1835 1836 ufshcd_remove_clk_scaling_sysfs(hba); 1837 destroy_workqueue(hba->clk_scaling.workq); 1838 ufshcd_devfreq_remove(hba); 1839 hba->clk_scaling.is_initialized = false; 1840 } 1841 ufshcd_ungate_work(struct work_struct * work)1842 static void ufshcd_ungate_work(struct work_struct *work) 1843 { 1844 int ret; 1845 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1846 clk_gating.ungate_work); 1847 1848 cancel_delayed_work_sync(&hba->clk_gating.gate_work); 1849 1850 scoped_guard(spinlock_irqsave, &hba->clk_gating.lock) { 1851 if (hba->clk_gating.state == CLKS_ON) 1852 return; 1853 } 1854 1855 ufshcd_hba_vreg_set_hpm(hba); 1856 ufshcd_setup_clocks(hba, true); 1857 1858 ufshcd_enable_irq(hba); 1859 1860 /* Exit from hibern8 */ 1861 if (ufshcd_can_hibern8_during_gating(hba)) { 1862 /* Prevent gating in this path */ 1863 hba->clk_gating.is_suspended = true; 1864 if (ufshcd_is_link_hibern8(hba)) { 1865 ret = ufshcd_uic_hibern8_exit(hba); 1866 if (ret) 1867 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 1868 __func__, ret); 1869 else 1870 ufshcd_set_link_active(hba); 1871 } 1872 hba->clk_gating.is_suspended = false; 1873 } 1874 } 1875 1876 /** 1877 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release. 1878 * Also, exit from hibern8 mode and set the link as active. 1879 * @hba: per adapter instance 1880 */ ufshcd_hold(struct ufs_hba * hba)1881 void ufshcd_hold(struct ufs_hba *hba) 1882 { 1883 bool flush_result; 1884 unsigned long flags; 1885 1886 if (!ufshcd_is_clkgating_allowed(hba) || 1887 !hba->clk_gating.is_initialized) 1888 return; 1889 spin_lock_irqsave(&hba->clk_gating.lock, flags); 1890 hba->clk_gating.active_reqs++; 1891 1892 start: 1893 switch (hba->clk_gating.state) { 1894 case CLKS_ON: 1895 /* 1896 * Wait for the ungate work to complete if in progress. 1897 * Though the clocks may be in ON state, the link could 1898 * still be in hibner8 state if hibern8 is allowed 1899 * during clock gating. 1900 * Make sure we exit hibern8 state also in addition to 1901 * clocks being ON. 1902 */ 1903 if (ufshcd_can_hibern8_during_gating(hba) && 1904 ufshcd_is_link_hibern8(hba)) { 1905 spin_unlock_irqrestore(&hba->clk_gating.lock, flags); 1906 flush_result = flush_work(&hba->clk_gating.ungate_work); 1907 if (hba->clk_gating.is_suspended && !flush_result) 1908 return; 1909 spin_lock_irqsave(&hba->clk_gating.lock, flags); 1910 goto start; 1911 } 1912 break; 1913 case REQ_CLKS_OFF: 1914 if (cancel_delayed_work(&hba->clk_gating.gate_work)) { 1915 hba->clk_gating.state = CLKS_ON; 1916 trace_ufshcd_clk_gating(hba, 1917 hba->clk_gating.state); 1918 break; 1919 } 1920 /* 1921 * If we are here, it means gating work is either done or 1922 * currently running. Hence, fall through to cancel gating 1923 * work and to enable clocks. 1924 */ 1925 fallthrough; 1926 case CLKS_OFF: 1927 hba->clk_gating.state = REQ_CLKS_ON; 1928 trace_ufshcd_clk_gating(hba, 1929 hba->clk_gating.state); 1930 queue_work(hba->clk_gating.clk_gating_workq, 1931 &hba->clk_gating.ungate_work); 1932 /* 1933 * fall through to check if we should wait for this 1934 * work to be done or not. 1935 */ 1936 fallthrough; 1937 case REQ_CLKS_ON: 1938 spin_unlock_irqrestore(&hba->clk_gating.lock, flags); 1939 flush_work(&hba->clk_gating.ungate_work); 1940 /* Make sure state is CLKS_ON before returning */ 1941 spin_lock_irqsave(&hba->clk_gating.lock, flags); 1942 goto start; 1943 default: 1944 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n", 1945 __func__, hba->clk_gating.state); 1946 break; 1947 } 1948 spin_unlock_irqrestore(&hba->clk_gating.lock, flags); 1949 } 1950 EXPORT_SYMBOL_GPL(ufshcd_hold); 1951 ufshcd_gate_work(struct work_struct * work)1952 static void ufshcd_gate_work(struct work_struct *work) 1953 { 1954 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1955 clk_gating.gate_work.work); 1956 int ret; 1957 1958 scoped_guard(spinlock_irqsave, &hba->clk_gating.lock) { 1959 /* 1960 * In case you are here to cancel this work the gating state 1961 * would be marked as REQ_CLKS_ON. In this case save time by 1962 * skipping the gating work and exit after changing the clock 1963 * state to CLKS_ON. 1964 */ 1965 if (hba->clk_gating.is_suspended || 1966 hba->clk_gating.state != REQ_CLKS_OFF) { 1967 hba->clk_gating.state = CLKS_ON; 1968 trace_ufshcd_clk_gating(hba, 1969 hba->clk_gating.state); 1970 return; 1971 } 1972 1973 if (hba->clk_gating.active_reqs) 1974 return; 1975 } 1976 1977 scoped_guard(spinlock_irqsave, hba->host->host_lock) { 1978 if (ufshcd_is_ufs_dev_busy(hba) || 1979 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) 1980 return; 1981 } 1982 1983 /* put the link into hibern8 mode before turning off clocks */ 1984 if (ufshcd_can_hibern8_during_gating(hba)) { 1985 ret = ufshcd_uic_hibern8_enter(hba); 1986 if (ret) { 1987 hba->clk_gating.state = CLKS_ON; 1988 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 1989 __func__, ret); 1990 trace_ufshcd_clk_gating(hba, 1991 hba->clk_gating.state); 1992 return; 1993 } 1994 ufshcd_set_link_hibern8(hba); 1995 } 1996 1997 ufshcd_disable_irq(hba); 1998 1999 ufshcd_setup_clocks(hba, false); 2000 2001 /* Put the host controller in low power mode if possible */ 2002 ufshcd_hba_vreg_set_lpm(hba); 2003 /* 2004 * In case you are here to cancel this work the gating state 2005 * would be marked as REQ_CLKS_ON. In this case keep the state 2006 * as REQ_CLKS_ON which would anyway imply that clocks are off 2007 * and a request to turn them on is pending. By doing this way, 2008 * we keep the state machine in tact and this would ultimately 2009 * prevent from doing cancel work multiple times when there are 2010 * new requests arriving before the current cancel work is done. 2011 */ 2012 guard(spinlock_irqsave)(&hba->clk_gating.lock); 2013 if (hba->clk_gating.state == REQ_CLKS_OFF) { 2014 hba->clk_gating.state = CLKS_OFF; 2015 trace_ufshcd_clk_gating(hba, 2016 hba->clk_gating.state); 2017 } 2018 } 2019 __ufshcd_release(struct ufs_hba * hba)2020 static void __ufshcd_release(struct ufs_hba *hba) 2021 { 2022 lockdep_assert_held(&hba->clk_gating.lock); 2023 2024 if (!ufshcd_is_clkgating_allowed(hba)) 2025 return; 2026 2027 hba->clk_gating.active_reqs--; 2028 2029 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended || 2030 !hba->clk_gating.is_initialized || 2031 hba->clk_gating.state == CLKS_OFF) 2032 return; 2033 2034 scoped_guard(spinlock_irqsave, hba->host->host_lock) { 2035 if (ufshcd_has_pending_tasks(hba) || 2036 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) 2037 return; 2038 } 2039 2040 hba->clk_gating.state = REQ_CLKS_OFF; 2041 trace_ufshcd_clk_gating(hba, hba->clk_gating.state); 2042 queue_delayed_work(hba->clk_gating.clk_gating_workq, 2043 &hba->clk_gating.gate_work, 2044 msecs_to_jiffies(hba->clk_gating.delay_ms)); 2045 } 2046 ufshcd_release(struct ufs_hba * hba)2047 void ufshcd_release(struct ufs_hba *hba) 2048 { 2049 guard(spinlock_irqsave)(&hba->clk_gating.lock); 2050 __ufshcd_release(hba); 2051 } 2052 EXPORT_SYMBOL_GPL(ufshcd_release); 2053 ufshcd_clkgate_delay_show(struct device * dev,struct device_attribute * attr,char * buf)2054 static ssize_t ufshcd_clkgate_delay_show(struct device *dev, 2055 struct device_attribute *attr, char *buf) 2056 { 2057 struct ufs_hba *hba = dev_get_drvdata(dev); 2058 2059 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms); 2060 } 2061 ufshcd_clkgate_delay_set(struct device * dev,unsigned long value)2062 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value) 2063 { 2064 struct ufs_hba *hba = dev_get_drvdata(dev); 2065 2066 guard(spinlock_irqsave)(&hba->clk_gating.lock); 2067 hba->clk_gating.delay_ms = value; 2068 } 2069 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set); 2070 ufshcd_clkgate_delay_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2071 static ssize_t ufshcd_clkgate_delay_store(struct device *dev, 2072 struct device_attribute *attr, const char *buf, size_t count) 2073 { 2074 unsigned long value; 2075 2076 if (kstrtoul(buf, 0, &value)) 2077 return -EINVAL; 2078 2079 ufshcd_clkgate_delay_set(dev, value); 2080 return count; 2081 } 2082 ufshcd_clkgate_enable_show(struct device * dev,struct device_attribute * attr,char * buf)2083 static ssize_t ufshcd_clkgate_enable_show(struct device *dev, 2084 struct device_attribute *attr, char *buf) 2085 { 2086 struct ufs_hba *hba = dev_get_drvdata(dev); 2087 2088 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled); 2089 } 2090 ufshcd_clkgate_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2091 static ssize_t ufshcd_clkgate_enable_store(struct device *dev, 2092 struct device_attribute *attr, const char *buf, size_t count) 2093 { 2094 struct ufs_hba *hba = dev_get_drvdata(dev); 2095 u32 value; 2096 2097 if (kstrtou32(buf, 0, &value)) 2098 return -EINVAL; 2099 2100 value = !!value; 2101 2102 guard(spinlock_irqsave)(&hba->clk_gating.lock); 2103 2104 if (value == hba->clk_gating.is_enabled) 2105 return count; 2106 2107 if (value) 2108 __ufshcd_release(hba); 2109 else 2110 hba->clk_gating.active_reqs++; 2111 2112 hba->clk_gating.is_enabled = value; 2113 2114 return count; 2115 } 2116 ufshcd_init_clk_gating_sysfs(struct ufs_hba * hba)2117 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba) 2118 { 2119 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show; 2120 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store; 2121 sysfs_attr_init(&hba->clk_gating.delay_attr.attr); 2122 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms"; 2123 hba->clk_gating.delay_attr.attr.mode = 0644; 2124 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr)) 2125 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n"); 2126 2127 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show; 2128 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store; 2129 sysfs_attr_init(&hba->clk_gating.enable_attr.attr); 2130 hba->clk_gating.enable_attr.attr.name = "clkgate_enable"; 2131 hba->clk_gating.enable_attr.attr.mode = 0644; 2132 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr)) 2133 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n"); 2134 } 2135 ufshcd_remove_clk_gating_sysfs(struct ufs_hba * hba)2136 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba) 2137 { 2138 if (hba->clk_gating.delay_attr.attr.name) 2139 device_remove_file(hba->dev, &hba->clk_gating.delay_attr); 2140 if (hba->clk_gating.enable_attr.attr.name) 2141 device_remove_file(hba->dev, &hba->clk_gating.enable_attr); 2142 } 2143 ufshcd_init_clk_gating(struct ufs_hba * hba)2144 static void ufshcd_init_clk_gating(struct ufs_hba *hba) 2145 { 2146 if (!ufshcd_is_clkgating_allowed(hba)) 2147 return; 2148 2149 hba->clk_gating.state = CLKS_ON; 2150 2151 hba->clk_gating.delay_ms = 150; 2152 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work); 2153 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work); 2154 2155 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue( 2156 "ufs_clk_gating_%d", WQ_MEM_RECLAIM | WQ_HIGHPRI, 2157 hba->host->host_no); 2158 2159 ufshcd_init_clk_gating_sysfs(hba); 2160 2161 hba->clk_gating.is_enabled = true; 2162 hba->clk_gating.is_initialized = true; 2163 } 2164 ufshcd_exit_clk_gating(struct ufs_hba * hba)2165 static void ufshcd_exit_clk_gating(struct ufs_hba *hba) 2166 { 2167 if (!hba->clk_gating.is_initialized) 2168 return; 2169 2170 ufshcd_remove_clk_gating_sysfs(hba); 2171 2172 /* Ungate the clock if necessary. */ 2173 ufshcd_hold(hba); 2174 hba->clk_gating.is_initialized = false; 2175 ufshcd_release(hba); 2176 2177 destroy_workqueue(hba->clk_gating.clk_gating_workq); 2178 } 2179 ufshcd_clk_scaling_start_busy(struct ufs_hba * hba)2180 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba) 2181 { 2182 bool queue_resume_work = false; 2183 ktime_t curr_t = ktime_get(); 2184 2185 if (!ufshcd_is_clkscaling_supported(hba)) 2186 return; 2187 2188 guard(spinlock_irqsave)(&hba->clk_scaling.lock); 2189 2190 if (!hba->clk_scaling.active_reqs++) 2191 queue_resume_work = true; 2192 2193 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) 2194 return; 2195 2196 if (queue_resume_work) 2197 queue_work(hba->clk_scaling.workq, 2198 &hba->clk_scaling.resume_work); 2199 2200 if (!hba->clk_scaling.window_start_t) { 2201 hba->clk_scaling.window_start_t = curr_t; 2202 hba->clk_scaling.tot_busy_t = 0; 2203 hba->clk_scaling.is_busy_started = false; 2204 } 2205 2206 if (!hba->clk_scaling.is_busy_started) { 2207 hba->clk_scaling.busy_start_t = curr_t; 2208 hba->clk_scaling.is_busy_started = true; 2209 } 2210 } 2211 ufshcd_clk_scaling_update_busy(struct ufs_hba * hba)2212 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba) 2213 { 2214 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 2215 2216 if (!ufshcd_is_clkscaling_supported(hba)) 2217 return; 2218 2219 guard(spinlock_irqsave)(&hba->clk_scaling.lock); 2220 2221 hba->clk_scaling.active_reqs--; 2222 if (!scaling->active_reqs && scaling->is_busy_started) { 2223 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(), 2224 scaling->busy_start_t)); 2225 scaling->busy_start_t = 0; 2226 scaling->is_busy_started = false; 2227 } 2228 } 2229 ufshcd_monitor_opcode2dir(u8 opcode)2230 static inline int ufshcd_monitor_opcode2dir(u8 opcode) 2231 { 2232 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16) 2233 return READ; 2234 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16) 2235 return WRITE; 2236 else 2237 return -EINVAL; 2238 } 2239 ufshcd_should_inform_monitor(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2240 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba, 2241 struct ufshcd_lrb *lrbp) 2242 { 2243 const struct ufs_hba_monitor *m = &hba->monitor; 2244 2245 return (m->enabled && lrbp && lrbp->cmd && 2246 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) && 2247 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp)); 2248 } 2249 ufshcd_start_monitor(struct ufs_hba * hba,const struct ufshcd_lrb * lrbp)2250 static void ufshcd_start_monitor(struct ufs_hba *hba, 2251 const struct ufshcd_lrb *lrbp) 2252 { 2253 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2254 unsigned long flags; 2255 2256 spin_lock_irqsave(hba->host->host_lock, flags); 2257 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0) 2258 hba->monitor.busy_start_ts[dir] = ktime_get(); 2259 spin_unlock_irqrestore(hba->host->host_lock, flags); 2260 } 2261 ufshcd_update_monitor(struct ufs_hba * hba,const struct ufshcd_lrb * lrbp)2262 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp) 2263 { 2264 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2265 unsigned long flags; 2266 2267 spin_lock_irqsave(hba->host->host_lock, flags); 2268 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) { 2269 const struct request *req = scsi_cmd_to_rq(lrbp->cmd); 2270 struct ufs_hba_monitor *m = &hba->monitor; 2271 ktime_t now, inc, lat; 2272 2273 now = lrbp->compl_time_stamp; 2274 inc = ktime_sub(now, m->busy_start_ts[dir]); 2275 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc); 2276 m->nr_sec_rw[dir] += blk_rq_sectors(req); 2277 2278 /* Update latencies */ 2279 m->nr_req[dir]++; 2280 lat = ktime_sub(now, lrbp->issue_time_stamp); 2281 m->lat_sum[dir] += lat; 2282 if (m->lat_max[dir] < lat || !m->lat_max[dir]) 2283 m->lat_max[dir] = lat; 2284 if (m->lat_min[dir] > lat || !m->lat_min[dir]) 2285 m->lat_min[dir] = lat; 2286 2287 m->nr_queued[dir]--; 2288 /* Push forward the busy start of monitor */ 2289 m->busy_start_ts[dir] = now; 2290 } 2291 spin_unlock_irqrestore(hba->host->host_lock, flags); 2292 } 2293 2294 /** 2295 * ufshcd_send_command - Send SCSI or device management commands 2296 * @hba: per adapter instance 2297 * @task_tag: Task tag of the command 2298 * @hwq: pointer to hardware queue instance 2299 */ 2300 static inline ufshcd_send_command(struct ufs_hba * hba,unsigned int task_tag,struct ufs_hw_queue * hwq)2301 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag, 2302 struct ufs_hw_queue *hwq) 2303 { 2304 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag]; 2305 unsigned long flags; 2306 2307 lrbp->issue_time_stamp = ktime_get(); 2308 lrbp->issue_time_stamp_local_clock = local_clock(); 2309 lrbp->compl_time_stamp = ktime_set(0, 0); 2310 lrbp->compl_time_stamp_local_clock = 0; 2311 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND); 2312 if (lrbp->cmd) 2313 ufshcd_clk_scaling_start_busy(hba); 2314 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 2315 ufshcd_start_monitor(hba, lrbp); 2316 2317 if (hba->mcq_enabled) { 2318 int utrd_size = sizeof(struct utp_transfer_req_desc); 2319 struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr; 2320 struct utp_transfer_req_desc *dest; 2321 2322 spin_lock(&hwq->sq_lock); 2323 dest = hwq->sqe_base_addr + hwq->sq_tail_slot; 2324 memcpy(dest, src, utrd_size); 2325 ufshcd_inc_sq_tail(hwq); 2326 spin_unlock(&hwq->sq_lock); 2327 } else { 2328 spin_lock_irqsave(&hba->outstanding_lock, flags); 2329 if (hba->vops && hba->vops->setup_xfer_req) 2330 hba->vops->setup_xfer_req(hba, lrbp->task_tag, 2331 !!lrbp->cmd); 2332 __set_bit(lrbp->task_tag, &hba->outstanding_reqs); 2333 ufshcd_writel(hba, 1 << lrbp->task_tag, 2334 REG_UTP_TRANSFER_REQ_DOOR_BELL); 2335 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 2336 } 2337 } 2338 2339 /** 2340 * ufshcd_copy_sense_data - Copy sense data in case of check condition 2341 * @lrbp: pointer to local reference block 2342 */ ufshcd_copy_sense_data(struct ufshcd_lrb * lrbp)2343 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp) 2344 { 2345 u8 *const sense_buffer = lrbp->cmd->sense_buffer; 2346 u16 resp_len; 2347 int len; 2348 2349 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length); 2350 if (sense_buffer && resp_len) { 2351 int len_to_copy; 2352 2353 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); 2354 len_to_copy = min_t(int, UFS_SENSE_SIZE, len); 2355 2356 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data, 2357 len_to_copy); 2358 } 2359 } 2360 2361 /** 2362 * ufshcd_copy_query_response() - Copy the Query Response and the data 2363 * descriptor 2364 * @hba: per adapter instance 2365 * @lrbp: pointer to local reference block 2366 * 2367 * Return: 0 upon success; < 0 upon failure. 2368 */ 2369 static ufshcd_copy_query_response(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2370 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2371 { 2372 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 2373 2374 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 2375 2376 /* Get the descriptor */ 2377 if (hba->dev_cmd.query.descriptor && 2378 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 2379 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + 2380 GENERAL_UPIU_REQUEST_SIZE; 2381 u16 resp_len; 2382 u16 buf_len; 2383 2384 /* data segment length */ 2385 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 2386 .data_segment_length); 2387 buf_len = be16_to_cpu( 2388 hba->dev_cmd.query.request.upiu_req.length); 2389 if (likely(buf_len >= resp_len)) { 2390 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 2391 } else { 2392 dev_warn(hba->dev, 2393 "%s: rsp size %d is bigger than buffer size %d", 2394 __func__, resp_len, buf_len); 2395 return -EINVAL; 2396 } 2397 } 2398 2399 return 0; 2400 } 2401 2402 /** 2403 * ufshcd_hba_capabilities - Read controller capabilities 2404 * @hba: per adapter instance 2405 * 2406 * Return: 0 on success, negative on error. 2407 */ ufshcd_hba_capabilities(struct ufs_hba * hba)2408 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) 2409 { 2410 int err; 2411 2412 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 2413 2414 /* nutrs and nutmrs are 0 based values */ 2415 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS_SDB) + 1; 2416 hba->nutmrs = 2417 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1; 2418 hba->reserved_slot = hba->nutrs - 1; 2419 2420 hba->nortt = FIELD_GET(MASK_NUMBER_OUTSTANDING_RTT, hba->capabilities) + 1; 2421 2422 /* Read crypto capabilities */ 2423 err = ufshcd_hba_init_crypto_capabilities(hba); 2424 if (err) { 2425 dev_err(hba->dev, "crypto setup failed\n"); 2426 return err; 2427 } 2428 2429 /* 2430 * The UFSHCI 3.0 specification does not define MCQ_SUPPORT and 2431 * LSDB_SUPPORT, but [31:29] as reserved bits with reset value 0s, which 2432 * means we can simply read values regardless of version. 2433 */ 2434 hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities); 2435 /* 2436 * 0h: legacy single doorbell support is available 2437 * 1h: indicate that legacy single doorbell support has been removed 2438 */ 2439 if (!(hba->quirks & UFSHCD_QUIRK_BROKEN_LSDBS_CAP)) 2440 hba->lsdb_sup = !FIELD_GET(MASK_LSDB_SUPPORT, hba->capabilities); 2441 else 2442 hba->lsdb_sup = true; 2443 2444 hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP); 2445 2446 return 0; 2447 } 2448 2449 /** 2450 * ufshcd_ready_for_uic_cmd - Check if controller is ready 2451 * to accept UIC commands 2452 * @hba: per adapter instance 2453 * 2454 * Return: true on success, else false. 2455 */ ufshcd_ready_for_uic_cmd(struct ufs_hba * hba)2456 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 2457 { 2458 u32 val; 2459 int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY, 2460 500, uic_cmd_timeout * 1000, false, hba, 2461 REG_CONTROLLER_STATUS); 2462 return ret == 0; 2463 } 2464 2465 /** 2466 * ufshcd_get_upmcrs - Get the power mode change request status 2467 * @hba: Pointer to adapter instance 2468 * 2469 * This function gets the UPMCRS field of HCS register 2470 * 2471 * Return: value of UPMCRS field. 2472 */ ufshcd_get_upmcrs(struct ufs_hba * hba)2473 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 2474 { 2475 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 2476 } 2477 2478 /** 2479 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer 2480 * @hba: per adapter instance 2481 * @uic_cmd: UIC command 2482 */ 2483 static inline void ufshcd_dispatch_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd)2484 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2485 { 2486 lockdep_assert_held(&hba->uic_cmd_mutex); 2487 2488 WARN_ON(hba->active_uic_cmd); 2489 2490 hba->active_uic_cmd = uic_cmd; 2491 2492 /* Write Args */ 2493 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 2494 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 2495 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 2496 2497 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND); 2498 2499 /* Write UIC Cmd */ 2500 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 2501 REG_UIC_COMMAND); 2502 } 2503 2504 /** 2505 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command 2506 * @hba: per adapter instance 2507 * @uic_cmd: UIC command 2508 * 2509 * Return: 0 only if success. 2510 */ 2511 static int ufshcd_wait_for_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd)2512 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2513 { 2514 int ret; 2515 unsigned long flags; 2516 2517 lockdep_assert_held(&hba->uic_cmd_mutex); 2518 2519 if (wait_for_completion_timeout(&uic_cmd->done, 2520 msecs_to_jiffies(uic_cmd_timeout))) { 2521 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2522 } else { 2523 ret = -ETIMEDOUT; 2524 dev_err(hba->dev, 2525 "uic cmd 0x%x with arg3 0x%x completion timeout\n", 2526 uic_cmd->command, uic_cmd->argument3); 2527 2528 if (!uic_cmd->cmd_active) { 2529 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n", 2530 __func__); 2531 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2532 } 2533 } 2534 2535 spin_lock_irqsave(hba->host->host_lock, flags); 2536 hba->active_uic_cmd = NULL; 2537 spin_unlock_irqrestore(hba->host->host_lock, flags); 2538 2539 return ret; 2540 } 2541 2542 /** 2543 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2544 * @hba: per adapter instance 2545 * @uic_cmd: UIC command 2546 * 2547 * Return: 0 only if success. 2548 */ 2549 static int __ufshcd_send_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd)2550 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2551 { 2552 lockdep_assert_held(&hba->uic_cmd_mutex); 2553 2554 if (!ufshcd_ready_for_uic_cmd(hba)) { 2555 dev_err(hba->dev, 2556 "Controller not ready to accept UIC commands\n"); 2557 return -EIO; 2558 } 2559 2560 init_completion(&uic_cmd->done); 2561 2562 uic_cmd->cmd_active = 1; 2563 ufshcd_dispatch_uic_cmd(hba, uic_cmd); 2564 2565 return 0; 2566 } 2567 2568 /** 2569 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2570 * @hba: per adapter instance 2571 * @uic_cmd: UIC command 2572 * 2573 * Return: 0 only if success. 2574 */ ufshcd_send_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd)2575 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2576 { 2577 int ret; 2578 2579 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD) 2580 return 0; 2581 2582 ufshcd_hold(hba); 2583 mutex_lock(&hba->uic_cmd_mutex); 2584 ufshcd_add_delay_before_dme_cmd(hba); 2585 2586 ret = __ufshcd_send_uic_cmd(hba, uic_cmd); 2587 if (!ret) 2588 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); 2589 2590 mutex_unlock(&hba->uic_cmd_mutex); 2591 2592 ufshcd_release(hba); 2593 return ret; 2594 } 2595 2596 /** 2597 * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format) 2598 * @hba: per-adapter instance 2599 * @lrbp: pointer to local reference block 2600 * @sg_entries: The number of sg lists actually used 2601 * @sg_list: Pointer to SG list 2602 */ ufshcd_sgl_to_prdt(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,int sg_entries,struct scatterlist * sg_list)2603 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries, 2604 struct scatterlist *sg_list) 2605 { 2606 struct ufshcd_sg_entry *prd; 2607 struct scatterlist *sg; 2608 int i; 2609 2610 if (sg_entries) { 2611 2612 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 2613 lrbp->utr_descriptor_ptr->prd_table_length = 2614 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba)); 2615 else 2616 lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries); 2617 2618 prd = lrbp->ucd_prdt_ptr; 2619 2620 for_each_sg(sg_list, sg, sg_entries, i) { 2621 const unsigned int len = sg_dma_len(sg); 2622 2623 /* 2624 * From the UFSHCI spec: "Data Byte Count (DBC): A '0' 2625 * based value that indicates the length, in bytes, of 2626 * the data block. A maximum of length of 256KB may 2627 * exist for any entry. Bits 1:0 of this field shall be 2628 * 11b to indicate Dword granularity. A value of '3' 2629 * indicates 4 bytes, '7' indicates 8 bytes, etc." 2630 */ 2631 WARN_ONCE(len > SZ_256K, "len = %#x\n", len); 2632 prd->size = cpu_to_le32(len - 1); 2633 prd->addr = cpu_to_le64(sg->dma_address); 2634 prd->reserved = 0; 2635 prd = (void *)prd + ufshcd_sg_entry_size(hba); 2636 } 2637 } else { 2638 lrbp->utr_descriptor_ptr->prd_table_length = 0; 2639 } 2640 } 2641 2642 /** 2643 * ufshcd_map_sg - Map scatter-gather list to prdt 2644 * @hba: per adapter instance 2645 * @lrbp: pointer to local reference block 2646 * 2647 * Return: 0 in case of success, non-zero value in case of failure. 2648 */ ufshcd_map_sg(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2649 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2650 { 2651 struct scsi_cmnd *cmd = lrbp->cmd; 2652 int sg_segments = scsi_dma_map(cmd); 2653 2654 if (sg_segments < 0) 2655 return sg_segments; 2656 2657 ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd)); 2658 2659 return ufshcd_crypto_fill_prdt(hba, lrbp); 2660 } 2661 2662 /** 2663 * ufshcd_enable_intr - enable interrupts 2664 * @hba: per adapter instance 2665 * @intrs: interrupt bits 2666 */ ufshcd_enable_intr(struct ufs_hba * hba,u32 intrs)2667 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 2668 { 2669 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2670 2671 set |= intrs; 2672 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2673 } 2674 2675 /** 2676 * ufshcd_disable_intr - disable interrupts 2677 * @hba: per adapter instance 2678 * @intrs: interrupt bits 2679 */ ufshcd_disable_intr(struct ufs_hba * hba,u32 intrs)2680 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) 2681 { 2682 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2683 2684 set &= ~intrs; 2685 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2686 } 2687 2688 /** 2689 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request 2690 * descriptor according to request 2691 * @hba: per adapter instance 2692 * @lrbp: pointer to local reference block 2693 * @upiu_flags: flags required in the header 2694 * @cmd_dir: requests data direction 2695 * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments) 2696 */ 2697 static void ufshcd_prepare_req_desc_hdr(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,u8 * upiu_flags,enum dma_data_direction cmd_dir,int ehs_length)2698 ufshcd_prepare_req_desc_hdr(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 2699 u8 *upiu_flags, enum dma_data_direction cmd_dir, 2700 int ehs_length) 2701 { 2702 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; 2703 struct request_desc_header *h = &req_desc->header; 2704 enum utp_data_direction data_direction; 2705 2706 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2707 2708 *h = (typeof(*h)){ }; 2709 2710 if (cmd_dir == DMA_FROM_DEVICE) { 2711 data_direction = UTP_DEVICE_TO_HOST; 2712 *upiu_flags = UPIU_CMD_FLAGS_READ; 2713 } else if (cmd_dir == DMA_TO_DEVICE) { 2714 data_direction = UTP_HOST_TO_DEVICE; 2715 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 2716 } else { 2717 data_direction = UTP_NO_DATA_TRANSFER; 2718 *upiu_flags = UPIU_CMD_FLAGS_NONE; 2719 } 2720 2721 h->command_type = lrbp->command_type; 2722 h->data_direction = data_direction; 2723 h->ehs_length = ehs_length; 2724 2725 if (lrbp->intr_cmd) 2726 h->interrupt = 1; 2727 2728 /* Prepare crypto related dwords */ 2729 ufshcd_prepare_req_desc_hdr_crypto(lrbp, h); 2730 2731 /* 2732 * assigning invalid value for command status. Controller 2733 * updates OCS on command completion, with the command 2734 * status 2735 */ 2736 h->ocs = OCS_INVALID_COMMAND_STATUS; 2737 2738 req_desc->prd_table_length = 0; 2739 } 2740 2741 /** 2742 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc, 2743 * for scsi commands 2744 * @lrbp: local reference block pointer 2745 * @upiu_flags: flags 2746 */ 2747 static ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb * lrbp,u8 upiu_flags)2748 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags) 2749 { 2750 struct scsi_cmnd *cmd = lrbp->cmd; 2751 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2752 unsigned short cdb_len; 2753 2754 ucd_req_ptr->header = (struct utp_upiu_header){ 2755 .transaction_code = UPIU_TRANSACTION_COMMAND, 2756 .flags = upiu_flags, 2757 .lun = lrbp->lun, 2758 .task_tag = lrbp->task_tag, 2759 .command_set_type = UPIU_COMMAND_SET_TYPE_SCSI, 2760 }; 2761 2762 WARN_ON_ONCE(ucd_req_ptr->header.task_tag != lrbp->task_tag); 2763 2764 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length); 2765 2766 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE); 2767 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len); 2768 2769 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2770 } 2771 2772 /** 2773 * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request 2774 * @hba: UFS hba 2775 * @lrbp: local reference block pointer 2776 * @upiu_flags: flags 2777 */ ufshcd_prepare_utp_query_req_upiu(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,u8 upiu_flags)2778 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 2779 struct ufshcd_lrb *lrbp, u8 upiu_flags) 2780 { 2781 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2782 struct ufs_query *query = &hba->dev_cmd.query; 2783 u16 len = be16_to_cpu(query->request.upiu_req.length); 2784 2785 /* Query request header */ 2786 ucd_req_ptr->header = (struct utp_upiu_header){ 2787 .transaction_code = UPIU_TRANSACTION_QUERY_REQ, 2788 .flags = upiu_flags, 2789 .lun = lrbp->lun, 2790 .task_tag = lrbp->task_tag, 2791 .query_function = query->request.query_func, 2792 /* Data segment length only need for WRITE_DESC */ 2793 .data_segment_length = 2794 query->request.upiu_req.opcode == 2795 UPIU_QUERY_OPCODE_WRITE_DESC ? 2796 cpu_to_be16(len) : 2797 0, 2798 }; 2799 2800 /* Copy the Query Request buffer as is */ 2801 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, 2802 QUERY_OSF_SIZE); 2803 2804 /* Copy the Descriptor */ 2805 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 2806 memcpy(ucd_req_ptr + 1, query->descriptor, len); 2807 2808 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2809 } 2810 ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb * lrbp)2811 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) 2812 { 2813 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2814 2815 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 2816 2817 ucd_req_ptr->header = (struct utp_upiu_header){ 2818 .transaction_code = UPIU_TRANSACTION_NOP_OUT, 2819 .task_tag = lrbp->task_tag, 2820 }; 2821 2822 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2823 } 2824 2825 /** 2826 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU) 2827 * for Device Management Purposes 2828 * @hba: per adapter instance 2829 * @lrbp: pointer to local reference block 2830 * 2831 * Return: 0 upon success; < 0 upon failure. 2832 */ ufshcd_compose_devman_upiu(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2833 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba, 2834 struct ufshcd_lrb *lrbp) 2835 { 2836 u8 upiu_flags; 2837 int ret = 0; 2838 2839 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0); 2840 2841 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) 2842 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags); 2843 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) 2844 ufshcd_prepare_utp_nop_upiu(lrbp); 2845 else 2846 ret = -EINVAL; 2847 2848 return ret; 2849 } 2850 2851 /** 2852 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU) 2853 * for SCSI Purposes 2854 * @hba: per adapter instance 2855 * @lrbp: pointer to local reference block 2856 */ ufshcd_comp_scsi_upiu(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2857 static void ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2858 { 2859 struct request *rq = scsi_cmd_to_rq(lrbp->cmd); 2860 unsigned int ioprio_class = IOPRIO_PRIO_CLASS(req_get_ioprio(rq)); 2861 u8 upiu_flags; 2862 2863 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, lrbp->cmd->sc_data_direction, 0); 2864 if (ioprio_class == IOPRIO_CLASS_RT) 2865 upiu_flags |= UPIU_CMD_FLAGS_CP; 2866 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); 2867 } 2868 __ufshcd_setup_cmd(struct ufshcd_lrb * lrbp,struct scsi_cmnd * cmd,u8 lun,int tag)2869 static void __ufshcd_setup_cmd(struct ufshcd_lrb *lrbp, struct scsi_cmnd *cmd, u8 lun, int tag) 2870 { 2871 memset(lrbp->ucd_req_ptr, 0, sizeof(*lrbp->ucd_req_ptr)); 2872 2873 lrbp->cmd = cmd; 2874 lrbp->task_tag = tag; 2875 lrbp->lun = lun; 2876 ufshcd_prepare_lrbp_crypto(cmd ? scsi_cmd_to_rq(cmd) : NULL, lrbp); 2877 } 2878 ufshcd_setup_scsi_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,struct scsi_cmnd * cmd,u8 lun,int tag)2879 static void ufshcd_setup_scsi_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 2880 struct scsi_cmnd *cmd, u8 lun, int tag) 2881 { 2882 __ufshcd_setup_cmd(lrbp, cmd, lun, tag); 2883 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba); 2884 lrbp->req_abort_skip = false; 2885 2886 ufshcd_comp_scsi_upiu(hba, lrbp); 2887 } 2888 2889 /** 2890 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID 2891 * @upiu_wlun_id: UPIU W-LUN id 2892 * 2893 * Return: SCSI W-LUN id. 2894 */ ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)2895 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id) 2896 { 2897 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE; 2898 } 2899 is_device_wlun(struct scsi_device * sdev)2900 static inline bool is_device_wlun(struct scsi_device *sdev) 2901 { 2902 return sdev->lun == 2903 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN); 2904 } 2905 2906 /* 2907 * Associate the UFS controller queue with the default and poll HCTX types. 2908 * Initialize the mq_map[] arrays. 2909 */ ufshcd_map_queues(struct Scsi_Host * shost)2910 static void ufshcd_map_queues(struct Scsi_Host *shost) 2911 { 2912 struct ufs_hba *hba = shost_priv(shost); 2913 int i, queue_offset = 0; 2914 2915 if (!is_mcq_supported(hba)) { 2916 hba->nr_queues[HCTX_TYPE_DEFAULT] = 1; 2917 hba->nr_queues[HCTX_TYPE_READ] = 0; 2918 hba->nr_queues[HCTX_TYPE_POLL] = 1; 2919 hba->nr_hw_queues = 1; 2920 } 2921 2922 for (i = 0; i < shost->nr_maps; i++) { 2923 struct blk_mq_queue_map *map = &shost->tag_set.map[i]; 2924 2925 map->nr_queues = hba->nr_queues[i]; 2926 if (!map->nr_queues) 2927 continue; 2928 map->queue_offset = queue_offset; 2929 if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba)) 2930 map->queue_offset = 0; 2931 2932 blk_mq_map_queues(map); 2933 queue_offset += map->nr_queues; 2934 } 2935 } 2936 ufshcd_init_lrb(struct ufs_hba * hba,struct ufshcd_lrb * lrb,int i)2937 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i) 2938 { 2939 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr + 2940 i * ufshcd_get_ucd_size(hba); 2941 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr; 2942 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr + 2943 i * ufshcd_get_ucd_size(hba); 2944 u16 response_offset = le16_to_cpu(utrdlp[i].response_upiu_offset); 2945 u16 prdt_offset = le16_to_cpu(utrdlp[i].prd_table_offset); 2946 2947 lrb->utr_descriptor_ptr = utrdlp + i; 2948 lrb->utrd_dma_addr = hba->utrdl_dma_addr + 2949 i * sizeof(struct utp_transfer_req_desc); 2950 lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu; 2951 lrb->ucd_req_dma_addr = cmd_desc_element_addr; 2952 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu; 2953 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset; 2954 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table; 2955 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset; 2956 } 2957 2958 /** 2959 * ufshcd_queuecommand - main entry point for SCSI requests 2960 * @host: SCSI host pointer 2961 * @cmd: command from SCSI Midlayer 2962 * 2963 * Return: 0 for success, non-zero in case of failure. 2964 */ ufshcd_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)2965 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 2966 { 2967 struct ufs_hba *hba = shost_priv(host); 2968 int tag = scsi_cmd_to_rq(cmd)->tag; 2969 struct ufshcd_lrb *lrbp; 2970 int err = 0; 2971 struct ufs_hw_queue *hwq = NULL; 2972 2973 switch (hba->ufshcd_state) { 2974 case UFSHCD_STATE_OPERATIONAL: 2975 break; 2976 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: 2977 /* 2978 * SCSI error handler can call ->queuecommand() while UFS error 2979 * handler is in progress. Error interrupts could change the 2980 * state from UFSHCD_STATE_RESET to 2981 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests 2982 * being issued in that case. 2983 */ 2984 if (ufshcd_eh_in_progress(hba)) { 2985 err = SCSI_MLQUEUE_HOST_BUSY; 2986 goto out; 2987 } 2988 break; 2989 case UFSHCD_STATE_EH_SCHEDULED_FATAL: 2990 /* 2991 * pm_runtime_get_sync() is used at error handling preparation 2992 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's 2993 * PM ops, it can never be finished if we let SCSI layer keep 2994 * retrying it, which gets err handler stuck forever. Neither 2995 * can we let the scsi cmd pass through, because UFS is in bad 2996 * state, the scsi cmd may eventually time out, which will get 2997 * err handler blocked for too long. So, just fail the scsi cmd 2998 * sent from PM ops, err handler can recover PM error anyways. 2999 */ 3000 if (hba->pm_op_in_progress) { 3001 hba->force_reset = true; 3002 set_host_byte(cmd, DID_BAD_TARGET); 3003 scsi_done(cmd); 3004 goto out; 3005 } 3006 fallthrough; 3007 case UFSHCD_STATE_RESET: 3008 err = SCSI_MLQUEUE_HOST_BUSY; 3009 goto out; 3010 case UFSHCD_STATE_ERROR: 3011 set_host_byte(cmd, DID_ERROR); 3012 scsi_done(cmd); 3013 goto out; 3014 } 3015 3016 hba->req_abort_count = 0; 3017 3018 ufshcd_hold(hba); 3019 3020 lrbp = &hba->lrb[tag]; 3021 3022 ufshcd_setup_scsi_cmd(hba, lrbp, cmd, ufshcd_scsi_to_upiu_lun(cmd->device->lun), tag); 3023 3024 err = ufshcd_map_sg(hba, lrbp); 3025 if (err) { 3026 ufshcd_release(hba); 3027 goto out; 3028 } 3029 3030 if (hba->mcq_enabled) 3031 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 3032 3033 ufshcd_send_command(hba, tag, hwq); 3034 3035 out: 3036 if (ufs_trigger_eh(hba)) { 3037 unsigned long flags; 3038 3039 spin_lock_irqsave(hba->host->host_lock, flags); 3040 ufshcd_schedule_eh_work(hba); 3041 spin_unlock_irqrestore(hba->host->host_lock, flags); 3042 } 3043 3044 return err; 3045 } 3046 ufshcd_setup_dev_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,enum dev_cmd_type cmd_type,u8 lun,int tag)3047 static void ufshcd_setup_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 3048 enum dev_cmd_type cmd_type, u8 lun, int tag) 3049 { 3050 __ufshcd_setup_cmd(lrbp, NULL, lun, tag); 3051 lrbp->intr_cmd = true; /* No interrupt aggregation */ 3052 hba->dev_cmd.type = cmd_type; 3053 } 3054 ufshcd_compose_dev_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,enum dev_cmd_type cmd_type,int tag)3055 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, 3056 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag) 3057 { 3058 ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag); 3059 3060 return ufshcd_compose_devman_upiu(hba, lrbp); 3061 } 3062 3063 /* 3064 * Check with the block layer if the command is inflight 3065 * @cmd: command to check. 3066 * 3067 * Return: true if command is inflight; false if not. 3068 */ ufshcd_cmd_inflight(struct scsi_cmnd * cmd)3069 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd) 3070 { 3071 return cmd && blk_mq_rq_state(scsi_cmd_to_rq(cmd)) == MQ_RQ_IN_FLIGHT; 3072 } 3073 3074 /* 3075 * Clear the pending command in the controller and wait until 3076 * the controller confirms that the command has been cleared. 3077 * @hba: per adapter instance 3078 * @task_tag: The tag number of the command to be cleared. 3079 */ ufshcd_clear_cmd(struct ufs_hba * hba,u32 task_tag)3080 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag) 3081 { 3082 u32 mask; 3083 int err; 3084 3085 if (hba->mcq_enabled) { 3086 /* 3087 * MCQ mode. Clean up the MCQ resources similar to 3088 * what the ufshcd_utrl_clear() does for SDB mode. 3089 */ 3090 err = ufshcd_mcq_sq_cleanup(hba, task_tag); 3091 if (err) { 3092 dev_err(hba->dev, "%s: failed tag=%d. err=%d\n", 3093 __func__, task_tag, err); 3094 return err; 3095 } 3096 return 0; 3097 } 3098 3099 mask = 1U << task_tag; 3100 3101 /* clear outstanding transaction before retry */ 3102 ufshcd_utrl_clear(hba, mask); 3103 3104 /* 3105 * wait for h/w to clear corresponding bit in door-bell. 3106 * max. wait is 1 sec. 3107 */ 3108 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL, 3109 mask, ~mask, 1000, 1000); 3110 } 3111 3112 /** 3113 * ufshcd_dev_cmd_completion() - handles device management command responses 3114 * @hba: per adapter instance 3115 * @lrbp: pointer to local reference block 3116 * 3117 * Return: 0 upon success; < 0 upon failure. 3118 */ 3119 static int ufshcd_dev_cmd_completion(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)3120 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 3121 { 3122 enum upiu_response_transaction resp; 3123 int err = 0; 3124 3125 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 3126 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); 3127 3128 switch (resp) { 3129 case UPIU_TRANSACTION_NOP_IN: 3130 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) { 3131 err = -EINVAL; 3132 dev_err(hba->dev, "%s: unexpected response %x\n", 3133 __func__, resp); 3134 } 3135 break; 3136 case UPIU_TRANSACTION_QUERY_RSP: { 3137 u8 response = lrbp->ucd_rsp_ptr->header.response; 3138 3139 if (response == 0) { 3140 err = ufshcd_copy_query_response(hba, lrbp); 3141 } else { 3142 err = -EINVAL; 3143 dev_err(hba->dev, "%s: unexpected response in Query RSP: %x\n", 3144 __func__, response); 3145 } 3146 break; 3147 } 3148 case UPIU_TRANSACTION_REJECT_UPIU: 3149 /* TODO: handle Reject UPIU Response */ 3150 err = -EPERM; 3151 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 3152 __func__); 3153 break; 3154 case UPIU_TRANSACTION_RESPONSE: 3155 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) { 3156 err = -EINVAL; 3157 dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp); 3158 } 3159 break; 3160 default: 3161 err = -EINVAL; 3162 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 3163 __func__, resp); 3164 break; 3165 } 3166 3167 return err; 3168 } 3169 ufshcd_wait_for_dev_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,int max_timeout)3170 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, 3171 struct ufshcd_lrb *lrbp, int max_timeout) 3172 { 3173 unsigned long time_left = msecs_to_jiffies(max_timeout); 3174 unsigned long flags; 3175 bool pending; 3176 int err; 3177 3178 retry: 3179 time_left = wait_for_completion_timeout(hba->dev_cmd.complete, 3180 time_left); 3181 3182 if (likely(time_left)) { 3183 /* 3184 * The completion handler called complete() and the caller of 3185 * this function still owns the @lrbp tag so the code below does 3186 * not trigger any race conditions. 3187 */ 3188 hba->dev_cmd.complete = NULL; 3189 err = ufshcd_get_tr_ocs(lrbp, NULL); 3190 if (!err) 3191 err = ufshcd_dev_cmd_completion(hba, lrbp); 3192 } else { 3193 err = -ETIMEDOUT; 3194 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n", 3195 __func__, lrbp->task_tag); 3196 3197 /* MCQ mode */ 3198 if (hba->mcq_enabled) { 3199 /* successfully cleared the command, retry if needed */ 3200 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) 3201 err = -EAGAIN; 3202 hba->dev_cmd.complete = NULL; 3203 return err; 3204 } 3205 3206 /* SDB mode */ 3207 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) { 3208 /* successfully cleared the command, retry if needed */ 3209 err = -EAGAIN; 3210 /* 3211 * Since clearing the command succeeded we also need to 3212 * clear the task tag bit from the outstanding_reqs 3213 * variable. 3214 */ 3215 spin_lock_irqsave(&hba->outstanding_lock, flags); 3216 pending = test_bit(lrbp->task_tag, 3217 &hba->outstanding_reqs); 3218 if (pending) { 3219 hba->dev_cmd.complete = NULL; 3220 __clear_bit(lrbp->task_tag, 3221 &hba->outstanding_reqs); 3222 } 3223 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3224 3225 if (!pending) { 3226 /* 3227 * The completion handler ran while we tried to 3228 * clear the command. 3229 */ 3230 time_left = 1; 3231 goto retry; 3232 } 3233 } else { 3234 dev_err(hba->dev, "%s: failed to clear tag %d\n", 3235 __func__, lrbp->task_tag); 3236 3237 spin_lock_irqsave(&hba->outstanding_lock, flags); 3238 pending = test_bit(lrbp->task_tag, 3239 &hba->outstanding_reqs); 3240 if (pending) 3241 hba->dev_cmd.complete = NULL; 3242 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3243 3244 if (!pending) { 3245 /* 3246 * The completion handler ran while we tried to 3247 * clear the command. 3248 */ 3249 time_left = 1; 3250 goto retry; 3251 } 3252 } 3253 } 3254 3255 return err; 3256 } 3257 ufshcd_dev_man_lock(struct ufs_hba * hba)3258 static void ufshcd_dev_man_lock(struct ufs_hba *hba) 3259 { 3260 ufshcd_hold(hba); 3261 mutex_lock(&hba->dev_cmd.lock); 3262 down_read(&hba->clk_scaling_lock); 3263 } 3264 ufshcd_dev_man_unlock(struct ufs_hba * hba)3265 static void ufshcd_dev_man_unlock(struct ufs_hba *hba) 3266 { 3267 up_read(&hba->clk_scaling_lock); 3268 mutex_unlock(&hba->dev_cmd.lock); 3269 ufshcd_release(hba); 3270 } 3271 ufshcd_issue_dev_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,const u32 tag,int timeout)3272 static int ufshcd_issue_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 3273 const u32 tag, int timeout) 3274 { 3275 DECLARE_COMPLETION_ONSTACK(wait); 3276 int err; 3277 3278 hba->dev_cmd.complete = &wait; 3279 3280 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 3281 3282 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 3283 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); 3284 3285 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 3286 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 3287 3288 return err; 3289 } 3290 3291 /** 3292 * ufshcd_exec_dev_cmd - API for sending device management requests 3293 * @hba: UFS hba 3294 * @cmd_type: specifies the type (NOP, Query...) 3295 * @timeout: timeout in milliseconds 3296 * 3297 * Return: 0 upon success; < 0 upon failure. 3298 * 3299 * NOTE: Since there is only one available tag for device management commands, 3300 * it is expected you hold the hba->dev_cmd.lock mutex. 3301 */ ufshcd_exec_dev_cmd(struct ufs_hba * hba,enum dev_cmd_type cmd_type,int timeout)3302 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, 3303 enum dev_cmd_type cmd_type, int timeout) 3304 { 3305 const u32 tag = hba->reserved_slot; 3306 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 3307 int err; 3308 3309 /* Protects use of hba->reserved_slot. */ 3310 lockdep_assert_held(&hba->dev_cmd.lock); 3311 3312 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag); 3313 if (unlikely(err)) 3314 return err; 3315 3316 return ufshcd_issue_dev_cmd(hba, lrbp, tag, timeout); 3317 } 3318 3319 /** 3320 * ufshcd_init_query() - init the query response and request parameters 3321 * @hba: per-adapter instance 3322 * @request: address of the request pointer to be initialized 3323 * @response: address of the response pointer to be initialized 3324 * @opcode: operation to perform 3325 * @idn: flag idn to access 3326 * @index: LU number to access 3327 * @selector: query/flag/descriptor further identification 3328 */ ufshcd_init_query(struct ufs_hba * hba,struct ufs_query_req ** request,struct ufs_query_res ** response,enum query_opcode opcode,u8 idn,u8 index,u8 selector)3329 static inline void ufshcd_init_query(struct ufs_hba *hba, 3330 struct ufs_query_req **request, struct ufs_query_res **response, 3331 enum query_opcode opcode, u8 idn, u8 index, u8 selector) 3332 { 3333 *request = &hba->dev_cmd.query.request; 3334 *response = &hba->dev_cmd.query.response; 3335 memset(*request, 0, sizeof(struct ufs_query_req)); 3336 memset(*response, 0, sizeof(struct ufs_query_res)); 3337 (*request)->upiu_req.opcode = opcode; 3338 (*request)->upiu_req.idn = idn; 3339 (*request)->upiu_req.index = index; 3340 (*request)->upiu_req.selector = selector; 3341 } 3342 ufshcd_query_flag_retry(struct ufs_hba * hba,enum query_opcode opcode,enum flag_idn idn,u8 index,bool * flag_res)3343 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 3344 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res) 3345 { 3346 int ret; 3347 int retries; 3348 3349 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 3350 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res); 3351 if (ret) 3352 dev_dbg(hba->dev, 3353 "%s: failed with error %d, retries %d\n", 3354 __func__, ret, retries); 3355 else 3356 break; 3357 } 3358 3359 if (ret) 3360 dev_err(hba->dev, 3361 "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n", 3362 __func__, opcode, idn, ret, retries); 3363 return ret; 3364 } 3365 3366 /** 3367 * ufshcd_query_flag() - API function for sending flag query requests 3368 * @hba: per-adapter instance 3369 * @opcode: flag query to perform 3370 * @idn: flag idn to access 3371 * @index: flag index to access 3372 * @flag_res: the flag value after the query request completes 3373 * 3374 * Return: 0 for success, non-zero in case of failure. 3375 */ ufshcd_query_flag(struct ufs_hba * hba,enum query_opcode opcode,enum flag_idn idn,u8 index,bool * flag_res)3376 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 3377 enum flag_idn idn, u8 index, bool *flag_res) 3378 { 3379 struct ufs_query_req *request = NULL; 3380 struct ufs_query_res *response = NULL; 3381 int err, selector = 0; 3382 int timeout = QUERY_REQ_TIMEOUT; 3383 3384 BUG_ON(!hba); 3385 3386 ufshcd_dev_man_lock(hba); 3387 3388 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3389 selector); 3390 3391 switch (opcode) { 3392 case UPIU_QUERY_OPCODE_SET_FLAG: 3393 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 3394 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 3395 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3396 break; 3397 case UPIU_QUERY_OPCODE_READ_FLAG: 3398 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3399 if (!flag_res) { 3400 /* No dummy reads */ 3401 dev_err(hba->dev, "%s: Invalid argument for read request\n", 3402 __func__); 3403 err = -EINVAL; 3404 goto out_unlock; 3405 } 3406 break; 3407 default: 3408 dev_err(hba->dev, 3409 "%s: Expected query flag opcode but got = %d\n", 3410 __func__, opcode); 3411 err = -EINVAL; 3412 goto out_unlock; 3413 } 3414 3415 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 3416 3417 if (err) { 3418 dev_err(hba->dev, 3419 "%s: Sending flag query for idn %d failed, err = %d\n", 3420 __func__, idn, err); 3421 goto out_unlock; 3422 } 3423 3424 if (flag_res) 3425 *flag_res = (be32_to_cpu(response->upiu_res.value) & 3426 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 3427 3428 out_unlock: 3429 ufshcd_dev_man_unlock(hba); 3430 return err; 3431 } 3432 3433 /** 3434 * ufshcd_query_attr - API function for sending attribute requests 3435 * @hba: per-adapter instance 3436 * @opcode: attribute opcode 3437 * @idn: attribute idn to access 3438 * @index: index field 3439 * @selector: selector field 3440 * @attr_val: the attribute value after the query request completes 3441 * 3442 * Return: 0 for success, non-zero in case of failure. 3443 */ ufshcd_query_attr(struct ufs_hba * hba,enum query_opcode opcode,enum attr_idn idn,u8 index,u8 selector,u32 * attr_val)3444 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, 3445 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) 3446 { 3447 struct ufs_query_req *request = NULL; 3448 struct ufs_query_res *response = NULL; 3449 int err; 3450 3451 BUG_ON(!hba); 3452 3453 if (!attr_val) { 3454 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", 3455 __func__, opcode); 3456 return -EINVAL; 3457 } 3458 3459 ufshcd_dev_man_lock(hba); 3460 3461 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3462 selector); 3463 3464 switch (opcode) { 3465 case UPIU_QUERY_OPCODE_WRITE_ATTR: 3466 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3467 request->upiu_req.value = cpu_to_be32(*attr_val); 3468 break; 3469 case UPIU_QUERY_OPCODE_READ_ATTR: 3470 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3471 break; 3472 default: 3473 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n", 3474 __func__, opcode); 3475 err = -EINVAL; 3476 goto out_unlock; 3477 } 3478 3479 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3480 3481 if (err) { 3482 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3483 __func__, opcode, idn, index, err); 3484 goto out_unlock; 3485 } 3486 3487 *attr_val = be32_to_cpu(response->upiu_res.value); 3488 3489 out_unlock: 3490 ufshcd_dev_man_unlock(hba); 3491 return err; 3492 } 3493 3494 /** 3495 * ufshcd_query_attr_retry() - API function for sending query 3496 * attribute with retries 3497 * @hba: per-adapter instance 3498 * @opcode: attribute opcode 3499 * @idn: attribute idn to access 3500 * @index: index field 3501 * @selector: selector field 3502 * @attr_val: the attribute value after the query request 3503 * completes 3504 * 3505 * Return: 0 for success, non-zero in case of failure. 3506 */ ufshcd_query_attr_retry(struct ufs_hba * hba,enum query_opcode opcode,enum attr_idn idn,u8 index,u8 selector,u32 * attr_val)3507 int ufshcd_query_attr_retry(struct ufs_hba *hba, 3508 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector, 3509 u32 *attr_val) 3510 { 3511 int ret = 0; 3512 u32 retries; 3513 3514 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3515 ret = ufshcd_query_attr(hba, opcode, idn, index, 3516 selector, attr_val); 3517 if (ret) 3518 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n", 3519 __func__, ret, retries); 3520 else 3521 break; 3522 } 3523 3524 if (ret) 3525 dev_err(hba->dev, 3526 "%s: query attribute, idn %d, failed with error %d after %d retries\n", 3527 __func__, idn, ret, QUERY_REQ_RETRIES); 3528 return ret; 3529 } 3530 __ufshcd_query_descriptor(struct ufs_hba * hba,enum query_opcode opcode,enum desc_idn idn,u8 index,u8 selector,u8 * desc_buf,int * buf_len)3531 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 3532 enum query_opcode opcode, enum desc_idn idn, u8 index, 3533 u8 selector, u8 *desc_buf, int *buf_len) 3534 { 3535 struct ufs_query_req *request = NULL; 3536 struct ufs_query_res *response = NULL; 3537 int err; 3538 3539 BUG_ON(!hba); 3540 3541 if (!desc_buf) { 3542 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 3543 __func__, opcode); 3544 return -EINVAL; 3545 } 3546 3547 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 3548 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 3549 __func__, *buf_len); 3550 return -EINVAL; 3551 } 3552 3553 ufshcd_dev_man_lock(hba); 3554 3555 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3556 selector); 3557 hba->dev_cmd.query.descriptor = desc_buf; 3558 request->upiu_req.length = cpu_to_be16(*buf_len); 3559 3560 switch (opcode) { 3561 case UPIU_QUERY_OPCODE_WRITE_DESC: 3562 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3563 break; 3564 case UPIU_QUERY_OPCODE_READ_DESC: 3565 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3566 break; 3567 default: 3568 dev_err(hba->dev, 3569 "%s: Expected query descriptor opcode but got = 0x%.2x\n", 3570 __func__, opcode); 3571 err = -EINVAL; 3572 goto out_unlock; 3573 } 3574 3575 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3576 3577 if (err) { 3578 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3579 __func__, opcode, idn, index, err); 3580 goto out_unlock; 3581 } 3582 3583 *buf_len = be16_to_cpu(response->upiu_res.length); 3584 3585 out_unlock: 3586 hba->dev_cmd.query.descriptor = NULL; 3587 ufshcd_dev_man_unlock(hba); 3588 return err; 3589 } 3590 3591 /** 3592 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 3593 * @hba: per-adapter instance 3594 * @opcode: attribute opcode 3595 * @idn: attribute idn to access 3596 * @index: index field 3597 * @selector: selector field 3598 * @desc_buf: the buffer that contains the descriptor 3599 * @buf_len: length parameter passed to the device 3600 * 3601 * The buf_len parameter will contain, on return, the length parameter 3602 * received on the response. 3603 * 3604 * Return: 0 for success, non-zero in case of failure. 3605 */ ufshcd_query_descriptor_retry(struct ufs_hba * hba,enum query_opcode opcode,enum desc_idn idn,u8 index,u8 selector,u8 * desc_buf,int * buf_len)3606 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, 3607 enum query_opcode opcode, 3608 enum desc_idn idn, u8 index, 3609 u8 selector, 3610 u8 *desc_buf, int *buf_len) 3611 { 3612 int err; 3613 int retries; 3614 3615 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3616 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 3617 selector, desc_buf, buf_len); 3618 if (!err || err == -EINVAL) 3619 break; 3620 } 3621 3622 return err; 3623 } 3624 3625 /** 3626 * ufshcd_read_desc_param - read the specified descriptor parameter 3627 * @hba: Pointer to adapter instance 3628 * @desc_id: descriptor idn value 3629 * @desc_index: descriptor index 3630 * @param_offset: offset of the parameter to read 3631 * @param_read_buf: pointer to buffer where parameter would be read 3632 * @param_size: sizeof(param_read_buf) 3633 * 3634 * Return: 0 in case of success, non-zero otherwise. 3635 */ ufshcd_read_desc_param(struct ufs_hba * hba,enum desc_idn desc_id,int desc_index,u8 param_offset,u8 * param_read_buf,u8 param_size)3636 int ufshcd_read_desc_param(struct ufs_hba *hba, 3637 enum desc_idn desc_id, 3638 int desc_index, 3639 u8 param_offset, 3640 u8 *param_read_buf, 3641 u8 param_size) 3642 { 3643 int ret; 3644 u8 *desc_buf; 3645 int buff_len = QUERY_DESC_MAX_SIZE; 3646 bool is_kmalloc = true; 3647 3648 /* Safety check */ 3649 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 3650 return -EINVAL; 3651 3652 /* Check whether we need temp memory */ 3653 if (param_offset != 0 || param_size < buff_len) { 3654 desc_buf = kzalloc(buff_len, GFP_KERNEL); 3655 if (!desc_buf) 3656 return -ENOMEM; 3657 } else { 3658 desc_buf = param_read_buf; 3659 is_kmalloc = false; 3660 } 3661 3662 /* Request for full descriptor */ 3663 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 3664 desc_id, desc_index, 0, 3665 desc_buf, &buff_len); 3666 if (ret) { 3667 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 3668 __func__, desc_id, desc_index, param_offset, ret); 3669 goto out; 3670 } 3671 3672 /* Update descriptor length */ 3673 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET]; 3674 3675 if (param_offset >= buff_len) { 3676 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n", 3677 __func__, param_offset, desc_id, buff_len); 3678 ret = -EINVAL; 3679 goto out; 3680 } 3681 3682 /* Sanity check */ 3683 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 3684 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 3685 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 3686 ret = -EINVAL; 3687 goto out; 3688 } 3689 3690 if (is_kmalloc) { 3691 /* Make sure we don't copy more data than available */ 3692 if (param_offset >= buff_len) 3693 ret = -EINVAL; 3694 else 3695 memcpy(param_read_buf, &desc_buf[param_offset], 3696 min_t(u32, param_size, buff_len - param_offset)); 3697 } 3698 out: 3699 if (is_kmalloc) 3700 kfree(desc_buf); 3701 return ret; 3702 } 3703 3704 /** 3705 * struct uc_string_id - unicode string 3706 * 3707 * @len: size of this descriptor inclusive 3708 * @type: descriptor type 3709 * @uc: unicode string character 3710 */ 3711 struct uc_string_id { 3712 u8 len; 3713 u8 type; 3714 wchar_t uc[]; 3715 } __packed; 3716 3717 /* replace non-printable or non-ASCII characters with spaces */ ufshcd_remove_non_printable(u8 ch)3718 static inline char ufshcd_remove_non_printable(u8 ch) 3719 { 3720 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' '; 3721 } 3722 3723 /** 3724 * ufshcd_read_string_desc - read string descriptor 3725 * @hba: pointer to adapter instance 3726 * @desc_index: descriptor index 3727 * @buf: pointer to buffer where descriptor would be read, 3728 * the caller should free the memory. 3729 * @ascii: if true convert from unicode to ascii characters 3730 * null terminated string. 3731 * 3732 * Return: 3733 * * string size on success. 3734 * * -ENOMEM: on allocation failure 3735 * * -EINVAL: on a wrong parameter 3736 */ ufshcd_read_string_desc(struct ufs_hba * hba,u8 desc_index,u8 ** buf,bool ascii)3737 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 3738 u8 **buf, bool ascii) 3739 { 3740 struct uc_string_id *uc_str; 3741 u8 *str; 3742 int ret; 3743 3744 if (!buf) 3745 return -EINVAL; 3746 3747 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 3748 if (!uc_str) 3749 return -ENOMEM; 3750 3751 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0, 3752 (u8 *)uc_str, QUERY_DESC_MAX_SIZE); 3753 if (ret < 0) { 3754 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n", 3755 QUERY_REQ_RETRIES, ret); 3756 str = NULL; 3757 goto out; 3758 } 3759 3760 if (uc_str->len <= QUERY_DESC_HDR_SIZE) { 3761 dev_dbg(hba->dev, "String Desc is of zero length\n"); 3762 str = NULL; 3763 ret = 0; 3764 goto out; 3765 } 3766 3767 if (ascii) { 3768 ssize_t ascii_len; 3769 int i; 3770 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 3771 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1; 3772 str = kzalloc(ascii_len, GFP_KERNEL); 3773 if (!str) { 3774 ret = -ENOMEM; 3775 goto out; 3776 } 3777 3778 /* 3779 * the descriptor contains string in UTF16 format 3780 * we need to convert to utf-8 so it can be displayed 3781 */ 3782 ret = utf16s_to_utf8s(uc_str->uc, 3783 uc_str->len - QUERY_DESC_HDR_SIZE, 3784 UTF16_BIG_ENDIAN, str, ascii_len - 1); 3785 3786 /* replace non-printable or non-ASCII characters with spaces */ 3787 for (i = 0; i < ret; i++) 3788 str[i] = ufshcd_remove_non_printable(str[i]); 3789 3790 str[ret++] = '\0'; 3791 3792 } else { 3793 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL); 3794 if (!str) { 3795 ret = -ENOMEM; 3796 goto out; 3797 } 3798 ret = uc_str->len; 3799 } 3800 out: 3801 *buf = str; 3802 kfree(uc_str); 3803 return ret; 3804 } 3805 3806 /** 3807 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter 3808 * @hba: Pointer to adapter instance 3809 * @lun: lun id 3810 * @param_offset: offset of the parameter to read 3811 * @param_read_buf: pointer to buffer where parameter would be read 3812 * @param_size: sizeof(param_read_buf) 3813 * 3814 * Return: 0 in case of success, non-zero otherwise. 3815 */ ufshcd_read_unit_desc_param(struct ufs_hba * hba,int lun,enum unit_desc_param param_offset,u8 * param_read_buf,u32 param_size)3816 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba, 3817 int lun, 3818 enum unit_desc_param param_offset, 3819 u8 *param_read_buf, 3820 u32 param_size) 3821 { 3822 /* 3823 * Unit descriptors are only available for general purpose LUs (LUN id 3824 * from 0 to 7) and RPMB Well known LU. 3825 */ 3826 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun)) 3827 return -EOPNOTSUPP; 3828 3829 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun, 3830 param_offset, param_read_buf, param_size); 3831 } 3832 ufshcd_get_ref_clk_gating_wait(struct ufs_hba * hba)3833 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba) 3834 { 3835 int err = 0; 3836 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3837 3838 if (hba->dev_info.wspecversion >= 0x300) { 3839 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 3840 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0, 3841 &gating_wait); 3842 if (err) 3843 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n", 3844 err, gating_wait); 3845 3846 if (gating_wait == 0) { 3847 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3848 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n", 3849 gating_wait); 3850 } 3851 3852 hba->dev_info.clk_gating_wait_us = gating_wait; 3853 } 3854 3855 return err; 3856 } 3857 3858 /** 3859 * ufshcd_memory_alloc - allocate memory for host memory space data structures 3860 * @hba: per adapter instance 3861 * 3862 * 1. Allocate DMA memory for Command Descriptor array 3863 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT 3864 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL). 3865 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List 3866 * (UTMRDL) 3867 * 4. Allocate memory for local reference block(lrb). 3868 * 3869 * Return: 0 for success, non-zero in case of failure. 3870 */ ufshcd_memory_alloc(struct ufs_hba * hba)3871 static int ufshcd_memory_alloc(struct ufs_hba *hba) 3872 { 3873 size_t utmrdl_size, utrdl_size, ucdl_size; 3874 3875 /* Allocate memory for UTP command descriptors */ 3876 ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs; 3877 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, 3878 ucdl_size, 3879 &hba->ucdl_dma_addr, 3880 GFP_KERNEL); 3881 3882 /* 3883 * UFSHCI requires UTP command descriptor to be 128 byte aligned. 3884 */ 3885 if (!hba->ucdl_base_addr || 3886 WARN_ON(hba->ucdl_dma_addr & (128 - 1))) { 3887 dev_err(hba->dev, 3888 "Command Descriptor Memory allocation failed\n"); 3889 goto out; 3890 } 3891 3892 /* 3893 * Allocate memory for UTP Transfer descriptors 3894 * UFSHCI requires 1KB alignment of UTRD 3895 */ 3896 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs); 3897 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev, 3898 utrdl_size, 3899 &hba->utrdl_dma_addr, 3900 GFP_KERNEL); 3901 if (!hba->utrdl_base_addr || 3902 WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) { 3903 dev_err(hba->dev, 3904 "Transfer Descriptor Memory allocation failed\n"); 3905 goto out; 3906 } 3907 3908 /* 3909 * Skip utmrdl allocation; it may have been 3910 * allocated during first pass and not released during 3911 * MCQ memory allocation. 3912 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq() 3913 */ 3914 if (hba->utmrdl_base_addr) 3915 goto skip_utmrdl; 3916 /* 3917 * Allocate memory for UTP Task Management descriptors 3918 * UFSHCI requires 1KB alignment of UTMRD 3919 */ 3920 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs; 3921 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev, 3922 utmrdl_size, 3923 &hba->utmrdl_dma_addr, 3924 GFP_KERNEL); 3925 if (!hba->utmrdl_base_addr || 3926 WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) { 3927 dev_err(hba->dev, 3928 "Task Management Descriptor Memory allocation failed\n"); 3929 goto out; 3930 } 3931 3932 skip_utmrdl: 3933 /* Allocate memory for local reference block */ 3934 hba->lrb = devm_kcalloc(hba->dev, 3935 hba->nutrs, sizeof(struct ufshcd_lrb), 3936 GFP_KERNEL); 3937 if (!hba->lrb) { 3938 dev_err(hba->dev, "LRB Memory allocation failed\n"); 3939 goto out; 3940 } 3941 return 0; 3942 out: 3943 return -ENOMEM; 3944 } 3945 3946 /** 3947 * ufshcd_host_memory_configure - configure local reference block with 3948 * memory offsets 3949 * @hba: per adapter instance 3950 * 3951 * Configure Host memory space 3952 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA 3953 * address. 3954 * 2. Update each UTRD with Response UPIU offset, Response UPIU length 3955 * and PRDT offset. 3956 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT 3957 * into local reference block. 3958 */ ufshcd_host_memory_configure(struct ufs_hba * hba)3959 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 3960 { 3961 struct utp_transfer_req_desc *utrdlp; 3962 dma_addr_t cmd_desc_dma_addr; 3963 dma_addr_t cmd_desc_element_addr; 3964 u16 response_offset; 3965 u16 prdt_offset; 3966 int cmd_desc_size; 3967 int i; 3968 3969 utrdlp = hba->utrdl_base_addr; 3970 3971 response_offset = 3972 offsetof(struct utp_transfer_cmd_desc, response_upiu); 3973 prdt_offset = 3974 offsetof(struct utp_transfer_cmd_desc, prd_table); 3975 3976 cmd_desc_size = ufshcd_get_ucd_size(hba); 3977 cmd_desc_dma_addr = hba->ucdl_dma_addr; 3978 3979 for (i = 0; i < hba->nutrs; i++) { 3980 /* Configure UTRD with command descriptor base address */ 3981 cmd_desc_element_addr = 3982 (cmd_desc_dma_addr + (cmd_desc_size * i)); 3983 utrdlp[i].command_desc_base_addr = 3984 cpu_to_le64(cmd_desc_element_addr); 3985 3986 /* Response upiu and prdt offset should be in double words */ 3987 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) { 3988 utrdlp[i].response_upiu_offset = 3989 cpu_to_le16(response_offset); 3990 utrdlp[i].prd_table_offset = 3991 cpu_to_le16(prdt_offset); 3992 utrdlp[i].response_upiu_length = 3993 cpu_to_le16(ALIGNED_UPIU_SIZE); 3994 } else { 3995 utrdlp[i].response_upiu_offset = 3996 cpu_to_le16(response_offset >> 2); 3997 utrdlp[i].prd_table_offset = 3998 cpu_to_le16(prdt_offset >> 2); 3999 utrdlp[i].response_upiu_length = 4000 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 4001 } 4002 4003 ufshcd_init_lrb(hba, &hba->lrb[i], i); 4004 } 4005 } 4006 4007 /** 4008 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 4009 * @hba: per adapter instance 4010 * 4011 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer, 4012 * in order to initialize the Unipro link startup procedure. 4013 * Once the Unipro links are up, the device connected to the controller 4014 * is detected. 4015 * 4016 * Return: 0 on success, non-zero value on failure. 4017 */ ufshcd_dme_link_startup(struct ufs_hba * hba)4018 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 4019 { 4020 struct uic_command uic_cmd = { 4021 .command = UIC_CMD_DME_LINK_STARTUP, 4022 }; 4023 int ret; 4024 4025 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4026 if (ret) 4027 dev_dbg(hba->dev, 4028 "dme-link-startup: error code %d\n", ret); 4029 return ret; 4030 } 4031 /** 4032 * ufshcd_dme_reset - UIC command for DME_RESET 4033 * @hba: per adapter instance 4034 * 4035 * DME_RESET command is issued in order to reset UniPro stack. 4036 * This function now deals with cold reset. 4037 * 4038 * Return: 0 on success, non-zero value on failure. 4039 */ ufshcd_dme_reset(struct ufs_hba * hba)4040 int ufshcd_dme_reset(struct ufs_hba *hba) 4041 { 4042 struct uic_command uic_cmd = { 4043 .command = UIC_CMD_DME_RESET, 4044 }; 4045 int ret; 4046 4047 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4048 if (ret) 4049 dev_err(hba->dev, 4050 "dme-reset: error code %d\n", ret); 4051 4052 return ret; 4053 } 4054 EXPORT_SYMBOL_GPL(ufshcd_dme_reset); 4055 ufshcd_dme_configure_adapt(struct ufs_hba * hba,int agreed_gear,int adapt_val)4056 int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 4057 int agreed_gear, 4058 int adapt_val) 4059 { 4060 int ret; 4061 4062 if (agreed_gear < UFS_HS_G4) 4063 adapt_val = PA_NO_ADAPT; 4064 4065 ret = ufshcd_dme_set(hba, 4066 UIC_ARG_MIB(PA_TXHSADAPTTYPE), 4067 adapt_val); 4068 return ret; 4069 } 4070 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt); 4071 4072 /** 4073 * ufshcd_dme_enable - UIC command for DME_ENABLE 4074 * @hba: per adapter instance 4075 * 4076 * DME_ENABLE command is issued in order to enable UniPro stack. 4077 * 4078 * Return: 0 on success, non-zero value on failure. 4079 */ ufshcd_dme_enable(struct ufs_hba * hba)4080 int ufshcd_dme_enable(struct ufs_hba *hba) 4081 { 4082 struct uic_command uic_cmd = { 4083 .command = UIC_CMD_DME_ENABLE, 4084 }; 4085 int ret; 4086 4087 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4088 if (ret) 4089 dev_err(hba->dev, 4090 "dme-enable: error code %d\n", ret); 4091 4092 return ret; 4093 } 4094 EXPORT_SYMBOL_GPL(ufshcd_dme_enable); 4095 ufshcd_add_delay_before_dme_cmd(struct ufs_hba * hba)4096 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba) 4097 { 4098 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000 4099 unsigned long min_sleep_time_us; 4100 4101 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS)) 4102 return; 4103 4104 /* 4105 * last_dme_cmd_tstamp will be 0 only for 1st call to 4106 * this function 4107 */ 4108 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) { 4109 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US; 4110 } else { 4111 unsigned long delta = 4112 (unsigned long) ktime_to_us( 4113 ktime_sub(ktime_get(), 4114 hba->last_dme_cmd_tstamp)); 4115 4116 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US) 4117 min_sleep_time_us = 4118 MIN_DELAY_BEFORE_DME_CMDS_US - delta; 4119 else 4120 min_sleep_time_us = 0; /* no more delay required */ 4121 } 4122 4123 if (min_sleep_time_us > 0) { 4124 /* allow sleep for extra 50us if needed */ 4125 usleep_range(min_sleep_time_us, min_sleep_time_us + 50); 4126 } 4127 4128 /* update the last_dme_cmd_tstamp */ 4129 hba->last_dme_cmd_tstamp = ktime_get(); 4130 } 4131 4132 /** 4133 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 4134 * @hba: per adapter instance 4135 * @attr_sel: uic command argument1 4136 * @attr_set: attribute set type as uic command argument2 4137 * @mib_val: setting value as uic command argument3 4138 * @peer: indicate whether peer or local 4139 * 4140 * Return: 0 on success, non-zero value on failure. 4141 */ ufshcd_dme_set_attr(struct ufs_hba * hba,u32 attr_sel,u8 attr_set,u32 mib_val,u8 peer)4142 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 4143 u8 attr_set, u32 mib_val, u8 peer) 4144 { 4145 struct uic_command uic_cmd = { 4146 .command = peer ? UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET, 4147 .argument1 = attr_sel, 4148 .argument2 = UIC_ARG_ATTR_TYPE(attr_set), 4149 .argument3 = mib_val, 4150 }; 4151 static const char *const action[] = { 4152 "dme-set", 4153 "dme-peer-set" 4154 }; 4155 const char *set = action[!!peer]; 4156 int ret; 4157 int retries = UFS_UIC_COMMAND_RETRIES; 4158 4159 do { 4160 /* for peer attributes we retry upon failure */ 4161 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4162 if (ret) 4163 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 4164 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 4165 } while (ret && peer && --retries); 4166 4167 if (ret) 4168 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 4169 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 4170 UFS_UIC_COMMAND_RETRIES - retries); 4171 4172 return ret; 4173 } 4174 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr); 4175 4176 /** 4177 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 4178 * @hba: per adapter instance 4179 * @attr_sel: uic command argument1 4180 * @mib_val: the value of the attribute as returned by the UIC command 4181 * @peer: indicate whether peer or local 4182 * 4183 * Return: 0 on success, non-zero value on failure. 4184 */ ufshcd_dme_get_attr(struct ufs_hba * hba,u32 attr_sel,u32 * mib_val,u8 peer)4185 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 4186 u32 *mib_val, u8 peer) 4187 { 4188 struct uic_command uic_cmd = { 4189 .command = peer ? UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET, 4190 .argument1 = attr_sel, 4191 }; 4192 static const char *const action[] = { 4193 "dme-get", 4194 "dme-peer-get" 4195 }; 4196 const char *get = action[!!peer]; 4197 int ret; 4198 int retries = UFS_UIC_COMMAND_RETRIES; 4199 struct ufs_pa_layer_attr orig_pwr_info; 4200 struct ufs_pa_layer_attr temp_pwr_info; 4201 bool pwr_mode_change = false; 4202 4203 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) { 4204 orig_pwr_info = hba->pwr_info; 4205 temp_pwr_info = orig_pwr_info; 4206 4207 if (orig_pwr_info.pwr_tx == FAST_MODE || 4208 orig_pwr_info.pwr_rx == FAST_MODE) { 4209 temp_pwr_info.pwr_tx = FASTAUTO_MODE; 4210 temp_pwr_info.pwr_rx = FASTAUTO_MODE; 4211 pwr_mode_change = true; 4212 } else if (orig_pwr_info.pwr_tx == SLOW_MODE || 4213 orig_pwr_info.pwr_rx == SLOW_MODE) { 4214 temp_pwr_info.pwr_tx = SLOWAUTO_MODE; 4215 temp_pwr_info.pwr_rx = SLOWAUTO_MODE; 4216 pwr_mode_change = true; 4217 } 4218 if (pwr_mode_change) { 4219 ret = ufshcd_change_power_mode(hba, &temp_pwr_info); 4220 if (ret) 4221 goto out; 4222 } 4223 } 4224 4225 do { 4226 /* for peer attributes we retry upon failure */ 4227 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4228 if (ret) 4229 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 4230 get, UIC_GET_ATTR_ID(attr_sel), ret); 4231 } while (ret && peer && --retries); 4232 4233 if (ret) 4234 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 4235 get, UIC_GET_ATTR_ID(attr_sel), 4236 UFS_UIC_COMMAND_RETRIES - retries); 4237 4238 if (mib_val && !ret) 4239 *mib_val = uic_cmd.argument3; 4240 4241 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) 4242 && pwr_mode_change) 4243 ufshcd_change_power_mode(hba, &orig_pwr_info); 4244 out: 4245 return ret; 4246 } 4247 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr); 4248 4249 /** 4250 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 4251 * state) and waits for it to take effect. 4252 * 4253 * @hba: per adapter instance 4254 * @cmd: UIC command to execute 4255 * 4256 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER & 4257 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host 4258 * and device UniPro link and hence it's final completion would be indicated by 4259 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in 4260 * addition to normal UIC command completion Status (UCCS). This function only 4261 * returns after the relevant status bits indicate the completion. 4262 * 4263 * Return: 0 on success, non-zero value on failure. 4264 */ ufshcd_uic_pwr_ctrl(struct ufs_hba * hba,struct uic_command * cmd)4265 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 4266 { 4267 DECLARE_COMPLETION_ONSTACK(uic_async_done); 4268 unsigned long flags; 4269 u8 status; 4270 int ret; 4271 bool reenable_intr = false; 4272 4273 mutex_lock(&hba->uic_cmd_mutex); 4274 ufshcd_add_delay_before_dme_cmd(hba); 4275 4276 spin_lock_irqsave(hba->host->host_lock, flags); 4277 if (ufshcd_is_link_broken(hba)) { 4278 ret = -ENOLINK; 4279 goto out_unlock; 4280 } 4281 hba->uic_async_done = &uic_async_done; 4282 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) { 4283 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL); 4284 /* 4285 * Make sure UIC command completion interrupt is disabled before 4286 * issuing UIC command. 4287 */ 4288 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 4289 reenable_intr = true; 4290 } 4291 spin_unlock_irqrestore(hba->host->host_lock, flags); 4292 ret = __ufshcd_send_uic_cmd(hba, cmd); 4293 if (ret) { 4294 dev_err(hba->dev, 4295 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 4296 cmd->command, cmd->argument3, ret); 4297 goto out; 4298 } 4299 4300 if (!wait_for_completion_timeout(hba->uic_async_done, 4301 msecs_to_jiffies(uic_cmd_timeout))) { 4302 dev_err(hba->dev, 4303 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n", 4304 cmd->command, cmd->argument3); 4305 4306 if (!cmd->cmd_active) { 4307 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n", 4308 __func__); 4309 goto check_upmcrs; 4310 } 4311 4312 ret = -ETIMEDOUT; 4313 goto out; 4314 } 4315 4316 check_upmcrs: 4317 status = ufshcd_get_upmcrs(hba); 4318 if (status != PWR_LOCAL) { 4319 dev_err(hba->dev, 4320 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 4321 cmd->command, status); 4322 ret = (status != PWR_OK) ? status : -1; 4323 } 4324 out: 4325 if (ret) { 4326 ufshcd_print_host_state(hba); 4327 ufshcd_print_pwr_info(hba); 4328 ufshcd_print_evt_hist(hba); 4329 } 4330 4331 spin_lock_irqsave(hba->host->host_lock, flags); 4332 hba->active_uic_cmd = NULL; 4333 hba->uic_async_done = NULL; 4334 if (reenable_intr) 4335 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL); 4336 if (ret) { 4337 ufshcd_set_link_broken(hba); 4338 ufshcd_schedule_eh_work(hba); 4339 } 4340 out_unlock: 4341 spin_unlock_irqrestore(hba->host->host_lock, flags); 4342 mutex_unlock(&hba->uic_cmd_mutex); 4343 4344 return ret; 4345 } 4346 4347 /** 4348 * ufshcd_send_bsg_uic_cmd - Send UIC commands requested via BSG layer and retrieve the result 4349 * @hba: per adapter instance 4350 * @uic_cmd: UIC command 4351 * 4352 * Return: 0 only if success. 4353 */ ufshcd_send_bsg_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd)4354 int ufshcd_send_bsg_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 4355 { 4356 int ret; 4357 4358 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD) 4359 return 0; 4360 4361 ufshcd_hold(hba); 4362 4363 if (uic_cmd->argument1 == UIC_ARG_MIB(PA_PWRMODE) && 4364 uic_cmd->command == UIC_CMD_DME_SET) { 4365 ret = ufshcd_uic_pwr_ctrl(hba, uic_cmd); 4366 goto out; 4367 } 4368 4369 mutex_lock(&hba->uic_cmd_mutex); 4370 ufshcd_add_delay_before_dme_cmd(hba); 4371 4372 ret = __ufshcd_send_uic_cmd(hba, uic_cmd); 4373 if (!ret) 4374 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); 4375 4376 mutex_unlock(&hba->uic_cmd_mutex); 4377 4378 out: 4379 ufshcd_release(hba); 4380 return ret; 4381 } 4382 4383 /** 4384 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage 4385 * using DME_SET primitives. 4386 * @hba: per adapter instance 4387 * @mode: powr mode value 4388 * 4389 * Return: 0 on success, non-zero value on failure. 4390 */ ufshcd_uic_change_pwr_mode(struct ufs_hba * hba,u8 mode)4391 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 4392 { 4393 struct uic_command uic_cmd = { 4394 .command = UIC_CMD_DME_SET, 4395 .argument1 = UIC_ARG_MIB(PA_PWRMODE), 4396 .argument3 = mode, 4397 }; 4398 int ret; 4399 4400 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) { 4401 ret = ufshcd_dme_set(hba, 4402 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); 4403 if (ret) { 4404 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n", 4405 __func__, ret); 4406 goto out; 4407 } 4408 } 4409 4410 ufshcd_hold(hba); 4411 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4412 ufshcd_release(hba); 4413 4414 out: 4415 return ret; 4416 } 4417 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode); 4418 ufshcd_link_recovery(struct ufs_hba * hba)4419 int ufshcd_link_recovery(struct ufs_hba *hba) 4420 { 4421 int ret; 4422 unsigned long flags; 4423 4424 spin_lock_irqsave(hba->host->host_lock, flags); 4425 hba->ufshcd_state = UFSHCD_STATE_RESET; 4426 ufshcd_set_eh_in_progress(hba); 4427 spin_unlock_irqrestore(hba->host->host_lock, flags); 4428 4429 /* Reset the attached device */ 4430 ufshcd_device_reset(hba); 4431 4432 ret = ufshcd_host_reset_and_restore(hba); 4433 4434 spin_lock_irqsave(hba->host->host_lock, flags); 4435 if (ret) 4436 hba->ufshcd_state = UFSHCD_STATE_ERROR; 4437 ufshcd_clear_eh_in_progress(hba); 4438 spin_unlock_irqrestore(hba->host->host_lock, flags); 4439 4440 if (ret) 4441 dev_err(hba->dev, "%s: link recovery failed, err %d", 4442 __func__, ret); 4443 4444 return ret; 4445 } 4446 EXPORT_SYMBOL_GPL(ufshcd_link_recovery); 4447 ufshcd_uic_hibern8_enter(struct ufs_hba * hba)4448 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba) 4449 { 4450 struct uic_command uic_cmd = { 4451 .command = UIC_CMD_DME_HIBER_ENTER, 4452 }; 4453 ktime_t start = ktime_get(); 4454 int ret; 4455 4456 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE); 4457 4458 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4459 trace_ufshcd_profile_hibern8(hba, "enter", 4460 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4461 4462 if (ret) 4463 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n", 4464 __func__, ret); 4465 else 4466 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, 4467 POST_CHANGE); 4468 4469 return ret; 4470 } 4471 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter); 4472 ufshcd_uic_hibern8_exit(struct ufs_hba * hba)4473 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) 4474 { 4475 struct uic_command uic_cmd = { 4476 .command = UIC_CMD_DME_HIBER_EXIT, 4477 }; 4478 int ret; 4479 ktime_t start = ktime_get(); 4480 4481 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE); 4482 4483 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4484 trace_ufshcd_profile_hibern8(hba, "exit", 4485 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4486 4487 if (ret) { 4488 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n", 4489 __func__, ret); 4490 } else { 4491 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, 4492 POST_CHANGE); 4493 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock(); 4494 hba->ufs_stats.hibern8_exit_cnt++; 4495 } 4496 4497 return ret; 4498 } 4499 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit); 4500 ufshcd_configure_auto_hibern8(struct ufs_hba * hba)4501 static void ufshcd_configure_auto_hibern8(struct ufs_hba *hba) 4502 { 4503 if (!ufshcd_is_auto_hibern8_supported(hba)) 4504 return; 4505 4506 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); 4507 } 4508 ufshcd_auto_hibern8_update(struct ufs_hba * hba,u32 ahit)4509 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit) 4510 { 4511 const u32 cur_ahit = READ_ONCE(hba->ahit); 4512 4513 if (!ufshcd_is_auto_hibern8_supported(hba) || cur_ahit == ahit) 4514 return; 4515 4516 WRITE_ONCE(hba->ahit, ahit); 4517 if (!pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) { 4518 ufshcd_rpm_get_sync(hba); 4519 ufshcd_hold(hba); 4520 ufshcd_configure_auto_hibern8(hba); 4521 ufshcd_release(hba); 4522 ufshcd_rpm_put_sync(hba); 4523 } 4524 } 4525 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update); 4526 4527 /** 4528 * ufshcd_init_pwr_info - setting the POR (power on reset) 4529 * values in hba power info 4530 * @hba: per-adapter instance 4531 */ ufshcd_init_pwr_info(struct ufs_hba * hba)4532 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 4533 { 4534 hba->pwr_info.gear_rx = UFS_PWM_G1; 4535 hba->pwr_info.gear_tx = UFS_PWM_G1; 4536 hba->pwr_info.lane_rx = UFS_LANE_1; 4537 hba->pwr_info.lane_tx = UFS_LANE_1; 4538 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 4539 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 4540 hba->pwr_info.hs_rate = 0; 4541 } 4542 4543 /** 4544 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 4545 * @hba: per-adapter instance 4546 * 4547 * Return: 0 upon success; < 0 upon failure. 4548 */ ufshcd_get_max_pwr_mode(struct ufs_hba * hba)4549 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 4550 { 4551 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 4552 4553 if (hba->max_pwr_info.is_valid) 4554 return 0; 4555 4556 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) { 4557 pwr_info->pwr_tx = FASTAUTO_MODE; 4558 pwr_info->pwr_rx = FASTAUTO_MODE; 4559 } else { 4560 pwr_info->pwr_tx = FAST_MODE; 4561 pwr_info->pwr_rx = FAST_MODE; 4562 } 4563 pwr_info->hs_rate = PA_HS_MODE_B; 4564 4565 /* Get the connected lane count */ 4566 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 4567 &pwr_info->lane_rx); 4568 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4569 &pwr_info->lane_tx); 4570 4571 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 4572 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 4573 __func__, 4574 pwr_info->lane_rx, 4575 pwr_info->lane_tx); 4576 return -EINVAL; 4577 } 4578 4579 if (pwr_info->lane_rx != pwr_info->lane_tx) { 4580 dev_err(hba->dev, "%s: asymmetric connected lanes. rx=%d, tx=%d\n", 4581 __func__, 4582 pwr_info->lane_rx, 4583 pwr_info->lane_tx); 4584 return -EINVAL; 4585 } 4586 4587 /* 4588 * First, get the maximum gears of HS speed. 4589 * If a zero value, it means there is no HSGEAR capability. 4590 * Then, get the maximum gears of PWM speed. 4591 */ 4592 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 4593 if (!pwr_info->gear_rx) { 4594 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4595 &pwr_info->gear_rx); 4596 if (!pwr_info->gear_rx) { 4597 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 4598 __func__, pwr_info->gear_rx); 4599 return -EINVAL; 4600 } 4601 pwr_info->pwr_rx = SLOW_MODE; 4602 } 4603 4604 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 4605 &pwr_info->gear_tx); 4606 if (!pwr_info->gear_tx) { 4607 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4608 &pwr_info->gear_tx); 4609 if (!pwr_info->gear_tx) { 4610 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 4611 __func__, pwr_info->gear_tx); 4612 return -EINVAL; 4613 } 4614 pwr_info->pwr_tx = SLOW_MODE; 4615 } 4616 4617 hba->max_pwr_info.is_valid = true; 4618 return 0; 4619 } 4620 ufshcd_change_power_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * pwr_mode)4621 static int ufshcd_change_power_mode(struct ufs_hba *hba, 4622 struct ufs_pa_layer_attr *pwr_mode) 4623 { 4624 int ret; 4625 4626 /* if already configured to the requested pwr_mode */ 4627 if (!hba->force_pmc && 4628 pwr_mode->gear_rx == hba->pwr_info.gear_rx && 4629 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 4630 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 4631 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 4632 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 4633 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 4634 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 4635 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 4636 return 0; 4637 } 4638 4639 /* 4640 * Configure attributes for power mode change with below. 4641 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 4642 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 4643 * - PA_HSSERIES 4644 */ 4645 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 4646 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 4647 pwr_mode->lane_rx); 4648 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4649 pwr_mode->pwr_rx == FAST_MODE) 4650 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true); 4651 else 4652 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false); 4653 4654 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 4655 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 4656 pwr_mode->lane_tx); 4657 if (pwr_mode->pwr_tx == FASTAUTO_MODE || 4658 pwr_mode->pwr_tx == FAST_MODE) 4659 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); 4660 else 4661 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false); 4662 4663 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4664 pwr_mode->pwr_tx == FASTAUTO_MODE || 4665 pwr_mode->pwr_rx == FAST_MODE || 4666 pwr_mode->pwr_tx == FAST_MODE) 4667 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 4668 pwr_mode->hs_rate); 4669 4670 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) { 4671 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 4672 DL_FC0ProtectionTimeOutVal_Default); 4673 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 4674 DL_TC0ReplayTimeOutVal_Default); 4675 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 4676 DL_AFC0ReqTimeOutVal_Default); 4677 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), 4678 DL_FC1ProtectionTimeOutVal_Default); 4679 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4), 4680 DL_TC1ReplayTimeOutVal_Default); 4681 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5), 4682 DL_AFC1ReqTimeOutVal_Default); 4683 4684 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), 4685 DL_FC0ProtectionTimeOutVal_Default); 4686 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), 4687 DL_TC0ReplayTimeOutVal_Default); 4688 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), 4689 DL_AFC0ReqTimeOutVal_Default); 4690 } 4691 4692 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 4693 | pwr_mode->pwr_tx); 4694 4695 if (ret) { 4696 dev_err(hba->dev, 4697 "%s: power mode change failed %d\n", __func__, ret); 4698 } else { 4699 memcpy(&hba->pwr_info, pwr_mode, 4700 sizeof(struct ufs_pa_layer_attr)); 4701 } 4702 4703 return ret; 4704 } 4705 4706 /** 4707 * ufshcd_config_pwr_mode - configure a new power mode 4708 * @hba: per-adapter instance 4709 * @desired_pwr_mode: desired power configuration 4710 * 4711 * Return: 0 upon success; < 0 upon failure. 4712 */ ufshcd_config_pwr_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * desired_pwr_mode)4713 int ufshcd_config_pwr_mode(struct ufs_hba *hba, 4714 struct ufs_pa_layer_attr *desired_pwr_mode) 4715 { 4716 struct ufs_pa_layer_attr final_params = { 0 }; 4717 int ret; 4718 4719 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, 4720 desired_pwr_mode, &final_params); 4721 4722 if (ret) 4723 memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); 4724 4725 ret = ufshcd_change_power_mode(hba, &final_params); 4726 4727 if (!ret) 4728 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL, 4729 &final_params); 4730 4731 return ret; 4732 } 4733 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); 4734 4735 /** 4736 * ufshcd_complete_dev_init() - checks device readiness 4737 * @hba: per-adapter instance 4738 * 4739 * Set fDeviceInit flag and poll until device toggles it. 4740 * 4741 * Return: 0 upon success; < 0 upon failure. 4742 */ ufshcd_complete_dev_init(struct ufs_hba * hba)4743 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 4744 { 4745 int err; 4746 bool flag_res = true; 4747 ktime_t timeout; 4748 4749 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 4750 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL); 4751 if (err) { 4752 dev_err(hba->dev, 4753 "%s: setting fDeviceInit flag failed with error %d\n", 4754 __func__, err); 4755 goto out; 4756 } 4757 4758 /* Poll fDeviceInit flag to be cleared */ 4759 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT); 4760 do { 4761 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG, 4762 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res); 4763 if (!flag_res) 4764 break; 4765 usleep_range(500, 1000); 4766 } while (ktime_before(ktime_get(), timeout)); 4767 4768 if (err) { 4769 dev_err(hba->dev, 4770 "%s: reading fDeviceInit flag failed with error %d\n", 4771 __func__, err); 4772 } else if (flag_res) { 4773 dev_err(hba->dev, 4774 "%s: fDeviceInit was not cleared by the device\n", 4775 __func__); 4776 err = -EBUSY; 4777 } 4778 out: 4779 return err; 4780 } 4781 4782 /** 4783 * ufshcd_make_hba_operational - Make UFS controller operational 4784 * @hba: per adapter instance 4785 * 4786 * To bring UFS host controller to operational state, 4787 * 1. Enable required interrupts 4788 * 2. Configure interrupt aggregation 4789 * 3. Program UTRL and UTMRL base address 4790 * 4. Configure run-stop-registers 4791 * 4792 * Return: 0 on success, non-zero value on failure. 4793 */ ufshcd_make_hba_operational(struct ufs_hba * hba)4794 int ufshcd_make_hba_operational(struct ufs_hba *hba) 4795 { 4796 int err = 0; 4797 u32 reg; 4798 4799 /* Enable required interrupts */ 4800 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 4801 4802 /* Configure interrupt aggregation */ 4803 if (ufshcd_is_intr_aggr_allowed(hba)) 4804 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO); 4805 else 4806 ufshcd_disable_intr_aggr(hba); 4807 4808 /* Configure UTRL and UTMRL base address registers */ 4809 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 4810 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 4811 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 4812 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 4813 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 4814 REG_UTP_TASK_REQ_LIST_BASE_L); 4815 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 4816 REG_UTP_TASK_REQ_LIST_BASE_H); 4817 4818 /* 4819 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 4820 */ 4821 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 4822 if (!(ufshcd_get_lists_status(reg))) { 4823 ufshcd_enable_run_stop_reg(hba); 4824 } else { 4825 dev_err(hba->dev, 4826 "Host controller not ready to process requests"); 4827 err = -EIO; 4828 } 4829 4830 return err; 4831 } 4832 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational); 4833 4834 /** 4835 * ufshcd_hba_stop - Send controller to reset state 4836 * @hba: per adapter instance 4837 */ ufshcd_hba_stop(struct ufs_hba * hba)4838 void ufshcd_hba_stop(struct ufs_hba *hba) 4839 { 4840 int err; 4841 4842 ufshcd_disable_irq(hba); 4843 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 4844 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 4845 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 4846 10, 1); 4847 ufshcd_enable_irq(hba); 4848 if (err) 4849 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 4850 } 4851 EXPORT_SYMBOL_GPL(ufshcd_hba_stop); 4852 4853 /** 4854 * ufshcd_hba_execute_hce - initialize the controller 4855 * @hba: per adapter instance 4856 * 4857 * The controller resets itself and controller firmware initialization 4858 * sequence kicks off. When controller is ready it will set 4859 * the Host Controller Enable bit to 1. 4860 * 4861 * Return: 0 on success, non-zero value on failure. 4862 */ ufshcd_hba_execute_hce(struct ufs_hba * hba)4863 static int ufshcd_hba_execute_hce(struct ufs_hba *hba) 4864 { 4865 int retry; 4866 4867 for (retry = 3; retry > 0; retry--) { 4868 if (ufshcd_is_hba_active(hba)) 4869 /* change controller state to "reset state" */ 4870 ufshcd_hba_stop(hba); 4871 4872 /* UniPro link is disabled at this point */ 4873 ufshcd_set_link_off(hba); 4874 4875 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4876 4877 /* start controller initialization sequence */ 4878 ufshcd_hba_start(hba); 4879 4880 /* 4881 * To initialize a UFS host controller HCE bit must be set to 1. 4882 * During initialization the HCE bit value changes from 1->0->1. 4883 * When the host controller completes initialization sequence 4884 * it sets the value of HCE bit to 1. The same HCE bit is read back 4885 * to check if the controller has completed initialization sequence. 4886 * So without this delay the value HCE = 1, set in the previous 4887 * instruction might be read back. 4888 * This delay can be changed based on the controller. 4889 */ 4890 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100); 4891 4892 /* wait for the host controller to complete initialization */ 4893 if (!ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, CONTROLLER_ENABLE, 4894 CONTROLLER_ENABLE, 1000, 50)) 4895 break; 4896 4897 dev_err(hba->dev, "Enabling the controller failed\n"); 4898 } 4899 4900 if (!retry) 4901 return -EIO; 4902 4903 /* enable UIC related interrupts */ 4904 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4905 4906 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4907 4908 return 0; 4909 } 4910 ufshcd_hba_enable(struct ufs_hba * hba)4911 int ufshcd_hba_enable(struct ufs_hba *hba) 4912 { 4913 int ret; 4914 4915 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) { 4916 ufshcd_set_link_off(hba); 4917 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4918 4919 /* enable UIC related interrupts */ 4920 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4921 ret = ufshcd_dme_reset(hba); 4922 if (ret) { 4923 dev_err(hba->dev, "DME_RESET failed\n"); 4924 return ret; 4925 } 4926 4927 ret = ufshcd_dme_enable(hba); 4928 if (ret) { 4929 dev_err(hba->dev, "Enabling DME failed\n"); 4930 return ret; 4931 } 4932 4933 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4934 } else { 4935 ret = ufshcd_hba_execute_hce(hba); 4936 } 4937 4938 return ret; 4939 } 4940 EXPORT_SYMBOL_GPL(ufshcd_hba_enable); 4941 ufshcd_disable_tx_lcc(struct ufs_hba * hba,bool peer)4942 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 4943 { 4944 int tx_lanes = 0, i, err = 0; 4945 4946 if (!peer) 4947 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4948 &tx_lanes); 4949 else 4950 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4951 &tx_lanes); 4952 for (i = 0; i < tx_lanes; i++) { 4953 if (!peer) 4954 err = ufshcd_dme_set(hba, 4955 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4956 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4957 0); 4958 else 4959 err = ufshcd_dme_peer_set(hba, 4960 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4961 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4962 0); 4963 if (err) { 4964 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", 4965 __func__, peer, i, err); 4966 break; 4967 } 4968 } 4969 4970 return err; 4971 } 4972 ufshcd_disable_device_tx_lcc(struct ufs_hba * hba)4973 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 4974 { 4975 return ufshcd_disable_tx_lcc(hba, true); 4976 } 4977 ufshcd_update_evt_hist(struct ufs_hba * hba,u32 id,u32 val)4978 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val) 4979 { 4980 struct ufs_event_hist *e; 4981 4982 if (id >= UFS_EVT_CNT) 4983 return; 4984 4985 e = &hba->ufs_stats.event[id]; 4986 e->val[e->pos] = val; 4987 e->tstamp[e->pos] = local_clock(); 4988 e->cnt += 1; 4989 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH; 4990 4991 ufshcd_vops_event_notify(hba, id, &val); 4992 } 4993 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist); 4994 4995 /** 4996 * ufshcd_link_startup - Initialize unipro link startup 4997 * @hba: per adapter instance 4998 * 4999 * Return: 0 for success, non-zero in case of failure. 5000 */ ufshcd_link_startup(struct ufs_hba * hba)5001 static int ufshcd_link_startup(struct ufs_hba *hba) 5002 { 5003 int ret; 5004 int retries = DME_LINKSTARTUP_RETRIES; 5005 bool link_startup_again = false; 5006 5007 /* 5008 * If UFS device isn't active then we will have to issue link startup 5009 * 2 times to make sure the device state move to active. 5010 */ 5011 if (!ufshcd_is_ufs_dev_active(hba)) 5012 link_startup_again = true; 5013 5014 link_startup: 5015 do { 5016 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE); 5017 5018 ret = ufshcd_dme_link_startup(hba); 5019 5020 /* check if device is detected by inter-connect layer */ 5021 if (!ret && !ufshcd_is_device_present(hba)) { 5022 ufshcd_update_evt_hist(hba, 5023 UFS_EVT_LINK_STARTUP_FAIL, 5024 0); 5025 dev_err(hba->dev, "%s: Device not present\n", __func__); 5026 ret = -ENXIO; 5027 goto out; 5028 } 5029 5030 /* 5031 * DME link lost indication is only received when link is up, 5032 * but we can't be sure if the link is up until link startup 5033 * succeeds. So reset the local Uni-Pro and try again. 5034 */ 5035 if (ret && retries && ufshcd_hba_enable(hba)) { 5036 ufshcd_update_evt_hist(hba, 5037 UFS_EVT_LINK_STARTUP_FAIL, 5038 (u32)ret); 5039 goto out; 5040 } 5041 } while (ret && retries--); 5042 5043 if (ret) { 5044 /* failed to get the link up... retire */ 5045 ufshcd_update_evt_hist(hba, 5046 UFS_EVT_LINK_STARTUP_FAIL, 5047 (u32)ret); 5048 goto out; 5049 } 5050 5051 if (link_startup_again) { 5052 link_startup_again = false; 5053 retries = DME_LINKSTARTUP_RETRIES; 5054 goto link_startup; 5055 } 5056 5057 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 5058 ufshcd_init_pwr_info(hba); 5059 ufshcd_print_pwr_info(hba); 5060 5061 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 5062 ret = ufshcd_disable_device_tx_lcc(hba); 5063 if (ret) 5064 goto out; 5065 } 5066 5067 /* Include any host controller configuration via UIC commands */ 5068 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE); 5069 if (ret) 5070 goto out; 5071 5072 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */ 5073 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 5074 ret = ufshcd_make_hba_operational(hba); 5075 out: 5076 if (ret) { 5077 dev_err(hba->dev, "link startup failed %d\n", ret); 5078 ufshcd_print_host_state(hba); 5079 ufshcd_print_pwr_info(hba); 5080 ufshcd_print_evt_hist(hba); 5081 } 5082 return ret; 5083 } 5084 5085 /** 5086 * ufshcd_verify_dev_init() - Verify device initialization 5087 * @hba: per-adapter instance 5088 * 5089 * Send NOP OUT UPIU and wait for NOP IN response to check whether the 5090 * device Transport Protocol (UTP) layer is ready after a reset. 5091 * If the UTP layer at the device side is not initialized, it may 5092 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT 5093 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations. 5094 * 5095 * Return: 0 upon success; < 0 upon failure. 5096 */ ufshcd_verify_dev_init(struct ufs_hba * hba)5097 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 5098 { 5099 int err = 0; 5100 int retries; 5101 5102 ufshcd_dev_man_lock(hba); 5103 5104 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 5105 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 5106 hba->nop_out_timeout); 5107 5108 if (!err || err == -ETIMEDOUT) 5109 break; 5110 5111 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 5112 } 5113 5114 ufshcd_dev_man_unlock(hba); 5115 5116 if (err) 5117 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 5118 return err; 5119 } 5120 5121 /** 5122 * ufshcd_setup_links - associate link b/w device wlun and other luns 5123 * @sdev: pointer to SCSI device 5124 * @hba: pointer to ufs hba 5125 */ ufshcd_setup_links(struct ufs_hba * hba,struct scsi_device * sdev)5126 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev) 5127 { 5128 struct device_link *link; 5129 5130 /* 5131 * Device wlun is the supplier & rest of the luns are consumers. 5132 * This ensures that device wlun suspends after all other luns. 5133 */ 5134 if (hba->ufs_device_wlun) { 5135 link = device_link_add(&sdev->sdev_gendev, 5136 &hba->ufs_device_wlun->sdev_gendev, 5137 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); 5138 if (!link) { 5139 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n", 5140 dev_name(&hba->ufs_device_wlun->sdev_gendev)); 5141 return; 5142 } 5143 hba->luns_avail--; 5144 /* Ignore REPORT_LUN wlun probing */ 5145 if (hba->luns_avail == 1) { 5146 ufshcd_rpm_put(hba); 5147 return; 5148 } 5149 } else { 5150 /* 5151 * Device wlun is probed. The assumption is that WLUNs are 5152 * scanned before other LUNs. 5153 */ 5154 hba->luns_avail--; 5155 } 5156 } 5157 5158 /** 5159 * ufshcd_lu_init - Initialize the relevant parameters of the LU 5160 * @hba: per-adapter instance 5161 * @sdev: pointer to SCSI device 5162 */ ufshcd_lu_init(struct ufs_hba * hba,struct scsi_device * sdev)5163 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev) 5164 { 5165 int len = QUERY_DESC_MAX_SIZE; 5166 u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun); 5167 u8 lun_qdepth = hba->nutrs; 5168 u8 *desc_buf; 5169 int ret; 5170 5171 desc_buf = kzalloc(len, GFP_KERNEL); 5172 if (!desc_buf) 5173 goto set_qdepth; 5174 5175 ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len); 5176 if (ret < 0) { 5177 if (ret == -EOPNOTSUPP) 5178 /* If LU doesn't support unit descriptor, its queue depth is set to 1 */ 5179 lun_qdepth = 1; 5180 kfree(desc_buf); 5181 goto set_qdepth; 5182 } 5183 5184 if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) { 5185 /* 5186 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will 5187 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth 5188 */ 5189 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs); 5190 } 5191 /* 5192 * According to UFS device specification, the write protection mode is only supported by 5193 * normal LU, not supported by WLUN. 5194 */ 5195 if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported && 5196 !hba->dev_info.is_lu_power_on_wp && 5197 desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP) 5198 hba->dev_info.is_lu_power_on_wp = true; 5199 5200 /* In case of RPMB LU, check if advanced RPMB mode is enabled */ 5201 if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN && 5202 desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) 5203 hba->dev_info.b_advanced_rpmb_en = true; 5204 5205 5206 kfree(desc_buf); 5207 set_qdepth: 5208 /* 5209 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose 5210 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue. 5211 */ 5212 dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth); 5213 scsi_change_queue_depth(sdev, lun_qdepth); 5214 } 5215 5216 /** 5217 * ufshcd_sdev_init - handle initial SCSI device configurations 5218 * @sdev: pointer to SCSI device 5219 * 5220 * Return: success. 5221 */ ufshcd_sdev_init(struct scsi_device * sdev)5222 static int ufshcd_sdev_init(struct scsi_device *sdev) 5223 { 5224 struct ufs_hba *hba; 5225 5226 hba = shost_priv(sdev->host); 5227 5228 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */ 5229 sdev->use_10_for_ms = 1; 5230 5231 /* DBD field should be set to 1 in mode sense(10) */ 5232 sdev->set_dbd_for_ms = 1; 5233 5234 /* allow SCSI layer to restart the device in case of errors */ 5235 sdev->allow_restart = 1; 5236 5237 /* REPORT SUPPORTED OPERATION CODES is not supported */ 5238 sdev->no_report_opcodes = 1; 5239 5240 /* WRITE_SAME command is not supported */ 5241 sdev->no_write_same = 1; 5242 5243 ufshcd_lu_init(hba, sdev); 5244 5245 ufshcd_setup_links(hba, sdev); 5246 5247 return 0; 5248 } 5249 5250 /** 5251 * ufshcd_change_queue_depth - change queue depth 5252 * @sdev: pointer to SCSI device 5253 * @depth: required depth to set 5254 * 5255 * Change queue depth and make sure the max. limits are not crossed. 5256 * 5257 * Return: new queue depth. 5258 */ ufshcd_change_queue_depth(struct scsi_device * sdev,int depth)5259 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth) 5260 { 5261 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue)); 5262 } 5263 5264 /** 5265 * ufshcd_sdev_configure - adjust SCSI device configurations 5266 * @sdev: pointer to SCSI device 5267 * @lim: queue limits 5268 * 5269 * Return: 0 (success). 5270 */ ufshcd_sdev_configure(struct scsi_device * sdev,struct queue_limits * lim)5271 static int ufshcd_sdev_configure(struct scsi_device *sdev, 5272 struct queue_limits *lim) 5273 { 5274 struct ufs_hba *hba = shost_priv(sdev->host); 5275 struct request_queue *q = sdev->request_queue; 5276 5277 lim->dma_pad_mask = PRDT_DATA_BYTE_COUNT_PAD - 1; 5278 5279 /* 5280 * Block runtime-pm until all consumers are added. 5281 * Refer ufshcd_setup_links(). 5282 */ 5283 if (is_device_wlun(sdev)) 5284 pm_runtime_get_noresume(&sdev->sdev_gendev); 5285 else if (ufshcd_is_rpm_autosuspend_allowed(hba)) 5286 sdev->rpm_autosuspend = 1; 5287 /* 5288 * Do not print messages during runtime PM to avoid never-ending cycles 5289 * of messages written back to storage by user space causing runtime 5290 * resume, causing more messages and so on. 5291 */ 5292 sdev->silence_suspend = 1; 5293 5294 if (hba->vops && hba->vops->config_scsi_dev) 5295 hba->vops->config_scsi_dev(sdev); 5296 5297 ufshcd_crypto_register(hba, q); 5298 5299 return 0; 5300 } 5301 5302 /** 5303 * ufshcd_sdev_destroy - remove SCSI device configurations 5304 * @sdev: pointer to SCSI device 5305 */ ufshcd_sdev_destroy(struct scsi_device * sdev)5306 static void ufshcd_sdev_destroy(struct scsi_device *sdev) 5307 { 5308 struct ufs_hba *hba; 5309 unsigned long flags; 5310 5311 hba = shost_priv(sdev->host); 5312 5313 /* Drop the reference as it won't be needed anymore */ 5314 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) { 5315 spin_lock_irqsave(hba->host->host_lock, flags); 5316 hba->ufs_device_wlun = NULL; 5317 spin_unlock_irqrestore(hba->host->host_lock, flags); 5318 } else if (hba->ufs_device_wlun) { 5319 struct device *supplier = NULL; 5320 5321 /* Ensure UFS Device WLUN exists and does not disappear */ 5322 spin_lock_irqsave(hba->host->host_lock, flags); 5323 if (hba->ufs_device_wlun) { 5324 supplier = &hba->ufs_device_wlun->sdev_gendev; 5325 get_device(supplier); 5326 } 5327 spin_unlock_irqrestore(hba->host->host_lock, flags); 5328 5329 if (supplier) { 5330 /* 5331 * If a LUN fails to probe (e.g. absent BOOT WLUN), the 5332 * device will not have been registered but can still 5333 * have a device link holding a reference to the device. 5334 */ 5335 device_link_remove(&sdev->sdev_gendev, supplier); 5336 put_device(supplier); 5337 } 5338 } 5339 } 5340 5341 /** 5342 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status 5343 * @lrbp: pointer to local reference block of completed command 5344 * @scsi_status: SCSI command status 5345 * 5346 * Return: value base on SCSI command status. 5347 */ 5348 static inline int ufshcd_scsi_cmd_status(struct ufshcd_lrb * lrbp,int scsi_status)5349 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status) 5350 { 5351 int result = 0; 5352 5353 switch (scsi_status) { 5354 case SAM_STAT_CHECK_CONDITION: 5355 ufshcd_copy_sense_data(lrbp); 5356 fallthrough; 5357 case SAM_STAT_GOOD: 5358 result |= DID_OK << 16 | scsi_status; 5359 break; 5360 case SAM_STAT_TASK_SET_FULL: 5361 case SAM_STAT_BUSY: 5362 case SAM_STAT_TASK_ABORTED: 5363 ufshcd_copy_sense_data(lrbp); 5364 result |= scsi_status; 5365 break; 5366 default: 5367 result |= DID_ERROR << 16; 5368 break; 5369 } /* end of switch */ 5370 5371 return result; 5372 } 5373 5374 /** 5375 * ufshcd_transfer_rsp_status - Get overall status of the response 5376 * @hba: per adapter instance 5377 * @lrbp: pointer to local reference block of completed command 5378 * @cqe: pointer to the completion queue entry 5379 * 5380 * Return: result of the command to notify SCSI midlayer. 5381 */ 5382 static inline int ufshcd_transfer_rsp_status(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,struct cq_entry * cqe)5383 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 5384 struct cq_entry *cqe) 5385 { 5386 int result = 0; 5387 int scsi_status; 5388 enum utp_ocs ocs; 5389 u8 upiu_flags; 5390 u32 resid; 5391 5392 upiu_flags = lrbp->ucd_rsp_ptr->header.flags; 5393 resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count); 5394 /* 5395 * Test !overflow instead of underflow to support UFS devices that do 5396 * not set either flag. 5397 */ 5398 if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW)) 5399 scsi_set_resid(lrbp->cmd, resid); 5400 5401 /* overall command status of utrd */ 5402 ocs = ufshcd_get_tr_ocs(lrbp, cqe); 5403 5404 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) { 5405 if (lrbp->ucd_rsp_ptr->header.response || 5406 lrbp->ucd_rsp_ptr->header.status) 5407 ocs = OCS_SUCCESS; 5408 } 5409 5410 switch (ocs) { 5411 case OCS_SUCCESS: 5412 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 5413 switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) { 5414 case UPIU_TRANSACTION_RESPONSE: 5415 /* 5416 * get the result based on SCSI status response 5417 * to notify the SCSI midlayer of the command status 5418 */ 5419 scsi_status = lrbp->ucd_rsp_ptr->header.status; 5420 result = ufshcd_scsi_cmd_status(lrbp, scsi_status); 5421 5422 /* 5423 * Currently we are only supporting BKOPs exception 5424 * events hence we can ignore BKOPs exception event 5425 * during power management callbacks. BKOPs exception 5426 * event is not expected to be raised in runtime suspend 5427 * callback as it allows the urgent bkops. 5428 * During system suspend, we are anyway forcefully 5429 * disabling the bkops and if urgent bkops is needed 5430 * it will be enabled on system resume. Long term 5431 * solution could be to abort the system suspend if 5432 * UFS device needs urgent BKOPs. 5433 */ 5434 if (!hba->pm_op_in_progress && 5435 !ufshcd_eh_in_progress(hba) && 5436 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) 5437 /* Flushed in suspend */ 5438 schedule_work(&hba->eeh_work); 5439 break; 5440 case UPIU_TRANSACTION_REJECT_UPIU: 5441 /* TODO: handle Reject UPIU Response */ 5442 result = DID_ERROR << 16; 5443 dev_err(hba->dev, 5444 "Reject UPIU not fully implemented\n"); 5445 break; 5446 default: 5447 dev_err(hba->dev, 5448 "Unexpected request response code = %x\n", 5449 result); 5450 result = DID_ERROR << 16; 5451 break; 5452 } 5453 break; 5454 case OCS_ABORTED: 5455 case OCS_INVALID_COMMAND_STATUS: 5456 result |= DID_REQUEUE << 16; 5457 dev_warn(hba->dev, 5458 "OCS %s from controller for tag %d\n", 5459 (ocs == OCS_ABORTED ? "aborted" : "invalid"), 5460 lrbp->task_tag); 5461 break; 5462 case OCS_INVALID_CMD_TABLE_ATTR: 5463 case OCS_INVALID_PRDT_ATTR: 5464 case OCS_MISMATCH_DATA_BUF_SIZE: 5465 case OCS_MISMATCH_RESP_UPIU_SIZE: 5466 case OCS_PEER_COMM_FAILURE: 5467 case OCS_FATAL_ERROR: 5468 case OCS_DEVICE_FATAL_ERROR: 5469 case OCS_INVALID_CRYPTO_CONFIG: 5470 case OCS_GENERAL_CRYPTO_ERROR: 5471 default: 5472 result |= DID_ERROR << 16; 5473 dev_err(hba->dev, 5474 "OCS error from controller = %x for tag %d\n", 5475 ocs, lrbp->task_tag); 5476 ufshcd_print_evt_hist(hba); 5477 ufshcd_print_host_state(hba); 5478 break; 5479 } /* end of switch */ 5480 5481 if ((host_byte(result) != DID_OK) && 5482 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs) 5483 ufshcd_print_tr(hba, lrbp->task_tag, true); 5484 return result; 5485 } 5486 ufshcd_is_auto_hibern8_error(struct ufs_hba * hba,u32 intr_mask)5487 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba, 5488 u32 intr_mask) 5489 { 5490 if (!ufshcd_is_auto_hibern8_supported(hba) || 5491 !ufshcd_is_auto_hibern8_enabled(hba)) 5492 return false; 5493 5494 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK)) 5495 return false; 5496 5497 if (hba->active_uic_cmd && 5498 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER || 5499 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT)) 5500 return false; 5501 5502 return true; 5503 } 5504 5505 /** 5506 * ufshcd_uic_cmd_compl - handle completion of uic command 5507 * @hba: per adapter instance 5508 * @intr_status: interrupt status generated by the controller 5509 * 5510 * Return: 5511 * IRQ_HANDLED - If interrupt is valid 5512 * IRQ_NONE - If invalid interrupt 5513 */ ufshcd_uic_cmd_compl(struct ufs_hba * hba,u32 intr_status)5514 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) 5515 { 5516 irqreturn_t retval = IRQ_NONE; 5517 struct uic_command *cmd; 5518 5519 spin_lock(hba->host->host_lock); 5520 cmd = hba->active_uic_cmd; 5521 if (WARN_ON_ONCE(!cmd)) 5522 goto unlock; 5523 5524 if (ufshcd_is_auto_hibern8_error(hba, intr_status)) 5525 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status); 5526 5527 if (intr_status & UIC_COMMAND_COMPL) { 5528 cmd->argument2 |= ufshcd_get_uic_cmd_result(hba); 5529 cmd->argument3 = ufshcd_get_dme_attr_val(hba); 5530 if (!hba->uic_async_done) 5531 cmd->cmd_active = 0; 5532 complete(&cmd->done); 5533 retval = IRQ_HANDLED; 5534 } 5535 5536 if (intr_status & UFSHCD_UIC_PWR_MASK && hba->uic_async_done) { 5537 cmd->cmd_active = 0; 5538 complete(hba->uic_async_done); 5539 retval = IRQ_HANDLED; 5540 } 5541 5542 if (retval == IRQ_HANDLED) 5543 ufshcd_add_uic_command_trace(hba, cmd, UFS_CMD_COMP); 5544 5545 unlock: 5546 spin_unlock(hba->host->host_lock); 5547 5548 return retval; 5549 } 5550 5551 /* Release the resources allocated for processing a SCSI command. */ ufshcd_release_scsi_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)5552 void ufshcd_release_scsi_cmd(struct ufs_hba *hba, 5553 struct ufshcd_lrb *lrbp) 5554 { 5555 struct scsi_cmnd *cmd = lrbp->cmd; 5556 5557 scsi_dma_unmap(cmd); 5558 ufshcd_crypto_clear_prdt(hba, lrbp); 5559 ufshcd_release(hba); 5560 ufshcd_clk_scaling_update_busy(hba); 5561 } 5562 5563 /** 5564 * ufshcd_compl_one_cqe - handle a completion queue entry 5565 * @hba: per adapter instance 5566 * @task_tag: the task tag of the request to be completed 5567 * @cqe: pointer to the completion queue entry 5568 */ ufshcd_compl_one_cqe(struct ufs_hba * hba,int task_tag,struct cq_entry * cqe)5569 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag, 5570 struct cq_entry *cqe) 5571 { 5572 struct ufshcd_lrb *lrbp; 5573 struct scsi_cmnd *cmd; 5574 enum utp_ocs ocs; 5575 5576 lrbp = &hba->lrb[task_tag]; 5577 lrbp->compl_time_stamp = ktime_get(); 5578 lrbp->compl_time_stamp_local_clock = local_clock(); 5579 cmd = lrbp->cmd; 5580 if (cmd) { 5581 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 5582 ufshcd_update_monitor(hba, lrbp); 5583 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP); 5584 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe); 5585 ufshcd_release_scsi_cmd(hba, lrbp); 5586 /* Do not touch lrbp after scsi done */ 5587 scsi_done(cmd); 5588 } else if (hba->dev_cmd.complete) { 5589 if (cqe) { 5590 ocs = le32_to_cpu(cqe->status) & MASK_OCS; 5591 lrbp->utr_descriptor_ptr->header.ocs = ocs; 5592 } 5593 complete(hba->dev_cmd.complete); 5594 } 5595 } 5596 5597 /** 5598 * __ufshcd_transfer_req_compl - handle SCSI and query command completion 5599 * @hba: per adapter instance 5600 * @completed_reqs: bitmask that indicates which requests to complete 5601 */ __ufshcd_transfer_req_compl(struct ufs_hba * hba,unsigned long completed_reqs)5602 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, 5603 unsigned long completed_reqs) 5604 { 5605 int tag; 5606 5607 for_each_set_bit(tag, &completed_reqs, hba->nutrs) 5608 ufshcd_compl_one_cqe(hba, tag, NULL); 5609 } 5610 5611 /* Any value that is not an existing queue number is fine for this constant. */ 5612 enum { 5613 UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1 5614 }; 5615 ufshcd_clear_polled(struct ufs_hba * hba,unsigned long * completed_reqs)5616 static void ufshcd_clear_polled(struct ufs_hba *hba, 5617 unsigned long *completed_reqs) 5618 { 5619 int tag; 5620 5621 for_each_set_bit(tag, completed_reqs, hba->nutrs) { 5622 struct scsi_cmnd *cmd = hba->lrb[tag].cmd; 5623 5624 if (!cmd) 5625 continue; 5626 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED) 5627 __clear_bit(tag, completed_reqs); 5628 } 5629 } 5630 5631 /* 5632 * Return: > 0 if one or more commands have been completed or 0 if no 5633 * requests have been completed. 5634 */ ufshcd_poll(struct Scsi_Host * shost,unsigned int queue_num)5635 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num) 5636 { 5637 struct ufs_hba *hba = shost_priv(shost); 5638 unsigned long completed_reqs, flags; 5639 u32 tr_doorbell; 5640 struct ufs_hw_queue *hwq; 5641 5642 if (hba->mcq_enabled) { 5643 hwq = &hba->uhq[queue_num]; 5644 5645 return ufshcd_mcq_poll_cqe_lock(hba, hwq); 5646 } 5647 5648 spin_lock_irqsave(&hba->outstanding_lock, flags); 5649 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 5650 completed_reqs = ~tr_doorbell & hba->outstanding_reqs; 5651 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs, 5652 "completed: %#lx; outstanding: %#lx\n", completed_reqs, 5653 hba->outstanding_reqs); 5654 if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) { 5655 /* Do not complete polled requests from interrupt context. */ 5656 ufshcd_clear_polled(hba, &completed_reqs); 5657 } 5658 hba->outstanding_reqs &= ~completed_reqs; 5659 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 5660 5661 if (completed_reqs) 5662 __ufshcd_transfer_req_compl(hba, completed_reqs); 5663 5664 return completed_reqs != 0; 5665 } 5666 5667 /** 5668 * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is 5669 * invoked from the error handler context or ufshcd_host_reset_and_restore() 5670 * to complete the pending transfers and free the resources associated with 5671 * the scsi command. 5672 * 5673 * @hba: per adapter instance 5674 * @force_compl: This flag is set to true when invoked 5675 * from ufshcd_host_reset_and_restore() in which case it requires special 5676 * handling because the host controller has been reset by ufshcd_hba_stop(). 5677 */ ufshcd_mcq_compl_pending_transfer(struct ufs_hba * hba,bool force_compl)5678 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba, 5679 bool force_compl) 5680 { 5681 struct ufs_hw_queue *hwq; 5682 struct ufshcd_lrb *lrbp; 5683 struct scsi_cmnd *cmd; 5684 unsigned long flags; 5685 int tag; 5686 5687 for (tag = 0; tag < hba->nutrs; tag++) { 5688 lrbp = &hba->lrb[tag]; 5689 cmd = lrbp->cmd; 5690 if (!ufshcd_cmd_inflight(cmd) || 5691 test_bit(SCMD_STATE_COMPLETE, &cmd->state)) 5692 continue; 5693 5694 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 5695 5696 if (force_compl) { 5697 ufshcd_mcq_compl_all_cqes_lock(hba, hwq); 5698 /* 5699 * For those cmds of which the cqes are not present 5700 * in the cq, complete them explicitly. 5701 */ 5702 spin_lock_irqsave(&hwq->cq_lock, flags); 5703 if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) { 5704 set_host_byte(cmd, DID_REQUEUE); 5705 ufshcd_release_scsi_cmd(hba, lrbp); 5706 scsi_done(cmd); 5707 } 5708 spin_unlock_irqrestore(&hwq->cq_lock, flags); 5709 } else { 5710 ufshcd_mcq_poll_cqe_lock(hba, hwq); 5711 } 5712 } 5713 } 5714 5715 /** 5716 * ufshcd_transfer_req_compl - handle SCSI and query command completion 5717 * @hba: per adapter instance 5718 * 5719 * Return: 5720 * IRQ_HANDLED - If interrupt is valid 5721 * IRQ_NONE - If invalid interrupt 5722 */ ufshcd_transfer_req_compl(struct ufs_hba * hba)5723 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) 5724 { 5725 /* Resetting interrupt aggregation counters first and reading the 5726 * DOOR_BELL afterward allows us to handle all the completed requests. 5727 * In order to prevent other interrupts starvation the DB is read once 5728 * after reset. The down side of this solution is the possibility of 5729 * false interrupt if device completes another request after resetting 5730 * aggregation and before reading the DB. 5731 */ 5732 if (ufshcd_is_intr_aggr_allowed(hba) && 5733 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR)) 5734 ufshcd_reset_intr_aggr(hba); 5735 5736 if (ufs_fail_completion(hba)) 5737 return IRQ_HANDLED; 5738 5739 /* 5740 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we 5741 * do not want polling to trigger spurious interrupt complaints. 5742 */ 5743 ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT); 5744 5745 return IRQ_HANDLED; 5746 } 5747 __ufshcd_write_ee_control(struct ufs_hba * hba,u32 ee_ctrl_mask)5748 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask) 5749 { 5750 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 5751 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, 5752 &ee_ctrl_mask); 5753 } 5754 ufshcd_write_ee_control(struct ufs_hba * hba)5755 int ufshcd_write_ee_control(struct ufs_hba *hba) 5756 { 5757 int err; 5758 5759 mutex_lock(&hba->ee_ctrl_mutex); 5760 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask); 5761 mutex_unlock(&hba->ee_ctrl_mutex); 5762 if (err) 5763 dev_err(hba->dev, "%s: failed to write ee control %d\n", 5764 __func__, err); 5765 return err; 5766 } 5767 ufshcd_update_ee_control(struct ufs_hba * hba,u16 * mask,const u16 * other_mask,u16 set,u16 clr)5768 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 5769 const u16 *other_mask, u16 set, u16 clr) 5770 { 5771 u16 new_mask, ee_ctrl_mask; 5772 int err = 0; 5773 5774 mutex_lock(&hba->ee_ctrl_mutex); 5775 new_mask = (*mask & ~clr) | set; 5776 ee_ctrl_mask = new_mask | *other_mask; 5777 if (ee_ctrl_mask != hba->ee_ctrl_mask) 5778 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask); 5779 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */ 5780 if (!err) { 5781 hba->ee_ctrl_mask = ee_ctrl_mask; 5782 *mask = new_mask; 5783 } 5784 mutex_unlock(&hba->ee_ctrl_mutex); 5785 return err; 5786 } 5787 5788 /** 5789 * ufshcd_disable_ee - disable exception event 5790 * @hba: per-adapter instance 5791 * @mask: exception event to disable 5792 * 5793 * Disables exception event in the device so that the EVENT_ALERT 5794 * bit is not set. 5795 * 5796 * Return: zero on success, non-zero error value on failure. 5797 */ ufshcd_disable_ee(struct ufs_hba * hba,u16 mask)5798 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) 5799 { 5800 return ufshcd_update_ee_drv_mask(hba, 0, mask); 5801 } 5802 5803 /** 5804 * ufshcd_enable_ee - enable exception event 5805 * @hba: per-adapter instance 5806 * @mask: exception event to enable 5807 * 5808 * Enable corresponding exception event in the device to allow 5809 * device to alert host in critical scenarios. 5810 * 5811 * Return: zero on success, non-zero error value on failure. 5812 */ ufshcd_enable_ee(struct ufs_hba * hba,u16 mask)5813 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) 5814 { 5815 return ufshcd_update_ee_drv_mask(hba, mask, 0); 5816 } 5817 5818 /** 5819 * ufshcd_enable_auto_bkops - Allow device managed BKOPS 5820 * @hba: per-adapter instance 5821 * 5822 * Allow device to manage background operations on its own. Enabling 5823 * this might lead to inconsistent latencies during normal data transfers 5824 * as the device is allowed to manage its own way of handling background 5825 * operations. 5826 * 5827 * Return: zero on success, non-zero on failure. 5828 */ ufshcd_enable_auto_bkops(struct ufs_hba * hba)5829 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba) 5830 { 5831 int err = 0; 5832 5833 if (hba->auto_bkops_enabled) 5834 goto out; 5835 5836 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 5837 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5838 if (err) { 5839 dev_err(hba->dev, "%s: failed to enable bkops %d\n", 5840 __func__, err); 5841 goto out; 5842 } 5843 5844 hba->auto_bkops_enabled = true; 5845 trace_ufshcd_auto_bkops_state(hba, "Enabled"); 5846 5847 /* No need of URGENT_BKOPS exception from the device */ 5848 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5849 if (err) 5850 dev_err(hba->dev, "%s: failed to disable exception event %d\n", 5851 __func__, err); 5852 out: 5853 return err; 5854 } 5855 5856 /** 5857 * ufshcd_disable_auto_bkops - block device in doing background operations 5858 * @hba: per-adapter instance 5859 * 5860 * Disabling background operations improves command response latency but 5861 * has drawback of device moving into critical state where the device is 5862 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the 5863 * host is idle so that BKOPS are managed effectively without any negative 5864 * impacts. 5865 * 5866 * Return: zero on success, non-zero on failure. 5867 */ ufshcd_disable_auto_bkops(struct ufs_hba * hba)5868 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba) 5869 { 5870 int err = 0; 5871 5872 if (!hba->auto_bkops_enabled) 5873 goto out; 5874 5875 /* 5876 * If host assisted BKOPs is to be enabled, make sure 5877 * urgent bkops exception is allowed. 5878 */ 5879 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS); 5880 if (err) { 5881 dev_err(hba->dev, "%s: failed to enable exception event %d\n", 5882 __func__, err); 5883 goto out; 5884 } 5885 5886 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, 5887 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5888 if (err) { 5889 dev_err(hba->dev, "%s: failed to disable bkops %d\n", 5890 __func__, err); 5891 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5892 goto out; 5893 } 5894 5895 hba->auto_bkops_enabled = false; 5896 trace_ufshcd_auto_bkops_state(hba, "Disabled"); 5897 hba->is_urgent_bkops_lvl_checked = false; 5898 out: 5899 return err; 5900 } 5901 5902 /** 5903 * ufshcd_force_reset_auto_bkops - force reset auto bkops state 5904 * @hba: per adapter instance 5905 * 5906 * After a device reset the device may toggle the BKOPS_EN flag 5907 * to default value. The s/w tracking variables should be updated 5908 * as well. This function would change the auto-bkops state based on 5909 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND. 5910 */ ufshcd_force_reset_auto_bkops(struct ufs_hba * hba)5911 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba) 5912 { 5913 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) { 5914 hba->auto_bkops_enabled = false; 5915 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS; 5916 ufshcd_enable_auto_bkops(hba); 5917 } else { 5918 hba->auto_bkops_enabled = true; 5919 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS; 5920 ufshcd_disable_auto_bkops(hba); 5921 } 5922 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT; 5923 hba->is_urgent_bkops_lvl_checked = false; 5924 } 5925 ufshcd_get_bkops_status(struct ufs_hba * hba,u32 * status)5926 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) 5927 { 5928 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5929 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); 5930 } 5931 5932 /** 5933 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status 5934 * @hba: per-adapter instance 5935 * 5936 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn 5937 * flag in the device to permit background operations if the device 5938 * bkops_status is greater than or equal to the "hba->urgent_bkops_lvl", 5939 * disable otherwise. 5940 * 5941 * Return: 0 for success, non-zero in case of failure. 5942 * 5943 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag 5944 * to know whether auto bkops is enabled or disabled after this function 5945 * returns control to it. 5946 */ ufshcd_bkops_ctrl(struct ufs_hba * hba)5947 static int ufshcd_bkops_ctrl(struct ufs_hba *hba) 5948 { 5949 enum bkops_status status = hba->urgent_bkops_lvl; 5950 u32 curr_status = 0; 5951 int err; 5952 5953 err = ufshcd_get_bkops_status(hba, &curr_status); 5954 if (err) { 5955 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5956 __func__, err); 5957 goto out; 5958 } else if (curr_status > BKOPS_STATUS_MAX) { 5959 dev_err(hba->dev, "%s: invalid BKOPS status %d\n", 5960 __func__, curr_status); 5961 err = -EINVAL; 5962 goto out; 5963 } 5964 5965 if (curr_status >= status) 5966 err = ufshcd_enable_auto_bkops(hba); 5967 else 5968 err = ufshcd_disable_auto_bkops(hba); 5969 out: 5970 return err; 5971 } 5972 ufshcd_get_ee_status(struct ufs_hba * hba,u32 * status)5973 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) 5974 { 5975 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5976 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); 5977 } 5978 ufshcd_bkops_exception_event_handler(struct ufs_hba * hba)5979 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba) 5980 { 5981 int err; 5982 u32 curr_status = 0; 5983 5984 if (hba->is_urgent_bkops_lvl_checked) 5985 goto enable_auto_bkops; 5986 5987 err = ufshcd_get_bkops_status(hba, &curr_status); 5988 if (err) { 5989 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5990 __func__, err); 5991 goto out; 5992 } 5993 5994 /* 5995 * We are seeing that some devices are raising the urgent bkops 5996 * exception events even when BKOPS status doesn't indicate performace 5997 * impacted or critical. Handle these device by determining their urgent 5998 * bkops status at runtime. 5999 */ 6000 if (curr_status < BKOPS_STATUS_PERF_IMPACT) { 6001 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n", 6002 __func__, curr_status); 6003 /* update the current status as the urgent bkops level */ 6004 hba->urgent_bkops_lvl = curr_status; 6005 hba->is_urgent_bkops_lvl_checked = true; 6006 } 6007 6008 enable_auto_bkops: 6009 err = ufshcd_enable_auto_bkops(hba); 6010 out: 6011 if (err < 0) 6012 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", 6013 __func__, err); 6014 } 6015 __ufshcd_wb_toggle(struct ufs_hba * hba,bool set,enum flag_idn idn)6016 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn) 6017 { 6018 u8 index; 6019 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG : 6020 UPIU_QUERY_OPCODE_CLEAR_FLAG; 6021 6022 index = ufshcd_wb_get_query_index(hba); 6023 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL); 6024 } 6025 ufshcd_wb_toggle(struct ufs_hba * hba,bool enable)6026 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable) 6027 { 6028 int ret; 6029 6030 if (!ufshcd_is_wb_allowed(hba) || 6031 hba->dev_info.wb_enabled == enable) 6032 return 0; 6033 6034 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN); 6035 if (ret) { 6036 dev_err(hba->dev, "%s: Write Booster %s failed %d\n", 6037 __func__, enable ? "enabling" : "disabling", ret); 6038 return ret; 6039 } 6040 6041 hba->dev_info.wb_enabled = enable; 6042 dev_dbg(hba->dev, "%s: Write Booster %s\n", 6043 __func__, enable ? "enabled" : "disabled"); 6044 6045 return ret; 6046 } 6047 ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba * hba,bool enable)6048 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 6049 bool enable) 6050 { 6051 int ret; 6052 6053 ret = __ufshcd_wb_toggle(hba, enable, 6054 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8); 6055 if (ret) { 6056 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n", 6057 __func__, enable ? "enabling" : "disabling", ret); 6058 return; 6059 } 6060 dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n", 6061 __func__, enable ? "enabled" : "disabled"); 6062 } 6063 ufshcd_wb_toggle_buf_flush(struct ufs_hba * hba,bool enable)6064 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable) 6065 { 6066 int ret; 6067 6068 if (!ufshcd_is_wb_allowed(hba) || 6069 hba->dev_info.wb_buf_flush_enabled == enable) 6070 return 0; 6071 6072 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN); 6073 if (ret) { 6074 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n", 6075 __func__, enable ? "enabling" : "disabling", ret); 6076 return ret; 6077 } 6078 6079 hba->dev_info.wb_buf_flush_enabled = enable; 6080 dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n", 6081 __func__, enable ? "enabled" : "disabled"); 6082 6083 return ret; 6084 } 6085 ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba * hba,u32 avail_buf)6086 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba, 6087 u32 avail_buf) 6088 { 6089 u32 cur_buf; 6090 int ret; 6091 u8 index; 6092 6093 index = ufshcd_wb_get_query_index(hba); 6094 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6095 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE, 6096 index, 0, &cur_buf); 6097 if (ret) { 6098 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n", 6099 __func__, ret); 6100 return false; 6101 } 6102 6103 if (!cur_buf) { 6104 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n", 6105 cur_buf); 6106 return false; 6107 } 6108 /* Let it continue to flush when available buffer exceeds threshold */ 6109 return avail_buf < hba->vps->wb_flush_threshold; 6110 } 6111 ufshcd_wb_force_disable(struct ufs_hba * hba)6112 static void ufshcd_wb_force_disable(struct ufs_hba *hba) 6113 { 6114 if (ufshcd_is_wb_buf_flush_allowed(hba)) 6115 ufshcd_wb_toggle_buf_flush(hba, false); 6116 6117 ufshcd_wb_toggle_buf_flush_during_h8(hba, false); 6118 ufshcd_wb_toggle(hba, false); 6119 hba->caps &= ~UFSHCD_CAP_WB_EN; 6120 6121 dev_info(hba->dev, "%s: WB force disabled\n", __func__); 6122 } 6123 ufshcd_is_wb_buf_lifetime_available(struct ufs_hba * hba)6124 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba) 6125 { 6126 u32 lifetime; 6127 int ret; 6128 u8 index; 6129 6130 index = ufshcd_wb_get_query_index(hba); 6131 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6132 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST, 6133 index, 0, &lifetime); 6134 if (ret) { 6135 dev_err(hba->dev, 6136 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n", 6137 __func__, ret); 6138 return false; 6139 } 6140 6141 if (lifetime == UFS_WB_EXCEED_LIFETIME) { 6142 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n", 6143 __func__, lifetime); 6144 return false; 6145 } 6146 6147 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n", 6148 __func__, lifetime); 6149 6150 return true; 6151 } 6152 ufshcd_wb_need_flush(struct ufs_hba * hba)6153 static bool ufshcd_wb_need_flush(struct ufs_hba *hba) 6154 { 6155 int ret; 6156 u32 avail_buf; 6157 u8 index; 6158 6159 if (!ufshcd_is_wb_allowed(hba)) 6160 return false; 6161 6162 if (!ufshcd_is_wb_buf_lifetime_available(hba)) { 6163 ufshcd_wb_force_disable(hba); 6164 return false; 6165 } 6166 6167 /* 6168 * The ufs device needs the vcc to be ON to flush. 6169 * With user-space reduction enabled, it's enough to enable flush 6170 * by checking only the available buffer. The threshold 6171 * defined here is > 90% full. 6172 * With user-space preserved enabled, the current-buffer 6173 * should be checked too because the wb buffer size can reduce 6174 * when disk tends to be full. This info is provided by current 6175 * buffer (dCurrentWriteBoosterBufferSize). There's no point in 6176 * keeping vcc on when current buffer is empty. 6177 */ 6178 index = ufshcd_wb_get_query_index(hba); 6179 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6180 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE, 6181 index, 0, &avail_buf); 6182 if (ret) { 6183 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n", 6184 __func__, ret); 6185 return false; 6186 } 6187 6188 if (!hba->dev_info.b_presrv_uspc_en) 6189 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10); 6190 6191 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf); 6192 } 6193 ufshcd_rpm_dev_flush_recheck_work(struct work_struct * work)6194 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work) 6195 { 6196 struct ufs_hba *hba = container_of(to_delayed_work(work), 6197 struct ufs_hba, 6198 rpm_dev_flush_recheck_work); 6199 /* 6200 * To prevent unnecessary VCC power drain after device finishes 6201 * WriteBooster buffer flush or Auto BKOPs, force runtime resume 6202 * after a certain delay to recheck the threshold by next runtime 6203 * suspend. 6204 */ 6205 ufshcd_rpm_get_sync(hba); 6206 ufshcd_rpm_put_sync(hba); 6207 } 6208 6209 /** 6210 * ufshcd_exception_event_handler - handle exceptions raised by device 6211 * @work: pointer to work data 6212 * 6213 * Read bExceptionEventStatus attribute from the device and handle the 6214 * exception event accordingly. 6215 */ ufshcd_exception_event_handler(struct work_struct * work)6216 static void ufshcd_exception_event_handler(struct work_struct *work) 6217 { 6218 struct ufs_hba *hba; 6219 int err; 6220 u32 status = 0; 6221 hba = container_of(work, struct ufs_hba, eeh_work); 6222 6223 err = ufshcd_get_ee_status(hba, &status); 6224 if (err) { 6225 dev_err(hba->dev, "%s: failed to get exception status %d\n", 6226 __func__, err); 6227 return; 6228 } 6229 6230 trace_ufshcd_exception_event(hba, status); 6231 6232 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS) 6233 ufshcd_bkops_exception_event_handler(hba); 6234 6235 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP) 6236 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP); 6237 6238 if (status & hba->ee_drv_mask & MASK_EE_HEALTH_CRITICAL) { 6239 hba->critical_health_count++; 6240 sysfs_notify(&hba->dev->kobj, NULL, "critical_health"); 6241 } 6242 6243 ufs_debugfs_exception_event(hba, status); 6244 } 6245 6246 /* Complete requests that have door-bell cleared */ ufshcd_complete_requests(struct ufs_hba * hba,bool force_compl)6247 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl) 6248 { 6249 if (hba->mcq_enabled) 6250 ufshcd_mcq_compl_pending_transfer(hba, force_compl); 6251 else 6252 ufshcd_transfer_req_compl(hba); 6253 6254 ufshcd_tmc_handler(hba); 6255 } 6256 6257 /** 6258 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is 6259 * to recover from the DL NAC errors or not. 6260 * @hba: per-adapter instance 6261 * 6262 * Return: true if error handling is required, false otherwise. 6263 */ ufshcd_quirk_dl_nac_errors(struct ufs_hba * hba)6264 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba) 6265 { 6266 unsigned long flags; 6267 bool err_handling = true; 6268 6269 spin_lock_irqsave(hba->host->host_lock, flags); 6270 /* 6271 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the 6272 * device fatal error and/or DL NAC & REPLAY timeout errors. 6273 */ 6274 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR)) 6275 goto out; 6276 6277 if ((hba->saved_err & DEVICE_FATAL_ERROR) || 6278 ((hba->saved_err & UIC_ERROR) && 6279 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR))) 6280 goto out; 6281 6282 if ((hba->saved_err & UIC_ERROR) && 6283 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) { 6284 int err; 6285 /* 6286 * wait for 50ms to see if we can get any other errors or not. 6287 */ 6288 spin_unlock_irqrestore(hba->host->host_lock, flags); 6289 msleep(50); 6290 spin_lock_irqsave(hba->host->host_lock, flags); 6291 6292 /* 6293 * now check if we have got any other severe errors other than 6294 * DL NAC error? 6295 */ 6296 if ((hba->saved_err & INT_FATAL_ERRORS) || 6297 ((hba->saved_err & UIC_ERROR) && 6298 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR))) 6299 goto out; 6300 6301 /* 6302 * As DL NAC is the only error received so far, send out NOP 6303 * command to confirm if link is still active or not. 6304 * - If we don't get any response then do error recovery. 6305 * - If we get response then clear the DL NAC error bit. 6306 */ 6307 6308 spin_unlock_irqrestore(hba->host->host_lock, flags); 6309 err = ufshcd_verify_dev_init(hba); 6310 spin_lock_irqsave(hba->host->host_lock, flags); 6311 6312 if (err) 6313 goto out; 6314 6315 /* Link seems to be alive hence ignore the DL NAC errors */ 6316 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR) 6317 hba->saved_err &= ~UIC_ERROR; 6318 /* clear NAC error */ 6319 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6320 if (!hba->saved_uic_err) 6321 err_handling = false; 6322 } 6323 out: 6324 spin_unlock_irqrestore(hba->host->host_lock, flags); 6325 return err_handling; 6326 } 6327 6328 /* host lock must be held before calling this func */ ufshcd_is_saved_err_fatal(struct ufs_hba * hba)6329 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba) 6330 { 6331 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) || 6332 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)); 6333 } 6334 ufshcd_schedule_eh_work(struct ufs_hba * hba)6335 void ufshcd_schedule_eh_work(struct ufs_hba *hba) 6336 { 6337 lockdep_assert_held(hba->host->host_lock); 6338 6339 /* handle fatal errors only when link is not in error state */ 6340 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6341 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6342 ufshcd_is_saved_err_fatal(hba)) 6343 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL; 6344 else 6345 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL; 6346 queue_work(hba->eh_wq, &hba->eh_work); 6347 } 6348 } 6349 ufshcd_force_error_recovery(struct ufs_hba * hba)6350 static void ufshcd_force_error_recovery(struct ufs_hba *hba) 6351 { 6352 spin_lock_irq(hba->host->host_lock); 6353 hba->force_reset = true; 6354 ufshcd_schedule_eh_work(hba); 6355 spin_unlock_irq(hba->host->host_lock); 6356 } 6357 ufshcd_clk_scaling_allow(struct ufs_hba * hba,bool allow)6358 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow) 6359 { 6360 mutex_lock(&hba->wb_mutex); 6361 down_write(&hba->clk_scaling_lock); 6362 hba->clk_scaling.is_allowed = allow; 6363 up_write(&hba->clk_scaling_lock); 6364 mutex_unlock(&hba->wb_mutex); 6365 } 6366 ufshcd_clk_scaling_suspend(struct ufs_hba * hba,bool suspend)6367 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend) 6368 { 6369 if (suspend) { 6370 if (hba->clk_scaling.is_enabled) 6371 ufshcd_suspend_clkscaling(hba); 6372 ufshcd_clk_scaling_allow(hba, false); 6373 } else { 6374 ufshcd_clk_scaling_allow(hba, true); 6375 if (hba->clk_scaling.is_enabled) 6376 ufshcd_resume_clkscaling(hba); 6377 } 6378 } 6379 ufshcd_err_handling_prepare(struct ufs_hba * hba)6380 static void ufshcd_err_handling_prepare(struct ufs_hba *hba) 6381 { 6382 ufshcd_rpm_get_sync(hba); 6383 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) || 6384 hba->is_sys_suspended) { 6385 enum ufs_pm_op pm_op; 6386 6387 /* 6388 * Don't assume anything of resume, if 6389 * resume fails, irq and clocks can be OFF, and powers 6390 * can be OFF or in LPM. 6391 */ 6392 ufshcd_setup_hba_vreg(hba, true); 6393 ufshcd_enable_irq(hba); 6394 ufshcd_setup_vreg(hba, true); 6395 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 6396 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 6397 ufshcd_hold(hba); 6398 if (!ufshcd_is_clkgating_allowed(hba)) 6399 ufshcd_setup_clocks(hba, true); 6400 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM; 6401 ufshcd_vops_resume(hba, pm_op); 6402 } else { 6403 ufshcd_hold(hba); 6404 if (ufshcd_is_clkscaling_supported(hba) && 6405 hba->clk_scaling.is_enabled) 6406 ufshcd_suspend_clkscaling(hba); 6407 ufshcd_clk_scaling_allow(hba, false); 6408 } 6409 /* Wait for ongoing ufshcd_queuecommand() calls to finish. */ 6410 blk_mq_quiesce_tagset(&hba->host->tag_set); 6411 cancel_work_sync(&hba->eeh_work); 6412 } 6413 ufshcd_err_handling_unprepare(struct ufs_hba * hba)6414 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba) 6415 { 6416 blk_mq_unquiesce_tagset(&hba->host->tag_set); 6417 ufshcd_release(hba); 6418 if (ufshcd_is_clkscaling_supported(hba)) 6419 ufshcd_clk_scaling_suspend(hba, false); 6420 ufshcd_rpm_put(hba); 6421 } 6422 ufshcd_err_handling_should_stop(struct ufs_hba * hba)6423 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba) 6424 { 6425 return (!hba->is_powered || hba->shutting_down || 6426 !hba->ufs_device_wlun || 6427 hba->ufshcd_state == UFSHCD_STATE_ERROR || 6428 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset || 6429 ufshcd_is_link_broken(hba)))); 6430 } 6431 6432 #ifdef CONFIG_PM ufshcd_recover_pm_error(struct ufs_hba * hba)6433 static void ufshcd_recover_pm_error(struct ufs_hba *hba) 6434 { 6435 struct Scsi_Host *shost = hba->host; 6436 struct scsi_device *sdev; 6437 struct request_queue *q; 6438 int ret; 6439 6440 hba->is_sys_suspended = false; 6441 /* 6442 * Set RPM status of wlun device to RPM_ACTIVE, 6443 * this also clears its runtime error. 6444 */ 6445 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev); 6446 6447 /* hba device might have a runtime error otherwise */ 6448 if (ret) 6449 ret = pm_runtime_set_active(hba->dev); 6450 /* 6451 * If wlun device had runtime error, we also need to resume those 6452 * consumer scsi devices in case any of them has failed to be 6453 * resumed due to supplier runtime resume failure. This is to unblock 6454 * blk_queue_enter in case there are bios waiting inside it. 6455 */ 6456 if (!ret) { 6457 shost_for_each_device(sdev, shost) { 6458 q = sdev->request_queue; 6459 if (q->dev && (q->rpm_status == RPM_SUSPENDED || 6460 q->rpm_status == RPM_SUSPENDING)) 6461 pm_request_resume(q->dev); 6462 } 6463 } 6464 } 6465 #else ufshcd_recover_pm_error(struct ufs_hba * hba)6466 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba) 6467 { 6468 } 6469 #endif 6470 ufshcd_is_pwr_mode_restore_needed(struct ufs_hba * hba)6471 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba) 6472 { 6473 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info; 6474 u32 mode; 6475 6476 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode); 6477 6478 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK)) 6479 return true; 6480 6481 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK)) 6482 return true; 6483 6484 return false; 6485 } 6486 ufshcd_abort_one(struct request * rq,void * priv)6487 static bool ufshcd_abort_one(struct request *rq, void *priv) 6488 { 6489 int *ret = priv; 6490 u32 tag = rq->tag; 6491 struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq); 6492 struct scsi_device *sdev = cmd->device; 6493 struct Scsi_Host *shost = sdev->host; 6494 struct ufs_hba *hba = shost_priv(shost); 6495 6496 *ret = ufshcd_try_to_abort_task(hba, tag); 6497 dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag, 6498 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1, 6499 *ret ? "failed" : "succeeded"); 6500 6501 return *ret == 0; 6502 } 6503 6504 /** 6505 * ufshcd_abort_all - Abort all pending commands. 6506 * @hba: Host bus adapter pointer. 6507 * 6508 * Return: true if and only if the host controller needs to be reset. 6509 */ ufshcd_abort_all(struct ufs_hba * hba)6510 static bool ufshcd_abort_all(struct ufs_hba *hba) 6511 { 6512 int tag, ret = 0; 6513 6514 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret); 6515 if (ret) 6516 goto out; 6517 6518 /* Clear pending task management requests */ 6519 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) { 6520 ret = ufshcd_clear_tm_cmd(hba, tag); 6521 if (ret) 6522 goto out; 6523 } 6524 6525 out: 6526 /* Complete the requests that are cleared by s/w */ 6527 ufshcd_complete_requests(hba, false); 6528 6529 return ret != 0; 6530 } 6531 6532 /** 6533 * ufshcd_err_handler - handle UFS errors that require s/w attention 6534 * @work: pointer to work structure 6535 */ ufshcd_err_handler(struct work_struct * work)6536 static void ufshcd_err_handler(struct work_struct *work) 6537 { 6538 int retries = MAX_ERR_HANDLER_RETRIES; 6539 struct ufs_hba *hba; 6540 unsigned long flags; 6541 bool needs_restore; 6542 bool needs_reset; 6543 int pmc_err; 6544 6545 hba = container_of(work, struct ufs_hba, eh_work); 6546 6547 dev_info(hba->dev, 6548 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n", 6549 __func__, ufshcd_state_name[hba->ufshcd_state], 6550 hba->is_powered, hba->shutting_down, hba->saved_err, 6551 hba->saved_uic_err, hba->force_reset, 6552 ufshcd_is_link_broken(hba) ? "; link is broken" : ""); 6553 6554 down(&hba->host_sem); 6555 spin_lock_irqsave(hba->host->host_lock, flags); 6556 if (ufshcd_err_handling_should_stop(hba)) { 6557 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6558 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6559 spin_unlock_irqrestore(hba->host->host_lock, flags); 6560 up(&hba->host_sem); 6561 return; 6562 } 6563 ufshcd_set_eh_in_progress(hba); 6564 spin_unlock_irqrestore(hba->host->host_lock, flags); 6565 ufshcd_err_handling_prepare(hba); 6566 /* Complete requests that have door-bell cleared by h/w */ 6567 ufshcd_complete_requests(hba, false); 6568 spin_lock_irqsave(hba->host->host_lock, flags); 6569 again: 6570 needs_restore = false; 6571 needs_reset = false; 6572 6573 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6574 hba->ufshcd_state = UFSHCD_STATE_RESET; 6575 /* 6576 * A full reset and restore might have happened after preparation 6577 * is finished, double check whether we should stop. 6578 */ 6579 if (ufshcd_err_handling_should_stop(hba)) 6580 goto skip_err_handling; 6581 6582 if ((hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) && 6583 !hba->force_reset) { 6584 bool ret; 6585 6586 spin_unlock_irqrestore(hba->host->host_lock, flags); 6587 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */ 6588 ret = ufshcd_quirk_dl_nac_errors(hba); 6589 spin_lock_irqsave(hba->host->host_lock, flags); 6590 if (!ret && ufshcd_err_handling_should_stop(hba)) 6591 goto skip_err_handling; 6592 } 6593 6594 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6595 (hba->saved_uic_err && 6596 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6597 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR); 6598 6599 spin_unlock_irqrestore(hba->host->host_lock, flags); 6600 ufshcd_print_host_state(hba); 6601 ufshcd_print_pwr_info(hba); 6602 ufshcd_print_evt_hist(hba); 6603 ufshcd_print_tmrs(hba, hba->outstanding_tasks); 6604 ufshcd_print_trs_all(hba, pr_prdt); 6605 spin_lock_irqsave(hba->host->host_lock, flags); 6606 } 6607 6608 /* 6609 * if host reset is required then skip clearing the pending 6610 * transfers forcefully because they will get cleared during 6611 * host reset and restore 6612 */ 6613 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6614 ufshcd_is_saved_err_fatal(hba) || 6615 ((hba->saved_err & UIC_ERROR) && 6616 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR | 6617 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) { 6618 needs_reset = true; 6619 goto do_reset; 6620 } 6621 6622 /* 6623 * If LINERESET was caught, UFS might have been put to PWM mode, 6624 * check if power mode restore is needed. 6625 */ 6626 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) { 6627 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6628 if (!hba->saved_uic_err) 6629 hba->saved_err &= ~UIC_ERROR; 6630 spin_unlock_irqrestore(hba->host->host_lock, flags); 6631 if (ufshcd_is_pwr_mode_restore_needed(hba)) 6632 needs_restore = true; 6633 spin_lock_irqsave(hba->host->host_lock, flags); 6634 if (!hba->saved_err && !needs_restore) 6635 goto skip_err_handling; 6636 } 6637 6638 hba->silence_err_logs = true; 6639 /* release lock as clear command might sleep */ 6640 spin_unlock_irqrestore(hba->host->host_lock, flags); 6641 6642 needs_reset = ufshcd_abort_all(hba); 6643 6644 spin_lock_irqsave(hba->host->host_lock, flags); 6645 hba->silence_err_logs = false; 6646 if (needs_reset) 6647 goto do_reset; 6648 6649 /* 6650 * After all reqs and tasks are cleared from doorbell, 6651 * now it is safe to retore power mode. 6652 */ 6653 if (needs_restore) { 6654 spin_unlock_irqrestore(hba->host->host_lock, flags); 6655 /* 6656 * Hold the scaling lock just in case dev cmds 6657 * are sent via bsg and/or sysfs. 6658 */ 6659 down_write(&hba->clk_scaling_lock); 6660 hba->force_pmc = true; 6661 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info)); 6662 if (pmc_err) { 6663 needs_reset = true; 6664 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n", 6665 __func__, pmc_err); 6666 } 6667 hba->force_pmc = false; 6668 ufshcd_print_pwr_info(hba); 6669 up_write(&hba->clk_scaling_lock); 6670 spin_lock_irqsave(hba->host->host_lock, flags); 6671 } 6672 6673 do_reset: 6674 /* Fatal errors need reset */ 6675 if (needs_reset) { 6676 int err; 6677 6678 hba->force_reset = false; 6679 spin_unlock_irqrestore(hba->host->host_lock, flags); 6680 err = ufshcd_reset_and_restore(hba); 6681 if (err) 6682 dev_err(hba->dev, "%s: reset and restore failed with err %d\n", 6683 __func__, err); 6684 else 6685 ufshcd_recover_pm_error(hba); 6686 spin_lock_irqsave(hba->host->host_lock, flags); 6687 } 6688 6689 skip_err_handling: 6690 if (!needs_reset) { 6691 if (hba->ufshcd_state == UFSHCD_STATE_RESET) 6692 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6693 if (hba->saved_err || hba->saved_uic_err) 6694 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x", 6695 __func__, hba->saved_err, hba->saved_uic_err); 6696 } 6697 /* Exit in an operational state or dead */ 6698 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 6699 hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6700 if (--retries) 6701 goto again; 6702 hba->ufshcd_state = UFSHCD_STATE_ERROR; 6703 } 6704 ufshcd_clear_eh_in_progress(hba); 6705 spin_unlock_irqrestore(hba->host->host_lock, flags); 6706 ufshcd_err_handling_unprepare(hba); 6707 up(&hba->host_sem); 6708 6709 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__, 6710 ufshcd_state_name[hba->ufshcd_state]); 6711 } 6712 6713 /** 6714 * ufshcd_update_uic_error - check and set fatal UIC error flags. 6715 * @hba: per-adapter instance 6716 * 6717 * Return: 6718 * IRQ_HANDLED - If interrupt is valid 6719 * IRQ_NONE - If invalid interrupt 6720 */ ufshcd_update_uic_error(struct ufs_hba * hba)6721 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba) 6722 { 6723 u32 reg; 6724 irqreturn_t retval = IRQ_NONE; 6725 6726 /* PHY layer error */ 6727 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 6728 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) && 6729 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) { 6730 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg); 6731 /* 6732 * To know whether this error is fatal or not, DB timeout 6733 * must be checked but this error is handled separately. 6734 */ 6735 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK) 6736 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", 6737 __func__); 6738 6739 /* Got a LINERESET indication. */ 6740 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) { 6741 struct uic_command *cmd = NULL; 6742 6743 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR; 6744 if (hba->uic_async_done && hba->active_uic_cmd) 6745 cmd = hba->active_uic_cmd; 6746 /* 6747 * Ignore the LINERESET during power mode change 6748 * operation via DME_SET command. 6749 */ 6750 if (cmd && (cmd->command == UIC_CMD_DME_SET)) 6751 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6752 } 6753 retval |= IRQ_HANDLED; 6754 } 6755 6756 /* PA_INIT_ERROR is fatal and needs UIC reset */ 6757 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); 6758 if ((reg & UIC_DATA_LINK_LAYER_ERROR) && 6759 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) { 6760 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg); 6761 6762 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 6763 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR; 6764 else if (hba->dev_quirks & 6765 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6766 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) 6767 hba->uic_error |= 6768 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6769 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) 6770 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; 6771 } 6772 retval |= IRQ_HANDLED; 6773 } 6774 6775 /* UIC NL/TL/DME errors needs software retry */ 6776 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); 6777 if ((reg & UIC_NETWORK_LAYER_ERROR) && 6778 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) { 6779 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg); 6780 hba->uic_error |= UFSHCD_UIC_NL_ERROR; 6781 retval |= IRQ_HANDLED; 6782 } 6783 6784 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); 6785 if ((reg & UIC_TRANSPORT_LAYER_ERROR) && 6786 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) { 6787 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg); 6788 hba->uic_error |= UFSHCD_UIC_TL_ERROR; 6789 retval |= IRQ_HANDLED; 6790 } 6791 6792 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); 6793 if ((reg & UIC_DME_ERROR) && 6794 (reg & UIC_DME_ERROR_CODE_MASK)) { 6795 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg); 6796 hba->uic_error |= UFSHCD_UIC_DME_ERROR; 6797 retval |= IRQ_HANDLED; 6798 } 6799 6800 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", 6801 __func__, hba->uic_error); 6802 return retval; 6803 } 6804 6805 /** 6806 * ufshcd_check_errors - Check for errors that need s/w attention 6807 * @hba: per-adapter instance 6808 * @intr_status: interrupt status generated by the controller 6809 * 6810 * Return: 6811 * IRQ_HANDLED - If interrupt is valid 6812 * IRQ_NONE - If invalid interrupt 6813 */ ufshcd_check_errors(struct ufs_hba * hba,u32 intr_status)6814 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status) 6815 { 6816 bool queue_eh_work = false; 6817 irqreturn_t retval = IRQ_NONE; 6818 6819 spin_lock(hba->host->host_lock); 6820 hba->errors |= UFSHCD_ERROR_MASK & intr_status; 6821 6822 if (hba->errors & INT_FATAL_ERRORS) { 6823 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR, 6824 hba->errors); 6825 queue_eh_work = true; 6826 } 6827 6828 if (hba->errors & UIC_ERROR) { 6829 hba->uic_error = 0; 6830 retval = ufshcd_update_uic_error(hba); 6831 if (hba->uic_error) 6832 queue_eh_work = true; 6833 } 6834 6835 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) { 6836 dev_err(hba->dev, 6837 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n", 6838 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ? 6839 "Enter" : "Exit", 6840 hba->errors, ufshcd_get_upmcrs(hba)); 6841 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR, 6842 hba->errors); 6843 ufshcd_set_link_broken(hba); 6844 queue_eh_work = true; 6845 } 6846 6847 if (queue_eh_work) { 6848 /* 6849 * update the transfer error masks to sticky bits, let's do this 6850 * irrespective of current ufshcd_state. 6851 */ 6852 hba->saved_err |= hba->errors; 6853 hba->saved_uic_err |= hba->uic_error; 6854 6855 /* dump controller state before resetting */ 6856 if ((hba->saved_err & 6857 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6858 (hba->saved_uic_err && 6859 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6860 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n", 6861 __func__, hba->saved_err, 6862 hba->saved_uic_err); 6863 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, 6864 "host_regs: "); 6865 ufshcd_print_pwr_info(hba); 6866 } 6867 ufshcd_schedule_eh_work(hba); 6868 retval |= IRQ_HANDLED; 6869 } 6870 /* 6871 * if (!queue_eh_work) - 6872 * Other errors are either non-fatal where host recovers 6873 * itself without s/w intervention or errors that will be 6874 * handled by the SCSI core layer. 6875 */ 6876 hba->errors = 0; 6877 hba->uic_error = 0; 6878 spin_unlock(hba->host->host_lock); 6879 return retval; 6880 } 6881 6882 /** 6883 * ufshcd_tmc_handler - handle task management function completion 6884 * @hba: per adapter instance 6885 * 6886 * Return: 6887 * IRQ_HANDLED - If interrupt is valid 6888 * IRQ_NONE - If invalid interrupt 6889 */ ufshcd_tmc_handler(struct ufs_hba * hba)6890 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba) 6891 { 6892 unsigned long flags, pending, issued; 6893 irqreturn_t ret = IRQ_NONE; 6894 int tag; 6895 6896 spin_lock_irqsave(hba->host->host_lock, flags); 6897 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 6898 issued = hba->outstanding_tasks & ~pending; 6899 for_each_set_bit(tag, &issued, hba->nutmrs) { 6900 struct request *req = hba->tmf_rqs[tag]; 6901 struct completion *c = req->end_io_data; 6902 6903 complete(c); 6904 ret = IRQ_HANDLED; 6905 } 6906 spin_unlock_irqrestore(hba->host->host_lock, flags); 6907 6908 return ret; 6909 } 6910 6911 /** 6912 * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events 6913 * @hba: per adapter instance 6914 * 6915 * Return: IRQ_HANDLED if interrupt is handled. 6916 */ ufshcd_handle_mcq_cq_events(struct ufs_hba * hba)6917 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba) 6918 { 6919 struct ufs_hw_queue *hwq; 6920 unsigned long outstanding_cqs; 6921 unsigned int nr_queues; 6922 int i, ret; 6923 u32 events; 6924 6925 ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs); 6926 if (ret) 6927 outstanding_cqs = (1U << hba->nr_hw_queues) - 1; 6928 6929 /* Exclude the poll queues */ 6930 nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 6931 for_each_set_bit(i, &outstanding_cqs, nr_queues) { 6932 hwq = &hba->uhq[i]; 6933 6934 events = ufshcd_mcq_read_cqis(hba, i); 6935 if (events) 6936 ufshcd_mcq_write_cqis(hba, events, i); 6937 6938 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS) 6939 ufshcd_mcq_poll_cqe_lock(hba, hwq); 6940 } 6941 6942 return IRQ_HANDLED; 6943 } 6944 6945 /** 6946 * ufshcd_sl_intr - Interrupt service routine 6947 * @hba: per adapter instance 6948 * @intr_status: contains interrupts generated by the controller 6949 * 6950 * Return: 6951 * IRQ_HANDLED - If interrupt is valid 6952 * IRQ_NONE - If invalid interrupt 6953 */ ufshcd_sl_intr(struct ufs_hba * hba,u32 intr_status)6954 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) 6955 { 6956 irqreturn_t retval = IRQ_NONE; 6957 6958 if (intr_status & UFSHCD_UIC_MASK) 6959 retval |= ufshcd_uic_cmd_compl(hba, intr_status); 6960 6961 if (intr_status & UFSHCD_ERROR_MASK || hba->errors) 6962 retval |= ufshcd_check_errors(hba, intr_status); 6963 6964 if (intr_status & UTP_TASK_REQ_COMPL) 6965 retval |= ufshcd_tmc_handler(hba); 6966 6967 if (intr_status & UTP_TRANSFER_REQ_COMPL) 6968 retval |= ufshcd_transfer_req_compl(hba); 6969 6970 if (intr_status & MCQ_CQ_EVENT_STATUS) 6971 retval |= ufshcd_handle_mcq_cq_events(hba); 6972 6973 return retval; 6974 } 6975 6976 /** 6977 * ufshcd_intr - Main interrupt service routine 6978 * @irq: irq number 6979 * @__hba: pointer to adapter instance 6980 * 6981 * Return: 6982 * IRQ_HANDLED - If interrupt is valid 6983 * IRQ_NONE - If invalid interrupt 6984 */ ufshcd_intr(int irq,void * __hba)6985 static irqreturn_t ufshcd_intr(int irq, void *__hba) 6986 { 6987 u32 intr_status, enabled_intr_status = 0; 6988 irqreturn_t retval = IRQ_NONE; 6989 struct ufs_hba *hba = __hba; 6990 int retries = hba->nutrs; 6991 6992 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6993 hba->ufs_stats.last_intr_status = intr_status; 6994 hba->ufs_stats.last_intr_ts = local_clock(); 6995 6996 /* 6997 * There could be max of hba->nutrs reqs in flight and in worst case 6998 * if the reqs get finished 1 by 1 after the interrupt status is 6999 * read, make sure we handle them by checking the interrupt status 7000 * again in a loop until we process all of the reqs before returning. 7001 */ 7002 while (intr_status && retries--) { 7003 enabled_intr_status = 7004 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 7005 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 7006 if (enabled_intr_status) 7007 retval |= ufshcd_sl_intr(hba, enabled_intr_status); 7008 7009 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 7010 } 7011 7012 if (enabled_intr_status && retval == IRQ_NONE && 7013 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) || 7014 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) { 7015 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n", 7016 __func__, 7017 intr_status, 7018 hba->ufs_stats.last_intr_status, 7019 enabled_intr_status); 7020 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 7021 } 7022 7023 return retval; 7024 } 7025 ufshcd_clear_tm_cmd(struct ufs_hba * hba,int tag)7026 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag) 7027 { 7028 int err = 0; 7029 u32 mask = 1 << tag; 7030 7031 if (!test_bit(tag, &hba->outstanding_tasks)) 7032 goto out; 7033 7034 ufshcd_utmrl_clear(hba, tag); 7035 7036 /* poll for max. 1 sec to clear door bell register by h/w */ 7037 err = ufshcd_wait_for_register(hba, 7038 REG_UTP_TASK_REQ_DOOR_BELL, 7039 mask, 0, 1000, 1000); 7040 7041 dev_err(hba->dev, "Clearing task management function with tag %d %s\n", 7042 tag, err < 0 ? "failed" : "succeeded"); 7043 7044 out: 7045 return err; 7046 } 7047 __ufshcd_issue_tm_cmd(struct ufs_hba * hba,struct utp_task_req_desc * treq,u8 tm_function)7048 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba, 7049 struct utp_task_req_desc *treq, u8 tm_function) 7050 { 7051 struct request_queue *q = hba->tmf_queue; 7052 struct Scsi_Host *host = hba->host; 7053 DECLARE_COMPLETION_ONSTACK(wait); 7054 struct request *req; 7055 unsigned long flags; 7056 int task_tag, err; 7057 7058 /* 7059 * blk_mq_alloc_request() is used here only to get a free tag. 7060 */ 7061 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0); 7062 if (IS_ERR(req)) 7063 return PTR_ERR(req); 7064 7065 req->end_io_data = &wait; 7066 ufshcd_hold(hba); 7067 7068 spin_lock_irqsave(host->host_lock, flags); 7069 7070 task_tag = req->tag; 7071 hba->tmf_rqs[req->tag] = req; 7072 treq->upiu_req.req_header.task_tag = task_tag; 7073 7074 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq)); 7075 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function); 7076 7077 __set_bit(task_tag, &hba->outstanding_tasks); 7078 7079 spin_unlock_irqrestore(host->host_lock, flags); 7080 7081 /* send command to the controller */ 7082 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL); 7083 7084 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND); 7085 7086 /* wait until the task management command is completed */ 7087 err = wait_for_completion_io_timeout(&wait, 7088 msecs_to_jiffies(TM_CMD_TIMEOUT)); 7089 if (!err) { 7090 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR); 7091 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n", 7092 __func__, tm_function); 7093 if (ufshcd_clear_tm_cmd(hba, task_tag)) 7094 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n", 7095 __func__, task_tag); 7096 err = -ETIMEDOUT; 7097 } else { 7098 err = 0; 7099 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq)); 7100 7101 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP); 7102 } 7103 7104 spin_lock_irqsave(hba->host->host_lock, flags); 7105 hba->tmf_rqs[req->tag] = NULL; 7106 __clear_bit(task_tag, &hba->outstanding_tasks); 7107 spin_unlock_irqrestore(hba->host->host_lock, flags); 7108 7109 ufshcd_release(hba); 7110 blk_mq_free_request(req); 7111 7112 return err; 7113 } 7114 7115 /** 7116 * ufshcd_issue_tm_cmd - issues task management commands to controller 7117 * @hba: per adapter instance 7118 * @lun_id: LUN ID to which TM command is sent 7119 * @task_id: task ID to which the TM command is applicable 7120 * @tm_function: task management function opcode 7121 * @tm_response: task management service response return value 7122 * 7123 * Return: non-zero value on error, zero on success. 7124 */ ufshcd_issue_tm_cmd(struct ufs_hba * hba,int lun_id,int task_id,u8 tm_function,u8 * tm_response)7125 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id, 7126 u8 tm_function, u8 *tm_response) 7127 { 7128 struct utp_task_req_desc treq = { }; 7129 enum utp_ocs ocs_value; 7130 int err; 7131 7132 /* Configure task request descriptor */ 7133 treq.header.interrupt = 1; 7134 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7135 7136 /* Configure task request UPIU */ 7137 treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ; 7138 treq.upiu_req.req_header.lun = lun_id; 7139 treq.upiu_req.req_header.tm_function = tm_function; 7140 7141 /* 7142 * The host shall provide the same value for LUN field in the basic 7143 * header and for Input Parameter. 7144 */ 7145 treq.upiu_req.input_param1 = cpu_to_be32(lun_id); 7146 treq.upiu_req.input_param2 = cpu_to_be32(task_id); 7147 7148 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function); 7149 if (err == -ETIMEDOUT) 7150 return err; 7151 7152 ocs_value = treq.header.ocs & MASK_OCS; 7153 if (ocs_value != OCS_SUCCESS) 7154 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", 7155 __func__, ocs_value); 7156 else if (tm_response) 7157 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) & 7158 MASK_TM_SERVICE_RESP; 7159 return err; 7160 } 7161 7162 /** 7163 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests 7164 * @hba: per-adapter instance 7165 * @req_upiu: upiu request 7166 * @rsp_upiu: upiu reply 7167 * @desc_buff: pointer to descriptor buffer, NULL if NA 7168 * @buff_len: descriptor size, 0 if NA 7169 * @cmd_type: specifies the type (NOP, Query...) 7170 * @desc_op: descriptor operation 7171 * 7172 * Those type of requests uses UTP Transfer Request Descriptor - utrd. 7173 * Therefore, it "rides" the device management infrastructure: uses its tag and 7174 * tasks work queues. 7175 * 7176 * Since there is only one available tag for device management commands, 7177 * the caller is expected to hold the hba->dev_cmd.lock mutex. 7178 * 7179 * Return: 0 upon success; < 0 upon failure. 7180 */ ufshcd_issue_devman_upiu_cmd(struct ufs_hba * hba,struct utp_upiu_req * req_upiu,struct utp_upiu_req * rsp_upiu,u8 * desc_buff,int * buff_len,enum dev_cmd_type cmd_type,enum query_opcode desc_op)7181 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba, 7182 struct utp_upiu_req *req_upiu, 7183 struct utp_upiu_req *rsp_upiu, 7184 u8 *desc_buff, int *buff_len, 7185 enum dev_cmd_type cmd_type, 7186 enum query_opcode desc_op) 7187 { 7188 const u32 tag = hba->reserved_slot; 7189 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7190 int err = 0; 7191 u8 upiu_flags; 7192 7193 /* Protects use of hba->reserved_slot. */ 7194 lockdep_assert_held(&hba->dev_cmd.lock); 7195 7196 ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag); 7197 7198 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0); 7199 7200 /* update the task tag in the request upiu */ 7201 req_upiu->header.task_tag = tag; 7202 7203 /* just copy the upiu request as it is */ 7204 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7205 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) { 7206 /* The Data Segment Area is optional depending upon the query 7207 * function value. for WRITE DESCRIPTOR, the data segment 7208 * follows right after the tsf. 7209 */ 7210 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len); 7211 *buff_len = 0; 7212 } 7213 7214 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7215 7216 /* 7217 * ignore the returning value here - ufshcd_check_query_response is 7218 * bound to fail since dev_cmd.query and dev_cmd.type were left empty. 7219 * read the response directly ignoring all errors. 7220 */ 7221 ufshcd_issue_dev_cmd(hba, lrbp, tag, QUERY_REQ_TIMEOUT); 7222 7223 /* just copy the upiu response as it is */ 7224 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7225 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) { 7226 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu); 7227 u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 7228 .data_segment_length); 7229 7230 if (*buff_len >= resp_len) { 7231 memcpy(desc_buff, descp, resp_len); 7232 *buff_len = resp_len; 7233 } else { 7234 dev_warn(hba->dev, 7235 "%s: rsp size %d is bigger than buffer size %d", 7236 __func__, resp_len, *buff_len); 7237 *buff_len = 0; 7238 err = -EINVAL; 7239 } 7240 } 7241 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 7242 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 7243 7244 return err; 7245 } 7246 7247 /** 7248 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands 7249 * @hba: per-adapter instance 7250 * @req_upiu: upiu request 7251 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands 7252 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target 7253 * @desc_buff: pointer to descriptor buffer, NULL if NA 7254 * @buff_len: descriptor size, 0 if NA 7255 * @desc_op: descriptor operation 7256 * 7257 * Supports UTP Transfer requests (nop and query), and UTP Task 7258 * Management requests. 7259 * It is up to the caller to fill the upiu conent properly, as it will 7260 * be copied without any further input validations. 7261 * 7262 * Return: 0 upon success; < 0 upon failure. 7263 */ ufshcd_exec_raw_upiu_cmd(struct ufs_hba * hba,struct utp_upiu_req * req_upiu,struct utp_upiu_req * rsp_upiu,enum upiu_request_transaction msgcode,u8 * desc_buff,int * buff_len,enum query_opcode desc_op)7264 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 7265 struct utp_upiu_req *req_upiu, 7266 struct utp_upiu_req *rsp_upiu, 7267 enum upiu_request_transaction msgcode, 7268 u8 *desc_buff, int *buff_len, 7269 enum query_opcode desc_op) 7270 { 7271 int err; 7272 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY; 7273 struct utp_task_req_desc treq = { }; 7274 enum utp_ocs ocs_value; 7275 u8 tm_f = req_upiu->header.tm_function; 7276 7277 switch (msgcode) { 7278 case UPIU_TRANSACTION_NOP_OUT: 7279 cmd_type = DEV_CMD_TYPE_NOP; 7280 fallthrough; 7281 case UPIU_TRANSACTION_QUERY_REQ: 7282 ufshcd_dev_man_lock(hba); 7283 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu, 7284 desc_buff, buff_len, 7285 cmd_type, desc_op); 7286 ufshcd_dev_man_unlock(hba); 7287 7288 break; 7289 case UPIU_TRANSACTION_TASK_REQ: 7290 treq.header.interrupt = 1; 7291 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7292 7293 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu)); 7294 7295 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f); 7296 if (err == -ETIMEDOUT) 7297 break; 7298 7299 ocs_value = treq.header.ocs & MASK_OCS; 7300 if (ocs_value != OCS_SUCCESS) { 7301 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__, 7302 ocs_value); 7303 break; 7304 } 7305 7306 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu)); 7307 7308 break; 7309 default: 7310 err = -EINVAL; 7311 7312 break; 7313 } 7314 7315 return err; 7316 } 7317 7318 /** 7319 * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request 7320 * @hba: per adapter instance 7321 * @req_upiu: upiu request 7322 * @rsp_upiu: upiu reply 7323 * @req_ehs: EHS field which contains Advanced RPMB Request Message 7324 * @rsp_ehs: EHS field which returns Advanced RPMB Response Message 7325 * @sg_cnt: The number of sg lists actually used 7326 * @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation 7327 * @dir: DMA direction 7328 * 7329 * Return: zero on success, non-zero on failure. 7330 */ ufshcd_advanced_rpmb_req_handler(struct ufs_hba * hba,struct utp_upiu_req * req_upiu,struct utp_upiu_req * rsp_upiu,struct ufs_ehs * req_ehs,struct ufs_ehs * rsp_ehs,int sg_cnt,struct scatterlist * sg_list,enum dma_data_direction dir)7331 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 7332 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs, 7333 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list, 7334 enum dma_data_direction dir) 7335 { 7336 const u32 tag = hba->reserved_slot; 7337 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7338 int err = 0; 7339 int result; 7340 u8 upiu_flags; 7341 u8 *ehs_data; 7342 u16 ehs_len; 7343 int ehs = (hba->capabilities & MASK_EHSLUTRD_SUPPORTED) ? 2 : 0; 7344 7345 /* Protects use of hba->reserved_slot. */ 7346 ufshcd_dev_man_lock(hba); 7347 7348 ufshcd_setup_dev_cmd(hba, lrbp, DEV_CMD_TYPE_RPMB, UFS_UPIU_RPMB_WLUN, tag); 7349 7350 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, ehs); 7351 7352 /* update the task tag */ 7353 req_upiu->header.task_tag = tag; 7354 7355 /* copy the UPIU(contains CDB) request as it is */ 7356 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7357 /* Copy EHS, starting with byte32, immediately after the CDB package */ 7358 memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs)); 7359 7360 if (dir != DMA_NONE && sg_list) 7361 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list); 7362 7363 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7364 7365 err = ufshcd_issue_dev_cmd(hba, lrbp, tag, ADVANCED_RPMB_REQ_TIMEOUT); 7366 7367 if (!err) { 7368 /* Just copy the upiu response as it is */ 7369 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7370 /* Get the response UPIU result */ 7371 result = (lrbp->ucd_rsp_ptr->header.response << 8) | 7372 lrbp->ucd_rsp_ptr->header.status; 7373 7374 ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length; 7375 /* 7376 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data 7377 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB 7378 * Message is 02h 7379 */ 7380 if (ehs_len == 2 && rsp_ehs) { 7381 /* 7382 * ucd_rsp_ptr points to a buffer with a length of 512 bytes 7383 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32 7384 */ 7385 ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE; 7386 memcpy(rsp_ehs, ehs_data, ehs_len * 32); 7387 } 7388 } 7389 7390 ufshcd_dev_man_unlock(hba); 7391 7392 return err ? : result; 7393 } 7394 7395 /** 7396 * ufshcd_eh_device_reset_handler() - Reset a single logical unit. 7397 * @cmd: SCSI command pointer 7398 * 7399 * Return: SUCCESS or FAILED. 7400 */ ufshcd_eh_device_reset_handler(struct scsi_cmnd * cmd)7401 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) 7402 { 7403 unsigned long flags, pending_reqs = 0, not_cleared = 0; 7404 struct Scsi_Host *host; 7405 struct ufs_hba *hba; 7406 struct ufs_hw_queue *hwq; 7407 struct ufshcd_lrb *lrbp; 7408 u32 pos, not_cleared_mask = 0; 7409 int err; 7410 u8 resp = 0xF, lun; 7411 7412 host = cmd->device->host; 7413 hba = shost_priv(host); 7414 7415 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 7416 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp); 7417 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7418 if (!err) 7419 err = resp; 7420 goto out; 7421 } 7422 7423 if (hba->mcq_enabled) { 7424 for (pos = 0; pos < hba->nutrs; pos++) { 7425 lrbp = &hba->lrb[pos]; 7426 if (ufshcd_cmd_inflight(lrbp->cmd) && 7427 lrbp->lun == lun) { 7428 ufshcd_clear_cmd(hba, pos); 7429 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 7430 ufshcd_mcq_poll_cqe_lock(hba, hwq); 7431 } 7432 } 7433 err = 0; 7434 goto out; 7435 } 7436 7437 /* clear the commands that were pending for corresponding LUN */ 7438 spin_lock_irqsave(&hba->outstanding_lock, flags); 7439 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) 7440 if (hba->lrb[pos].lun == lun) 7441 __set_bit(pos, &pending_reqs); 7442 hba->outstanding_reqs &= ~pending_reqs; 7443 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7444 7445 for_each_set_bit(pos, &pending_reqs, hba->nutrs) { 7446 if (ufshcd_clear_cmd(hba, pos) < 0) { 7447 spin_lock_irqsave(&hba->outstanding_lock, flags); 7448 not_cleared = 1U << pos & 7449 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7450 hba->outstanding_reqs |= not_cleared; 7451 not_cleared_mask |= not_cleared; 7452 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7453 7454 dev_err(hba->dev, "%s: failed to clear request %d\n", 7455 __func__, pos); 7456 } 7457 } 7458 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask); 7459 7460 out: 7461 hba->req_abort_count = 0; 7462 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err); 7463 if (!err) { 7464 err = SUCCESS; 7465 } else { 7466 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7467 err = FAILED; 7468 } 7469 return err; 7470 } 7471 ufshcd_set_req_abort_skip(struct ufs_hba * hba,unsigned long bitmap)7472 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap) 7473 { 7474 struct ufshcd_lrb *lrbp; 7475 int tag; 7476 7477 for_each_set_bit(tag, &bitmap, hba->nutrs) { 7478 lrbp = &hba->lrb[tag]; 7479 lrbp->req_abort_skip = true; 7480 } 7481 } 7482 7483 /** 7484 * ufshcd_try_to_abort_task - abort a specific task 7485 * @hba: Pointer to adapter instance 7486 * @tag: Task tag/index to be aborted 7487 * 7488 * Abort the pending command in device by sending UFS_ABORT_TASK task management 7489 * command, and in host controller by clearing the door-bell register. There can 7490 * be race between controller sending the command to the device while abort is 7491 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is 7492 * really issued and then try to abort it. 7493 * 7494 * Return: zero on success, non-zero on failure. 7495 */ ufshcd_try_to_abort_task(struct ufs_hba * hba,int tag)7496 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag) 7497 { 7498 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7499 int err; 7500 int poll_cnt; 7501 u8 resp = 0xF; 7502 7503 for (poll_cnt = 100; poll_cnt; poll_cnt--) { 7504 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7505 UFS_QUERY_TASK, &resp); 7506 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) { 7507 /* cmd pending in the device */ 7508 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n", 7509 __func__, tag); 7510 break; 7511 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7512 /* 7513 * cmd not pending in the device, check if it is 7514 * in transition. 7515 */ 7516 dev_info( 7517 hba->dev, 7518 "%s: cmd with tag %d not pending in the device.\n", 7519 __func__, tag); 7520 if (!ufshcd_cmd_inflight(lrbp->cmd)) { 7521 dev_info(hba->dev, 7522 "%s: cmd with tag=%d completed.\n", 7523 __func__, tag); 7524 return 0; 7525 } 7526 usleep_range(100, 200); 7527 } else { 7528 dev_err(hba->dev, 7529 "%s: no response from device. tag = %d, err %d\n", 7530 __func__, tag, err); 7531 return err ? : resp; 7532 } 7533 } 7534 7535 if (!poll_cnt) 7536 return -EBUSY; 7537 7538 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7539 UFS_ABORT_TASK, &resp); 7540 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7541 if (!err) { 7542 err = resp; /* service response error */ 7543 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n", 7544 __func__, tag, err); 7545 } 7546 return err; 7547 } 7548 7549 err = ufshcd_clear_cmd(hba, tag); 7550 if (err) 7551 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n", 7552 __func__, tag, err); 7553 7554 return err; 7555 } 7556 7557 /** 7558 * ufshcd_abort - scsi host template eh_abort_handler callback 7559 * @cmd: SCSI command pointer 7560 * 7561 * Return: SUCCESS or FAILED. 7562 */ ufshcd_abort(struct scsi_cmnd * cmd)7563 static int ufshcd_abort(struct scsi_cmnd *cmd) 7564 { 7565 struct Scsi_Host *host = cmd->device->host; 7566 struct ufs_hba *hba = shost_priv(host); 7567 int tag = scsi_cmd_to_rq(cmd)->tag; 7568 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7569 unsigned long flags; 7570 int err = FAILED; 7571 bool outstanding; 7572 u32 reg; 7573 7574 ufshcd_hold(hba); 7575 7576 if (!hba->mcq_enabled) { 7577 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7578 if (!test_bit(tag, &hba->outstanding_reqs)) { 7579 /* If command is already aborted/completed, return FAILED. */ 7580 dev_err(hba->dev, 7581 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n", 7582 __func__, tag, hba->outstanding_reqs, reg); 7583 goto release; 7584 } 7585 } 7586 7587 /* Print Transfer Request of aborted task */ 7588 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag); 7589 7590 /* 7591 * Print detailed info about aborted request. 7592 * As more than one request might get aborted at the same time, 7593 * print full information only for the first aborted request in order 7594 * to reduce repeated printouts. For other aborted requests only print 7595 * basic details. 7596 */ 7597 scsi_print_command(cmd); 7598 if (!hba->req_abort_count) { 7599 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag); 7600 ufshcd_print_evt_hist(hba); 7601 ufshcd_print_host_state(hba); 7602 ufshcd_print_pwr_info(hba); 7603 ufshcd_print_tr(hba, tag, true); 7604 } else { 7605 ufshcd_print_tr(hba, tag, false); 7606 } 7607 hba->req_abort_count++; 7608 7609 if (!hba->mcq_enabled && !(reg & (1 << tag))) { 7610 /* only execute this code in single doorbell mode */ 7611 dev_err(hba->dev, 7612 "%s: cmd was completed, but without a notifying intr, tag = %d", 7613 __func__, tag); 7614 __ufshcd_transfer_req_compl(hba, 1UL << tag); 7615 goto release; 7616 } 7617 7618 /* 7619 * Task abort to the device W-LUN is illegal. When this command 7620 * will fail, due to spec violation, scsi err handling next step 7621 * will be to send LU reset which, again, is a spec violation. 7622 * To avoid these unnecessary/illegal steps, first we clean up 7623 * the lrb taken by this cmd and re-set it in outstanding_reqs, 7624 * then queue the eh_work and bail. 7625 */ 7626 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) { 7627 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun); 7628 7629 spin_lock_irqsave(host->host_lock, flags); 7630 hba->force_reset = true; 7631 ufshcd_schedule_eh_work(hba); 7632 spin_unlock_irqrestore(host->host_lock, flags); 7633 goto release; 7634 } 7635 7636 if (hba->mcq_enabled) { 7637 /* MCQ mode. Branch off to handle abort for mcq mode */ 7638 err = ufshcd_mcq_abort(cmd); 7639 goto release; 7640 } 7641 7642 /* Skip task abort in case previous aborts failed and report failure */ 7643 if (lrbp->req_abort_skip) { 7644 dev_err(hba->dev, "%s: skipping abort\n", __func__); 7645 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7646 goto release; 7647 } 7648 7649 err = ufshcd_try_to_abort_task(hba, tag); 7650 if (err) { 7651 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7652 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7653 err = FAILED; 7654 goto release; 7655 } 7656 7657 /* 7658 * Clear the corresponding bit from outstanding_reqs since the command 7659 * has been aborted successfully. 7660 */ 7661 spin_lock_irqsave(&hba->outstanding_lock, flags); 7662 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs); 7663 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7664 7665 if (outstanding) 7666 ufshcd_release_scsi_cmd(hba, lrbp); 7667 7668 err = SUCCESS; 7669 7670 release: 7671 /* Matches the ufshcd_hold() call at the start of this function. */ 7672 ufshcd_release(hba); 7673 return err; 7674 } 7675 7676 /** 7677 * ufshcd_process_probe_result - Process the ufshcd_probe_hba() result. 7678 * @hba: UFS host controller instance. 7679 * @probe_start: time when the ufshcd_probe_hba() call started. 7680 * @ret: ufshcd_probe_hba() return value. 7681 */ ufshcd_process_probe_result(struct ufs_hba * hba,ktime_t probe_start,int ret)7682 static void ufshcd_process_probe_result(struct ufs_hba *hba, 7683 ktime_t probe_start, int ret) 7684 { 7685 unsigned long flags; 7686 7687 spin_lock_irqsave(hba->host->host_lock, flags); 7688 if (ret) 7689 hba->ufshcd_state = UFSHCD_STATE_ERROR; 7690 else if (hba->ufshcd_state == UFSHCD_STATE_RESET) 7691 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 7692 spin_unlock_irqrestore(hba->host->host_lock, flags); 7693 7694 trace_ufshcd_init(hba, ret, 7695 ktime_to_us(ktime_sub(ktime_get(), probe_start)), 7696 hba->curr_dev_pwr_mode, hba->uic_link_state); 7697 } 7698 7699 /** 7700 * ufshcd_host_reset_and_restore - reset and restore host controller 7701 * @hba: per-adapter instance 7702 * 7703 * Note that host controller reset may issue DME_RESET to 7704 * local and remote (device) Uni-Pro stack and the attributes 7705 * are reset to default state. 7706 * 7707 * Return: zero on success, non-zero on failure. 7708 */ ufshcd_host_reset_and_restore(struct ufs_hba * hba)7709 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba) 7710 { 7711 int err; 7712 7713 /* 7714 * Stop the host controller and complete the requests 7715 * cleared by h/w 7716 */ 7717 ufshcd_hba_stop(hba); 7718 hba->silence_err_logs = true; 7719 ufshcd_complete_requests(hba, true); 7720 hba->silence_err_logs = false; 7721 7722 /* scale up clocks to max frequency before full reinitialization */ 7723 ufshcd_scale_clks(hba, ULONG_MAX, true); 7724 7725 err = ufshcd_hba_enable(hba); 7726 7727 /* Establish the link again and restore the device */ 7728 if (!err) { 7729 ktime_t probe_start = ktime_get(); 7730 7731 err = ufshcd_device_init(hba, /*init_dev_params=*/false); 7732 if (!err) 7733 err = ufshcd_probe_hba(hba, false); 7734 ufshcd_process_probe_result(hba, probe_start, err); 7735 } 7736 7737 if (err) 7738 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err); 7739 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err); 7740 return err; 7741 } 7742 7743 /** 7744 * ufshcd_reset_and_restore - reset and re-initialize host/device 7745 * @hba: per-adapter instance 7746 * 7747 * Reset and recover device, host and re-establish link. This 7748 * is helpful to recover the communication in fatal error conditions. 7749 * 7750 * Return: zero on success, non-zero on failure. 7751 */ ufshcd_reset_and_restore(struct ufs_hba * hba)7752 static int ufshcd_reset_and_restore(struct ufs_hba *hba) 7753 { 7754 u32 saved_err = 0; 7755 u32 saved_uic_err = 0; 7756 int err = 0; 7757 unsigned long flags; 7758 int retries = MAX_HOST_RESET_RETRIES; 7759 7760 spin_lock_irqsave(hba->host->host_lock, flags); 7761 do { 7762 /* 7763 * This is a fresh start, cache and clear saved error first, 7764 * in case new error generated during reset and restore. 7765 */ 7766 saved_err |= hba->saved_err; 7767 saved_uic_err |= hba->saved_uic_err; 7768 hba->saved_err = 0; 7769 hba->saved_uic_err = 0; 7770 hba->force_reset = false; 7771 hba->ufshcd_state = UFSHCD_STATE_RESET; 7772 spin_unlock_irqrestore(hba->host->host_lock, flags); 7773 7774 /* Reset the attached device */ 7775 ufshcd_device_reset(hba); 7776 7777 err = ufshcd_host_reset_and_restore(hba); 7778 7779 spin_lock_irqsave(hba->host->host_lock, flags); 7780 if (err) 7781 continue; 7782 /* Do not exit unless operational or dead */ 7783 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 7784 hba->ufshcd_state != UFSHCD_STATE_ERROR && 7785 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL) 7786 err = -EAGAIN; 7787 } while (err && --retries); 7788 7789 /* 7790 * Inform scsi mid-layer that we did reset and allow to handle 7791 * Unit Attention properly. 7792 */ 7793 scsi_report_bus_reset(hba->host, 0); 7794 if (err) { 7795 hba->ufshcd_state = UFSHCD_STATE_ERROR; 7796 hba->saved_err |= saved_err; 7797 hba->saved_uic_err |= saved_uic_err; 7798 } 7799 spin_unlock_irqrestore(hba->host->host_lock, flags); 7800 7801 return err; 7802 } 7803 7804 /** 7805 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer 7806 * @cmd: SCSI command pointer 7807 * 7808 * Return: SUCCESS or FAILED. 7809 */ ufshcd_eh_host_reset_handler(struct scsi_cmnd * cmd)7810 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd) 7811 { 7812 int err = SUCCESS; 7813 unsigned long flags; 7814 struct ufs_hba *hba; 7815 7816 hba = shost_priv(cmd->device->host); 7817 7818 /* 7819 * If runtime PM sent SSU and got a timeout, scsi_error_handler is 7820 * stuck in this function waiting for flush_work(&hba->eh_work). And 7821 * ufshcd_err_handler(eh_work) is stuck waiting for runtime PM. Do 7822 * ufshcd_link_recovery instead of eh_work to prevent deadlock. 7823 */ 7824 if (hba->pm_op_in_progress) { 7825 if (ufshcd_link_recovery(hba)) 7826 err = FAILED; 7827 7828 return err; 7829 } 7830 7831 spin_lock_irqsave(hba->host->host_lock, flags); 7832 hba->force_reset = true; 7833 ufshcd_schedule_eh_work(hba); 7834 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__); 7835 spin_unlock_irqrestore(hba->host->host_lock, flags); 7836 7837 flush_work(&hba->eh_work); 7838 7839 spin_lock_irqsave(hba->host->host_lock, flags); 7840 if (hba->ufshcd_state == UFSHCD_STATE_ERROR) 7841 err = FAILED; 7842 spin_unlock_irqrestore(hba->host->host_lock, flags); 7843 7844 return err; 7845 } 7846 7847 /** 7848 * ufshcd_get_max_icc_level - calculate the ICC level 7849 * @sup_curr_uA: max. current supported by the regulator 7850 * @start_scan: row at the desc table to start scan from 7851 * @buff: power descriptor buffer 7852 * 7853 * Return: calculated max ICC level for specific regulator. 7854 */ ufshcd_get_max_icc_level(int sup_curr_uA,u32 start_scan,const char * buff)7855 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, 7856 const char *buff) 7857 { 7858 int i; 7859 int curr_uA; 7860 u16 data; 7861 u16 unit; 7862 7863 for (i = start_scan; i >= 0; i--) { 7864 data = get_unaligned_be16(&buff[2 * i]); 7865 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >> 7866 ATTR_ICC_LVL_UNIT_OFFSET; 7867 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK; 7868 switch (unit) { 7869 case UFSHCD_NANO_AMP: 7870 curr_uA = curr_uA / 1000; 7871 break; 7872 case UFSHCD_MILI_AMP: 7873 curr_uA = curr_uA * 1000; 7874 break; 7875 case UFSHCD_AMP: 7876 curr_uA = curr_uA * 1000 * 1000; 7877 break; 7878 case UFSHCD_MICRO_AMP: 7879 default: 7880 break; 7881 } 7882 if (sup_curr_uA >= curr_uA) 7883 break; 7884 } 7885 if (i < 0) { 7886 i = 0; 7887 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i); 7888 } 7889 7890 return (u32)i; 7891 } 7892 7893 /** 7894 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level 7895 * In case regulators are not initialized we'll return 0 7896 * @hba: per-adapter instance 7897 * @desc_buf: power descriptor buffer to extract ICC levels from. 7898 * 7899 * Return: calculated ICC level. 7900 */ ufshcd_find_max_sup_active_icc_level(struct ufs_hba * hba,const u8 * desc_buf)7901 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba, 7902 const u8 *desc_buf) 7903 { 7904 u32 icc_level = 0; 7905 7906 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq || 7907 !hba->vreg_info.vccq2) { 7908 /* 7909 * Using dev_dbg to avoid messages during runtime PM to avoid 7910 * never-ending cycles of messages written back to storage by 7911 * user space causing runtime resume, causing more messages and 7912 * so on. 7913 */ 7914 dev_dbg(hba->dev, 7915 "%s: Regulator capability was not set, actvIccLevel=%d", 7916 __func__, icc_level); 7917 goto out; 7918 } 7919 7920 if (hba->vreg_info.vcc->max_uA) 7921 icc_level = ufshcd_get_max_icc_level( 7922 hba->vreg_info.vcc->max_uA, 7923 POWER_DESC_MAX_ACTV_ICC_LVLS - 1, 7924 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]); 7925 7926 if (hba->vreg_info.vccq->max_uA) 7927 icc_level = ufshcd_get_max_icc_level( 7928 hba->vreg_info.vccq->max_uA, 7929 icc_level, 7930 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]); 7931 7932 if (hba->vreg_info.vccq2->max_uA) 7933 icc_level = ufshcd_get_max_icc_level( 7934 hba->vreg_info.vccq2->max_uA, 7935 icc_level, 7936 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]); 7937 out: 7938 return icc_level; 7939 } 7940 ufshcd_set_active_icc_lvl(struct ufs_hba * hba)7941 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba) 7942 { 7943 int ret; 7944 u8 *desc_buf; 7945 u32 icc_level; 7946 7947 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 7948 if (!desc_buf) 7949 return; 7950 7951 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0, 7952 desc_buf, QUERY_DESC_MAX_SIZE); 7953 if (ret) { 7954 dev_err(hba->dev, 7955 "%s: Failed reading power descriptor ret = %d", 7956 __func__, ret); 7957 goto out; 7958 } 7959 7960 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf); 7961 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level); 7962 7963 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 7964 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level); 7965 7966 if (ret) 7967 dev_err(hba->dev, 7968 "%s: Failed configuring bActiveICCLevel = %d ret = %d", 7969 __func__, icc_level, ret); 7970 7971 out: 7972 kfree(desc_buf); 7973 } 7974 ufshcd_blk_pm_runtime_init(struct scsi_device * sdev)7975 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev) 7976 { 7977 struct Scsi_Host *shost = sdev->host; 7978 7979 scsi_autopm_get_device(sdev); 7980 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev); 7981 if (sdev->rpm_autosuspend) 7982 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev, 7983 shost->rpm_autosuspend_delay); 7984 scsi_autopm_put_device(sdev); 7985 } 7986 7987 /** 7988 * ufshcd_scsi_add_wlus - Adds required W-LUs 7989 * @hba: per-adapter instance 7990 * 7991 * UFS device specification requires the UFS devices to support 4 well known 7992 * logical units: 7993 * "REPORT_LUNS" (address: 01h) 7994 * "UFS Device" (address: 50h) 7995 * "RPMB" (address: 44h) 7996 * "BOOT" (address: 30h) 7997 * UFS device's power management needs to be controlled by "POWER CONDITION" 7998 * field of SSU (START STOP UNIT) command. But this "power condition" field 7999 * will take effect only when its sent to "UFS device" well known logical unit 8000 * hence we require the scsi_device instance to represent this logical unit in 8001 * order for the UFS host driver to send the SSU command for power management. 8002 * 8003 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory 8004 * Block) LU so user space process can control this LU. User space may also 8005 * want to have access to BOOT LU. 8006 * 8007 * This function adds scsi device instances for each of all well known LUs 8008 * (except "REPORT LUNS" LU). 8009 * 8010 * Return: zero on success (all required W-LUs are added successfully), 8011 * non-zero error value on failure (if failed to add any of the required W-LU). 8012 */ ufshcd_scsi_add_wlus(struct ufs_hba * hba)8013 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) 8014 { 8015 int ret = 0; 8016 struct scsi_device *sdev_boot, *sdev_rpmb; 8017 8018 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0, 8019 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL); 8020 if (IS_ERR(hba->ufs_device_wlun)) { 8021 ret = PTR_ERR(hba->ufs_device_wlun); 8022 hba->ufs_device_wlun = NULL; 8023 goto out; 8024 } 8025 scsi_device_put(hba->ufs_device_wlun); 8026 8027 sdev_rpmb = __scsi_add_device(hba->host, 0, 0, 8028 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL); 8029 if (IS_ERR(sdev_rpmb)) { 8030 ret = PTR_ERR(sdev_rpmb); 8031 goto remove_ufs_device_wlun; 8032 } 8033 ufshcd_blk_pm_runtime_init(sdev_rpmb); 8034 scsi_device_put(sdev_rpmb); 8035 8036 sdev_boot = __scsi_add_device(hba->host, 0, 0, 8037 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL); 8038 if (IS_ERR(sdev_boot)) { 8039 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__); 8040 } else { 8041 ufshcd_blk_pm_runtime_init(sdev_boot); 8042 scsi_device_put(sdev_boot); 8043 } 8044 goto out; 8045 8046 remove_ufs_device_wlun: 8047 scsi_remove_device(hba->ufs_device_wlun); 8048 out: 8049 return ret; 8050 } 8051 ufshcd_wb_probe(struct ufs_hba * hba,const u8 * desc_buf)8052 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf) 8053 { 8054 struct ufs_dev_info *dev_info = &hba->dev_info; 8055 u8 lun; 8056 u32 d_lu_wb_buf_alloc; 8057 u32 ext_ufs_feature; 8058 8059 if (!ufshcd_is_wb_allowed(hba)) 8060 return; 8061 8062 /* 8063 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or 8064 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES 8065 * enabled 8066 */ 8067 if (!(dev_info->wspecversion >= 0x310 || 8068 dev_info->wspecversion == 0x220 || 8069 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES))) 8070 goto wb_disabled; 8071 8072 ext_ufs_feature = get_unaligned_be32(desc_buf + 8073 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8074 8075 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP)) 8076 goto wb_disabled; 8077 8078 /* 8079 * WB may be supported but not configured while provisioning. The spec 8080 * says, in dedicated wb buffer mode, a max of 1 lun would have wb 8081 * buffer configured. 8082 */ 8083 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE]; 8084 8085 dev_info->b_presrv_uspc_en = 8086 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN]; 8087 8088 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) { 8089 if (!get_unaligned_be32(desc_buf + 8090 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS)) 8091 goto wb_disabled; 8092 } else { 8093 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) { 8094 d_lu_wb_buf_alloc = 0; 8095 ufshcd_read_unit_desc_param(hba, 8096 lun, 8097 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS, 8098 (u8 *)&d_lu_wb_buf_alloc, 8099 sizeof(d_lu_wb_buf_alloc)); 8100 if (d_lu_wb_buf_alloc) { 8101 dev_info->wb_dedicated_lu = lun; 8102 break; 8103 } 8104 } 8105 8106 if (!d_lu_wb_buf_alloc) 8107 goto wb_disabled; 8108 } 8109 8110 if (!ufshcd_is_wb_buf_lifetime_available(hba)) 8111 goto wb_disabled; 8112 8113 return; 8114 8115 wb_disabled: 8116 hba->caps &= ~UFSHCD_CAP_WB_EN; 8117 } 8118 ufshcd_temp_notif_probe(struct ufs_hba * hba,const u8 * desc_buf)8119 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf) 8120 { 8121 struct ufs_dev_info *dev_info = &hba->dev_info; 8122 u32 ext_ufs_feature; 8123 u8 mask = 0; 8124 8125 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300) 8126 return; 8127 8128 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8129 8130 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF) 8131 mask |= MASK_EE_TOO_LOW_TEMP; 8132 8133 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF) 8134 mask |= MASK_EE_TOO_HIGH_TEMP; 8135 8136 if (mask) { 8137 ufshcd_enable_ee(hba, mask); 8138 ufs_hwmon_probe(hba, mask); 8139 } 8140 } 8141 ufshcd_set_rtt(struct ufs_hba * hba)8142 static void ufshcd_set_rtt(struct ufs_hba *hba) 8143 { 8144 struct ufs_dev_info *dev_info = &hba->dev_info; 8145 u32 rtt = 0; 8146 u32 dev_rtt = 0; 8147 int host_rtt_cap = hba->vops && hba->vops->max_num_rtt ? 8148 hba->vops->max_num_rtt : hba->nortt; 8149 8150 /* RTT override makes sense only for UFS-4.0 and above */ 8151 if (dev_info->wspecversion < 0x400) 8152 return; 8153 8154 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8155 QUERY_ATTR_IDN_MAX_NUM_OF_RTT, 0, 0, &dev_rtt)) { 8156 dev_err(hba->dev, "failed reading bMaxNumOfRTT\n"); 8157 return; 8158 } 8159 8160 /* do not override if it was already written */ 8161 if (dev_rtt != DEFAULT_MAX_NUM_RTT) 8162 return; 8163 8164 rtt = min_t(int, dev_info->rtt_cap, host_rtt_cap); 8165 8166 if (rtt == dev_rtt) 8167 return; 8168 8169 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8170 QUERY_ATTR_IDN_MAX_NUM_OF_RTT, 0, 0, &rtt)) 8171 dev_err(hba->dev, "failed writing bMaxNumOfRTT\n"); 8172 } 8173 ufshcd_fixup_dev_quirks(struct ufs_hba * hba,const struct ufs_dev_quirk * fixups)8174 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 8175 const struct ufs_dev_quirk *fixups) 8176 { 8177 const struct ufs_dev_quirk *f; 8178 struct ufs_dev_info *dev_info = &hba->dev_info; 8179 8180 if (!fixups) 8181 return; 8182 8183 for (f = fixups; f->quirk; f++) { 8184 if ((f->wmanufacturerid == dev_info->wmanufacturerid || 8185 f->wmanufacturerid == UFS_ANY_VENDOR) && 8186 ((dev_info->model && 8187 STR_PRFX_EQUAL(f->model, dev_info->model)) || 8188 !strcmp(f->model, UFS_ANY_MODEL))) 8189 hba->dev_quirks |= f->quirk; 8190 } 8191 } 8192 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks); 8193 ufs_fixup_device_setup(struct ufs_hba * hba)8194 static void ufs_fixup_device_setup(struct ufs_hba *hba) 8195 { 8196 /* fix by general quirk table */ 8197 ufshcd_fixup_dev_quirks(hba, ufs_fixups); 8198 8199 /* allow vendors to fix quirks */ 8200 ufshcd_vops_fixup_dev_quirks(hba); 8201 } 8202 ufshcd_update_rtc(struct ufs_hba * hba)8203 static void ufshcd_update_rtc(struct ufs_hba *hba) 8204 { 8205 struct timespec64 ts64; 8206 int err; 8207 u32 val; 8208 8209 ktime_get_real_ts64(&ts64); 8210 8211 if (ts64.tv_sec < hba->dev_info.rtc_time_baseline) { 8212 dev_warn_once(hba->dev, "%s: Current time precedes previous setting!\n", __func__); 8213 return; 8214 } 8215 8216 /* 8217 * The Absolute RTC mode has a 136-year limit, spanning from 2010 to 2146. If a time beyond 8218 * 2146 is required, it is recommended to choose the relative RTC mode. 8219 */ 8220 val = ts64.tv_sec - hba->dev_info.rtc_time_baseline; 8221 8222 /* Skip update RTC if RPM state is not RPM_ACTIVE */ 8223 if (ufshcd_rpm_get_if_active(hba) <= 0) 8224 return; 8225 8226 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, QUERY_ATTR_IDN_SECONDS_PASSED, 8227 0, 0, &val); 8228 ufshcd_rpm_put(hba); 8229 8230 if (err) 8231 dev_err(hba->dev, "%s: Failed to update rtc %d\n", __func__, err); 8232 else if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE) 8233 hba->dev_info.rtc_time_baseline = ts64.tv_sec; 8234 } 8235 ufshcd_rtc_work(struct work_struct * work)8236 static void ufshcd_rtc_work(struct work_struct *work) 8237 { 8238 struct ufs_hba *hba; 8239 8240 hba = container_of(to_delayed_work(work), struct ufs_hba, ufs_rtc_update_work); 8241 8242 /* Update RTC only when there are no requests in progress and UFSHCI is operational */ 8243 if (!ufshcd_is_ufs_dev_busy(hba) && 8244 hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL && 8245 !hba->clk_gating.active_reqs) 8246 ufshcd_update_rtc(hba); 8247 8248 if (ufshcd_is_ufs_dev_active(hba) && hba->dev_info.rtc_update_period) 8249 schedule_delayed_work(&hba->ufs_rtc_update_work, 8250 msecs_to_jiffies(hba->dev_info.rtc_update_period)); 8251 } 8252 ufs_init_rtc(struct ufs_hba * hba,u8 * desc_buf)8253 static void ufs_init_rtc(struct ufs_hba *hba, u8 *desc_buf) 8254 { 8255 u16 periodic_rtc_update = get_unaligned_be16(&desc_buf[DEVICE_DESC_PARAM_FRQ_RTC]); 8256 struct ufs_dev_info *dev_info = &hba->dev_info; 8257 8258 if (periodic_rtc_update & UFS_RTC_TIME_BASELINE) { 8259 dev_info->rtc_type = UFS_RTC_ABSOLUTE; 8260 8261 /* 8262 * The concept of measuring time in Linux as the number of seconds elapsed since 8263 * 00:00:00 UTC on January 1, 1970, and UFS ABS RTC is elapsed from January 1st 8264 * 2010 00:00, here we need to adjust ABS baseline. 8265 */ 8266 dev_info->rtc_time_baseline = mktime64(2010, 1, 1, 0, 0, 0) - 8267 mktime64(1970, 1, 1, 0, 0, 0); 8268 } else { 8269 dev_info->rtc_type = UFS_RTC_RELATIVE; 8270 dev_info->rtc_time_baseline = 0; 8271 } 8272 8273 /* 8274 * We ignore TIME_PERIOD defined in wPeriodicRTCUpdate because Spec does not clearly state 8275 * how to calculate the specific update period for each time unit. And we disable periodic 8276 * RTC update work, let user configure by sysfs node according to specific circumstance. 8277 */ 8278 dev_info->rtc_update_period = 0; 8279 } 8280 ufs_get_device_desc(struct ufs_hba * hba)8281 static int ufs_get_device_desc(struct ufs_hba *hba) 8282 { 8283 int err; 8284 u8 model_index; 8285 u8 *desc_buf; 8286 struct ufs_dev_info *dev_info = &hba->dev_info; 8287 8288 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8289 if (!desc_buf) { 8290 err = -ENOMEM; 8291 goto out; 8292 } 8293 8294 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf, 8295 QUERY_DESC_MAX_SIZE); 8296 if (err) { 8297 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 8298 __func__, err); 8299 goto out; 8300 } 8301 8302 /* 8303 * getting vendor (manufacturerID) and Bank Index in big endian 8304 * format 8305 */ 8306 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 | 8307 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]; 8308 8309 /* getting Specification Version in big endian format */ 8310 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 | 8311 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1]; 8312 dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH]; 8313 8314 dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP]; 8315 8316 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME]; 8317 8318 err = ufshcd_read_string_desc(hba, model_index, 8319 &dev_info->model, SD_ASCII_STD); 8320 if (err < 0) { 8321 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n", 8322 __func__, err); 8323 goto out; 8324 } 8325 8326 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] + 8327 desc_buf[DEVICE_DESC_PARAM_NUM_WLU]; 8328 8329 ufs_fixup_device_setup(hba); 8330 8331 ufshcd_wb_probe(hba, desc_buf); 8332 8333 ufshcd_temp_notif_probe(hba, desc_buf); 8334 8335 if (dev_info->wspecversion >= 0x410) { 8336 hba->critical_health_count = 0; 8337 ufshcd_enable_ee(hba, MASK_EE_HEALTH_CRITICAL); 8338 } 8339 8340 ufs_init_rtc(hba, desc_buf); 8341 8342 /* 8343 * ufshcd_read_string_desc returns size of the string 8344 * reset the error value 8345 */ 8346 err = 0; 8347 8348 out: 8349 kfree(desc_buf); 8350 return err; 8351 } 8352 ufs_put_device_desc(struct ufs_hba * hba)8353 static void ufs_put_device_desc(struct ufs_hba *hba) 8354 { 8355 struct ufs_dev_info *dev_info = &hba->dev_info; 8356 8357 kfree(dev_info->model); 8358 dev_info->model = NULL; 8359 } 8360 8361 /** 8362 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is 8363 * less than device PA_TACTIVATE time. 8364 * @hba: per-adapter instance 8365 * 8366 * Some UFS devices require host PA_TACTIVATE to be lower than device 8367 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk 8368 * for such devices. 8369 * 8370 * Return: zero on success, non-zero error value on failure. 8371 */ ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba * hba)8372 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba) 8373 { 8374 int ret = 0; 8375 u32 granularity, peer_granularity; 8376 u32 pa_tactivate, peer_pa_tactivate; 8377 u32 pa_tactivate_us, peer_pa_tactivate_us; 8378 static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100}; 8379 8380 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8381 &granularity); 8382 if (ret) 8383 goto out; 8384 8385 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8386 &peer_granularity); 8387 if (ret) 8388 goto out; 8389 8390 if ((granularity < PA_GRANULARITY_MIN_VAL) || 8391 (granularity > PA_GRANULARITY_MAX_VAL)) { 8392 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d", 8393 __func__, granularity); 8394 return -EINVAL; 8395 } 8396 8397 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) || 8398 (peer_granularity > PA_GRANULARITY_MAX_VAL)) { 8399 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d", 8400 __func__, peer_granularity); 8401 return -EINVAL; 8402 } 8403 8404 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate); 8405 if (ret) 8406 goto out; 8407 8408 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 8409 &peer_pa_tactivate); 8410 if (ret) 8411 goto out; 8412 8413 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1]; 8414 peer_pa_tactivate_us = peer_pa_tactivate * 8415 gran_to_us_table[peer_granularity - 1]; 8416 8417 if (pa_tactivate_us >= peer_pa_tactivate_us) { 8418 u32 new_peer_pa_tactivate; 8419 8420 new_peer_pa_tactivate = pa_tactivate_us / 8421 gran_to_us_table[peer_granularity - 1]; 8422 new_peer_pa_tactivate++; 8423 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8424 new_peer_pa_tactivate); 8425 } 8426 8427 out: 8428 return ret; 8429 } 8430 ufshcd_tune_unipro_params(struct ufs_hba * hba)8431 static void ufshcd_tune_unipro_params(struct ufs_hba *hba) 8432 { 8433 ufshcd_vops_apply_dev_quirks(hba); 8434 8435 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE) 8436 /* set 1ms timeout for PA_TACTIVATE */ 8437 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10); 8438 8439 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE) 8440 ufshcd_quirk_tune_host_pa_tactivate(hba); 8441 } 8442 ufshcd_clear_dbg_ufs_stats(struct ufs_hba * hba)8443 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba) 8444 { 8445 hba->ufs_stats.hibern8_exit_cnt = 0; 8446 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 8447 hba->req_abort_count = 0; 8448 } 8449 ufshcd_device_geo_params_init(struct ufs_hba * hba)8450 static int ufshcd_device_geo_params_init(struct ufs_hba *hba) 8451 { 8452 int err; 8453 u8 *desc_buf; 8454 8455 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8456 if (!desc_buf) { 8457 err = -ENOMEM; 8458 goto out; 8459 } 8460 8461 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0, 8462 desc_buf, QUERY_DESC_MAX_SIZE); 8463 if (err) { 8464 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n", 8465 __func__, err); 8466 goto out; 8467 } 8468 8469 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1) 8470 hba->dev_info.max_lu_supported = 32; 8471 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0) 8472 hba->dev_info.max_lu_supported = 8; 8473 8474 out: 8475 kfree(desc_buf); 8476 return err; 8477 } 8478 8479 struct ufs_ref_clk { 8480 unsigned long freq_hz; 8481 enum ufs_ref_clk_freq val; 8482 }; 8483 8484 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = { 8485 {19200000, REF_CLK_FREQ_19_2_MHZ}, 8486 {26000000, REF_CLK_FREQ_26_MHZ}, 8487 {38400000, REF_CLK_FREQ_38_4_MHZ}, 8488 {52000000, REF_CLK_FREQ_52_MHZ}, 8489 {0, REF_CLK_FREQ_INVAL}, 8490 }; 8491 8492 static enum ufs_ref_clk_freq ufs_get_bref_clk_from_hz(unsigned long freq)8493 ufs_get_bref_clk_from_hz(unsigned long freq) 8494 { 8495 int i; 8496 8497 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++) 8498 if (ufs_ref_clk_freqs[i].freq_hz == freq) 8499 return ufs_ref_clk_freqs[i].val; 8500 8501 return REF_CLK_FREQ_INVAL; 8502 } 8503 ufshcd_parse_dev_ref_clk_freq(struct ufs_hba * hba,struct clk * refclk)8504 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk) 8505 { 8506 unsigned long freq; 8507 8508 freq = clk_get_rate(refclk); 8509 8510 hba->dev_ref_clk_freq = 8511 ufs_get_bref_clk_from_hz(freq); 8512 8513 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 8514 dev_err(hba->dev, 8515 "invalid ref_clk setting = %ld\n", freq); 8516 } 8517 ufshcd_set_dev_ref_clk(struct ufs_hba * hba)8518 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba) 8519 { 8520 int err; 8521 u32 ref_clk; 8522 u32 freq = hba->dev_ref_clk_freq; 8523 8524 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8525 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk); 8526 8527 if (err) { 8528 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n", 8529 err); 8530 goto out; 8531 } 8532 8533 if (ref_clk == freq) 8534 goto out; /* nothing to update */ 8535 8536 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8537 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq); 8538 8539 if (err) { 8540 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n", 8541 ufs_ref_clk_freqs[freq].freq_hz); 8542 goto out; 8543 } 8544 8545 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n", 8546 ufs_ref_clk_freqs[freq].freq_hz); 8547 8548 out: 8549 return err; 8550 } 8551 ufshcd_device_params_init(struct ufs_hba * hba)8552 static int ufshcd_device_params_init(struct ufs_hba *hba) 8553 { 8554 bool flag; 8555 int ret; 8556 8557 /* Init UFS geometry descriptor related parameters */ 8558 ret = ufshcd_device_geo_params_init(hba); 8559 if (ret) 8560 goto out; 8561 8562 /* Check and apply UFS device quirks */ 8563 ret = ufs_get_device_desc(hba); 8564 if (ret) { 8565 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 8566 __func__, ret); 8567 goto out; 8568 } 8569 8570 ufshcd_set_rtt(hba); 8571 8572 ufshcd_get_ref_clk_gating_wait(hba); 8573 8574 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 8575 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag)) 8576 hba->dev_info.f_power_on_wp_en = flag; 8577 8578 /* Probe maximum power mode co-supported by both UFS host and device */ 8579 if (ufshcd_get_max_pwr_mode(hba)) 8580 dev_err(hba->dev, 8581 "%s: Failed getting max supported power mode\n", 8582 __func__); 8583 out: 8584 return ret; 8585 } 8586 ufshcd_set_timestamp_attr(struct ufs_hba * hba)8587 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba) 8588 { 8589 int err; 8590 struct ufs_query_req *request = NULL; 8591 struct ufs_query_res *response = NULL; 8592 struct ufs_dev_info *dev_info = &hba->dev_info; 8593 struct utp_upiu_query_v4_0 *upiu_data; 8594 8595 if (dev_info->wspecversion < 0x400) 8596 return; 8597 8598 ufshcd_dev_man_lock(hba); 8599 8600 ufshcd_init_query(hba, &request, &response, 8601 UPIU_QUERY_OPCODE_WRITE_ATTR, 8602 QUERY_ATTR_IDN_TIMESTAMP, 0, 0); 8603 8604 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 8605 8606 upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req; 8607 8608 put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3); 8609 8610 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 8611 8612 if (err) 8613 dev_err(hba->dev, "%s: failed to set timestamp %d\n", 8614 __func__, err); 8615 8616 ufshcd_dev_man_unlock(hba); 8617 } 8618 8619 /** 8620 * ufshcd_add_lus - probe and add UFS logical units 8621 * @hba: per-adapter instance 8622 * 8623 * Return: 0 upon success; < 0 upon failure. 8624 */ ufshcd_add_lus(struct ufs_hba * hba)8625 static int ufshcd_add_lus(struct ufs_hba *hba) 8626 { 8627 int ret; 8628 8629 /* Add required well known logical units to scsi mid layer */ 8630 ret = ufshcd_scsi_add_wlus(hba); 8631 if (ret) 8632 goto out; 8633 8634 /* Initialize devfreq after UFS device is detected */ 8635 if (ufshcd_is_clkscaling_supported(hba)) { 8636 memcpy(&hba->clk_scaling.saved_pwr_info, 8637 &hba->pwr_info, 8638 sizeof(struct ufs_pa_layer_attr)); 8639 hba->clk_scaling.is_allowed = true; 8640 8641 ret = ufshcd_devfreq_init(hba); 8642 if (ret) 8643 goto out; 8644 8645 hba->clk_scaling.is_enabled = true; 8646 ufshcd_init_clk_scaling_sysfs(hba); 8647 } 8648 8649 /* 8650 * The RTC update code accesses the hba->ufs_device_wlun->sdev_gendev 8651 * pointer and hence must only be started after the WLUN pointer has 8652 * been initialized by ufshcd_scsi_add_wlus(). 8653 */ 8654 schedule_delayed_work(&hba->ufs_rtc_update_work, 8655 msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS)); 8656 8657 ufs_bsg_probe(hba); 8658 scsi_scan_host(hba->host); 8659 8660 out: 8661 return ret; 8662 } 8663 8664 /* SDB - Single Doorbell */ ufshcd_release_sdb_queue(struct ufs_hba * hba,int nutrs)8665 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs) 8666 { 8667 size_t ucdl_size, utrdl_size; 8668 8669 ucdl_size = ufshcd_get_ucd_size(hba) * nutrs; 8670 dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr, 8671 hba->ucdl_dma_addr); 8672 8673 utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs; 8674 dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr, 8675 hba->utrdl_dma_addr); 8676 8677 devm_kfree(hba->dev, hba->lrb); 8678 } 8679 ufshcd_alloc_mcq(struct ufs_hba * hba)8680 static int ufshcd_alloc_mcq(struct ufs_hba *hba) 8681 { 8682 int ret; 8683 int old_nutrs = hba->nutrs; 8684 8685 ret = ufshcd_mcq_decide_queue_depth(hba); 8686 if (ret < 0) 8687 return ret; 8688 8689 hba->nutrs = ret; 8690 ret = ufshcd_mcq_init(hba); 8691 if (ret) 8692 goto err; 8693 8694 /* 8695 * Previously allocated memory for nutrs may not be enough in MCQ mode. 8696 * Number of supported tags in MCQ mode may be larger than SDB mode. 8697 */ 8698 if (hba->nutrs != old_nutrs) { 8699 ufshcd_release_sdb_queue(hba, old_nutrs); 8700 ret = ufshcd_memory_alloc(hba); 8701 if (ret) 8702 goto err; 8703 ufshcd_host_memory_configure(hba); 8704 } 8705 8706 ret = ufshcd_mcq_memory_alloc(hba); 8707 if (ret) 8708 goto err; 8709 8710 hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 8711 hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED; 8712 8713 return 0; 8714 err: 8715 hba->nutrs = old_nutrs; 8716 return ret; 8717 } 8718 ufshcd_config_mcq(struct ufs_hba * hba)8719 static void ufshcd_config_mcq(struct ufs_hba *hba) 8720 { 8721 int ret; 8722 u32 intrs; 8723 8724 ret = ufshcd_mcq_vops_config_esi(hba); 8725 dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : ""); 8726 8727 intrs = UFSHCD_ENABLE_MCQ_INTRS; 8728 if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR) 8729 intrs &= ~MCQ_CQ_EVENT_STATUS; 8730 ufshcd_enable_intr(hba, intrs); 8731 ufshcd_mcq_make_queues_operational(hba); 8732 ufshcd_mcq_config_mac(hba, hba->nutrs); 8733 8734 dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n", 8735 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT], 8736 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL], 8737 hba->nutrs); 8738 } 8739 ufshcd_post_device_init(struct ufs_hba * hba)8740 static int ufshcd_post_device_init(struct ufs_hba *hba) 8741 { 8742 int ret; 8743 8744 ufshcd_tune_unipro_params(hba); 8745 8746 /* UFS device is also active now */ 8747 ufshcd_set_ufs_dev_active(hba); 8748 ufshcd_force_reset_auto_bkops(hba); 8749 8750 ufshcd_set_timestamp_attr(hba); 8751 8752 if (!hba->max_pwr_info.is_valid) 8753 return 0; 8754 8755 /* 8756 * Set the right value to bRefClkFreq before attempting to 8757 * switch to HS gears. 8758 */ 8759 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL) 8760 ufshcd_set_dev_ref_clk(hba); 8761 /* Gear up to HS gear. */ 8762 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); 8763 if (ret) { 8764 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 8765 __func__, ret); 8766 return ret; 8767 } 8768 8769 return 0; 8770 } 8771 ufshcd_device_init(struct ufs_hba * hba,bool init_dev_params)8772 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) 8773 { 8774 int ret; 8775 8776 WARN_ON_ONCE(!hba->scsi_host_added); 8777 8778 hba->ufshcd_state = UFSHCD_STATE_RESET; 8779 8780 ret = ufshcd_link_startup(hba); 8781 if (ret) 8782 return ret; 8783 8784 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) 8785 return ret; 8786 8787 /* Debug counters initialization */ 8788 ufshcd_clear_dbg_ufs_stats(hba); 8789 8790 /* UniPro link is active now */ 8791 ufshcd_set_link_active(hba); 8792 8793 /* Reconfigure MCQ upon reset */ 8794 if (hba->mcq_enabled && !init_dev_params) { 8795 ufshcd_config_mcq(hba); 8796 ufshcd_mcq_enable(hba); 8797 } 8798 8799 /* Verify device initialization by sending NOP OUT UPIU */ 8800 ret = ufshcd_verify_dev_init(hba); 8801 if (ret) 8802 return ret; 8803 8804 /* Initiate UFS initialization, and waiting until completion */ 8805 ret = ufshcd_complete_dev_init(hba); 8806 if (ret) 8807 return ret; 8808 8809 /* 8810 * Initialize UFS device parameters used by driver, these 8811 * parameters are associated with UFS descriptors. 8812 */ 8813 if (init_dev_params) { 8814 ret = ufshcd_device_params_init(hba); 8815 if (ret) 8816 return ret; 8817 if (is_mcq_supported(hba) && 8818 hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH) { 8819 ufshcd_config_mcq(hba); 8820 ufshcd_mcq_enable(hba); 8821 } 8822 } 8823 8824 return ufshcd_post_device_init(hba); 8825 } 8826 8827 /** 8828 * ufshcd_probe_hba - probe hba to detect device and initialize it 8829 * @hba: per-adapter instance 8830 * @init_dev_params: whether or not to call ufshcd_device_params_init(). 8831 * 8832 * Execute link-startup and verify device initialization 8833 * 8834 * Return: 0 upon success; < 0 upon failure. 8835 */ ufshcd_probe_hba(struct ufs_hba * hba,bool init_dev_params)8836 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) 8837 { 8838 int ret; 8839 8840 if (!hba->pm_op_in_progress && 8841 (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) { 8842 /* Reset the device and controller before doing reinit */ 8843 ufshcd_device_reset(hba); 8844 ufs_put_device_desc(hba); 8845 ufshcd_hba_stop(hba); 8846 ret = ufshcd_hba_enable(hba); 8847 if (ret) { 8848 dev_err(hba->dev, "Host controller enable failed\n"); 8849 ufshcd_print_evt_hist(hba); 8850 ufshcd_print_host_state(hba); 8851 return ret; 8852 } 8853 8854 /* Reinit the device */ 8855 ret = ufshcd_device_init(hba, init_dev_params); 8856 if (ret) 8857 return ret; 8858 } 8859 8860 ufshcd_print_pwr_info(hba); 8861 8862 /* 8863 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) 8864 * and for removable UFS card as well, hence always set the parameter. 8865 * Note: Error handler may issue the device reset hence resetting 8866 * bActiveICCLevel as well so it is always safe to set this here. 8867 */ 8868 ufshcd_set_active_icc_lvl(hba); 8869 8870 /* Enable UFS Write Booster if supported */ 8871 ufshcd_configure_wb(hba); 8872 8873 if (hba->ee_usr_mask) 8874 ufshcd_write_ee_control(hba); 8875 ufshcd_configure_auto_hibern8(hba); 8876 8877 return 0; 8878 } 8879 8880 /** 8881 * ufshcd_async_scan - asynchronous execution for probing hba 8882 * @data: data pointer to pass to this function 8883 * @cookie: cookie data 8884 */ ufshcd_async_scan(void * data,async_cookie_t cookie)8885 static void ufshcd_async_scan(void *data, async_cookie_t cookie) 8886 { 8887 struct ufs_hba *hba = (struct ufs_hba *)data; 8888 ktime_t probe_start; 8889 int ret; 8890 8891 down(&hba->host_sem); 8892 /* Initialize hba, detect and initialize UFS device */ 8893 probe_start = ktime_get(); 8894 ret = ufshcd_probe_hba(hba, true); 8895 ufshcd_process_probe_result(hba, probe_start, ret); 8896 up(&hba->host_sem); 8897 if (ret) 8898 goto out; 8899 8900 /* Probe and add UFS logical units */ 8901 ret = ufshcd_add_lus(hba); 8902 8903 out: 8904 pm_runtime_put_sync(hba->dev); 8905 8906 if (ret) 8907 dev_err(hba->dev, "%s failed: %d\n", __func__, ret); 8908 } 8909 ufshcd_eh_timed_out(struct scsi_cmnd * scmd)8910 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd) 8911 { 8912 struct ufs_hba *hba = shost_priv(scmd->device->host); 8913 8914 if (!hba->system_suspending) { 8915 /* Activate the error handler in the SCSI core. */ 8916 return SCSI_EH_NOT_HANDLED; 8917 } 8918 8919 /* 8920 * If we get here we know that no TMFs are outstanding and also that 8921 * the only pending command is a START STOP UNIT command. Handle the 8922 * timeout of that command directly to prevent a deadlock between 8923 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler(). 8924 */ 8925 ufshcd_link_recovery(hba); 8926 dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n", 8927 __func__, hba->outstanding_tasks); 8928 8929 return scsi_host_busy(hba->host) ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE; 8930 } 8931 8932 static const struct attribute_group *ufshcd_driver_groups[] = { 8933 &ufs_sysfs_unit_descriptor_group, 8934 &ufs_sysfs_lun_attributes_group, 8935 NULL, 8936 }; 8937 8938 static struct ufs_hba_variant_params ufs_hba_vps = { 8939 .hba_enable_delay_us = 1000, 8940 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40), 8941 .devfreq_profile.polling_ms = 100, 8942 .devfreq_profile.target = ufshcd_devfreq_target, 8943 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status, 8944 .ondemand_data.upthreshold = 70, 8945 .ondemand_data.downdifferential = 5, 8946 }; 8947 8948 static const struct scsi_host_template ufshcd_driver_template = { 8949 .module = THIS_MODULE, 8950 .name = UFSHCD, 8951 .proc_name = UFSHCD, 8952 .map_queues = ufshcd_map_queues, 8953 .queuecommand = ufshcd_queuecommand, 8954 .mq_poll = ufshcd_poll, 8955 .sdev_init = ufshcd_sdev_init, 8956 .sdev_configure = ufshcd_sdev_configure, 8957 .sdev_destroy = ufshcd_sdev_destroy, 8958 .change_queue_depth = ufshcd_change_queue_depth, 8959 .eh_abort_handler = ufshcd_abort, 8960 .eh_device_reset_handler = ufshcd_eh_device_reset_handler, 8961 .eh_host_reset_handler = ufshcd_eh_host_reset_handler, 8962 .eh_timed_out = ufshcd_eh_timed_out, 8963 .this_id = -1, 8964 .sg_tablesize = SG_ALL, 8965 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX, 8966 .max_sectors = SZ_1M / SECTOR_SIZE, 8967 .max_host_blocked = 1, 8968 .track_queue_depth = 1, 8969 .skip_settle_delay = 1, 8970 .sdev_groups = ufshcd_driver_groups, 8971 }; 8972 ufshcd_config_vreg_load(struct device * dev,struct ufs_vreg * vreg,int ua)8973 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg, 8974 int ua) 8975 { 8976 int ret; 8977 8978 if (!vreg) 8979 return 0; 8980 8981 /* 8982 * "set_load" operation shall be required on those regulators 8983 * which specifically configured current limitation. Otherwise 8984 * zero max_uA may cause unexpected behavior when regulator is 8985 * enabled or set as high power mode. 8986 */ 8987 if (!vreg->max_uA) 8988 return 0; 8989 8990 ret = regulator_set_load(vreg->reg, ua); 8991 if (ret < 0) { 8992 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n", 8993 __func__, vreg->name, ua, ret); 8994 } 8995 8996 return ret; 8997 } 8998 ufshcd_config_vreg_lpm(struct ufs_hba * hba,struct ufs_vreg * vreg)8999 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba, 9000 struct ufs_vreg *vreg) 9001 { 9002 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA); 9003 } 9004 ufshcd_config_vreg_hpm(struct ufs_hba * hba,struct ufs_vreg * vreg)9005 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 9006 struct ufs_vreg *vreg) 9007 { 9008 if (!vreg) 9009 return 0; 9010 9011 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA); 9012 } 9013 ufshcd_config_vreg(struct device * dev,struct ufs_vreg * vreg,bool on)9014 static int ufshcd_config_vreg(struct device *dev, 9015 struct ufs_vreg *vreg, bool on) 9016 { 9017 if (regulator_count_voltages(vreg->reg) <= 0) 9018 return 0; 9019 9020 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0); 9021 } 9022 ufshcd_enable_vreg(struct device * dev,struct ufs_vreg * vreg)9023 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg) 9024 { 9025 int ret = 0; 9026 9027 if (!vreg || vreg->enabled) 9028 goto out; 9029 9030 ret = ufshcd_config_vreg(dev, vreg, true); 9031 if (!ret) 9032 ret = regulator_enable(vreg->reg); 9033 9034 if (!ret) 9035 vreg->enabled = true; 9036 else 9037 dev_err(dev, "%s: %s enable failed, err=%d\n", 9038 __func__, vreg->name, ret); 9039 out: 9040 return ret; 9041 } 9042 ufshcd_disable_vreg(struct device * dev,struct ufs_vreg * vreg)9043 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg) 9044 { 9045 int ret = 0; 9046 9047 if (!vreg || !vreg->enabled || vreg->always_on) 9048 goto out; 9049 9050 ret = regulator_disable(vreg->reg); 9051 9052 if (!ret) { 9053 /* ignore errors on applying disable config */ 9054 ufshcd_config_vreg(dev, vreg, false); 9055 vreg->enabled = false; 9056 } else { 9057 dev_err(dev, "%s: %s disable failed, err=%d\n", 9058 __func__, vreg->name, ret); 9059 } 9060 out: 9061 return ret; 9062 } 9063 ufshcd_setup_vreg(struct ufs_hba * hba,bool on)9064 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on) 9065 { 9066 int ret = 0; 9067 struct device *dev = hba->dev; 9068 struct ufs_vreg_info *info = &hba->vreg_info; 9069 9070 ret = ufshcd_toggle_vreg(dev, info->vcc, on); 9071 if (ret) 9072 goto out; 9073 9074 ret = ufshcd_toggle_vreg(dev, info->vccq, on); 9075 if (ret) 9076 goto out; 9077 9078 ret = ufshcd_toggle_vreg(dev, info->vccq2, on); 9079 9080 out: 9081 if (ret) { 9082 ufshcd_toggle_vreg(dev, info->vccq2, false); 9083 ufshcd_toggle_vreg(dev, info->vccq, false); 9084 ufshcd_toggle_vreg(dev, info->vcc, false); 9085 } 9086 return ret; 9087 } 9088 ufshcd_setup_hba_vreg(struct ufs_hba * hba,bool on)9089 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on) 9090 { 9091 struct ufs_vreg_info *info = &hba->vreg_info; 9092 9093 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); 9094 } 9095 ufshcd_get_vreg(struct device * dev,struct ufs_vreg * vreg)9096 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) 9097 { 9098 int ret = 0; 9099 9100 if (!vreg) 9101 goto out; 9102 9103 vreg->reg = devm_regulator_get(dev, vreg->name); 9104 if (IS_ERR(vreg->reg)) { 9105 ret = PTR_ERR(vreg->reg); 9106 dev_err(dev, "%s: %s get failed, err=%d\n", 9107 __func__, vreg->name, ret); 9108 } 9109 out: 9110 return ret; 9111 } 9112 EXPORT_SYMBOL_GPL(ufshcd_get_vreg); 9113 ufshcd_init_vreg(struct ufs_hba * hba)9114 static int ufshcd_init_vreg(struct ufs_hba *hba) 9115 { 9116 int ret = 0; 9117 struct device *dev = hba->dev; 9118 struct ufs_vreg_info *info = &hba->vreg_info; 9119 9120 ret = ufshcd_get_vreg(dev, info->vcc); 9121 if (ret) 9122 goto out; 9123 9124 ret = ufshcd_get_vreg(dev, info->vccq); 9125 if (!ret) 9126 ret = ufshcd_get_vreg(dev, info->vccq2); 9127 out: 9128 return ret; 9129 } 9130 ufshcd_init_hba_vreg(struct ufs_hba * hba)9131 static int ufshcd_init_hba_vreg(struct ufs_hba *hba) 9132 { 9133 struct ufs_vreg_info *info = &hba->vreg_info; 9134 9135 return ufshcd_get_vreg(hba->dev, info->vdd_hba); 9136 } 9137 ufshcd_setup_clocks(struct ufs_hba * hba,bool on)9138 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) 9139 { 9140 int ret = 0; 9141 struct ufs_clk_info *clki; 9142 struct list_head *head = &hba->clk_list_head; 9143 ktime_t start = ktime_get(); 9144 bool clk_state_changed = false; 9145 9146 if (list_empty(head)) 9147 goto out; 9148 9149 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE); 9150 if (ret) 9151 return ret; 9152 9153 list_for_each_entry(clki, head, list) { 9154 if (!IS_ERR_OR_NULL(clki->clk)) { 9155 /* 9156 * Don't disable clocks which are needed 9157 * to keep the link active. 9158 */ 9159 if (ufshcd_is_link_active(hba) && 9160 clki->keep_link_active) 9161 continue; 9162 9163 clk_state_changed = on ^ clki->enabled; 9164 if (on && !clki->enabled) { 9165 ret = clk_prepare_enable(clki->clk); 9166 if (ret) { 9167 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n", 9168 __func__, clki->name, ret); 9169 goto out; 9170 } 9171 } else if (!on && clki->enabled) { 9172 clk_disable_unprepare(clki->clk); 9173 } 9174 clki->enabled = on; 9175 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__, 9176 clki->name, on ? "en" : "dis"); 9177 } 9178 } 9179 9180 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE); 9181 if (ret) 9182 return ret; 9183 9184 if (!ufshcd_is_clkscaling_supported(hba)) 9185 ufshcd_pm_qos_update(hba, on); 9186 out: 9187 if (ret) { 9188 list_for_each_entry(clki, head, list) { 9189 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled) 9190 clk_disable_unprepare(clki->clk); 9191 } 9192 } else if (!ret && on && hba->clk_gating.is_initialized) { 9193 scoped_guard(spinlock_irqsave, &hba->clk_gating.lock) 9194 hba->clk_gating.state = CLKS_ON; 9195 trace_ufshcd_clk_gating(hba, 9196 hba->clk_gating.state); 9197 } 9198 9199 if (clk_state_changed) 9200 trace_ufshcd_profile_clk_gating(hba, 9201 (on ? "on" : "off"), 9202 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 9203 return ret; 9204 } 9205 ufshcd_parse_ref_clk_property(struct ufs_hba * hba)9206 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba) 9207 { 9208 u32 freq; 9209 int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq); 9210 9211 if (ret) { 9212 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret); 9213 return REF_CLK_FREQ_INVAL; 9214 } 9215 9216 return ufs_get_bref_clk_from_hz(freq); 9217 } 9218 ufshcd_init_clocks(struct ufs_hba * hba)9219 static int ufshcd_init_clocks(struct ufs_hba *hba) 9220 { 9221 int ret = 0; 9222 struct ufs_clk_info *clki; 9223 struct device *dev = hba->dev; 9224 struct list_head *head = &hba->clk_list_head; 9225 9226 if (list_empty(head)) 9227 goto out; 9228 9229 list_for_each_entry(clki, head, list) { 9230 if (!clki->name) 9231 continue; 9232 9233 clki->clk = devm_clk_get(dev, clki->name); 9234 if (IS_ERR(clki->clk)) { 9235 ret = PTR_ERR(clki->clk); 9236 dev_err(dev, "%s: %s clk get failed, %d\n", 9237 __func__, clki->name, ret); 9238 goto out; 9239 } 9240 9241 /* 9242 * Parse device ref clk freq as per device tree "ref_clk". 9243 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL 9244 * in ufshcd_alloc_host(). 9245 */ 9246 if (!strcmp(clki->name, "ref_clk")) 9247 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk); 9248 9249 if (clki->max_freq) { 9250 ret = clk_set_rate(clki->clk, clki->max_freq); 9251 if (ret) { 9252 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 9253 __func__, clki->name, 9254 clki->max_freq, ret); 9255 goto out; 9256 } 9257 clki->curr_freq = clki->max_freq; 9258 } 9259 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__, 9260 clki->name, clk_get_rate(clki->clk)); 9261 } 9262 9263 /* Set Max. frequency for all clocks */ 9264 if (hba->use_pm_opp) { 9265 ret = ufshcd_opp_set_rate(hba, ULONG_MAX); 9266 if (ret) { 9267 dev_err(hba->dev, "%s: failed to set OPP: %d", __func__, 9268 ret); 9269 goto out; 9270 } 9271 } 9272 9273 out: 9274 return ret; 9275 } 9276 ufshcd_variant_hba_init(struct ufs_hba * hba)9277 static int ufshcd_variant_hba_init(struct ufs_hba *hba) 9278 { 9279 int err = 0; 9280 9281 if (!hba->vops) 9282 goto out; 9283 9284 err = ufshcd_vops_init(hba); 9285 if (err) 9286 dev_err_probe(hba->dev, err, 9287 "%s: variant %s init failed with err %d\n", 9288 __func__, ufshcd_get_var_name(hba), err); 9289 out: 9290 return err; 9291 } 9292 ufshcd_variant_hba_exit(struct ufs_hba * hba)9293 static void ufshcd_variant_hba_exit(struct ufs_hba *hba) 9294 { 9295 if (!hba->vops) 9296 return; 9297 9298 ufshcd_vops_exit(hba); 9299 } 9300 ufshcd_hba_init(struct ufs_hba * hba)9301 static int ufshcd_hba_init(struct ufs_hba *hba) 9302 { 9303 int err; 9304 9305 /* 9306 * Handle host controller power separately from the UFS device power 9307 * rails as it will help controlling the UFS host controller power 9308 * collapse easily which is different than UFS device power collapse. 9309 * Also, enable the host controller power before we go ahead with rest 9310 * of the initialization here. 9311 */ 9312 err = ufshcd_init_hba_vreg(hba); 9313 if (err) 9314 goto out; 9315 9316 err = ufshcd_setup_hba_vreg(hba, true); 9317 if (err) 9318 goto out; 9319 9320 err = ufshcd_init_clocks(hba); 9321 if (err) 9322 goto out_disable_hba_vreg; 9323 9324 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 9325 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba); 9326 9327 err = ufshcd_setup_clocks(hba, true); 9328 if (err) 9329 goto out_disable_hba_vreg; 9330 9331 err = ufshcd_init_vreg(hba); 9332 if (err) 9333 goto out_disable_clks; 9334 9335 err = ufshcd_setup_vreg(hba, true); 9336 if (err) 9337 goto out_disable_clks; 9338 9339 err = ufshcd_variant_hba_init(hba); 9340 if (err) 9341 goto out_disable_vreg; 9342 9343 ufs_debugfs_hba_init(hba); 9344 ufs_fault_inject_hba_init(hba); 9345 9346 hba->is_powered = true; 9347 goto out; 9348 9349 out_disable_vreg: 9350 ufshcd_setup_vreg(hba, false); 9351 out_disable_clks: 9352 ufshcd_setup_clocks(hba, false); 9353 out_disable_hba_vreg: 9354 ufshcd_setup_hba_vreg(hba, false); 9355 out: 9356 return err; 9357 } 9358 ufshcd_hba_exit(struct ufs_hba * hba)9359 static void ufshcd_hba_exit(struct ufs_hba *hba) 9360 { 9361 if (hba->is_powered) { 9362 ufshcd_pm_qos_exit(hba); 9363 ufshcd_exit_clk_scaling(hba); 9364 ufshcd_exit_clk_gating(hba); 9365 if (hba->eh_wq) 9366 destroy_workqueue(hba->eh_wq); 9367 ufs_debugfs_hba_exit(hba); 9368 ufshcd_variant_hba_exit(hba); 9369 ufshcd_setup_vreg(hba, false); 9370 ufshcd_setup_clocks(hba, false); 9371 ufshcd_setup_hba_vreg(hba, false); 9372 hba->is_powered = false; 9373 ufs_put_device_desc(hba); 9374 } 9375 } 9376 ufshcd_execute_start_stop(struct scsi_device * sdev,enum ufs_dev_pwr_mode pwr_mode,struct scsi_sense_hdr * sshdr)9377 static int ufshcd_execute_start_stop(struct scsi_device *sdev, 9378 enum ufs_dev_pwr_mode pwr_mode, 9379 struct scsi_sense_hdr *sshdr) 9380 { 9381 const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 }; 9382 struct scsi_failure failure_defs[] = { 9383 { 9384 .allowed = 2, 9385 .result = SCMD_FAILURE_RESULT_ANY, 9386 }, 9387 }; 9388 struct scsi_failures failures = { 9389 .failure_definitions = failure_defs, 9390 }; 9391 const struct scsi_exec_args args = { 9392 .failures = &failures, 9393 .sshdr = sshdr, 9394 .req_flags = BLK_MQ_REQ_PM, 9395 .scmd_flags = SCMD_FAIL_IF_RECOVERING, 9396 }; 9397 9398 return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL, 9399 /*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0, 9400 &args); 9401 } 9402 9403 /** 9404 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device 9405 * power mode 9406 * @hba: per adapter instance 9407 * @pwr_mode: device power mode to set 9408 * 9409 * Return: 0 if requested power mode is set successfully; 9410 * < 0 if failed to set the requested power mode. 9411 */ ufshcd_set_dev_pwr_mode(struct ufs_hba * hba,enum ufs_dev_pwr_mode pwr_mode)9412 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, 9413 enum ufs_dev_pwr_mode pwr_mode) 9414 { 9415 struct scsi_sense_hdr sshdr; 9416 struct scsi_device *sdp; 9417 unsigned long flags; 9418 int ret; 9419 9420 spin_lock_irqsave(hba->host->host_lock, flags); 9421 sdp = hba->ufs_device_wlun; 9422 if (sdp && scsi_device_online(sdp)) 9423 ret = scsi_device_get(sdp); 9424 else 9425 ret = -ENODEV; 9426 spin_unlock_irqrestore(hba->host->host_lock, flags); 9427 9428 if (ret) 9429 return ret; 9430 9431 /* 9432 * If scsi commands fail, the scsi mid-layer schedules scsi error- 9433 * handling, which would wait for host to be resumed. Since we know 9434 * we are functional while we are here, skip host resume in error 9435 * handling context. 9436 */ 9437 hba->host->eh_noresume = 1; 9438 9439 /* 9440 * Current function would be generally called from the power management 9441 * callbacks hence set the RQF_PM flag so that it doesn't resume the 9442 * already suspended childs. 9443 */ 9444 ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr); 9445 if (ret) { 9446 sdev_printk(KERN_WARNING, sdp, 9447 "START_STOP failed for power mode: %d, result %x\n", 9448 pwr_mode, ret); 9449 if (ret > 0) { 9450 if (scsi_sense_valid(&sshdr)) 9451 scsi_print_sense_hdr(sdp, NULL, &sshdr); 9452 ret = -EIO; 9453 } 9454 } else { 9455 hba->curr_dev_pwr_mode = pwr_mode; 9456 } 9457 9458 scsi_device_put(sdp); 9459 hba->host->eh_noresume = 0; 9460 return ret; 9461 } 9462 ufshcd_link_state_transition(struct ufs_hba * hba,enum uic_link_state req_link_state,bool check_for_bkops)9463 static int ufshcd_link_state_transition(struct ufs_hba *hba, 9464 enum uic_link_state req_link_state, 9465 bool check_for_bkops) 9466 { 9467 int ret = 0; 9468 9469 if (req_link_state == hba->uic_link_state) 9470 return 0; 9471 9472 if (req_link_state == UIC_LINK_HIBERN8_STATE) { 9473 ret = ufshcd_uic_hibern8_enter(hba); 9474 if (!ret) { 9475 ufshcd_set_link_hibern8(hba); 9476 } else { 9477 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9478 __func__, ret); 9479 goto out; 9480 } 9481 } 9482 /* 9483 * If autobkops is enabled, link can't be turned off because 9484 * turning off the link would also turn off the device, except in the 9485 * case of DeepSleep where the device is expected to remain powered. 9486 */ 9487 else if ((req_link_state == UIC_LINK_OFF_STATE) && 9488 (!check_for_bkops || !hba->auto_bkops_enabled)) { 9489 /* 9490 * Let's make sure that link is in low power mode, we are doing 9491 * this currently by putting the link in Hibern8. Otherway to 9492 * put the link in low power mode is to send the DME end point 9493 * to device and then send the DME reset command to local 9494 * unipro. But putting the link in hibern8 is much faster. 9495 * 9496 * Note also that putting the link in Hibern8 is a requirement 9497 * for entering DeepSleep. 9498 */ 9499 ret = ufshcd_uic_hibern8_enter(hba); 9500 if (ret) { 9501 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9502 __func__, ret); 9503 goto out; 9504 } 9505 /* 9506 * Change controller state to "reset state" which 9507 * should also put the link in off/reset state 9508 */ 9509 ufshcd_hba_stop(hba); 9510 /* 9511 * TODO: Check if we need any delay to make sure that 9512 * controller is reset 9513 */ 9514 ufshcd_set_link_off(hba); 9515 } 9516 9517 out: 9518 return ret; 9519 } 9520 ufshcd_vreg_set_lpm(struct ufs_hba * hba)9521 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba) 9522 { 9523 bool vcc_off = false; 9524 9525 /* 9526 * It seems some UFS devices may keep drawing more than sleep current 9527 * (atleast for 500us) from UFS rails (especially from VCCQ rail). 9528 * To avoid this situation, add 2ms delay before putting these UFS 9529 * rails in LPM mode. 9530 */ 9531 if (!ufshcd_is_link_active(hba) && 9532 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM) 9533 usleep_range(2000, 2100); 9534 9535 /* 9536 * If UFS device is either in UFS_Sleep turn off VCC rail to save some 9537 * power. 9538 * 9539 * If UFS device and link is in OFF state, all power supplies (VCC, 9540 * VCCQ, VCCQ2) can be turned off if power on write protect is not 9541 * required. If UFS link is inactive (Hibern8 or OFF state) and device 9542 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode. 9543 * 9544 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway 9545 * in low power state which would save some power. 9546 * 9547 * If Write Booster is enabled and the device needs to flush the WB 9548 * buffer OR if bkops status is urgent for WB, keep Vcc on. 9549 */ 9550 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9551 !hba->dev_info.is_lu_power_on_wp) { 9552 ufshcd_setup_vreg(hba, false); 9553 vcc_off = true; 9554 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9555 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9556 vcc_off = true; 9557 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) { 9558 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9559 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2); 9560 } 9561 } 9562 9563 /* 9564 * Some UFS devices require delay after VCC power rail is turned-off. 9565 */ 9566 if (vcc_off && hba->vreg_info.vcc && 9567 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM) 9568 usleep_range(5000, 5100); 9569 } 9570 9571 #ifdef CONFIG_PM ufshcd_vreg_set_hpm(struct ufs_hba * hba)9572 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba) 9573 { 9574 int ret = 0; 9575 9576 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9577 !hba->dev_info.is_lu_power_on_wp) { 9578 ret = ufshcd_setup_vreg(hba, true); 9579 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9580 if (!ufshcd_is_link_active(hba)) { 9581 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 9582 if (ret) 9583 goto vcc_disable; 9584 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 9585 if (ret) 9586 goto vccq_lpm; 9587 } 9588 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true); 9589 } 9590 goto out; 9591 9592 vccq_lpm: 9593 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9594 vcc_disable: 9595 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9596 out: 9597 return ret; 9598 } 9599 #endif /* CONFIG_PM */ 9600 ufshcd_hba_vreg_set_lpm(struct ufs_hba * hba)9601 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba) 9602 { 9603 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9604 ufshcd_setup_hba_vreg(hba, false); 9605 } 9606 ufshcd_hba_vreg_set_hpm(struct ufs_hba * hba)9607 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba) 9608 { 9609 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9610 ufshcd_setup_hba_vreg(hba, true); 9611 } 9612 __ufshcd_wl_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op)9613 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9614 { 9615 int ret = 0; 9616 bool check_for_bkops; 9617 enum ufs_pm_level pm_lvl; 9618 enum ufs_dev_pwr_mode req_dev_pwr_mode; 9619 enum uic_link_state req_link_state; 9620 9621 hba->pm_op_in_progress = true; 9622 if (pm_op != UFS_SHUTDOWN_PM) { 9623 pm_lvl = pm_op == UFS_RUNTIME_PM ? 9624 hba->rpm_lvl : hba->spm_lvl; 9625 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl); 9626 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl); 9627 } else { 9628 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE; 9629 req_link_state = UIC_LINK_OFF_STATE; 9630 } 9631 9632 /* 9633 * If we can't transition into any of the low power modes 9634 * just gate the clocks. 9635 */ 9636 ufshcd_hold(hba); 9637 hba->clk_gating.is_suspended = true; 9638 9639 if (ufshcd_is_clkscaling_supported(hba)) 9640 ufshcd_clk_scaling_suspend(hba, true); 9641 9642 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE && 9643 req_link_state == UIC_LINK_ACTIVE_STATE) { 9644 goto vops_suspend; 9645 } 9646 9647 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) && 9648 (req_link_state == hba->uic_link_state)) 9649 goto enable_scaling; 9650 9651 /* UFS device & link must be active before we enter in this function */ 9652 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) { 9653 /* Wait err handler finish or trigger err recovery */ 9654 if (!ufshcd_eh_in_progress(hba)) 9655 ufshcd_force_error_recovery(hba); 9656 ret = -EBUSY; 9657 goto enable_scaling; 9658 } 9659 9660 if (pm_op == UFS_RUNTIME_PM) { 9661 if (ufshcd_can_autobkops_during_suspend(hba)) { 9662 /* 9663 * The device is idle with no requests in the queue, 9664 * allow background operations if bkops status shows 9665 * that performance might be impacted. 9666 */ 9667 ret = ufshcd_bkops_ctrl(hba); 9668 if (ret) { 9669 /* 9670 * If return err in suspend flow, IO will hang. 9671 * Trigger error handler and break suspend for 9672 * error recovery. 9673 */ 9674 ufshcd_force_error_recovery(hba); 9675 ret = -EBUSY; 9676 goto enable_scaling; 9677 } 9678 } else { 9679 /* make sure that auto bkops is disabled */ 9680 ufshcd_disable_auto_bkops(hba); 9681 } 9682 /* 9683 * If device needs to do BKOP or WB buffer flush during 9684 * Hibern8, keep device power mode as "active power mode" 9685 * and VCC supply. 9686 */ 9687 hba->dev_info.b_rpm_dev_flush_capable = 9688 hba->auto_bkops_enabled || 9689 (((req_link_state == UIC_LINK_HIBERN8_STATE) || 9690 ((req_link_state == UIC_LINK_ACTIVE_STATE) && 9691 ufshcd_is_auto_hibern8_enabled(hba))) && 9692 ufshcd_wb_need_flush(hba)); 9693 } 9694 9695 flush_work(&hba->eeh_work); 9696 9697 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9698 if (ret) 9699 goto enable_scaling; 9700 9701 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) { 9702 if (pm_op != UFS_RUNTIME_PM) 9703 /* ensure that bkops is disabled */ 9704 ufshcd_disable_auto_bkops(hba); 9705 9706 if (!hba->dev_info.b_rpm_dev_flush_capable) { 9707 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode); 9708 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9709 /* 9710 * If return err in suspend flow, IO will hang. 9711 * Trigger error handler and break suspend for 9712 * error recovery. 9713 */ 9714 ufshcd_force_error_recovery(hba); 9715 ret = -EBUSY; 9716 } 9717 if (ret) 9718 goto enable_scaling; 9719 } 9720 } 9721 9722 /* 9723 * In the case of DeepSleep, the device is expected to remain powered 9724 * with the link off, so do not check for bkops. 9725 */ 9726 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba); 9727 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops); 9728 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9729 /* 9730 * If return err in suspend flow, IO will hang. 9731 * Trigger error handler and break suspend for 9732 * error recovery. 9733 */ 9734 ufshcd_force_error_recovery(hba); 9735 ret = -EBUSY; 9736 } 9737 if (ret) 9738 goto set_dev_active; 9739 9740 vops_suspend: 9741 /* 9742 * Call vendor specific suspend callback. As these callbacks may access 9743 * vendor specific host controller register space call them before the 9744 * host clocks are ON. 9745 */ 9746 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9747 if (ret) 9748 goto set_link_active; 9749 9750 cancel_delayed_work_sync(&hba->ufs_rtc_update_work); 9751 goto out; 9752 9753 set_link_active: 9754 /* 9755 * Device hardware reset is required to exit DeepSleep. Also, for 9756 * DeepSleep, the link is off so host reset and restore will be done 9757 * further below. 9758 */ 9759 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9760 ufshcd_device_reset(hba); 9761 WARN_ON(!ufshcd_is_link_off(hba)); 9762 } 9763 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba)) 9764 ufshcd_set_link_active(hba); 9765 else if (ufshcd_is_link_off(hba)) 9766 ufshcd_host_reset_and_restore(hba); 9767 set_dev_active: 9768 /* Can also get here needing to exit DeepSleep */ 9769 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9770 ufshcd_device_reset(hba); 9771 ufshcd_host_reset_and_restore(hba); 9772 } 9773 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE)) 9774 ufshcd_disable_auto_bkops(hba); 9775 enable_scaling: 9776 if (ufshcd_is_clkscaling_supported(hba)) 9777 ufshcd_clk_scaling_suspend(hba, false); 9778 9779 hba->dev_info.b_rpm_dev_flush_capable = false; 9780 out: 9781 if (hba->dev_info.b_rpm_dev_flush_capable) { 9782 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work, 9783 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS)); 9784 } 9785 9786 if (ret) { 9787 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret); 9788 hba->clk_gating.is_suspended = false; 9789 ufshcd_release(hba); 9790 } 9791 hba->pm_op_in_progress = false; 9792 return ret; 9793 } 9794 9795 #ifdef CONFIG_PM __ufshcd_wl_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)9796 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9797 { 9798 int ret; 9799 enum uic_link_state old_link_state = hba->uic_link_state; 9800 9801 hba->pm_op_in_progress = true; 9802 9803 /* 9804 * Call vendor specific resume callback. As these callbacks may access 9805 * vendor specific host controller register space call them when the 9806 * host clocks are ON. 9807 */ 9808 ret = ufshcd_vops_resume(hba, pm_op); 9809 if (ret) 9810 goto out; 9811 9812 /* For DeepSleep, the only supported option is to have the link off */ 9813 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba)); 9814 9815 if (ufshcd_is_link_hibern8(hba)) { 9816 ret = ufshcd_uic_hibern8_exit(hba); 9817 if (!ret) { 9818 ufshcd_set_link_active(hba); 9819 } else { 9820 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 9821 __func__, ret); 9822 goto vendor_suspend; 9823 } 9824 } else if (ufshcd_is_link_off(hba)) { 9825 /* 9826 * A full initialization of the host and the device is 9827 * required since the link was put to off during suspend. 9828 * Note, in the case of DeepSleep, the device will exit 9829 * DeepSleep due to device reset. 9830 */ 9831 ret = ufshcd_reset_and_restore(hba); 9832 /* 9833 * ufshcd_reset_and_restore() should have already 9834 * set the link state as active 9835 */ 9836 if (ret || !ufshcd_is_link_active(hba)) 9837 goto vendor_suspend; 9838 } 9839 9840 if (!ufshcd_is_ufs_dev_active(hba)) { 9841 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE); 9842 if (ret) 9843 goto set_old_link_state; 9844 ufshcd_set_timestamp_attr(hba); 9845 schedule_delayed_work(&hba->ufs_rtc_update_work, 9846 msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS)); 9847 } 9848 9849 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) 9850 ufshcd_enable_auto_bkops(hba); 9851 else 9852 /* 9853 * If BKOPs operations are urgently needed at this moment then 9854 * keep auto-bkops enabled or else disable it. 9855 */ 9856 ufshcd_bkops_ctrl(hba); 9857 9858 if (hba->ee_usr_mask) 9859 ufshcd_write_ee_control(hba); 9860 9861 if (ufshcd_is_clkscaling_supported(hba)) 9862 ufshcd_clk_scaling_suspend(hba, false); 9863 9864 if (hba->dev_info.b_rpm_dev_flush_capable) { 9865 hba->dev_info.b_rpm_dev_flush_capable = false; 9866 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work); 9867 } 9868 9869 ufshcd_configure_auto_hibern8(hba); 9870 9871 goto out; 9872 9873 set_old_link_state: 9874 ufshcd_link_state_transition(hba, old_link_state, 0); 9875 vendor_suspend: 9876 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9877 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9878 out: 9879 if (ret) 9880 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret); 9881 hba->clk_gating.is_suspended = false; 9882 ufshcd_release(hba); 9883 hba->pm_op_in_progress = false; 9884 return ret; 9885 } 9886 ufshcd_wl_runtime_suspend(struct device * dev)9887 static int ufshcd_wl_runtime_suspend(struct device *dev) 9888 { 9889 struct scsi_device *sdev = to_scsi_device(dev); 9890 struct ufs_hba *hba; 9891 int ret; 9892 ktime_t start = ktime_get(); 9893 9894 hba = shost_priv(sdev->host); 9895 9896 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM); 9897 if (ret) 9898 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9899 9900 trace_ufshcd_wl_runtime_suspend(hba, ret, 9901 ktime_to_us(ktime_sub(ktime_get(), start)), 9902 hba->curr_dev_pwr_mode, hba->uic_link_state); 9903 9904 return ret; 9905 } 9906 ufshcd_wl_runtime_resume(struct device * dev)9907 static int ufshcd_wl_runtime_resume(struct device *dev) 9908 { 9909 struct scsi_device *sdev = to_scsi_device(dev); 9910 struct ufs_hba *hba; 9911 int ret = 0; 9912 ktime_t start = ktime_get(); 9913 9914 hba = shost_priv(sdev->host); 9915 9916 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM); 9917 if (ret) 9918 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9919 9920 trace_ufshcd_wl_runtime_resume(hba, ret, 9921 ktime_to_us(ktime_sub(ktime_get(), start)), 9922 hba->curr_dev_pwr_mode, hba->uic_link_state); 9923 9924 return ret; 9925 } 9926 #endif 9927 9928 #ifdef CONFIG_PM_SLEEP ufshcd_wl_suspend(struct device * dev)9929 static int ufshcd_wl_suspend(struct device *dev) 9930 { 9931 struct scsi_device *sdev = to_scsi_device(dev); 9932 struct ufs_hba *hba; 9933 int ret = 0; 9934 ktime_t start = ktime_get(); 9935 9936 hba = shost_priv(sdev->host); 9937 down(&hba->host_sem); 9938 hba->system_suspending = true; 9939 9940 if (pm_runtime_suspended(dev)) 9941 goto out; 9942 9943 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM); 9944 if (ret) { 9945 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9946 up(&hba->host_sem); 9947 } 9948 9949 out: 9950 if (!ret) 9951 hba->is_sys_suspended = true; 9952 trace_ufshcd_wl_suspend(hba, ret, 9953 ktime_to_us(ktime_sub(ktime_get(), start)), 9954 hba->curr_dev_pwr_mode, hba->uic_link_state); 9955 9956 return ret; 9957 } 9958 ufshcd_wl_resume(struct device * dev)9959 static int ufshcd_wl_resume(struct device *dev) 9960 { 9961 struct scsi_device *sdev = to_scsi_device(dev); 9962 struct ufs_hba *hba; 9963 int ret = 0; 9964 ktime_t start = ktime_get(); 9965 9966 hba = shost_priv(sdev->host); 9967 9968 if (pm_runtime_suspended(dev)) 9969 goto out; 9970 9971 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM); 9972 if (ret) 9973 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9974 out: 9975 trace_ufshcd_wl_resume(hba, ret, 9976 ktime_to_us(ktime_sub(ktime_get(), start)), 9977 hba->curr_dev_pwr_mode, hba->uic_link_state); 9978 if (!ret) 9979 hba->is_sys_suspended = false; 9980 hba->system_suspending = false; 9981 up(&hba->host_sem); 9982 return ret; 9983 } 9984 #endif 9985 9986 /** 9987 * ufshcd_suspend - helper function for suspend operations 9988 * @hba: per adapter instance 9989 * 9990 * This function will put disable irqs, turn off clocks 9991 * and set vreg and hba-vreg in lpm mode. 9992 * 9993 * Return: 0 upon success; < 0 upon failure. 9994 */ ufshcd_suspend(struct ufs_hba * hba)9995 static int ufshcd_suspend(struct ufs_hba *hba) 9996 { 9997 int ret; 9998 9999 if (!hba->is_powered) 10000 return 0; 10001 /* 10002 * Disable the host irq as host controller as there won't be any 10003 * host controller transaction expected till resume. 10004 */ 10005 ufshcd_disable_irq(hba); 10006 ret = ufshcd_setup_clocks(hba, false); 10007 if (ret) { 10008 ufshcd_enable_irq(hba); 10009 return ret; 10010 } 10011 if (ufshcd_is_clkgating_allowed(hba)) { 10012 hba->clk_gating.state = CLKS_OFF; 10013 trace_ufshcd_clk_gating(hba, 10014 hba->clk_gating.state); 10015 } 10016 10017 ufshcd_vreg_set_lpm(hba); 10018 /* Put the host controller in low power mode if possible */ 10019 ufshcd_hba_vreg_set_lpm(hba); 10020 ufshcd_pm_qos_update(hba, false); 10021 return ret; 10022 } 10023 10024 #ifdef CONFIG_PM 10025 /** 10026 * ufshcd_resume - helper function for resume operations 10027 * @hba: per adapter instance 10028 * 10029 * This function basically turns on the regulators, clocks and 10030 * irqs of the hba. 10031 * 10032 * Return: 0 for success and non-zero for failure. 10033 */ ufshcd_resume(struct ufs_hba * hba)10034 static int ufshcd_resume(struct ufs_hba *hba) 10035 { 10036 int ret; 10037 10038 if (!hba->is_powered) 10039 return 0; 10040 10041 ufshcd_hba_vreg_set_hpm(hba); 10042 ret = ufshcd_vreg_set_hpm(hba); 10043 if (ret) 10044 goto out; 10045 10046 /* Make sure clocks are enabled before accessing controller */ 10047 ret = ufshcd_setup_clocks(hba, true); 10048 if (ret) 10049 goto disable_vreg; 10050 10051 /* enable the host irq as host controller would be active soon */ 10052 ufshcd_enable_irq(hba); 10053 10054 goto out; 10055 10056 disable_vreg: 10057 ufshcd_vreg_set_lpm(hba); 10058 out: 10059 if (ret) 10060 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret); 10061 return ret; 10062 } 10063 #endif /* CONFIG_PM */ 10064 10065 #ifdef CONFIG_PM_SLEEP 10066 /** 10067 * ufshcd_system_suspend - system suspend callback 10068 * @dev: Device associated with the UFS controller. 10069 * 10070 * Executed before putting the system into a sleep state in which the contents 10071 * of main memory are preserved. 10072 * 10073 * Return: 0 for success and non-zero for failure. 10074 */ ufshcd_system_suspend(struct device * dev)10075 int ufshcd_system_suspend(struct device *dev) 10076 { 10077 struct ufs_hba *hba = dev_get_drvdata(dev); 10078 int ret = 0; 10079 ktime_t start = ktime_get(); 10080 10081 if (pm_runtime_suspended(hba->dev)) 10082 goto out; 10083 10084 ret = ufshcd_suspend(hba); 10085 out: 10086 trace_ufshcd_system_suspend(hba, ret, 10087 ktime_to_us(ktime_sub(ktime_get(), start)), 10088 hba->curr_dev_pwr_mode, hba->uic_link_state); 10089 return ret; 10090 } 10091 EXPORT_SYMBOL(ufshcd_system_suspend); 10092 10093 /** 10094 * ufshcd_system_resume - system resume callback 10095 * @dev: Device associated with the UFS controller. 10096 * 10097 * Executed after waking the system up from a sleep state in which the contents 10098 * of main memory were preserved. 10099 * 10100 * Return: 0 for success and non-zero for failure. 10101 */ ufshcd_system_resume(struct device * dev)10102 int ufshcd_system_resume(struct device *dev) 10103 { 10104 struct ufs_hba *hba = dev_get_drvdata(dev); 10105 ktime_t start = ktime_get(); 10106 int ret = 0; 10107 10108 if (pm_runtime_suspended(hba->dev)) 10109 goto out; 10110 10111 ret = ufshcd_resume(hba); 10112 10113 out: 10114 trace_ufshcd_system_resume(hba, ret, 10115 ktime_to_us(ktime_sub(ktime_get(), start)), 10116 hba->curr_dev_pwr_mode, hba->uic_link_state); 10117 10118 return ret; 10119 } 10120 EXPORT_SYMBOL(ufshcd_system_resume); 10121 #endif /* CONFIG_PM_SLEEP */ 10122 10123 #ifdef CONFIG_PM 10124 /** 10125 * ufshcd_runtime_suspend - runtime suspend callback 10126 * @dev: Device associated with the UFS controller. 10127 * 10128 * Check the description of ufshcd_suspend() function for more details. 10129 * 10130 * Return: 0 for success and non-zero for failure. 10131 */ ufshcd_runtime_suspend(struct device * dev)10132 int ufshcd_runtime_suspend(struct device *dev) 10133 { 10134 struct ufs_hba *hba = dev_get_drvdata(dev); 10135 int ret; 10136 ktime_t start = ktime_get(); 10137 10138 ret = ufshcd_suspend(hba); 10139 10140 trace_ufshcd_runtime_suspend(hba, ret, 10141 ktime_to_us(ktime_sub(ktime_get(), start)), 10142 hba->curr_dev_pwr_mode, hba->uic_link_state); 10143 return ret; 10144 } 10145 EXPORT_SYMBOL(ufshcd_runtime_suspend); 10146 10147 /** 10148 * ufshcd_runtime_resume - runtime resume routine 10149 * @dev: Device associated with the UFS controller. 10150 * 10151 * This function basically brings controller 10152 * to active state. Following operations are done in this function: 10153 * 10154 * 1. Turn on all the controller related clocks 10155 * 2. Turn ON VCC rail 10156 * 10157 * Return: 0 upon success; < 0 upon failure. 10158 */ ufshcd_runtime_resume(struct device * dev)10159 int ufshcd_runtime_resume(struct device *dev) 10160 { 10161 struct ufs_hba *hba = dev_get_drvdata(dev); 10162 int ret; 10163 ktime_t start = ktime_get(); 10164 10165 ret = ufshcd_resume(hba); 10166 10167 trace_ufshcd_runtime_resume(hba, ret, 10168 ktime_to_us(ktime_sub(ktime_get(), start)), 10169 hba->curr_dev_pwr_mode, hba->uic_link_state); 10170 return ret; 10171 } 10172 EXPORT_SYMBOL(ufshcd_runtime_resume); 10173 #endif /* CONFIG_PM */ 10174 ufshcd_wl_shutdown(struct device * dev)10175 static void ufshcd_wl_shutdown(struct device *dev) 10176 { 10177 struct scsi_device *sdev = to_scsi_device(dev); 10178 struct ufs_hba *hba = shost_priv(sdev->host); 10179 10180 down(&hba->host_sem); 10181 hba->shutting_down = true; 10182 up(&hba->host_sem); 10183 10184 /* Turn on everything while shutting down */ 10185 ufshcd_rpm_get_sync(hba); 10186 scsi_device_quiesce(sdev); 10187 shost_for_each_device(sdev, hba->host) { 10188 if (sdev == hba->ufs_device_wlun) 10189 continue; 10190 mutex_lock(&sdev->state_mutex); 10191 scsi_device_set_state(sdev, SDEV_OFFLINE); 10192 mutex_unlock(&sdev->state_mutex); 10193 } 10194 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10195 10196 /* 10197 * Next, turn off the UFS controller and the UFS regulators. Disable 10198 * clocks. 10199 */ 10200 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba)) 10201 ufshcd_suspend(hba); 10202 10203 hba->is_powered = false; 10204 } 10205 10206 /** 10207 * ufshcd_remove - de-allocate SCSI host and host memory space 10208 * data structure memory 10209 * @hba: per adapter instance 10210 */ ufshcd_remove(struct ufs_hba * hba)10211 void ufshcd_remove(struct ufs_hba *hba) 10212 { 10213 if (hba->ufs_device_wlun) 10214 ufshcd_rpm_get_sync(hba); 10215 ufs_hwmon_remove(hba); 10216 ufs_bsg_remove(hba); 10217 ufs_sysfs_remove_nodes(hba->dev); 10218 cancel_delayed_work_sync(&hba->ufs_rtc_update_work); 10219 blk_mq_destroy_queue(hba->tmf_queue); 10220 blk_put_queue(hba->tmf_queue); 10221 blk_mq_free_tag_set(&hba->tmf_tag_set); 10222 if (hba->scsi_host_added) 10223 scsi_remove_host(hba->host); 10224 /* disable interrupts */ 10225 ufshcd_disable_intr(hba, hba->intr_mask); 10226 ufshcd_hba_stop(hba); 10227 ufshcd_hba_exit(hba); 10228 } 10229 EXPORT_SYMBOL_GPL(ufshcd_remove); 10230 10231 #ifdef CONFIG_PM_SLEEP ufshcd_system_freeze(struct device * dev)10232 int ufshcd_system_freeze(struct device *dev) 10233 { 10234 10235 return ufshcd_system_suspend(dev); 10236 10237 } 10238 EXPORT_SYMBOL_GPL(ufshcd_system_freeze); 10239 ufshcd_system_restore(struct device * dev)10240 int ufshcd_system_restore(struct device *dev) 10241 { 10242 10243 struct ufs_hba *hba = dev_get_drvdata(dev); 10244 int ret; 10245 10246 ret = ufshcd_system_resume(dev); 10247 if (ret) 10248 return ret; 10249 10250 /* Configure UTRL and UTMRL base address registers */ 10251 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 10252 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 10253 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 10254 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 10255 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 10256 REG_UTP_TASK_REQ_LIST_BASE_L); 10257 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 10258 REG_UTP_TASK_REQ_LIST_BASE_H); 10259 /* 10260 * Make sure that UTRL and UTMRL base address registers 10261 * are updated with the latest queue addresses. Only after 10262 * updating these addresses, we can queue the new commands. 10263 */ 10264 ufshcd_readl(hba, REG_UTP_TASK_REQ_LIST_BASE_H); 10265 10266 return 0; 10267 10268 } 10269 EXPORT_SYMBOL_GPL(ufshcd_system_restore); 10270 ufshcd_system_thaw(struct device * dev)10271 int ufshcd_system_thaw(struct device *dev) 10272 { 10273 return ufshcd_system_resume(dev); 10274 } 10275 EXPORT_SYMBOL_GPL(ufshcd_system_thaw); 10276 #endif /* CONFIG_PM_SLEEP */ 10277 10278 /** 10279 * ufshcd_set_dma_mask - Set dma mask based on the controller 10280 * addressing capability 10281 * @hba: per adapter instance 10282 * 10283 * Return: 0 for success, non-zero for failure. 10284 */ ufshcd_set_dma_mask(struct ufs_hba * hba)10285 static int ufshcd_set_dma_mask(struct ufs_hba *hba) 10286 { 10287 if (hba->vops && hba->vops->set_dma_mask) 10288 return hba->vops->set_dma_mask(hba); 10289 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { 10290 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) 10291 return 0; 10292 } 10293 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); 10294 } 10295 10296 /** 10297 * ufshcd_devres_release - devres cleanup handler, invoked during release of 10298 * hba->dev 10299 * @host: pointer to SCSI host 10300 */ ufshcd_devres_release(void * host)10301 static void ufshcd_devres_release(void *host) 10302 { 10303 scsi_host_put(host); 10304 } 10305 10306 /** 10307 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA) 10308 * @dev: pointer to device handle 10309 * @hba_handle: driver private handle 10310 * 10311 * Return: 0 on success, non-zero value on failure. 10312 * 10313 * NOTE: There is no corresponding ufshcd_dealloc_host() because this function 10314 * keeps track of its allocations using devres and deallocates everything on 10315 * device removal automatically. 10316 */ ufshcd_alloc_host(struct device * dev,struct ufs_hba ** hba_handle)10317 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle) 10318 { 10319 struct Scsi_Host *host; 10320 struct ufs_hba *hba; 10321 int err = 0; 10322 10323 if (!dev) { 10324 dev_err(dev, 10325 "Invalid memory reference for dev is NULL\n"); 10326 err = -ENODEV; 10327 goto out_error; 10328 } 10329 10330 host = scsi_host_alloc(&ufshcd_driver_template, 10331 sizeof(struct ufs_hba)); 10332 if (!host) { 10333 dev_err(dev, "scsi_host_alloc failed\n"); 10334 err = -ENOMEM; 10335 goto out_error; 10336 } 10337 10338 err = devm_add_action_or_reset(dev, ufshcd_devres_release, 10339 host); 10340 if (err) 10341 return dev_err_probe(dev, err, 10342 "failed to add ufshcd dealloc action\n"); 10343 10344 host->nr_maps = HCTX_TYPE_POLL + 1; 10345 hba = shost_priv(host); 10346 hba->host = host; 10347 hba->dev = dev; 10348 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL; 10349 hba->nop_out_timeout = NOP_OUT_TIMEOUT; 10350 ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry)); 10351 INIT_LIST_HEAD(&hba->clk_list_head); 10352 spin_lock_init(&hba->outstanding_lock); 10353 10354 *hba_handle = hba; 10355 10356 out_error: 10357 return err; 10358 } 10359 EXPORT_SYMBOL(ufshcd_alloc_host); 10360 10361 /* This function exists because blk_mq_alloc_tag_set() requires this. */ ufshcd_queue_tmf(struct blk_mq_hw_ctx * hctx,const struct blk_mq_queue_data * qd)10362 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx, 10363 const struct blk_mq_queue_data *qd) 10364 { 10365 WARN_ON_ONCE(true); 10366 return BLK_STS_NOTSUPP; 10367 } 10368 10369 static const struct blk_mq_ops ufshcd_tmf_ops = { 10370 .queue_rq = ufshcd_queue_tmf, 10371 }; 10372 ufshcd_add_scsi_host(struct ufs_hba * hba)10373 static int ufshcd_add_scsi_host(struct ufs_hba *hba) 10374 { 10375 int err; 10376 10377 if (is_mcq_supported(hba)) { 10378 ufshcd_mcq_enable(hba); 10379 err = ufshcd_alloc_mcq(hba); 10380 if (!err) { 10381 ufshcd_config_mcq(hba); 10382 } else { 10383 /* Continue with SDB mode */ 10384 ufshcd_mcq_disable(hba); 10385 use_mcq_mode = false; 10386 dev_err(hba->dev, "MCQ mode is disabled, err=%d\n", 10387 err); 10388 } 10389 } 10390 if (!is_mcq_supported(hba) && !hba->lsdb_sup) { 10391 dev_err(hba->dev, 10392 "%s: failed to initialize (legacy doorbell mode not supported)\n", 10393 __func__); 10394 return -EINVAL; 10395 } 10396 10397 err = scsi_add_host(hba->host, hba->dev); 10398 if (err) { 10399 dev_err(hba->dev, "scsi_add_host failed\n"); 10400 return err; 10401 } 10402 hba->scsi_host_added = true; 10403 10404 hba->tmf_tag_set = (struct blk_mq_tag_set) { 10405 .nr_hw_queues = 1, 10406 .queue_depth = hba->nutmrs, 10407 .ops = &ufshcd_tmf_ops, 10408 }; 10409 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set); 10410 if (err < 0) 10411 goto remove_scsi_host; 10412 hba->tmf_queue = blk_mq_alloc_queue(&hba->tmf_tag_set, NULL, NULL); 10413 if (IS_ERR(hba->tmf_queue)) { 10414 err = PTR_ERR(hba->tmf_queue); 10415 goto free_tmf_tag_set; 10416 } 10417 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs, 10418 sizeof(*hba->tmf_rqs), GFP_KERNEL); 10419 if (!hba->tmf_rqs) { 10420 err = -ENOMEM; 10421 goto free_tmf_queue; 10422 } 10423 10424 return 0; 10425 10426 free_tmf_queue: 10427 blk_mq_destroy_queue(hba->tmf_queue); 10428 blk_put_queue(hba->tmf_queue); 10429 10430 free_tmf_tag_set: 10431 blk_mq_free_tag_set(&hba->tmf_tag_set); 10432 10433 remove_scsi_host: 10434 if (hba->scsi_host_added) 10435 scsi_remove_host(hba->host); 10436 10437 return err; 10438 } 10439 10440 /** 10441 * ufshcd_init - Driver initialization routine 10442 * @hba: per-adapter instance 10443 * @mmio_base: base register address 10444 * @irq: Interrupt line of device 10445 * 10446 * Return: 0 on success, non-zero value on failure. 10447 */ ufshcd_init(struct ufs_hba * hba,void __iomem * mmio_base,unsigned int irq)10448 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) 10449 { 10450 int err; 10451 struct Scsi_Host *host = hba->host; 10452 struct device *dev = hba->dev; 10453 10454 /* 10455 * dev_set_drvdata() must be called before any callbacks are registered 10456 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon, 10457 * sysfs). 10458 */ 10459 dev_set_drvdata(dev, hba); 10460 10461 if (!mmio_base) { 10462 dev_err(hba->dev, 10463 "Invalid memory reference for mmio_base is NULL\n"); 10464 err = -ENODEV; 10465 goto out_error; 10466 } 10467 10468 hba->mmio_base = mmio_base; 10469 hba->irq = irq; 10470 hba->vps = &ufs_hba_vps; 10471 10472 /* 10473 * Initialize clk_gating.lock early since it is being used in 10474 * ufshcd_setup_clocks() 10475 */ 10476 spin_lock_init(&hba->clk_gating.lock); 10477 10478 /* 10479 * Set the default power management level for runtime and system PM. 10480 * Host controller drivers can override them in their 10481 * 'ufs_hba_variant_ops::init' callback. 10482 * 10483 * Default power saving mode is to keep UFS link in Hibern8 state 10484 * and UFS device in sleep state. 10485 */ 10486 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10487 UFS_SLEEP_PWR_MODE, 10488 UIC_LINK_HIBERN8_STATE); 10489 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10490 UFS_SLEEP_PWR_MODE, 10491 UIC_LINK_HIBERN8_STATE); 10492 10493 err = ufshcd_hba_init(hba); 10494 if (err) 10495 goto out_error; 10496 10497 /* Read capabilities registers */ 10498 err = ufshcd_hba_capabilities(hba); 10499 if (err) 10500 goto out_disable; 10501 10502 /* Get UFS version supported by the controller */ 10503 hba->ufs_version = ufshcd_get_ufs_version(hba); 10504 10505 /* Get Interrupt bit mask per version */ 10506 hba->intr_mask = ufshcd_get_intr_mask(hba); 10507 10508 err = ufshcd_set_dma_mask(hba); 10509 if (err) { 10510 dev_err(hba->dev, "set dma mask failed\n"); 10511 goto out_disable; 10512 } 10513 10514 /* Allocate memory for host memory space */ 10515 err = ufshcd_memory_alloc(hba); 10516 if (err) { 10517 dev_err(hba->dev, "Memory allocation failed\n"); 10518 goto out_disable; 10519 } 10520 10521 /* Configure LRB */ 10522 ufshcd_host_memory_configure(hba); 10523 10524 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 10525 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED; 10526 host->max_id = UFSHCD_MAX_ID; 10527 host->max_lun = UFS_MAX_LUNS; 10528 host->max_channel = UFSHCD_MAX_CHANNEL; 10529 host->unique_id = host->host_no; 10530 host->max_cmd_len = UFS_CDB_SIZE; 10531 host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING); 10532 10533 /* Use default RPM delay if host not set */ 10534 if (host->rpm_autosuspend_delay == 0) 10535 host->rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS; 10536 10537 hba->max_pwr_info.is_valid = false; 10538 10539 /* Initialize work queues */ 10540 hba->eh_wq = alloc_ordered_workqueue("ufs_eh_wq_%d", WQ_MEM_RECLAIM, 10541 hba->host->host_no); 10542 if (!hba->eh_wq) { 10543 dev_err(hba->dev, "%s: failed to create eh workqueue\n", 10544 __func__); 10545 err = -ENOMEM; 10546 goto out_disable; 10547 } 10548 INIT_WORK(&hba->eh_work, ufshcd_err_handler); 10549 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); 10550 10551 sema_init(&hba->host_sem, 1); 10552 10553 /* Initialize UIC command mutex */ 10554 mutex_init(&hba->uic_cmd_mutex); 10555 10556 /* Initialize mutex for device management commands */ 10557 mutex_init(&hba->dev_cmd.lock); 10558 10559 /* Initialize mutex for exception event control */ 10560 mutex_init(&hba->ee_ctrl_mutex); 10561 10562 mutex_init(&hba->wb_mutex); 10563 init_rwsem(&hba->clk_scaling_lock); 10564 10565 ufshcd_init_clk_gating(hba); 10566 10567 ufshcd_init_clk_scaling(hba); 10568 10569 /* 10570 * In order to avoid any spurious interrupt immediately after 10571 * registering UFS controller interrupt handler, clear any pending UFS 10572 * interrupt status and disable all the UFS interrupts. 10573 */ 10574 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 10575 REG_INTERRUPT_STATUS); 10576 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 10577 /* 10578 * Make sure that UFS interrupts are disabled and any pending interrupt 10579 * status is cleared before registering UFS interrupt handler. 10580 */ 10581 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 10582 10583 /* IRQ registration */ 10584 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); 10585 if (err) { 10586 dev_err(hba->dev, "request irq failed\n"); 10587 goto out_disable; 10588 } else { 10589 hba->is_irq_enabled = true; 10590 } 10591 10592 /* Reset the attached device */ 10593 ufshcd_device_reset(hba); 10594 10595 ufshcd_init_crypto(hba); 10596 10597 /* Host controller enable */ 10598 err = ufshcd_hba_enable(hba); 10599 if (err) { 10600 dev_err(hba->dev, "Host controller enable failed\n"); 10601 ufshcd_print_evt_hist(hba); 10602 ufshcd_print_host_state(hba); 10603 goto out_disable; 10604 } 10605 10606 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work, ufshcd_rpm_dev_flush_recheck_work); 10607 INIT_DELAYED_WORK(&hba->ufs_rtc_update_work, ufshcd_rtc_work); 10608 10609 /* Set the default auto-hiberate idle timer value to 150 ms */ 10610 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) { 10611 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) | 10612 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3); 10613 } 10614 10615 /* Hold auto suspend until async scan completes */ 10616 pm_runtime_get_sync(dev); 10617 10618 /* 10619 * We are assuming that device wasn't put in sleep/power-down 10620 * state exclusively during the boot stage before kernel. 10621 * This assumption helps avoid doing link startup twice during 10622 * ufshcd_probe_hba(). 10623 */ 10624 ufshcd_set_ufs_dev_active(hba); 10625 10626 /* Initialize hba, detect and initialize UFS device */ 10627 ktime_t probe_start = ktime_get(); 10628 10629 hba->ufshcd_state = UFSHCD_STATE_RESET; 10630 10631 err = ufshcd_link_startup(hba); 10632 if (err) 10633 goto out_disable; 10634 10635 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) 10636 goto initialized; 10637 10638 /* Debug counters initialization */ 10639 ufshcd_clear_dbg_ufs_stats(hba); 10640 10641 /* UniPro link is active now */ 10642 ufshcd_set_link_active(hba); 10643 10644 /* Verify device initialization by sending NOP OUT UPIU */ 10645 err = ufshcd_verify_dev_init(hba); 10646 if (err) 10647 goto out_disable; 10648 10649 /* Initiate UFS initialization, and waiting until completion */ 10650 err = ufshcd_complete_dev_init(hba); 10651 if (err) 10652 goto out_disable; 10653 10654 err = ufshcd_device_params_init(hba); 10655 if (err) 10656 goto out_disable; 10657 10658 err = ufshcd_post_device_init(hba); 10659 10660 initialized: 10661 ufshcd_process_probe_result(hba, probe_start, err); 10662 if (err) 10663 goto out_disable; 10664 10665 err = ufshcd_add_scsi_host(hba); 10666 if (err) 10667 goto out_disable; 10668 10669 async_schedule(ufshcd_async_scan, hba); 10670 ufs_sysfs_add_nodes(hba->dev); 10671 10672 device_enable_async_suspend(dev); 10673 ufshcd_pm_qos_init(hba); 10674 return 0; 10675 10676 out_disable: 10677 hba->is_irq_enabled = false; 10678 ufshcd_hba_exit(hba); 10679 out_error: 10680 return err; 10681 } 10682 EXPORT_SYMBOL_GPL(ufshcd_init); 10683 ufshcd_resume_complete(struct device * dev)10684 void ufshcd_resume_complete(struct device *dev) 10685 { 10686 struct ufs_hba *hba = dev_get_drvdata(dev); 10687 10688 if (hba->complete_put) { 10689 ufshcd_rpm_put(hba); 10690 hba->complete_put = false; 10691 } 10692 } 10693 EXPORT_SYMBOL_GPL(ufshcd_resume_complete); 10694 ufshcd_rpm_ok_for_spm(struct ufs_hba * hba)10695 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba) 10696 { 10697 struct device *dev = &hba->ufs_device_wlun->sdev_gendev; 10698 enum ufs_dev_pwr_mode dev_pwr_mode; 10699 enum uic_link_state link_state; 10700 unsigned long flags; 10701 bool res; 10702 10703 spin_lock_irqsave(&dev->power.lock, flags); 10704 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl); 10705 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl); 10706 res = pm_runtime_suspended(dev) && 10707 hba->curr_dev_pwr_mode == dev_pwr_mode && 10708 hba->uic_link_state == link_state && 10709 !hba->dev_info.b_rpm_dev_flush_capable; 10710 spin_unlock_irqrestore(&dev->power.lock, flags); 10711 10712 return res; 10713 } 10714 __ufshcd_suspend_prepare(struct device * dev,bool rpm_ok_for_spm)10715 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm) 10716 { 10717 struct ufs_hba *hba = dev_get_drvdata(dev); 10718 int ret; 10719 10720 /* 10721 * SCSI assumes that runtime-pm and system-pm for scsi drivers 10722 * are same. And it doesn't wake up the device for system-suspend 10723 * if it's runtime suspended. But ufs doesn't follow that. 10724 * Refer ufshcd_resume_complete() 10725 */ 10726 if (hba->ufs_device_wlun) { 10727 /* Prevent runtime suspend */ 10728 ufshcd_rpm_get_noresume(hba); 10729 /* 10730 * Check if already runtime suspended in same state as system 10731 * suspend would be. 10732 */ 10733 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) { 10734 /* RPM state is not ok for SPM, so runtime resume */ 10735 ret = ufshcd_rpm_resume(hba); 10736 if (ret < 0 && ret != -EACCES) { 10737 ufshcd_rpm_put(hba); 10738 return ret; 10739 } 10740 } 10741 hba->complete_put = true; 10742 } 10743 return 0; 10744 } 10745 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare); 10746 ufshcd_suspend_prepare(struct device * dev)10747 int ufshcd_suspend_prepare(struct device *dev) 10748 { 10749 return __ufshcd_suspend_prepare(dev, true); 10750 } 10751 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare); 10752 10753 #ifdef CONFIG_PM_SLEEP ufshcd_wl_poweroff(struct device * dev)10754 static int ufshcd_wl_poweroff(struct device *dev) 10755 { 10756 struct scsi_device *sdev = to_scsi_device(dev); 10757 struct ufs_hba *hba = shost_priv(sdev->host); 10758 10759 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10760 return 0; 10761 } 10762 #endif 10763 ufshcd_wl_probe(struct device * dev)10764 static int ufshcd_wl_probe(struct device *dev) 10765 { 10766 struct scsi_device *sdev = to_scsi_device(dev); 10767 10768 if (!is_device_wlun(sdev)) 10769 return -ENODEV; 10770 10771 blk_pm_runtime_init(sdev->request_queue, dev); 10772 pm_runtime_set_autosuspend_delay(dev, 0); 10773 pm_runtime_allow(dev); 10774 10775 return 0; 10776 } 10777 ufshcd_wl_remove(struct device * dev)10778 static int ufshcd_wl_remove(struct device *dev) 10779 { 10780 pm_runtime_forbid(dev); 10781 return 0; 10782 } 10783 10784 static const struct dev_pm_ops ufshcd_wl_pm_ops = { 10785 #ifdef CONFIG_PM_SLEEP 10786 .suspend = ufshcd_wl_suspend, 10787 .resume = ufshcd_wl_resume, 10788 .freeze = ufshcd_wl_suspend, 10789 .thaw = ufshcd_wl_resume, 10790 .poweroff = ufshcd_wl_poweroff, 10791 .restore = ufshcd_wl_resume, 10792 #endif 10793 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL) 10794 }; 10795 ufshcd_check_header_layout(void)10796 static void ufshcd_check_header_layout(void) 10797 { 10798 /* 10799 * gcc compilers before version 10 cannot do constant-folding for 10800 * sub-byte bitfields. Hence skip the layout checks for gcc 9 and 10801 * before. 10802 */ 10803 if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000) 10804 return; 10805 10806 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10807 .cci = 3})[0] != 3); 10808 10809 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10810 .ehs_length = 2})[1] != 2); 10811 10812 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10813 .enable_crypto = 1})[2] 10814 != 0x80); 10815 10816 BUILD_BUG_ON((((u8 *)&(struct request_desc_header){ 10817 .command_type = 5, 10818 .data_direction = 3, 10819 .interrupt = 1, 10820 })[3]) != ((5 << 4) | (3 << 1) | 1)); 10821 10822 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10823 .dunl = cpu_to_le32(0xdeadbeef)})[1] != 10824 cpu_to_le32(0xdeadbeef)); 10825 10826 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10827 .ocs = 4})[8] != 4); 10828 10829 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10830 .cds = 5})[9] != 5); 10831 10832 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10833 .dunu = cpu_to_le32(0xbadcafe)})[3] != 10834 cpu_to_le32(0xbadcafe)); 10835 10836 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10837 .iid = 0xf })[4] != 0xf0); 10838 10839 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10840 .command_set_type = 0xf })[4] != 0xf); 10841 } 10842 10843 /* 10844 * ufs_dev_wlun_template - describes ufs device wlun 10845 * ufs-device wlun - used to send pm commands 10846 * All luns are consumers of ufs-device wlun. 10847 * 10848 * Currently, no sd driver is present for wluns. 10849 * Hence the no specific pm operations are performed. 10850 * With ufs design, SSU should be sent to ufs-device wlun. 10851 * Hence register a scsi driver for ufs wluns only. 10852 */ 10853 static struct scsi_driver ufs_dev_wlun_template = { 10854 .gendrv = { 10855 .name = "ufs_device_wlun", 10856 .probe = ufshcd_wl_probe, 10857 .remove = ufshcd_wl_remove, 10858 .pm = &ufshcd_wl_pm_ops, 10859 .shutdown = ufshcd_wl_shutdown, 10860 }, 10861 }; 10862 ufshcd_core_init(void)10863 static int __init ufshcd_core_init(void) 10864 { 10865 int ret; 10866 10867 ufshcd_check_header_layout(); 10868 10869 ufs_debugfs_init(); 10870 10871 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv); 10872 if (ret) 10873 ufs_debugfs_exit(); 10874 return ret; 10875 } 10876 ufshcd_core_exit(void)10877 static void __exit ufshcd_core_exit(void) 10878 { 10879 ufs_debugfs_exit(); 10880 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv); 10881 } 10882 10883 module_init(ufshcd_core_init); 10884 module_exit(ufshcd_core_exit); 10885 10886 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); 10887 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); 10888 MODULE_DESCRIPTION("Generic UFS host controller driver Core"); 10889 MODULE_SOFTDEP("pre: governor_simpleondemand"); 10890 MODULE_LICENSE("GPL"); 10891