xref: /linux/drivers/ufs/host/ufs-qcom.c (revision 88e45067a30918ebb4942120892963e2311330af)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/acpi.h>
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/devfreq.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/interconnect.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset-controller.h>
17 #include <linux/time.h>
18 
19 #include <soc/qcom/ice.h>
20 
21 #include <ufs/ufshcd.h>
22 #include <ufs/ufshci.h>
23 #include <ufs/ufs_quirks.h>
24 #include <ufs/unipro.h>
25 #include "ufshcd-pltfrm.h"
26 #include "ufs-qcom.h"
27 
28 #define MCQ_QCFGPTR_MASK	GENMASK(7, 0)
29 #define MCQ_QCFGPTR_UNIT	0x200
30 #define MCQ_SQATTR_OFFSET(c) \
31 	((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT)
32 #define MCQ_QCFG_SIZE	0x40
33 
34 enum {
35 	TSTBUS_UAWM,
36 	TSTBUS_UARM,
37 	TSTBUS_TXUC,
38 	TSTBUS_RXUC,
39 	TSTBUS_DFC,
40 	TSTBUS_TRLUT,
41 	TSTBUS_TMRLUT,
42 	TSTBUS_OCSC,
43 	TSTBUS_UTP_HCI,
44 	TSTBUS_COMBINED,
45 	TSTBUS_WRAPPER,
46 	TSTBUS_UNIPRO,
47 	TSTBUS_MAX,
48 };
49 
50 #define QCOM_UFS_MAX_GEAR 5
51 #define QCOM_UFS_MAX_LANE 2
52 
53 enum {
54 	MODE_MIN,
55 	MODE_PWM,
56 	MODE_HS_RA,
57 	MODE_HS_RB,
58 	MODE_MAX,
59 };
60 
61 static const struct __ufs_qcom_bw_table {
62 	u32 mem_bw;
63 	u32 cfg_bw;
64 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = {
65 	[MODE_MIN][0][0]		   = { 0,		0 }, /* Bandwidth values in KB/s */
66 	[MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922,		1000 },
67 	[MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844,		1000 },
68 	[MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688,		1000 },
69 	[MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376,		1000 },
70 	[MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752,		1000 },
71 	[MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844,		1000 },
72 	[MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688,		1000 },
73 	[MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376,		1000 },
74 	[MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752,		1000 },
75 	[MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504,		1000 },
76 	[MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796,		1000 },
77 	[MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591,		1000 },
78 	[MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582,	102400 },
79 	[MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200,	204800 },
80 	[MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800,	409600 },
81 	[MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591,		1000 },
82 	[MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181,		1000 },
83 	[MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582,	204800 },
84 	[MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200,	409600 },
85 	[MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800,	819200 },
86 	[MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422,		1000 },
87 	[MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189,		1000 },
88 	[MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582,	102400 },
89 	[MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200,	204800 },
90 	[MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800,	409600 },
91 	[MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189,		1000 },
92 	[MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378,		1000 },
93 	[MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582,	204800 },
94 	[MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200,	409600 },
95 	[MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800,	819200 },
96 	[MODE_MAX][0][0]		    = { 7643136,	819200 },
97 };
98 
99 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
100 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up);
101 
rcdev_to_ufs_host(struct reset_controller_dev * rcd)102 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
103 {
104 	return container_of(rcd, struct ufs_qcom_host, rcdev);
105 }
106 
107 #ifdef CONFIG_SCSI_UFS_CRYPTO
108 
ufs_qcom_ice_enable(struct ufs_qcom_host * host)109 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
110 {
111 	if (host->hba->caps & UFSHCD_CAP_CRYPTO)
112 		qcom_ice_enable(host->ice);
113 }
114 
115 static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops; /* forward decl */
116 
ufs_qcom_ice_init(struct ufs_qcom_host * host)117 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
118 {
119 	struct ufs_hba *hba = host->hba;
120 	struct blk_crypto_profile *profile = &hba->crypto_profile;
121 	struct device *dev = hba->dev;
122 	struct qcom_ice *ice;
123 	union ufs_crypto_capabilities caps;
124 	union ufs_crypto_cap_entry cap;
125 	int err;
126 	int i;
127 
128 	ice = of_qcom_ice_get(dev);
129 	if (ice == ERR_PTR(-EOPNOTSUPP)) {
130 		dev_warn(dev, "Disabling inline encryption support\n");
131 		ice = NULL;
132 	}
133 
134 	if (IS_ERR_OR_NULL(ice))
135 		return PTR_ERR_OR_ZERO(ice);
136 
137 	host->ice = ice;
138 
139 	/* Initialize the blk_crypto_profile */
140 
141 	caps.reg_val = cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP));
142 
143 	/* The number of keyslots supported is (CFGC+1) */
144 	err = devm_blk_crypto_profile_init(dev, profile, caps.config_count + 1);
145 	if (err)
146 		return err;
147 
148 	profile->ll_ops = ufs_qcom_crypto_ops;
149 	profile->max_dun_bytes_supported = 8;
150 	profile->dev = dev;
151 
152 	/*
153 	 * Currently this driver only supports AES-256-XTS.  All known versions
154 	 * of ICE support it, but to be safe make sure it is really declared in
155 	 * the crypto capability registers.  The crypto capability registers
156 	 * also give the supported data unit size(s).
157 	 */
158 	for (i = 0; i < caps.num_crypto_cap; i++) {
159 		cap.reg_val = cpu_to_le32(ufshcd_readl(hba,
160 						       REG_UFS_CRYPTOCAP +
161 						       i * sizeof(__le32)));
162 		if (cap.algorithm_id == UFS_CRYPTO_ALG_AES_XTS &&
163 		    cap.key_size == UFS_CRYPTO_KEY_SIZE_256)
164 			profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |=
165 				cap.sdus_mask * 512;
166 	}
167 
168 	hba->caps |= UFSHCD_CAP_CRYPTO;
169 	hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE;
170 	return 0;
171 }
172 
ufs_qcom_ice_resume(struct ufs_qcom_host * host)173 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
174 {
175 	if (host->hba->caps & UFSHCD_CAP_CRYPTO)
176 		return qcom_ice_resume(host->ice);
177 
178 	return 0;
179 }
180 
ufs_qcom_ice_suspend(struct ufs_qcom_host * host)181 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
182 {
183 	if (host->hba->caps & UFSHCD_CAP_CRYPTO)
184 		return qcom_ice_suspend(host->ice);
185 
186 	return 0;
187 }
188 
ufs_qcom_ice_keyslot_program(struct blk_crypto_profile * profile,const struct blk_crypto_key * key,unsigned int slot)189 static int ufs_qcom_ice_keyslot_program(struct blk_crypto_profile *profile,
190 					const struct blk_crypto_key *key,
191 					unsigned int slot)
192 {
193 	struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile);
194 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
195 	int err;
196 
197 	/* Only AES-256-XTS has been tested so far. */
198 	if (key->crypto_cfg.crypto_mode != BLK_ENCRYPTION_MODE_AES_256_XTS)
199 		return -EOPNOTSUPP;
200 
201 	ufshcd_hold(hba);
202 	err = qcom_ice_program_key(host->ice,
203 				   QCOM_ICE_CRYPTO_ALG_AES_XTS,
204 				   QCOM_ICE_CRYPTO_KEY_SIZE_256,
205 				   key->raw,
206 				   key->crypto_cfg.data_unit_size / 512,
207 				   slot);
208 	ufshcd_release(hba);
209 	return err;
210 }
211 
ufs_qcom_ice_keyslot_evict(struct blk_crypto_profile * profile,const struct blk_crypto_key * key,unsigned int slot)212 static int ufs_qcom_ice_keyslot_evict(struct blk_crypto_profile *profile,
213 				      const struct blk_crypto_key *key,
214 				      unsigned int slot)
215 {
216 	struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile);
217 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
218 	int err;
219 
220 	ufshcd_hold(hba);
221 	err = qcom_ice_evict_key(host->ice, slot);
222 	ufshcd_release(hba);
223 	return err;
224 }
225 
226 static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops = {
227 	.keyslot_program	= ufs_qcom_ice_keyslot_program,
228 	.keyslot_evict		= ufs_qcom_ice_keyslot_evict,
229 };
230 
231 #else
232 
ufs_qcom_ice_enable(struct ufs_qcom_host * host)233 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
234 {
235 }
236 
ufs_qcom_ice_init(struct ufs_qcom_host * host)237 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
238 {
239 	return 0;
240 }
241 
ufs_qcom_ice_resume(struct ufs_qcom_host * host)242 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
243 {
244 	return 0;
245 }
246 
ufs_qcom_ice_suspend(struct ufs_qcom_host * host)247 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
248 {
249 	return 0;
250 }
251 #endif
252 
ufs_qcom_disable_lane_clks(struct ufs_qcom_host * host)253 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
254 {
255 	if (!host->is_lane_clks_enabled)
256 		return;
257 
258 	clk_bulk_disable_unprepare(host->num_clks, host->clks);
259 
260 	host->is_lane_clks_enabled = false;
261 }
262 
ufs_qcom_enable_lane_clks(struct ufs_qcom_host * host)263 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
264 {
265 	int err;
266 
267 	err = clk_bulk_prepare_enable(host->num_clks, host->clks);
268 	if (err)
269 		return err;
270 
271 	host->is_lane_clks_enabled = true;
272 
273 	return 0;
274 }
275 
ufs_qcom_init_lane_clks(struct ufs_qcom_host * host)276 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
277 {
278 	int err;
279 	struct device *dev = host->hba->dev;
280 
281 	if (has_acpi_companion(dev))
282 		return 0;
283 
284 	err = devm_clk_bulk_get_all(dev, &host->clks);
285 	if (err <= 0)
286 		return err;
287 
288 	host->num_clks = err;
289 
290 	return 0;
291 }
292 
ufs_qcom_check_hibern8(struct ufs_hba * hba)293 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
294 {
295 	int err;
296 	u32 tx_fsm_val;
297 	unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
298 
299 	do {
300 		err = ufshcd_dme_get(hba,
301 				UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
302 					UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
303 				&tx_fsm_val);
304 		if (err || tx_fsm_val == TX_FSM_HIBERN8)
305 			break;
306 
307 		/* sleep for max. 200us */
308 		usleep_range(100, 200);
309 	} while (time_before(jiffies, timeout));
310 
311 	/*
312 	 * we might have scheduled out for long during polling so
313 	 * check the state again.
314 	 */
315 	if (time_after(jiffies, timeout))
316 		err = ufshcd_dme_get(hba,
317 				UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
318 					UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
319 				&tx_fsm_val);
320 
321 	if (err) {
322 		dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
323 				__func__, err);
324 	} else if (tx_fsm_val != TX_FSM_HIBERN8) {
325 		err = tx_fsm_val;
326 		dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
327 				__func__, err);
328 	}
329 
330 	return err;
331 }
332 
ufs_qcom_select_unipro_mode(struct ufs_qcom_host * host)333 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
334 {
335 	ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1);
336 
337 	if (host->hw_ver.major >= 0x05)
338 		ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0);
339 }
340 
341 /*
342  * ufs_qcom_host_reset - reset host controller and PHY
343  */
ufs_qcom_host_reset(struct ufs_hba * hba)344 static int ufs_qcom_host_reset(struct ufs_hba *hba)
345 {
346 	int ret;
347 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
348 	bool reenable_intr;
349 
350 	if (!host->core_reset)
351 		return 0;
352 
353 	reenable_intr = hba->is_irq_enabled;
354 	ufshcd_disable_irq(hba);
355 
356 	ret = reset_control_assert(host->core_reset);
357 	if (ret) {
358 		dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
359 				 __func__, ret);
360 		return ret;
361 	}
362 
363 	/*
364 	 * The hardware requirement for delay between assert/deassert
365 	 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
366 	 * ~125us (4/32768). To be on the safe side add 200us delay.
367 	 */
368 	usleep_range(200, 210);
369 
370 	ret = reset_control_deassert(host->core_reset);
371 	if (ret) {
372 		dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
373 				 __func__, ret);
374 		return ret;
375 	}
376 
377 	usleep_range(1000, 1100);
378 
379 	if (reenable_intr)
380 		ufshcd_enable_irq(hba);
381 
382 	return 0;
383 }
384 
ufs_qcom_get_hs_gear(struct ufs_hba * hba)385 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
386 {
387 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
388 
389 	if (host->hw_ver.major >= 0x4)
390 		return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0));
391 
392 	/* Default is HS-G3 */
393 	return UFS_HS_G3;
394 }
395 
ufs_qcom_power_up_sequence(struct ufs_hba * hba)396 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
397 {
398 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
399 	struct ufs_host_params *host_params = &host->host_params;
400 	struct phy *phy = host->generic_phy;
401 	enum phy_mode mode;
402 	int ret;
403 
404 	/*
405 	 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
406 	 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
407 	 * so that the subsequent power mode change shall stick to Rate-A.
408 	 */
409 	if (host->hw_ver.major == 0x5) {
410 		if (host->phy_gear == UFS_HS_G5)
411 			host_params->hs_rate = PA_HS_MODE_A;
412 		else
413 			host_params->hs_rate = PA_HS_MODE_B;
414 	}
415 
416 	mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
417 
418 	/* Reset UFS Host Controller and PHY */
419 	ret = ufs_qcom_host_reset(hba);
420 	if (ret)
421 		return ret;
422 
423 	if (phy->power_count) {
424 		phy_power_off(phy);
425 		phy_exit(phy);
426 	}
427 
428 	/* phy initialization - calibrate the phy */
429 	ret = phy_init(phy);
430 	if (ret) {
431 		dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
432 			__func__, ret);
433 		return ret;
434 	}
435 
436 	ret = phy_set_mode_ext(phy, mode, host->phy_gear);
437 	if (ret)
438 		goto out_disable_phy;
439 
440 	/* power on phy - start serdes and phy's power and clocks */
441 	ret = phy_power_on(phy);
442 	if (ret) {
443 		dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
444 			__func__, ret);
445 		goto out_disable_phy;
446 	}
447 
448 	ufs_qcom_select_unipro_mode(host);
449 
450 	return 0;
451 
452 out_disable_phy:
453 	phy_exit(phy);
454 
455 	return ret;
456 }
457 
458 /*
459  * The UTP controller has a number of internal clock gating cells (CGCs).
460  * Internal hardware sub-modules within the UTP controller control the CGCs.
461  * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
462  * in a specific operation, UTP controller CGCs are by default disabled and
463  * this function enables them (after every UFS link startup) to save some power
464  * leakage.
465  */
ufs_qcom_enable_hw_clk_gating(struct ufs_hba * hba)466 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
467 {
468 	ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL,
469 		    REG_UFS_CFG2);
470 
471 	/* Ensure that HW clock gating is enabled before next operations */
472 	ufshcd_readl(hba, REG_UFS_CFG2);
473 }
474 
ufs_qcom_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)475 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
476 				      enum ufs_notify_change_status status)
477 {
478 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
479 	int err;
480 
481 	switch (status) {
482 	case PRE_CHANGE:
483 		err = ufs_qcom_power_up_sequence(hba);
484 		if (err)
485 			return err;
486 
487 		/*
488 		 * The PHY PLL output is the source of tx/rx lane symbol
489 		 * clocks, hence, enable the lane clocks only after PHY
490 		 * is initialized.
491 		 */
492 		err = ufs_qcom_enable_lane_clks(host);
493 		break;
494 	case POST_CHANGE:
495 		/* check if UFS PHY moved from DISABLED to HIBERN8 */
496 		err = ufs_qcom_check_hibern8(hba);
497 		ufs_qcom_enable_hw_clk_gating(hba);
498 		ufs_qcom_ice_enable(host);
499 		break;
500 	default:
501 		dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
502 		err = -EINVAL;
503 		break;
504 	}
505 	return err;
506 }
507 
508 /**
509  * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers
510  *
511  * @hba: host controller instance
512  * @gear: Current operating gear
513  * @hs: current power mode
514  * @rate: current operating rate (A or B)
515  * @update_link_startup_timer: indicate if link_start ongoing
516  * @is_pre_scale_up: flag to check if pre scale up condition.
517  * Return: zero for success and non-zero in case of a failure.
518  */
ufs_qcom_cfg_timers(struct ufs_hba * hba,u32 gear,u32 hs,u32 rate,bool update_link_startup_timer,bool is_pre_scale_up)519 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
520 			       u32 hs, u32 rate, bool update_link_startup_timer,
521 			       bool is_pre_scale_up)
522 {
523 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
524 	struct ufs_clk_info *clki;
525 	unsigned long core_clk_rate = 0;
526 	u32 core_clk_cycles_per_us;
527 
528 	/*
529 	 * UTP controller uses SYS1CLK_1US_REG register for Interrupt
530 	 * Aggregation logic.
531 	 * It is mandatory to write SYS1CLK_1US_REG register on UFS host
532 	 * controller V4.0.0 onwards.
533 	 */
534 	if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba))
535 		return 0;
536 
537 	if (gear == 0) {
538 		dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
539 		return -EINVAL;
540 	}
541 
542 	list_for_each_entry(clki, &hba->clk_list_head, list) {
543 		if (!strcmp(clki->name, "core_clk")) {
544 			if (is_pre_scale_up)
545 				core_clk_rate = clki->max_freq;
546 			else
547 				core_clk_rate = clk_get_rate(clki->clk);
548 			break;
549 		}
550 
551 	}
552 
553 	/* If frequency is smaller than 1MHz, set to 1MHz */
554 	if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
555 		core_clk_rate = DEFAULT_CLK_RATE_HZ;
556 
557 	core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
558 	if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
559 		ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
560 		/*
561 		 * make sure above write gets applied before we return from
562 		 * this function.
563 		 */
564 		ufshcd_readl(hba, REG_UFS_SYS1CLK_1US);
565 	}
566 
567 	return 0;
568 }
569 
ufs_qcom_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)570 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
571 					enum ufs_notify_change_status status)
572 {
573 	int err = 0;
574 
575 	switch (status) {
576 	case PRE_CHANGE:
577 		if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
578 					0, true, false)) {
579 			dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
580 				__func__);
581 			return -EINVAL;
582 		}
583 
584 		err = ufs_qcom_set_core_clk_ctrl(hba, true);
585 		if (err)
586 			dev_err(hba->dev, "cfg core clk ctrl failed\n");
587 		/*
588 		 * Some UFS devices (and may be host) have issues if LCC is
589 		 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
590 		 * before link startup which will make sure that both host
591 		 * and device TX LCC are disabled once link startup is
592 		 * completed.
593 		 */
594 		err = ufshcd_disable_host_tx_lcc(hba);
595 
596 		break;
597 	default:
598 		break;
599 	}
600 
601 	return err;
602 }
603 
ufs_qcom_device_reset_ctrl(struct ufs_hba * hba,bool asserted)604 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted)
605 {
606 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
607 
608 	/* reset gpio is optional */
609 	if (!host->device_reset)
610 		return;
611 
612 	gpiod_set_value_cansleep(host->device_reset, asserted);
613 }
614 
ufs_qcom_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op,enum ufs_notify_change_status status)615 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
616 	enum ufs_notify_change_status status)
617 {
618 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
619 	struct phy *phy = host->generic_phy;
620 
621 	if (status == PRE_CHANGE)
622 		return 0;
623 
624 	if (ufs_qcom_is_link_off(hba)) {
625 		/*
626 		 * Disable the tx/rx lane symbol clocks before PHY is
627 		 * powered down as the PLL source should be disabled
628 		 * after downstream clocks are disabled.
629 		 */
630 		ufs_qcom_disable_lane_clks(host);
631 		phy_power_off(phy);
632 
633 		/* reset the connected UFS device during power down */
634 		ufs_qcom_device_reset_ctrl(hba, true);
635 
636 	} else if (!ufs_qcom_is_link_active(hba)) {
637 		ufs_qcom_disable_lane_clks(host);
638 	}
639 
640 	return ufs_qcom_ice_suspend(host);
641 }
642 
ufs_qcom_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)643 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
644 {
645 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
646 	struct phy *phy = host->generic_phy;
647 	int err;
648 
649 	if (ufs_qcom_is_link_off(hba)) {
650 		err = phy_power_on(phy);
651 		if (err) {
652 			dev_err(hba->dev, "%s: failed PHY power on: %d\n",
653 				__func__, err);
654 			return err;
655 		}
656 
657 		err = ufs_qcom_enable_lane_clks(host);
658 		if (err)
659 			return err;
660 
661 	} else if (!ufs_qcom_is_link_active(hba)) {
662 		err = ufs_qcom_enable_lane_clks(host);
663 		if (err)
664 			return err;
665 	}
666 
667 	return ufs_qcom_ice_resume(host);
668 }
669 
ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host * host,bool enable)670 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
671 {
672 	if (host->dev_ref_clk_ctrl_mmio &&
673 	    (enable ^ host->is_dev_ref_clk_enabled)) {
674 		u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
675 
676 		if (enable)
677 			temp |= host->dev_ref_clk_en_mask;
678 		else
679 			temp &= ~host->dev_ref_clk_en_mask;
680 
681 		/*
682 		 * If we are here to disable this clock it might be immediately
683 		 * after entering into hibern8 in which case we need to make
684 		 * sure that device ref_clk is active for specific time after
685 		 * hibern8 enter.
686 		 */
687 		if (!enable) {
688 			unsigned long gating_wait;
689 
690 			gating_wait = host->hba->dev_info.clk_gating_wait_us;
691 			if (!gating_wait) {
692 				udelay(1);
693 			} else {
694 				/*
695 				 * bRefClkGatingWaitTime defines the minimum
696 				 * time for which the reference clock is
697 				 * required by device during transition from
698 				 * HS-MODE to LS-MODE or HIBERN8 state. Give it
699 				 * more delay to be on the safe side.
700 				 */
701 				gating_wait += 10;
702 				usleep_range(gating_wait, gating_wait + 10);
703 			}
704 		}
705 
706 		writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
707 
708 		/*
709 		 * Make sure the write to ref_clk reaches the destination and
710 		 * not stored in a Write Buffer (WB).
711 		 */
712 		readl(host->dev_ref_clk_ctrl_mmio);
713 
714 		/*
715 		 * If we call hibern8 exit after this, we need to make sure that
716 		 * device ref_clk is stable for at least 1us before the hibern8
717 		 * exit command.
718 		 */
719 		if (enable)
720 			udelay(1);
721 
722 		host->is_dev_ref_clk_enabled = enable;
723 	}
724 }
725 
ufs_qcom_icc_set_bw(struct ufs_qcom_host * host,u32 mem_bw,u32 cfg_bw)726 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw)
727 {
728 	struct device *dev = host->hba->dev;
729 	int ret;
730 
731 	ret = icc_set_bw(host->icc_ddr, 0, mem_bw);
732 	if (ret < 0) {
733 		dev_err(dev, "failed to set bandwidth request: %d\n", ret);
734 		return ret;
735 	}
736 
737 	ret = icc_set_bw(host->icc_cpu, 0, cfg_bw);
738 	if (ret < 0) {
739 		dev_err(dev, "failed to set bandwidth request: %d\n", ret);
740 		return ret;
741 	}
742 
743 	return 0;
744 }
745 
ufs_qcom_get_bw_table(struct ufs_qcom_host * host)746 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host)
747 {
748 	struct ufs_pa_layer_attr *p = &host->dev_req_params;
749 	int gear = max_t(u32, p->gear_rx, p->gear_tx);
750 	int lane = max_t(u32, p->lane_rx, p->lane_tx);
751 
752 	if (WARN_ONCE(gear > QCOM_UFS_MAX_GEAR,
753 		      "ICC scaling for UFS Gear (%d) not supported. Using Gear (%d) bandwidth\n",
754 		      gear, QCOM_UFS_MAX_GEAR))
755 		gear = QCOM_UFS_MAX_GEAR;
756 
757 	if (WARN_ONCE(lane > QCOM_UFS_MAX_LANE,
758 		      "ICC scaling for UFS Lane (%d) not supported. Using Lane (%d) bandwidth\n",
759 		      lane, QCOM_UFS_MAX_LANE))
760 		lane = QCOM_UFS_MAX_LANE;
761 
762 	if (ufshcd_is_hs_mode(p)) {
763 		if (p->hs_rate == PA_HS_MODE_B)
764 			return ufs_qcom_bw_table[MODE_HS_RB][gear][lane];
765 		else
766 			return ufs_qcom_bw_table[MODE_HS_RA][gear][lane];
767 	} else {
768 		return ufs_qcom_bw_table[MODE_PWM][gear][lane];
769 	}
770 }
771 
ufs_qcom_icc_update_bw(struct ufs_qcom_host * host)772 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host)
773 {
774 	struct __ufs_qcom_bw_table bw_table;
775 
776 	bw_table = ufs_qcom_get_bw_table(host);
777 
778 	return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw);
779 }
780 
ufs_qcom_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)781 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
782 				enum ufs_notify_change_status status,
783 				struct ufs_pa_layer_attr *dev_max_params,
784 				struct ufs_pa_layer_attr *dev_req_params)
785 {
786 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
787 	struct ufs_host_params *host_params = &host->host_params;
788 	int ret = 0;
789 
790 	if (!dev_req_params) {
791 		pr_err("%s: incoming dev_req_params is NULL\n", __func__);
792 		return -EINVAL;
793 	}
794 
795 	switch (status) {
796 	case PRE_CHANGE:
797 		ret = ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params);
798 		if (ret) {
799 			dev_err(hba->dev, "%s: failed to determine capabilities\n",
800 					__func__);
801 			return ret;
802 		}
803 
804 		/*
805 		 * During UFS driver probe, always update the PHY gear to match the negotiated
806 		 * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled,
807 		 * the second init can program the optimal PHY settings. This allows one to start
808 		 * the first init with either the minimum or the maximum support gear.
809 		 */
810 		if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
811 			/*
812 			 * Skip REINIT if the negotiated gear matches with the
813 			 * initial phy_gear. Otherwise, update the phy_gear to
814 			 * program the optimal gear setting during REINIT.
815 			 */
816 			if (host->phy_gear == dev_req_params->gear_tx)
817 				hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
818 			else
819 				host->phy_gear = dev_req_params->gear_tx;
820 		}
821 
822 		/* enable the device ref clock before changing to HS mode */
823 		if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
824 			ufshcd_is_hs_mode(dev_req_params))
825 			ufs_qcom_dev_ref_clk_ctrl(host, true);
826 
827 		if (host->hw_ver.major >= 0x4) {
828 			ufshcd_dme_configure_adapt(hba,
829 						dev_req_params->gear_tx,
830 						PA_INITIAL_ADAPT);
831 		}
832 		break;
833 	case POST_CHANGE:
834 		if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
835 					dev_req_params->pwr_rx,
836 					dev_req_params->hs_rate, false, false)) {
837 			dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
838 				__func__);
839 			/*
840 			 * we return error code at the end of the routine,
841 			 * but continue to configure UFS_PHY_TX_LANE_ENABLE
842 			 * and bus voting as usual
843 			 */
844 			ret = -EINVAL;
845 		}
846 
847 		/* cache the power mode parameters to use internally */
848 		memcpy(&host->dev_req_params,
849 				dev_req_params, sizeof(*dev_req_params));
850 
851 		ufs_qcom_icc_update_bw(host);
852 
853 		/* disable the device ref clock if entered PWM mode */
854 		if (ufshcd_is_hs_mode(&hba->pwr_info) &&
855 			!ufshcd_is_hs_mode(dev_req_params))
856 			ufs_qcom_dev_ref_clk_ctrl(host, false);
857 		break;
858 	default:
859 		ret = -EINVAL;
860 		break;
861 	}
862 
863 	return ret;
864 }
865 
ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba * hba)866 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
867 {
868 	int err;
869 	u32 pa_vs_config_reg1;
870 
871 	err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
872 			     &pa_vs_config_reg1);
873 	if (err)
874 		return err;
875 
876 	/* Allow extension of MSB bits of PA_SaveConfigTime attribute */
877 	return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
878 			    (pa_vs_config_reg1 | (1 << 12)));
879 }
880 
ufs_qcom_apply_dev_quirks(struct ufs_hba * hba)881 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
882 {
883 	int err = 0;
884 
885 	if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
886 		err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
887 
888 	return err;
889 }
890 
891 /* UFS device-specific quirks */
892 static struct ufs_dev_quirk ufs_qcom_dev_fixups[] = {
893 	{ .wmanufacturerid = UFS_VENDOR_SKHYNIX,
894 	  .model = UFS_ANY_MODEL,
895 	  .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
896 	{ .wmanufacturerid = UFS_VENDOR_TOSHIBA,
897 	  .model = UFS_ANY_MODEL,
898 	  .quirk = UFS_DEVICE_QUIRK_DELAY_AFTER_LPM },
899 	{ .wmanufacturerid = UFS_VENDOR_WDC,
900 	  .model = UFS_ANY_MODEL,
901 	  .quirk = UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE },
902 	{}
903 };
904 
ufs_qcom_fixup_dev_quirks(struct ufs_hba * hba)905 static void ufs_qcom_fixup_dev_quirks(struct ufs_hba *hba)
906 {
907 	ufshcd_fixup_dev_quirks(hba, ufs_qcom_dev_fixups);
908 }
909 
ufs_qcom_get_ufs_hci_version(struct ufs_hba * hba)910 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
911 {
912 	return ufshci_version(2, 0);
913 }
914 
915 /**
916  * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
917  * @hba: host controller instance
918  *
919  * QCOM UFS host controller might have some non standard behaviours (quirks)
920  * than what is specified by UFSHCI specification. Advertise all such
921  * quirks to standard UFS host controller driver so standard takes them into
922  * account.
923  */
ufs_qcom_advertise_quirks(struct ufs_hba * hba)924 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
925 {
926 	const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev);
927 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
928 
929 	if (host->hw_ver.major == 0x2)
930 		hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
931 
932 	if (host->hw_ver.major > 0x3)
933 		hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
934 
935 	if (drvdata && drvdata->quirks)
936 		hba->quirks |= drvdata->quirks;
937 }
938 
ufs_qcom_set_phy_gear(struct ufs_qcom_host * host)939 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
940 {
941 	struct ufs_host_params *host_params = &host->host_params;
942 	u32 val, dev_major;
943 
944 	/*
945 	 * Default to powering up the PHY to the max gear possible, which is
946 	 * backwards compatible with lower gears but not optimal from
947 	 * a power usage point of view. After device negotiation, if the
948 	 * gear is lower a reinit will be performed to program the PHY
949 	 * to the ideal gear for this combo of controller and device.
950 	 */
951 	host->phy_gear = host_params->hs_tx_gear;
952 
953 	if (host->hw_ver.major < 0x4) {
954 		/*
955 		 * These controllers only have one PHY init sequence,
956 		 * let's power up the PHY using that (the minimum supported
957 		 * gear, UFS_HS_G2).
958 		 */
959 		host->phy_gear = UFS_HS_G2;
960 	} else if (host->hw_ver.major >= 0x5) {
961 		val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
962 		dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val);
963 
964 		/*
965 		 * Since the UFS device version is populated, let's remove the
966 		 * REINIT quirk as the negotiated gear won't change during boot.
967 		 * So there is no need to do reinit.
968 		 */
969 		if (dev_major != 0x0)
970 			host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
971 
972 		/*
973 		 * For UFS 3.1 device and older, power up the PHY using HS-G4
974 		 * PHY gear to save power.
975 		 */
976 		if (dev_major > 0x0 && dev_major < 0x4)
977 			host->phy_gear = UFS_HS_G4;
978 	}
979 }
980 
ufs_qcom_set_host_params(struct ufs_hba * hba)981 static void ufs_qcom_set_host_params(struct ufs_hba *hba)
982 {
983 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
984 	struct ufs_host_params *host_params = &host->host_params;
985 
986 	ufshcd_init_host_params(host_params);
987 
988 	/* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
989 	host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba);
990 }
991 
ufs_qcom_set_caps(struct ufs_hba * hba)992 static void ufs_qcom_set_caps(struct ufs_hba *hba)
993 {
994 	hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
995 	hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING;
996 	hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
997 	hba->caps |= UFSHCD_CAP_WB_EN;
998 	hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE;
999 	hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
1000 }
1001 
1002 /**
1003  * ufs_qcom_setup_clocks - enables/disable clocks
1004  * @hba: host controller instance
1005  * @on: If true, enable clocks else disable them.
1006  * @status: PRE_CHANGE or POST_CHANGE notify
1007  *
1008  * Return: 0 on success, non-zero on failure.
1009  */
ufs_qcom_setup_clocks(struct ufs_hba * hba,bool on,enum ufs_notify_change_status status)1010 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
1011 				 enum ufs_notify_change_status status)
1012 {
1013 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1014 
1015 	/*
1016 	 * In case ufs_qcom_init() is not yet done, simply ignore.
1017 	 * This ufs_qcom_setup_clocks() shall be called from
1018 	 * ufs_qcom_init() after init is done.
1019 	 */
1020 	if (!host)
1021 		return 0;
1022 
1023 	switch (status) {
1024 	case PRE_CHANGE:
1025 		if (on) {
1026 			ufs_qcom_icc_update_bw(host);
1027 		} else {
1028 			if (!ufs_qcom_is_link_active(hba)) {
1029 				/* disable device ref_clk */
1030 				ufs_qcom_dev_ref_clk_ctrl(host, false);
1031 			}
1032 		}
1033 		break;
1034 	case POST_CHANGE:
1035 		if (on) {
1036 			/* enable the device ref clock for HS mode*/
1037 			if (ufshcd_is_hs_mode(&hba->pwr_info))
1038 				ufs_qcom_dev_ref_clk_ctrl(host, true);
1039 		} else {
1040 			ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw,
1041 					    ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw);
1042 		}
1043 		break;
1044 	}
1045 
1046 	return 0;
1047 }
1048 
1049 static int
ufs_qcom_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)1050 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
1051 {
1052 	struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1053 
1054 	ufs_qcom_assert_reset(host->hba);
1055 	/* provide 1ms delay to let the reset pulse propagate. */
1056 	usleep_range(1000, 1100);
1057 	return 0;
1058 }
1059 
1060 static int
ufs_qcom_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)1061 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
1062 {
1063 	struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1064 
1065 	ufs_qcom_deassert_reset(host->hba);
1066 
1067 	/*
1068 	 * after reset deassertion, phy will need all ref clocks,
1069 	 * voltage, current to settle down before starting serdes.
1070 	 */
1071 	usleep_range(1000, 1100);
1072 	return 0;
1073 }
1074 
1075 static const struct reset_control_ops ufs_qcom_reset_ops = {
1076 	.assert = ufs_qcom_reset_assert,
1077 	.deassert = ufs_qcom_reset_deassert,
1078 };
1079 
ufs_qcom_icc_init(struct ufs_qcom_host * host)1080 static int ufs_qcom_icc_init(struct ufs_qcom_host *host)
1081 {
1082 	struct device *dev = host->hba->dev;
1083 	int ret;
1084 
1085 	host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr");
1086 	if (IS_ERR(host->icc_ddr))
1087 		return dev_err_probe(dev, PTR_ERR(host->icc_ddr),
1088 				    "failed to acquire interconnect path\n");
1089 
1090 	host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs");
1091 	if (IS_ERR(host->icc_cpu))
1092 		return dev_err_probe(dev, PTR_ERR(host->icc_cpu),
1093 				    "failed to acquire interconnect path\n");
1094 
1095 	/*
1096 	 * Set Maximum bandwidth vote before initializing the UFS controller and
1097 	 * device. Ideally, a minimal interconnect vote would suffice for the
1098 	 * initialization, but a max vote would allow faster initialization.
1099 	 */
1100 	ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw,
1101 				  ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw);
1102 	if (ret < 0)
1103 		return dev_err_probe(dev, ret, "failed to set bandwidth request\n");
1104 
1105 	return 0;
1106 }
1107 
1108 /**
1109  * ufs_qcom_init - bind phy with controller
1110  * @hba: host controller instance
1111  *
1112  * Binds PHY with controller and powers up PHY enabling clocks
1113  * and regulators.
1114  *
1115  * Return: -EPROBE_DEFER if binding fails, returns negative error
1116  * on phy power up failure and returns zero on success.
1117  */
ufs_qcom_init(struct ufs_hba * hba)1118 static int ufs_qcom_init(struct ufs_hba *hba)
1119 {
1120 	int err;
1121 	struct device *dev = hba->dev;
1122 	struct ufs_qcom_host *host;
1123 	struct ufs_clk_info *clki;
1124 	const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev);
1125 
1126 	host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1127 	if (!host)
1128 		return -ENOMEM;
1129 
1130 	/* Make a two way bind between the qcom host and the hba */
1131 	host->hba = hba;
1132 	ufshcd_set_variant(hba, host);
1133 
1134 	/* Setup the optional reset control of HCI */
1135 	host->core_reset = devm_reset_control_get_optional(hba->dev, "rst");
1136 	if (IS_ERR(host->core_reset)) {
1137 		err = dev_err_probe(dev, PTR_ERR(host->core_reset),
1138 				    "Failed to get reset control\n");
1139 		goto out_variant_clear;
1140 	}
1141 
1142 	/* Fire up the reset controller. Failure here is non-fatal. */
1143 	host->rcdev.of_node = dev->of_node;
1144 	host->rcdev.ops = &ufs_qcom_reset_ops;
1145 	host->rcdev.owner = dev->driver->owner;
1146 	host->rcdev.nr_resets = 1;
1147 	err = devm_reset_controller_register(dev, &host->rcdev);
1148 	if (err)
1149 		dev_warn(dev, "Failed to register reset controller\n");
1150 
1151 	if (!has_acpi_companion(dev)) {
1152 		host->generic_phy = devm_phy_get(dev, "ufsphy");
1153 		if (IS_ERR(host->generic_phy)) {
1154 			err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n");
1155 			goto out_variant_clear;
1156 		}
1157 	}
1158 
1159 	err = ufs_qcom_icc_init(host);
1160 	if (err)
1161 		goto out_variant_clear;
1162 
1163 	host->device_reset = devm_gpiod_get_optional(dev, "reset",
1164 						     GPIOD_OUT_HIGH);
1165 	if (IS_ERR(host->device_reset)) {
1166 		err = dev_err_probe(dev, PTR_ERR(host->device_reset),
1167 				    "Failed to acquire device reset gpio\n");
1168 		goto out_variant_clear;
1169 	}
1170 
1171 	ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1172 		&host->hw_ver.minor, &host->hw_ver.step);
1173 
1174 	host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1175 	host->dev_ref_clk_en_mask = BIT(26);
1176 
1177 	list_for_each_entry(clki, &hba->clk_list_head, list) {
1178 		if (!strcmp(clki->name, "core_clk_unipro"))
1179 			clki->keep_link_active = true;
1180 	}
1181 
1182 	err = ufs_qcom_init_lane_clks(host);
1183 	if (err)
1184 		goto out_variant_clear;
1185 
1186 	ufs_qcom_set_caps(hba);
1187 	ufs_qcom_advertise_quirks(hba);
1188 	ufs_qcom_set_host_params(hba);
1189 	ufs_qcom_set_phy_gear(host);
1190 
1191 	err = ufs_qcom_ice_init(host);
1192 	if (err)
1193 		goto out_variant_clear;
1194 
1195 	ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1196 
1197 	ufs_qcom_get_default_testbus_cfg(host);
1198 	err = ufs_qcom_testbus_config(host);
1199 	if (err)
1200 		/* Failure is non-fatal */
1201 		dev_warn(dev, "%s: failed to configure the testbus %d\n",
1202 				__func__, err);
1203 
1204 	if (drvdata && drvdata->no_phy_retention)
1205 		hba->spm_lvl = UFS_PM_LVL_5;
1206 
1207 	return 0;
1208 
1209 out_variant_clear:
1210 	ufshcd_set_variant(hba, NULL);
1211 
1212 	return err;
1213 }
1214 
ufs_qcom_exit(struct ufs_hba * hba)1215 static void ufs_qcom_exit(struct ufs_hba *hba)
1216 {
1217 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1218 
1219 	ufs_qcom_disable_lane_clks(host);
1220 	phy_power_off(host->generic_phy);
1221 	phy_exit(host->generic_phy);
1222 }
1223 
1224 /**
1225  * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles
1226  *
1227  * @hba: host controller instance
1228  * @cycles_in_1us: No of cycles in 1us to be configured
1229  *
1230  * Returns error if dme get/set configuration for 40ns fails
1231  * and returns zero on success.
1232  */
ufs_qcom_set_clk_40ns_cycles(struct ufs_hba * hba,u32 cycles_in_1us)1233 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba,
1234 					u32 cycles_in_1us)
1235 {
1236 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1237 	u32 cycles_in_40ns;
1238 	u32 reg;
1239 	int err;
1240 
1241 	/*
1242 	 * UFS host controller V4.0.0 onwards needs to program
1243 	 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed
1244 	 * frequency of unipro core clk of UFS host controller.
1245 	 */
1246 	if (host->hw_ver.major < 4)
1247 		return 0;
1248 
1249 	/*
1250 	 * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not
1251 	 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will
1252 	 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware
1253 	 * specification expect to be 16. Hence use exact hardware spec
1254 	 * mandated value for cycles_in_40ns instead of calculating using
1255 	 * generic formulae.
1256 	 */
1257 	switch (cycles_in_1us) {
1258 	case UNIPRO_CORE_CLK_FREQ_403_MHZ:
1259 		cycles_in_40ns = 16;
1260 		break;
1261 	case UNIPRO_CORE_CLK_FREQ_300_MHZ:
1262 		cycles_in_40ns = 12;
1263 		break;
1264 	case UNIPRO_CORE_CLK_FREQ_201_5_MHZ:
1265 		cycles_in_40ns = 8;
1266 		break;
1267 	case UNIPRO_CORE_CLK_FREQ_150_MHZ:
1268 		cycles_in_40ns = 6;
1269 		break;
1270 	case UNIPRO_CORE_CLK_FREQ_100_MHZ:
1271 		cycles_in_40ns = 4;
1272 		break;
1273 	case  UNIPRO_CORE_CLK_FREQ_75_MHZ:
1274 		cycles_in_40ns = 3;
1275 		break;
1276 	case UNIPRO_CORE_CLK_FREQ_37_5_MHZ:
1277 		cycles_in_40ns = 2;
1278 		break;
1279 	default:
1280 		dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n",
1281 				cycles_in_1us);
1282 		return -EINVAL;
1283 	}
1284 
1285 	err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), &reg);
1286 	if (err)
1287 		return err;
1288 
1289 	reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK;
1290 	reg |= cycles_in_40ns;
1291 
1292 	return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg);
1293 }
1294 
ufs_qcom_set_core_clk_ctrl(struct ufs_hba * hba,bool is_scale_up)1295 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up)
1296 {
1297 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1298 	struct list_head *head = &hba->clk_list_head;
1299 	struct ufs_clk_info *clki;
1300 	u32 cycles_in_1us = 0;
1301 	u32 core_clk_ctrl_reg;
1302 	int err;
1303 
1304 	list_for_each_entry(clki, head, list) {
1305 		if (!IS_ERR_OR_NULL(clki->clk) &&
1306 		    !strcmp(clki->name, "core_clk_unipro")) {
1307 			if (!clki->max_freq)
1308 				cycles_in_1us = 150; /* default for backwards compatibility */
1309 			else if (is_scale_up)
1310 				cycles_in_1us = ceil(clki->max_freq, (1000 * 1000));
1311 			else
1312 				cycles_in_1us = ceil(clk_get_rate(clki->clk), (1000 * 1000));
1313 			break;
1314 		}
1315 	}
1316 
1317 	err = ufshcd_dme_get(hba,
1318 			    UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1319 			    &core_clk_ctrl_reg);
1320 	if (err)
1321 		return err;
1322 
1323 	/* Bit mask is different for UFS host controller V4.0.0 onwards */
1324 	if (host->hw_ver.major >= 4) {
1325 		if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us))
1326 			return -ERANGE;
1327 		core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4;
1328 		core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us);
1329 	} else {
1330 		if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us))
1331 			return -ERANGE;
1332 		core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK;
1333 		core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us);
1334 	}
1335 
1336 	/* Clear CORE_CLK_DIV_EN */
1337 	core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1338 
1339 	err = ufshcd_dme_set(hba,
1340 			    UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1341 			    core_clk_ctrl_reg);
1342 	if (err)
1343 		return err;
1344 
1345 	/* Configure unipro core clk 40ns attribute */
1346 	return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us);
1347 }
1348 
ufs_qcom_clk_scale_up_pre_change(struct ufs_hba * hba)1349 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1350 {
1351 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1352 	struct ufs_pa_layer_attr *attr = &host->dev_req_params;
1353 	int ret;
1354 
1355 	ret = ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx,
1356 				  attr->hs_rate, false, true);
1357 	if (ret) {
1358 		dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__);
1359 		return ret;
1360 	}
1361 	/* set unipro core clock attributes and clear clock divider */
1362 	return ufs_qcom_set_core_clk_ctrl(hba, true);
1363 }
1364 
ufs_qcom_clk_scale_up_post_change(struct ufs_hba * hba)1365 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1366 {
1367 	return 0;
1368 }
1369 
ufs_qcom_clk_scale_down_pre_change(struct ufs_hba * hba)1370 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1371 {
1372 	int err;
1373 	u32 core_clk_ctrl_reg;
1374 
1375 	err = ufshcd_dme_get(hba,
1376 			    UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1377 			    &core_clk_ctrl_reg);
1378 
1379 	/* make sure CORE_CLK_DIV_EN is cleared */
1380 	if (!err &&
1381 	    (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1382 		core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1383 		err = ufshcd_dme_set(hba,
1384 				    UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1385 				    core_clk_ctrl_reg);
1386 	}
1387 
1388 	return err;
1389 }
1390 
ufs_qcom_clk_scale_down_post_change(struct ufs_hba * hba)1391 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1392 {
1393 	/* set unipro core clock attributes and clear clock divider */
1394 	return ufs_qcom_set_core_clk_ctrl(hba, false);
1395 }
1396 
ufs_qcom_clk_scale_notify(struct ufs_hba * hba,bool scale_up,enum ufs_notify_change_status status)1397 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1398 		bool scale_up, enum ufs_notify_change_status status)
1399 {
1400 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1401 	int err;
1402 
1403 	/* check the host controller state before sending hibern8 cmd */
1404 	if (!ufshcd_is_hba_active(hba))
1405 		return 0;
1406 
1407 	if (status == PRE_CHANGE) {
1408 		err = ufshcd_uic_hibern8_enter(hba);
1409 		if (err)
1410 			return err;
1411 		if (scale_up)
1412 			err = ufs_qcom_clk_scale_up_pre_change(hba);
1413 		else
1414 			err = ufs_qcom_clk_scale_down_pre_change(hba);
1415 
1416 		if (err) {
1417 			ufshcd_uic_hibern8_exit(hba);
1418 			return err;
1419 		}
1420 	} else {
1421 		if (scale_up)
1422 			err = ufs_qcom_clk_scale_up_post_change(hba);
1423 		else
1424 			err = ufs_qcom_clk_scale_down_post_change(hba);
1425 
1426 
1427 		if (err) {
1428 			ufshcd_uic_hibern8_exit(hba);
1429 			return err;
1430 		}
1431 
1432 		ufs_qcom_icc_update_bw(host);
1433 		ufshcd_uic_hibern8_exit(hba);
1434 	}
1435 
1436 	return 0;
1437 }
1438 
ufs_qcom_enable_test_bus(struct ufs_qcom_host * host)1439 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1440 {
1441 	ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1442 			UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1443 	ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1444 }
1445 
ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host * host)1446 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1447 {
1448 	/* provide a legal default configuration */
1449 	host->testbus.select_major = TSTBUS_UNIPRO;
1450 	host->testbus.select_minor = 37;
1451 }
1452 
ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host * host)1453 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1454 {
1455 	if (host->testbus.select_major >= TSTBUS_MAX) {
1456 		dev_err(host->hba->dev,
1457 			"%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1458 			__func__, host->testbus.select_major);
1459 		return false;
1460 	}
1461 
1462 	return true;
1463 }
1464 
ufs_qcom_testbus_config(struct ufs_qcom_host * host)1465 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1466 {
1467 	int reg;
1468 	int offset;
1469 	u32 mask = TEST_BUS_SUB_SEL_MASK;
1470 
1471 	if (!host)
1472 		return -EINVAL;
1473 
1474 	if (!ufs_qcom_testbus_cfg_is_ok(host))
1475 		return -EPERM;
1476 
1477 	switch (host->testbus.select_major) {
1478 	case TSTBUS_UAWM:
1479 		reg = UFS_TEST_BUS_CTRL_0;
1480 		offset = 24;
1481 		break;
1482 	case TSTBUS_UARM:
1483 		reg = UFS_TEST_BUS_CTRL_0;
1484 		offset = 16;
1485 		break;
1486 	case TSTBUS_TXUC:
1487 		reg = UFS_TEST_BUS_CTRL_0;
1488 		offset = 8;
1489 		break;
1490 	case TSTBUS_RXUC:
1491 		reg = UFS_TEST_BUS_CTRL_0;
1492 		offset = 0;
1493 		break;
1494 	case TSTBUS_DFC:
1495 		reg = UFS_TEST_BUS_CTRL_1;
1496 		offset = 24;
1497 		break;
1498 	case TSTBUS_TRLUT:
1499 		reg = UFS_TEST_BUS_CTRL_1;
1500 		offset = 16;
1501 		break;
1502 	case TSTBUS_TMRLUT:
1503 		reg = UFS_TEST_BUS_CTRL_1;
1504 		offset = 8;
1505 		break;
1506 	case TSTBUS_OCSC:
1507 		reg = UFS_TEST_BUS_CTRL_1;
1508 		offset = 0;
1509 		break;
1510 	case TSTBUS_WRAPPER:
1511 		reg = UFS_TEST_BUS_CTRL_2;
1512 		offset = 16;
1513 		break;
1514 	case TSTBUS_COMBINED:
1515 		reg = UFS_TEST_BUS_CTRL_2;
1516 		offset = 8;
1517 		break;
1518 	case TSTBUS_UTP_HCI:
1519 		reg = UFS_TEST_BUS_CTRL_2;
1520 		offset = 0;
1521 		break;
1522 	case TSTBUS_UNIPRO:
1523 		reg = UFS_UNIPRO_CFG;
1524 		offset = 20;
1525 		mask = 0xFFF;
1526 		break;
1527 	/*
1528 	 * No need for a default case, since
1529 	 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1530 	 * is legal
1531 	 */
1532 	}
1533 	mask <<= offset;
1534 	ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1535 		    (u32)host->testbus.select_major << 19,
1536 		    REG_UFS_CFG1);
1537 	ufshcd_rmwl(host->hba, mask,
1538 		    (u32)host->testbus.select_minor << offset,
1539 		    reg);
1540 	ufs_qcom_enable_test_bus(host);
1541 
1542 	return 0;
1543 }
1544 
ufs_qcom_dump_dbg_regs(struct ufs_hba * hba)1545 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1546 {
1547 	u32 reg;
1548 	struct ufs_qcom_host *host;
1549 
1550 	host = ufshcd_get_variant(hba);
1551 
1552 	ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1553 			 "HCI Vendor Specific Registers ");
1554 
1555 	reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1556 	ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC ");
1557 
1558 	reg = ufshcd_readl(hba, REG_UFS_CFG1);
1559 	reg |= UTP_DBG_RAMS_EN;
1560 	ufshcd_writel(hba, reg, REG_UFS_CFG1);
1561 
1562 	reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1563 	ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM ");
1564 
1565 	reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1566 	ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM ");
1567 
1568 	reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1569 	ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM ");
1570 
1571 	/* clear bit 17 - UTP_DBG_RAMS_EN */
1572 	ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1573 
1574 	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1575 	ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM ");
1576 
1577 	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1578 	ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM ");
1579 
1580 	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1581 	ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC ");
1582 
1583 	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1584 	ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC ");
1585 
1586 	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1587 	ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC ");
1588 
1589 	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1590 	ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT ");
1591 
1592 	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1593 	ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT ");
1594 }
1595 
1596 /**
1597  * ufs_qcom_device_reset() - toggle the (optional) device reset line
1598  * @hba: per-adapter instance
1599  *
1600  * Toggles the (optional) reset line to reset the attached device.
1601  */
ufs_qcom_device_reset(struct ufs_hba * hba)1602 static int ufs_qcom_device_reset(struct ufs_hba *hba)
1603 {
1604 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1605 
1606 	/* reset gpio is optional */
1607 	if (!host->device_reset)
1608 		return -EOPNOTSUPP;
1609 
1610 	/*
1611 	 * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1612 	 * be on the safe side.
1613 	 */
1614 	ufs_qcom_device_reset_ctrl(hba, true);
1615 	usleep_range(10, 15);
1616 
1617 	ufs_qcom_device_reset_ctrl(hba, false);
1618 	usleep_range(10, 15);
1619 
1620 	return 0;
1621 }
1622 
1623 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
ufs_qcom_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * p,struct devfreq_simple_ondemand_data * d)1624 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1625 					struct devfreq_dev_profile *p,
1626 					struct devfreq_simple_ondemand_data *d)
1627 {
1628 	p->polling_ms = 60;
1629 	p->timer = DEVFREQ_TIMER_DELAYED;
1630 	d->upthreshold = 70;
1631 	d->downdifferential = 5;
1632 
1633 	hba->clk_scaling.suspend_on_no_request = true;
1634 }
1635 #else
ufs_qcom_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * p,struct devfreq_simple_ondemand_data * data)1636 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1637 		struct devfreq_dev_profile *p,
1638 		struct devfreq_simple_ondemand_data *data)
1639 {
1640 }
1641 #endif
1642 
1643 /* Resources */
1644 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = {
1645 	{.name = "ufs_mem",},
1646 	{.name = "mcq",},
1647 	/* Submission Queue DAO */
1648 	{.name = "mcq_sqd",},
1649 	/* Submission Queue Interrupt Status */
1650 	{.name = "mcq_sqis",},
1651 	/* Completion Queue DAO */
1652 	{.name = "mcq_cqd",},
1653 	/* Completion Queue Interrupt Status */
1654 	{.name = "mcq_cqis",},
1655 	/* MCQ vendor specific */
1656 	{.name = "mcq_vs",},
1657 };
1658 
ufs_qcom_mcq_config_resource(struct ufs_hba * hba)1659 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba)
1660 {
1661 	struct platform_device *pdev = to_platform_device(hba->dev);
1662 	struct ufshcd_res_info *res;
1663 	struct resource *res_mem, *res_mcq;
1664 	int i, ret;
1665 
1666 	memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info));
1667 
1668 	for (i = 0; i < RES_MAX; i++) {
1669 		res = &hba->res[i];
1670 		res->resource = platform_get_resource_byname(pdev,
1671 							     IORESOURCE_MEM,
1672 							     res->name);
1673 		if (!res->resource) {
1674 			dev_info(hba->dev, "Resource %s not provided\n", res->name);
1675 			if (i == RES_UFS)
1676 				return -ENODEV;
1677 			continue;
1678 		} else if (i == RES_UFS) {
1679 			res_mem = res->resource;
1680 			res->base = hba->mmio_base;
1681 			continue;
1682 		}
1683 
1684 		res->base = devm_ioremap_resource(hba->dev, res->resource);
1685 		if (IS_ERR(res->base)) {
1686 			dev_err(hba->dev, "Failed to map res %s, err=%d\n",
1687 					 res->name, (int)PTR_ERR(res->base));
1688 			ret = PTR_ERR(res->base);
1689 			res->base = NULL;
1690 			return ret;
1691 		}
1692 	}
1693 
1694 	/* MCQ resource provided in DT */
1695 	res = &hba->res[RES_MCQ];
1696 	/* Bail if MCQ resource is provided */
1697 	if (res->base)
1698 		goto out;
1699 
1700 	/* Explicitly allocate MCQ resource from ufs_mem */
1701 	res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL);
1702 	if (!res_mcq)
1703 		return -ENOMEM;
1704 
1705 	res_mcq->start = res_mem->start +
1706 			 MCQ_SQATTR_OFFSET(hba->mcq_capabilities);
1707 	res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1;
1708 	res_mcq->flags = res_mem->flags;
1709 	res_mcq->name = "mcq";
1710 
1711 	ret = insert_resource(&iomem_resource, res_mcq);
1712 	if (ret) {
1713 		dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n",
1714 			ret);
1715 		return ret;
1716 	}
1717 
1718 	res->base = devm_ioremap_resource(hba->dev, res_mcq);
1719 	if (IS_ERR(res->base)) {
1720 		dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n",
1721 			(int)PTR_ERR(res->base));
1722 		ret = PTR_ERR(res->base);
1723 		goto ioremap_err;
1724 	}
1725 
1726 out:
1727 	hba->mcq_base = res->base;
1728 	return 0;
1729 ioremap_err:
1730 	res->base = NULL;
1731 	remove_resource(res_mcq);
1732 	return ret;
1733 }
1734 
ufs_qcom_op_runtime_config(struct ufs_hba * hba)1735 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba)
1736 {
1737 	struct ufshcd_res_info *mem_res, *sqdao_res;
1738 	struct ufshcd_mcq_opr_info_t *opr;
1739 	int i;
1740 
1741 	mem_res = &hba->res[RES_UFS];
1742 	sqdao_res = &hba->res[RES_MCQ_SQD];
1743 
1744 	if (!mem_res->base || !sqdao_res->base)
1745 		return -EINVAL;
1746 
1747 	for (i = 0; i < OPR_MAX; i++) {
1748 		opr = &hba->mcq_opr[i];
1749 		opr->offset = sqdao_res->resource->start -
1750 			      mem_res->resource->start + 0x40 * i;
1751 		opr->stride = 0x100;
1752 		opr->base = sqdao_res->base + 0x40 * i;
1753 	}
1754 
1755 	return 0;
1756 }
1757 
ufs_qcom_get_hba_mac(struct ufs_hba * hba)1758 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba)
1759 {
1760 	/* Qualcomm HC supports up to 64 */
1761 	return MAX_SUPP_MAC;
1762 }
1763 
ufs_qcom_get_outstanding_cqs(struct ufs_hba * hba,unsigned long * ocqs)1764 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba,
1765 					unsigned long *ocqs)
1766 {
1767 	struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS];
1768 
1769 	if (!mcq_vs_res->base)
1770 		return -EINVAL;
1771 
1772 	*ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS);
1773 
1774 	return 0;
1775 }
1776 
ufs_qcom_write_msi_msg(struct msi_desc * desc,struct msi_msg * msg)1777 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
1778 {
1779 	struct device *dev = msi_desc_to_dev(desc);
1780 	struct ufs_hba *hba = dev_get_drvdata(dev);
1781 
1782 	ufshcd_mcq_config_esi(hba, msg);
1783 }
1784 
ufs_qcom_mcq_esi_handler(int irq,void * data)1785 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data)
1786 {
1787 	struct msi_desc *desc = data;
1788 	struct device *dev = msi_desc_to_dev(desc);
1789 	struct ufs_hba *hba = dev_get_drvdata(dev);
1790 	u32 id = desc->msi_index;
1791 	struct ufs_hw_queue *hwq = &hba->uhq[id];
1792 
1793 	ufshcd_mcq_write_cqis(hba, 0x1, id);
1794 	ufshcd_mcq_poll_cqe_lock(hba, hwq);
1795 
1796 	return IRQ_HANDLED;
1797 }
1798 
ufs_qcom_config_esi(struct ufs_hba * hba)1799 static int ufs_qcom_config_esi(struct ufs_hba *hba)
1800 {
1801 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1802 	struct msi_desc *desc;
1803 	struct msi_desc *failed_desc = NULL;
1804 	int nr_irqs, ret;
1805 
1806 	if (host->esi_enabled)
1807 		return 0;
1808 
1809 	/*
1810 	 * 1. We only handle CQs as of now.
1811 	 * 2. Poll queues do not need ESI.
1812 	 */
1813 	nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL];
1814 	ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs,
1815 						      ufs_qcom_write_msi_msg);
1816 	if (ret) {
1817 		dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret);
1818 		return ret;
1819 	}
1820 
1821 	msi_lock_descs(hba->dev);
1822 	msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
1823 		ret = devm_request_irq(hba->dev, desc->irq,
1824 				       ufs_qcom_mcq_esi_handler,
1825 				       IRQF_SHARED, "qcom-mcq-esi", desc);
1826 		if (ret) {
1827 			dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n",
1828 				__func__, desc->irq, ret);
1829 			failed_desc = desc;
1830 			break;
1831 		}
1832 	}
1833 	msi_unlock_descs(hba->dev);
1834 
1835 	if (ret) {
1836 		/* Rewind */
1837 		msi_lock_descs(hba->dev);
1838 		msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
1839 			if (desc == failed_desc)
1840 				break;
1841 			devm_free_irq(hba->dev, desc->irq, hba);
1842 		}
1843 		msi_unlock_descs(hba->dev);
1844 		platform_device_msi_free_irqs_all(hba->dev);
1845 	} else {
1846 		if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 &&
1847 		    host->hw_ver.step == 0)
1848 			ufshcd_rmwl(hba, ESI_VEC_MASK,
1849 				    FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1),
1850 				    REG_UFS_CFG3);
1851 		ufshcd_mcq_enable_esi(hba);
1852 		host->esi_enabled = true;
1853 	}
1854 
1855 	return ret;
1856 }
1857 
1858 /*
1859  * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1860  *
1861  * The variant operations configure the necessary controller and PHY
1862  * handshake during initialization.
1863  */
1864 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1865 	.name                   = "qcom",
1866 	.init                   = ufs_qcom_init,
1867 	.exit                   = ufs_qcom_exit,
1868 	.get_ufs_hci_version	= ufs_qcom_get_ufs_hci_version,
1869 	.clk_scale_notify	= ufs_qcom_clk_scale_notify,
1870 	.setup_clocks           = ufs_qcom_setup_clocks,
1871 	.hce_enable_notify      = ufs_qcom_hce_enable_notify,
1872 	.link_startup_notify    = ufs_qcom_link_startup_notify,
1873 	.pwr_change_notify	= ufs_qcom_pwr_change_notify,
1874 	.apply_dev_quirks	= ufs_qcom_apply_dev_quirks,
1875 	.fixup_dev_quirks       = ufs_qcom_fixup_dev_quirks,
1876 	.suspend		= ufs_qcom_suspend,
1877 	.resume			= ufs_qcom_resume,
1878 	.dbg_register_dump	= ufs_qcom_dump_dbg_regs,
1879 	.device_reset		= ufs_qcom_device_reset,
1880 	.config_scaling_param = ufs_qcom_config_scaling_param,
1881 	.mcq_config_resource	= ufs_qcom_mcq_config_resource,
1882 	.get_hba_mac		= ufs_qcom_get_hba_mac,
1883 	.op_runtime_config	= ufs_qcom_op_runtime_config,
1884 	.get_outstanding_cqs	= ufs_qcom_get_outstanding_cqs,
1885 	.config_esi		= ufs_qcom_config_esi,
1886 };
1887 
1888 /**
1889  * ufs_qcom_probe - probe routine of the driver
1890  * @pdev: pointer to Platform device handle
1891  *
1892  * Return: zero for success and non-zero for failure.
1893  */
ufs_qcom_probe(struct platform_device * pdev)1894 static int ufs_qcom_probe(struct platform_device *pdev)
1895 {
1896 	int err;
1897 	struct device *dev = &pdev->dev;
1898 
1899 	/* Perform generic probe */
1900 	err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1901 	if (err)
1902 		return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n");
1903 
1904 	return 0;
1905 }
1906 
1907 /**
1908  * ufs_qcom_remove - set driver_data of the device to NULL
1909  * @pdev: pointer to platform device handle
1910  *
1911  * Always returns 0
1912  */
ufs_qcom_remove(struct platform_device * pdev)1913 static void ufs_qcom_remove(struct platform_device *pdev)
1914 {
1915 	struct ufs_hba *hba =  platform_get_drvdata(pdev);
1916 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1917 
1918 	ufshcd_pltfrm_remove(pdev);
1919 	if (host->esi_enabled)
1920 		platform_device_msi_free_irqs_all(hba->dev);
1921 }
1922 
1923 static const struct ufs_qcom_drvdata ufs_qcom_sm8550_drvdata = {
1924 	.quirks = UFSHCD_QUIRK_BROKEN_LSDBS_CAP,
1925 	.no_phy_retention = true,
1926 };
1927 
1928 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = {
1929 	{ .compatible = "qcom,ufshc" },
1930 	{ .compatible = "qcom,sm8550-ufshc", .data = &ufs_qcom_sm8550_drvdata },
1931 	{ .compatible = "qcom,sm8650-ufshc", .data = &ufs_qcom_sm8550_drvdata },
1932 	{},
1933 };
1934 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1935 
1936 #ifdef CONFIG_ACPI
1937 static const struct acpi_device_id ufs_qcom_acpi_match[] = {
1938 	{ "QCOM24A5" },
1939 	{ },
1940 };
1941 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
1942 #endif
1943 
1944 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1945 	SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
1946 	.prepare	 = ufshcd_suspend_prepare,
1947 	.complete	 = ufshcd_resume_complete,
1948 #ifdef CONFIG_PM_SLEEP
1949 	.suspend         = ufshcd_system_suspend,
1950 	.resume          = ufshcd_system_resume,
1951 	.freeze          = ufshcd_system_freeze,
1952 	.restore         = ufshcd_system_restore,
1953 	.thaw            = ufshcd_system_thaw,
1954 #endif
1955 };
1956 
1957 static struct platform_driver ufs_qcom_pltform = {
1958 	.probe	= ufs_qcom_probe,
1959 	.remove = ufs_qcom_remove,
1960 	.driver	= {
1961 		.name	= "ufshcd-qcom",
1962 		.pm	= &ufs_qcom_pm_ops,
1963 		.of_match_table = of_match_ptr(ufs_qcom_of_match),
1964 		.acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
1965 	},
1966 };
1967 module_platform_driver(ufs_qcom_pltform);
1968 
1969 MODULE_DESCRIPTION("Qualcomm UFS host controller driver");
1970 MODULE_LICENSE("GPL v2");
1971