1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/clk.h>
8 #include <linux/cleanup.h>
9 #include <linux/delay.h>
10 #include <linux/devfreq.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/interconnect.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/phy/phy.h>
16 #include <linux/platform_device.h>
17 #include <linux/reset-controller.h>
18 #include <linux/time.h>
19 #include <linux/unaligned.h>
20 #include <linux/units.h>
21
22 #include <soc/qcom/ice.h>
23
24 #include <ufs/ufshcd.h>
25 #include <ufs/ufshci.h>
26 #include <ufs/ufs_quirks.h>
27 #include <ufs/unipro.h>
28 #include "ufshcd-pltfrm.h"
29 #include "ufs-qcom.h"
30
31 #define MCQ_QCFGPTR_MASK GENMASK(7, 0)
32 #define MCQ_QCFGPTR_UNIT 0x200
33 #define MCQ_SQATTR_OFFSET(c) \
34 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT)
35 #define MCQ_QCFG_SIZE 0x40
36
37 /* De-emphasis for gear-5 */
38 #define DEEMPHASIS_3_5_dB 0x04
39 #define NO_DEEMPHASIS 0x0
40
41 #define UFS_ICE_SYNC_RST_SEL BIT(3)
42 #define UFS_ICE_SYNC_RST_SW BIT(4)
43
44 enum {
45 TSTBUS_UAWM,
46 TSTBUS_UARM,
47 TSTBUS_TXUC,
48 TSTBUS_RXUC,
49 TSTBUS_DFC,
50 TSTBUS_TRLUT,
51 TSTBUS_TMRLUT,
52 TSTBUS_OCSC,
53 TSTBUS_UTP_HCI,
54 TSTBUS_COMBINED,
55 TSTBUS_WRAPPER,
56 TSTBUS_UNIPRO,
57 TSTBUS_MAX,
58 };
59
60 #define QCOM_UFS_MAX_GEAR 5
61 #define QCOM_UFS_MAX_LANE 2
62
63 enum {
64 MODE_MIN,
65 MODE_PWM,
66 MODE_HS_RA,
67 MODE_HS_RB,
68 MODE_MAX,
69 };
70
71 static const struct __ufs_qcom_bw_table {
72 u32 mem_bw;
73 u32 cfg_bw;
74 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = {
75 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */
76 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 },
77 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 },
78 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 },
79 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 },
80 [MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752, 1000 },
81 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 },
82 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 },
83 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 },
84 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 },
85 [MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504, 1000 },
86 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 },
87 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 },
88 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 },
89 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 },
90 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 },
91 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 },
92 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 },
93 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 },
94 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 },
95 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 },
96 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 },
97 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 },
98 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 },
99 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 },
100 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 },
101 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 },
102 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 },
103 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 },
104 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 },
105 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 },
106 [MODE_MAX][0][0] = { 7643136, 819200 },
107 };
108
109 static const struct {
110 int nminor;
111 char *prefix;
112 } testbus_info[TSTBUS_MAX] = {
113 [TSTBUS_UAWM] = {32, "TSTBUS_UAWM"},
114 [TSTBUS_UARM] = {32, "TSTBUS_UARM"},
115 [TSTBUS_TXUC] = {32, "TSTBUS_TXUC"},
116 [TSTBUS_RXUC] = {32, "TSTBUS_RXUC"},
117 [TSTBUS_DFC] = {32, "TSTBUS_DFC"},
118 [TSTBUS_TRLUT] = {32, "TSTBUS_TRLUT"},
119 [TSTBUS_TMRLUT] = {32, "TSTBUS_TMRLUT"},
120 [TSTBUS_OCSC] = {32, "TSTBUS_OCSC"},
121 [TSTBUS_UTP_HCI] = {32, "TSTBUS_UTP_HCI"},
122 [TSTBUS_COMBINED] = {32, "TSTBUS_COMBINED"},
123 [TSTBUS_WRAPPER] = {32, "TSTBUS_WRAPPER"},
124 [TSTBUS_UNIPRO] = {256, "TSTBUS_UNIPRO"},
125 };
126
127 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
128 static unsigned long ufs_qcom_opp_freq_to_clk_freq(struct ufs_hba *hba,
129 unsigned long freq, char *name);
130 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up, unsigned long freq);
131
rcdev_to_ufs_host(struct reset_controller_dev * rcd)132 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
133 {
134 return container_of(rcd, struct ufs_qcom_host, rcdev);
135 }
136
137 #ifdef CONFIG_SCSI_UFS_CRYPTO
138 /**
139 * ufs_qcom_config_ice_allocator() - ICE core allocator configuration
140 *
141 * @host: pointer to qcom specific variant structure.
142 */
ufs_qcom_config_ice_allocator(struct ufs_qcom_host * host)143 static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host)
144 {
145 struct ufs_hba *hba = host->hba;
146 static const uint8_t val[4] = { NUM_RX_R1W0, NUM_TX_R0W1, NUM_RX_R1W1, NUM_TX_R1W1 };
147 u32 config;
148
149 if (!(host->caps & UFS_QCOM_CAP_ICE_CONFIG) ||
150 !(host->hba->caps & UFSHCD_CAP_CRYPTO))
151 return;
152
153 config = get_unaligned_le32(val);
154
155 ufshcd_writel(hba, ICE_ALLOCATOR_TYPE, REG_UFS_MEM_ICE_CONFIG);
156 ufshcd_writel(hba, config, REG_UFS_MEM_ICE_NUM_CORE);
157 }
158
ufs_qcom_ice_enable(struct ufs_qcom_host * host)159 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
160 {
161 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
162 qcom_ice_enable(host->ice);
163 }
164
165 static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops; /* forward decl */
166
ufs_qcom_ice_init(struct ufs_qcom_host * host)167 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
168 {
169 struct ufs_hba *hba = host->hba;
170 struct blk_crypto_profile *profile = &hba->crypto_profile;
171 struct device *dev = hba->dev;
172 struct qcom_ice *ice;
173 union ufs_crypto_capabilities caps;
174 union ufs_crypto_cap_entry cap;
175 int err;
176 int i;
177
178 ice = devm_of_qcom_ice_get(dev);
179 if (ice == ERR_PTR(-EOPNOTSUPP)) {
180 dev_warn(dev, "Disabling inline encryption support\n");
181 ice = NULL;
182 }
183
184 if (IS_ERR_OR_NULL(ice))
185 return PTR_ERR_OR_ZERO(ice);
186
187 host->ice = ice;
188
189 /* Initialize the blk_crypto_profile */
190
191 caps.reg_val = cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP));
192
193 /* The number of keyslots supported is (CFGC+1) */
194 err = devm_blk_crypto_profile_init(dev, profile, caps.config_count + 1);
195 if (err)
196 return err;
197
198 profile->ll_ops = ufs_qcom_crypto_ops;
199 profile->max_dun_bytes_supported = 8;
200 profile->key_types_supported = qcom_ice_get_supported_key_type(ice);
201 profile->dev = dev;
202
203 /*
204 * Currently this driver only supports AES-256-XTS. All known versions
205 * of ICE support it, but to be safe make sure it is really declared in
206 * the crypto capability registers. The crypto capability registers
207 * also give the supported data unit size(s).
208 */
209 for (i = 0; i < caps.num_crypto_cap; i++) {
210 cap.reg_val = cpu_to_le32(ufshcd_readl(hba,
211 REG_UFS_CRYPTOCAP +
212 i * sizeof(__le32)));
213 if (cap.algorithm_id == UFS_CRYPTO_ALG_AES_XTS &&
214 cap.key_size == UFS_CRYPTO_KEY_SIZE_256)
215 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |=
216 cap.sdus_mask * 512;
217 }
218
219 hba->caps |= UFSHCD_CAP_CRYPTO;
220 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE;
221 return 0;
222 }
223
ufs_qcom_ice_resume(struct ufs_qcom_host * host)224 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
225 {
226 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
227 return qcom_ice_resume(host->ice);
228
229 return 0;
230 }
231
ufs_qcom_ice_suspend(struct ufs_qcom_host * host)232 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
233 {
234 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
235 return qcom_ice_suspend(host->ice);
236
237 return 0;
238 }
239
ufs_qcom_ice_keyslot_program(struct blk_crypto_profile * profile,const struct blk_crypto_key * key,unsigned int slot)240 static int ufs_qcom_ice_keyslot_program(struct blk_crypto_profile *profile,
241 const struct blk_crypto_key *key,
242 unsigned int slot)
243 {
244 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile);
245 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
246 int err;
247
248 ufshcd_hold(hba);
249 err = qcom_ice_program_key(host->ice, slot, key);
250 ufshcd_release(hba);
251 return err;
252 }
253
ufs_qcom_ice_keyslot_evict(struct blk_crypto_profile * profile,const struct blk_crypto_key * key,unsigned int slot)254 static int ufs_qcom_ice_keyslot_evict(struct blk_crypto_profile *profile,
255 const struct blk_crypto_key *key,
256 unsigned int slot)
257 {
258 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile);
259 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
260 int err;
261
262 ufshcd_hold(hba);
263 err = qcom_ice_evict_key(host->ice, slot);
264 ufshcd_release(hba);
265 return err;
266 }
267
ufs_qcom_ice_derive_sw_secret(struct blk_crypto_profile * profile,const u8 * eph_key,size_t eph_key_size,u8 sw_secret[BLK_CRYPTO_SW_SECRET_SIZE])268 static int ufs_qcom_ice_derive_sw_secret(struct blk_crypto_profile *profile,
269 const u8 *eph_key, size_t eph_key_size,
270 u8 sw_secret[BLK_CRYPTO_SW_SECRET_SIZE])
271 {
272 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile);
273 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
274
275 return qcom_ice_derive_sw_secret(host->ice, eph_key, eph_key_size,
276 sw_secret);
277 }
278
ufs_qcom_ice_import_key(struct blk_crypto_profile * profile,const u8 * raw_key,size_t raw_key_size,u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE])279 static int ufs_qcom_ice_import_key(struct blk_crypto_profile *profile,
280 const u8 *raw_key, size_t raw_key_size,
281 u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE])
282 {
283 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile);
284 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
285
286 return qcom_ice_import_key(host->ice, raw_key, raw_key_size, lt_key);
287 }
288
ufs_qcom_ice_generate_key(struct blk_crypto_profile * profile,u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE])289 static int ufs_qcom_ice_generate_key(struct blk_crypto_profile *profile,
290 u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE])
291 {
292 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile);
293 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
294
295 return qcom_ice_generate_key(host->ice, lt_key);
296 }
297
ufs_qcom_ice_prepare_key(struct blk_crypto_profile * profile,const u8 * lt_key,size_t lt_key_size,u8 eph_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE])298 static int ufs_qcom_ice_prepare_key(struct blk_crypto_profile *profile,
299 const u8 *lt_key, size_t lt_key_size,
300 u8 eph_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE])
301 {
302 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile);
303 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
304
305 return qcom_ice_prepare_key(host->ice, lt_key, lt_key_size, eph_key);
306 }
307
308 static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops = {
309 .keyslot_program = ufs_qcom_ice_keyslot_program,
310 .keyslot_evict = ufs_qcom_ice_keyslot_evict,
311 .derive_sw_secret = ufs_qcom_ice_derive_sw_secret,
312 .import_key = ufs_qcom_ice_import_key,
313 .generate_key = ufs_qcom_ice_generate_key,
314 .prepare_key = ufs_qcom_ice_prepare_key,
315 };
316
317 #else
318
ufs_qcom_ice_enable(struct ufs_qcom_host * host)319 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
320 {
321 }
322
ufs_qcom_ice_init(struct ufs_qcom_host * host)323 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
324 {
325 return 0;
326 }
327
ufs_qcom_ice_resume(struct ufs_qcom_host * host)328 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
329 {
330 return 0;
331 }
332
ufs_qcom_ice_suspend(struct ufs_qcom_host * host)333 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
334 {
335 return 0;
336 }
337
ufs_qcom_config_ice_allocator(struct ufs_qcom_host * host)338 static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host)
339 {
340 }
341
342 #endif
343
ufs_qcom_disable_lane_clks(struct ufs_qcom_host * host)344 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
345 {
346 if (!host->is_lane_clks_enabled)
347 return;
348
349 clk_bulk_disable_unprepare(host->num_clks, host->clks);
350
351 host->is_lane_clks_enabled = false;
352 }
353
ufs_qcom_enable_lane_clks(struct ufs_qcom_host * host)354 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
355 {
356 int err;
357
358 err = clk_bulk_prepare_enable(host->num_clks, host->clks);
359 if (err)
360 return err;
361
362 host->is_lane_clks_enabled = true;
363
364 return 0;
365 }
366
ufs_qcom_init_lane_clks(struct ufs_qcom_host * host)367 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
368 {
369 int err;
370 struct device *dev = host->hba->dev;
371
372 if (has_acpi_companion(dev))
373 return 0;
374
375 err = devm_clk_bulk_get_all(dev, &host->clks);
376 if (err <= 0)
377 return err;
378
379 host->num_clks = err;
380
381 return 0;
382 }
383
ufs_qcom_check_hibern8(struct ufs_hba * hba)384 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
385 {
386 int err;
387 u32 tx_fsm_val;
388 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
389
390 do {
391 err = ufshcd_dme_get(hba,
392 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
393 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
394 &tx_fsm_val);
395 if (err || tx_fsm_val == TX_FSM_HIBERN8)
396 break;
397
398 /* sleep for max. 200us */
399 usleep_range(100, 200);
400 } while (time_before(jiffies, timeout));
401
402 /*
403 * we might have scheduled out for long during polling so
404 * check the state again.
405 */
406 if (time_after(jiffies, timeout))
407 err = ufshcd_dme_get(hba,
408 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
409 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
410 &tx_fsm_val);
411
412 if (err) {
413 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
414 __func__, err);
415 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
416 err = tx_fsm_val;
417 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
418 __func__, err);
419 }
420
421 return err;
422 }
423
ufs_qcom_select_unipro_mode(struct ufs_qcom_host * host)424 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
425 {
426 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1);
427
428 if (host->hw_ver.major >= 0x05)
429 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0);
430 }
431
432 /*
433 * ufs_qcom_host_reset - reset host controller and PHY
434 */
ufs_qcom_host_reset(struct ufs_hba * hba)435 static int ufs_qcom_host_reset(struct ufs_hba *hba)
436 {
437 int ret;
438 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
439 bool reenable_intr;
440
441 if (!host->core_reset)
442 return 0;
443
444 reenable_intr = hba->is_irq_enabled;
445 ufshcd_disable_irq(hba);
446
447 ret = reset_control_assert(host->core_reset);
448 if (ret) {
449 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
450 __func__, ret);
451 return ret;
452 }
453
454 /*
455 * The hardware requirement for delay between assert/deassert
456 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
457 * ~125us (4/32768). To be on the safe side add 200us delay.
458 */
459 usleep_range(200, 210);
460
461 ret = reset_control_deassert(host->core_reset);
462 if (ret) {
463 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
464 __func__, ret);
465 return ret;
466 }
467
468 usleep_range(1000, 1100);
469
470 if (reenable_intr)
471 ufshcd_enable_irq(hba);
472
473 return 0;
474 }
475
ufs_qcom_get_hs_gear(struct ufs_hba * hba)476 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
477 {
478 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
479
480 if (host->hw_ver.major >= 0x4)
481 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0));
482
483 /* Default is HS-G3 */
484 return UFS_HS_G3;
485 }
486
ufs_qcom_power_up_sequence(struct ufs_hba * hba)487 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
488 {
489 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
490 struct ufs_host_params *host_params = &host->host_params;
491 struct phy *phy = host->generic_phy;
492 enum phy_mode mode;
493 int ret;
494
495 /*
496 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
497 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
498 * so that the subsequent power mode change shall stick to Rate-A.
499 */
500 if (host->hw_ver.major == 0x5 && host->phy_gear == UFS_HS_G5)
501 host_params->hs_rate = PA_HS_MODE_A;
502
503 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
504
505 /* Reset UFS Host Controller and PHY */
506 ret = ufs_qcom_host_reset(hba);
507 if (ret)
508 return ret;
509
510 if (phy->power_count)
511 phy_power_off(phy);
512
513
514 /* phy initialization - calibrate the phy */
515 ret = phy_init(phy);
516 if (ret) {
517 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
518 __func__, ret);
519 return ret;
520 }
521
522 ret = phy_set_mode_ext(phy, mode, host->phy_gear);
523 if (ret)
524 goto out_disable_phy;
525
526 /* power on phy - start serdes and phy's power and clocks */
527 ret = phy_power_on(phy);
528 if (ret) {
529 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
530 __func__, ret);
531 goto out_disable_phy;
532 }
533
534 ret = phy_calibrate(phy);
535 if (ret) {
536 dev_err(hba->dev, "Failed to calibrate PHY: %d\n", ret);
537 goto out_disable_phy;
538 }
539
540 ufs_qcom_select_unipro_mode(host);
541
542 return 0;
543
544 out_disable_phy:
545 phy_exit(phy);
546
547 return ret;
548 }
549
550 /*
551 * The UTP controller has a number of internal clock gating cells (CGCs).
552 * Internal hardware sub-modules within the UTP controller control the CGCs.
553 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
554 * in a specific operation, UTP controller CGCs are by default disabled and
555 * this function enables them (after every UFS link startup) to save some power
556 * leakage.
557 */
ufs_qcom_enable_hw_clk_gating(struct ufs_hba * hba)558 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
559 {
560 int err;
561
562 /* Enable UTP internal clock gating */
563 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL,
564 REG_UFS_CFG2);
565
566 /* Ensure that HW clock gating is enabled before next operations */
567 ufshcd_readl(hba, REG_UFS_CFG2);
568
569 /* Enable Unipro internal clock gating */
570 err = ufshcd_dme_rmw(hba, DL_VS_CLK_CFG_MASK,
571 DL_VS_CLK_CFG_MASK, DL_VS_CLK_CFG);
572 if (err)
573 goto out;
574
575 err = ufshcd_dme_rmw(hba, PA_VS_CLK_CFG_REG_MASK,
576 PA_VS_CLK_CFG_REG_MASK, PA_VS_CLK_CFG_REG);
577 if (err)
578 goto out;
579
580 err = ufshcd_dme_rmw(hba, DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN,
581 DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN,
582 DME_VS_CORE_CLK_CTRL);
583 out:
584 if (err)
585 dev_err(hba->dev, "hw clk gating enabled failed\n");
586 }
587
ufs_qcom_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)588 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
589 enum ufs_notify_change_status status)
590 {
591 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
592 int err;
593
594 switch (status) {
595 case PRE_CHANGE:
596 err = ufs_qcom_power_up_sequence(hba);
597 if (err)
598 return err;
599
600 /*
601 * The PHY PLL output is the source of tx/rx lane symbol
602 * clocks, hence, enable the lane clocks only after PHY
603 * is initialized.
604 */
605 err = ufs_qcom_enable_lane_clks(host);
606 break;
607 case POST_CHANGE:
608 /* check if UFS PHY moved from DISABLED to HIBERN8 */
609 err = ufs_qcom_check_hibern8(hba);
610 ufs_qcom_enable_hw_clk_gating(hba);
611 ufs_qcom_ice_enable(host);
612 ufs_qcom_config_ice_allocator(host);
613 break;
614 default:
615 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
616 err = -EINVAL;
617 break;
618 }
619 return err;
620 }
621
622 /**
623 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers
624 *
625 * @hba: host controller instance
626 * @is_pre_scale_up: flag to check if pre scale up condition.
627 * @freq: target opp freq
628 * Return: zero for success and non-zero in case of a failure.
629 */
ufs_qcom_cfg_timers(struct ufs_hba * hba,bool is_pre_scale_up,unsigned long freq)630 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up, unsigned long freq)
631 {
632 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
633 struct ufs_clk_info *clki;
634 unsigned long clk_freq = 0;
635 u32 core_clk_cycles_per_us;
636
637 /*
638 * UTP controller uses SYS1CLK_1US_REG register for Interrupt
639 * Aggregation logic.
640 * It is mandatory to write SYS1CLK_1US_REG register on UFS host
641 * controller V4.0.0 onwards.
642 */
643 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba))
644 return 0;
645
646 if (hba->use_pm_opp && freq != ULONG_MAX) {
647 clk_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk");
648 if (clk_freq)
649 goto cfg_timers;
650 }
651
652 list_for_each_entry(clki, &hba->clk_list_head, list) {
653 if (!strcmp(clki->name, "core_clk")) {
654 if (freq == ULONG_MAX) {
655 clk_freq = clki->max_freq;
656 break;
657 }
658
659 if (is_pre_scale_up)
660 clk_freq = clki->max_freq;
661 else
662 clk_freq = clk_get_rate(clki->clk);
663 break;
664 }
665
666 }
667
668 cfg_timers:
669 /* If frequency is smaller than 1MHz, set to 1MHz */
670 if (clk_freq < DEFAULT_CLK_RATE_HZ)
671 clk_freq = DEFAULT_CLK_RATE_HZ;
672
673 core_clk_cycles_per_us = clk_freq / USEC_PER_SEC;
674 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
675 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
676 /*
677 * make sure above write gets applied before we return from
678 * this function.
679 */
680 ufshcd_readl(hba, REG_UFS_SYS1CLK_1US);
681 }
682
683 return 0;
684 }
685
ufs_qcom_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)686 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
687 enum ufs_notify_change_status status)
688 {
689 int err = 0;
690
691 switch (status) {
692 case PRE_CHANGE:
693 if (ufs_qcom_cfg_timers(hba, false, ULONG_MAX)) {
694 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
695 __func__);
696 return -EINVAL;
697 }
698
699 err = ufs_qcom_set_core_clk_ctrl(hba, true, ULONG_MAX);
700 if (err)
701 dev_err(hba->dev, "cfg core clk ctrl failed\n");
702 /*
703 * Some UFS devices (and may be host) have issues if LCC is
704 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
705 * before link startup which will make sure that both host
706 * and device TX LCC are disabled once link startup is
707 * completed.
708 */
709 err = ufshcd_disable_host_tx_lcc(hba);
710
711 break;
712 default:
713 break;
714 }
715
716 return err;
717 }
718
ufs_qcom_device_reset_ctrl(struct ufs_hba * hba,bool asserted)719 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted)
720 {
721 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
722
723 /* reset gpio is optional */
724 if (!host->device_reset)
725 return;
726
727 gpiod_set_value_cansleep(host->device_reset, asserted);
728 }
729
ufs_qcom_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op,enum ufs_notify_change_status status)730 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
731 enum ufs_notify_change_status status)
732 {
733 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
734
735 if (status == PRE_CHANGE)
736 return 0;
737
738 if (!ufs_qcom_is_link_active(hba))
739 ufs_qcom_disable_lane_clks(host);
740
741
742 /* reset the connected UFS device during power down */
743 if (ufs_qcom_is_link_off(hba) && host->device_reset) {
744 ufs_qcom_device_reset_ctrl(hba, true);
745 /*
746 * After sending the SSU command, asserting the rst_n
747 * line causes the device firmware to wake up and
748 * execute its reset routine.
749 *
750 * During this process, the device may draw current
751 * beyond the permissible limit for low-power mode (LPM).
752 * A 10ms delay, based on experimental observations,
753 * allows the UFS device to complete its hardware reset
754 * before transitioning the power rail to LPM.
755 */
756 usleep_range(10000, 11000);
757 }
758
759 return ufs_qcom_ice_suspend(host);
760 }
761
ufs_qcom_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)762 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
763 {
764 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
765 int err;
766 u32 reg_val;
767
768 err = ufs_qcom_enable_lane_clks(host);
769 if (err)
770 return err;
771
772 if ((!ufs_qcom_is_link_active(hba)) &&
773 host->hw_ver.major == 5 &&
774 host->hw_ver.minor == 0 &&
775 host->hw_ver.step == 0) {
776 ufshcd_writel(hba, UFS_ICE_SYNC_RST_SEL | UFS_ICE_SYNC_RST_SW, UFS_MEM_ICE_CFG);
777 reg_val = ufshcd_readl(hba, UFS_MEM_ICE_CFG);
778 reg_val &= ~(UFS_ICE_SYNC_RST_SEL | UFS_ICE_SYNC_RST_SW);
779 /*
780 * HW documentation doesn't recommend any delay between the
781 * reset set and clear. But we are enforcing an arbitrary delay
782 * to give flops enough time to settle in.
783 */
784 usleep_range(50, 100);
785 ufshcd_writel(hba, reg_val, UFS_MEM_ICE_CFG);
786 ufshcd_readl(hba, UFS_MEM_ICE_CFG);
787 }
788
789 return ufs_qcom_ice_resume(host);
790 }
791
ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host * host,bool enable)792 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
793 {
794 if (host->dev_ref_clk_ctrl_mmio &&
795 (enable ^ host->is_dev_ref_clk_enabled)) {
796 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
797
798 if (enable)
799 temp |= host->dev_ref_clk_en_mask;
800 else
801 temp &= ~host->dev_ref_clk_en_mask;
802
803 /*
804 * If we are here to disable this clock it might be immediately
805 * after entering into hibern8 in which case we need to make
806 * sure that device ref_clk is active for specific time after
807 * hibern8 enter.
808 */
809 if (!enable) {
810 unsigned long gating_wait;
811
812 gating_wait = host->hba->dev_info.clk_gating_wait_us;
813 if (!gating_wait) {
814 udelay(1);
815 } else {
816 /*
817 * bRefClkGatingWaitTime defines the minimum
818 * time for which the reference clock is
819 * required by device during transition from
820 * HS-MODE to LS-MODE or HIBERN8 state. Give it
821 * more delay to be on the safe side.
822 */
823 gating_wait += 10;
824 usleep_range(gating_wait, gating_wait + 10);
825 }
826 }
827
828 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
829
830 /*
831 * Make sure the write to ref_clk reaches the destination and
832 * not stored in a Write Buffer (WB).
833 */
834 readl(host->dev_ref_clk_ctrl_mmio);
835
836 /*
837 * If we call hibern8 exit after this, we need to make sure that
838 * device ref_clk is stable for at least 1us before the hibern8
839 * exit command.
840 */
841 if (enable)
842 udelay(1);
843
844 host->is_dev_ref_clk_enabled = enable;
845 }
846 }
847
ufs_qcom_icc_set_bw(struct ufs_qcom_host * host,u32 mem_bw,u32 cfg_bw)848 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw)
849 {
850 struct device *dev = host->hba->dev;
851 int ret;
852
853 ret = icc_set_bw(host->icc_ddr, 0, mem_bw);
854 if (ret < 0) {
855 dev_err(dev, "failed to set bandwidth request: %d\n", ret);
856 return ret;
857 }
858
859 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw);
860 if (ret < 0) {
861 dev_err(dev, "failed to set bandwidth request: %d\n", ret);
862 return ret;
863 }
864
865 return 0;
866 }
867
ufs_qcom_get_bw_table(struct ufs_qcom_host * host)868 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host)
869 {
870 struct ufs_pa_layer_attr *p = &host->dev_req_params;
871 int gear = max_t(u32, p->gear_rx, p->gear_tx);
872 int lane = max_t(u32, p->lane_rx, p->lane_tx);
873
874 if (WARN_ONCE(gear > QCOM_UFS_MAX_GEAR,
875 "ICC scaling for UFS Gear (%d) not supported. Using Gear (%d) bandwidth\n",
876 gear, QCOM_UFS_MAX_GEAR))
877 gear = QCOM_UFS_MAX_GEAR;
878
879 if (WARN_ONCE(lane > QCOM_UFS_MAX_LANE,
880 "ICC scaling for UFS Lane (%d) not supported. Using Lane (%d) bandwidth\n",
881 lane, QCOM_UFS_MAX_LANE))
882 lane = QCOM_UFS_MAX_LANE;
883
884 if (ufshcd_is_hs_mode(p)) {
885 if (p->hs_rate == PA_HS_MODE_B)
886 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane];
887 else
888 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane];
889 } else {
890 return ufs_qcom_bw_table[MODE_PWM][gear][lane];
891 }
892 }
893
ufs_qcom_icc_update_bw(struct ufs_qcom_host * host)894 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host)
895 {
896 struct __ufs_qcom_bw_table bw_table;
897
898 bw_table = ufs_qcom_get_bw_table(host);
899
900 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw);
901 }
902
ufs_qcom_set_tx_hs_equalizer(struct ufs_hba * hba,u32 gear,u32 tx_lanes)903 static void ufs_qcom_set_tx_hs_equalizer(struct ufs_hba *hba, u32 gear, u32 tx_lanes)
904 {
905 u32 equalizer_val;
906 int ret, i;
907
908 /* Determine the equalizer value based on the gear */
909 equalizer_val = (gear == 5) ? DEEMPHASIS_3_5_dB : NO_DEEMPHASIS;
910
911 for (i = 0; i < tx_lanes; i++) {
912 ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HS_EQUALIZER, i),
913 equalizer_val);
914 if (ret)
915 dev_err(hba->dev, "%s: failed equalizer lane %d\n",
916 __func__, i);
917 }
918 }
919
ufs_qcom_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,const struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)920 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
921 enum ufs_notify_change_status status,
922 const struct ufs_pa_layer_attr *dev_max_params,
923 struct ufs_pa_layer_attr *dev_req_params)
924 {
925 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
926 struct ufs_host_params *host_params = &host->host_params;
927 int ret = 0;
928
929 if (!dev_req_params) {
930 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
931 return -EINVAL;
932 }
933
934 switch (status) {
935 case PRE_CHANGE:
936 ret = ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params);
937 if (ret) {
938 dev_err(hba->dev, "%s: failed to determine capabilities\n",
939 __func__);
940 return ret;
941 }
942
943 /*
944 * During UFS driver probe, always update the PHY gear to match the negotiated
945 * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled,
946 * the second init can program the optimal PHY settings. This allows one to start
947 * the first init with either the minimum or the maximum support gear.
948 */
949 if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
950 /*
951 * Skip REINIT if the negotiated gear matches with the
952 * initial phy_gear. Otherwise, update the phy_gear to
953 * program the optimal gear setting during REINIT.
954 */
955 if (host->phy_gear == dev_req_params->gear_tx)
956 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
957 else
958 host->phy_gear = dev_req_params->gear_tx;
959 }
960
961 /* enable the device ref clock before changing to HS mode */
962 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
963 ufshcd_is_hs_mode(dev_req_params))
964 ufs_qcom_dev_ref_clk_ctrl(host, true);
965
966 if (host->hw_ver.major >= 0x4) {
967 ufshcd_dme_configure_adapt(hba,
968 dev_req_params->gear_tx,
969 PA_INITIAL_ADAPT);
970 }
971
972 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING)
973 ufs_qcom_set_tx_hs_equalizer(hba,
974 dev_req_params->gear_tx, dev_req_params->lane_tx);
975
976 break;
977 case POST_CHANGE:
978 /* cache the power mode parameters to use internally */
979 memcpy(&host->dev_req_params,
980 dev_req_params, sizeof(*dev_req_params));
981
982 ufs_qcom_icc_update_bw(host);
983
984 /* disable the device ref clock if entered PWM mode */
985 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
986 !ufshcd_is_hs_mode(dev_req_params))
987 ufs_qcom_dev_ref_clk_ctrl(host, false);
988 break;
989 default:
990 ret = -EINVAL;
991 break;
992 }
993
994 return ret;
995 }
996
ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba * hba)997 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
998 {
999 int err;
1000 u32 pa_vs_config_reg1;
1001
1002 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1003 &pa_vs_config_reg1);
1004 if (err)
1005 return err;
1006
1007 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
1008 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1009 (pa_vs_config_reg1 | (1 << 12)));
1010 }
1011
ufs_qcom_override_pa_tx_hsg1_sync_len(struct ufs_hba * hba)1012 static void ufs_qcom_override_pa_tx_hsg1_sync_len(struct ufs_hba *hba)
1013 {
1014 int err;
1015
1016 err = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TX_HSG1_SYNC_LENGTH),
1017 PA_TX_HSG1_SYNC_LENGTH_VAL);
1018 if (err)
1019 dev_err(hba->dev, "Failed (%d) set PA_TX_HSG1_SYNC_LENGTH\n", err);
1020 }
1021
ufs_qcom_apply_dev_quirks(struct ufs_hba * hba)1022 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
1023 {
1024 int err = 0;
1025
1026 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
1027 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
1028
1029 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH)
1030 ufs_qcom_override_pa_tx_hsg1_sync_len(hba);
1031
1032 return err;
1033 }
1034
1035 /* UFS device-specific quirks */
1036 static struct ufs_dev_quirk ufs_qcom_dev_fixups[] = {
1037 { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
1038 .model = UFS_ANY_MODEL,
1039 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
1040 { .wmanufacturerid = UFS_VENDOR_WDC,
1041 .model = UFS_ANY_MODEL,
1042 .quirk = UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE },
1043 { .wmanufacturerid = UFS_VENDOR_SAMSUNG,
1044 .model = UFS_ANY_MODEL,
1045 .quirk = UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH |
1046 UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING },
1047 {}
1048 };
1049
ufs_qcom_fixup_dev_quirks(struct ufs_hba * hba)1050 static void ufs_qcom_fixup_dev_quirks(struct ufs_hba *hba)
1051 {
1052 ufshcd_fixup_dev_quirks(hba, ufs_qcom_dev_fixups);
1053 }
1054
ufs_qcom_get_ufs_hci_version(struct ufs_hba * hba)1055 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
1056 {
1057 return ufshci_version(2, 0);
1058 }
1059
1060 /**
1061 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
1062 * @hba: host controller instance
1063 *
1064 * QCOM UFS host controller might have some non standard behaviours (quirks)
1065 * than what is specified by UFSHCI specification. Advertise all such
1066 * quirks to standard UFS host controller driver so standard takes them into
1067 * account.
1068 */
ufs_qcom_advertise_quirks(struct ufs_hba * hba)1069 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
1070 {
1071 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev);
1072 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1073
1074 if (host->hw_ver.major == 0x2)
1075 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
1076
1077 if (host->hw_ver.major > 0x3)
1078 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
1079
1080 if (drvdata && drvdata->quirks)
1081 hba->quirks |= drvdata->quirks;
1082 }
1083
ufs_qcom_set_phy_gear(struct ufs_qcom_host * host)1084 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
1085 {
1086 struct ufs_host_params *host_params = &host->host_params;
1087 u32 val, dev_major;
1088
1089 /*
1090 * Default to powering up the PHY to the max gear possible, which is
1091 * backwards compatible with lower gears but not optimal from
1092 * a power usage point of view. After device negotiation, if the
1093 * gear is lower a reinit will be performed to program the PHY
1094 * to the ideal gear for this combo of controller and device.
1095 */
1096 host->phy_gear = host_params->hs_tx_gear;
1097
1098 if (host->hw_ver.major < 0x4) {
1099 /*
1100 * These controllers only have one PHY init sequence,
1101 * let's power up the PHY using that (the minimum supported
1102 * gear, UFS_HS_G2).
1103 */
1104 host->phy_gear = UFS_HS_G2;
1105 } else if (host->hw_ver.major >= 0x5) {
1106 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
1107 dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val);
1108
1109 /*
1110 * Since the UFS device version is populated, let's remove the
1111 * REINIT quirk as the negotiated gear won't change during boot.
1112 * So there is no need to do reinit.
1113 */
1114 if (dev_major != 0x0)
1115 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
1116
1117 /*
1118 * For UFS 3.1 device and older, power up the PHY using HS-G4
1119 * PHY gear to save power.
1120 */
1121 if (dev_major > 0x0 && dev_major < 0x4)
1122 host->phy_gear = UFS_HS_G4;
1123 }
1124 }
1125
ufs_qcom_parse_gear_limits(struct ufs_hba * hba)1126 static void ufs_qcom_parse_gear_limits(struct ufs_hba *hba)
1127 {
1128 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1129 struct ufs_host_params *host_params = &host->host_params;
1130 u32 hs_gear_old = host_params->hs_tx_gear;
1131
1132 ufshcd_parse_gear_limits(hba, host_params);
1133 if (host_params->hs_tx_gear != hs_gear_old) {
1134 host->phy_gear = host_params->hs_tx_gear;
1135 }
1136 }
1137
ufs_qcom_set_host_params(struct ufs_hba * hba)1138 static void ufs_qcom_set_host_params(struct ufs_hba *hba)
1139 {
1140 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1141 struct ufs_host_params *host_params = &host->host_params;
1142
1143 ufshcd_init_host_params(host_params);
1144
1145 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
1146 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba);
1147 }
1148
ufs_qcom_set_host_caps(struct ufs_hba * hba)1149 static void ufs_qcom_set_host_caps(struct ufs_hba *hba)
1150 {
1151 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1152
1153 if (host->hw_ver.major >= 0x5)
1154 host->caps |= UFS_QCOM_CAP_ICE_CONFIG;
1155 }
1156
ufs_qcom_set_caps(struct ufs_hba * hba)1157 static void ufs_qcom_set_caps(struct ufs_hba *hba)
1158 {
1159 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1160 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING;
1161 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1162 hba->caps |= UFSHCD_CAP_WB_EN;
1163 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE;
1164 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
1165
1166 ufs_qcom_set_host_caps(hba);
1167 }
1168
1169 /**
1170 * ufs_qcom_setup_clocks - enables/disable clocks
1171 * @hba: host controller instance
1172 * @on: If true, enable clocks else disable them.
1173 * @status: PRE_CHANGE or POST_CHANGE notify
1174 *
1175 * There are certain clocks which comes from the PHY so it needs
1176 * to be managed together along with controller clocks which also
1177 * provides a better power saving. Hence keep phy_power_off/on calls
1178 * in ufs_qcom_setup_clocks, so that PHY's regulators & clks can be
1179 * turned on/off along with UFS's clocks.
1180 *
1181 * Return: 0 on success, non-zero on failure.
1182 */
ufs_qcom_setup_clocks(struct ufs_hba * hba,bool on,enum ufs_notify_change_status status)1183 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
1184 enum ufs_notify_change_status status)
1185 {
1186 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1187 struct phy *phy;
1188 int err;
1189
1190 /*
1191 * In case ufs_qcom_init() is not yet done, simply ignore.
1192 * This ufs_qcom_setup_clocks() shall be called from
1193 * ufs_qcom_init() after init is done.
1194 */
1195 if (!host)
1196 return 0;
1197
1198 phy = host->generic_phy;
1199
1200 switch (status) {
1201 case PRE_CHANGE:
1202 if (on) {
1203 ufs_qcom_icc_update_bw(host);
1204 if (ufs_qcom_is_link_hibern8(hba)) {
1205 err = ufs_qcom_enable_lane_clks(host);
1206 if (err) {
1207 dev_err(hba->dev, "enable lane clks failed, ret=%d\n", err);
1208 return err;
1209 }
1210 }
1211 } else {
1212 if (!ufs_qcom_is_link_active(hba)) {
1213 /* disable device ref_clk */
1214 ufs_qcom_dev_ref_clk_ctrl(host, false);
1215 }
1216
1217 err = phy_power_off(phy);
1218 if (err) {
1219 dev_err(hba->dev, "phy power off failed, ret=%d\n", err);
1220 return err;
1221 }
1222 }
1223 break;
1224 case POST_CHANGE:
1225 if (on) {
1226 err = phy_power_on(phy);
1227 if (err) {
1228 dev_err(hba->dev, "phy power on failed, ret = %d\n", err);
1229 return err;
1230 }
1231
1232 /* enable the device ref clock for HS mode*/
1233 if (ufshcd_is_hs_mode(&hba->pwr_info))
1234 ufs_qcom_dev_ref_clk_ctrl(host, true);
1235 } else {
1236 if (ufs_qcom_is_link_hibern8(hba))
1237 ufs_qcom_disable_lane_clks(host);
1238
1239 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw,
1240 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw);
1241 }
1242 break;
1243 }
1244
1245 return 0;
1246 }
1247
1248 static int
ufs_qcom_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)1249 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
1250 {
1251 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1252
1253 ufs_qcom_assert_reset(host->hba);
1254 /* provide 1ms delay to let the reset pulse propagate. */
1255 usleep_range(1000, 1100);
1256 return 0;
1257 }
1258
1259 static int
ufs_qcom_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)1260 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
1261 {
1262 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1263
1264 ufs_qcom_deassert_reset(host->hba);
1265
1266 /*
1267 * after reset deassertion, phy will need all ref clocks,
1268 * voltage, current to settle down before starting serdes.
1269 */
1270 usleep_range(1000, 1100);
1271 return 0;
1272 }
1273
1274 static const struct reset_control_ops ufs_qcom_reset_ops = {
1275 .assert = ufs_qcom_reset_assert,
1276 .deassert = ufs_qcom_reset_deassert,
1277 };
1278
ufs_qcom_icc_init(struct ufs_qcom_host * host)1279 static int ufs_qcom_icc_init(struct ufs_qcom_host *host)
1280 {
1281 struct device *dev = host->hba->dev;
1282 int ret;
1283
1284 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr");
1285 if (IS_ERR(host->icc_ddr))
1286 return dev_err_probe(dev, PTR_ERR(host->icc_ddr),
1287 "failed to acquire interconnect path\n");
1288
1289 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs");
1290 if (IS_ERR(host->icc_cpu))
1291 return dev_err_probe(dev, PTR_ERR(host->icc_cpu),
1292 "failed to acquire interconnect path\n");
1293
1294 /*
1295 * Set Maximum bandwidth vote before initializing the UFS controller and
1296 * device. Ideally, a minimal interconnect vote would suffice for the
1297 * initialization, but a max vote would allow faster initialization.
1298 */
1299 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw,
1300 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw);
1301 if (ret < 0)
1302 return dev_err_probe(dev, ret, "failed to set bandwidth request\n");
1303
1304 return 0;
1305 }
1306
1307 /**
1308 * ufs_qcom_init - bind phy with controller
1309 * @hba: host controller instance
1310 *
1311 * Binds PHY with controller and powers up PHY enabling clocks
1312 * and regulators.
1313 *
1314 * Return: -EPROBE_DEFER if binding fails, returns negative error
1315 * on phy power up failure and returns zero on success.
1316 */
ufs_qcom_init(struct ufs_hba * hba)1317 static int ufs_qcom_init(struct ufs_hba *hba)
1318 {
1319 int err;
1320 struct device *dev = hba->dev;
1321 struct ufs_qcom_host *host;
1322 struct ufs_clk_info *clki;
1323 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev);
1324
1325 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1326 if (!host)
1327 return -ENOMEM;
1328
1329 /* Make a two way bind between the qcom host and the hba */
1330 host->hba = hba;
1331 ufshcd_set_variant(hba, host);
1332
1333 /* Setup the optional reset control of HCI */
1334 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst");
1335 if (IS_ERR(host->core_reset)) {
1336 err = dev_err_probe(dev, PTR_ERR(host->core_reset),
1337 "Failed to get reset control\n");
1338 goto out_variant_clear;
1339 }
1340
1341 /* Fire up the reset controller. Failure here is non-fatal. */
1342 host->rcdev.of_node = dev->of_node;
1343 host->rcdev.ops = &ufs_qcom_reset_ops;
1344 host->rcdev.owner = dev->driver->owner;
1345 host->rcdev.nr_resets = 1;
1346 err = devm_reset_controller_register(dev, &host->rcdev);
1347 if (err)
1348 dev_warn(dev, "Failed to register reset controller\n");
1349
1350 if (!has_acpi_companion(dev)) {
1351 host->generic_phy = devm_phy_get(dev, "ufsphy");
1352 if (IS_ERR(host->generic_phy)) {
1353 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n");
1354 goto out_variant_clear;
1355 }
1356 }
1357
1358 err = ufs_qcom_icc_init(host);
1359 if (err)
1360 goto out_variant_clear;
1361
1362 host->device_reset = devm_gpiod_get_optional(dev, "reset",
1363 GPIOD_OUT_HIGH);
1364 if (IS_ERR(host->device_reset)) {
1365 err = dev_err_probe(dev, PTR_ERR(host->device_reset),
1366 "Failed to acquire device reset gpio\n");
1367 goto out_variant_clear;
1368 }
1369
1370 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1371 &host->hw_ver.minor, &host->hw_ver.step);
1372
1373 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1374 host->dev_ref_clk_en_mask = BIT(26);
1375
1376 list_for_each_entry(clki, &hba->clk_list_head, list) {
1377 if (!strcmp(clki->name, "core_clk_unipro"))
1378 clki->keep_link_active = true;
1379 }
1380
1381 err = ufs_qcom_init_lane_clks(host);
1382 if (err)
1383 goto out_variant_clear;
1384
1385 ufs_qcom_set_caps(hba);
1386 ufs_qcom_advertise_quirks(hba);
1387 ufs_qcom_set_host_params(hba);
1388 ufs_qcom_set_phy_gear(host);
1389 ufs_qcom_parse_gear_limits(hba);
1390
1391 err = ufs_qcom_ice_init(host);
1392 if (err)
1393 goto out_variant_clear;
1394
1395 ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1396
1397 ufs_qcom_get_default_testbus_cfg(host);
1398 err = ufs_qcom_testbus_config(host);
1399 if (err)
1400 /* Failure is non-fatal */
1401 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1402 __func__, err);
1403
1404 if (drvdata && drvdata->no_phy_retention)
1405 hba->spm_lvl = UFS_PM_LVL_5;
1406
1407 return 0;
1408
1409 out_variant_clear:
1410 ufshcd_set_variant(hba, NULL);
1411
1412 return err;
1413 }
1414
ufs_qcom_exit(struct ufs_hba * hba)1415 static void ufs_qcom_exit(struct ufs_hba *hba)
1416 {
1417 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1418
1419 ufs_qcom_disable_lane_clks(host);
1420 phy_power_off(host->generic_phy);
1421 phy_exit(host->generic_phy);
1422 }
1423
1424 /**
1425 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles
1426 *
1427 * @hba: host controller instance
1428 * @cycles_in_1us: No of cycles in 1us to be configured
1429 *
1430 * Returns error if dme get/set configuration for 40ns fails
1431 * and returns zero on success.
1432 */
ufs_qcom_set_clk_40ns_cycles(struct ufs_hba * hba,u32 cycles_in_1us)1433 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba,
1434 u32 cycles_in_1us)
1435 {
1436 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1437 u32 cycles_in_40ns;
1438 u32 reg;
1439 int err;
1440
1441 /*
1442 * UFS host controller V4.0.0 onwards needs to program
1443 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed
1444 * frequency of unipro core clk of UFS host controller.
1445 */
1446 if (host->hw_ver.major < 4)
1447 return 0;
1448
1449 /*
1450 * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not
1451 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will
1452 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware
1453 * specification expect to be 16. Hence use exact hardware spec
1454 * mandated value for cycles_in_40ns instead of calculating using
1455 * generic formulae.
1456 */
1457 switch (cycles_in_1us) {
1458 case UNIPRO_CORE_CLK_FREQ_403_MHZ:
1459 cycles_in_40ns = 16;
1460 break;
1461 case UNIPRO_CORE_CLK_FREQ_300_MHZ:
1462 cycles_in_40ns = 12;
1463 break;
1464 case UNIPRO_CORE_CLK_FREQ_201_5_MHZ:
1465 cycles_in_40ns = 8;
1466 break;
1467 case UNIPRO_CORE_CLK_FREQ_150_MHZ:
1468 cycles_in_40ns = 6;
1469 break;
1470 case UNIPRO_CORE_CLK_FREQ_100_MHZ:
1471 cycles_in_40ns = 4;
1472 break;
1473 case UNIPRO_CORE_CLK_FREQ_75_MHZ:
1474 cycles_in_40ns = 3;
1475 break;
1476 case UNIPRO_CORE_CLK_FREQ_37_5_MHZ:
1477 cycles_in_40ns = 2;
1478 break;
1479 default:
1480 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n",
1481 cycles_in_1us);
1482 return -EINVAL;
1483 }
1484
1485 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®);
1486 if (err)
1487 return err;
1488
1489 reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK;
1490 reg |= cycles_in_40ns;
1491
1492 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg);
1493 }
1494
ufs_qcom_set_core_clk_ctrl(struct ufs_hba * hba,bool is_scale_up,unsigned long freq)1495 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up, unsigned long freq)
1496 {
1497 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1498 struct list_head *head = &hba->clk_list_head;
1499 struct ufs_clk_info *clki;
1500 u32 cycles_in_1us = 0;
1501 u32 core_clk_ctrl_reg;
1502 unsigned long clk_freq;
1503 int err;
1504
1505 if (hba->use_pm_opp && freq != ULONG_MAX) {
1506 clk_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk_unipro");
1507 if (clk_freq) {
1508 cycles_in_1us = ceil(clk_freq, HZ_PER_MHZ);
1509 goto set_core_clk_ctrl;
1510 }
1511 }
1512
1513 list_for_each_entry(clki, head, list) {
1514 if (!IS_ERR_OR_NULL(clki->clk) &&
1515 !strcmp(clki->name, "core_clk_unipro")) {
1516 if (!clki->max_freq) {
1517 cycles_in_1us = 150; /* default for backwards compatibility */
1518 break;
1519 }
1520
1521 if (freq == ULONG_MAX) {
1522 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ);
1523 break;
1524 }
1525
1526 if (is_scale_up)
1527 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ);
1528 else
1529 cycles_in_1us = ceil(clk_get_rate(clki->clk), HZ_PER_MHZ);
1530 break;
1531 }
1532 }
1533
1534 set_core_clk_ctrl:
1535 err = ufshcd_dme_get(hba,
1536 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1537 &core_clk_ctrl_reg);
1538 if (err)
1539 return err;
1540
1541 /* Bit mask is different for UFS host controller V4.0.0 onwards */
1542 if (host->hw_ver.major >= 4) {
1543 if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us))
1544 return -ERANGE;
1545 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4;
1546 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us);
1547 } else {
1548 if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us))
1549 return -ERANGE;
1550 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK;
1551 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us);
1552 }
1553
1554 /* Clear CORE_CLK_DIV_EN */
1555 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1556
1557 err = ufshcd_dme_set(hba,
1558 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1559 core_clk_ctrl_reg);
1560 if (err)
1561 return err;
1562
1563 /* Configure unipro core clk 40ns attribute */
1564 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us);
1565 }
1566
ufs_qcom_clk_scale_up_pre_change(struct ufs_hba * hba,unsigned long freq)1567 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba, unsigned long freq)
1568 {
1569 int ret;
1570
1571 ret = ufs_qcom_cfg_timers(hba, true, freq);
1572 if (ret) {
1573 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__);
1574 return ret;
1575 }
1576 /* set unipro core clock attributes and clear clock divider */
1577 return ufs_qcom_set_core_clk_ctrl(hba, true, freq);
1578 }
1579
ufs_qcom_clk_scale_up_post_change(struct ufs_hba * hba)1580 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1581 {
1582 return 0;
1583 }
1584
ufs_qcom_clk_scale_down_pre_change(struct ufs_hba * hba)1585 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1586 {
1587 int err;
1588 u32 core_clk_ctrl_reg;
1589
1590 err = ufshcd_dme_get(hba,
1591 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1592 &core_clk_ctrl_reg);
1593
1594 /* make sure CORE_CLK_DIV_EN is cleared */
1595 if (!err &&
1596 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1597 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1598 err = ufshcd_dme_set(hba,
1599 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1600 core_clk_ctrl_reg);
1601 }
1602
1603 return err;
1604 }
1605
ufs_qcom_clk_scale_down_post_change(struct ufs_hba * hba,unsigned long freq)1606 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba, unsigned long freq)
1607 {
1608 int ret;
1609
1610 ret = ufs_qcom_cfg_timers(hba, false, freq);
1611 if (ret) {
1612 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__);
1613 return ret;
1614 }
1615 /* set unipro core clock attributes and clear clock divider */
1616 return ufs_qcom_set_core_clk_ctrl(hba, false, freq);
1617 }
1618
ufs_qcom_clk_scale_notify(struct ufs_hba * hba,bool scale_up,unsigned long target_freq,enum ufs_notify_change_status status)1619 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up,
1620 unsigned long target_freq,
1621 enum ufs_notify_change_status status)
1622 {
1623 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1624 int err;
1625
1626 /* check the host controller state before sending hibern8 cmd */
1627 if (!ufshcd_is_hba_active(hba))
1628 return 0;
1629
1630 if (status == PRE_CHANGE) {
1631 err = ufshcd_uic_hibern8_enter(hba);
1632 if (err)
1633 return err;
1634 if (scale_up)
1635 err = ufs_qcom_clk_scale_up_pre_change(hba, target_freq);
1636 else
1637 err = ufs_qcom_clk_scale_down_pre_change(hba);
1638
1639 if (err) {
1640 ufshcd_uic_hibern8_exit(hba);
1641 return err;
1642 }
1643 } else {
1644 if (scale_up)
1645 err = ufs_qcom_clk_scale_up_post_change(hba);
1646 else
1647 err = ufs_qcom_clk_scale_down_post_change(hba, target_freq);
1648
1649
1650 if (err) {
1651 ufshcd_uic_hibern8_exit(hba);
1652 return err;
1653 }
1654
1655 ufs_qcom_icc_update_bw(host);
1656 ufshcd_uic_hibern8_exit(hba);
1657 }
1658
1659 return 0;
1660 }
1661
ufs_qcom_enable_test_bus(struct ufs_qcom_host * host)1662 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1663 {
1664 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1665 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1666 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1667 }
1668
ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host * host)1669 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1670 {
1671 /* provide a legal default configuration */
1672 host->testbus.select_major = TSTBUS_UNIPRO;
1673 host->testbus.select_minor = 37;
1674 }
1675
ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host * host)1676 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1677 {
1678 if (host->testbus.select_major >= TSTBUS_MAX) {
1679 dev_err(host->hba->dev,
1680 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1681 __func__, host->testbus.select_major);
1682 return false;
1683 }
1684
1685 return true;
1686 }
1687
ufs_qcom_testbus_config(struct ufs_qcom_host * host)1688 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1689 {
1690 int reg;
1691 int offset;
1692 u32 mask = TEST_BUS_SUB_SEL_MASK;
1693
1694 if (!host)
1695 return -EINVAL;
1696
1697 if (!ufs_qcom_testbus_cfg_is_ok(host))
1698 return -EPERM;
1699
1700 switch (host->testbus.select_major) {
1701 case TSTBUS_UAWM:
1702 reg = UFS_TEST_BUS_CTRL_0;
1703 offset = 24;
1704 break;
1705 case TSTBUS_UARM:
1706 reg = UFS_TEST_BUS_CTRL_0;
1707 offset = 16;
1708 break;
1709 case TSTBUS_TXUC:
1710 reg = UFS_TEST_BUS_CTRL_0;
1711 offset = 8;
1712 break;
1713 case TSTBUS_RXUC:
1714 reg = UFS_TEST_BUS_CTRL_0;
1715 offset = 0;
1716 break;
1717 case TSTBUS_DFC:
1718 reg = UFS_TEST_BUS_CTRL_1;
1719 offset = 24;
1720 break;
1721 case TSTBUS_TRLUT:
1722 reg = UFS_TEST_BUS_CTRL_1;
1723 offset = 16;
1724 break;
1725 case TSTBUS_TMRLUT:
1726 reg = UFS_TEST_BUS_CTRL_1;
1727 offset = 8;
1728 break;
1729 case TSTBUS_OCSC:
1730 reg = UFS_TEST_BUS_CTRL_1;
1731 offset = 0;
1732 break;
1733 case TSTBUS_WRAPPER:
1734 reg = UFS_TEST_BUS_CTRL_2;
1735 offset = 16;
1736 break;
1737 case TSTBUS_COMBINED:
1738 reg = UFS_TEST_BUS_CTRL_2;
1739 offset = 8;
1740 break;
1741 case TSTBUS_UTP_HCI:
1742 reg = UFS_TEST_BUS_CTRL_2;
1743 offset = 0;
1744 break;
1745 case TSTBUS_UNIPRO:
1746 reg = UFS_UNIPRO_CFG;
1747 offset = 20;
1748 mask = 0xFFF;
1749 break;
1750 /*
1751 * No need for a default case, since
1752 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1753 * is legal
1754 */
1755 }
1756 mask <<= offset;
1757 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1758 (u32)host->testbus.select_major << 19,
1759 REG_UFS_CFG1);
1760 ufshcd_rmwl(host->hba, mask,
1761 (u32)host->testbus.select_minor << offset,
1762 reg);
1763 ufs_qcom_enable_test_bus(host);
1764
1765 return 0;
1766 }
1767
ufs_qcom_dump_testbus(struct ufs_hba * hba)1768 static void ufs_qcom_dump_testbus(struct ufs_hba *hba)
1769 {
1770 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1771 int i, j, nminor = 0, testbus_len = 0;
1772 u32 *testbus __free(kfree) = NULL;
1773 char *prefix;
1774
1775 testbus = kmalloc_array(256, sizeof(u32), GFP_KERNEL);
1776 if (!testbus)
1777 return;
1778
1779 for (j = 0; j < TSTBUS_MAX; j++) {
1780 nminor = testbus_info[j].nminor;
1781 prefix = testbus_info[j].prefix;
1782 host->testbus.select_major = j;
1783 testbus_len = nminor * sizeof(u32);
1784 for (i = 0; i < nminor; i++) {
1785 host->testbus.select_minor = i;
1786 ufs_qcom_testbus_config(host);
1787 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS);
1788 }
1789 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
1790 16, 4, testbus, testbus_len, false);
1791 }
1792 }
1793
ufs_qcom_dump_regs(struct ufs_hba * hba,size_t offset,size_t len,const char * prefix,void __iomem * base)1794 static int ufs_qcom_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
1795 const char *prefix, void __iomem *base)
1796 {
1797 u32 *regs __free(kfree) = NULL;
1798 size_t pos;
1799
1800 if (offset % 4 != 0 || len % 4 != 0)
1801 return -EINVAL;
1802
1803 regs = kzalloc(len, GFP_ATOMIC);
1804 if (!regs)
1805 return -ENOMEM;
1806
1807 for (pos = 0; pos < len; pos += 4)
1808 regs[pos / 4] = readl(base + offset + pos);
1809
1810 print_hex_dump(KERN_ERR, prefix,
1811 len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,
1812 16, 4, regs, len, false);
1813
1814 return 0;
1815 }
1816
ufs_qcom_dump_mcq_hci_regs(struct ufs_hba * hba)1817 static void ufs_qcom_dump_mcq_hci_regs(struct ufs_hba *hba)
1818 {
1819 struct ufshcd_mcq_opr_info_t *opr = &hba->mcq_opr[0];
1820 void __iomem *mcq_vs_base = hba->mcq_base + UFS_MEM_VS_BASE;
1821
1822 struct dump_info {
1823 void __iomem *base;
1824 size_t offset;
1825 size_t len;
1826 const char *prefix;
1827 };
1828
1829 struct dump_info mcq_dumps[] = {
1830 {hba->mcq_base, 0x0, 256 * 4, "MCQ HCI-0 "},
1831 {hba->mcq_base, 0x400, 256 * 4, "MCQ HCI-1 "},
1832 {mcq_vs_base, 0x0, 5 * 4, "MCQ VS-0 "},
1833 {opr->base, 0x0, 256 * 4, "MCQ SQD-0 "},
1834 {opr->base, 0x400, 256 * 4, "MCQ SQD-1 "},
1835 {opr->base, 0x800, 256 * 4, "MCQ SQD-2 "},
1836 {opr->base, 0xc00, 256 * 4, "MCQ SQD-3 "},
1837 {opr->base, 0x1000, 256 * 4, "MCQ SQD-4 "},
1838 {opr->base, 0x1400, 256 * 4, "MCQ SQD-5 "},
1839 {opr->base, 0x1800, 256 * 4, "MCQ SQD-6 "},
1840 {opr->base, 0x1c00, 256 * 4, "MCQ SQD-7 "},
1841
1842 };
1843
1844 for (int i = 0; i < ARRAY_SIZE(mcq_dumps); i++) {
1845 ufs_qcom_dump_regs(hba, mcq_dumps[i].offset, mcq_dumps[i].len,
1846 mcq_dumps[i].prefix, mcq_dumps[i].base);
1847 cond_resched();
1848 }
1849 }
1850
ufs_qcom_dump_dbg_regs(struct ufs_hba * hba)1851 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1852 {
1853 u32 reg;
1854 struct ufs_qcom_host *host;
1855
1856 host = ufshcd_get_variant(hba);
1857
1858 dev_err(hba->dev, "HW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_ENTER_CNT));
1859 dev_err(hba->dev, "HW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_EXIT_CNT));
1860
1861 dev_err(hba->dev, "SW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_ENTER_CNT));
1862 dev_err(hba->dev, "SW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_EXIT_CNT));
1863
1864 dev_err(hba->dev, "SW_AFTER_HW_H8_ENTER_CNT=%d\n",
1865 ufshcd_readl(hba, REG_UFS_SW_AFTER_HW_H8_ENTER_CNT));
1866
1867 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1868 "HCI Vendor Specific Registers ");
1869
1870 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1871 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC ");
1872
1873 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1874 reg |= UTP_DBG_RAMS_EN;
1875 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1876
1877 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1878 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM ");
1879
1880 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1881 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM ");
1882
1883 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1884 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM ");
1885
1886 /* clear bit 17 - UTP_DBG_RAMS_EN */
1887 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1888
1889 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1890 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM ");
1891
1892 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1893 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM ");
1894
1895 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1896 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC ");
1897
1898 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1899 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC ");
1900
1901 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1902 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC ");
1903
1904 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1905 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT ");
1906
1907 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1908 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT ");
1909
1910 if (hba->mcq_enabled) {
1911 reg = ufs_qcom_get_debug_reg_offset(host, UFS_RD_REG_MCQ);
1912 ufshcd_dump_regs(hba, reg, 64 * 4, "HCI MCQ Debug Registers ");
1913 }
1914
1915 /* ensure below dumps occur only in task context due to blocking calls. */
1916 if (in_task()) {
1917 /* Dump MCQ Host Vendor Specific Registers */
1918 if (hba->mcq_enabled)
1919 ufs_qcom_dump_mcq_hci_regs(hba);
1920
1921 /* voluntarily yield the CPU as we are dumping too much data */
1922 ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS ");
1923 cond_resched();
1924 ufs_qcom_dump_testbus(hba);
1925 }
1926 }
1927
1928 /**
1929 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1930 * @hba: per-adapter instance
1931 *
1932 * Toggles the (optional) reset line to reset the attached device.
1933 */
ufs_qcom_device_reset(struct ufs_hba * hba)1934 static int ufs_qcom_device_reset(struct ufs_hba *hba)
1935 {
1936 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1937
1938 /* reset gpio is optional */
1939 if (!host->device_reset)
1940 return -EOPNOTSUPP;
1941
1942 /*
1943 * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1944 * be on the safe side.
1945 */
1946 ufs_qcom_device_reset_ctrl(hba, true);
1947 usleep_range(10, 15);
1948
1949 ufs_qcom_device_reset_ctrl(hba, false);
1950 usleep_range(10, 15);
1951
1952 return 0;
1953 }
1954
ufs_qcom_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * p,struct devfreq_simple_ondemand_data * d)1955 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1956 struct devfreq_dev_profile *p,
1957 struct devfreq_simple_ondemand_data *d)
1958 {
1959 p->polling_ms = 60;
1960 p->timer = DEVFREQ_TIMER_DELAYED;
1961 d->upthreshold = 70;
1962 d->downdifferential = 5;
1963
1964 hba->clk_scaling.suspend_on_no_request = true;
1965 }
1966
ufs_qcom_mcq_config_resource(struct ufs_hba * hba)1967 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba)
1968 {
1969 struct platform_device *pdev = to_platform_device(hba->dev);
1970 struct resource *res;
1971
1972 /* Map the MCQ configuration region */
1973 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mcq");
1974 if (!res) {
1975 dev_err(hba->dev, "MCQ resource not found in device tree\n");
1976 return -ENODEV;
1977 }
1978
1979 hba->mcq_base = devm_ioremap_resource(hba->dev, res);
1980 if (IS_ERR(hba->mcq_base)) {
1981 dev_err(hba->dev, "Failed to map MCQ region: %ld\n",
1982 PTR_ERR(hba->mcq_base));
1983 return PTR_ERR(hba->mcq_base);
1984 }
1985
1986 return 0;
1987 }
1988
ufs_qcom_op_runtime_config(struct ufs_hba * hba)1989 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba)
1990 {
1991 struct ufshcd_mcq_opr_info_t *opr;
1992 int i;
1993 u32 doorbell_offsets[OPR_MAX];
1994
1995 /*
1996 * Configure doorbell address offsets in MCQ configuration registers.
1997 * These values are offsets relative to mmio_base (UFS_HCI_BASE).
1998 *
1999 * Memory Layout:
2000 * - mmio_base = UFS_HCI_BASE
2001 * - mcq_base = MCQ_CONFIG_BASE = mmio_base + (UFS_QCOM_MCQCAP_QCFGPTR * 0x200)
2002 * - Doorbell registers are at: mmio_base + (UFS_QCOM_MCQCAP_QCFGPTR * 0x200) +
2003 * - UFS_QCOM_MCQ_SQD_OFFSET
2004 * - Which is also: mcq_base + UFS_QCOM_MCQ_SQD_OFFSET
2005 */
2006
2007 doorbell_offsets[OPR_SQD] = UFS_QCOM_SQD_ADDR_OFFSET;
2008 doorbell_offsets[OPR_SQIS] = UFS_QCOM_SQIS_ADDR_OFFSET;
2009 doorbell_offsets[OPR_CQD] = UFS_QCOM_CQD_ADDR_OFFSET;
2010 doorbell_offsets[OPR_CQIS] = UFS_QCOM_CQIS_ADDR_OFFSET;
2011
2012 /*
2013 * Configure MCQ operation registers.
2014 *
2015 * The doorbell registers are physically located within the MCQ region:
2016 * - doorbell_physical_addr = mmio_base + doorbell_offset
2017 * - doorbell_physical_addr = mcq_base + (doorbell_offset - MCQ_CONFIG_OFFSET)
2018 */
2019 for (i = 0; i < OPR_MAX; i++) {
2020 opr = &hba->mcq_opr[i];
2021 opr->offset = doorbell_offsets[i]; /* Offset relative to mmio_base */
2022 opr->stride = UFS_QCOM_MCQ_STRIDE; /* 256 bytes between queues */
2023
2024 /*
2025 * Calculate the actual doorbell base address within MCQ region:
2026 * base = mcq_base + (doorbell_offset - MCQ_CONFIG_OFFSET)
2027 */
2028 opr->base = hba->mcq_base + (opr->offset - UFS_QCOM_MCQ_CONFIG_OFFSET);
2029 }
2030
2031 return 0;
2032 }
2033
ufs_qcom_get_hba_mac(struct ufs_hba * hba)2034 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba)
2035 {
2036 /* Qualcomm HC supports up to 64 */
2037 return MAX_SUPP_MAC;
2038 }
2039
ufs_qcom_get_outstanding_cqs(struct ufs_hba * hba,unsigned long * ocqs)2040 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba,
2041 unsigned long *ocqs)
2042 {
2043 /* Read from MCQ vendor-specific register in MCQ region */
2044 *ocqs = readl(hba->mcq_base + UFS_MEM_CQIS_VS);
2045
2046 return 0;
2047 }
2048
ufs_qcom_write_msi_msg(struct msi_desc * desc,struct msi_msg * msg)2049 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
2050 {
2051 struct device *dev = msi_desc_to_dev(desc);
2052 struct ufs_hba *hba = dev_get_drvdata(dev);
2053
2054 ufshcd_mcq_config_esi(hba, msg);
2055 }
2056
2057 struct ufs_qcom_irq {
2058 unsigned int irq;
2059 unsigned int idx;
2060 struct ufs_hba *hba;
2061 };
2062
ufs_qcom_mcq_esi_handler(int irq,void * data)2063 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data)
2064 {
2065 struct ufs_qcom_irq *qi = data;
2066 struct ufs_hba *hba = qi->hba;
2067 struct ufs_hw_queue *hwq = &hba->uhq[qi->idx];
2068
2069 ufshcd_mcq_write_cqis(hba, 0x1, qi->idx);
2070 ufshcd_mcq_poll_cqe_lock(hba, hwq);
2071
2072 return IRQ_HANDLED;
2073 }
2074
ufs_qcom_config_esi(struct ufs_hba * hba)2075 static int ufs_qcom_config_esi(struct ufs_hba *hba)
2076 {
2077 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
2078 int nr_irqs, ret;
2079
2080 if (host->esi_enabled)
2081 return 0;
2082
2083 /*
2084 * 1. We only handle CQs as of now.
2085 * 2. Poll queues do not need ESI.
2086 */
2087 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL];
2088
2089 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs,
2090 ufs_qcom_write_msi_msg);
2091 if (ret) {
2092 dev_warn(hba->dev, "Platform MSI not supported or failed, continuing without ESI\n");
2093 return ret; /* Continue without ESI */
2094 }
2095
2096 struct ufs_qcom_irq *qi = devm_kcalloc(hba->dev, nr_irqs, sizeof(*qi), GFP_KERNEL);
2097
2098 if (!qi) {
2099 platform_device_msi_free_irqs_all(hba->dev);
2100 return -ENOMEM;
2101 }
2102
2103 for (int idx = 0; idx < nr_irqs; idx++) {
2104 qi[idx].irq = msi_get_virq(hba->dev, idx);
2105 qi[idx].idx = idx;
2106 qi[idx].hba = hba;
2107
2108 ret = devm_request_irq(hba->dev, qi[idx].irq, ufs_qcom_mcq_esi_handler,
2109 IRQF_SHARED, "qcom-mcq-esi", qi + idx);
2110 if (ret) {
2111 dev_err(hba->dev, "%s: Failed to request IRQ for %d, err = %d\n",
2112 __func__, qi[idx].irq, ret);
2113 /* Free previously allocated IRQs */
2114 for (int j = 0; j < idx; j++)
2115 devm_free_irq(hba->dev, qi[j].irq, qi + j);
2116 platform_device_msi_free_irqs_all(hba->dev);
2117 devm_kfree(hba->dev, qi);
2118 return ret;
2119 }
2120 }
2121
2122 if (host->hw_ver.major >= 6) {
2123 ufshcd_rmwl(hba, ESI_VEC_MASK, FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1),
2124 REG_UFS_CFG3);
2125 }
2126 ufshcd_mcq_enable_esi(hba);
2127 host->esi_enabled = true;
2128 return 0;
2129 }
2130
ufs_qcom_opp_freq_to_clk_freq(struct ufs_hba * hba,unsigned long freq,char * name)2131 static unsigned long ufs_qcom_opp_freq_to_clk_freq(struct ufs_hba *hba,
2132 unsigned long freq, char *name)
2133 {
2134 struct ufs_clk_info *clki;
2135 struct dev_pm_opp *opp;
2136 unsigned long clk_freq;
2137 int idx = 0;
2138 bool found = false;
2139
2140 opp = dev_pm_opp_find_freq_exact_indexed(hba->dev, freq, 0, true);
2141 if (IS_ERR(opp)) {
2142 dev_err(hba->dev, "Failed to find OPP for exact frequency %lu\n", freq);
2143 return 0;
2144 }
2145
2146 list_for_each_entry(clki, &hba->clk_list_head, list) {
2147 if (!strcmp(clki->name, name)) {
2148 found = true;
2149 break;
2150 }
2151
2152 idx++;
2153 }
2154
2155 if (!found) {
2156 dev_err(hba->dev, "Failed to find clock '%s' in clk list\n", name);
2157 dev_pm_opp_put(opp);
2158 return 0;
2159 }
2160
2161 clk_freq = dev_pm_opp_get_freq_indexed(opp, idx);
2162
2163 dev_pm_opp_put(opp);
2164
2165 return clk_freq;
2166 }
2167
ufs_qcom_freq_to_gear_speed(struct ufs_hba * hba,unsigned long freq)2168 static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq)
2169 {
2170 u32 gear = UFS_HS_DONT_CHANGE;
2171 unsigned long unipro_freq;
2172
2173 if (!hba->use_pm_opp)
2174 return gear;
2175
2176 unipro_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk_unipro");
2177 switch (unipro_freq) {
2178 case 403000000:
2179 gear = UFS_HS_G5;
2180 break;
2181 case 300000000:
2182 gear = UFS_HS_G4;
2183 break;
2184 case 201500000:
2185 gear = UFS_HS_G3;
2186 break;
2187 case 150000000:
2188 case 100000000:
2189 gear = UFS_HS_G2;
2190 break;
2191 case 75000000:
2192 case 37500000:
2193 gear = UFS_HS_G1;
2194 break;
2195 default:
2196 dev_err(hba->dev, "%s: Unsupported clock freq : %lu\n", __func__, freq);
2197 return UFS_HS_DONT_CHANGE;
2198 }
2199
2200 return min_t(u32, gear, hba->max_pwr_info.info.gear_rx);
2201 }
2202
2203 /*
2204 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
2205 *
2206 * The variant operations configure the necessary controller and PHY
2207 * handshake during initialization.
2208 */
2209 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
2210 .name = "qcom",
2211 .init = ufs_qcom_init,
2212 .exit = ufs_qcom_exit,
2213 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
2214 .clk_scale_notify = ufs_qcom_clk_scale_notify,
2215 .setup_clocks = ufs_qcom_setup_clocks,
2216 .hce_enable_notify = ufs_qcom_hce_enable_notify,
2217 .link_startup_notify = ufs_qcom_link_startup_notify,
2218 .pwr_change_notify = ufs_qcom_pwr_change_notify,
2219 .apply_dev_quirks = ufs_qcom_apply_dev_quirks,
2220 .fixup_dev_quirks = ufs_qcom_fixup_dev_quirks,
2221 .suspend = ufs_qcom_suspend,
2222 .resume = ufs_qcom_resume,
2223 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
2224 .device_reset = ufs_qcom_device_reset,
2225 .config_scaling_param = ufs_qcom_config_scaling_param,
2226 .mcq_config_resource = ufs_qcom_mcq_config_resource,
2227 .get_hba_mac = ufs_qcom_get_hba_mac,
2228 .op_runtime_config = ufs_qcom_op_runtime_config,
2229 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs,
2230 .config_esi = ufs_qcom_config_esi,
2231 .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed,
2232 };
2233
2234 /**
2235 * ufs_qcom_probe - probe routine of the driver
2236 * @pdev: pointer to Platform device handle
2237 *
2238 * Return: zero for success and non-zero for failure.
2239 */
ufs_qcom_probe(struct platform_device * pdev)2240 static int ufs_qcom_probe(struct platform_device *pdev)
2241 {
2242 int err;
2243 struct device *dev = &pdev->dev;
2244
2245 /* Perform generic probe */
2246 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
2247 if (err)
2248 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n");
2249
2250 return 0;
2251 }
2252
2253 /**
2254 * ufs_qcom_remove - set driver_data of the device to NULL
2255 * @pdev: pointer to platform device handle
2256 *
2257 * Always returns 0
2258 */
ufs_qcom_remove(struct platform_device * pdev)2259 static void ufs_qcom_remove(struct platform_device *pdev)
2260 {
2261 struct ufs_hba *hba = platform_get_drvdata(pdev);
2262 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
2263
2264 ufshcd_pltfrm_remove(pdev);
2265 if (host->esi_enabled)
2266 platform_device_msi_free_irqs_all(hba->dev);
2267 }
2268
2269 static const struct ufs_qcom_drvdata ufs_qcom_sm8550_drvdata = {
2270 .quirks = UFSHCD_QUIRK_BROKEN_LSDBS_CAP,
2271 .no_phy_retention = true,
2272 };
2273
2274 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = {
2275 { .compatible = "qcom,ufshc" },
2276 { .compatible = "qcom,sm8550-ufshc", .data = &ufs_qcom_sm8550_drvdata },
2277 { .compatible = "qcom,sm8650-ufshc", .data = &ufs_qcom_sm8550_drvdata },
2278 {},
2279 };
2280 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
2281
2282 #ifdef CONFIG_ACPI
2283 static const struct acpi_device_id ufs_qcom_acpi_match[] = {
2284 { "QCOM24A5" },
2285 { },
2286 };
2287 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
2288 #endif
2289
2290 static const struct dev_pm_ops ufs_qcom_pm_ops = {
2291 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
2292 .prepare = ufshcd_suspend_prepare,
2293 .complete = ufshcd_resume_complete,
2294 #ifdef CONFIG_PM_SLEEP
2295 .suspend = ufshcd_system_suspend,
2296 .resume = ufshcd_system_resume,
2297 .freeze = ufshcd_system_freeze,
2298 .restore = ufshcd_system_restore,
2299 .thaw = ufshcd_system_thaw,
2300 #endif
2301 };
2302
2303 static struct platform_driver ufs_qcom_pltform = {
2304 .probe = ufs_qcom_probe,
2305 .remove = ufs_qcom_remove,
2306 .driver = {
2307 .name = "ufshcd-qcom",
2308 .pm = &ufs_qcom_pm_ops,
2309 .of_match_table = of_match_ptr(ufs_qcom_of_match),
2310 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
2311 },
2312 };
2313 module_platform_driver(ufs_qcom_pltform);
2314
2315 MODULE_DESCRIPTION("Qualcomm UFS host controller driver");
2316 MODULE_LICENSE("GPL v2");
2317