1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 Red Hat
4 *
5 * based in parts on udlfb.c:
6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it>
7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com>
8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
9 */
10
11 #include <linux/bitfield.h>
12
13 #include <drm/drm_atomic.h>
14 #include <drm/drm_atomic_helper.h>
15 #include <drm/drm_crtc_helper.h>
16 #include <drm/drm_damage_helper.h>
17 #include <drm/drm_drv.h>
18 #include <drm/drm_edid.h>
19 #include <drm/drm_fourcc.h>
20 #include <drm/drm_gem_atomic_helper.h>
21 #include <drm/drm_gem_framebuffer_helper.h>
22 #include <drm/drm_gem_shmem_helper.h>
23 #include <drm/drm_modeset_helper_vtables.h>
24 #include <drm/drm_probe_helper.h>
25 #include <drm/drm_vblank.h>
26
27 #include "udl_drv.h"
28 #include "udl_edid.h"
29 #include "udl_proto.h"
30
31 /*
32 * All DisplayLink bulk operations start with 0xaf (UDL_MSG_BULK), followed by
33 * a specific command code. All operations are written to a command buffer, which
34 * the driver sends to the device.
35 */
udl_set_register(char * buf,u8 reg,u8 val)36 static char *udl_set_register(char *buf, u8 reg, u8 val)
37 {
38 *buf++ = UDL_MSG_BULK;
39 *buf++ = UDL_CMD_WRITEREG;
40 *buf++ = reg;
41 *buf++ = val;
42
43 return buf;
44 }
45
udl_vidreg_lock(char * buf)46 static char *udl_vidreg_lock(char *buf)
47 {
48 return udl_set_register(buf, UDL_REG_VIDREG, UDL_VIDREG_LOCK);
49 }
50
udl_vidreg_unlock(char * buf)51 static char *udl_vidreg_unlock(char *buf)
52 {
53 return udl_set_register(buf, UDL_REG_VIDREG, UDL_VIDREG_UNLOCK);
54 }
55
udl_set_blank_mode(char * buf,u8 mode)56 static char *udl_set_blank_mode(char *buf, u8 mode)
57 {
58 return udl_set_register(buf, UDL_REG_BLANKMODE, mode);
59 }
60
udl_set_color_depth(char * buf,u8 selection)61 static char *udl_set_color_depth(char *buf, u8 selection)
62 {
63 return udl_set_register(buf, UDL_REG_COLORDEPTH, selection);
64 }
65
udl_set_base16bpp(char * buf,u32 base)66 static char *udl_set_base16bpp(char *buf, u32 base)
67 {
68 /* the base pointer is 24 bits wide, 0x20 is hi byte. */
69 u8 reg20 = FIELD_GET(UDL_BASE_ADDR2_MASK, base);
70 u8 reg21 = FIELD_GET(UDL_BASE_ADDR1_MASK, base);
71 u8 reg22 = FIELD_GET(UDL_BASE_ADDR0_MASK, base);
72
73 buf = udl_set_register(buf, UDL_REG_BASE16BPP_ADDR2, reg20);
74 buf = udl_set_register(buf, UDL_REG_BASE16BPP_ADDR1, reg21);
75 buf = udl_set_register(buf, UDL_REG_BASE16BPP_ADDR0, reg22);
76
77 return buf;
78 }
79
80 /*
81 * DisplayLink HW has separate 16bpp and 8bpp framebuffers.
82 * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer
83 */
udl_set_base8bpp(char * buf,u32 base)84 static char *udl_set_base8bpp(char *buf, u32 base)
85 {
86 /* the base pointer is 24 bits wide, 0x26 is hi byte. */
87 u8 reg26 = FIELD_GET(UDL_BASE_ADDR2_MASK, base);
88 u8 reg27 = FIELD_GET(UDL_BASE_ADDR1_MASK, base);
89 u8 reg28 = FIELD_GET(UDL_BASE_ADDR0_MASK, base);
90
91 buf = udl_set_register(buf, UDL_REG_BASE8BPP_ADDR2, reg26);
92 buf = udl_set_register(buf, UDL_REG_BASE8BPP_ADDR1, reg27);
93 buf = udl_set_register(buf, UDL_REG_BASE8BPP_ADDR0, reg28);
94
95 return buf;
96 }
97
udl_set_register_16(char * wrptr,u8 reg,u16 value)98 static char *udl_set_register_16(char *wrptr, u8 reg, u16 value)
99 {
100 wrptr = udl_set_register(wrptr, reg, value >> 8);
101 return udl_set_register(wrptr, reg+1, value);
102 }
103
104 /*
105 * This is kind of weird because the controller takes some
106 * register values in a different byte order than other registers.
107 */
udl_set_register_16be(char * wrptr,u8 reg,u16 value)108 static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value)
109 {
110 wrptr = udl_set_register(wrptr, reg, value);
111 return udl_set_register(wrptr, reg+1, value >> 8);
112 }
113
114 /*
115 * LFSR is linear feedback shift register. The reason we have this is
116 * because the display controller needs to minimize the clock depth of
117 * various counters used in the display path. So this code reverses the
118 * provided value into the lfsr16 value by counting backwards to get
119 * the value that needs to be set in the hardware comparator to get the
120 * same actual count. This makes sense once you read above a couple of
121 * times and think about it from a hardware perspective.
122 */
udl_lfsr16(u16 actual_count)123 static u16 udl_lfsr16(u16 actual_count)
124 {
125 u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */
126
127 while (actual_count--) {
128 lv = ((lv << 1) |
129 (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1))
130 & 0xFFFF;
131 }
132
133 return (u16) lv;
134 }
135
136 /*
137 * This does LFSR conversion on the value that is to be written.
138 * See LFSR explanation above for more detail.
139 */
udl_set_register_lfsr16(char * wrptr,u8 reg,u16 value)140 static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value)
141 {
142 return udl_set_register_16(wrptr, reg, udl_lfsr16(value));
143 }
144
145 /*
146 * Takes a DRM display mode and converts it into the DisplayLink
147 * equivalent register commands.
148 */
udl_set_display_mode(char * buf,struct drm_display_mode * mode)149 static char *udl_set_display_mode(char *buf, struct drm_display_mode *mode)
150 {
151 u16 reg01 = mode->crtc_htotal - mode->crtc_hsync_start;
152 u16 reg03 = reg01 + mode->crtc_hdisplay;
153 u16 reg05 = mode->crtc_vtotal - mode->crtc_vsync_start;
154 u16 reg07 = reg05 + mode->crtc_vdisplay;
155 u16 reg09 = mode->crtc_htotal - 1;
156 u16 reg0b = 1; /* libdlo hardcodes hsync start to 1 */
157 u16 reg0d = mode->crtc_hsync_end - mode->crtc_hsync_start + 1;
158 u16 reg0f = mode->hdisplay;
159 u16 reg11 = mode->crtc_vtotal;
160 u16 reg13 = 0; /* libdlo hardcodes vsync start to 0 */
161 u16 reg15 = mode->crtc_vsync_end - mode->crtc_vsync_start;
162 u16 reg17 = mode->crtc_vdisplay;
163 u16 reg1b = mode->clock / 5;
164
165 buf = udl_set_register_lfsr16(buf, UDL_REG_XDISPLAYSTART, reg01);
166 buf = udl_set_register_lfsr16(buf, UDL_REG_XDISPLAYEND, reg03);
167 buf = udl_set_register_lfsr16(buf, UDL_REG_YDISPLAYSTART, reg05);
168 buf = udl_set_register_lfsr16(buf, UDL_REG_YDISPLAYEND, reg07);
169 buf = udl_set_register_lfsr16(buf, UDL_REG_XENDCOUNT, reg09);
170 buf = udl_set_register_lfsr16(buf, UDL_REG_HSYNCSTART, reg0b);
171 buf = udl_set_register_lfsr16(buf, UDL_REG_HSYNCEND, reg0d);
172 buf = udl_set_register_16(buf, UDL_REG_HPIXELS, reg0f);
173 buf = udl_set_register_lfsr16(buf, UDL_REG_YENDCOUNT, reg11);
174 buf = udl_set_register_lfsr16(buf, UDL_REG_VSYNCSTART, reg13);
175 buf = udl_set_register_lfsr16(buf, UDL_REG_VSYNCEND, reg15);
176 buf = udl_set_register_16(buf, UDL_REG_VPIXELS, reg17);
177 buf = udl_set_register_16be(buf, UDL_REG_PIXELCLOCK5KHZ, reg1b);
178
179 return buf;
180 }
181
udl_dummy_render(char * wrptr)182 static char *udl_dummy_render(char *wrptr)
183 {
184 *wrptr++ = UDL_MSG_BULK;
185 *wrptr++ = UDL_CMD_WRITECOPY16;
186 *wrptr++ = 0x00; /* from addr */
187 *wrptr++ = 0x00;
188 *wrptr++ = 0x00;
189 *wrptr++ = 0x01; /* one pixel */
190 *wrptr++ = 0x00; /* to address */
191 *wrptr++ = 0x00;
192 *wrptr++ = 0x00;
193 return wrptr;
194 }
195
udl_log_cpp(unsigned int cpp)196 static long udl_log_cpp(unsigned int cpp)
197 {
198 if (WARN_ON(!is_power_of_2(cpp)))
199 return -EINVAL;
200 return __ffs(cpp);
201 }
202
udl_handle_damage(struct drm_framebuffer * fb,const struct iosys_map * map,const struct drm_rect * clip)203 static int udl_handle_damage(struct drm_framebuffer *fb,
204 const struct iosys_map *map,
205 const struct drm_rect *clip)
206 {
207 struct drm_device *dev = fb->dev;
208 void *vaddr = map->vaddr; /* TODO: Use mapping abstraction properly */
209 int i, ret;
210 char *cmd;
211 struct urb *urb;
212 int log_bpp;
213
214 ret = udl_log_cpp(fb->format->cpp[0]);
215 if (ret < 0)
216 return ret;
217 log_bpp = ret;
218
219 urb = udl_get_urb(dev);
220 if (!urb)
221 return -ENOMEM;
222 cmd = urb->transfer_buffer;
223
224 for (i = clip->y1; i < clip->y2; i++) {
225 const int line_offset = fb->pitches[0] * i;
226 const int byte_offset = line_offset + (clip->x1 << log_bpp);
227 const int dev_byte_offset = (fb->width * i + clip->x1) << log_bpp;
228 const int byte_width = drm_rect_width(clip) << log_bpp;
229 ret = udl_render_hline(dev, log_bpp, &urb, (char *)vaddr,
230 &cmd, byte_offset, dev_byte_offset,
231 byte_width);
232 if (ret)
233 return ret;
234 }
235
236 if (cmd > (char *)urb->transfer_buffer) {
237 /* Send partial buffer remaining before exiting */
238 int len;
239 if (cmd < (char *)urb->transfer_buffer + urb->transfer_buffer_length)
240 *cmd++ = UDL_MSG_BULK;
241 len = cmd - (char *)urb->transfer_buffer;
242 ret = udl_submit_urb(dev, urb, len);
243 } else {
244 udl_urb_completion(urb);
245 }
246
247 return 0;
248 }
249
250 /*
251 * Primary plane
252 */
253
254 static const uint32_t udl_primary_plane_formats[] = {
255 DRM_FORMAT_RGB565,
256 DRM_FORMAT_XRGB8888,
257 };
258
259 static const uint64_t udl_primary_plane_fmtmods[] = {
260 DRM_FORMAT_MOD_LINEAR,
261 DRM_FORMAT_MOD_INVALID
262 };
263
udl_primary_plane_helper_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)264 static int udl_primary_plane_helper_atomic_check(struct drm_plane *plane,
265 struct drm_atomic_state *state)
266 {
267 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane);
268 struct drm_crtc *new_crtc = new_plane_state->crtc;
269 struct drm_crtc_state *new_crtc_state = NULL;
270
271 if (new_crtc)
272 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
273
274 return drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state,
275 DRM_PLANE_NO_SCALING,
276 DRM_PLANE_NO_SCALING,
277 false, false);
278 }
279
udl_primary_plane_helper_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)280 static void udl_primary_plane_helper_atomic_update(struct drm_plane *plane,
281 struct drm_atomic_state *state)
282 {
283 struct drm_device *dev = plane->dev;
284 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
285 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
286 struct drm_framebuffer *fb = plane_state->fb;
287 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);
288 struct drm_atomic_helper_damage_iter iter;
289 struct drm_rect damage;
290 int ret, idx;
291
292 if (!fb)
293 return; /* no framebuffer; plane is disabled */
294
295 ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
296 if (ret)
297 return;
298
299 if (!drm_dev_enter(dev, &idx))
300 goto out_drm_gem_fb_end_cpu_access;
301
302 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);
303 drm_atomic_for_each_plane_damage(&iter, &damage) {
304 udl_handle_damage(fb, &shadow_plane_state->data[0], &damage);
305 }
306
307 drm_dev_exit(idx);
308
309 out_drm_gem_fb_end_cpu_access:
310 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
311 }
312
313 static const struct drm_plane_helper_funcs udl_primary_plane_helper_funcs = {
314 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
315 .atomic_check = udl_primary_plane_helper_atomic_check,
316 .atomic_update = udl_primary_plane_helper_atomic_update,
317 };
318
319 static const struct drm_plane_funcs udl_primary_plane_funcs = {
320 .update_plane = drm_atomic_helper_update_plane,
321 .disable_plane = drm_atomic_helper_disable_plane,
322 .destroy = drm_plane_cleanup,
323 DRM_GEM_SHADOW_PLANE_FUNCS,
324 };
325
326 /*
327 * CRTC
328 */
329
udl_crtc_helper_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)330 static void udl_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state)
331 {
332 struct drm_device *dev = crtc->dev;
333 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
334 struct drm_display_mode *mode = &crtc_state->mode;
335 struct urb *urb;
336 char *buf;
337 int idx;
338
339 if (!drm_dev_enter(dev, &idx))
340 return;
341
342 urb = udl_get_urb(dev);
343 if (!urb)
344 goto out;
345
346 buf = (char *)urb->transfer_buffer;
347 buf = udl_vidreg_lock(buf);
348 buf = udl_set_color_depth(buf, UDL_COLORDEPTH_16BPP);
349 /* set base for 16bpp segment to 0 */
350 buf = udl_set_base16bpp(buf, 0);
351 /* set base for 8bpp segment to end of fb */
352 buf = udl_set_base8bpp(buf, 2 * mode->vdisplay * mode->hdisplay);
353 buf = udl_set_display_mode(buf, mode);
354 buf = udl_set_blank_mode(buf, UDL_BLANKMODE_ON);
355 buf = udl_vidreg_unlock(buf);
356 buf = udl_dummy_render(buf);
357
358 udl_submit_urb(dev, urb, buf - (char *)urb->transfer_buffer);
359
360 out:
361 drm_dev_exit(idx);
362 }
363
udl_crtc_helper_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)364 static void udl_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state)
365 {
366 struct drm_device *dev = crtc->dev;
367 struct urb *urb;
368 char *buf;
369 int idx;
370
371 if (!drm_dev_enter(dev, &idx))
372 return;
373
374 urb = udl_get_urb(dev);
375 if (!urb)
376 goto out;
377
378 buf = (char *)urb->transfer_buffer;
379 buf = udl_vidreg_lock(buf);
380 buf = udl_set_blank_mode(buf, UDL_BLANKMODE_POWERDOWN);
381 buf = udl_vidreg_unlock(buf);
382 buf = udl_dummy_render(buf);
383
384 udl_submit_urb(dev, urb, buf - (char *)urb->transfer_buffer);
385
386 out:
387 drm_dev_exit(idx);
388 }
389
390 static const struct drm_crtc_helper_funcs udl_crtc_helper_funcs = {
391 .atomic_check = drm_crtc_helper_atomic_check,
392 .atomic_enable = udl_crtc_helper_atomic_enable,
393 .atomic_disable = udl_crtc_helper_atomic_disable,
394 };
395
396 static const struct drm_crtc_funcs udl_crtc_funcs = {
397 .reset = drm_atomic_helper_crtc_reset,
398 .destroy = drm_crtc_cleanup,
399 .set_config = drm_atomic_helper_set_config,
400 .page_flip = drm_atomic_helper_page_flip,
401 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
402 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
403 };
404
405 /*
406 * Encoder
407 */
408
409 static const struct drm_encoder_funcs udl_encoder_funcs = {
410 .destroy = drm_encoder_cleanup,
411 };
412
413 /*
414 * Connector
415 */
416
udl_connector_helper_get_modes(struct drm_connector * connector)417 static int udl_connector_helper_get_modes(struct drm_connector *connector)
418 {
419 const struct drm_edid *drm_edid;
420 int count;
421
422 drm_edid = udl_edid_read(connector);
423 drm_edid_connector_update(connector, drm_edid);
424 count = drm_edid_connector_add_modes(connector);
425 drm_edid_free(drm_edid);
426
427 return count;
428 }
429
udl_connector_helper_detect_ctx(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)430 static int udl_connector_helper_detect_ctx(struct drm_connector *connector,
431 struct drm_modeset_acquire_ctx *ctx,
432 bool force)
433 {
434 struct udl_device *udl = to_udl(connector->dev);
435
436 if (udl_probe_edid(udl))
437 return connector_status_connected;
438
439 return connector_status_disconnected;
440 }
441
442 static const struct drm_connector_helper_funcs udl_connector_helper_funcs = {
443 .get_modes = udl_connector_helper_get_modes,
444 .detect_ctx = udl_connector_helper_detect_ctx,
445 };
446
447 static const struct drm_connector_funcs udl_connector_funcs = {
448 .reset = drm_atomic_helper_connector_reset,
449 .fill_modes = drm_helper_probe_single_connector_modes,
450 .destroy = drm_connector_cleanup,
451 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
452 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
453 };
454
455 /*
456 * Modesetting
457 */
458
udl_mode_config_mode_valid(struct drm_device * dev,const struct drm_display_mode * mode)459 static enum drm_mode_status udl_mode_config_mode_valid(struct drm_device *dev,
460 const struct drm_display_mode *mode)
461 {
462 struct udl_device *udl = to_udl(dev);
463
464 if (udl->sku_pixel_limit) {
465 if (mode->vdisplay * mode->hdisplay > udl->sku_pixel_limit)
466 return MODE_MEM;
467 }
468
469 return MODE_OK;
470 }
471
472 static const struct drm_mode_config_funcs udl_mode_config_funcs = {
473 .fb_create = drm_gem_fb_create_with_dirty,
474 .mode_valid = udl_mode_config_mode_valid,
475 .atomic_check = drm_atomic_helper_check,
476 .atomic_commit = drm_atomic_helper_commit,
477 };
478
udl_modeset_init(struct drm_device * dev)479 int udl_modeset_init(struct drm_device *dev)
480 {
481 struct udl_device *udl = to_udl(dev);
482 struct drm_plane *primary_plane;
483 struct drm_crtc *crtc;
484 struct drm_encoder *encoder;
485 struct drm_connector *connector;
486 int ret;
487
488 ret = drmm_mode_config_init(dev);
489 if (ret)
490 return ret;
491
492 dev->mode_config.min_width = 640;
493 dev->mode_config.min_height = 480;
494 dev->mode_config.max_width = 2048;
495 dev->mode_config.max_height = 2048;
496 dev->mode_config.preferred_depth = 16;
497 dev->mode_config.funcs = &udl_mode_config_funcs;
498
499 primary_plane = &udl->primary_plane;
500 ret = drm_universal_plane_init(dev, primary_plane, 0,
501 &udl_primary_plane_funcs,
502 udl_primary_plane_formats,
503 ARRAY_SIZE(udl_primary_plane_formats),
504 udl_primary_plane_fmtmods,
505 DRM_PLANE_TYPE_PRIMARY, NULL);
506 if (ret)
507 return ret;
508 drm_plane_helper_add(primary_plane, &udl_primary_plane_helper_funcs);
509 drm_plane_enable_fb_damage_clips(primary_plane);
510
511 crtc = &udl->crtc;
512 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL,
513 &udl_crtc_funcs, NULL);
514 if (ret)
515 return ret;
516 drm_crtc_helper_add(crtc, &udl_crtc_helper_funcs);
517
518 encoder = &udl->encoder;
519 ret = drm_encoder_init(dev, encoder, &udl_encoder_funcs, DRM_MODE_ENCODER_DAC, NULL);
520 if (ret)
521 return ret;
522 encoder->possible_crtcs = drm_crtc_mask(crtc);
523
524 connector = &udl->connector;
525 ret = drm_connector_init(dev, connector, &udl_connector_funcs, DRM_MODE_CONNECTOR_VGA);
526 if (ret)
527 return ret;
528 drm_connector_helper_add(connector, &udl_connector_helper_funcs);
529
530 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
531 DRM_CONNECTOR_POLL_DISCONNECT;
532
533 ret = drm_connector_attach_encoder(connector, encoder);
534 if (ret)
535 return ret;
536
537 drm_mode_config_reset(dev);
538
539 return 0;
540 }
541