xref: /linux/include/ufs/ufshcd.h (revision 674b0ddb7586a192612442c3aed9cf523faeed7a)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Universal Flash Storage Host controller driver
4  * Copyright (C) 2011-2013 Samsung India Software Operations
5  * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6  *
7  * Authors:
8  *	Santosh Yaraganavi <santosh.sy@samsung.com>
9  *	Vinayak Holikatti <h.vinayak@samsung.com>
10  */
11 
12 #ifndef _UFSHCD_H
13 #define _UFSHCD_H
14 
15 #include <linux/bitfield.h>
16 #include <linux/blk-crypto-profile.h>
17 #include <linux/blk-mq.h>
18 #include <linux/devfreq.h>
19 #include <linux/fault-inject.h>
20 #include <linux/debugfs.h>
21 #include <linux/msi.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/dma-direction.h>
24 #include <scsi/scsi_device.h>
25 #include <scsi/scsi_host.h>
26 #include <ufs/unipro.h>
27 #include <ufs/ufs.h>
28 #include <ufs/ufs_quirks.h>
29 #include <ufs/ufshci.h>
30 
31 #define UFSHCD "ufshcd"
32 
33 struct scsi_device;
34 struct ufs_hba;
35 
36 enum dev_cmd_type {
37 	DEV_CMD_TYPE_NOP		= 0x0,
38 	DEV_CMD_TYPE_QUERY		= 0x1,
39 	DEV_CMD_TYPE_RPMB		= 0x2,
40 };
41 
42 enum ufs_event_type {
43 	/* uic specific errors */
44 	UFS_EVT_PA_ERR = 0,
45 	UFS_EVT_DL_ERR,
46 	UFS_EVT_NL_ERR,
47 	UFS_EVT_TL_ERR,
48 	UFS_EVT_DME_ERR,
49 
50 	/* fatal errors */
51 	UFS_EVT_AUTO_HIBERN8_ERR,
52 	UFS_EVT_FATAL_ERR,
53 	UFS_EVT_LINK_STARTUP_FAIL,
54 	UFS_EVT_RESUME_ERR,
55 	UFS_EVT_SUSPEND_ERR,
56 	UFS_EVT_WL_SUSP_ERR,
57 	UFS_EVT_WL_RES_ERR,
58 
59 	/* abnormal events */
60 	UFS_EVT_DEV_RESET,
61 	UFS_EVT_HOST_RESET,
62 	UFS_EVT_ABORT,
63 
64 	UFS_EVT_CNT,
65 };
66 
67 /**
68  * struct uic_command - UIC command structure
69  * @command: UIC command
70  * @argument1: UIC command argument 1
71  * @argument2: UIC command argument 2
72  * @argument3: UIC command argument 3
73  * @cmd_active: Indicate if UIC command is outstanding
74  * @done: UIC command completion
75  */
76 struct uic_command {
77 	const u32 command;
78 	const u32 argument1;
79 	u32 argument2;
80 	u32 argument3;
81 	int cmd_active;
82 	struct completion done;
83 };
84 
85 /* Used to differentiate the power management options */
86 enum ufs_pm_op {
87 	UFS_RUNTIME_PM,
88 	UFS_SYSTEM_PM,
89 	UFS_SHUTDOWN_PM,
90 };
91 
92 /* Host <-> Device UniPro Link state */
93 enum uic_link_state {
94 	UIC_LINK_OFF_STATE	= 0, /* Link powered down or disabled */
95 	UIC_LINK_ACTIVE_STATE	= 1, /* Link is in Fast/Slow/Sleep state */
96 	UIC_LINK_HIBERN8_STATE	= 2, /* Link is in Hibernate state */
97 	UIC_LINK_BROKEN_STATE	= 3, /* Link is in broken state */
98 };
99 
100 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
101 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
102 				    UIC_LINK_ACTIVE_STATE)
103 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
104 				    UIC_LINK_HIBERN8_STATE)
105 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \
106 				   UIC_LINK_BROKEN_STATE)
107 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
108 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
109 				    UIC_LINK_ACTIVE_STATE)
110 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
111 				    UIC_LINK_HIBERN8_STATE)
112 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \
113 				    UIC_LINK_BROKEN_STATE)
114 
115 #define ufshcd_set_ufs_dev_active(h) \
116 	((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
117 #define ufshcd_set_ufs_dev_sleep(h) \
118 	((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
119 #define ufshcd_set_ufs_dev_poweroff(h) \
120 	((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
121 #define ufshcd_set_ufs_dev_deepsleep(h) \
122 	((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE)
123 #define ufshcd_is_ufs_dev_active(h) \
124 	((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
125 #define ufshcd_is_ufs_dev_sleep(h) \
126 	((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
127 #define ufshcd_is_ufs_dev_poweroff(h) \
128 	((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
129 #define ufshcd_is_ufs_dev_deepsleep(h) \
130 	((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE)
131 
132 /*
133  * UFS Power management levels.
134  * Each level is in increasing order of power savings, except DeepSleep
135  * which is lower than PowerDown with power on but not PowerDown with
136  * power off.
137  */
138 enum ufs_pm_level {
139 	UFS_PM_LVL_0,
140 	UFS_PM_LVL_1,
141 	UFS_PM_LVL_2,
142 	UFS_PM_LVL_3,
143 	UFS_PM_LVL_4,
144 	UFS_PM_LVL_5,
145 	UFS_PM_LVL_6,
146 	UFS_PM_LVL_MAX
147 };
148 
149 struct ufs_pm_lvl_states {
150 	enum ufs_dev_pwr_mode dev_state;
151 	enum uic_link_state link_state;
152 };
153 
154 /**
155  * struct ufshcd_lrb - local reference block
156  * @utr_descriptor_ptr: UTRD address of the command
157  * @ucd_req_ptr: UCD address of the command
158  * @ucd_rsp_ptr: Response UPIU address for this command
159  * @ucd_prdt_ptr: PRDT address of the command
160  * @utrd_dma_addr: UTRD dma address for debug
161  * @ucd_prdt_dma_addr: PRDT dma address for debug
162  * @ucd_rsp_dma_addr: UPIU response dma address for debug
163  * @ucd_req_dma_addr: UPIU request dma address for debug
164  * @cmd: pointer to SCSI command
165  * @scsi_status: SCSI status of the command
166  * @command_type: SCSI, UFS, Query.
167  * @task_tag: Task tag of the command
168  * @lun: LUN of the command
169  * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
170  * @req_abort_skip: skip request abort task flag
171  * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC)
172  * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock)
173  * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC)
174  * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock)
175  * @crypto_key_slot: the key slot to use for inline crypto (-1 if none)
176  * @data_unit_num: the data unit number for the first block for inline crypto
177  */
178 struct ufshcd_lrb {
179 	struct utp_transfer_req_desc *utr_descriptor_ptr;
180 	struct utp_upiu_req *ucd_req_ptr;
181 	struct utp_upiu_rsp *ucd_rsp_ptr;
182 	struct ufshcd_sg_entry *ucd_prdt_ptr;
183 
184 	dma_addr_t utrd_dma_addr;
185 	dma_addr_t ucd_req_dma_addr;
186 	dma_addr_t ucd_rsp_dma_addr;
187 	dma_addr_t ucd_prdt_dma_addr;
188 
189 	struct scsi_cmnd *cmd;
190 	int scsi_status;
191 
192 	int command_type;
193 	int task_tag;
194 	u8 lun; /* UPIU LUN id field is only 8-bit wide */
195 	bool intr_cmd;
196 	bool req_abort_skip;
197 	ktime_t issue_time_stamp;
198 	u64 issue_time_stamp_local_clock;
199 	ktime_t compl_time_stamp;
200 	u64 compl_time_stamp_local_clock;
201 #ifdef CONFIG_SCSI_UFS_CRYPTO
202 	int crypto_key_slot;
203 	u64 data_unit_num;
204 #endif
205 };
206 
207 /**
208  * struct ufs_query_req - parameters for building a query request
209  * @query_func: UPIU header query function
210  * @upiu_req: the query request data
211  */
212 struct ufs_query_req {
213 	u8 query_func;
214 	struct utp_upiu_query upiu_req;
215 };
216 
217 /**
218  * struct ufs_query_resp - UPIU QUERY
219  * @response: device response code
220  * @upiu_res: query response data
221  */
222 struct ufs_query_res {
223 	struct utp_upiu_query upiu_res;
224 };
225 
226 /**
227  * struct ufs_query - holds relevant data structures for query request
228  * @request: request upiu and function
229  * @descriptor: buffer for sending/receiving descriptor
230  * @response: response upiu and response
231  */
232 struct ufs_query {
233 	struct ufs_query_req request;
234 	u8 *descriptor;
235 	struct ufs_query_res response;
236 };
237 
238 /**
239  * struct ufs_dev_cmd - all assosiated fields with device management commands
240  * @type: device management command type - Query, NOP OUT
241  * @lock: lock to allow one command at a time
242  * @complete: internal commands completion
243  * @query: Device management query information
244  */
245 struct ufs_dev_cmd {
246 	enum dev_cmd_type type;
247 	struct mutex lock;
248 	struct completion complete;
249 	struct ufs_query query;
250 };
251 
252 /**
253  * struct ufs_clk_info - UFS clock related info
254  * @list: list headed by hba->clk_list_head
255  * @clk: clock node
256  * @name: clock name
257  * @max_freq: maximum frequency supported by the clock
258  * @min_freq: min frequency that can be used for clock scaling
259  * @curr_freq: indicates the current frequency that it is set to
260  * @keep_link_active: indicates that the clk should not be disabled if
261  *		      link is active
262  * @enabled: variable to check against multiple enable/disable
263  */
264 struct ufs_clk_info {
265 	struct list_head list;
266 	struct clk *clk;
267 	const char *name;
268 	u32 max_freq;
269 	u32 min_freq;
270 	u32 curr_freq;
271 	bool keep_link_active;
272 	bool enabled;
273 };
274 
275 enum ufs_notify_change_status {
276 	PRE_CHANGE,
277 	POST_CHANGE,
278 };
279 
280 struct ufs_pa_layer_attr {
281 	u32 gear_rx;
282 	u32 gear_tx;
283 	u32 lane_rx;
284 	u32 lane_tx;
285 	u32 pwr_rx;
286 	u32 pwr_tx;
287 	u32 hs_rate;
288 };
289 
290 struct ufs_pwr_mode_info {
291 	bool is_valid;
292 	struct ufs_pa_layer_attr info;
293 };
294 
295 /**
296  * struct ufs_hba_variant_ops - variant specific callbacks
297  * @name: variant name
298  * @max_num_rtt: maximum RTT supported by the host
299  * @init: called when the driver is initialized
300  * @exit: called to cleanup everything done in init
301  * @set_dma_mask: For setting another DMA mask than indicated by the 64AS
302  *	capability bit.
303  * @get_ufs_hci_version: called to get UFS HCI version
304  * @clk_scale_notify: notifies that clks are scaled up/down
305  * @setup_clocks: called before touching any of the controller registers
306  * @hce_enable_notify: called before and after HCE enable bit is set to allow
307  *                     variant specific Uni-Pro initialization.
308  * @link_startup_notify: called before and after Link startup is carried out
309  *                       to allow variant specific Uni-Pro initialization.
310  * @pwr_change_notify: called before and after a power mode change
311  *			is carried out to allow vendor spesific capabilities
312  *			to be set. PRE_CHANGE can modify final_params based
313  *			on desired_pwr_mode, but POST_CHANGE must not alter
314  *			the final_params parameter
315  * @setup_xfer_req: called before any transfer request is issued
316  *                  to set some things
317  * @setup_task_mgmt: called before any task management request is issued
318  *                  to set some things
319  * @hibern8_notify: called around hibern8 enter/exit
320  * @apply_dev_quirks: called to apply device specific quirks
321  * @fixup_dev_quirks: called to modify device specific quirks
322  * @suspend: called during host controller PM callback
323  * @resume: called during host controller PM callback
324  * @dbg_register_dump: used to dump controller debug information
325  * @phy_initialization: used to initialize phys
326  * @device_reset: called to issue a reset pulse on the UFS device
327  * @config_scaling_param: called to configure clock scaling parameters
328  * @fill_crypto_prdt: initialize crypto-related fields in the PRDT
329  * @event_notify: called to notify important events
330  * @mcq_config_resource: called to configure MCQ platform resources
331  * @get_hba_mac: reports maximum number of outstanding commands supported by
332  *	the controller. Should be implemented for UFSHCI 4.0 or later
333  *	controllers that are not compliant with the UFSHCI 4.0 specification.
334  * @op_runtime_config: called to config Operation and runtime regs Pointers
335  * @get_outstanding_cqs: called to get outstanding completion queues
336  * @config_esi: called to config Event Specific Interrupt
337  * @config_scsi_dev: called to configure SCSI device parameters
338  * @freq_to_gear_speed: called to map clock frequency to the max supported gear speed
339  */
340 struct ufs_hba_variant_ops {
341 	const char *name;
342 	int	max_num_rtt;
343 	int	(*init)(struct ufs_hba *);
344 	void    (*exit)(struct ufs_hba *);
345 	u32	(*get_ufs_hci_version)(struct ufs_hba *);
346 	int	(*set_dma_mask)(struct ufs_hba *);
347 	int	(*clk_scale_notify)(struct ufs_hba *, bool, unsigned long,
348 				enum ufs_notify_change_status);
349 	int	(*setup_clocks)(struct ufs_hba *, bool,
350 				enum ufs_notify_change_status);
351 	int	(*hce_enable_notify)(struct ufs_hba *,
352 				     enum ufs_notify_change_status);
353 	int	(*link_startup_notify)(struct ufs_hba *,
354 				       enum ufs_notify_change_status);
355 	int	(*pwr_change_notify)(struct ufs_hba *,
356 			enum ufs_notify_change_status status,
357 			const struct ufs_pa_layer_attr *desired_pwr_mode,
358 			struct ufs_pa_layer_attr *final_params);
359 	void	(*setup_xfer_req)(struct ufs_hba *hba, int tag,
360 				  bool is_scsi_cmd);
361 	void	(*setup_task_mgmt)(struct ufs_hba *, int, u8);
362 	void    (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme,
363 					enum ufs_notify_change_status);
364 	int	(*apply_dev_quirks)(struct ufs_hba *hba);
365 	void	(*fixup_dev_quirks)(struct ufs_hba *hba);
366 	int     (*suspend)(struct ufs_hba *, enum ufs_pm_op,
367 					enum ufs_notify_change_status);
368 	int     (*resume)(struct ufs_hba *, enum ufs_pm_op);
369 	void	(*dbg_register_dump)(struct ufs_hba *hba);
370 	int	(*phy_initialization)(struct ufs_hba *);
371 	int	(*device_reset)(struct ufs_hba *hba);
372 	void	(*config_scaling_param)(struct ufs_hba *hba,
373 				struct devfreq_dev_profile *profile,
374 				struct devfreq_simple_ondemand_data *data);
375 	int	(*fill_crypto_prdt)(struct ufs_hba *hba,
376 				    const struct bio_crypt_ctx *crypt_ctx,
377 				    void *prdt, unsigned int num_segments);
378 	void	(*event_notify)(struct ufs_hba *hba,
379 				enum ufs_event_type evt, void *data);
380 	int	(*mcq_config_resource)(struct ufs_hba *hba);
381 	int	(*get_hba_mac)(struct ufs_hba *hba);
382 	int	(*op_runtime_config)(struct ufs_hba *hba);
383 	int	(*get_outstanding_cqs)(struct ufs_hba *hba,
384 				       unsigned long *ocqs);
385 	int	(*config_esi)(struct ufs_hba *hba);
386 	void	(*config_scsi_dev)(struct scsi_device *sdev);
387 	u32	(*freq_to_gear_speed)(struct ufs_hba *hba, unsigned long freq);
388 };
389 
390 /* clock gating state  */
391 enum clk_gating_state {
392 	CLKS_OFF,
393 	CLKS_ON,
394 	REQ_CLKS_OFF,
395 	REQ_CLKS_ON,
396 };
397 
398 /**
399  * struct ufs_clk_gating - UFS clock gating related info
400  * @gate_work: worker to turn off clocks after some delay as specified in
401  * delay_ms
402  * @ungate_work: worker to turn on clocks that will be used in case of
403  * interrupt context
404  * @clk_gating_workq: workqueue for clock gating work.
405  * @lock: serialize access to some struct ufs_clk_gating members. An outer lock
406  * relative to the host lock
407  * @state: the current clocks state
408  * @delay_ms: gating delay in ms
409  * @is_suspended: clk gating is suspended when set to 1 which can be used
410  * during suspend/resume
411  * @delay_attr: sysfs attribute to control delay_attr
412  * @enable_attr: sysfs attribute to enable/disable clock gating
413  * @is_enabled: Indicates the current status of clock gating
414  * @is_initialized: Indicates whether clock gating is initialized or not
415  * @active_reqs: number of requests that are pending and should be waited for
416  * completion before gating clocks.
417  */
418 struct ufs_clk_gating {
419 	struct delayed_work gate_work;
420 	struct work_struct ungate_work;
421 	struct workqueue_struct *clk_gating_workq;
422 
423 	spinlock_t lock;
424 
425 	enum clk_gating_state state;
426 	unsigned long delay_ms;
427 	bool is_suspended;
428 	struct device_attribute delay_attr;
429 	struct device_attribute enable_attr;
430 	bool is_enabled;
431 	bool is_initialized;
432 	int active_reqs;
433 };
434 
435 /**
436  * struct ufs_clk_scaling - UFS clock scaling related data
437  * @workq: workqueue to schedule devfreq suspend/resume work
438  * @suspend_work: worker to suspend devfreq
439  * @resume_work: worker to resume devfreq
440  * @lock: serialize access to some struct ufs_clk_scaling members
441  * @active_reqs: number of requests that are pending. If this is zero when
442  * devfreq ->target() function is called then schedule "suspend_work" to
443  * suspend devfreq.
444  * @tot_busy_t: Total busy time in current polling window
445  * @window_start_t: Start time (in jiffies) of the current polling window
446  * @busy_start_t: Start time of current busy period
447  * @enable_attr: sysfs attribute to enable/disable clock scaling
448  * @saved_pwr_info: UFS power mode may also be changed during scaling and this
449  * one keeps track of previous power mode.
450  * @target_freq: frequency requested by devfreq framework
451  * @min_gear: lowest HS gear to scale down to
452  * @wb_gear: enable Write Booster when HS gear scales above or equal to it, else
453  *		disable Write Booster
454  * @is_enabled: tracks if scaling is currently enabled or not, controlled by
455  *		clkscale_enable sysfs node
456  * @is_allowed: tracks if scaling is currently allowed or not, used to block
457  *		clock scaling which is not invoked from devfreq governor
458  * @is_initialized: Indicates whether clock scaling is initialized or not
459  * @is_busy_started: tracks if busy period has started or not
460  * @is_suspended: tracks if devfreq is suspended or not
461  */
462 struct ufs_clk_scaling {
463 	struct workqueue_struct *workq;
464 	struct work_struct suspend_work;
465 	struct work_struct resume_work;
466 
467 	spinlock_t lock;
468 
469 	int active_reqs;
470 	unsigned long tot_busy_t;
471 	ktime_t window_start_t;
472 	ktime_t busy_start_t;
473 	struct device_attribute enable_attr;
474 	struct ufs_pa_layer_attr saved_pwr_info;
475 	unsigned long target_freq;
476 	u32 min_gear;
477 	u32 wb_gear;
478 	bool is_enabled;
479 	bool is_allowed;
480 	bool is_initialized;
481 	bool is_busy_started;
482 	bool is_suspended;
483 	bool suspend_on_no_request;
484 };
485 
486 #define UFS_EVENT_HIST_LENGTH 8
487 /**
488  * struct ufs_event_hist - keeps history of errors
489  * @pos: index to indicate cyclic buffer position
490  * @val: cyclic buffer for registers value
491  * @tstamp: cyclic buffer for time stamp
492  * @cnt: error counter
493  */
494 struct ufs_event_hist {
495 	int pos;
496 	u32 val[UFS_EVENT_HIST_LENGTH];
497 	u64 tstamp[UFS_EVENT_HIST_LENGTH];
498 	unsigned long long cnt;
499 };
500 
501 /**
502  * struct ufs_stats - keeps usage/err statistics
503  * @hibern8_exit_cnt: Counter to keep track of number of exits,
504  *		reset this after link-startup.
505  * @last_hibern8_exit_tstamp: Set time after the hibern8 exit.
506  *		Clear after the first successful command completion.
507  * @event: array with event history.
508  */
509 struct ufs_stats {
510 	u32 hibern8_exit_cnt;
511 	u64 last_hibern8_exit_tstamp;
512 	struct ufs_event_hist event[UFS_EVT_CNT];
513 };
514 
515 /**
516  * enum ufshcd_state - UFS host controller state
517  * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command
518  *	processing.
519  * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process
520  *	SCSI commands.
521  * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled.
522  *	SCSI commands may be submitted to the controller.
523  * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail
524  *	newly submitted SCSI commands with error code DID_BAD_TARGET.
525  * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery
526  *	failed. Fail all SCSI commands with error code DID_ERROR.
527  */
528 enum ufshcd_state {
529 	UFSHCD_STATE_RESET,
530 	UFSHCD_STATE_OPERATIONAL,
531 	UFSHCD_STATE_EH_SCHEDULED_NON_FATAL,
532 	UFSHCD_STATE_EH_SCHEDULED_FATAL,
533 	UFSHCD_STATE_ERROR,
534 };
535 
536 enum ufshcd_quirks {
537 	/* Interrupt aggregation support is broken */
538 	UFSHCD_QUIRK_BROKEN_INTR_AGGR			= 1 << 0,
539 
540 	/*
541 	 * delay before each dme command is required as the unipro
542 	 * layer has shown instabilities
543 	 */
544 	UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS		= 1 << 1,
545 
546 	/*
547 	 * If UFS host controller is having issue in processing LCC (Line
548 	 * Control Command) coming from device then enable this quirk.
549 	 * When this quirk is enabled, host controller driver should disable
550 	 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
551 	 * attribute of device to 0).
552 	 */
553 	UFSHCD_QUIRK_BROKEN_LCC				= 1 << 2,
554 
555 	/*
556 	 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
557 	 * inbound Link supports unterminated line in HS mode. Setting this
558 	 * attribute to 1 fixes moving to HS gear.
559 	 */
560 	UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP		= 1 << 3,
561 
562 	/*
563 	 * This quirk needs to be enabled if the host controller only allows
564 	 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
565 	 * SLOW AUTO).
566 	 */
567 	UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE		= 1 << 4,
568 
569 	/*
570 	 * This quirk needs to be enabled if the host controller doesn't
571 	 * advertise the correct version in UFS_VER register. If this quirk
572 	 * is enabled, standard UFS host driver will call the vendor specific
573 	 * ops (get_ufs_hci_version) to get the correct version.
574 	 */
575 	UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION		= 1 << 5,
576 
577 	/*
578 	 * Clear handling for transfer/task request list is just opposite.
579 	 */
580 	UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR		= 1 << 6,
581 
582 	/*
583 	 * This quirk needs to be enabled if host controller doesn't allow
584 	 * that the interrupt aggregation timer and counter are reset by s/w.
585 	 */
586 	UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR		= 1 << 7,
587 
588 	/*
589 	 * This quirks needs to be enabled if host controller cannot be
590 	 * enabled via HCE register.
591 	 */
592 	UFSHCI_QUIRK_BROKEN_HCE				= 1 << 8,
593 
594 	/*
595 	 * This quirk needs to be enabled if the host controller regards
596 	 * resolution of the values of PRDTO and PRDTL in UTRD as byte.
597 	 */
598 	UFSHCD_QUIRK_PRDT_BYTE_GRAN			= 1 << 9,
599 
600 	/*
601 	 * This quirk needs to be enabled if the host controller reports
602 	 * OCS FATAL ERROR with device error through sense data
603 	 */
604 	UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR		= 1 << 10,
605 
606 	/*
607 	 * This quirk needs to be enabled if the host controller has
608 	 * auto-hibernate capability but it doesn't work.
609 	 */
610 	UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8		= 1 << 11,
611 
612 	/*
613 	 * This quirk needs to disable manual flush for write booster
614 	 */
615 	UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL		= 1 << 12,
616 
617 	/*
618 	 * This quirk needs to disable unipro timeout values
619 	 * before power mode change
620 	 */
621 	UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13,
622 
623 	/*
624 	 * This quirk needs to be enabled if the host controller does not
625 	 * support UIC command
626 	 */
627 	UFSHCD_QUIRK_BROKEN_UIC_CMD			= 1 << 15,
628 
629 	/*
630 	 * This quirk needs to be enabled if the host controller cannot
631 	 * support physical host configuration.
632 	 */
633 	UFSHCD_QUIRK_SKIP_PH_CONFIGURATION		= 1 << 16,
634 
635 	/*
636 	 * This quirk needs to be enabled if the host controller has
637 	 * auto-hibernate capability but it's FASTAUTO only.
638 	 */
639 	UFSHCD_QUIRK_HIBERN_FASTAUTO			= 1 << 18,
640 
641 	/*
642 	 * This quirk needs to be enabled if the host controller needs
643 	 * to reinit the device after switching to maximum gear.
644 	 */
645 	UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH       = 1 << 19,
646 
647 	/*
648 	 * Some host raises interrupt (per queue) in addition to
649 	 * CQES (traditional) when ESI is disabled.
650 	 * Enable this quirk will disable CQES and use per queue interrupt.
651 	 */
652 	UFSHCD_QUIRK_MCQ_BROKEN_INTR			= 1 << 20,
653 
654 	/*
655 	 * Some host does not implement SQ Run Time Command (SQRTC) register
656 	 * thus need this quirk to skip related flow.
657 	 */
658 	UFSHCD_QUIRK_MCQ_BROKEN_RTC			= 1 << 21,
659 
660 	/*
661 	 * This quirk needs to be enabled if the host controller supports inline
662 	 * encryption but it needs to initialize the crypto capabilities in a
663 	 * nonstandard way and/or needs to override blk_crypto_ll_ops.  If
664 	 * enabled, the standard code won't initialize the blk_crypto_profile;
665 	 * ufs_hba_variant_ops::init() must do it instead.
666 	 */
667 	UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE		= 1 << 22,
668 
669 	/*
670 	 * This quirk needs to be enabled if the host controller supports inline
671 	 * encryption but does not support the CRYPTO_GENERAL_ENABLE bit, i.e.
672 	 * host controller initialization fails if that bit is set.
673 	 */
674 	UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE		= 1 << 23,
675 
676 	/*
677 	 * This quirk needs to be enabled if the host controller driver copies
678 	 * cryptographic keys into the PRDT in order to send them to hardware,
679 	 * and therefore the PRDT should be zeroized after each request (as per
680 	 * the standard best practice for managing keys).
681 	 */
682 	UFSHCD_QUIRK_KEYS_IN_PRDT			= 1 << 24,
683 
684 	/*
685 	 * This quirk indicates that the controller reports the value 1 (not
686 	 * supported) in the Legacy Single DoorBell Support (LSDBS) bit of the
687 	 * Controller Capabilities register although it supports the legacy
688 	 * single doorbell mode.
689 	 */
690 	UFSHCD_QUIRK_BROKEN_LSDBS_CAP			= 1 << 25,
691 };
692 
693 enum ufshcd_caps {
694 	/* Allow dynamic clk gating */
695 	UFSHCD_CAP_CLK_GATING				= 1 << 0,
696 
697 	/* Allow hiberb8 with clk gating */
698 	UFSHCD_CAP_HIBERN8_WITH_CLK_GATING		= 1 << 1,
699 
700 	/* Allow dynamic clk scaling */
701 	UFSHCD_CAP_CLK_SCALING				= 1 << 2,
702 
703 	/* Allow auto bkops to enabled during runtime suspend */
704 	UFSHCD_CAP_AUTO_BKOPS_SUSPEND			= 1 << 3,
705 
706 	/*
707 	 * This capability allows host controller driver to use the UFS HCI's
708 	 * interrupt aggregation capability.
709 	 * CAUTION: Enabling this might reduce overall UFS throughput.
710 	 */
711 	UFSHCD_CAP_INTR_AGGR				= 1 << 4,
712 
713 	/*
714 	 * This capability allows the device auto-bkops to be always enabled
715 	 * except during suspend (both runtime and suspend).
716 	 * Enabling this capability means that device will always be allowed
717 	 * to do background operation when it's active but it might degrade
718 	 * the performance of ongoing read/write operations.
719 	 */
720 	UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5,
721 
722 	/*
723 	 * This capability allows host controller driver to automatically
724 	 * enable runtime power management by itself instead of waiting
725 	 * for userspace to control the power management.
726 	 */
727 	UFSHCD_CAP_RPM_AUTOSUSPEND			= 1 << 6,
728 
729 	/*
730 	 * This capability allows the host controller driver to turn-on
731 	 * WriteBooster, if the underlying device supports it and is
732 	 * provisioned to be used. This would increase the write performance.
733 	 */
734 	UFSHCD_CAP_WB_EN				= 1 << 7,
735 
736 	/*
737 	 * This capability allows the host controller driver to use the
738 	 * inline crypto engine, if it is present
739 	 */
740 	UFSHCD_CAP_CRYPTO				= 1 << 8,
741 
742 	/*
743 	 * This capability allows the controller regulators to be put into
744 	 * lpm mode aggressively during clock gating.
745 	 * This would increase power savings.
746 	 */
747 	UFSHCD_CAP_AGGR_POWER_COLLAPSE			= 1 << 9,
748 
749 	/*
750 	 * This capability allows the host controller driver to use DeepSleep,
751 	 * if it is supported by the UFS device. The host controller driver must
752 	 * support device hardware reset via the hba->device_reset() callback,
753 	 * in order to exit DeepSleep state.
754 	 */
755 	UFSHCD_CAP_DEEPSLEEP				= 1 << 10,
756 
757 	/*
758 	 * This capability allows the host controller driver to use temperature
759 	 * notification if it is supported by the UFS device.
760 	 */
761 	UFSHCD_CAP_TEMP_NOTIF				= 1 << 11,
762 
763 	/*
764 	 * Enable WriteBooster when scaling up the clock and disable
765 	 * WriteBooster when scaling the clock down.
766 	 */
767 	UFSHCD_CAP_WB_WITH_CLK_SCALING			= 1 << 12,
768 };
769 
770 struct ufs_hba_variant_params {
771 	struct devfreq_dev_profile devfreq_profile;
772 	struct devfreq_simple_ondemand_data ondemand_data;
773 	u16 hba_enable_delay_us;
774 	u32 wb_flush_threshold;
775 };
776 
777 struct ufs_hba_monitor {
778 	unsigned long chunk_size;
779 
780 	unsigned long nr_sec_rw[2];
781 	ktime_t total_busy[2];
782 
783 	unsigned long nr_req[2];
784 	/* latencies*/
785 	ktime_t lat_sum[2];
786 	ktime_t lat_max[2];
787 	ktime_t lat_min[2];
788 
789 	u32 nr_queued[2];
790 	ktime_t busy_start_ts[2];
791 
792 	ktime_t enabled_ts;
793 	bool enabled;
794 };
795 
796 /**
797  * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers
798  *
799  * @offset: Doorbell Address Offset
800  * @stride: Steps proportional to queue [0...31]
801  * @base: base address
802  */
803 struct ufshcd_mcq_opr_info_t {
804 	unsigned long offset;
805 	unsigned long stride;
806 	void __iomem *base;
807 };
808 
809 enum ufshcd_mcq_opr {
810 	OPR_SQD,
811 	OPR_SQIS,
812 	OPR_CQD,
813 	OPR_CQIS,
814 	OPR_MAX,
815 };
816 
817 /**
818  * struct ufs_hba - per adapter private structure
819  * @mmio_base: UFSHCI base register address
820  * @ucdl_base_addr: UFS Command Descriptor base address
821  * @utrdl_base_addr: UTP Transfer Request Descriptor base address
822  * @utmrdl_base_addr: UTP Task Management Descriptor base address
823  * @ucdl_dma_addr: UFS Command Descriptor DMA address
824  * @utrdl_dma_addr: UTRDL DMA address
825  * @utmrdl_dma_addr: UTMRDL DMA address
826  * @host: Scsi_Host instance of the driver
827  * @dev: device handle
828  * @ufs_device_wlun: WLUN that controls the entire UFS device.
829  * @hwmon_device: device instance registered with the hwmon core.
830  * @curr_dev_pwr_mode: active UFS device power mode.
831  * @uic_link_state: active state of the link to the UFS device.
832  * @rpm_lvl: desired UFS power management level during runtime PM.
833  * @spm_lvl: desired UFS power management level during system PM.
834  * @pm_op_in_progress: whether or not a PM operation is in progress.
835  * @ahit: value of Auto-Hibernate Idle Timer register.
836  * @lrb: local reference block
837  * @outstanding_tasks: Bits representing outstanding task requests
838  * @outstanding_lock: Protects @outstanding_reqs.
839  * @outstanding_reqs: Bits representing outstanding transfer requests
840  * @capabilities: UFS Controller Capabilities
841  * @mcq_capabilities: UFS Multi Circular Queue capabilities
842  * @nutrs: Transfer Request Queue depth supported by controller
843  * @nortt - Max outstanding RTTs supported by controller
844  * @nutmrs: Task Management Queue depth supported by controller
845  * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock.
846  * @ufs_version: UFS Version to which controller complies
847  * @vops: pointer to variant specific operations
848  * @vps: pointer to variant specific parameters
849  * @priv: pointer to variant specific private data
850  * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields)
851  * @irq: Irq number of the controller
852  * @is_irq_enabled: whether or not the UFS controller interrupt is enabled.
853  * @dev_ref_clk_freq: reference clock frequency
854  * @quirks: bitmask with information about deviations from the UFSHCI standard.
855  * @dev_quirks: bitmask with information about deviations from the UFS standard.
856  * @tmf_tag_set: TMF tag set.
857  * @tmf_queue: Used to allocate TMF tags.
858  * @tmf_rqs: array with pointers to TMF requests while these are in progress.
859  * @active_uic_cmd: pointer to active UIC command.
860  * @uic_cmd_mutex: mutex used for serializing UIC command processing.
861  * @uic_async_done: completion used to wait for power mode or hibernation state
862  *	changes.
863  * @ufshcd_state: UFSHCD state
864  * @eh_flags: Error handling flags
865  * @intr_mask: Interrupt Mask Bits
866  * @ee_ctrl_mask: Exception event control mask
867  * @ee_drv_mask: Exception event mask for driver
868  * @ee_usr_mask: Exception event mask for user (set via debugfs)
869  * @ee_ctrl_mutex: Used to serialize exception event information.
870  * @is_powered: flag to check if HBA is powered
871  * @shutting_down: flag to check if shutdown has been invoked
872  * @host_sem: semaphore used to serialize concurrent contexts
873  * @eh_wq: Workqueue that eh_work works on
874  * @eh_work: Worker to handle UFS errors that require s/w attention
875  * @eeh_work: Worker to handle exception events
876  * @errors: HBA errors
877  * @uic_error: UFS interconnect layer error status
878  * @saved_err: sticky error mask
879  * @saved_uic_err: sticky UIC error mask
880  * @ufs_stats: various error counters
881  * @force_reset: flag to force eh_work perform a full reset
882  * @force_pmc: flag to force a power mode change
883  * @silence_err_logs: flag to silence error logs
884  * @dev_cmd: ufs device management command information
885  * @last_dme_cmd_tstamp: time stamp of the last completed DME command
886  * @nop_out_timeout: NOP OUT timeout value
887  * @dev_info: information about the UFS device
888  * @auto_bkops_enabled: to track whether bkops is enabled in device
889  * @vreg_info: UFS device voltage regulator information
890  * @clk_list_head: UFS host controller clocks list node head
891  * @use_pm_opp: Indicates whether OPP based scaling is used or not
892  * @req_abort_count: number of times ufshcd_abort() has been called
893  * @lanes_per_direction: number of lanes per data direction between the UFS
894  *	controller and the UFS device.
895  * @pwr_info: holds current power mode
896  * @max_pwr_info: keeps the device max valid pwm
897  * @clk_gating: information related to clock gating
898  * @caps: bitmask with information about UFS controller capabilities
899  * @devfreq: frequency scaling information owned by the devfreq core
900  * @clk_scaling: frequency scaling information owned by the UFS driver
901  * @system_suspending: system suspend has been started and system resume has
902  *	not yet finished.
903  * @is_sys_suspended: UFS device has been suspended because of system suspend
904  * @urgent_bkops_lvl: keeps track of urgent bkops level for device
905  * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
906  *  device is known or not.
907  * @wb_mutex: used to serialize devfreq and sysfs write booster toggling
908  * @clk_scaling_lock: used to serialize device commands and clock scaling
909  * @desc_size: descriptor sizes reported by device
910  * @bsg_dev: struct device associated with the BSG queue
911  * @bsg_queue: BSG queue associated with the UFS controller
912  * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power
913  *	management) after the UFS device has finished a WriteBooster buffer
914  *	flush or auto BKOP.
915  * @monitor: statistics about UFS commands
916  * @crypto_capabilities: Content of crypto capabilities register (0x100)
917  * @crypto_cap_array: Array of crypto capabilities
918  * @crypto_cfg_register: Start of the crypto cfg array
919  * @crypto_profile: the crypto profile of this hba (if applicable)
920  * @debugfs_root: UFS controller debugfs root directory
921  * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay
922  * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore
923  *	ee_ctrl_mask
924  * @luns_avail: number of regular and well known LUNs supported by the UFS
925  *	device
926  * @nr_hw_queues: number of hardware queues configured
927  * @nr_queues: number of Queues of different queue types
928  * @complete_put: whether or not to call ufshcd_rpm_put() from inside
929  *	ufshcd_resume_complete()
930  * @mcq_sup: is mcq supported by UFSHC
931  * @mcq_enabled: is mcq ready to accept requests
932  * @mcq_esi_enabled: is mcq ESI configured
933  * @res: array of resource info of MCQ registers
934  * @mcq_base: Multi circular queue registers base address
935  * @uhq: array of supported hardware queues
936  * @dev_cmd_queue: Queue for issuing device management commands
937  * @mcq_opr: MCQ operation and runtime registers
938  * @ufs_rtc_update_work: A work for UFS RTC periodic update
939  * @pm_qos_req: PM QoS request handle
940  * @pm_qos_enabled: flag to check if pm qos is enabled
941  * @pm_qos_mutex: synchronizes PM QoS request and status updates
942  * @critical_health_count: count of critical health exceptions
943  * @dev_lvl_exception_count: count of device level exceptions since last reset
944  * @dev_lvl_exception_id: vendor specific information about the
945  * device level exception event.
946  */
947 struct ufs_hba {
948 	void __iomem *mmio_base;
949 
950 	/* Virtual memory reference */
951 	struct utp_transfer_cmd_desc *ucdl_base_addr;
952 	struct utp_transfer_req_desc *utrdl_base_addr;
953 	struct utp_task_req_desc *utmrdl_base_addr;
954 
955 	/* DMA memory reference */
956 	dma_addr_t ucdl_dma_addr;
957 	dma_addr_t utrdl_dma_addr;
958 	dma_addr_t utmrdl_dma_addr;
959 
960 	struct Scsi_Host *host;
961 	struct device *dev;
962 	struct scsi_device *ufs_device_wlun;
963 
964 #ifdef CONFIG_SCSI_UFS_HWMON
965 	struct device *hwmon_device;
966 #endif
967 
968 	enum ufs_dev_pwr_mode curr_dev_pwr_mode;
969 	enum uic_link_state uic_link_state;
970 	/* Desired UFS power management level during runtime PM */
971 	enum ufs_pm_level rpm_lvl;
972 	/* Desired UFS power management level during system PM */
973 	enum ufs_pm_level spm_lvl;
974 	int pm_op_in_progress;
975 
976 	/* Auto-Hibernate Idle Timer register value */
977 	u32 ahit;
978 
979 	struct ufshcd_lrb *lrb;
980 
981 	unsigned long outstanding_tasks;
982 	spinlock_t outstanding_lock;
983 	unsigned long outstanding_reqs;
984 
985 	u32 capabilities;
986 	int nutrs;
987 	int nortt;
988 	u32 mcq_capabilities;
989 	int nutmrs;
990 	u32 reserved_slot;
991 	u32 ufs_version;
992 	const struct ufs_hba_variant_ops *vops;
993 	struct ufs_hba_variant_params *vps;
994 	void *priv;
995 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
996 	size_t sg_entry_size;
997 #endif
998 	unsigned int irq;
999 	bool is_irq_enabled;
1000 	enum ufs_ref_clk_freq dev_ref_clk_freq;
1001 
1002 	unsigned int quirks;	/* Deviations from standard UFSHCI spec. */
1003 
1004 	/* Device deviations from standard UFS device spec. */
1005 	unsigned int dev_quirks;
1006 
1007 	struct blk_mq_tag_set tmf_tag_set;
1008 	struct request_queue *tmf_queue;
1009 	struct request **tmf_rqs;
1010 
1011 	struct uic_command *active_uic_cmd;
1012 	struct mutex uic_cmd_mutex;
1013 	struct completion *uic_async_done;
1014 
1015 	enum ufshcd_state ufshcd_state;
1016 	u32 eh_flags;
1017 	u32 intr_mask;
1018 	u16 ee_ctrl_mask;
1019 	u16 ee_drv_mask;
1020 	u16 ee_usr_mask;
1021 	struct mutex ee_ctrl_mutex;
1022 	bool is_powered;
1023 	bool shutting_down;
1024 	struct semaphore host_sem;
1025 
1026 	/* Work Queues */
1027 	struct workqueue_struct *eh_wq;
1028 	struct work_struct eh_work;
1029 	struct work_struct eeh_work;
1030 
1031 	/* HBA Errors */
1032 	u32 errors;
1033 	u32 uic_error;
1034 	u32 saved_err;
1035 	u32 saved_uic_err;
1036 	struct ufs_stats ufs_stats;
1037 	bool force_reset;
1038 	bool force_pmc;
1039 	bool silence_err_logs;
1040 
1041 	/* Device management request data */
1042 	struct ufs_dev_cmd dev_cmd;
1043 	ktime_t last_dme_cmd_tstamp;
1044 	int nop_out_timeout;
1045 
1046 	/* Keeps information of the UFS device connected to this host */
1047 	struct ufs_dev_info dev_info;
1048 	bool auto_bkops_enabled;
1049 	struct ufs_vreg_info vreg_info;
1050 	struct list_head clk_list_head;
1051 	bool use_pm_opp;
1052 
1053 	/* Number of requests aborts */
1054 	int req_abort_count;
1055 
1056 	/* Number of lanes available (1 or 2) for Rx/Tx */
1057 	u32 lanes_per_direction;
1058 	struct ufs_pa_layer_attr pwr_info;
1059 	struct ufs_pwr_mode_info max_pwr_info;
1060 
1061 	struct ufs_clk_gating clk_gating;
1062 	/* Control to enable/disable host capabilities */
1063 	u32 caps;
1064 
1065 	struct devfreq *devfreq;
1066 	struct ufs_clk_scaling clk_scaling;
1067 	bool system_suspending;
1068 	bool is_sys_suspended;
1069 
1070 	enum bkops_status urgent_bkops_lvl;
1071 	bool is_urgent_bkops_lvl_checked;
1072 
1073 	struct mutex wb_mutex;
1074 	struct rw_semaphore clk_scaling_lock;
1075 
1076 	struct device		bsg_dev;
1077 	struct request_queue	*bsg_queue;
1078 	struct delayed_work rpm_dev_flush_recheck_work;
1079 
1080 	struct ufs_hba_monitor	monitor;
1081 
1082 #ifdef CONFIG_SCSI_UFS_CRYPTO
1083 	union ufs_crypto_capabilities crypto_capabilities;
1084 	union ufs_crypto_cap_entry *crypto_cap_array;
1085 	u32 crypto_cfg_register;
1086 	struct blk_crypto_profile crypto_profile;
1087 #endif
1088 #ifdef CONFIG_DEBUG_FS
1089 	struct dentry *debugfs_root;
1090 	struct delayed_work debugfs_ee_work;
1091 	u32 debugfs_ee_rate_limit_ms;
1092 #endif
1093 #ifdef CONFIG_SCSI_UFS_FAULT_INJECTION
1094 	struct fault_attr trigger_eh_attr;
1095 	struct fault_attr timeout_attr;
1096 #endif
1097 	u32 luns_avail;
1098 	unsigned int nr_hw_queues;
1099 	unsigned int nr_queues[HCTX_MAX_TYPES];
1100 	bool complete_put;
1101 	bool scsi_host_added;
1102 	bool mcq_sup;
1103 	bool lsdb_sup;
1104 	bool mcq_enabled;
1105 	bool mcq_esi_enabled;
1106 	void __iomem *mcq_base;
1107 	struct ufs_hw_queue *uhq;
1108 	struct ufs_hw_queue *dev_cmd_queue;
1109 	struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX];
1110 
1111 	struct delayed_work ufs_rtc_update_work;
1112 	struct pm_qos_request pm_qos_req;
1113 	bool pm_qos_enabled;
1114 	/* synchronizes PM QoS request and status updates */
1115 	struct mutex pm_qos_mutex;
1116 
1117 	int critical_health_count;
1118 	atomic_t dev_lvl_exception_count;
1119 	u64 dev_lvl_exception_id;
1120 };
1121 
1122 /**
1123  * struct ufs_hw_queue - per hardware queue structure
1124  * @mcq_sq_head: base address of submission queue head pointer
1125  * @mcq_sq_tail: base address of submission queue tail pointer
1126  * @mcq_cq_head: base address of completion queue head pointer
1127  * @mcq_cq_tail: base address of completion queue tail pointer
1128  * @sqe_base_addr: submission queue entry base address
1129  * @sqe_dma_addr: submission queue dma address
1130  * @cqe_base_addr: completion queue base address
1131  * @cqe_dma_addr: completion queue dma address
1132  * @max_entries: max number of slots in this hardware queue
1133  * @id: hardware queue ID
1134  * @sq_tp_slot: current slot to which SQ tail pointer is pointing
1135  * @sq_lock: serialize submission queue access
1136  * @cq_tail_slot: current slot to which CQ tail pointer is pointing
1137  * @cq_head_slot: current slot to which CQ head pointer is pointing
1138  * @cq_lock: Synchronize between multiple polling instances
1139  * @sq_mutex: prevent submission queue concurrent access
1140  */
1141 struct ufs_hw_queue {
1142 	void __iomem *mcq_sq_head;
1143 	void __iomem *mcq_sq_tail;
1144 	void __iomem *mcq_cq_head;
1145 	void __iomem *mcq_cq_tail;
1146 
1147 	struct utp_transfer_req_desc *sqe_base_addr;
1148 	dma_addr_t sqe_dma_addr;
1149 	struct cq_entry *cqe_base_addr;
1150 	dma_addr_t cqe_dma_addr;
1151 	u32 max_entries;
1152 	u32 id;
1153 	u32 sq_tail_slot;
1154 	spinlock_t sq_lock;
1155 	u32 cq_tail_slot;
1156 	u32 cq_head_slot;
1157 	spinlock_t cq_lock;
1158 	/* prevent concurrent access to submission queue */
1159 	struct mutex sq_mutex;
1160 };
1161 
1162 #define MCQ_QCFG_SIZE		0x40
1163 
1164 static inline unsigned int ufshcd_mcq_opr_offset(struct ufs_hba *hba,
1165 		enum ufshcd_mcq_opr opr, int idx)
1166 {
1167 	return hba->mcq_opr[opr].offset + hba->mcq_opr[opr].stride * idx;
1168 }
1169 
1170 static inline unsigned int ufshcd_mcq_cfg_offset(unsigned int reg, int idx)
1171 {
1172 	return reg + MCQ_QCFG_SIZE * idx;
1173 }
1174 
1175 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
1176 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1177 {
1178 	return hba->sg_entry_size;
1179 }
1180 
1181 static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size)
1182 {
1183 	WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry));
1184 	hba->sg_entry_size = sg_entry_size;
1185 }
1186 #else
1187 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1188 {
1189 	return sizeof(struct ufshcd_sg_entry);
1190 }
1191 
1192 #define ufshcd_set_sg_entry_size(hba, sg_entry_size)                   \
1193 	({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); })
1194 #endif
1195 
1196 #ifdef CONFIG_SCSI_UFS_CRYPTO
1197 static inline struct ufs_hba *
1198 ufs_hba_from_crypto_profile(struct blk_crypto_profile *profile)
1199 {
1200 	return container_of(profile, struct ufs_hba, crypto_profile);
1201 }
1202 #endif
1203 
1204 static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba)
1205 {
1206 	return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba);
1207 }
1208 
1209 /* Returns true if clocks can be gated. Otherwise false */
1210 static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba)
1211 {
1212 	return hba->caps & UFSHCD_CAP_CLK_GATING;
1213 }
1214 static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba)
1215 {
1216 	return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1217 }
1218 static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba)
1219 {
1220 	return hba->caps & UFSHCD_CAP_CLK_SCALING;
1221 }
1222 static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
1223 {
1224 	return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1225 }
1226 static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba)
1227 {
1228 	return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND;
1229 }
1230 
1231 static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
1232 {
1233 	return (hba->caps & UFSHCD_CAP_INTR_AGGR) &&
1234 		!(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR);
1235 }
1236 
1237 static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba)
1238 {
1239 	return !!(ufshcd_is_link_hibern8(hba) &&
1240 		  (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE));
1241 }
1242 
1243 static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba)
1244 {
1245 	return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) &&
1246 		!(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8);
1247 }
1248 
1249 static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba)
1250 {
1251 	return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit);
1252 }
1253 
1254 static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba)
1255 {
1256 	return hba->caps & UFSHCD_CAP_WB_EN;
1257 }
1258 
1259 static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba)
1260 {
1261 	return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING;
1262 }
1263 
1264 #define ufsmcq_writel(hba, val, reg)	\
1265 	writel((val), (hba)->mcq_base + (reg))
1266 #define ufsmcq_readl(hba, reg)	\
1267 	readl((hba)->mcq_base + (reg))
1268 
1269 #define ufsmcq_writelx(hba, val, reg)	\
1270 	writel_relaxed((val), (hba)->mcq_base + (reg))
1271 #define ufsmcq_readlx(hba, reg)	\
1272 	readl_relaxed((hba)->mcq_base + (reg))
1273 
1274 #define ufshcd_writel(hba, val, reg)	\
1275 	writel((val), (hba)->mmio_base + (reg))
1276 #define ufshcd_readl(hba, reg)	\
1277 	readl((hba)->mmio_base + (reg))
1278 
1279 /**
1280  * ufshcd_rmwl - perform read/modify/write for a controller register
1281  * @hba: per adapter instance
1282  * @mask: mask to apply on read value
1283  * @val: actual value to write
1284  * @reg: register address
1285  */
1286 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
1287 {
1288 	u32 tmp;
1289 
1290 	tmp = ufshcd_readl(hba, reg);
1291 	tmp &= ~mask;
1292 	tmp |= (val & mask);
1293 	ufshcd_writel(hba, tmp, reg);
1294 }
1295 
1296 void ufshcd_enable_irq(struct ufs_hba *hba);
1297 void ufshcd_disable_irq(struct ufs_hba *hba);
1298 void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs);
1299 int ufshcd_alloc_host(struct device *, struct ufs_hba **);
1300 int ufshcd_hba_enable(struct ufs_hba *hba);
1301 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int);
1302 int ufshcd_link_recovery(struct ufs_hba *hba);
1303 int ufshcd_make_hba_operational(struct ufs_hba *hba);
1304 void ufshcd_remove(struct ufs_hba *);
1305 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
1306 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
1307 void ufshcd_delay_us(unsigned long us, unsigned long tolerance);
1308 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk);
1309 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val);
1310 void ufshcd_hba_stop(struct ufs_hba *hba);
1311 void ufshcd_schedule_eh_work(struct ufs_hba *hba);
1312 void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds);
1313 unsigned int ufshcd_mcq_queue_cfg_addr(struct ufs_hba *hba);
1314 u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i);
1315 void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i);
1316 unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba,
1317 					 struct ufs_hw_queue *hwq);
1318 void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba);
1319 void ufshcd_mcq_enable(struct ufs_hba *hba);
1320 void ufshcd_mcq_enable_esi(struct ufs_hba *hba);
1321 void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg);
1322 
1323 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table,
1324 			   struct dev_pm_opp *opp, void *data,
1325 			   bool scaling_down);
1326 /**
1327  * ufshcd_set_variant - set variant specific data to the hba
1328  * @hba: per adapter instance
1329  * @variant: pointer to variant specific data
1330  */
1331 static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant)
1332 {
1333 	BUG_ON(!hba);
1334 	hba->priv = variant;
1335 }
1336 
1337 /**
1338  * ufshcd_get_variant - get variant specific data from the hba
1339  * @hba: per adapter instance
1340  */
1341 static inline void *ufshcd_get_variant(struct ufs_hba *hba)
1342 {
1343 	BUG_ON(!hba);
1344 	return hba->priv;
1345 }
1346 
1347 #ifdef CONFIG_PM
1348 extern int ufshcd_runtime_suspend(struct device *dev);
1349 extern int ufshcd_runtime_resume(struct device *dev);
1350 #endif
1351 #ifdef CONFIG_PM_SLEEP
1352 extern int ufshcd_system_suspend(struct device *dev);
1353 extern int ufshcd_system_resume(struct device *dev);
1354 extern int ufshcd_system_freeze(struct device *dev);
1355 extern int ufshcd_system_thaw(struct device *dev);
1356 extern int ufshcd_system_restore(struct device *dev);
1357 #endif
1358 
1359 extern int ufshcd_dme_reset(struct ufs_hba *hba);
1360 extern int ufshcd_dme_enable(struct ufs_hba *hba);
1361 extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
1362 				      int agreed_gear,
1363 				      int adapt_val);
1364 extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
1365 			       u8 attr_set, u32 mib_val, u8 peer);
1366 extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
1367 			       u32 *mib_val, u8 peer);
1368 extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
1369 			struct ufs_pa_layer_attr *desired_pwr_mode);
1370 extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode);
1371 
1372 /* UIC command interfaces for DME primitives */
1373 #define DME_LOCAL	0
1374 #define DME_PEER	1
1375 #define ATTR_SET_NOR	0	/* NORMAL */
1376 #define ATTR_SET_ST	1	/* STATIC */
1377 
1378 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
1379 				 u32 mib_val)
1380 {
1381 	return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1382 				   mib_val, DME_LOCAL);
1383 }
1384 
1385 static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel,
1386 				    u32 mib_val)
1387 {
1388 	return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1389 				   mib_val, DME_LOCAL);
1390 }
1391 
1392 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
1393 				      u32 mib_val)
1394 {
1395 	return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1396 				   mib_val, DME_PEER);
1397 }
1398 
1399 static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel,
1400 					 u32 mib_val)
1401 {
1402 	return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1403 				   mib_val, DME_PEER);
1404 }
1405 
1406 static inline int ufshcd_dme_get(struct ufs_hba *hba,
1407 				 u32 attr_sel, u32 *mib_val)
1408 {
1409 	return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
1410 }
1411 
1412 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
1413 				      u32 attr_sel, u32 *mib_val)
1414 {
1415 	return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
1416 }
1417 
1418 static inline bool ufshcd_is_hs_mode(const struct ufs_pa_layer_attr *pwr_info)
1419 {
1420 	return (pwr_info->pwr_rx == FAST_MODE ||
1421 		pwr_info->pwr_rx == FASTAUTO_MODE) &&
1422 		(pwr_info->pwr_tx == FAST_MODE ||
1423 		pwr_info->pwr_tx == FASTAUTO_MODE);
1424 }
1425 
1426 static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba)
1427 {
1428 	return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);
1429 }
1430 
1431 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
1432 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
1433 			     const struct ufs_dev_quirk *fixups);
1434 #define SD_ASCII_STD true
1435 #define SD_RAW false
1436 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
1437 			    u8 **buf, bool ascii);
1438 
1439 void ufshcd_hold(struct ufs_hba *hba);
1440 void ufshcd_release(struct ufs_hba *hba);
1441 
1442 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value);
1443 
1444 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg);
1445 
1446 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd);
1447 
1448 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,
1449 				     struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req,
1450 				     struct ufs_ehs *ehs_rsp, int sg_cnt,
1451 				     struct scatterlist *sg_list, enum dma_data_direction dir);
1452 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable);
1453 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable);
1454 int ufshcd_wb_set_resize_en(struct ufs_hba *hba, enum wb_resize_en en_mode);
1455 int ufshcd_suspend_prepare(struct device *dev);
1456 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm);
1457 void ufshcd_resume_complete(struct device *dev);
1458 bool ufshcd_is_hba_active(struct ufs_hba *hba);
1459 void ufshcd_pm_qos_init(struct ufs_hba *hba);
1460 void ufshcd_pm_qos_exit(struct ufs_hba *hba);
1461 int ufshcd_dme_rmw(struct ufs_hba *hba, u32 mask, u32 val, u32 attr);
1462 
1463 /* Wrapper functions for safely calling variant operations */
1464 static inline int ufshcd_vops_init(struct ufs_hba *hba)
1465 {
1466 	if (hba->vops && hba->vops->init)
1467 		return hba->vops->init(hba);
1468 
1469 	return 0;
1470 }
1471 
1472 static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba)
1473 {
1474 	if (hba->vops && hba->vops->phy_initialization)
1475 		return hba->vops->phy_initialization(hba);
1476 
1477 	return 0;
1478 }
1479 
1480 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[];
1481 
1482 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
1483 		     const char *prefix);
1484 
1485 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask);
1486 int ufshcd_write_ee_control(struct ufs_hba *hba);
1487 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
1488 			     const u16 *other_mask, u16 set, u16 clr);
1489 void ufshcd_force_error_recovery(struct ufs_hba *hba);
1490 
1491 #endif /* End of Header */
1492