1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the Texas Instruments DS90UB953 video serializer
4 *
5 * Based on a driver from Luca Ceresoli <luca@lucaceresoli.net>
6 *
7 * Copyright (c) 2019 Luca Ceresoli <luca@lucaceresoli.net>
8 * Copyright (c) 2023 Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
9 */
10
11 #include <linux/clk-provider.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/fwnode.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/i2c-atr.h>
17 #include <linux/i2c.h>
18 #include <linux/kernel.h>
19 #include <linux/math64.h>
20 #include <linux/module.h>
21 #include <linux/property.h>
22 #include <linux/rational.h>
23 #include <linux/regmap.h>
24
25 #include <media/i2c/ds90ub9xx.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-fwnode.h>
28 #include <media/v4l2-mediabus.h>
29 #include <media/v4l2-subdev.h>
30
31 #define UB953_PAD_SINK 0
32 #define UB953_PAD_SOURCE 1
33
34 #define UB953_NUM_GPIOS 4
35
36 #define UB953_DEFAULT_CLKOUT_RATE 25000000UL
37
38 #define UB953_REG_RESET_CTL 0x01
39 #define UB953_REG_RESET_CTL_DIGITAL_RESET_1 BIT(1)
40 #define UB953_REG_RESET_CTL_DIGITAL_RESET_0 BIT(0)
41
42 #define UB953_REG_GENERAL_CFG 0x02
43 #define UB953_REG_GENERAL_CFG_CONT_CLK BIT(6)
44 #define UB953_REG_GENERAL_CFG_CSI_LANE_SEL_SHIFT 4
45 #define UB953_REG_GENERAL_CFG_CSI_LANE_SEL_MASK GENMASK(5, 4)
46 #define UB953_REG_GENERAL_CFG_CRC_TX_GEN_ENABLE BIT(1)
47 #define UB953_REG_GENERAL_CFG_I2C_STRAP_MODE BIT(0)
48
49 #define UB953_REG_MODE_SEL 0x03
50 #define UB953_REG_MODE_SEL_MODE_DONE BIT(3)
51 #define UB953_REG_MODE_SEL_MODE_OVERRIDE BIT(4)
52 #define UB953_REG_MODE_SEL_MODE_MASK GENMASK(2, 0)
53
54 #define UB953_REG_CLKOUT_CTRL0 0x06
55 #define UB953_REG_CLKOUT_CTRL1 0x07
56
57 #define UB953_REG_SCL_HIGH_TIME 0x0b
58 #define UB953_REG_SCL_LOW_TIME 0x0c
59
60 #define UB953_REG_LOCAL_GPIO_DATA 0x0d
61 #define UB953_REG_LOCAL_GPIO_DATA_GPIO_RMTEN(n) BIT(4 + (n))
62 #define UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(n) BIT(0 + (n))
63
64 #define UB953_REG_GPIO_INPUT_CTRL 0x0e
65 #define UB953_REG_GPIO_INPUT_CTRL_OUT_EN(n) BIT(4 + (n))
66 #define UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(n) BIT(0 + (n))
67
68 #define UB953_REG_BC_CTRL 0x49
69 #define UB953_REG_BC_CTRL_CRC_ERR_CLR BIT(3)
70
71 #define UB953_REG_REV_MASK_ID 0x50
72 #define UB953_REG_GENERAL_STATUS 0x52
73
74 #define UB953_REG_GPIO_PIN_STS 0x53
75 #define UB953_REG_GPIO_PIN_STS_GPIO_STS(n) BIT(0 + (n))
76
77 #define UB953_REG_BIST_ERR_CNT 0x54
78 #define UB953_REG_CRC_ERR_CNT1 0x55
79 #define UB953_REG_CRC_ERR_CNT2 0x56
80
81 #define UB953_REG_CSI_ERR_CNT 0x5c
82 #define UB953_REG_CSI_ERR_STATUS 0x5d
83 #define UB953_REG_CSI_ERR_DLANE01 0x5e
84 #define UB953_REG_CSI_ERR_DLANE23 0x5f
85 #define UB953_REG_CSI_ERR_CLK_LANE 0x60
86 #define UB953_REG_CSI_PKT_HDR_VC_ID 0x61
87 #define UB953_REG_PKT_HDR_WC_LSB 0x62
88 #define UB953_REG_PKT_HDR_WC_MSB 0x63
89 #define UB953_REG_CSI_ECC 0x64
90
91 #define UB953_REG_IND_ACC_CTL 0xb0
92 #define UB953_REG_IND_ACC_ADDR 0xb1
93 #define UB953_REG_IND_ACC_DATA 0xb2
94
95 #define UB953_REG_FPD3_RX_ID(n) (0xf0 + (n))
96 #define UB953_REG_FPD3_RX_ID_LEN 6
97
98 /* Indirect register blocks */
99 #define UB953_IND_TARGET_PAT_GEN 0x00
100 #define UB953_IND_TARGET_FPD3_TX 0x01
101 #define UB953_IND_TARGET_DIE_ID 0x02
102
103 #define UB953_IND_PGEN_CTL 0x01
104 #define UB953_IND_PGEN_CTL_PGEN_ENABLE BIT(0)
105 #define UB953_IND_PGEN_CFG 0x02
106 #define UB953_IND_PGEN_CSI_DI 0x03
107 #define UB953_IND_PGEN_LINE_SIZE1 0x04
108 #define UB953_IND_PGEN_LINE_SIZE0 0x05
109 #define UB953_IND_PGEN_BAR_SIZE1 0x06
110 #define UB953_IND_PGEN_BAR_SIZE0 0x07
111 #define UB953_IND_PGEN_ACT_LPF1 0x08
112 #define UB953_IND_PGEN_ACT_LPF0 0x09
113 #define UB953_IND_PGEN_TOT_LPF1 0x0a
114 #define UB953_IND_PGEN_TOT_LPF0 0x0b
115 #define UB953_IND_PGEN_LINE_PD1 0x0c
116 #define UB953_IND_PGEN_LINE_PD0 0x0d
117 #define UB953_IND_PGEN_VBP 0x0e
118 #define UB953_IND_PGEN_VFP 0x0f
119 #define UB953_IND_PGEN_COLOR(n) (0x10 + (n)) /* n <= 15 */
120
121 /* Note: Only sync mode supported for now */
122 enum ub953_mode {
123 /* FPD-Link III CSI-2 synchronous mode */
124 UB953_MODE_SYNC,
125 /* FPD-Link III CSI-2 non-synchronous mode, external ref clock */
126 UB953_MODE_NONSYNC_EXT,
127 /* FPD-Link III CSI-2 non-synchronous mode, internal ref clock */
128 UB953_MODE_NONSYNC_INT,
129 /* FPD-Link III DVP mode */
130 UB953_MODE_DVP,
131 };
132
133 struct ub953_hw_data {
134 const char *model;
135 bool is_ub971;
136 };
137
138 struct ub953_clkout_data {
139 u32 hs_div;
140 u32 m;
141 u32 n;
142 unsigned long rate;
143 };
144
145 struct ub953_data {
146 const struct ub953_hw_data *hw_data;
147
148 struct i2c_client *client;
149 struct regmap *regmap;
150 struct clk *clkin;
151
152 u32 num_data_lanes;
153 bool non_continous_clk;
154
155 struct gpio_chip gpio_chip;
156
157 struct v4l2_subdev sd;
158 struct media_pad pads[2];
159
160 struct v4l2_async_notifier notifier;
161
162 struct v4l2_subdev *source_sd;
163 u16 source_sd_pad;
164
165 u64 enabled_source_streams;
166
167 /* lock for register access */
168 struct mutex reg_lock;
169
170 u8 current_indirect_target;
171
172 struct clk_hw clkout_clk_hw;
173
174 enum ub953_mode mode;
175
176 const struct ds90ub9xx_platform_data *plat_data;
177 };
178
sd_to_ub953(struct v4l2_subdev * sd)179 static inline struct ub953_data *sd_to_ub953(struct v4l2_subdev *sd)
180 {
181 return container_of(sd, struct ub953_data, sd);
182 }
183
184 /*
185 * HW Access
186 */
187
ub953_read(struct ub953_data * priv,u8 reg,u8 * val)188 static int ub953_read(struct ub953_data *priv, u8 reg, u8 *val)
189 {
190 unsigned int v;
191 int ret;
192
193 mutex_lock(&priv->reg_lock);
194
195 ret = regmap_read(priv->regmap, reg, &v);
196 if (ret) {
197 dev_err(&priv->client->dev, "Cannot read register 0x%02x: %d\n",
198 reg, ret);
199 goto out_unlock;
200 }
201
202 *val = v;
203
204 out_unlock:
205 mutex_unlock(&priv->reg_lock);
206
207 return ret;
208 }
209
ub953_write(struct ub953_data * priv,u8 reg,u8 val)210 static int ub953_write(struct ub953_data *priv, u8 reg, u8 val)
211 {
212 int ret;
213
214 mutex_lock(&priv->reg_lock);
215
216 ret = regmap_write(priv->regmap, reg, val);
217 if (ret)
218 dev_err(&priv->client->dev,
219 "Cannot write register 0x%02x: %d\n", reg, ret);
220
221 mutex_unlock(&priv->reg_lock);
222
223 return ret;
224 }
225
ub953_select_ind_reg_block(struct ub953_data * priv,u8 block)226 static int ub953_select_ind_reg_block(struct ub953_data *priv, u8 block)
227 {
228 struct device *dev = &priv->client->dev;
229 int ret;
230
231 if (priv->current_indirect_target == block)
232 return 0;
233
234 ret = regmap_write(priv->regmap, UB953_REG_IND_ACC_CTL, block << 2);
235 if (ret) {
236 dev_err(dev, "%s: cannot select indirect target %u (%d)\n",
237 __func__, block, ret);
238 return ret;
239 }
240
241 priv->current_indirect_target = block;
242
243 return 0;
244 }
245
246 __maybe_unused
ub953_read_ind(struct ub953_data * priv,u8 block,u8 reg,u8 * val)247 static int ub953_read_ind(struct ub953_data *priv, u8 block, u8 reg, u8 *val)
248 {
249 unsigned int v;
250 int ret;
251
252 mutex_lock(&priv->reg_lock);
253
254 ret = ub953_select_ind_reg_block(priv, block);
255 if (ret)
256 goto out_unlock;
257
258 ret = regmap_write(priv->regmap, UB953_REG_IND_ACC_ADDR, reg);
259 if (ret) {
260 dev_err(&priv->client->dev,
261 "Write to IND_ACC_ADDR failed when reading %u:%x02x: %d\n",
262 block, reg, ret);
263 goto out_unlock;
264 }
265
266 ret = regmap_read(priv->regmap, UB953_REG_IND_ACC_DATA, &v);
267 if (ret) {
268 dev_err(&priv->client->dev,
269 "Write to IND_ACC_DATA failed when reading %u:%x02x: %d\n",
270 block, reg, ret);
271 goto out_unlock;
272 }
273
274 *val = v;
275
276 out_unlock:
277 mutex_unlock(&priv->reg_lock);
278
279 return ret;
280 }
281
282 __maybe_unused
ub953_write_ind(struct ub953_data * priv,u8 block,u8 reg,u8 val)283 static int ub953_write_ind(struct ub953_data *priv, u8 block, u8 reg, u8 val)
284 {
285 int ret;
286
287 mutex_lock(&priv->reg_lock);
288
289 ret = ub953_select_ind_reg_block(priv, block);
290 if (ret)
291 goto out_unlock;
292
293 ret = regmap_write(priv->regmap, UB953_REG_IND_ACC_ADDR, reg);
294 if (ret) {
295 dev_err(&priv->client->dev,
296 "Write to IND_ACC_ADDR failed when writing %u:%x02x: %d\n",
297 block, reg, ret);
298 goto out_unlock;
299 }
300
301 ret = regmap_write(priv->regmap, UB953_REG_IND_ACC_DATA, val);
302 if (ret) {
303 dev_err(&priv->client->dev,
304 "Write to IND_ACC_DATA failed when writing %u:%x02x\n: %d\n",
305 block, reg, ret);
306 }
307
308 out_unlock:
309 mutex_unlock(&priv->reg_lock);
310
311 return ret;
312 }
313
314 /*
315 * GPIO chip
316 */
ub953_gpio_get_direction(struct gpio_chip * gc,unsigned int offset)317 static int ub953_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
318 {
319 struct ub953_data *priv = gpiochip_get_data(gc);
320 int ret;
321 u8 v;
322
323 ret = ub953_read(priv, UB953_REG_GPIO_INPUT_CTRL, &v);
324 if (ret)
325 return ret;
326
327 if (v & UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(offset))
328 return GPIO_LINE_DIRECTION_IN;
329 else
330 return GPIO_LINE_DIRECTION_OUT;
331 }
332
ub953_gpio_direction_in(struct gpio_chip * gc,unsigned int offset)333 static int ub953_gpio_direction_in(struct gpio_chip *gc, unsigned int offset)
334 {
335 struct ub953_data *priv = gpiochip_get_data(gc);
336
337 return regmap_update_bits(priv->regmap, UB953_REG_GPIO_INPUT_CTRL,
338 UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(offset) |
339 UB953_REG_GPIO_INPUT_CTRL_OUT_EN(offset),
340 UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(offset));
341 }
342
ub953_gpio_direction_out(struct gpio_chip * gc,unsigned int offset,int value)343 static int ub953_gpio_direction_out(struct gpio_chip *gc, unsigned int offset,
344 int value)
345 {
346 struct ub953_data *priv = gpiochip_get_data(gc);
347 int ret;
348
349 ret = regmap_update_bits(priv->regmap, UB953_REG_LOCAL_GPIO_DATA,
350 UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(offset),
351 value ? UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(offset) :
352 0);
353
354 if (ret)
355 return ret;
356
357 return regmap_update_bits(priv->regmap, UB953_REG_GPIO_INPUT_CTRL,
358 UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(offset) |
359 UB953_REG_GPIO_INPUT_CTRL_OUT_EN(offset),
360 UB953_REG_GPIO_INPUT_CTRL_OUT_EN(offset));
361 }
362
ub953_gpio_get(struct gpio_chip * gc,unsigned int offset)363 static int ub953_gpio_get(struct gpio_chip *gc, unsigned int offset)
364 {
365 struct ub953_data *priv = gpiochip_get_data(gc);
366 int ret;
367 u8 v;
368
369 ret = ub953_read(priv, UB953_REG_GPIO_PIN_STS, &v);
370 if (ret)
371 return ret;
372
373 return !!(v & UB953_REG_GPIO_PIN_STS_GPIO_STS(offset));
374 }
375
ub953_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)376 static void ub953_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
377 {
378 struct ub953_data *priv = gpiochip_get_data(gc);
379
380 regmap_update_bits(priv->regmap, UB953_REG_LOCAL_GPIO_DATA,
381 UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(offset),
382 value ? UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(offset) :
383 0);
384 }
385
ub953_gpio_of_xlate(struct gpio_chip * gc,const struct of_phandle_args * gpiospec,u32 * flags)386 static int ub953_gpio_of_xlate(struct gpio_chip *gc,
387 const struct of_phandle_args *gpiospec,
388 u32 *flags)
389 {
390 if (flags)
391 *flags = gpiospec->args[1];
392
393 return gpiospec->args[0];
394 }
395
ub953_gpiochip_probe(struct ub953_data * priv)396 static int ub953_gpiochip_probe(struct ub953_data *priv)
397 {
398 struct device *dev = &priv->client->dev;
399 struct gpio_chip *gc = &priv->gpio_chip;
400 int ret;
401
402 /* Set all GPIOs to local input mode */
403 ret = ub953_write(priv, UB953_REG_LOCAL_GPIO_DATA, 0);
404 if (ret)
405 return ret;
406
407 ret = ub953_write(priv, UB953_REG_GPIO_INPUT_CTRL, 0xf);
408 if (ret)
409 return ret;
410
411 gc->label = dev_name(dev);
412 gc->parent = dev;
413 gc->owner = THIS_MODULE;
414 gc->base = -1;
415 gc->can_sleep = true;
416 gc->ngpio = UB953_NUM_GPIOS;
417 gc->get_direction = ub953_gpio_get_direction;
418 gc->direction_input = ub953_gpio_direction_in;
419 gc->direction_output = ub953_gpio_direction_out;
420 gc->get = ub953_gpio_get;
421 gc->set = ub953_gpio_set;
422 gc->of_xlate = ub953_gpio_of_xlate;
423 gc->of_gpio_n_cells = 2;
424
425 ret = gpiochip_add_data(gc, priv);
426 if (ret) {
427 dev_err(dev, "Failed to add GPIOs: %d\n", ret);
428 return ret;
429 }
430
431 return 0;
432 }
433
ub953_gpiochip_remove(struct ub953_data * priv)434 static void ub953_gpiochip_remove(struct ub953_data *priv)
435 {
436 gpiochip_remove(&priv->gpio_chip);
437 }
438
439 /*
440 * V4L2
441 */
442
_ub953_set_routing(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_krouting * routing)443 static int _ub953_set_routing(struct v4l2_subdev *sd,
444 struct v4l2_subdev_state *state,
445 struct v4l2_subdev_krouting *routing)
446 {
447 static const struct v4l2_mbus_framefmt format = {
448 .width = 640,
449 .height = 480,
450 .code = MEDIA_BUS_FMT_UYVY8_1X16,
451 .field = V4L2_FIELD_NONE,
452 .colorspace = V4L2_COLORSPACE_SRGB,
453 .ycbcr_enc = V4L2_YCBCR_ENC_601,
454 .quantization = V4L2_QUANTIZATION_LIM_RANGE,
455 .xfer_func = V4L2_XFER_FUNC_SRGB,
456 };
457 int ret;
458
459 /*
460 * Note: we can only support up to V4L2_FRAME_DESC_ENTRY_MAX, until
461 * frame desc is made dynamically allocated.
462 */
463
464 if (routing->num_routes > V4L2_FRAME_DESC_ENTRY_MAX)
465 return -EINVAL;
466
467 ret = v4l2_subdev_routing_validate(sd, routing,
468 V4L2_SUBDEV_ROUTING_ONLY_1_TO_1);
469 if (ret)
470 return ret;
471
472 ret = v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format);
473 if (ret)
474 return ret;
475
476 return 0;
477 }
478
ub953_set_routing(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,enum v4l2_subdev_format_whence which,struct v4l2_subdev_krouting * routing)479 static int ub953_set_routing(struct v4l2_subdev *sd,
480 struct v4l2_subdev_state *state,
481 enum v4l2_subdev_format_whence which,
482 struct v4l2_subdev_krouting *routing)
483 {
484 struct ub953_data *priv = sd_to_ub953(sd);
485
486 if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->enabled_source_streams)
487 return -EBUSY;
488
489 return _ub953_set_routing(sd, state, routing);
490 }
491
ub953_get_frame_desc(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_frame_desc * fd)492 static int ub953_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
493 struct v4l2_mbus_frame_desc *fd)
494 {
495 struct ub953_data *priv = sd_to_ub953(sd);
496 struct v4l2_mbus_frame_desc source_fd;
497 struct v4l2_subdev_route *route;
498 struct v4l2_subdev_state *state;
499 int ret;
500
501 if (pad != UB953_PAD_SOURCE)
502 return -EINVAL;
503
504 ret = v4l2_subdev_call(priv->source_sd, pad, get_frame_desc,
505 priv->source_sd_pad, &source_fd);
506 if (ret)
507 return ret;
508
509 fd->type = V4L2_MBUS_FRAME_DESC_TYPE_CSI2;
510
511 state = v4l2_subdev_lock_and_get_active_state(sd);
512
513 for_each_active_route(&state->routing, route) {
514 struct v4l2_mbus_frame_desc_entry *source_entry = NULL;
515 unsigned int i;
516
517 if (route->source_pad != pad)
518 continue;
519
520 for (i = 0; i < source_fd.num_entries; i++) {
521 if (source_fd.entry[i].stream == route->sink_stream) {
522 source_entry = &source_fd.entry[i];
523 break;
524 }
525 }
526
527 if (!source_entry) {
528 dev_err(&priv->client->dev,
529 "Failed to find stream from source frame desc\n");
530 ret = -EPIPE;
531 goto out_unlock;
532 }
533
534 fd->entry[fd->num_entries].stream = route->source_stream;
535 fd->entry[fd->num_entries].flags = source_entry->flags;
536 fd->entry[fd->num_entries].length = source_entry->length;
537 fd->entry[fd->num_entries].pixelcode = source_entry->pixelcode;
538 fd->entry[fd->num_entries].bus.csi2.vc =
539 source_entry->bus.csi2.vc;
540 fd->entry[fd->num_entries].bus.csi2.dt =
541 source_entry->bus.csi2.dt;
542
543 fd->num_entries++;
544 }
545
546 out_unlock:
547 v4l2_subdev_unlock_state(state);
548
549 return ret;
550 }
551
ub953_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_format * format)552 static int ub953_set_fmt(struct v4l2_subdev *sd,
553 struct v4l2_subdev_state *state,
554 struct v4l2_subdev_format *format)
555 {
556 struct ub953_data *priv = sd_to_ub953(sd);
557 struct v4l2_mbus_framefmt *fmt;
558
559 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE &&
560 priv->enabled_source_streams)
561 return -EBUSY;
562
563 /* No transcoding, source and sink formats must match. */
564 if (format->pad == UB953_PAD_SOURCE)
565 return v4l2_subdev_get_fmt(sd, state, format);
566
567 /* Set sink format */
568 fmt = v4l2_subdev_state_get_format(state, format->pad, format->stream);
569 if (!fmt)
570 return -EINVAL;
571
572 *fmt = format->format;
573
574 /* Propagate to source format */
575 fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad,
576 format->stream);
577 if (!fmt)
578 return -EINVAL;
579
580 *fmt = format->format;
581
582 return 0;
583 }
584
ub953_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * state)585 static int ub953_init_state(struct v4l2_subdev *sd,
586 struct v4l2_subdev_state *state)
587 {
588 struct v4l2_subdev_route routes[] = {
589 {
590 .sink_pad = UB953_PAD_SINK,
591 .sink_stream = 0,
592 .source_pad = UB953_PAD_SOURCE,
593 .source_stream = 0,
594 .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE,
595 },
596 };
597
598 struct v4l2_subdev_krouting routing = {
599 .num_routes = ARRAY_SIZE(routes),
600 .routes = routes,
601 };
602
603 return _ub953_set_routing(sd, state, &routing);
604 }
605
ub953_log_status(struct v4l2_subdev * sd)606 static int ub953_log_status(struct v4l2_subdev *sd)
607 {
608 struct ub953_data *priv = sd_to_ub953(sd);
609 struct device *dev = &priv->client->dev;
610 u8 v = 0, v1 = 0, v2 = 0;
611 unsigned int i;
612 char id[UB953_REG_FPD3_RX_ID_LEN];
613 u8 gpio_local_data = 0;
614 u8 gpio_input_ctrl = 0;
615 u8 gpio_pin_sts = 0;
616
617 for (i = 0; i < sizeof(id); i++)
618 ub953_read(priv, UB953_REG_FPD3_RX_ID(i), &id[i]);
619
620 dev_info(dev, "ID '%.*s'\n", (int)sizeof(id), id);
621
622 ub953_read(priv, UB953_REG_GENERAL_STATUS, &v);
623 dev_info(dev, "GENERAL_STATUS %#02x\n", v);
624
625 ub953_read(priv, UB953_REG_CRC_ERR_CNT1, &v1);
626 ub953_read(priv, UB953_REG_CRC_ERR_CNT2, &v2);
627 dev_info(dev, "CRC error count %u\n", v1 | (v2 << 8));
628
629 /* Clear CRC error counter */
630 if (v1 || v2)
631 regmap_update_bits(priv->regmap, UB953_REG_BC_CTRL,
632 UB953_REG_BC_CTRL_CRC_ERR_CLR,
633 UB953_REG_BC_CTRL_CRC_ERR_CLR);
634
635 ub953_read(priv, UB953_REG_CSI_ERR_CNT, &v);
636 dev_info(dev, "CSI error count %u\n", v);
637
638 ub953_read(priv, UB953_REG_CSI_ERR_STATUS, &v);
639 dev_info(dev, "CSI_ERR_STATUS %#02x\n", v);
640
641 ub953_read(priv, UB953_REG_CSI_ERR_DLANE01, &v);
642 dev_info(dev, "CSI_ERR_DLANE01 %#02x\n", v);
643
644 ub953_read(priv, UB953_REG_CSI_ERR_DLANE23, &v);
645 dev_info(dev, "CSI_ERR_DLANE23 %#02x\n", v);
646
647 ub953_read(priv, UB953_REG_CSI_ERR_CLK_LANE, &v);
648 dev_info(dev, "CSI_ERR_CLK_LANE %#02x\n", v);
649
650 ub953_read(priv, UB953_REG_CSI_PKT_HDR_VC_ID, &v);
651 dev_info(dev, "CSI packet header VC %u ID %u\n", v >> 6, v & 0x3f);
652
653 ub953_read(priv, UB953_REG_PKT_HDR_WC_LSB, &v1);
654 ub953_read(priv, UB953_REG_PKT_HDR_WC_MSB, &v2);
655 dev_info(dev, "CSI packet header WC %u\n", (v2 << 8) | v1);
656
657 ub953_read(priv, UB953_REG_CSI_ECC, &v);
658 dev_info(dev, "CSI ECC %#02x\n", v);
659
660 ub953_read(priv, UB953_REG_LOCAL_GPIO_DATA, &gpio_local_data);
661 ub953_read(priv, UB953_REG_GPIO_INPUT_CTRL, &gpio_input_ctrl);
662 ub953_read(priv, UB953_REG_GPIO_PIN_STS, &gpio_pin_sts);
663
664 for (i = 0; i < UB953_NUM_GPIOS; i++) {
665 dev_info(dev,
666 "GPIO%u: remote: %u is_input: %u is_output: %u val: %u sts: %u\n",
667 i,
668 !!(gpio_local_data & UB953_REG_LOCAL_GPIO_DATA_GPIO_RMTEN(i)),
669 !!(gpio_input_ctrl & UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(i)),
670 !!(gpio_input_ctrl & UB953_REG_GPIO_INPUT_CTRL_OUT_EN(i)),
671 !!(gpio_local_data & UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(i)),
672 !!(gpio_pin_sts & UB953_REG_GPIO_PIN_STS_GPIO_STS(i)));
673 }
674
675 return 0;
676 }
677
ub953_enable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)678 static int ub953_enable_streams(struct v4l2_subdev *sd,
679 struct v4l2_subdev_state *state, u32 pad,
680 u64 streams_mask)
681 {
682 struct ub953_data *priv = sd_to_ub953(sd);
683 u64 sink_streams;
684 int ret;
685
686 sink_streams = v4l2_subdev_state_xlate_streams(state, UB953_PAD_SOURCE,
687 UB953_PAD_SINK,
688 &streams_mask);
689
690 ret = v4l2_subdev_enable_streams(priv->source_sd, priv->source_sd_pad,
691 sink_streams);
692 if (ret)
693 return ret;
694
695 priv->enabled_source_streams |= streams_mask;
696
697 return 0;
698 }
699
ub953_disable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)700 static int ub953_disable_streams(struct v4l2_subdev *sd,
701 struct v4l2_subdev_state *state, u32 pad,
702 u64 streams_mask)
703 {
704 struct ub953_data *priv = sd_to_ub953(sd);
705 u64 sink_streams;
706 int ret;
707
708 sink_streams = v4l2_subdev_state_xlate_streams(state, UB953_PAD_SOURCE,
709 UB953_PAD_SINK,
710 &streams_mask);
711
712 ret = v4l2_subdev_disable_streams(priv->source_sd, priv->source_sd_pad,
713 sink_streams);
714 if (ret)
715 return ret;
716
717 priv->enabled_source_streams &= ~streams_mask;
718
719 return 0;
720 }
721
722 static const struct v4l2_subdev_pad_ops ub953_pad_ops = {
723 .enable_streams = ub953_enable_streams,
724 .disable_streams = ub953_disable_streams,
725 .set_routing = ub953_set_routing,
726 .get_frame_desc = ub953_get_frame_desc,
727 .get_fmt = v4l2_subdev_get_fmt,
728 .set_fmt = ub953_set_fmt,
729 };
730
731 static const struct v4l2_subdev_core_ops ub953_subdev_core_ops = {
732 .log_status = ub953_log_status,
733 };
734
735 static const struct v4l2_subdev_ops ub953_subdev_ops = {
736 .core = &ub953_subdev_core_ops,
737 .pad = &ub953_pad_ops,
738 };
739
740 static const struct v4l2_subdev_internal_ops ub953_internal_ops = {
741 .init_state = ub953_init_state,
742 };
743
744 static const struct media_entity_operations ub953_entity_ops = {
745 .link_validate = v4l2_subdev_link_validate,
746 };
747
ub953_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * source_subdev,struct v4l2_async_connection * asd)748 static int ub953_notify_bound(struct v4l2_async_notifier *notifier,
749 struct v4l2_subdev *source_subdev,
750 struct v4l2_async_connection *asd)
751 {
752 struct ub953_data *priv = sd_to_ub953(notifier->sd);
753 struct device *dev = &priv->client->dev;
754 int ret;
755
756 ret = media_entity_get_fwnode_pad(&source_subdev->entity,
757 source_subdev->fwnode,
758 MEDIA_PAD_FL_SOURCE);
759 if (ret < 0) {
760 dev_err(dev, "Failed to find pad for %s\n",
761 source_subdev->name);
762 return ret;
763 }
764
765 priv->source_sd = source_subdev;
766 priv->source_sd_pad = ret;
767
768 ret = media_create_pad_link(&source_subdev->entity, priv->source_sd_pad,
769 &priv->sd.entity, 0,
770 MEDIA_LNK_FL_ENABLED |
771 MEDIA_LNK_FL_IMMUTABLE);
772 if (ret) {
773 dev_err(dev, "Unable to link %s:%u -> %s:0\n",
774 source_subdev->name, priv->source_sd_pad,
775 priv->sd.name);
776 return ret;
777 }
778
779 return 0;
780 }
781
782 static const struct v4l2_async_notifier_operations ub953_notify_ops = {
783 .bound = ub953_notify_bound,
784 };
785
ub953_v4l2_notifier_register(struct ub953_data * priv)786 static int ub953_v4l2_notifier_register(struct ub953_data *priv)
787 {
788 struct device *dev = &priv->client->dev;
789 struct v4l2_async_connection *asd;
790 struct fwnode_handle *ep_fwnode;
791 int ret;
792
793 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
794 UB953_PAD_SINK, 0, 0);
795 if (!ep_fwnode) {
796 dev_err(dev, "No graph endpoint\n");
797 return -ENODEV;
798 }
799
800 v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd);
801
802 asd = v4l2_async_nf_add_fwnode_remote(&priv->notifier, ep_fwnode,
803 struct v4l2_async_connection);
804
805 fwnode_handle_put(ep_fwnode);
806
807 if (IS_ERR(asd)) {
808 dev_err(dev, "Failed to add subdev: %ld", PTR_ERR(asd));
809 v4l2_async_nf_cleanup(&priv->notifier);
810 return PTR_ERR(asd);
811 }
812
813 priv->notifier.ops = &ub953_notify_ops;
814
815 ret = v4l2_async_nf_register(&priv->notifier);
816 if (ret) {
817 dev_err(dev, "Failed to register subdev_notifier");
818 v4l2_async_nf_cleanup(&priv->notifier);
819 return ret;
820 }
821
822 return 0;
823 }
824
ub953_v4l2_notifier_unregister(struct ub953_data * priv)825 static void ub953_v4l2_notifier_unregister(struct ub953_data *priv)
826 {
827 v4l2_async_nf_unregister(&priv->notifier);
828 v4l2_async_nf_cleanup(&priv->notifier);
829 }
830
831 /*
832 * Probing
833 */
834
ub953_i2c_master_init(struct ub953_data * priv)835 static int ub953_i2c_master_init(struct ub953_data *priv)
836 {
837 /* i2c fast mode */
838 u32 ref = 26250000;
839 u32 scl_high = 915; /* ns */
840 u32 scl_low = 1641; /* ns */
841 int ret;
842
843 scl_high = div64_u64((u64)scl_high * ref, 1000000000) - 5;
844 scl_low = div64_u64((u64)scl_low * ref, 1000000000) - 5;
845
846 ret = ub953_write(priv, UB953_REG_SCL_HIGH_TIME, scl_high);
847 if (ret)
848 return ret;
849
850 ret = ub953_write(priv, UB953_REG_SCL_LOW_TIME, scl_low);
851 if (ret)
852 return ret;
853
854 return 0;
855 }
856
ub953_get_fc_rate(struct ub953_data * priv)857 static u64 ub953_get_fc_rate(struct ub953_data *priv)
858 {
859 switch (priv->mode) {
860 case UB953_MODE_SYNC:
861 if (priv->hw_data->is_ub971)
862 return priv->plat_data->bc_rate * 160ull;
863 else
864 return priv->plat_data->bc_rate / 2 * 160ull;
865
866 case UB953_MODE_NONSYNC_EXT:
867 /* CLKIN_DIV = 1 always */
868 return clk_get_rate(priv->clkin) * 80ull;
869
870 default:
871 /* Not supported */
872 return 0;
873 }
874 }
875
ub953_calc_clkout_ub953(struct ub953_data * priv,unsigned long target,u64 fc,u8 * hs_div,u8 * m,u8 * n)876 static unsigned long ub953_calc_clkout_ub953(struct ub953_data *priv,
877 unsigned long target, u64 fc,
878 u8 *hs_div, u8 *m, u8 *n)
879 {
880 /*
881 * We always use 4 as a pre-divider (HS_CLK_DIV = 2).
882 *
883 * According to the datasheet:
884 * - "HS_CLK_DIV typically should be set to either 16, 8, or 4 (default)."
885 * - "if it is not possible to have an integer ratio of N/M, it is best to
886 * select a smaller value for HS_CLK_DIV.
887 *
888 * For above reasons the default HS_CLK_DIV seems the best in the average
889 * case. Use always that value to keep the code simple.
890 */
891 static const unsigned long hs_clk_div = 4;
892
893 u64 fc_divided;
894 unsigned long mul, div;
895 unsigned long res;
896
897 /* clkout = fc / hs_clk_div * m / n */
898
899 fc_divided = div_u64(fc, hs_clk_div);
900
901 rational_best_approximation(target, fc_divided, (1 << 5) - 1,
902 (1 << 8) - 1, &mul, &div);
903
904 res = div_u64(fc_divided * mul, div);
905
906 *hs_div = hs_clk_div;
907 *m = mul;
908 *n = div;
909
910 return res;
911 }
912
ub953_calc_clkout_ub971(struct ub953_data * priv,unsigned long target,u64 fc,u8 * m,u8 * n)913 static unsigned long ub953_calc_clkout_ub971(struct ub953_data *priv,
914 unsigned long target, u64 fc,
915 u8 *m, u8 *n)
916 {
917 u64 fc_divided;
918 unsigned long mul, div;
919 unsigned long res;
920
921 /* clkout = fc * m / (8 * n) */
922
923 fc_divided = div_u64(fc, 8);
924
925 rational_best_approximation(target, fc_divided, (1 << 5) - 1,
926 (1 << 8) - 1, &mul, &div);
927
928 res = div_u64(fc_divided * mul, div);
929
930 *m = mul;
931 *n = div;
932
933 return res;
934 }
935
ub953_calc_clkout_params(struct ub953_data * priv,unsigned long target_rate,struct ub953_clkout_data * clkout_data)936 static void ub953_calc_clkout_params(struct ub953_data *priv,
937 unsigned long target_rate,
938 struct ub953_clkout_data *clkout_data)
939 {
940 struct device *dev = &priv->client->dev;
941 unsigned long clkout_rate;
942 u64 fc_rate;
943
944 fc_rate = ub953_get_fc_rate(priv);
945
946 if (priv->hw_data->is_ub971) {
947 u8 m, n;
948
949 clkout_rate = ub953_calc_clkout_ub971(priv, target_rate,
950 fc_rate, &m, &n);
951
952 clkout_data->m = m;
953 clkout_data->n = n;
954
955 dev_dbg(dev, "%s %llu * %u / (8 * %u) = %lu (requested %lu)",
956 __func__, fc_rate, m, n, clkout_rate, target_rate);
957 } else {
958 u8 hs_div, m, n;
959
960 clkout_rate = ub953_calc_clkout_ub953(priv, target_rate,
961 fc_rate, &hs_div, &m, &n);
962
963 clkout_data->hs_div = hs_div;
964 clkout_data->m = m;
965 clkout_data->n = n;
966
967 dev_dbg(dev, "%s %llu / %u * %u / %u = %lu (requested %lu)",
968 __func__, fc_rate, hs_div, m, n, clkout_rate,
969 target_rate);
970 }
971
972 clkout_data->rate = clkout_rate;
973 }
974
ub953_write_clkout_regs(struct ub953_data * priv,const struct ub953_clkout_data * clkout_data)975 static int ub953_write_clkout_regs(struct ub953_data *priv,
976 const struct ub953_clkout_data *clkout_data)
977 {
978 u8 clkout_ctrl0, clkout_ctrl1;
979 int ret;
980
981 if (priv->hw_data->is_ub971)
982 clkout_ctrl0 = clkout_data->m;
983 else
984 clkout_ctrl0 = (__ffs(clkout_data->hs_div) << 5) |
985 clkout_data->m;
986
987 clkout_ctrl1 = clkout_data->n;
988
989 ret = ub953_write(priv, UB953_REG_CLKOUT_CTRL0, clkout_ctrl0);
990 if (ret)
991 return ret;
992
993 ret = ub953_write(priv, UB953_REG_CLKOUT_CTRL1, clkout_ctrl1);
994 if (ret)
995 return ret;
996
997 return 0;
998 }
999
ub953_clkout_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1000 static unsigned long ub953_clkout_recalc_rate(struct clk_hw *hw,
1001 unsigned long parent_rate)
1002 {
1003 struct ub953_data *priv = container_of(hw, struct ub953_data, clkout_clk_hw);
1004 struct device *dev = &priv->client->dev;
1005 u8 ctrl0, ctrl1;
1006 u32 mul, div;
1007 u64 fc_rate;
1008 u32 hs_clk_div;
1009 u64 rate;
1010 int ret;
1011
1012 ret = ub953_read(priv, UB953_REG_CLKOUT_CTRL0, &ctrl0);
1013 if (ret) {
1014 dev_err(dev, "Failed to read CLKOUT_CTRL0: %d\n", ret);
1015 return 0;
1016 }
1017
1018 ret = ub953_read(priv, UB953_REG_CLKOUT_CTRL1, &ctrl1);
1019 if (ret) {
1020 dev_err(dev, "Failed to read CLKOUT_CTRL1: %d\n", ret);
1021 return 0;
1022 }
1023
1024 fc_rate = ub953_get_fc_rate(priv);
1025
1026 if (priv->hw_data->is_ub971) {
1027 mul = ctrl0 & 0x1f;
1028 div = ctrl1;
1029
1030 if (div == 0)
1031 return 0;
1032
1033 rate = div_u64(fc_rate * mul, 8 * div);
1034
1035 dev_dbg(dev, "clkout: fc rate %llu, mul %u, div %u = %llu\n",
1036 fc_rate, mul, div, rate);
1037 } else {
1038 mul = ctrl0 & 0x1f;
1039 hs_clk_div = 1 << (ctrl0 >> 5);
1040 div = ctrl1;
1041
1042 if (div == 0)
1043 return 0;
1044
1045 rate = div_u64(div_u64(fc_rate, hs_clk_div) * mul, div);
1046
1047 dev_dbg(dev,
1048 "clkout: fc rate %llu, hs_clk_div %u, mul %u, div %u = %llu\n",
1049 fc_rate, hs_clk_div, mul, div, rate);
1050 }
1051
1052 return rate;
1053 }
1054
ub953_clkout_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)1055 static long ub953_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
1056 unsigned long *parent_rate)
1057 {
1058 struct ub953_data *priv = container_of(hw, struct ub953_data, clkout_clk_hw);
1059 struct ub953_clkout_data clkout_data;
1060
1061 ub953_calc_clkout_params(priv, rate, &clkout_data);
1062
1063 return clkout_data.rate;
1064 }
1065
ub953_clkout_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1066 static int ub953_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
1067 unsigned long parent_rate)
1068 {
1069 struct ub953_data *priv = container_of(hw, struct ub953_data, clkout_clk_hw);
1070 struct ub953_clkout_data clkout_data;
1071
1072 ub953_calc_clkout_params(priv, rate, &clkout_data);
1073
1074 dev_dbg(&priv->client->dev, "%s %lu (requested %lu)\n", __func__,
1075 clkout_data.rate, rate);
1076
1077 return ub953_write_clkout_regs(priv, &clkout_data);
1078 }
1079
1080 static const struct clk_ops ub953_clkout_ops = {
1081 .recalc_rate = ub953_clkout_recalc_rate,
1082 .round_rate = ub953_clkout_round_rate,
1083 .set_rate = ub953_clkout_set_rate,
1084 };
1085
ub953_register_clkout(struct ub953_data * priv)1086 static int ub953_register_clkout(struct ub953_data *priv)
1087 {
1088 struct device *dev = &priv->client->dev;
1089 const struct clk_init_data init = {
1090 .name = kasprintf(GFP_KERNEL, "ds90%s.%s.clk_out",
1091 priv->hw_data->model, dev_name(dev)),
1092 .ops = &ub953_clkout_ops,
1093 };
1094 struct ub953_clkout_data clkout_data;
1095 int ret;
1096
1097 if (!init.name)
1098 return -ENOMEM;
1099
1100 /* Initialize clkout to 25MHz by default */
1101 ub953_calc_clkout_params(priv, UB953_DEFAULT_CLKOUT_RATE, &clkout_data);
1102 ret = ub953_write_clkout_regs(priv, &clkout_data);
1103 if (ret)
1104 return ret;
1105
1106 priv->clkout_clk_hw.init = &init;
1107
1108 ret = devm_clk_hw_register(dev, &priv->clkout_clk_hw);
1109 kfree(init.name);
1110 if (ret)
1111 return dev_err_probe(dev, ret, "Cannot register clock HW\n");
1112
1113 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
1114 &priv->clkout_clk_hw);
1115 if (ret)
1116 return dev_err_probe(dev, ret,
1117 "Cannot add OF clock provider\n");
1118
1119 return 0;
1120 }
1121
ub953_add_i2c_adapter(struct ub953_data * priv)1122 static int ub953_add_i2c_adapter(struct ub953_data *priv)
1123 {
1124 struct device *dev = &priv->client->dev;
1125 struct fwnode_handle *i2c_handle;
1126 int ret;
1127
1128 i2c_handle = device_get_named_child_node(dev, "i2c");
1129 if (!i2c_handle)
1130 return 0;
1131
1132 ret = i2c_atr_add_adapter(priv->plat_data->atr, priv->plat_data->port,
1133 dev, i2c_handle);
1134
1135 fwnode_handle_put(i2c_handle);
1136
1137 if (ret)
1138 return ret;
1139
1140 return 0;
1141 }
1142
1143 static const struct regmap_config ub953_regmap_config = {
1144 .name = "ds90ub953",
1145 .reg_bits = 8,
1146 .val_bits = 8,
1147 .reg_format_endian = REGMAP_ENDIAN_DEFAULT,
1148 .val_format_endian = REGMAP_ENDIAN_DEFAULT,
1149 };
1150
ub953_parse_dt(struct ub953_data * priv)1151 static int ub953_parse_dt(struct ub953_data *priv)
1152 {
1153 struct device *dev = &priv->client->dev;
1154 struct v4l2_fwnode_endpoint vep = {
1155 .bus_type = V4L2_MBUS_CSI2_DPHY,
1156 };
1157 struct fwnode_handle *ep_fwnode;
1158 unsigned char nlanes;
1159 int ret;
1160
1161 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
1162 UB953_PAD_SINK, 0, 0);
1163 if (!ep_fwnode)
1164 return dev_err_probe(dev, -ENOENT, "no endpoint found\n");
1165
1166 ret = v4l2_fwnode_endpoint_parse(ep_fwnode, &vep);
1167
1168 fwnode_handle_put(ep_fwnode);
1169
1170 if (ret)
1171 return dev_err_probe(dev, ret,
1172 "failed to parse sink endpoint data\n");
1173
1174 nlanes = vep.bus.mipi_csi2.num_data_lanes;
1175 if (nlanes != 1 && nlanes != 2 && nlanes != 4)
1176 return dev_err_probe(dev, -EINVAL,
1177 "bad number of data-lanes: %u\n", nlanes);
1178
1179 priv->num_data_lanes = nlanes;
1180
1181 priv->non_continous_clk = vep.bus.mipi_csi2.flags &
1182 V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK;
1183
1184 return 0;
1185 }
1186
ub953_hw_init(struct ub953_data * priv)1187 static int ub953_hw_init(struct ub953_data *priv)
1188 {
1189 struct device *dev = &priv->client->dev;
1190 bool mode_override;
1191 int ret;
1192 u8 v;
1193
1194 ret = ub953_read(priv, UB953_REG_MODE_SEL, &v);
1195 if (ret)
1196 return ret;
1197
1198 if (!(v & UB953_REG_MODE_SEL_MODE_DONE))
1199 return dev_err_probe(dev, -EIO, "Mode value not stabilized\n");
1200
1201 mode_override = v & UB953_REG_MODE_SEL_MODE_OVERRIDE;
1202
1203 switch (v & UB953_REG_MODE_SEL_MODE_MASK) {
1204 case 0:
1205 priv->mode = UB953_MODE_SYNC;
1206 break;
1207 case 2:
1208 priv->mode = UB953_MODE_NONSYNC_EXT;
1209 break;
1210 case 3:
1211 priv->mode = UB953_MODE_NONSYNC_INT;
1212 break;
1213 case 5:
1214 priv->mode = UB953_MODE_DVP;
1215 break;
1216 default:
1217 return dev_err_probe(dev, -EIO,
1218 "Invalid mode in mode register\n");
1219 }
1220
1221 dev_dbg(dev, "mode from %s: %#x\n", mode_override ? "reg" : "strap",
1222 priv->mode);
1223
1224 if (priv->mode != UB953_MODE_SYNC &&
1225 priv->mode != UB953_MODE_NONSYNC_EXT)
1226 return dev_err_probe(dev, -ENODEV,
1227 "Unsupported mode selected: %u\n",
1228 priv->mode);
1229
1230 if (priv->mode == UB953_MODE_NONSYNC_EXT && !priv->clkin)
1231 return dev_err_probe(dev, -EINVAL,
1232 "clkin required for non-sync ext mode\n");
1233
1234 ret = ub953_read(priv, UB953_REG_REV_MASK_ID, &v);
1235 if (ret)
1236 return dev_err_probe(dev, ret, "Failed to read revision");
1237
1238 dev_info(dev, "Found %s rev/mask %#04x\n", priv->hw_data->model, v);
1239
1240 ret = ub953_read(priv, UB953_REG_GENERAL_CFG, &v);
1241 if (ret)
1242 return ret;
1243
1244 dev_dbg(dev, "i2c strap setting %s V\n",
1245 (v & UB953_REG_GENERAL_CFG_I2C_STRAP_MODE) ? "1.8" : "3.3");
1246
1247 ret = ub953_i2c_master_init(priv);
1248 if (ret)
1249 return dev_err_probe(dev, ret, "i2c init failed\n");
1250
1251 v = 0;
1252 v |= priv->non_continous_clk ? 0 : UB953_REG_GENERAL_CFG_CONT_CLK;
1253 v |= (priv->num_data_lanes - 1) <<
1254 UB953_REG_GENERAL_CFG_CSI_LANE_SEL_SHIFT;
1255 v |= UB953_REG_GENERAL_CFG_CRC_TX_GEN_ENABLE;
1256
1257 ret = ub953_write(priv, UB953_REG_GENERAL_CFG, v);
1258 if (ret)
1259 return ret;
1260
1261 return 0;
1262 }
1263
ub953_subdev_init(struct ub953_data * priv)1264 static int ub953_subdev_init(struct ub953_data *priv)
1265 {
1266 struct device *dev = &priv->client->dev;
1267 int ret;
1268
1269 v4l2_i2c_subdev_init(&priv->sd, priv->client, &ub953_subdev_ops);
1270 priv->sd.internal_ops = &ub953_internal_ops;
1271
1272 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1273 V4L2_SUBDEV_FL_STREAMS;
1274 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1275 priv->sd.entity.ops = &ub953_entity_ops;
1276
1277 priv->pads[0].flags = MEDIA_PAD_FL_SINK;
1278 priv->pads[1].flags = MEDIA_PAD_FL_SOURCE;
1279
1280 ret = media_entity_pads_init(&priv->sd.entity, 2, priv->pads);
1281 if (ret)
1282 return dev_err_probe(dev, ret, "Failed to init pads\n");
1283
1284 ret = v4l2_subdev_init_finalize(&priv->sd);
1285 if (ret)
1286 goto err_entity_cleanup;
1287
1288 ret = ub953_v4l2_notifier_register(priv);
1289 if (ret) {
1290 dev_err_probe(dev, ret,
1291 "v4l2 subdev notifier register failed\n");
1292 goto err_free_state;
1293 }
1294
1295 ret = v4l2_async_register_subdev(&priv->sd);
1296 if (ret) {
1297 dev_err_probe(dev, ret, "v4l2_async_register_subdev error\n");
1298 goto err_unreg_notif;
1299 }
1300
1301 return 0;
1302
1303 err_unreg_notif:
1304 ub953_v4l2_notifier_unregister(priv);
1305 err_free_state:
1306 v4l2_subdev_cleanup(&priv->sd);
1307 err_entity_cleanup:
1308 media_entity_cleanup(&priv->sd.entity);
1309
1310 return ret;
1311 }
1312
ub953_subdev_uninit(struct ub953_data * priv)1313 static void ub953_subdev_uninit(struct ub953_data *priv)
1314 {
1315 v4l2_async_unregister_subdev(&priv->sd);
1316 ub953_v4l2_notifier_unregister(priv);
1317 v4l2_subdev_cleanup(&priv->sd);
1318 media_entity_cleanup(&priv->sd.entity);
1319 }
1320
ub953_probe(struct i2c_client * client)1321 static int ub953_probe(struct i2c_client *client)
1322 {
1323 struct device *dev = &client->dev;
1324 struct ub953_data *priv;
1325 int ret;
1326
1327 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1328 if (!priv)
1329 return -ENOMEM;
1330
1331 priv->client = client;
1332
1333 priv->hw_data = device_get_match_data(dev);
1334
1335 priv->plat_data = dev_get_platdata(&client->dev);
1336 if (!priv->plat_data)
1337 return dev_err_probe(dev, -ENODEV, "Platform data missing\n");
1338
1339 mutex_init(&priv->reg_lock);
1340
1341 /*
1342 * Initialize to invalid values so that the first reg writes will
1343 * configure the target.
1344 */
1345 priv->current_indirect_target = 0xff;
1346
1347 priv->regmap = devm_regmap_init_i2c(client, &ub953_regmap_config);
1348 if (IS_ERR(priv->regmap)) {
1349 ret = PTR_ERR(priv->regmap);
1350 dev_err_probe(dev, ret, "Failed to init regmap\n");
1351 goto err_mutex_destroy;
1352 }
1353
1354 priv->clkin = devm_clk_get_optional(dev, "clkin");
1355 if (IS_ERR(priv->clkin)) {
1356 ret = PTR_ERR(priv->clkin);
1357 dev_err_probe(dev, ret, "failed to parse 'clkin'\n");
1358 goto err_mutex_destroy;
1359 }
1360
1361 ret = ub953_parse_dt(priv);
1362 if (ret)
1363 goto err_mutex_destroy;
1364
1365 ret = ub953_hw_init(priv);
1366 if (ret)
1367 goto err_mutex_destroy;
1368
1369 ret = ub953_gpiochip_probe(priv);
1370 if (ret) {
1371 dev_err_probe(dev, ret, "Failed to init gpiochip\n");
1372 goto err_mutex_destroy;
1373 }
1374
1375 ret = ub953_register_clkout(priv);
1376 if (ret) {
1377 dev_err_probe(dev, ret, "Failed to register clkout\n");
1378 goto err_gpiochip_remove;
1379 }
1380
1381 ret = ub953_subdev_init(priv);
1382 if (ret)
1383 goto err_gpiochip_remove;
1384
1385 ret = ub953_add_i2c_adapter(priv);
1386 if (ret) {
1387 dev_err_probe(dev, ret, "failed to add remote i2c adapter\n");
1388 goto err_subdev_uninit;
1389 }
1390
1391 return 0;
1392
1393 err_subdev_uninit:
1394 ub953_subdev_uninit(priv);
1395 err_gpiochip_remove:
1396 ub953_gpiochip_remove(priv);
1397 err_mutex_destroy:
1398 mutex_destroy(&priv->reg_lock);
1399
1400 return ret;
1401 }
1402
ub953_remove(struct i2c_client * client)1403 static void ub953_remove(struct i2c_client *client)
1404 {
1405 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1406 struct ub953_data *priv = sd_to_ub953(sd);
1407
1408 i2c_atr_del_adapter(priv->plat_data->atr, priv->plat_data->port);
1409
1410 ub953_subdev_uninit(priv);
1411
1412 ub953_gpiochip_remove(priv);
1413 mutex_destroy(&priv->reg_lock);
1414 }
1415
1416 static const struct ub953_hw_data ds90ub953_hw = {
1417 .model = "ub953",
1418 };
1419
1420 static const struct ub953_hw_data ds90ub971_hw = {
1421 .model = "ub971",
1422 .is_ub971 = true,
1423 };
1424
1425 static const struct i2c_device_id ub953_id[] = {
1426 { "ds90ub953-q1", (kernel_ulong_t)&ds90ub953_hw },
1427 { "ds90ub971-q1", (kernel_ulong_t)&ds90ub971_hw },
1428 {}
1429 };
1430 MODULE_DEVICE_TABLE(i2c, ub953_id);
1431
1432 static const struct of_device_id ub953_dt_ids[] = {
1433 { .compatible = "ti,ds90ub953-q1", .data = &ds90ub953_hw },
1434 { .compatible = "ti,ds90ub971-q1", .data = &ds90ub971_hw },
1435 {}
1436 };
1437 MODULE_DEVICE_TABLE(of, ub953_dt_ids);
1438
1439 static struct i2c_driver ds90ub953_driver = {
1440 .probe = ub953_probe,
1441 .remove = ub953_remove,
1442 .id_table = ub953_id,
1443 .driver = {
1444 .name = "ds90ub953",
1445 .of_match_table = ub953_dt_ids,
1446 },
1447 };
1448 module_i2c_driver(ds90ub953_driver);
1449
1450 MODULE_LICENSE("GPL");
1451 MODULE_DESCRIPTION("Texas Instruments FPD-Link III/IV CSI-2 Serializers Driver");
1452 MODULE_AUTHOR("Luca Ceresoli <luca@lucaceresoli.net>");
1453 MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>");
1454 MODULE_IMPORT_NS("I2C_ATR");
1455