1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2012 Semihalf.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include "opt_acpi.h"
30 #include "opt_platform.h"
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/bus.h>
36
37 #include <machine/bus.h>
38 #include <machine/machdep.h>
39
40 #include <dev/uart/uart.h>
41 #include <dev/uart/uart_cpu.h>
42 #ifdef FDT
43 #include <dev/uart/uart_cpu_fdt.h>
44 #include <dev/ofw/ofw_bus.h>
45 #endif
46 #include <dev/uart/uart_bus.h>
47 #include "uart_if.h"
48
49 #ifdef DEV_ACPI
50 #include <dev/uart/uart_cpu_acpi.h>
51 #include <contrib/dev/acpica/include/acpi.h>
52 #include <contrib/dev/acpica/include/accommon.h>
53 #include <contrib/dev/acpica/include/actables.h>
54 #endif
55
56 #include <sys/kdb.h>
57
58 #ifdef __aarch64__
59 #define IS_FDT (arm64_bus_method == ARM64_BUS_FDT)
60 #elif defined(FDT)
61 #define IS_FDT 1
62 #else
63 #error Unsupported configuration
64 #endif
65
66 /* PL011 UART registers and masks*/
67 #define UART_DR 0x00 /* Data register */
68 #define DR_FE (1 << 8) /* Framing error */
69 #define DR_PE (1 << 9) /* Parity error */
70 #define DR_BE (1 << 10) /* Break error */
71 #define DR_OE (1 << 11) /* Overrun error */
72
73 #define UART_FR 0x06 /* Flag register */
74 #define FR_RXFE (1 << 4) /* Receive FIFO/reg empty */
75 #define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */
76 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */
77 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */
78
79 #define UART_IBRD 0x09 /* Integer baud rate register */
80 #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */
81
82 #define UART_FBRD 0x0a /* Fractional baud rate register */
83 #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */
84
85 #define UART_LCR_H 0x0b /* Line control register */
86 #define LCR_H_WLEN8 (0x3 << 5)
87 #define LCR_H_WLEN7 (0x2 << 5)
88 #define LCR_H_WLEN6 (0x1 << 5)
89 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */
90 #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */
91 #define LCR_H_EPS (1 << 2) /* Even parity select */
92 #define LCR_H_PEN (1 << 1) /* Parity enable */
93
94 #define UART_CR 0x0c /* Control register */
95 #define CR_RXE (1 << 9) /* Receive enable */
96 #define CR_TXE (1 << 8) /* Transmit enable */
97 #define CR_UARTEN (1 << 0) /* UART enable */
98
99 #define UART_IFLS 0x0d /* FIFO level select register */
100 #define IFLS_RX_SHIFT 3 /* RX level in bits [5:3] */
101 #define IFLS_TX_SHIFT 0 /* TX level in bits [2:0] */
102 #define IFLS_MASK 0x07 /* RX/TX level is 3 bits */
103 #define IFLS_LVL_1_8th 0 /* Interrupt at 1/8 full */
104 #define IFLS_LVL_2_8th 1 /* Interrupt at 1/4 full */
105 #define IFLS_LVL_4_8th 2 /* Interrupt at 1/2 full */
106 #define IFLS_LVL_6_8th 3 /* Interrupt at 3/4 full */
107 #define IFLS_LVL_7_8th 4 /* Interrupt at 7/8 full */
108
109 #define UART_IMSC 0x0e /* Interrupt mask set/clear register */
110 #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */
111
112 #define UART_RIS 0x0f /* Raw interrupt status register */
113 #define UART_RXREADY (1 << 4) /* RX buffer full */
114 #define UART_TXEMPTY (1 << 5) /* TX buffer empty */
115 #define RIS_RTIM (1 << 6) /* Receive timeout */
116 #define RIS_FE (1 << 7) /* Framing error interrupt status */
117 #define RIS_PE (1 << 8) /* Parity error interrupt status */
118 #define RIS_BE (1 << 9) /* Break error interrupt status */
119 #define RIS_OE (1 << 10) /* Overrun interrupt status */
120
121 #define UART_MIS 0x10 /* Masked interrupt status register */
122 #define UART_ICR 0x11 /* Interrupt clear register */
123
124 #define UART_PIDREG_0 0x3f8 /* Peripheral ID register 0 */
125 #define UART_PIDREG_1 0x3f9 /* Peripheral ID register 1 */
126 #define UART_PIDREG_2 0x3fa /* Peripheral ID register 2 */
127 #define UART_PIDREG_3 0x3fb /* Peripheral ID register 3 */
128
129 /*
130 * The hardware FIFOs are 16 bytes each on rev 2 and earlier hardware, 32 bytes
131 * on rev 3 and later. We configure them to interrupt when 3/4 full/empty. For
132 * RX we set the size to the full hardware capacity so that the uart core
133 * allocates enough buffer space to hold a complete fifo full of incoming data.
134 * For TX, we need to limit the size to the capacity we know will be available
135 * when the interrupt occurs; uart_core will feed exactly that many bytes to
136 * uart_pl011_bus_transmit() which must consume them all.
137 */
138 #define FIFO_RX_SIZE_R2 16
139 #define FIFO_TX_SIZE_R2 12
140 #define FIFO_RX_SIZE_R3 32
141 #define FIFO_TX_SIZE_R3 24
142 #define FIFO_IFLS_BITS ((IFLS_LVL_6_8th << IFLS_RX_SHIFT) | (IFLS_LVL_2_8th))
143
144 /*
145 * FIXME: actual register size is SoC-dependent, we need to handle it
146 */
147 #define __uart_getreg(bas, reg) \
148 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
149 #define __uart_setreg(bas, reg, value) \
150 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
151
152 /*
153 * Low-level UART interface.
154 */
155 static int uart_pl011_probe(struct uart_bas *bas);
156 static void uart_pl011_init(struct uart_bas *bas, int, int, int, int);
157 static void uart_pl011_term(struct uart_bas *bas);
158 static void uart_pl011_putc(struct uart_bas *bas, int);
159 static int uart_pl011_rxready(struct uart_bas *bas);
160 static int uart_pl011_getc(struct uart_bas *bas, struct mtx *);
161
162 static struct uart_ops uart_pl011_ops = {
163 .probe = uart_pl011_probe,
164 .init = uart_pl011_init,
165 .term = uart_pl011_term,
166 .putc = uart_pl011_putc,
167 .rxready = uart_pl011_rxready,
168 .getc = uart_pl011_getc,
169 };
170
171 static int
uart_pl011_probe(struct uart_bas * bas)172 uart_pl011_probe(struct uart_bas *bas)
173 {
174
175 return (0);
176 }
177
178 static void
uart_pl011_param(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)179 uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
180 int parity)
181 {
182 uint32_t ctrl, line;
183 uint32_t baud;
184
185 /*
186 * Zero all settings to make sure
187 * UART is disabled and not configured
188 */
189 ctrl = line = 0x0;
190 __uart_setreg(bas, UART_CR, ctrl);
191
192 /* As we know UART is disabled we may setup the line */
193 switch (databits) {
194 case 7:
195 line |= LCR_H_WLEN7;
196 break;
197 case 6:
198 line |= LCR_H_WLEN6;
199 break;
200 case 8:
201 default:
202 line |= LCR_H_WLEN8;
203 break;
204 }
205
206 if (stopbits == 2)
207 line |= LCR_H_STP2;
208 else
209 line &= ~LCR_H_STP2;
210
211 if (parity)
212 line |= LCR_H_PEN;
213 else
214 line &= ~LCR_H_PEN;
215 line |= LCR_H_FEN;
216
217 /* Configure the rest */
218 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN);
219
220 if (bas->rclk != 0 && baudrate != 0) {
221 baud = bas->rclk * 4 / baudrate;
222 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT);
223 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC);
224 }
225
226 /* Add config. to line before reenabling UART */
227 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) &
228 ~0xff) | line);
229
230 /* Set rx and tx fifo levels. */
231 __uart_setreg(bas, UART_IFLS, FIFO_IFLS_BITS);
232
233 __uart_setreg(bas, UART_CR, ctrl);
234
235 /*
236 * Loader tells us to infer the rclk when it sets xo to 0 in
237 * hw.uart.console. The APCI SPCR code does likewise. We know the
238 * baudrate was set by the firmware, so calculate rclk from baudrate and
239 * the divisor register. If 'div' is actually 0, the resulting 0 value
240 * will have us fall back to other rclk methods. This method should be
241 * good to 5% or better because the error in baud rates needs to be
242 * below this for devices to communicate.
243 */
244 if (bas->rclk == 0 && baudrate > 0 && bas->rclk_guess) {
245 uint32_t div;
246
247 div = ((__uart_getreg(bas, UART_IBRD) & IBRD_BDIVINT) << 6) |
248 (__uart_getreg(bas, UART_FBRD) & FBRD_BDIVFRAC);
249 bas->rclk = (div * baudrate) / 4;
250 }
251
252 }
253
254 static void
uart_pl011_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)255 uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
256 int parity)
257 {
258 /* Mask all interrupts */
259 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) &
260 ~IMSC_MASK_ALL);
261
262 uart_pl011_param(bas, baudrate, databits, stopbits, parity);
263 }
264
265 static void
uart_pl011_term(struct uart_bas * bas)266 uart_pl011_term(struct uart_bas *bas)
267 {
268 }
269
270 #if CHECK_EARLY_PRINTF(pl011)
271 static void
uart_pl011_early_putc(int c)272 uart_pl011_early_putc(int c)
273 {
274 volatile uint32_t *fr = (uint32_t *)(socdev_va + UART_FR * 4);
275 volatile uint32_t *dr = (uint32_t *)(socdev_va + UART_DR * 4);
276
277 while ((*fr & FR_TXFF) != 0)
278 ;
279 *dr = c & 0xff;
280 }
281 early_putc_t *early_putc = uart_pl011_early_putc;
282 #endif /* CHECK_EARLY_PRINTF */
283
284 static void
uart_pl011_putc(struct uart_bas * bas,int c)285 uart_pl011_putc(struct uart_bas *bas, int c)
286 {
287
288 /* Wait when TX FIFO full. Push character otherwise. */
289 while (__uart_getreg(bas, UART_FR) & FR_TXFF)
290 ;
291 __uart_setreg(bas, UART_DR, c & 0xff);
292 }
293
294 static int
uart_pl011_rxready(struct uart_bas * bas)295 uart_pl011_rxready(struct uart_bas *bas)
296 {
297
298 return !(__uart_getreg(bas, UART_FR) & FR_RXFE);
299 }
300
301 static int
uart_pl011_getc(struct uart_bas * bas,struct mtx * hwmtx)302 uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx)
303 {
304 int c;
305
306 while (!uart_pl011_rxready(bas))
307 ;
308 c = __uart_getreg(bas, UART_DR) & 0xff;
309
310 return (c);
311 }
312
313 /*
314 * High-level UART interface.
315 */
316 struct uart_pl011_softc {
317 struct uart_softc base;
318 uint16_t imsc; /* Interrupt mask */
319 };
320
321 static int uart_pl011_bus_attach(struct uart_softc *);
322 static int uart_pl011_bus_detach(struct uart_softc *);
323 static int uart_pl011_bus_flush(struct uart_softc *, int);
324 static int uart_pl011_bus_getsig(struct uart_softc *);
325 static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t);
326 static int uart_pl011_bus_ipend(struct uart_softc *);
327 static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int);
328 static int uart_pl011_bus_probe(struct uart_softc *);
329 static int uart_pl011_bus_receive(struct uart_softc *);
330 static int uart_pl011_bus_setsig(struct uart_softc *, int);
331 static int uart_pl011_bus_transmit(struct uart_softc *);
332 static void uart_pl011_bus_grab(struct uart_softc *);
333 static void uart_pl011_bus_ungrab(struct uart_softc *);
334
335 static kobj_method_t uart_pl011_methods[] = {
336 KOBJMETHOD(uart_attach, uart_pl011_bus_attach),
337 KOBJMETHOD(uart_detach, uart_pl011_bus_detach),
338 KOBJMETHOD(uart_flush, uart_pl011_bus_flush),
339 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig),
340 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl),
341 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend),
342 KOBJMETHOD(uart_param, uart_pl011_bus_param),
343 KOBJMETHOD(uart_probe, uart_pl011_bus_probe),
344 KOBJMETHOD(uart_receive, uart_pl011_bus_receive),
345 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig),
346 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit),
347 KOBJMETHOD(uart_grab, uart_pl011_bus_grab),
348 KOBJMETHOD(uart_ungrab, uart_pl011_bus_ungrab),
349 { 0, 0 }
350 };
351
352 static struct uart_class uart_pl011_class = {
353 "pl011",
354 uart_pl011_methods,
355 sizeof(struct uart_pl011_softc),
356 .uc_ops = &uart_pl011_ops,
357 .uc_range = 0x48,
358 .uc_rclk = 0,
359 .uc_rshift = 2
360 };
361 UART_CLASS(uart_pl011_class);
362
363 #ifdef FDT
364 static struct ofw_compat_data fdt_compat_data[] = {
365 {"arm,pl011", (uintptr_t)&uart_pl011_class},
366 {NULL, (uintptr_t)NULL},
367 };
368 UART_FDT_CLASS_AND_DEVICE(fdt_compat_data);
369 #endif
370
371 #ifdef DEV_ACPI
372 static struct acpi_uart_compat_data acpi_compat_data[] = {
373 {"ARMH0011", &uart_pl011_class, ACPI_DBG2_ARM_PL011, 2, 0, 0, UART_F_IGNORE_SPCR_REGSHFT, "uart pl011"},
374 {"ARMHB000", &uart_pl011_class, ACPI_DBG2_ARM_SBSA_GENERIC, 2, 0, 0, UART_F_IGNORE_SPCR_REGSHFT, "uart pl011"},
375 {"ARMHB000", &uart_pl011_class, ACPI_DBG2_ARM_SBSA_32BIT, 2, 0, 0, UART_F_IGNORE_SPCR_REGSHFT, "uart pl011"},
376 {NULL, NULL, 0, 0, 0, 0, 0, NULL},
377 };
378 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data);
379 #endif
380
381 static int
uart_pl011_bus_attach(struct uart_softc * sc)382 uart_pl011_bus_attach(struct uart_softc *sc)
383 {
384 struct uart_pl011_softc *psc;
385 struct uart_bas *bas;
386
387 psc = (struct uart_pl011_softc *)sc;
388 bas = &sc->sc_bas;
389
390 /* Enable interrupts */
391 psc->imsc = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY);
392 __uart_setreg(bas, UART_IMSC, psc->imsc);
393
394 /* Clear interrupts */
395 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL);
396
397 return (0);
398 }
399
400 static int
uart_pl011_bus_detach(struct uart_softc * sc)401 uart_pl011_bus_detach(struct uart_softc *sc)
402 {
403
404 return (0);
405 }
406
407 static int
uart_pl011_bus_flush(struct uart_softc * sc,int what)408 uart_pl011_bus_flush(struct uart_softc *sc, int what)
409 {
410
411 return (0);
412 }
413
414 static int
uart_pl011_bus_getsig(struct uart_softc * sc)415 uart_pl011_bus_getsig(struct uart_softc *sc)
416 {
417
418 return (0);
419 }
420
421 static int
uart_pl011_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)422 uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
423 {
424 int error;
425
426 error = 0;
427 uart_lock(sc->sc_hwmtx);
428 switch (request) {
429 case UART_IOCTL_BREAK:
430 break;
431 case UART_IOCTL_BAUD:
432 *(int*)data = 115200;
433 break;
434 default:
435 error = EINVAL;
436 break;
437 }
438 uart_unlock(sc->sc_hwmtx);
439
440 return (error);
441 }
442
443 static int
uart_pl011_bus_ipend(struct uart_softc * sc)444 uart_pl011_bus_ipend(struct uart_softc *sc)
445 {
446 struct uart_pl011_softc *psc;
447 struct uart_bas *bas;
448 uint32_t ints;
449 int ipend;
450
451 psc = (struct uart_pl011_softc *)sc;
452 bas = &sc->sc_bas;
453
454 uart_lock(sc->sc_hwmtx);
455 ints = __uart_getreg(bas, UART_MIS);
456 ipend = 0;
457
458 if (ints & (UART_RXREADY | RIS_RTIM))
459 ipend |= SER_INT_RXREADY;
460 if (ints & RIS_BE)
461 ipend |= SER_INT_BREAK;
462 if (ints & RIS_OE)
463 ipend |= SER_INT_OVERRUN;
464 if (ints & UART_TXEMPTY) {
465 if (sc->sc_txbusy)
466 ipend |= SER_INT_TXIDLE;
467
468 /* Disable TX interrupt */
469 __uart_setreg(bas, UART_IMSC, psc->imsc & ~UART_TXEMPTY);
470 }
471
472 uart_unlock(sc->sc_hwmtx);
473
474 return (ipend);
475 }
476
477 static int
uart_pl011_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)478 uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits,
479 int stopbits, int parity)
480 {
481
482 uart_lock(sc->sc_hwmtx);
483 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity);
484 uart_unlock(sc->sc_hwmtx);
485
486 return (0);
487 }
488
489 #ifdef FDT
490 static int
uart_pl011_bus_hwrev_fdt(struct uart_softc * sc)491 uart_pl011_bus_hwrev_fdt(struct uart_softc *sc)
492 {
493 pcell_t node;
494 uint32_t periphid;
495
496 /*
497 * The FIFO sizes vary depending on hardware; rev 2 and below have 16
498 * byte FIFOs, rev 3 and up are 32 byte. The hardware rev is in the
499 * primecell periphid register, but we get a bit of drama, as always,
500 * with the bcm2835 (rpi), which claims to be rev 3, but has 16 byte
501 * FIFOs. We check for both the old freebsd-historic and the proper
502 * bindings-defined compatible strings for bcm2835, and also check the
503 * workaround the linux drivers use for rpi3, which is to override the
504 * primecell periphid register value with a property.
505 */
506 if (ofw_bus_is_compatible(sc->sc_dev, "brcm,bcm2835-pl011") ||
507 ofw_bus_is_compatible(sc->sc_dev, "broadcom,bcm2835-uart")) {
508 return (2);
509 } else {
510 node = ofw_bus_get_node(sc->sc_dev);
511 if (OF_getencprop(node, "arm,primecell-periphid", &periphid,
512 sizeof(periphid)) > 0) {
513 return ((periphid >> 20) & 0x0f);
514 }
515 }
516
517 return (-1);
518 }
519 #endif
520
521 static int
uart_pl011_bus_probe(struct uart_softc * sc)522 uart_pl011_bus_probe(struct uart_softc *sc)
523 {
524 int hwrev;
525
526 hwrev = -1;
527 #ifdef FDT
528 if (IS_FDT)
529 hwrev = uart_pl011_bus_hwrev_fdt(sc);
530 #endif
531 if (hwrev < 0)
532 hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4;
533
534 if (hwrev <= 2) {
535 sc->sc_rxfifosz = FIFO_RX_SIZE_R2;
536 sc->sc_txfifosz = FIFO_TX_SIZE_R2;
537 } else {
538 sc->sc_rxfifosz = FIFO_RX_SIZE_R3;
539 sc->sc_txfifosz = FIFO_TX_SIZE_R3;
540 }
541
542 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)");
543
544 return (0);
545 }
546
547 static int
uart_pl011_bus_receive(struct uart_softc * sc)548 uart_pl011_bus_receive(struct uart_softc *sc)
549 {
550 struct uart_bas *bas;
551 uint32_t ints, xc;
552 int rx;
553
554 bas = &sc->sc_bas;
555 uart_lock(sc->sc_hwmtx);
556
557 for (;;) {
558 ints = __uart_getreg(bas, UART_FR);
559 if (ints & FR_RXFE)
560 break;
561 if (uart_rx_full(sc)) {
562 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
563 break;
564 }
565
566 xc = __uart_getreg(bas, UART_DR);
567 rx = xc & 0xff;
568
569 if (xc & DR_FE)
570 rx |= UART_STAT_FRAMERR;
571 if (xc & DR_PE)
572 rx |= UART_STAT_PARERR;
573
574 uart_rx_put(sc, rx);
575 }
576
577 uart_unlock(sc->sc_hwmtx);
578
579 return (0);
580 }
581
582 static int
uart_pl011_bus_setsig(struct uart_softc * sc,int sig)583 uart_pl011_bus_setsig(struct uart_softc *sc, int sig)
584 {
585
586 return (0);
587 }
588
589 static int
uart_pl011_bus_transmit(struct uart_softc * sc)590 uart_pl011_bus_transmit(struct uart_softc *sc)
591 {
592 struct uart_pl011_softc *psc;
593 struct uart_bas *bas;
594 int i;
595
596 psc = (struct uart_pl011_softc *)sc;
597 bas = &sc->sc_bas;
598 uart_lock(sc->sc_hwmtx);
599
600 for (i = 0; i < sc->sc_txdatasz; i++) {
601 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]);
602 uart_barrier(bas);
603 }
604
605 /* Mark busy and enable TX interrupt */
606 sc->sc_txbusy = 1;
607 __uart_setreg(bas, UART_IMSC, psc->imsc);
608
609 uart_unlock(sc->sc_hwmtx);
610
611 return (0);
612 }
613
614 static void
uart_pl011_bus_grab(struct uart_softc * sc)615 uart_pl011_bus_grab(struct uart_softc *sc)
616 {
617 struct uart_pl011_softc *psc;
618 struct uart_bas *bas;
619
620 psc = (struct uart_pl011_softc *)sc;
621 bas = &sc->sc_bas;
622
623 /* Disable interrupts on switch to polling */
624 uart_lock(sc->sc_hwmtx);
625 __uart_setreg(bas, UART_IMSC, psc->imsc & ~IMSC_MASK_ALL);
626 uart_unlock(sc->sc_hwmtx);
627 }
628
629 static void
uart_pl011_bus_ungrab(struct uart_softc * sc)630 uart_pl011_bus_ungrab(struct uart_softc *sc)
631 {
632 struct uart_pl011_softc *psc;
633 struct uart_bas *bas;
634
635 psc = (struct uart_pl011_softc *)sc;
636 bas = &sc->sc_bas;
637
638 /* Switch to using interrupts while not grabbed */
639 uart_lock(sc->sc_hwmtx);
640 __uart_setreg(bas, UART_IMSC, psc->imsc);
641 uart_unlock(sc->sc_hwmtx);
642 }
643