1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // ALSA SoC Texas Instruments TAC5XX2 Audio Smart Amplifier
4 //
5 // Copyright (C) 2025 Texas Instruments Incorporated
6 // https://www.ti.com
7 //
8 // Author: Niranjan H Y <niranjan.hy@ti.com>
9
10 #include <linux/err.h>
11 #include <linux/firmware.h>
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/pm.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/soundwire/sdw.h>
19 #include <linux/soundwire/sdw_registers.h>
20 #include <linux/soundwire/sdw_type.h>
21 #include <linux/time.h>
22 #include <linux/unaligned.h>
23 #include <sound/pcm_params.h>
24 #include <sound/sdw.h>
25 #include <sound/soc.h>
26 #include <sound/tlv.h>
27 #include <sound/sdca_asoc.h>
28 #include <sound/sdca_function.h>
29 #include <sound/sdca_regmap.h>
30 #include <sound/jack.h>
31
32 #include "tac5xx2.h"
33
34 #define TAC5XX2_PROBE_TIMEOUT_MS 3000
35 #define TAC5XX2_FW_CACHE_TIMEOUT_MS 300
36
37 #define TAC5XX2_DEVICE_RATES (SNDRV_PCM_RATE_44100 | \
38 SNDRV_PCM_RATE_48000 | \
39 SNDRV_PCM_RATE_96000 | \
40 SNDRV_PCM_RATE_88200)
41 #define TAC5XX2_DEVICE_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
42 SNDRV_PCM_FMTBIT_S24_LE | \
43 SNDRV_PCM_FMTBIT_S32_LE)
44 /* Define channel constants */
45 #define TAC_CHANNEL_LEFT 1
46 #define TAC_CHANNEL_RIGHT 2
47 #define TAC_JACK_MONO_CS 2
48
49 #define TAC_MUTE_REG(func, fu, ch) \
50 SDW_SDCA_CTL(TAC_FUNCTION_ID_##func, TAC_SDCA_ENT_##fu, \
51 TAC_SDCA_CHANNEL_MUTE, TAC_CHANNEL_##ch)
52 #define TAC_USAGE_REG(func, ent) \
53 SDW_SDCA_CTL(TAC_FUNCTION_ID_##func, TAC_SDCA_ENT_##ent, \
54 TAC_SDCA_CTL_USAGE, 0)
55 #define TAC_XU_BYPASS_REG(func, xu) \
56 SDW_SDCA_CTL(TAC_FUNCTION_ID_##func, TAC_SDCA_ENT_##xu, \
57 TAC_SDCA_CTL_XU_BYPASS, 0)
58
59 /* mute registers */
60 #define FU21_L_MUTE_REG TAC_MUTE_REG(SA, FU21, LEFT)
61 #define FU21_R_MUTE_REG TAC_MUTE_REG(SA, FU21, RIGHT)
62 #define FU23_L_MUTE_REG TAC_MUTE_REG(SA, FU23, LEFT)
63 #define FU23_R_MUTE_REG TAC_MUTE_REG(SA, FU23, RIGHT)
64 #define FU26_MUTE_REG TAC_MUTE_REG(SA, FU26, LEFT)
65 #define FU11_L_MUTE_REG TAC_MUTE_REG(SM, FU11, LEFT)
66 #define FU11_R_MUTE_REG TAC_MUTE_REG(SM, FU11, RIGHT)
67 #define FU113_L_MUTE_REG TAC_MUTE_REG(SM, FU113, LEFT)
68 #define FU113_R_MUTE_REG TAC_MUTE_REG(SM, FU113, RIGHT)
69 #define FU41_L_MUTE_REG TAC_MUTE_REG(UAJ, FU41, LEFT)
70 #define FU41_R_MUTE_REG TAC_MUTE_REG(UAJ, FU41, RIGHT)
71 #define FU36_MUTE_REG TAC_MUTE_REG(UAJ, FU36, RIGHT)
72
73 /* it/ot usage */
74 #define IT11_USAGE_REG TAC_USAGE_REG(SM, IT11)
75 #define IT41_USAGE_REG TAC_USAGE_REG(UAJ, IT41)
76 #define IT33_USAGE_REG TAC_USAGE_REG(UAJ, IT33)
77 #define OT113_USAGE_REG TAC_USAGE_REG(SM, OT113)
78 #define OT45_USAGE_REG TAC_USAGE_REG(UAJ, OT45)
79 #define OT36_USAGE_REG TAC_USAGE_REG(UAJ, OT36)
80
81 /* xu bypass */
82 #define XU12_BYPASS_REG TAC_XU_BYPASS_REG(SM, XU12)
83 #define XU42_BYPASS_REG TAC_XU_BYPASS_REG(UAJ, XU42)
84
85 #define TAC_DSP_ALGO_STATUS TAC_REG_SDW(0, 3, 12)
86 #define TAC_DSP_ALGO_STATUS_RUNNING 0x20
87 #define TAC_FW_HDR_SIZE 88
88 #define TAC_FW_FILE_HDR 20
89 #define TAC_MAX_FW_CHUNKS 512
90
91 #define TAC_UAJ_PREP_CONNECTED 0xff
92 #define TAC_UAJ_PREP_DISCONNECTED 0xdf
93
94 struct tac_fw_hdr {
95 u32 size;
96 u32 version_offset;
97 u32 plt_id;
98 u32 ppc3_ver;
99 u64 timestamp;
100 u8 ddc_name[64];
101 };
102
103 /* Firmware file/chunk structure */
104 struct tac_fw_file {
105 u32 vendor_id;
106 u32 file_id;
107 u32 version;
108 u32 length;
109 u32 dest_addr;
110 u8 *fw_data;
111 };
112
113 /* TLV for volume control */
114 static const DECLARE_TLV_DB_SCALE(tac5xx2_amp_tlv, 0, 50, 0);
115 static const DECLARE_TLV_DB_SCALE(tac5xx2_dvc_tlv, -7200, 50, 0);
116
117 /* Q7.8 volume control parameters: range -72dB to +6dB, step 0.5dB */
118 #define TAC_DVC_STEP 128 /* 0.5 dB in Q7.8 format */
119 #define TAC_DVC_MIN (-144) /* -72 dB / 0.5 dB step */
120 #define TAC_DVC_MAX 12 /* +6 dB / 0.5 dB step */
121
122 /* TAC-specific stereo volume control macro using SDW_SDCA_CTL (single control for L/R) */
123 #define TAC_DOUBLE_Q78_TLV(name, func_id, ent_id) \
124 SDCA_DOUBLE_Q78_TLV(name, \
125 SDW_SDCA_CTL(TAC_FUNCTION_ID_##func_id, TAC_SDCA_ENT_##ent_id, \
126 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_LEFT), \
127 SDW_SDCA_CTL(TAC_FUNCTION_ID_##func_id, TAC_SDCA_ENT_##ent_id, \
128 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_RIGHT), \
129 TAC_DVC_MIN, TAC_DVC_MAX, TAC_DVC_STEP, tac5xx2_dvc_tlv)
130
131 struct tac5xx2_prv {
132 struct snd_soc_component *component;
133 struct sdw_slave *sdw_peripheral;
134 struct sdca_function_data *sa_func_data;
135 struct sdca_function_data *sm_func_data;
136 struct sdca_function_data *uaj_func_data;
137 struct sdca_function_data *hid_func_data;
138 enum sdw_slave_status status;
139 struct regmap *regmap;
140 struct device *dev;
141 bool hw_init;
142 bool first_hw_init_done;
143 u32 part_id;
144 u32 rev_id;
145 struct snd_soc_jack *hs_jack;
146 int jack_type;
147 /* Custom fw binary. UMP File Download is not used. */
148 unsigned int fw_file_cnt;
149 struct tac_fw_file *fw_files;
150 struct completion fw_caching_complete;
151 bool fw_dl_success;
152 u8 fw_binaryname[64];
153 };
154
155 static const struct reg_default tac_reg_default[] = {
156 {TAC_SW_RESET, 0x0},
157 {TAC_SLEEP_MODEZ, 0x0},
158 {TAC_FEATURE_PDZ, 0x0},
159 {TAC_TX_CH_EN, 0xf0},
160 {TAC_REG_SDW(0, 0, 0x5), 0xcf},
161 {TAC_REG_SDW(0, 0, 0x6), 0xa},
162 {TAC_REG_SDW(0, 0, 0x7), 0x0},
163 {TAC_REG_SDW(0, 0, 0x8), 0xfe},
164 {TAC_REG_SDW(0, 0, 0x9), 0x9},
165 {TAC_REG_SDW(0, 0, 0xa), 0x28},
166 {TAC_REG_SDW(0, 0, 0xb), 0x1},
167 {TAC_REG_SDW(0, 0, 0xc), 0x11},
168 {TAC_REG_SDW(0, 0, 0xd), 0x11},
169 {TAC_REG_SDW(0, 0, 0xe), 0x61},
170 {TAC_REG_SDW(0, 0, 0xf), 0x0},
171 {TAC_REG_SDW(0, 0, 0x10), 0x50},
172 {TAC_REG_SDW(0, 0, 0x11), 0x70},
173 {TAC_REG_SDW(0, 0, 0x12), 0x60},
174 {TAC_REG_SDW(0, 0, 0x13), 0x28},
175 {TAC_REG_SDW(0, 0, 0x14), 0x0},
176 {TAC_REG_SDW(0, 0, 0x15), 0x18},
177 {TAC_REG_SDW(0, 0, 0x16), 0x20},
178 {TAC_REG_SDW(0, 0, 0x17), 0x0},
179 {TAC_REG_SDW(0, 0, 0x18), 0x18},
180 {TAC_REG_SDW(0, 0, 0x19), 0x54},
181 {TAC_REG_SDW(0, 0, 0x1a), 0x8},
182 {TAC_REG_SDW(0, 0, 0x1b), 0x0},
183 {TAC_REG_SDW(0, 0, 0x1c), 0x30},
184 {TAC_REG_SDW(0, 0, 0x1d), 0x0},
185 {TAC_REG_SDW(0, 0, 0x1e), 0x0},
186 {TAC_REG_SDW(0, 0, 0x1f), 0x0},
187 {TAC_REG_SDW(0, 0, 0x20), 0x0},
188 {TAC_REG_SDW(0, 0, 0x21), 0x20},
189 {TAC_REG_SDW(0, 0, 0x22), 0x21},
190 {TAC_REG_SDW(0, 0, 0x23), 0x22},
191 {TAC_REG_SDW(0, 0, 0x24), 0x23},
192 {TAC_REG_SDW(0, 0, 0x25), 0x4},
193 {TAC_REG_SDW(0, 0, 0x26), 0x5},
194 {TAC_REG_SDW(0, 0, 0x27), 0x6},
195 {TAC_REG_SDW(0, 0, 0x28), 0x7},
196 {TAC_REG_SDW(0, 0, 0x29), 0x0},
197 {TAC_REG_SDW(0, 0, 0x2a), 0x0},
198 {TAC_REG_SDW(0, 0, 0x2b), 0x0},
199 {TAC_REG_SDW(0, 0, 0x2c), 0x20},
200 {TAC_REG_SDW(0, 0, 0x2d), 0x21},
201 {TAC_REG_SDW(0, 0, 0x2e), 0x2},
202 {TAC_REG_SDW(0, 0, 0x2f), 0x3},
203 {TAC_REG_SDW(0, 0, 0x30), 0x4},
204 {TAC_REG_SDW(0, 0, 0x31), 0x5},
205 {TAC_REG_SDW(0, 0, 0x32), 0x6},
206 {TAC_REG_SDW(0, 0, 0x33), 0x7},
207 {TAC_REG_SDW(0, 0, 0x34), 0x0},
208 {TAC_REG_SDW(0, 0, 0x35), 0x90},
209 {TAC_REG_SDW(0, 0, 0x36), 0x80},
210 {TAC_REG_SDW(0, 0, 0x37), 0x0},
211 {TAC_REG_SDW(0, 0, 0x39), 0x0},
212 {TAC_REG_SDW(0, 0, 0x3a), 0x90},
213 {TAC_REG_SDW(0, 0, 0x3b), 0x80},
214 {TAC_REG_SDW(0, 0, 0x3c), 0x0},
215 {TAC_REG_SDW(0, 0, 0x3e), 0x0},
216 {TAC_REG_SDW(0, 0, 0x3f), 0x90},
217 {TAC_REG_SDW(0, 0, 0x40), 0x80},
218 {TAC_REG_SDW(0, 0, 0x41), 0x0},
219 {TAC_REG_SDW(0, 0, 0x43), 0x90},
220 {TAC_REG_SDW(0, 0, 0x44), 0x80},
221 {TAC_REG_SDW(0, 0, 0x45), 0x0},
222 {TAC_REG_SDW(0, 0, 0x47), 0x90},
223 {TAC_REG_SDW(0, 0, 0x48), 0x80},
224 {TAC_REG_SDW(0, 0, 0x49), 0x0},
225 {TAC_REG_SDW(0, 0, 0x4b), 0x90},
226 {TAC_REG_SDW(0, 0, 0x4c), 0x80},
227 {TAC_REG_SDW(0, 0, 0x4d), 0x0},
228 {TAC_REG_SDW(0, 0, 0x4f), 0x31},
229 {TAC_REG_SDW(0, 0, 0x50), 0x0},
230 {TAC_REG_SDW(0, 0, 0x51), 0x0},
231 {TAC_REG_SDW(0, 0, 0x52), 0x90},
232 {TAC_REG_SDW(0, 0, 0x53), 0x80},
233 {TAC_REG_SDW(0, 0, 0x55), 0x90},
234 {TAC_REG_SDW(0, 0, 0x56), 0x80},
235 {TAC_REG_SDW(0, 0, 0x58), 0x90},
236 {TAC_REG_SDW(0, 0, 0x59), 0x80},
237 {TAC_REG_SDW(0, 0, 0x5b), 0x90},
238 {TAC_REG_SDW(0, 0, 0x5c), 0x80},
239 {TAC_REG_SDW(0, 0, 0x5e), 0x8},
240 {TAC_REG_SDW(0, 0, 0x5f), 0x8},
241 {TAC_REG_SDW(0, 0, 0x60), 0x0},
242 {TAC_REG_SDW(0, 0, 0x61), 0x0},
243 {TAC_REG_SDW(0, 0, 0x62), 0xff},
244 {TAC_REG_SDW(0, 0, 0x63), 0xc0},
245 {TAC_REG_SDW(0, 0, 0x64), 0x5},
246 {TAC_REG_SDW(0, 0, 0x65), 0x3},
247 {TAC_REG_SDW(0, 0, 0x66), 0x0},
248 {TAC_REG_SDW(0, 0, 0x67), 0x0},
249 {TAC_REG_SDW(0, 0, 0x68), 0x0},
250 {TAC_REG_SDW(0, 0, 0x69), 0x8},
251 {TAC_REG_SDW(0, 0, 0x6a), 0x0},
252 {TAC_REG_SDW(0, 0, 0x6b), 0xa0},
253 {TAC_REG_SDW(0, 0, 0x6c), 0x18},
254 {TAC_REG_SDW(0, 0, 0x6d), 0x18},
255 {TAC_REG_SDW(0, 0, 0x6e), 0x18},
256 {TAC_REG_SDW(0, 0, 0x6f), 0x18},
257 {TAC_REG_SDW(0, 0, 0x70), 0x88},
258 {TAC_REG_SDW(0, 0, 0x71), 0xff},
259 {TAC_REG_SDW(0, 0, 0x72), 0x0},
260 {TAC_REG_SDW(0, 0, 0x73), 0x31},
261 {TAC_REG_SDW(0, 0, 0x74), 0xc0},
262 {TAC_REG_SDW(0, 0, 0x75), 0x0},
263 {TAC_REG_SDW(0, 0, 0x76), 0x0},
264 {TAC_REG_SDW(0, 0, 0x77), 0x0},
265 {TAC_REG_SDW(0, 0, 0x78), 0x0},
266 {TAC_REG_SDW(0, 0, 0x7b), 0x0},
267 {TAC_REG_SDW(0, 0, 0x7c), 0xd0},
268 {TAC_REG_SDW(0, 0, 0x7e), 0x0},
269 {TAC_REG_SDW(0, 1, 0x1), 0x0},
270 {TAC_REG_SDW(0, 1, 0x2), 0x0},
271 {TAC_REG_SDW(0, 1, 0x3), 0x0},
272 {TAC_REG_SDW(0, 1, 0x4), 0x4},
273 {TAC_REG_SDW(0, 1, 0x5), 0x0},
274 {TAC_REG_SDW(0, 1, 0x6), 0x0},
275 {TAC_REG_SDW(0, 1, 0x7), 0x0},
276 {TAC_REG_SDW(0, 1, 0x8), 0x0},
277 {TAC_REG_SDW(0, 1, 0x9), 0x0},
278 {TAC_REG_SDW(0, 1, 0xa), 0x0},
279 {TAC_REG_SDW(0, 1, 0xb), 0x1},
280 {TAC_REG_SDW(0, 1, 0xc), 0x0},
281 {TAC_REG_SDW(0, 1, 0xd), 0x0},
282 {TAC_REG_SDW(0, 1, 0xe), 0x0},
283 {TAC_REG_SDW(0, 1, 0xf), 0x8},
284 {TAC_REG_SDW(0, 1, 0x10), 0x0},
285 {TAC_REG_SDW(0, 1, 0x11), 0x0},
286 {TAC_REG_SDW(0, 1, 0x12), 0x1},
287 {TAC_REG_SDW(0, 1, 0x13), 0x0},
288 {TAC_REG_SDW(0, 1, 0x14), 0x0},
289 {TAC_REG_SDW(0, 1, 0x15), 0x0},
290 {TAC_REG_SDW(0, 1, 0x16), 0x0},
291 {TAC_REG_SDW(0, 1, 0x17), 0x0},
292 {TAC_REG_SDW(0, 1, 0x18), 0x0},
293 {TAC_REG_SDW(0, 1, 0x19), 0x0},
294 {TAC_REG_SDW(0, 1, 0x1a), 0x0},
295 {TAC_REG_SDW(0, 1, 0x1b), 0x0},
296 {TAC_REG_SDW(0, 1, 0x1c), 0x0},
297 {TAC_REG_SDW(0, 1, 0x1d), 0x0},
298 {TAC_REG_SDW(0, 1, 0x1e), 0x2},
299 {TAC_REG_SDW(0, 1, 0x1f), 0x8},
300 {TAC_REG_SDW(0, 1, 0x20), 0x9},
301 {TAC_REG_SDW(0, 1, 0x21), 0xa},
302 {TAC_REG_SDW(0, 1, 0x22), 0xb},
303 {TAC_REG_SDW(0, 1, 0x23), 0xc},
304 {TAC_REG_SDW(0, 1, 0x24), 0xd},
305 {TAC_REG_SDW(0, 1, 0x25), 0xe},
306 {TAC_REG_SDW(0, 1, 0x26), 0xf},
307 {TAC_REG_SDW(0, 1, 0x27), 0x8},
308 {TAC_REG_SDW(0, 1, 0x28), 0x9},
309 {TAC_REG_SDW(0, 1, 0x29), 0xa},
310 {TAC_REG_SDW(0, 1, 0x2a), 0xb},
311 {TAC_REG_SDW(0, 1, 0x2b), 0xc},
312 {TAC_REG_SDW(0, 1, 0x2c), 0xd},
313 {TAC_REG_SDW(0, 1, 0x2d), 0xe},
314 {TAC_REG_SDW(0, 1, 0x2e), 0xf},
315 {TAC_REG_SDW(0, 1, 0x2f), 0x0},
316 {TAC_REG_SDW(0, 1, 0x30), 0x0},
317 {TAC_REG_SDW(0, 1, 0x31), 0x0},
318 {TAC_REG_SDW(0, 1, 0x32), 0x0},
319 {TAC_REG_SDW(0, 1, 0x33), 0x0},
320 {TAC_REG_SDW(0, 1, 0x34), 0x0},
321 {TAC_REG_SDW(0, 1, 0x35), 0x0},
322 {TAC_REG_SDW(0, 1, 0x36), 0x0},
323 {TAC_REG_SDW(0, 1, 0x37), 0x0},
324 {TAC_REG_SDW(0, 1, 0x38), 0x98},
325 {TAC_REG_SDW(0, 1, 0x39), 0x0},
326 {TAC_REG_SDW(0, 1, 0x3a), 0x0},
327 {TAC_REG_SDW(0, 1, 0x3b), 0x0},
328 {TAC_REG_SDW(0, 1, 0x3c), 0x1},
329 {TAC_REG_SDW(0, 1, 0x3d), 0x2},
330 {TAC_REG_SDW(0, 1, 0x3e), 0x3},
331 {TAC_REG_SDW(0, 1, 0x3f), 0x4},
332 {TAC_REG_SDW(0, 1, 0x40), 0x5},
333 {TAC_REG_SDW(0, 1, 0x41), 0x6},
334 {TAC_REG_SDW(0, 1, 0x42), 0x7},
335 {TAC_REG_SDW(0, 1, 0x43), 0x0},
336 {TAC_REG_SDW(0, 1, 0x44), 0x0},
337 {TAC_REG_SDW(0, 1, 0x45), 0x1},
338 {TAC_REG_SDW(0, 1, 0x46), 0x2},
339 {TAC_REG_SDW(0, 1, 0x47), 0x3},
340 {TAC_REG_SDW(0, 1, 0x48), 0x4},
341 {TAC_REG_SDW(0, 1, 0x49), 0x5},
342 {TAC_REG_SDW(0, 1, 0x4a), 0x6},
343 {TAC_REG_SDW(0, 1, 0x4b), 0x7},
344 {TAC_REG_SDW(0, 1, 0x4c), 0x98},
345 {TAC_REG_SDW(0, 1, 0x4d), 0x0},
346 {TAC_REG_SDW(0, 1, 0x4e), 0x0},
347 {TAC_REG_SDW(0, 1, 0x4f), 0x0},
348 {TAC_REG_SDW(0, 1, 0x50), 0x1},
349 {TAC_REG_SDW(0, 1, 0x51), 0x2},
350 {TAC_REG_SDW(0, 1, 0x52), 0x3},
351 {TAC_REG_SDW(0, 1, 0x53), 0x4},
352 {TAC_REG_SDW(0, 1, 0x54), 0x5},
353 {TAC_REG_SDW(0, 1, 0x55), 0x6},
354 {TAC_REG_SDW(0, 1, 0x56), 0x7},
355 {TAC_REG_SDW(0, 1, 0x57), 0x0},
356 {TAC_REG_SDW(0, 1, 0x58), 0x0},
357 {TAC_REG_SDW(0, 1, 0x59), 0x1},
358 {TAC_REG_SDW(0, 1, 0x5a), 0x2},
359 {TAC_REG_SDW(0, 1, 0x5b), 0x3},
360 {TAC_REG_SDW(0, 1, 0x5c), 0x4},
361 {TAC_REG_SDW(0, 1, 0x5d), 0x5},
362 {TAC_REG_SDW(0, 1, 0x5e), 0x6},
363 {TAC_REG_SDW(0, 1, 0x5f), 0x7},
364 {TAC_REG_SDW(0, 1, 0x60), 0x98},
365 {TAC_REG_SDW(0, 1, 0x61), 0x0},
366 {TAC_REG_SDW(0, 1, 0x62), 0x0},
367 {TAC_REG_SDW(0, 1, 0x63), 0x0},
368 {TAC_REG_SDW(0, 1, 0x64), 0x1},
369 {TAC_REG_SDW(0, 1, 0x65), 0x2},
370 {TAC_REG_SDW(0, 1, 0x66), 0x3},
371 {TAC_REG_SDW(0, 1, 0x67), 0x4},
372 {TAC_REG_SDW(0, 1, 0x68), 0x5},
373 {TAC_REG_SDW(0, 1, 0x69), 0x6},
374 {TAC_REG_SDW(0, 1, 0x6a), 0x7},
375 {TAC_REG_SDW(0, 1, 0x6b), 0x0},
376 {TAC_REG_SDW(0, 1, 0x6c), 0x0},
377 {TAC_REG_SDW(0, 1, 0x6d), 0x1},
378 {TAC_REG_SDW(0, 1, 0x6e), 0x2},
379 {TAC_REG_SDW(0, 1, 0x6f), 0x3},
380 {TAC_REG_SDW(0, 1, 0x70), 0x4},
381 {TAC_REG_SDW(0, 1, 0x71), 0x5},
382 {TAC_REG_SDW(0, 1, 0x72), 0x6},
383 {TAC_REG_SDW(0, 1, 0x73), 0x7},
384 };
385
386 static const struct reg_sequence tac_spk_seq[] = {
387 REG_SEQ0(SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_FU21,
388 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_LEFT), 0),
389 REG_SEQ0(SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_FU21,
390 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_RIGHT), 0),
391 REG_SEQ0(SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_FU23,
392 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_LEFT), 0),
393 REG_SEQ0(SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_FU23,
394 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_RIGHT), 0),
395 };
396
397 static const struct reg_sequence tac_sm_seq[] = {
398 REG_SEQ0(SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_FU113,
399 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_LEFT), 0),
400 REG_SEQ0(SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_FU113,
401 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_RIGHT), 0),
402 REG_SEQ0(SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_FU11,
403 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_LEFT), 0),
404 REG_SEQ0(SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_FU11,
405 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_RIGHT), 0),
406 };
407
408 static const struct reg_sequence tac_uaj_seq[] = {
409 REG_SEQ0(SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_FU41,
410 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_LEFT), 0),
411 REG_SEQ0(SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_FU41,
412 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_RIGHT), 0),
413 REG_SEQ0(SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_FU36,
414 TAC_SDCA_CHANNEL_GAIN, TAC_JACK_MONO_CS), 0),
415 };
416
tac_volatile_reg(struct device * dev,unsigned int reg)417 static bool tac_volatile_reg(struct device *dev, unsigned int reg)
418 {
419 switch (reg) {
420 case TAC_REG_SDW(0, 0, 1) ... TAC_REG_SDW(0, 0, 5):
421 case TAC_REG_SDW(0, 2, 1) ... TAC_REG_SDW(0, 2, 6):
422 case TAC_REG_SDW(0, 2, 24) ... TAC_REG_SDW(0, 2, 55):
423 case SDW_SDCA_CTL(TAC_FUNCTION_ID_HID, TAC_SDCA_ENT_HID1,
424 TAC_SDCA_CTL_HIDTX_CURRENT_OWNER, 0):
425 case SDW_SDCA_CTL(TAC_FUNCTION_ID_HID, TAC_SDCA_ENT_HID1,
426 TAC_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0):
427 case SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_GE35,
428 TAC_SDCA_CTL_DET_MODE, 0):
429 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_PDE23,
430 TAC_SDCA_REQUESTED_PS, 0):
431 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_PDE11,
432 TAC_SDCA_REQUESTED_PS, 0):
433 case SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_PDE47,
434 TAC_SDCA_REQUESTED_PS, 0):
435 case SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_PDE34,
436 TAC_SDCA_REQUESTED_PS, 0):
437 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_PDE23,
438 TAC_SDCA_ACTUAL_PS, 0):
439 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_PDE11,
440 TAC_SDCA_ACTUAL_PS, 0):
441 case SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_PDE47,
442 TAC_SDCA_ACTUAL_PS, 0):
443 case SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_PDE34,
444 TAC_SDCA_ACTUAL_PS, 0):
445 case SDW_SCP_SDCA_INT1:
446 case SDW_SCP_SDCA_INT2:
447 case SDW_SCP_SDCA_INT3:
448 case SDW_SCP_SDCA_INT4:
449 case SDW_SDCA_CTL(1, 0, 0x10, 0):
450 case SDW_SDCA_CTL(2, 0, 0x10, 0):
451 case SDW_SDCA_CTL(3, 0, 0x10, 0):
452 case SDW_SDCA_CTL(4, 0, 0x1, 0):
453 case 0x44007F80 ... 0x44007F87:
454 case TAC_DSP_ALGO_STATUS: /* DSP algo status - always read from HW */
455 return true;
456 default:
457 break;
458 }
459
460 return false;
461 }
462
tac_sdca_mbq_size(struct device * dev,unsigned int reg)463 static int tac_sdca_mbq_size(struct device *dev, unsigned int reg)
464 {
465 switch (reg) {
466 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_FU21,
467 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_LEFT):
468 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_FU21,
469 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_RIGHT):
470 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_FU23,
471 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_LEFT):
472 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_FU23,
473 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_RIGHT):
474 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_FU23,
475 TAC_SDCA_MASTER_GAIN, 0):
476 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_FU113,
477 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_LEFT):
478 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_FU113,
479 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_RIGHT):
480 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_FU11,
481 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_LEFT):
482 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_FU11,
483 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_RIGHT):
484 case SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_FU41,
485 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_LEFT):
486 case SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_FU41,
487 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_RIGHT):
488 case SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_FU36,
489 TAC_SDCA_CHANNEL_GAIN, TAC_JACK_MONO_CS):
490 return 2;
491
492 default:
493 return 1;
494 }
495 }
496
497 static const struct regmap_sdw_mbq_cfg tac_mbq_cfg = {
498 .mbq_size = tac_sdca_mbq_size,
499 };
500
501 static const struct regmap_config tac_regmap = {
502 .reg_bits = 32,
503 .val_bits = 16, /* mbq support */
504 .reg_defaults = tac_reg_default,
505 .num_reg_defaults = ARRAY_SIZE(tac_reg_default),
506 .max_register = 0x47FFFFFF,
507 .cache_type = REGCACHE_MAPLE,
508 .volatile_reg = tac_volatile_reg,
509 .use_single_read = true,
510 .use_single_write = true,
511 };
512
513 /* Check if device has UAJ (Universal Audio Jack) support */
tac_has_uaj_support(struct tac5xx2_prv * tac_dev)514 static bool tac_has_uaj_support(struct tac5xx2_prv *tac_dev)
515 {
516 return tac_dev->uaj_func_data;
517 }
518
519 /* Forward declaration for headset detection */
520 static int tac5xx2_sdca_headset_detect(struct tac5xx2_prv *tac_dev);
521
522 /* Volume controls for mic, hp and mic cap */
523 static const struct snd_kcontrol_new tac5xx2_snd_controls[] = {
524 SOC_DOUBLE_R_RANGE_TLV("Amp Volume", TAC_AMP_LVL_CFG0, TAC_AMP_LVL_CFG1,
525 2, 0, 44, 1, tac5xx2_amp_tlv),
526 TAC_DOUBLE_Q78_TLV("DMIC Capture Volume", SM, FU113),
527 TAC_DOUBLE_Q78_TLV("Speaker Volume", SA, FU21),
528 };
529
530 static const struct snd_kcontrol_new tac_uaj_controls[] = {
531 TAC_DOUBLE_Q78_TLV("UAJ Playback Volume", UAJ, FU41),
532 SDCA_SINGLE_Q78_TLV("UAJ Capture Volume",
533 SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_FU36,
534 TAC_SDCA_CHANNEL_GAIN, TAC_JACK_MONO_CS),
535 TAC_DVC_MIN, TAC_DVC_MAX, TAC_DVC_STEP, tac5xx2_dvc_tlv),
536 };
537
538 static const struct snd_soc_dapm_widget tac5xx2_common_widgets[] = {
539 /* Port 1: Speaker Playback Path */
540 SND_SOC_DAPM_AIF_IN("AIF1 Playback", "DP1 Speaker Playback", 0,
541 SND_SOC_NOPM, 0, 0),
542 SND_SOC_DAPM_PGA("FU21_L", FU21_L_MUTE_REG, 0, 1, NULL, 0),
543 SND_SOC_DAPM_PGA("FU21_R", FU21_R_MUTE_REG, 0, 1, NULL, 0),
544 SND_SOC_DAPM_PGA("FU23_L", FU23_L_MUTE_REG, 0, 1, NULL, 0),
545 SND_SOC_DAPM_PGA("FU23_R", FU23_R_MUTE_REG, 0, 1, NULL, 0),
546 SND_SOC_DAPM_OUTPUT("SPK_L"),
547 SND_SOC_DAPM_OUTPUT("SPK_R"),
548
549 /* Port 3: Smart Mic (DMIC) Capture Path */
550 SND_SOC_DAPM_AIF_OUT("AIF3 Capture", "DP3 Mic Capture", 0, SND_SOC_NOPM, 0, 0),
551 SND_SOC_DAPM_INPUT("DMIC_L"),
552 SND_SOC_DAPM_INPUT("DMIC_R"),
553 SND_SOC_DAPM_PGA("IT11", IT11_USAGE_REG, 0, 0, NULL, 0),
554 SND_SOC_DAPM_SUPPLY("CS113", SND_SOC_NOPM, 0, 0, NULL, 0),
555 SND_SOC_DAPM_PGA("FU11_L", FU11_L_MUTE_REG, 0, 1, NULL, 0),
556 SND_SOC_DAPM_PGA("FU11_R", FU11_R_MUTE_REG, 0, 1, NULL, 0),
557 SND_SOC_DAPM_PGA("PPU11", SND_SOC_NOPM, 0, 0, NULL, 0),
558 SND_SOC_DAPM_PGA("XU12", XU12_BYPASS_REG, 0, 0, NULL, 0),
559 SND_SOC_DAPM_PGA("FU113_L", FU113_L_MUTE_REG, 0, 1, NULL, 0),
560 SND_SOC_DAPM_PGA("FU113_R", FU113_R_MUTE_REG, 0, 1, NULL, 0),
561 SND_SOC_DAPM_PGA("OT113", OT113_USAGE_REG, 0, 0, NULL, 0),
562 };
563
564 static const struct snd_soc_dapm_widget tac_uaj_widgets[] = {
565 /* Port 4: UAJ (Headphone) Playback Path */
566 SND_SOC_DAPM_AIF_IN("AIF4 Playback", "DP4 UAJ Speaker Playback", 0,
567 SND_SOC_NOPM, 0, 0),
568 SND_SOC_DAPM_PGA("IT41", IT41_USAGE_REG, 0, 0, NULL, 0),
569 SND_SOC_DAPM_PGA("FU41_L", FU41_L_MUTE_REG, 0, 1, NULL, 0),
570 SND_SOC_DAPM_PGA("FU41_R", FU41_R_MUTE_REG, 0, 1, NULL, 0),
571 SND_SOC_DAPM_PGA("XU42", XU42_BYPASS_REG, 0, 0, NULL, 0),
572 SND_SOC_DAPM_SUPPLY("CS41", SND_SOC_NOPM, 0, 0, NULL, 0),
573 SND_SOC_DAPM_DAC("OT45", "DP4 UAJ Speaker Playback", OT45_USAGE_REG, 0, 0),
574 SND_SOC_DAPM_OUTPUT("HP_L"),
575 SND_SOC_DAPM_OUTPUT("HP_R"),
576
577 /* Port 7: UAJ (Headset Mic) Capture Path */
578 SND_SOC_DAPM_AIF_OUT("AIF7 Capture", "DP7 UAJ Mic Capture", 0,
579 SND_SOC_NOPM, 0, 0),
580 SND_SOC_DAPM_INPUT("UAJ_MIC"),
581 SND_SOC_DAPM_ADC("IT33", "DP7 UAJ Mic Capture", IT33_USAGE_REG, 0, 0),
582 SND_SOC_DAPM_PGA("FU36", FU36_MUTE_REG, 0, 1, NULL, 0),
583 SND_SOC_DAPM_SUPPLY("CS36", SND_SOC_NOPM, 0, 0, NULL, 0),
584 SND_SOC_DAPM_PGA("OT36", OT36_USAGE_REG, 0, 0, NULL, 0),
585 };
586
587 static const struct snd_soc_dapm_route tac5xx2_common_routes[] = {
588 /* Speaker Playback Path */
589 {"FU21_L", NULL, "AIF1 Playback"},
590 {"FU21_R", NULL, "AIF1 Playback"},
591
592 {"FU23_L", NULL, "FU21_L"},
593 {"FU23_R", NULL, "FU21_R"},
594
595 {"SPK_L", NULL, "FU23_L"},
596 {"SPK_R", NULL, "FU23_R"},
597
598 /* Smart Mic DAPM Routes */
599 {"IT11", NULL, "DMIC_L"},
600 {"IT11", NULL, "DMIC_R"},
601 {"FU11_L", NULL, "IT11"},
602 {"FU11_R", NULL, "IT11"},
603 {"PPU11", NULL, "FU11_L"},
604 {"PPU11", NULL, "FU11_R"},
605 {"XU12", NULL, "PPU11"},
606 {"FU113_L", NULL, "XU12"},
607 {"FU113_R", NULL, "XU12"},
608 {"FU113_L", NULL, "CS113"},
609 {"FU113_R", NULL, "CS113"},
610 {"OT113", NULL, "FU113_L"},
611 {"OT113", NULL, "FU113_R"},
612 {"OT113", NULL, "CS113"},
613 {"AIF3 Capture", NULL, "OT113"},
614 };
615
616 static const struct snd_soc_dapm_route tac_uaj_routes[] = {
617 /* UAJ Playback routes */
618 {"IT41", NULL, "AIF4 Playback"},
619 {"IT41", NULL, "CS41"},
620 {"FU41_L", NULL, "IT41"},
621 {"FU41_R", NULL, "IT41"},
622 {"XU42", NULL, "FU41_L"},
623 {"XU42", NULL, "FU41_R"},
624 {"OT45", NULL, "XU42"},
625 {"OT45", NULL, "CS41"},
626 {"HP_L", NULL, "OT45"},
627 {"HP_R", NULL, "OT45"},
628
629 /* UAJ Capture routes */
630 {"IT33", NULL, "UAJ_MIC"},
631 {"IT33", NULL, "CS36"},
632 {"FU36", NULL, "IT33"},
633 {"OT36", NULL, "FU36"},
634 {"OT36", NULL, "CS36"},
635 {"AIF7 Capture", NULL, "OT36"},
636 };
637
tac_set_sdw_stream(struct snd_soc_dai * dai,void * sdw_stream,s32 direction)638 static s32 tac_set_sdw_stream(struct snd_soc_dai *dai,
639 void *sdw_stream, s32 direction)
640 {
641 if (sdw_stream)
642 snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
643
644 return 0;
645 }
646
tac_sdw_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)647 static void tac_sdw_shutdown(struct snd_pcm_substream *substream,
648 struct snd_soc_dai *dai)
649 {
650 snd_soc_dai_set_dma_data(dai, substream, NULL);
651 }
652
tac_clear_latch(struct tac5xx2_prv * priv)653 static int tac_clear_latch(struct tac5xx2_prv *priv)
654 {
655 /* CLR_REG is a self-clearing bit */
656 return regmap_update_bits(priv->regmap, TAC_INT_CFG,
657 TAC_INT_CFG_CLR_REG, TAC_INT_CFG_CLR_REG);
658 }
659
tac_sdw_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)660 static int tac_sdw_hw_params(struct snd_pcm_substream *substream,
661 struct snd_pcm_hw_params *params,
662 struct snd_soc_dai *dai)
663 {
664 struct snd_soc_component *component = dai->component;
665 struct tac5xx2_prv *tac_dev = snd_soc_component_get_drvdata(component);
666 struct sdw_slave *sdw_peripheral = tac_dev->sdw_peripheral;
667 struct sdw_stream_runtime *sdw_stream;
668 struct sdw_stream_config stream_config = {0};
669 struct sdw_port_config port_config = {0};
670 u8 sample_rate_idx = 0;
671 int function_id;
672 int pde_entity;
673 int port_num;
674 int ret;
675
676 if (!tac_dev->hw_init) {
677 dev_err(tac_dev->dev,
678 "error: operation without hw initialization");
679 return -EINVAL;
680 }
681
682 sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
683 if (!sdw_stream) {
684 dev_err(tac_dev->dev, "failed to get dma data");
685 return -EINVAL;
686 }
687
688 ret = tac_clear_latch(tac_dev);
689 if (ret)
690 dev_warn(tac_dev->dev, "clear latch failed, err=%d", ret);
691
692 switch (dai->id) {
693 case TAC5XX2_DMIC:
694 function_id = TAC_FUNCTION_ID_SM;
695 pde_entity = TAC_SDCA_ENT_PDE11;
696 port_num = TAC_SDW_PORT_NUM_DMIC;
697 break;
698 case TAC5XX2_UAJ:
699 function_id = TAC_FUNCTION_ID_UAJ;
700 pde_entity = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
701 TAC_SDCA_ENT_PDE47 : TAC_SDCA_ENT_PDE34;
702 port_num = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
703 TAC_SDW_PORT_NUM_UAJ_PLAYBACK :
704 TAC_SDW_PORT_NUM_UAJ_CAPTURE;
705 break;
706 case TAC5XX2_SPK:
707 function_id = TAC_FUNCTION_ID_SA;
708 pde_entity = TAC_SDCA_ENT_PDE23;
709 port_num = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
710 TAC_SDW_PORT_NUM_SPK_PLAYBACK :
711 TAC_SDW_PORT_NUM_SPK_CAPTURE;
712 break;
713 default:
714 dev_err(tac_dev->dev, "Invalid dai id: %d for power up\n", dai->id);
715 return -EINVAL;
716 }
717
718 snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
719 port_config.num = port_num;
720 ret = sdw_stream_add_slave(sdw_peripheral, &stream_config,
721 &port_config, 1, sdw_stream);
722 if (ret) {
723 dev_err(dai->dev,
724 "Unable to configure port %d: %d\n", port_num, ret);
725 return ret;
726 }
727
728 switch (params_rate(params)) {
729 case 48000:
730 sample_rate_idx = 0x01;
731 break;
732 case 44100:
733 sample_rate_idx = 0x02;
734 break;
735 case 96000:
736 sample_rate_idx = 0x03;
737 break;
738 case 88200:
739 sample_rate_idx = 0x04;
740 break;
741 default:
742 dev_dbg(tac_dev->dev, "Unsupported sample rate: %d Hz",
743 params_rate(params));
744 return -EINVAL;
745 }
746
747 switch (function_id) {
748 case TAC_FUNCTION_ID_SM:
749 ret = regmap_write(tac_dev->regmap,
750 SDW_SDCA_CTL(function_id, TAC_SDCA_ENT_CS113,
751 TAC_SDCA_CTL_CS_SAMP_RATE_IDX, 0),
752 sample_rate_idx);
753 if (ret) {
754 dev_err(tac_dev->dev, "Failed to set CS113 sample rate: %d", ret);
755 return ret;
756 }
757
758 break;
759 case TAC_FUNCTION_ID_UAJ:
760 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
761 ret = regmap_write(tac_dev->regmap,
762 SDW_SDCA_CTL(function_id, TAC_SDCA_ENT_CS41,
763 TAC_SDCA_CTL_CS_SAMP_RATE_IDX, 0),
764 sample_rate_idx);
765 if (ret) {
766 dev_err(tac_dev->dev, "Failed to set CS41 sample rate: %d", ret);
767 return ret;
768 }
769 } else {
770 ret = regmap_write(tac_dev->regmap,
771 SDW_SDCA_CTL(function_id, TAC_SDCA_ENT_CS36,
772 TAC_SDCA_CTL_CS_SAMP_RATE_IDX, 0),
773 sample_rate_idx);
774 if (ret) {
775 dev_err(tac_dev->dev, "Failed to set CS36 sample rate: %d", ret);
776 return ret;
777 }
778 }
779 break;
780 case TAC_FUNCTION_ID_SA:
781 /* SmartAmp: no additional sample rate configuration needed */
782 break;
783 }
784
785 ret = regmap_write(tac_dev->regmap, SDW_SDCA_CTL(function_id, pde_entity,
786 TAC_SDCA_REQUESTED_PS, 0), 0);
787 if (ret) {
788 dev_err(tac_dev->dev,
789 "failed to set func %d, entity %d's requested PS to 0: %d\n",
790 function_id, pde_entity, ret);
791 return ret;
792 }
793
794 ret = sdca_asoc_pde_poll_actual_ps(tac_dev->regmap, function_id, pde_entity,
795 SDCA_PDE_PS3, SDCA_PDE_PS0, NULL, 0);
796 if (ret)
797 dev_err(tac_dev->dev, "failed to transition func %d, pde %d from PS3 -> PS0, err=%d\n",
798 function_id, pde_entity, ret);
799 return ret;
800 }
801
tac_sdw_pcm_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)802 static int tac_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
803 struct snd_soc_dai *dai)
804 {
805 struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
806 struct tac5xx2_prv *tac_dev = snd_soc_component_get_drvdata(dai->component);
807 int pde_entity, function_id;
808 int ret;
809
810 sdw_stream_remove_slave(tac_dev->sdw_peripheral, sdw_stream);
811
812 switch (dai->id) {
813 case TAC5XX2_DMIC:
814 pde_entity = TAC_SDCA_ENT_PDE11;
815 function_id = TAC_FUNCTION_ID_SM;
816 break;
817 case TAC5XX2_UAJ:
818 function_id = TAC_FUNCTION_ID_UAJ;
819 pde_entity = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
820 TAC_SDCA_ENT_PDE47 : TAC_SDCA_ENT_PDE34;
821 break;
822 case TAC5XX2_SPK:
823 function_id = TAC_FUNCTION_ID_SA;
824 pde_entity = TAC_SDCA_ENT_PDE23;
825 break;
826 default:
827 dev_err(tac_dev->dev, "unhandled dai %d for power down\n", dai->id);
828 return -EINVAL;
829 }
830
831 ret = regmap_write(tac_dev->regmap, SDW_SDCA_CTL(function_id, pde_entity,
832 TAC_SDCA_REQUESTED_PS, 0),
833 SDCA_PDE_PS3);
834 if (ret) {
835 dev_err(tac_dev->dev,
836 "failed to set func %d, entity %d's requested PS to 3: %d\n",
837 function_id, pde_entity, ret);
838 return ret;
839 }
840
841 ret = sdca_asoc_pde_poll_actual_ps(tac_dev->regmap, function_id,
842 pde_entity, SDCA_PDE_PS0, SDCA_PDE_PS3,
843 NULL, 0);
844 if (ret)
845 dev_err(tac_dev->dev,
846 "failed to transition func %d, pde %d from PS0 -> PS3, err=%d\n",
847 function_id, pde_entity, ret);
848
849 return ret;
850 }
851
852 static const struct snd_soc_dai_ops tac_dai_ops = {
853 .hw_params = tac_sdw_hw_params,
854 .hw_free = tac_sdw_pcm_hw_free,
855 .set_stream = tac_set_sdw_stream,
856 .shutdown = tac_sdw_shutdown,
857 };
858
tac5xx2_sdca_btn_type(unsigned char * buffer,struct tac5xx2_prv * tac_dev)859 static int tac5xx2_sdca_btn_type(unsigned char *buffer, struct tac5xx2_prv *tac_dev)
860 {
861 switch (*buffer) {
862 case 1: /* play pause */
863 return SND_JACK_BTN_0;
864 case 10: /* vol down */
865 return SND_JACK_BTN_3;
866 case 8: /* vol up */
867 return SND_JACK_BTN_2;
868 case 4: /* long press */
869 return SND_JACK_BTN_1;
870 case 2: /* next song */
871 case 32: /* next song */
872 return SND_JACK_BTN_4;
873 default:
874 return 0;
875 }
876 }
877
tac5xx2_sdca_button_detect(struct tac5xx2_prv * tac_dev)878 static int tac5xx2_sdca_button_detect(struct tac5xx2_prv *tac_dev)
879 {
880 unsigned int btn_type, offset, idx;
881 int ret, value, owner;
882 u8 buf[2];
883
884 ret = regmap_read(tac_dev->regmap,
885 SDW_SDCA_CTL(TAC_FUNCTION_ID_HID, TAC_SDCA_ENT_HID1,
886 TAC_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), &owner);
887 if (ret) {
888 dev_err(tac_dev->dev,
889 "Failed to read current UMP message owner 0x%x", ret);
890 return ret;
891 }
892
893 if (owner == SDCA_UMP_OWNER_DEVICE) {
894 dev_dbg(tac_dev->dev, "skip button detect as current owner is not host\n");
895 return 0;
896 }
897
898 ret = regmap_read(tac_dev->regmap,
899 SDW_SDCA_CTL(TAC_FUNCTION_ID_HID, TAC_SDCA_ENT_HID1,
900 TAC_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset);
901 if (ret) {
902 dev_err(tac_dev->dev,
903 "Failed to read current UMP message offset: %d", ret);
904 goto end_btn_det;
905 }
906
907 dev_dbg(tac_dev->dev, "button detect: message offset = %x", offset);
908
909 for (idx = 0; idx < sizeof(buf); idx++) {
910 ret = regmap_read(tac_dev->regmap,
911 TAC_BUF_ADDR_HID1 + offset + idx, &value);
912 if (ret) {
913 dev_err(tac_dev->dev,
914 "Failed to read HID buffer: %d", ret);
915 goto end_btn_det;
916 }
917 buf[idx] = value & 0xff;
918 }
919
920 if (buf[0] == 0x1) {
921 btn_type = tac5xx2_sdca_btn_type(&buf[1], tac_dev);
922 ret = btn_type;
923 }
924
925 end_btn_det:
926 regmap_write(tac_dev->regmap,
927 SDW_SDCA_CTL(TAC_FUNCTION_ID_HID, TAC_SDCA_ENT_HID1,
928 TAC_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), 0x01);
929
930 return ret;
931 }
932
tac5xx2_sdca_headset_detect(struct tac5xx2_prv * tac_dev)933 static int tac5xx2_sdca_headset_detect(struct tac5xx2_prv *tac_dev)
934 {
935 int val, ret;
936 u8 jack_prep;
937
938 ret = regmap_read(tac_dev->regmap,
939 SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_GE35,
940 TAC_SDCA_CTL_DET_MODE, 0), &val);
941 if (ret) {
942 dev_err(tac_dev->dev, "Failed to read the detect mode");
943 return ret;
944 }
945
946 jack_prep = TAC_UAJ_PREP_CONNECTED;
947
948 switch (val) {
949 case 4:
950 tac_dev->jack_type = SND_JACK_MICROPHONE;
951 break;
952 case 5:
953 tac_dev->jack_type = SND_JACK_HEADPHONE;
954 break;
955 case 6:
956 tac_dev->jack_type = SND_JACK_HEADSET;
957 break;
958 case 0:
959 default:
960 tac_dev->jack_type = 0;
961 jack_prep = TAC_UAJ_PREP_DISCONNECTED;
962 break;
963 }
964
965 ret = regmap_write(tac_dev->regmap,
966 SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_GE35,
967 TAC_SDCA_CTL_SEL_MODE, 0), val);
968 if (ret)
969 dev_err(tac_dev->dev, "Failed to update the jack type to device");
970
971 /*
972 * When uaj is uplugged and booted, we end up with the channel prepare
973 * timeout error for the uaj ports. This writes allows the channel prepare
974 * to succeed when the uaj is not plugged in.
975 */
976 if (tac_dev->rev_id >= 0x30) {
977 ret = regmap_write(tac_dev->regmap, TAC_REG_SDW(0, 3, 127), jack_prep);
978 if (ret)
979 dev_warn(tac_dev->dev, "Failed to write jack_prep register: %d\n", ret);
980 }
981
982 return 0;
983 }
984
tac5xx2_jack_init(struct tac5xx2_prv * tac_dev)985 static int tac5xx2_jack_init(struct tac5xx2_prv *tac_dev)
986 {
987 u32 jd_int_mask, hid_int_mask;
988 int ret = 0;
989
990 if (tac_dev->rev_id >= 0x30) {
991 jd_int_mask = SDW_SCP_SDCA_INTMASK_SDCA_12;
992 hid_int_mask = SDW_SCP_SDCA_INTMASK_SDCA_17;
993 } else {
994 jd_int_mask = SDW_SCP_SDCA_INTMASK_SDCA_11;
995 hid_int_mask = SDW_SCP_SDCA_INTMASK_SDCA_16;
996 }
997
998 if (!tac_dev->hs_jack)
999 goto disable_interrupts;
1000
1001 ret = regmap_write(tac_dev->regmap, SDW_SCP_SDCA_INTMASK2, jd_int_mask);
1002 if (ret) {
1003 dev_err(tac_dev->dev,
1004 "Failed to register jack detection interrupt: %d\n", ret);
1005 goto disable_interrupts;
1006 }
1007
1008 ret = regmap_write(tac_dev->regmap, SDW_SCP_SDCA_INTMASK3, hid_int_mask);
1009 if (ret) {
1010 dev_err(tac_dev->dev,
1011 "Failed to register for button detect interrupt: %d\n", ret);
1012 goto disable_interrupts;
1013 }
1014
1015 return 0;
1016
1017 disable_interrupts:
1018 /* ignore errors while disabling interrupts */
1019 regmap_write(tac_dev->regmap, SDW_SCP_SDCA_INTMASK2, 0);
1020 regmap_write(tac_dev->regmap, SDW_SCP_SDCA_INTMASK3, 0);
1021
1022 return ret;
1023 }
1024
tac5xx2_set_jack(struct snd_soc_component * component,struct snd_soc_jack * hs_jack,void * data)1025 static int tac5xx2_set_jack(struct snd_soc_component *component,
1026 struct snd_soc_jack *hs_jack, void *data)
1027 {
1028 struct tac5xx2_prv *tac_dev = snd_soc_component_get_drvdata(component);
1029 int ret;
1030
1031 tac_dev->hs_jack = hs_jack;
1032
1033 /* resume can happen only after first hw_init */
1034 if (!tac_dev->first_hw_init_done)
1035 return 0;
1036
1037 ret = pm_runtime_resume_and_get(component->dev);
1038 if (ret < 0) {
1039 if (ret != -EACCES) {
1040 dev_err(component->dev,
1041 "%s: failed to resume %d\n", __func__, ret);
1042 return ret;
1043 }
1044
1045 /* pm_runtime not enabled yet */
1046 dev_dbg(component->dev,
1047 "%s: skipping jack init for now\n", __func__);
1048 return 0;
1049 }
1050
1051 ret = tac5xx2_jack_init(tac_dev);
1052 if (ret)
1053 dev_err(tac_dev->dev, "jack init failed, err=%d\n", ret);
1054
1055 pm_runtime_mark_last_busy(component->dev);
1056 pm_runtime_put_autosuspend(component->dev);
1057
1058 return ret;
1059 }
1060
tac_interrupt_callback(struct sdw_slave * slave,struct sdw_slave_intr_status * status)1061 static int tac_interrupt_callback(struct sdw_slave *slave,
1062 struct sdw_slave_intr_status *status)
1063 {
1064 unsigned int sdca_int2, sdca_int3, jack_report_mask = 0;
1065 struct tac5xx2_prv *tac_dev = dev_get_drvdata(&slave->dev);
1066 struct device *dev = &slave->dev;
1067 u32 headset_detect_chk, hid_detect_chk;
1068 int btn_type = 0;
1069 int ret = 0;
1070
1071 if (status->control_port) {
1072 if (status->control_port & SDW_SCP_INT1_PARITY)
1073 dev_warn(dev, "SCP: Parity error interrupt");
1074 if (status->control_port & SDW_SCP_INT1_BUS_CLASH)
1075 dev_warn(dev, "SCP: Bus clash interrupt");
1076 }
1077
1078 if (!tac_has_uaj_support(tac_dev))
1079 return 0;
1080
1081 ret = regmap_read(tac_dev->regmap, SDW_SCP_SDCA_INT2, &sdca_int2);
1082 if (ret) {
1083 dev_err(dev, "Failed to read UAJ Interrupt, reg:%#x err=%d\n",
1084 SDW_SCP_SDCA_INT2, ret);
1085 return ret;
1086 }
1087
1088 ret = regmap_read(tac_dev->regmap, SDW_SCP_SDCA_INT3, &sdca_int3);
1089 if (ret) {
1090 dev_err(dev, "Failed to read HID interrupt reg=%#x: err=%d",
1091 SDW_SCP_SDCA_INT3, ret);
1092 return ret;
1093 }
1094
1095 dev_dbg(dev, "SDCA_INT2: 0x%02x, SDCA_INT3: 0x%02x\n",
1096 sdca_int2, sdca_int3);
1097
1098 if (tac_dev->rev_id >= 0x30) {
1099 headset_detect_chk = SDW_SCP_SDCA_INT_SDCA_12;
1100 hid_detect_chk = SDW_SCP_SDCA_INT_SDCA_17;
1101 } else {
1102 headset_detect_chk = SDW_SCP_SDCA_INT_SDCA_11;
1103 hid_detect_chk = SDW_SCP_SDCA_INT_SDCA_16;
1104 }
1105
1106 if (sdca_int2 & headset_detect_chk) {
1107 ret = tac5xx2_sdca_headset_detect(tac_dev);
1108 if (ret < 0)
1109 goto clear;
1110 jack_report_mask |= SND_JACK_HEADSET;
1111 }
1112
1113 if (sdca_int3 & hid_detect_chk) {
1114 btn_type = tac5xx2_sdca_button_detect(tac_dev);
1115 if (btn_type < 0)
1116 btn_type = 0;
1117 jack_report_mask |= SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1118 SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4;
1119 }
1120
1121 if (tac_dev->jack_type == 0)
1122 btn_type = 0;
1123
1124 dev_dbg(tac_dev->dev, "in %s, jack_type=%d\n", __func__, tac_dev->jack_type);
1125 dev_dbg(tac_dev->dev, "in %s, btn_type=0x%x\n", __func__, btn_type);
1126
1127 if (!tac_dev->hs_jack)
1128 goto clear;
1129
1130 snd_soc_jack_report(tac_dev->hs_jack, tac_dev->jack_type | btn_type,
1131 jack_report_mask);
1132
1133 clear:
1134 if (sdca_int2) {
1135 ret = regmap_write(tac_dev->regmap, SDW_SCP_SDCA_INT2, sdca_int2);
1136 if (ret)
1137 dev_dbg(tac_dev->dev, "Failed to clear jack interrupt\n");
1138 }
1139
1140 if (sdca_int3) {
1141 ret = regmap_write(tac_dev->regmap, SDW_SCP_SDCA_INT3, sdca_int3);
1142 if (ret)
1143 dev_dbg(tac_dev->dev, "failed to clear hid interrupt\n");
1144 }
1145
1146 return 0;
1147 }
1148
1149 static struct snd_soc_dai_driver tac5572_dai_driver[] = {
1150 {
1151 .name = "tac5xx2-aif1",
1152 .id = TAC5XX2_SPK,
1153 .playback = {
1154 .stream_name = "DP1 Speaker Playback",
1155 .channels_min = 1,
1156 .channels_max = 2,
1157 .rates = TAC5XX2_DEVICE_RATES,
1158 .formats = TAC5XX2_DEVICE_FORMATS,
1159 },
1160 .ops = &tac_dai_ops,
1161 },
1162 {
1163 .name = "tac5xx2-aif2",
1164 .id = TAC5XX2_DMIC,
1165 .capture = {
1166 .stream_name = "DP3 Mic Capture",
1167 .channels_min = 1,
1168 .channels_max = 4,
1169 .rates = TAC5XX2_DEVICE_RATES,
1170 .formats = TAC5XX2_DEVICE_FORMATS,
1171 },
1172 .ops = &tac_dai_ops,
1173 },
1174 {
1175 .name = "tac5xx2-aif3",
1176 .id = TAC5XX2_UAJ,
1177 .playback = {
1178 .stream_name = "DP4 UAJ Speaker Playback",
1179 .channels_min = 1,
1180 .channels_max = 2,
1181 .rates = TAC5XX2_DEVICE_RATES,
1182 .formats = TAC5XX2_DEVICE_FORMATS,
1183 },
1184 .capture = {
1185 .stream_name = "DP7 UAJ Mic Capture",
1186 .channels_min = 1,
1187 .channels_max = 2,
1188 .rates = TAC5XX2_DEVICE_RATES,
1189 .formats = TAC5XX2_DEVICE_FORMATS,
1190 },
1191 .ops = &tac_dai_ops,
1192 },
1193 };
1194
1195 static struct snd_soc_dai_driver tac5672_dai_driver[] = {
1196 {
1197 .name = "tac5xx2-aif1",
1198 .id = TAC5XX2_SPK,
1199 .playback = {
1200 .stream_name = "DP1 Speaker Playback",
1201 .channels_min = 1,
1202 .channels_max = 2,
1203 .rates = TAC5XX2_DEVICE_RATES,
1204 .formats = TAC5XX2_DEVICE_FORMATS,
1205 },
1206 .capture = {
1207 .stream_name = "DP8 IV Sense Capture",
1208 .channels_min = 1,
1209 .channels_max = 4,
1210 .rates = TAC5XX2_DEVICE_RATES,
1211 .formats = TAC5XX2_DEVICE_FORMATS,
1212 },
1213 .ops = &tac_dai_ops,
1214 .symmetric_rate = 1,
1215 },
1216 {
1217 .name = "tac5xx2-aif2",
1218 .id = TAC5XX2_DMIC,
1219 .capture = {
1220 .stream_name = "DP3 Mic Capture",
1221 .channels_min = 1,
1222 .channels_max = 4,
1223 .rates = TAC5XX2_DEVICE_RATES,
1224 .formats = TAC5XX2_DEVICE_FORMATS,
1225 },
1226 .ops = &tac_dai_ops,
1227 },
1228 {
1229 .name = "tac5xx2-aif3",
1230 .id = TAC5XX2_UAJ,
1231 .playback = {
1232 .stream_name = "DP4 UAJ Speaker Playback",
1233 .channels_min = 1,
1234 .channels_max = 2,
1235 .rates = TAC5XX2_DEVICE_RATES,
1236 .formats = TAC5XX2_DEVICE_FORMATS,
1237 },
1238 .capture = {
1239 .stream_name = "DP7 UAJ Mic Capture",
1240 .channels_min = 1,
1241 .channels_max = 2,
1242 .rates = TAC5XX2_DEVICE_RATES,
1243 .formats = TAC5XX2_DEVICE_FORMATS,
1244 },
1245 .ops = &tac_dai_ops,
1246 },
1247 };
1248
1249 static struct snd_soc_dai_driver tac5682_dai_driver[] = {
1250 {
1251 .name = "tac5xx2-aif1",
1252 .id = TAC5XX2_SPK,
1253 .playback = {
1254 .stream_name = "DP1 Speaker Playback",
1255 .channels_min = 1,
1256 .channels_max = 2,
1257 .rates = TAC5XX2_DEVICE_RATES,
1258 .formats = TAC5XX2_DEVICE_FORMATS,
1259 },
1260 .capture = {
1261 .stream_name = "DP2 Echo Reference Capture",
1262 .channels_min = 1,
1263 .channels_max = 4,
1264 .rates = TAC5XX2_DEVICE_RATES,
1265 .formats = TAC5XX2_DEVICE_FORMATS,
1266 },
1267 .ops = &tac_dai_ops,
1268 .symmetric_rate = 1,
1269 },
1270 {
1271 .name = "tac5xx2-aif2",
1272 .id = TAC5XX2_DMIC,
1273 .capture = {
1274 .stream_name = "DP3 Mic Capture",
1275 .channels_min = 1,
1276 .channels_max = 4,
1277 .rates = TAC5XX2_DEVICE_RATES,
1278 .formats = TAC5XX2_DEVICE_FORMATS,
1279 },
1280 .ops = &tac_dai_ops,
1281 },
1282 {
1283 .name = "tac5xx2-aif3",
1284 .id = TAC5XX2_UAJ,
1285 .playback = {
1286 .stream_name = "DP4 UAJ Speaker Playback",
1287 .channels_min = 1,
1288 .channels_max = 2,
1289 .rates = TAC5XX2_DEVICE_RATES,
1290 .formats = TAC5XX2_DEVICE_FORMATS,
1291 },
1292 .capture = {
1293 .stream_name = "DP7 UAJ Mic Capture",
1294 .channels_min = 1,
1295 .channels_max = 2,
1296 .rates = TAC5XX2_DEVICE_RATES,
1297 .formats = TAC5XX2_DEVICE_FORMATS,
1298 },
1299 .ops = &tac_dai_ops,
1300 },
1301 };
1302
1303 static struct snd_soc_dai_driver tas2883_dai_driver[] = {
1304 {
1305 .name = "tac5xx2-aif1",
1306 .id = TAC5XX2_SPK,
1307 .playback = {
1308 .stream_name = "DP1 Speaker Playback",
1309 .channels_min = 1,
1310 .channels_max = 2,
1311 .rates = TAC5XX2_DEVICE_RATES,
1312 .formats = TAC5XX2_DEVICE_FORMATS,
1313 },
1314 .ops = &tac_dai_ops,
1315 .symmetric_rate = 1,
1316 },
1317 {
1318 .name = "tac5xx2-aif2",
1319 .id = TAC5XX2_DMIC,
1320 .capture = {
1321 .stream_name = "DP3 Mic Capture",
1322 .channels_min = 1,
1323 .channels_max = 4,
1324 .rates = TAC5XX2_DEVICE_RATES,
1325 .formats = TAC5XX2_DEVICE_FORMATS,
1326 },
1327 .ops = &tac_dai_ops,
1328 },
1329 };
1330
tac_component_probe(struct snd_soc_component * component)1331 static s32 tac_component_probe(struct snd_soc_component *component)
1332 {
1333 struct tac5xx2_prv *tac_dev = snd_soc_component_get_drvdata(component);
1334 int ret;
1335
1336 ret = pm_runtime_resume(component->dev);
1337 if (ret < 0 && ret != -EACCES)
1338 return ret;
1339
1340 if (!tac_has_uaj_support(tac_dev))
1341 goto done_comp_probe;
1342
1343 ret = snd_soc_dapm_new_controls(snd_soc_component_to_dapm(component),
1344 tac_uaj_widgets,
1345 ARRAY_SIZE(tac_uaj_widgets));
1346 if (ret) {
1347 dev_err(component->dev, "Failed to add UAJ widgets: %d\n", ret);
1348 return ret;
1349 }
1350
1351 ret = snd_soc_dapm_add_routes(snd_soc_component_to_dapm(component),
1352 tac_uaj_routes, ARRAY_SIZE(tac_uaj_routes));
1353 if (ret) {
1354 dev_err(component->dev, "Failed to add UAJ routes: %d\n", ret);
1355 return ret;
1356 }
1357
1358 ret = snd_soc_add_component_controls(component, tac_uaj_controls,
1359 ARRAY_SIZE(tac_uaj_controls));
1360 if (ret) {
1361 dev_err(component->dev, "Failed to add UAJ controls: %d\n", ret);
1362 return ret;
1363 }
1364
1365 done_comp_probe:
1366 tac_dev->component = component;
1367 return 0;
1368 }
1369
tac_component_remove(struct snd_soc_component * codec)1370 static void tac_component_remove(struct snd_soc_component *codec)
1371 {
1372 struct tac5xx2_prv *tac_dev = snd_soc_component_get_drvdata(codec);
1373
1374 tac_dev->component = NULL;
1375 }
1376
1377 static const struct snd_soc_component_driver soc_codec_driver_tacdevice = {
1378 .probe = tac_component_probe,
1379 .remove = tac_component_remove,
1380 .controls = tac5xx2_snd_controls,
1381 .num_controls = ARRAY_SIZE(tac5xx2_snd_controls),
1382 .dapm_widgets = tac5xx2_common_widgets,
1383 .num_dapm_widgets = ARRAY_SIZE(tac5xx2_common_widgets),
1384 .dapm_routes = tac5xx2_common_routes,
1385 .num_dapm_routes = ARRAY_SIZE(tac5xx2_common_routes),
1386 .idle_bias_on = 0,
1387 .endianness = 1,
1388 };
1389
tac_init(struct tac5xx2_prv * tac_dev)1390 static s32 tac_init(struct tac5xx2_prv *tac_dev)
1391 {
1392 struct snd_soc_component_driver *component_driver;
1393 struct snd_soc_dai_driver *dai_drv;
1394 int num_dais;
1395 s32 ret;
1396
1397 dev_set_drvdata(tac_dev->dev, tac_dev);
1398
1399 switch (tac_dev->part_id) {
1400 case 0x5572:
1401 dai_drv = tac5572_dai_driver;
1402 num_dais = ARRAY_SIZE(tac5572_dai_driver);
1403 break;
1404 case 0x5672:
1405 dai_drv = tac5672_dai_driver;
1406 num_dais = ARRAY_SIZE(tac5672_dai_driver);
1407 break;
1408 case 0x5682:
1409 dai_drv = tac5682_dai_driver;
1410 num_dais = ARRAY_SIZE(tac5682_dai_driver);
1411 break;
1412 case 0x2883:
1413 dai_drv = tas2883_dai_driver;
1414 num_dais = ARRAY_SIZE(tas2883_dai_driver);
1415 break;
1416 default:
1417 dev_err(tac_dev->dev, "Unsupported device: 0x%x\n",
1418 tac_dev->part_id);
1419 return -EINVAL;
1420 }
1421
1422 component_driver = devm_kzalloc(tac_dev->dev, sizeof(*component_driver),
1423 GFP_KERNEL);
1424 if (!component_driver)
1425 return -ENOMEM;
1426
1427 memcpy(component_driver, &soc_codec_driver_tacdevice, sizeof(*component_driver));
1428 if (tac_has_uaj_support(tac_dev))
1429 component_driver->set_jack = tac5xx2_set_jack;
1430
1431 ret = devm_snd_soc_register_component(tac_dev->dev, component_driver,
1432 dai_drv, num_dais);
1433 if (ret) {
1434 dev_err(tac_dev->dev, "%s: codec register error:%d.\n",
1435 __func__, ret);
1436 return ret;
1437 }
1438
1439 return 0;
1440 }
1441
tac5xx2_sdca_dev_suspend(struct device * dev)1442 static s32 tac5xx2_sdca_dev_suspend(struct device *dev)
1443 {
1444 struct tac5xx2_prv *tac_dev = dev_get_drvdata(dev);
1445
1446 if (!tac_dev->hw_init)
1447 return 0;
1448
1449 regcache_cache_only(tac_dev->regmap, true);
1450 return 0;
1451 }
1452
tac5xx2_sdca_dev_system_suspend(struct device * dev)1453 static s32 tac5xx2_sdca_dev_system_suspend(struct device *dev)
1454 {
1455 return tac5xx2_sdca_dev_suspend(dev);
1456 }
1457
tac5xx2_sdca_dev_resume(struct device * dev)1458 static s32 tac5xx2_sdca_dev_resume(struct device *dev)
1459 {
1460 struct tac5xx2_prv *tac_dev = dev_get_drvdata(dev);
1461 struct sdw_slave *slave = dev_to_sdw_dev(dev);
1462 int ret;
1463
1464 if (!tac_dev->first_hw_init_done) {
1465 dev_dbg(dev, "Device not initialized yet, skipping resume sync\n");
1466 return 0;
1467 }
1468
1469 ret = sdw_slave_wait_for_init(slave, TAC5XX2_PROBE_TIMEOUT_MS);
1470 if (ret) {
1471 sdw_show_ping_status(slave->bus, true);
1472 return ret;
1473 }
1474
1475 regcache_cache_only(tac_dev->regmap, false);
1476 regcache_mark_dirty(tac_dev->regmap);
1477 ret = regcache_sync(tac_dev->regmap);
1478 if (ret < 0)
1479 dev_warn(dev, "Failed to sync regcache: %d\n", ret);
1480
1481 /* Detect and set jack type for UAJ path before playback.
1482 * This is required as jack detection does not trigger interrupt
1483 * when device is in runtime_pm suspend with bus in clock stop mode.
1484 */
1485 if (tac_has_uaj_support(tac_dev))
1486 tac5xx2_sdca_headset_detect(tac_dev);
1487
1488 return 0;
1489 }
1490
1491 static const struct dev_pm_ops tac5xx2_sdca_pm = {
1492 SYSTEM_SLEEP_PM_OPS(tac5xx2_sdca_dev_system_suspend, tac5xx2_sdca_dev_resume)
1493 RUNTIME_PM_OPS(tac5xx2_sdca_dev_suspend, tac5xx2_sdca_dev_resume, NULL)
1494 };
1495
tac_fw_read_hdr(const u8 * data,struct tac_fw_hdr * hdr)1496 static s32 tac_fw_read_hdr(const u8 *data, struct tac_fw_hdr *hdr)
1497 {
1498 hdr->size = get_unaligned_le32(data);
1499 hdr->version_offset = get_unaligned_le32(data + 4);
1500 hdr->plt_id = get_unaligned_le32(data + 8);
1501 hdr->ppc3_ver = get_unaligned_le32(data + 12);
1502 memcpy(hdr->ddc_name, data + 16, 64);
1503 hdr->ddc_name[63] = 0;
1504 hdr->timestamp = get_unaligned_le64(data + 80);
1505
1506 return TAC_FW_HDR_SIZE;
1507 }
1508
tac_fw_get_next_file(const u8 * data,size_t data_size,struct tac_fw_file * file)1509 static s32 tac_fw_get_next_file(const u8 *data, size_t data_size, struct tac_fw_file *file)
1510 {
1511 u32 file_length;
1512
1513 /* Validate file header size */
1514 if (data_size < TAC_FW_FILE_HDR)
1515 return -EINVAL;
1516
1517 file->vendor_id = get_unaligned_le32(&data[0]);
1518 file->file_id = get_unaligned_le32(&data[4]);
1519 file->version = get_unaligned_le32(&data[8]);
1520 file->length = get_unaligned_le32(&data[12]);
1521 file->dest_addr = get_unaligned_le32(&data[16]);
1522 file_length = file->length;
1523
1524 /* Validate file payload exists */
1525 if (data_size < TAC_FW_FILE_HDR + file_length)
1526 return -EINVAL;
1527
1528 file->fw_data = (u8 *)&data[20];
1529
1530 return file_length + sizeof(u32) * 5;
1531 }
1532
tac5xx2_fw_ready(const struct firmware * fmw,void * context)1533 static void tac5xx2_fw_ready(const struct firmware *fmw, void *context)
1534 {
1535 struct tac5xx2_prv *tac_dev = context;
1536 struct tac_fw_file *files;
1537 u32 fw_hdr_size;
1538 u32 num_files = 0;
1539 struct tac_fw_hdr hdr;
1540 struct tm tm_time;
1541 size_t img_sz;
1542 u32 offset;
1543 s32 ret = 0;
1544 u8 *buf;
1545
1546 if (!fmw || !fmw->data || fmw->size == 0 || fmw->size < TAC_FW_HDR_SIZE + TAC_FW_FILE_HDR) {
1547 dev_err(tac_dev->dev, "fw file: %s is empty or invalid\n",
1548 tac_dev->fw_binaryname);
1549 goto out;
1550 }
1551
1552 /* Verify firmware size from header */
1553 fw_hdr_size = get_unaligned_le32(fmw->data);
1554 if (fw_hdr_size != fmw->size) {
1555 dev_err(tac_dev->dev, "firmware size mismatch: hdr=%u, actual=%zu\n",
1556 fw_hdr_size, fmw->size);
1557 goto out;
1558 }
1559
1560 files = devm_kzalloc(tac_dev->dev, sizeof(*files) * TAC_MAX_FW_CHUNKS, GFP_KERNEL);
1561 buf = devm_kmemdup(tac_dev->dev, fmw->data, fmw->size, GFP_KERNEL);
1562 if (!files || !buf)
1563 goto out;
1564
1565 /* validate the cache the firmware */
1566 img_sz = fmw->size;
1567 offset = tac_fw_read_hdr(buf, &hdr);
1568 while (offset < img_sz && num_files < TAC_MAX_FW_CHUNKS) {
1569 u32 file_length;
1570
1571 if (offset + TAC_FW_FILE_HDR > img_sz) {
1572 dev_warn(tac_dev->dev, "Incomplete block header at offset %d\n",
1573 offset);
1574 goto out;
1575 }
1576 /* Validate that the file payload doesn't exceed buffer */
1577 file_length = get_unaligned_le32(&buf[offset + 12]);
1578 /* Check for integer overflow and buffer bounds */
1579 if (file_length > img_sz || offset > img_sz - TAC_FW_FILE_HDR ||
1580 file_length > img_sz - offset - TAC_FW_FILE_HDR) {
1581 dev_warn(tac_dev->dev, "File at offset %d exceeds buffer: length=%u, available=%zu\n",
1582 offset, file_length, img_sz - offset - TAC_FW_FILE_HDR);
1583 goto out;
1584 }
1585 ret = tac_fw_get_next_file(&buf[offset], img_sz - offset, &files[num_files]);
1586 if (ret < 0) {
1587 dev_err(tac_dev->dev, "Failed to parse file at offset %d\n", offset);
1588 goto out;
1589 }
1590 offset += ret;
1591 num_files++;
1592 }
1593
1594 if (num_files == 0) {
1595 dev_err(tac_dev->dev, "firmware with no files\n");
1596 goto out;
1597 }
1598
1599 /* cache ready to use validated firmware */
1600 tac_dev->fw_file_cnt = num_files;
1601 tac_dev->fw_files = files;
1602
1603 time64_to_tm(hdr.timestamp, 0, &tm_time);
1604 dev_dbg(tac_dev->dev, "fw file: %s, num_files=%u, ts:%04ld-%02d-%02d %02d:%02d\n",
1605 tac_dev->fw_binaryname, tac_dev->fw_file_cnt,
1606 tm_time.tm_year + 1900, tm_time.tm_mon + 1, tm_time.tm_mday,
1607 tm_time.tm_hour, tm_time.tm_min);
1608 dev_dbg(tac_dev->dev, "fw file: DDC Name: %s\n", hdr.ddc_name);
1609 dev_dbg(tac_dev->dev, "fw file: PPC3 Version: 3.%ld.%ld.%ld\n",
1610 FIELD_GET(GENMASK(31, 24), hdr.ppc3_ver),
1611 FIELD_GET(GENMASK(23, 16), hdr.ppc3_ver),
1612 FIELD_GET(GENMASK(15, 8), hdr.ppc3_ver) & 0x3f);
1613
1614 out:
1615 complete_all(&tac_dev->fw_caching_complete);
1616 if (fmw)
1617 release_firmware(fmw);
1618 }
1619
tac_load_and_cache_firmware_async(struct tac5xx2_prv * tac_dev)1620 static int tac_load_and_cache_firmware_async(struct tac5xx2_prv *tac_dev)
1621 {
1622 tac_dev->fw_file_cnt = 0;
1623 tac_dev->fw_files = NULL; /* ready to download files */
1624
1625 return request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
1626 tac_dev->fw_binaryname, tac_dev->dev,
1627 GFP_KERNEL, tac_dev, tac5xx2_fw_ready);
1628 }
1629
tac_download(struct tac5xx2_prv * tac_dev)1630 static int tac_download(struct tac5xx2_prv *tac_dev)
1631 {
1632 struct tac_fw_file *files = tac_dev->fw_files;
1633 u32 num_files = tac_dev->fw_file_cnt;
1634 u32 i;
1635 int ret = 0;
1636
1637 for (i = 0; i < num_files; i++) {
1638 ret = sdw_nwrite_no_pm(tac_dev->sdw_peripheral, files[i].dest_addr,
1639 files[i].length, files[i].fw_data);
1640 if (ret < 0) {
1641 dev_dbg(tac_dev->dev,
1642 "FW write failed at addr 0x%x: %d\n",
1643 files[i].dest_addr, ret);
1644 return ret;
1645 }
1646 }
1647
1648 return 0;
1649 }
1650
1651 /*
1652 * tac5xx2 uses custom firmware binary fw.
1653 * This is not using UMP File Download.
1654 */
tac_download_fw_to_hw(struct tac5xx2_prv * tac_dev)1655 static s32 tac_download_fw_to_hw(struct tac5xx2_prv *tac_dev)
1656 {
1657 int ret;
1658
1659 ret = tac_download(tac_dev);
1660 if (ret < 0) {
1661 dev_err(tac_dev->dev, "Firmware download failed: %d\n", ret);
1662 return ret;
1663 }
1664
1665 dev_dbg(tac_dev->dev, "Firmware download complete: %d chunks\n",
1666 tac_dev->fw_file_cnt);
1667 tac_dev->fw_dl_success = true;
1668
1669 return 0;
1670 }
1671
tac_get_pci_dev(struct sdw_slave * peripheral)1672 static struct pci_dev *tac_get_pci_dev(struct sdw_slave *peripheral)
1673 {
1674 struct device *dev = &peripheral->dev;
1675
1676 for (; dev; dev = dev->parent) {
1677 if (dev_is_pci(dev))
1678 return to_pci_dev(dev);
1679 }
1680
1681 return NULL;
1682 }
1683
tac_generate_fw_name(struct sdw_slave * slave,char * name,size_t size)1684 static void tac_generate_fw_name(struct sdw_slave *slave, char *name, size_t size)
1685 {
1686 struct sdw_bus *bus = slave->bus;
1687 u16 part_id = slave->id.part_id;
1688 u8 unique_id = slave->id.unique_id;
1689 struct pci_dev *pci = tac_get_pci_dev(slave);
1690
1691 if (pci)
1692 scnprintf(name, size, "%04X-%04X-%1X-%1X.bin", part_id,
1693 pci->subsystem_device, bus->link_id, unique_id);
1694 else
1695 /* Default firmware name based on part ID */
1696 scnprintf(name, size, "%s%04x-%1X-%1X.bin",
1697 part_id == 0x2883 ? "tas" : "tac",
1698 part_id, bus->link_id, unique_id);
1699 }
1700
tac_io_init(struct device * dev,struct sdw_slave * slave,bool first)1701 static int tac_io_init(struct device *dev, struct sdw_slave *slave, bool first)
1702 {
1703 struct tac5xx2_prv *tac_dev = dev_get_drvdata(dev);
1704 u64 time;
1705 int ret;
1706
1707 if (tac_dev->hw_init) {
1708 dev_dbg(dev, "early return hw_init already done..");
1709 return 0;
1710 }
1711
1712 time = wait_for_completion_timeout(&tac_dev->fw_caching_complete,
1713 msecs_to_jiffies(TAC5XX2_FW_CACHE_TIMEOUT_MS));
1714 if (!time) {
1715 ret = -ETIMEDOUT;
1716 dev_warn(tac_dev->dev, "%s: fw caching timeout\n", __func__);
1717 goto io_init_err;
1718 }
1719
1720 if (!tac_dev->rev_id) {
1721 ret = regmap_read(tac_dev->regmap, TAC_REV_ID, &tac_dev->rev_id);
1722 if (ret) {
1723 dev_err(tac_dev->dev, "failed to rev id, err=%d\n", ret);
1724 goto io_init_err;
1725 }
1726 dev_dbg(tac_dev->dev, "detected rev_id 0x%x", tac_dev->rev_id);
1727 }
1728
1729 if (tac_dev->fw_files && tac_dev->fw_file_cnt > 0) {
1730 ret = tac_download_fw_to_hw(tac_dev);
1731 if (ret) {
1732 dev_err(tac_dev->dev, "FW download failed, fw: %d\n", ret);
1733 goto io_init_err;
1734 }
1735 }
1736
1737 if (tac_dev->sa_func_data) {
1738 ret = sdca_regmap_write_init(dev, tac_dev->regmap,
1739 tac_dev->sa_func_data);
1740 if (ret) {
1741 dev_err(dev, "smartamp init table update failed\n");
1742 goto io_init_err;
1743 }
1744 dev_dbg(dev, "smartamp init done\n");
1745
1746 if (first) {
1747 ret = regmap_multi_reg_write(tac_dev->regmap, tac_spk_seq,
1748 ARRAY_SIZE(tac_spk_seq));
1749 if (ret) {
1750 dev_err(dev, "init writes failed, err=%d", ret);
1751 goto io_init_err;
1752 }
1753 }
1754 }
1755
1756 if (tac_dev->sm_func_data) {
1757 ret = sdca_regmap_write_init(dev, tac_dev->regmap,
1758 tac_dev->sm_func_data);
1759 if (ret) {
1760 dev_err(dev, "smartmic init table update failed\n");
1761 goto io_init_err;
1762 }
1763 dev_dbg(dev, "smartmic init done\n");
1764
1765 if (first) {
1766 ret = regmap_multi_reg_write(tac_dev->regmap, tac_sm_seq,
1767 ARRAY_SIZE(tac_sm_seq));
1768 if (ret) {
1769 dev_err(tac_dev->dev,
1770 "init writes failed, err=%d", ret);
1771 goto io_init_err;
1772 }
1773 }
1774 }
1775
1776 if (tac_dev->uaj_func_data) {
1777 ret = sdca_regmap_write_init(dev, tac_dev->regmap,
1778 tac_dev->uaj_func_data);
1779 if (ret) {
1780 dev_err(dev, "uaj init table update failed\n");
1781 goto io_init_err;
1782 }
1783 dev_dbg(dev, "uaj init done\n");
1784
1785 if (first) {
1786 ret = regmap_multi_reg_write(tac_dev->regmap, tac_uaj_seq,
1787 ARRAY_SIZE(tac_uaj_seq));
1788 if (ret) {
1789 dev_err(tac_dev->dev,
1790 "init writes failed, err=%d", ret);
1791 goto io_init_err;
1792 }
1793
1794 if (tac_dev->hs_jack) {
1795 ret = tac5xx2_jack_init(tac_dev);
1796 if (ret) {
1797 dev_err(tac_dev->dev, "jack init failed");
1798 goto io_init_err;
1799 }
1800 }
1801 }
1802 }
1803
1804 if (tac_dev->hid_func_data) {
1805 ret = sdca_regmap_write_init(dev, tac_dev->regmap,
1806 tac_dev->hid_func_data);
1807 if (ret) {
1808 dev_err(dev, "hid init table update failed\n");
1809 goto io_init_err;
1810 }
1811 dev_dbg(dev, "hid init done\n");
1812 }
1813
1814 tac_dev->hw_init = true;
1815
1816 return 0;
1817
1818 io_init_err:
1819 dev_err(dev, "init writes failed, err=%d", ret);
1820 return ret;
1821 }
1822
tac_update_status(struct sdw_slave * slave,enum sdw_slave_status status)1823 static int tac_update_status(struct sdw_slave *slave,
1824 enum sdw_slave_status status)
1825 {
1826 struct tac5xx2_prv *tac_dev = dev_get_drvdata(&slave->dev);
1827 struct device *dev = &slave->dev;
1828 bool first = false;
1829 int ret;
1830
1831 tac_dev->status = status;
1832 if (status == SDW_SLAVE_UNATTACHED) {
1833 tac_dev->hw_init = false;
1834 tac_dev->fw_dl_success = false;
1835 }
1836
1837 if (tac_dev->hw_init || tac_dev->status != SDW_SLAVE_ATTACHED) {
1838 dev_dbg(dev, "%s: early return, hw_init=%d, status=%d",
1839 __func__, tac_dev->hw_init, tac_dev->status);
1840 return 0;
1841 }
1842
1843 if (!tac_dev->first_hw_init_done) {
1844 pm_runtime_set_active(tac_dev->dev);
1845 tac_dev->first_hw_init_done = true;
1846 first = true;
1847 }
1848
1849 pm_runtime_get_noresume(tac_dev->dev);
1850
1851 regcache_mark_dirty(tac_dev->regmap);
1852 regcache_cache_only(tac_dev->regmap, false);
1853 ret = tac_io_init(&slave->dev, slave, first);
1854 if (ret) {
1855 dev_err(dev, "Device initialization failed: %d\n", ret);
1856 goto err_out;
1857 }
1858
1859 ret = regcache_sync(tac_dev->regmap);
1860 if (ret)
1861 dev_warn(dev, "Failed to sync regcache after init: %d\n", ret);
1862
1863 err_out:
1864 pm_runtime_mark_last_busy(tac_dev->dev);
1865 pm_runtime_put_autosuspend(tac_dev->dev);
1866
1867 return ret;
1868 }
1869
tac5xx2_sdw_read_prop(struct sdw_slave * peripheral)1870 static int tac5xx2_sdw_read_prop(struct sdw_slave *peripheral)
1871 {
1872 struct device *dev = &peripheral->dev;
1873 int ret;
1874
1875 ret = sdw_slave_read_prop(peripheral);
1876 if (ret) {
1877 dev_err(dev, "sdw_slave_read_prop failed: %d", ret);
1878 return ret;
1879 }
1880
1881 return 0;
1882 }
1883
tac_port_prep(struct sdw_slave * slave,struct sdw_prepare_ch * prep_ch,enum sdw_port_prep_ops pre_ops)1884 static int tac_port_prep(struct sdw_slave *slave, struct sdw_prepare_ch *prep_ch,
1885 enum sdw_port_prep_ops pre_ops)
1886 {
1887 struct device *dev = &slave->dev;
1888 struct tac5xx2_prv *tac_dev = dev_get_drvdata(dev);
1889 unsigned int val;
1890 int ret;
1891
1892 if (pre_ops != SDW_OPS_PORT_POST_PREP)
1893 return 0;
1894
1895 if (!tac_dev->fw_dl_success)
1896 return 0;
1897
1898 ret = regmap_read(tac_dev->regmap, TAC_DSP_ALGO_STATUS, &val);
1899 if (ret) {
1900 dev_err(dev, "Failed to read algo status: %d\n", ret);
1901 return ret;
1902 }
1903
1904 if (val != TAC_DSP_ALGO_STATUS_RUNNING) {
1905 dev_dbg(dev, "Algo not running (0x%02x), re-enabling\n", val);
1906 ret = regmap_write(tac_dev->regmap, TAC_DSP_ALGO_STATUS,
1907 TAC_DSP_ALGO_STATUS_RUNNING);
1908 if (ret) {
1909 dev_err(dev, "Failed to re-enable algo: %d\n", ret);
1910 return ret;
1911 }
1912 }
1913
1914 return 0;
1915 }
1916
1917 static const struct sdw_slave_ops tac_sdw_ops = {
1918 .read_prop = tac5xx2_sdw_read_prop,
1919 .update_status = tac_update_status,
1920 .interrupt_callback = tac_interrupt_callback,
1921 .port_prep = tac_port_prep,
1922 };
1923
tac_sdw_probe(struct sdw_slave * peripheral,const struct sdw_device_id * id)1924 static s32 tac_sdw_probe(struct sdw_slave *peripheral,
1925 const struct sdw_device_id *id)
1926 {
1927 struct sdca_function_data *function_data = NULL;
1928 struct device *dev = &peripheral->dev;
1929 struct tac5xx2_prv *tac_dev;
1930 struct regmap *regmap;
1931 int ret, i;
1932
1933 tac_dev = devm_kzalloc(dev, sizeof(*tac_dev), GFP_KERNEL);
1934 if (!tac_dev)
1935 return dev_err_probe(dev, -ENOMEM,
1936 "Failed devm_kzalloc");
1937
1938 if (peripheral->sdca_data.num_functions > 0) {
1939 dev_dbg(dev, "SDCA functions found: %d",
1940 peripheral->sdca_data.num_functions);
1941
1942 for (i = 0; i < peripheral->sdca_data.num_functions; i++) {
1943 struct sdca_function_data **func_ptr;
1944 const char *func_name;
1945
1946 switch (peripheral->sdca_data.function[i].type) {
1947 case SDCA_FUNCTION_TYPE_SMART_AMP:
1948 func_ptr = &tac_dev->sa_func_data;
1949 func_name = "smartamp";
1950 break;
1951 case SDCA_FUNCTION_TYPE_SMART_MIC:
1952 func_ptr = &tac_dev->sm_func_data;
1953 func_name = "smartmic";
1954 break;
1955 case SDCA_FUNCTION_TYPE_UAJ:
1956 func_ptr = &tac_dev->uaj_func_data;
1957 func_name = "uaj";
1958 break;
1959 case SDCA_FUNCTION_TYPE_HID:
1960 func_ptr = &tac_dev->hid_func_data;
1961 func_name = "hid";
1962 break;
1963 default:
1964 continue;
1965 }
1966
1967 function_data = devm_kzalloc(dev, sizeof(*function_data),
1968 GFP_KERNEL);
1969 if (!function_data)
1970 return dev_err_probe(dev, -ENOMEM,
1971 "failed to allocate %s function data",
1972 func_name);
1973 function_data->desc = &peripheral->sdca_data.function[i];
1974 ret = sdca_parse_function(dev, function_data);
1975 if (!ret)
1976 *func_ptr = function_data;
1977 else
1978 devm_kfree(dev, function_data);
1979 }
1980 }
1981
1982 dev_dbg(dev, "SDCA functions enabled: SA=%s SM=%s UAJ=%s HID=%s",
1983 tac_dev->sa_func_data ? "yes" : "no",
1984 tac_dev->sm_func_data ? "yes" : "no",
1985 tac_dev->uaj_func_data ? "yes" : "no",
1986 tac_dev->hid_func_data ? "yes" : "no");
1987
1988 tac_dev->dev = dev;
1989 tac_dev->sdw_peripheral = peripheral;
1990 tac_dev->hw_init = false;
1991 tac_dev->first_hw_init_done = false;
1992 tac_dev->part_id = id->part_id;
1993 tac_dev->rev_id = 0x0;
1994 dev_set_drvdata(dev, tac_dev);
1995
1996 regmap = devm_regmap_init_sdw_mbq_cfg(&peripheral->dev, peripheral,
1997 &tac_regmap, &tac_mbq_cfg);
1998 if (IS_ERR(regmap))
1999 return dev_err_probe(dev, PTR_ERR(regmap),
2000 "Failed devm_regmap_init_sdw\n");
2001
2002 regcache_cache_only(regmap, true);
2003 tac_dev->regmap = regmap;
2004 tac_dev->jack_type = 0;
2005 init_completion(&tac_dev->fw_caching_complete);
2006
2007 tac_generate_fw_name(peripheral, tac_dev->fw_binaryname,
2008 sizeof(tac_dev->fw_binaryname));
2009
2010 ret = tac_load_and_cache_firmware_async(tac_dev);
2011 if (ret) {
2012 complete_all(&tac_dev->fw_caching_complete);
2013 dev_dbg(dev, "failed to load fw: %d, use rom mode\n", ret);
2014 }
2015
2016 ret = tac_init(tac_dev);
2017 if (ret)
2018 return dev_err_probe(dev, ret,
2019 "failed to initialize tac device\n");
2020
2021 /* set autosuspend parameters */
2022 pm_runtime_set_autosuspend_delay(dev, 3000);
2023 pm_runtime_use_autosuspend(dev);
2024
2025 /* make sure the device does not suspend immediately */
2026 pm_runtime_mark_last_busy(dev);
2027
2028 pm_runtime_enable(dev);
2029 /* the device is still not in active */
2030
2031 return 0;
2032 }
2033
tac_sdw_remove(struct sdw_slave * peripheral)2034 static void tac_sdw_remove(struct sdw_slave *peripheral)
2035 {
2036 struct tac5xx2_prv *tac_dev = dev_get_drvdata(&peripheral->dev);
2037
2038 pm_runtime_disable(tac_dev->dev);
2039
2040 dev_set_drvdata(&peripheral->dev, NULL);
2041 }
2042
2043 static const struct sdw_device_id tac_sdw_id[] = {
2044 SDW_SLAVE_ENTRY(0x0102, 0x5572, 0),
2045 SDW_SLAVE_ENTRY(0x0102, 0x5672, 0),
2046 SDW_SLAVE_ENTRY(0x0102, 0x5682, 0),
2047 SDW_SLAVE_ENTRY(0x0102, 0x2883, 0),
2048 {},
2049 };
2050 MODULE_DEVICE_TABLE(sdw, tac_sdw_id);
2051
2052 static struct sdw_driver tac_sdw_driver = {
2053 .driver = {
2054 .name = "slave-tac5xx2",
2055 .pm = pm_ptr(&tac5xx2_sdca_pm),
2056 },
2057 .probe = tac_sdw_probe,
2058 .remove = tac_sdw_remove,
2059 .ops = &tac_sdw_ops,
2060 .id_table = tac_sdw_id,
2061 };
2062 module_sdw_driver(tac_sdw_driver);
2063
2064 MODULE_IMPORT_NS("SND_SOC_SDCA");
2065 MODULE_AUTHOR("Texas Instruments Inc.");
2066 MODULE_DESCRIPTION("ASoC TAC5XX2 SoundWire Driver");
2067 MODULE_LICENSE("GPL");
2068