1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver core for Samsung SoC onboard UARTs. 4 * 5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics 6 * http://armlinux.simtec.co.uk/ 7 */ 8 9 /* Note on 2410 error handling 10 * 11 * The s3c2410 manual has a love/hate affair with the contents of the 12 * UERSTAT register in the UART blocks, and keeps marking some of the 13 * error bits as reserved. Having checked with the s3c2410x01, 14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED 15 * feature from the latter versions of the manual. 16 * 17 * If it becomes aparrent that latter versions of the 2410 remove these 18 * bits, then action will have to be taken to differentiate the versions 19 * and change the policy on BREAK 20 * 21 * BJD, 04-Nov-2004 22 */ 23 24 #include <linux/console.h> 25 #include <linux/clk.h> 26 #include <linux/cpufreq.h> 27 #include <linux/delay.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/dmaengine.h> 30 #include <linux/init.h> 31 #include <linux/io.h> 32 #include <linux/ioport.h> 33 #include <linux/math.h> 34 #include <linux/module.h> 35 #include <linux/of.h> 36 #include <linux/platform_device.h> 37 #include <linux/serial.h> 38 #include <linux/serial_core.h> 39 #include <linux/serial_s3c.h> 40 #include <linux/slab.h> 41 #include <linux/sysrq.h> 42 #include <linux/tty.h> 43 #include <linux/tty_flip.h> 44 #include <linux/types.h> 45 46 #include <asm/irq.h> 47 48 /* UART name and device definitions */ 49 50 #define S3C24XX_SERIAL_NAME "ttySAC" 51 #define S3C24XX_SERIAL_MAJOR 204 52 #define S3C24XX_SERIAL_MINOR 64 53 54 #ifdef CONFIG_ARM64 55 #define UART_NR 18 56 #else 57 #define UART_NR CONFIG_SERIAL_SAMSUNG_UARTS 58 #endif 59 60 #define S3C24XX_TX_PIO 1 61 #define S3C24XX_TX_DMA 2 62 #define S3C24XX_RX_PIO 1 63 #define S3C24XX_RX_DMA 2 64 65 /* flag to ignore all characters coming in */ 66 #define RXSTAT_DUMMY_READ (0x10000000) 67 68 enum s3c24xx_port_type { 69 TYPE_S3C6400, 70 TYPE_APPLE_S5L, 71 }; 72 73 struct s3c24xx_uart_info { 74 const char *name; 75 enum s3c24xx_port_type type; 76 unsigned int port_type; 77 unsigned int fifosize; 78 u32 rx_fifomask; 79 u32 rx_fifoshift; 80 u32 rx_fifofull; 81 u32 tx_fifomask; 82 u32 tx_fifoshift; 83 u32 tx_fifofull; 84 u32 clksel_mask; 85 u32 clksel_shift; 86 u32 ucon_mask; 87 u8 def_clk_sel; 88 u8 num_clks; 89 u8 iotype; 90 91 /* uart port features */ 92 bool has_divslot; 93 }; 94 95 struct s3c24xx_serial_drv_data { 96 const struct s3c24xx_uart_info info; 97 const struct s3c2410_uartcfg def_cfg; 98 const unsigned int fifosize[UART_NR]; 99 }; 100 101 struct s3c24xx_uart_dma { 102 unsigned int rx_chan_id; 103 unsigned int tx_chan_id; 104 105 struct dma_slave_config rx_conf; 106 struct dma_slave_config tx_conf; 107 108 struct dma_chan *rx_chan; 109 struct dma_chan *tx_chan; 110 111 dma_addr_t rx_addr; 112 dma_addr_t tx_addr; 113 114 dma_cookie_t rx_cookie; 115 dma_cookie_t tx_cookie; 116 117 char *rx_buf; 118 119 dma_addr_t tx_transfer_addr; 120 121 size_t rx_size; 122 size_t tx_size; 123 124 struct dma_async_tx_descriptor *tx_desc; 125 struct dma_async_tx_descriptor *rx_desc; 126 127 int tx_bytes_requested; 128 int rx_bytes_requested; 129 }; 130 131 struct s3c24xx_uart_port { 132 unsigned char rx_enabled; 133 unsigned char tx_enabled; 134 unsigned int pm_level; 135 unsigned long baudclk_rate; 136 unsigned int min_dma_size; 137 138 unsigned int rx_irq; 139 unsigned int tx_irq; 140 141 unsigned int tx_in_progress; 142 unsigned int tx_mode; 143 unsigned int rx_mode; 144 145 const struct s3c24xx_uart_info *info; 146 struct clk *clk; 147 struct clk *baudclk; 148 struct uart_port port; 149 const struct s3c24xx_serial_drv_data *drv_data; 150 151 /* reference to platform data */ 152 const struct s3c2410_uartcfg *cfg; 153 154 struct s3c24xx_uart_dma *dma; 155 }; 156 157 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport); 158 159 /* conversion functions */ 160 161 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev) 162 163 /* register access controls */ 164 165 #define portaddr(port, reg) ((port)->membase + (reg)) 166 #define portaddrl(port, reg) \ 167 ((unsigned long *)(unsigned long)((port)->membase + (reg))) 168 169 static u32 rd_reg(const struct uart_port *port, u32 reg) 170 { 171 switch (port->iotype) { 172 case UPIO_MEM: 173 return readb_relaxed(portaddr(port, reg)); 174 case UPIO_MEM32: 175 return readl_relaxed(portaddr(port, reg)); 176 default: 177 return 0; 178 } 179 return 0; 180 } 181 182 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) 183 184 static void wr_reg(const struct uart_port *port, u32 reg, u32 val) 185 { 186 switch (port->iotype) { 187 case UPIO_MEM: 188 writeb_relaxed(val, portaddr(port, reg)); 189 break; 190 case UPIO_MEM32: 191 writel_relaxed(val, portaddr(port, reg)); 192 break; 193 default: 194 break; 195 } 196 } 197 198 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) 199 200 /* Byte-order aware bit setting/clearing functions. */ 201 202 static inline void s3c24xx_set_bit(const struct uart_port *port, int idx, 203 u32 reg) 204 { 205 unsigned long flags; 206 u32 val; 207 208 local_irq_save(flags); 209 val = rd_regl(port, reg); 210 val |= (1 << idx); 211 wr_regl(port, reg, val); 212 local_irq_restore(flags); 213 } 214 215 static inline void s3c24xx_clear_bit(const struct uart_port *port, int idx, 216 u32 reg) 217 { 218 unsigned long flags; 219 u32 val; 220 221 local_irq_save(flags); 222 val = rd_regl(port, reg); 223 val &= ~(1 << idx); 224 wr_regl(port, reg, val); 225 local_irq_restore(flags); 226 } 227 228 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port) 229 { 230 return container_of(port, struct s3c24xx_uart_port, port); 231 } 232 233 /* translate a port to the device name */ 234 235 static inline const char *s3c24xx_serial_portname(const struct uart_port *port) 236 { 237 return to_platform_device(port->dev)->name; 238 } 239 240 static bool s3c24xx_serial_txempty_nofifo(const struct uart_port *port) 241 { 242 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE; 243 } 244 245 static void s3c24xx_serial_rx_enable(struct uart_port *port) 246 { 247 struct s3c24xx_uart_port *ourport = to_ourport(port); 248 unsigned long flags; 249 int count = 10000; 250 u32 ucon, ufcon; 251 252 uart_port_lock_irqsave(port, &flags); 253 254 while (--count && !s3c24xx_serial_txempty_nofifo(port)) 255 udelay(100); 256 257 ufcon = rd_regl(port, S3C2410_UFCON); 258 ufcon |= S3C2410_UFCON_RESETRX; 259 wr_regl(port, S3C2410_UFCON, ufcon); 260 261 ucon = rd_regl(port, S3C2410_UCON); 262 ucon |= S3C2410_UCON_RXIRQMODE; 263 wr_regl(port, S3C2410_UCON, ucon); 264 265 ourport->rx_enabled = 1; 266 uart_port_unlock_irqrestore(port, flags); 267 } 268 269 static void s3c24xx_serial_rx_disable(struct uart_port *port) 270 { 271 struct s3c24xx_uart_port *ourport = to_ourport(port); 272 unsigned long flags; 273 u32 ucon; 274 275 uart_port_lock_irqsave(port, &flags); 276 277 ucon = rd_regl(port, S3C2410_UCON); 278 ucon &= ~S3C2410_UCON_RXIRQMODE; 279 wr_regl(port, S3C2410_UCON, ucon); 280 281 ourport->rx_enabled = 0; 282 uart_port_unlock_irqrestore(port, flags); 283 } 284 285 static void s3c24xx_serial_stop_tx(struct uart_port *port) 286 { 287 struct s3c24xx_uart_port *ourport = to_ourport(port); 288 struct s3c24xx_uart_dma *dma = ourport->dma; 289 struct dma_tx_state state; 290 int count; 291 292 if (!ourport->tx_enabled) 293 return; 294 295 switch (ourport->info->type) { 296 case TYPE_S3C6400: 297 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); 298 break; 299 case TYPE_APPLE_S5L: 300 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON); 301 break; 302 default: 303 disable_irq_nosync(ourport->tx_irq); 304 break; 305 } 306 307 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) { 308 dmaengine_pause(dma->tx_chan); 309 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); 310 dmaengine_terminate_all(dma->tx_chan); 311 dma_sync_single_for_cpu(dma->tx_chan->device->dev, 312 dma->tx_transfer_addr, dma->tx_size, 313 DMA_TO_DEVICE); 314 async_tx_ack(dma->tx_desc); 315 count = dma->tx_bytes_requested - state.residue; 316 uart_xmit_advance(port, count); 317 } 318 319 ourport->tx_enabled = 0; 320 ourport->tx_in_progress = 0; 321 322 if (port->flags & UPF_CONS_FLOW) 323 s3c24xx_serial_rx_enable(port); 324 325 ourport->tx_mode = 0; 326 } 327 328 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport); 329 330 static void s3c24xx_serial_tx_dma_complete(void *args) 331 { 332 struct s3c24xx_uart_port *ourport = args; 333 struct uart_port *port = &ourport->port; 334 struct tty_port *tport = &port->state->port; 335 struct s3c24xx_uart_dma *dma = ourport->dma; 336 struct dma_tx_state state; 337 unsigned long flags; 338 int count; 339 340 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); 341 count = dma->tx_bytes_requested - state.residue; 342 async_tx_ack(dma->tx_desc); 343 344 dma_sync_single_for_cpu(dma->tx_chan->device->dev, 345 dma->tx_transfer_addr, dma->tx_size, 346 DMA_TO_DEVICE); 347 348 uart_port_lock_irqsave(port, &flags); 349 350 uart_xmit_advance(port, count); 351 ourport->tx_in_progress = 0; 352 353 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 354 uart_write_wakeup(port); 355 356 s3c24xx_serial_start_next_tx(ourport); 357 uart_port_unlock_irqrestore(port, flags); 358 } 359 360 static void enable_tx_dma(struct s3c24xx_uart_port *ourport) 361 { 362 const struct uart_port *port = &ourport->port; 363 u32 ucon; 364 365 /* Mask Tx interrupt */ 366 switch (ourport->info->type) { 367 case TYPE_S3C6400: 368 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); 369 break; 370 case TYPE_APPLE_S5L: 371 WARN_ON(1); // No DMA 372 break; 373 default: 374 disable_irq_nosync(ourport->tx_irq); 375 break; 376 } 377 378 /* Enable tx dma mode */ 379 ucon = rd_regl(port, S3C2410_UCON); 380 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK); 381 ucon |= S3C64XX_UCON_TXBURST_1; 382 ucon |= S3C64XX_UCON_TXMODE_DMA; 383 wr_regl(port, S3C2410_UCON, ucon); 384 385 ourport->tx_mode = S3C24XX_TX_DMA; 386 } 387 388 static void enable_tx_pio(struct s3c24xx_uart_port *ourport) 389 { 390 const struct uart_port *port = &ourport->port; 391 u32 ucon, ufcon; 392 393 /* Set ufcon txtrig */ 394 ourport->tx_in_progress = S3C24XX_TX_PIO; 395 ufcon = rd_regl(port, S3C2410_UFCON); 396 wr_regl(port, S3C2410_UFCON, ufcon); 397 398 /* Enable tx pio mode */ 399 ucon = rd_regl(port, S3C2410_UCON); 400 ucon &= ~(S3C64XX_UCON_TXMODE_MASK); 401 ucon |= S3C64XX_UCON_TXMODE_CPU; 402 wr_regl(port, S3C2410_UCON, ucon); 403 404 /* Unmask Tx interrupt */ 405 switch (ourport->info->type) { 406 case TYPE_S3C6400: 407 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD, 408 S3C64XX_UINTM); 409 break; 410 case TYPE_APPLE_S5L: 411 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK; 412 wr_regl(port, S3C2410_UCON, ucon); 413 break; 414 default: 415 enable_irq(ourport->tx_irq); 416 break; 417 } 418 419 ourport->tx_mode = S3C24XX_TX_PIO; 420 421 /* 422 * The Apple version only has edge triggered TX IRQs, so we need 423 * to kick off the process by sending some characters here. 424 */ 425 if (ourport->info->type == TYPE_APPLE_S5L) 426 s3c24xx_serial_tx_chars(ourport); 427 } 428 429 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport) 430 { 431 if (ourport->tx_mode != S3C24XX_TX_PIO) 432 enable_tx_pio(ourport); 433 } 434 435 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport, 436 unsigned int count, unsigned int tail) 437 { 438 struct s3c24xx_uart_dma *dma = ourport->dma; 439 440 if (ourport->tx_mode != S3C24XX_TX_DMA) 441 enable_tx_dma(ourport); 442 443 dma->tx_size = count & ~(dma_get_cache_alignment() - 1); 444 dma->tx_transfer_addr = dma->tx_addr + tail; 445 446 dma_sync_single_for_device(dma->tx_chan->device->dev, 447 dma->tx_transfer_addr, dma->tx_size, 448 DMA_TO_DEVICE); 449 450 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan, 451 dma->tx_transfer_addr, dma->tx_size, 452 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 453 if (!dma->tx_desc) { 454 dev_err(ourport->port.dev, "Unable to get desc for Tx\n"); 455 return -EIO; 456 } 457 458 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete; 459 dma->tx_desc->callback_param = ourport; 460 dma->tx_bytes_requested = dma->tx_size; 461 462 ourport->tx_in_progress = S3C24XX_TX_DMA; 463 dma->tx_cookie = dmaengine_submit(dma->tx_desc); 464 dma_async_issue_pending(dma->tx_chan); 465 return 0; 466 } 467 468 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport) 469 { 470 struct uart_port *port = &ourport->port; 471 struct tty_port *tport = &port->state->port; 472 unsigned int count, tail; 473 474 /* Get data size up to the end of buffer */ 475 count = kfifo_out_linear(&tport->xmit_fifo, &tail, UART_XMIT_SIZE); 476 477 if (!count) { 478 s3c24xx_serial_stop_tx(port); 479 return; 480 } 481 482 if (!ourport->dma || !ourport->dma->tx_chan || 483 count < ourport->min_dma_size || 484 tail & (dma_get_cache_alignment() - 1)) 485 s3c24xx_serial_start_tx_pio(ourport); 486 else 487 s3c24xx_serial_start_tx_dma(ourport, count, tail); 488 } 489 490 static void s3c24xx_serial_start_tx(struct uart_port *port) 491 { 492 struct s3c24xx_uart_port *ourport = to_ourport(port); 493 struct tty_port *tport = &port->state->port; 494 495 if (!ourport->tx_enabled) { 496 if (port->flags & UPF_CONS_FLOW) 497 s3c24xx_serial_rx_disable(port); 498 499 ourport->tx_enabled = 1; 500 if (!ourport->dma || !ourport->dma->tx_chan) 501 s3c24xx_serial_start_tx_pio(ourport); 502 } 503 504 if (ourport->dma && ourport->dma->tx_chan) { 505 if (!kfifo_is_empty(&tport->xmit_fifo) && 506 !ourport->tx_in_progress) 507 s3c24xx_serial_start_next_tx(ourport); 508 } 509 } 510 511 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport, 512 struct tty_port *tty, int count) 513 { 514 struct s3c24xx_uart_dma *dma = ourport->dma; 515 int copied; 516 517 if (!count) 518 return; 519 520 dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr, 521 dma->rx_size, DMA_FROM_DEVICE); 522 523 ourport->port.icount.rx += count; 524 if (!tty) { 525 dev_err(ourport->port.dev, "No tty port\n"); 526 return; 527 } 528 copied = tty_insert_flip_string(tty, 529 ((unsigned char *)(ourport->dma->rx_buf)), count); 530 if (copied != count) { 531 WARN_ON(1); 532 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n"); 533 } 534 } 535 536 static void s3c24xx_serial_stop_rx(struct uart_port *port) 537 { 538 struct s3c24xx_uart_port *ourport = to_ourport(port); 539 struct s3c24xx_uart_dma *dma = ourport->dma; 540 struct tty_port *t = &port->state->port; 541 struct dma_tx_state state; 542 enum dma_status dma_status; 543 unsigned int received; 544 545 if (ourport->rx_enabled) { 546 dev_dbg(port->dev, "stopping rx\n"); 547 switch (ourport->info->type) { 548 case TYPE_S3C6400: 549 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD, 550 S3C64XX_UINTM); 551 break; 552 case TYPE_APPLE_S5L: 553 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); 554 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON); 555 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_LEGACY_ENA, S3C2410_UCON); 556 break; 557 default: 558 disable_irq_nosync(ourport->rx_irq); 559 break; 560 } 561 ourport->rx_enabled = 0; 562 } 563 if (dma && dma->rx_chan) { 564 dmaengine_pause(dma->tx_chan); 565 dma_status = dmaengine_tx_status(dma->rx_chan, 566 dma->rx_cookie, &state); 567 if (dma_status == DMA_IN_PROGRESS || 568 dma_status == DMA_PAUSED) { 569 received = dma->rx_bytes_requested - state.residue; 570 dmaengine_terminate_all(dma->rx_chan); 571 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 572 } 573 } 574 } 575 576 static inline const struct s3c24xx_uart_info 577 *s3c24xx_port_to_info(struct uart_port *port) 578 { 579 return to_ourport(port)->info; 580 } 581 582 static inline const struct s3c2410_uartcfg 583 *s3c24xx_port_to_cfg(const struct uart_port *port) 584 { 585 const struct s3c24xx_uart_port *ourport; 586 587 if (port->dev == NULL) 588 return NULL; 589 590 ourport = container_of(port, struct s3c24xx_uart_port, port); 591 return ourport->cfg; 592 } 593 594 static unsigned int 595 s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port *ourport, u32 ufstat) 596 { 597 const struct s3c24xx_uart_info *info = ourport->info; 598 599 if (ufstat & info->rx_fifofull) 600 return ourport->port.fifosize; 601 602 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift; 603 } 604 605 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport); 606 static void s3c24xx_serial_rx_dma_complete(void *args) 607 { 608 struct s3c24xx_uart_port *ourport = args; 609 struct uart_port *port = &ourport->port; 610 611 struct s3c24xx_uart_dma *dma = ourport->dma; 612 struct tty_port *t = &port->state->port; 613 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); 614 615 struct dma_tx_state state; 616 unsigned long flags; 617 int received; 618 619 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); 620 received = dma->rx_bytes_requested - state.residue; 621 async_tx_ack(dma->rx_desc); 622 623 uart_port_lock_irqsave(port, &flags); 624 625 if (received) 626 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 627 628 if (tty) { 629 tty_flip_buffer_push(t); 630 tty_kref_put(tty); 631 } 632 633 s3c64xx_start_rx_dma(ourport); 634 635 uart_port_unlock_irqrestore(port, flags); 636 } 637 638 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport) 639 { 640 struct s3c24xx_uart_dma *dma = ourport->dma; 641 642 dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr, 643 dma->rx_size, DMA_FROM_DEVICE); 644 645 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan, 646 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM, 647 DMA_PREP_INTERRUPT); 648 if (!dma->rx_desc) { 649 dev_err(ourport->port.dev, "Unable to get desc for Rx\n"); 650 return; 651 } 652 653 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete; 654 dma->rx_desc->callback_param = ourport; 655 dma->rx_bytes_requested = dma->rx_size; 656 657 dma->rx_cookie = dmaengine_submit(dma->rx_desc); 658 dma_async_issue_pending(dma->rx_chan); 659 } 660 661 /* ? - where has parity gone?? */ 662 #define S3C2410_UERSTAT_PARITY (0x1000) 663 664 static void enable_rx_dma(struct s3c24xx_uart_port *ourport) 665 { 666 struct uart_port *port = &ourport->port; 667 u32 ucon; 668 669 /* set Rx mode to DMA mode */ 670 ucon = rd_regl(port, S3C2410_UCON); 671 ucon &= ~(S3C64XX_UCON_RXBURST_MASK | 672 S3C64XX_UCON_TIMEOUT_MASK | 673 S3C64XX_UCON_EMPTYINT_EN | 674 S3C64XX_UCON_DMASUS_EN | 675 S3C64XX_UCON_TIMEOUT_EN | 676 S3C64XX_UCON_RXMODE_MASK); 677 ucon |= S3C64XX_UCON_RXBURST_1 | 678 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | 679 S3C64XX_UCON_EMPTYINT_EN | 680 S3C64XX_UCON_TIMEOUT_EN | 681 S3C64XX_UCON_RXMODE_DMA; 682 wr_regl(port, S3C2410_UCON, ucon); 683 684 ourport->rx_mode = S3C24XX_RX_DMA; 685 } 686 687 static void enable_rx_pio(struct s3c24xx_uart_port *ourport) 688 { 689 struct uart_port *port = &ourport->port; 690 u32 ucon; 691 692 /* set Rx mode to DMA mode */ 693 ucon = rd_regl(port, S3C2410_UCON); 694 ucon &= ~S3C64XX_UCON_RXMODE_MASK; 695 ucon |= S3C64XX_UCON_RXMODE_CPU; 696 697 /* Apple types use these bits for IRQ masks */ 698 if (ourport->info->type != TYPE_APPLE_S5L) { 699 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK | 700 S3C64XX_UCON_EMPTYINT_EN | 701 S3C64XX_UCON_DMASUS_EN | 702 S3C64XX_UCON_TIMEOUT_EN); 703 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | 704 S3C64XX_UCON_TIMEOUT_EN; 705 } 706 wr_regl(port, S3C2410_UCON, ucon); 707 708 ourport->rx_mode = S3C24XX_RX_PIO; 709 } 710 711 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport); 712 713 static irqreturn_t s3c24xx_serial_rx_chars_dma(struct s3c24xx_uart_port *ourport) 714 { 715 struct uart_port *port = &ourport->port; 716 struct s3c24xx_uart_dma *dma = ourport->dma; 717 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); 718 struct tty_port *t = &port->state->port; 719 struct dma_tx_state state; 720 unsigned int received; 721 u32 utrstat; 722 723 utrstat = rd_regl(port, S3C2410_UTRSTAT); 724 rd_regl(port, S3C2410_UFSTAT); 725 726 uart_port_lock(port); 727 728 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) { 729 s3c64xx_start_rx_dma(ourport); 730 if (ourport->rx_mode == S3C24XX_RX_PIO) 731 enable_rx_dma(ourport); 732 goto finish; 733 } 734 735 if (ourport->rx_mode == S3C24XX_RX_DMA) { 736 dmaengine_pause(dma->rx_chan); 737 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); 738 dmaengine_terminate_all(dma->rx_chan); 739 received = dma->rx_bytes_requested - state.residue; 740 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 741 742 enable_rx_pio(ourport); 743 } 744 745 s3c24xx_serial_rx_drain_fifo(ourport); 746 747 if (tty) { 748 tty_flip_buffer_push(t); 749 tty_kref_put(tty); 750 } 751 752 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT); 753 754 finish: 755 uart_port_unlock(port); 756 757 return IRQ_HANDLED; 758 } 759 760 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport) 761 { 762 struct uart_port *port = &ourport->port; 763 unsigned int max_count = port->fifosize; 764 unsigned int fifocnt = 0; 765 u32 ufcon, ufstat, uerstat; 766 u8 ch, flag; 767 768 while (max_count-- > 0) { 769 /* 770 * Receive all characters known to be in FIFO 771 * before reading FIFO level again 772 */ 773 if (fifocnt == 0) { 774 ufstat = rd_regl(port, S3C2410_UFSTAT); 775 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat); 776 if (fifocnt == 0) 777 break; 778 } 779 fifocnt--; 780 781 uerstat = rd_regl(port, S3C2410_UERSTAT); 782 ch = rd_reg(port, S3C2410_URXH); 783 784 if (port->flags & UPF_CONS_FLOW) { 785 bool txe = s3c24xx_serial_txempty_nofifo(port); 786 787 if (ourport->rx_enabled) { 788 if (!txe) { 789 ourport->rx_enabled = 0; 790 continue; 791 } 792 } else { 793 if (txe) { 794 ufcon = rd_regl(port, S3C2410_UFCON); 795 ufcon |= S3C2410_UFCON_RESETRX; 796 wr_regl(port, S3C2410_UFCON, ufcon); 797 ourport->rx_enabled = 1; 798 return; 799 } 800 continue; 801 } 802 } 803 804 /* insert the character into the buffer */ 805 806 flag = TTY_NORMAL; 807 port->icount.rx++; 808 809 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) { 810 dev_dbg(port->dev, 811 "rxerr: port ch=0x%02x, rxs=0x%08x\n", 812 ch, uerstat); 813 814 /* check for break */ 815 if (uerstat & S3C2410_UERSTAT_BREAK) { 816 dev_dbg(port->dev, "break!\n"); 817 port->icount.brk++; 818 if (uart_handle_break(port)) 819 continue; /* Ignore character */ 820 } 821 822 if (uerstat & S3C2410_UERSTAT_FRAME) 823 port->icount.frame++; 824 if (uerstat & S3C2410_UERSTAT_OVERRUN) 825 port->icount.overrun++; 826 827 uerstat &= port->read_status_mask; 828 829 if (uerstat & S3C2410_UERSTAT_BREAK) 830 flag = TTY_BREAK; 831 else if (uerstat & S3C2410_UERSTAT_PARITY) 832 flag = TTY_PARITY; 833 else if (uerstat & (S3C2410_UERSTAT_FRAME | 834 S3C2410_UERSTAT_OVERRUN)) 835 flag = TTY_FRAME; 836 } 837 838 if (uart_handle_sysrq_char(port, ch)) 839 continue; /* Ignore character */ 840 841 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, 842 ch, flag); 843 } 844 845 tty_flip_buffer_push(&port->state->port); 846 } 847 848 static irqreturn_t s3c24xx_serial_rx_chars_pio(struct s3c24xx_uart_port *ourport) 849 { 850 struct uart_port *port = &ourport->port; 851 852 uart_port_lock(port); 853 s3c24xx_serial_rx_drain_fifo(ourport); 854 uart_port_unlock(port); 855 856 return IRQ_HANDLED; 857 } 858 859 static irqreturn_t s3c24xx_serial_rx_irq(struct s3c24xx_uart_port *ourport) 860 { 861 if (ourport->dma && ourport->dma->rx_chan) 862 return s3c24xx_serial_rx_chars_dma(ourport); 863 return s3c24xx_serial_rx_chars_pio(ourport); 864 } 865 866 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport) 867 { 868 struct uart_port *port = &ourport->port; 869 struct tty_port *tport = &port->state->port; 870 unsigned int count, dma_count = 0, tail; 871 872 count = kfifo_out_linear(&tport->xmit_fifo, &tail, UART_XMIT_SIZE); 873 874 if (ourport->dma && ourport->dma->tx_chan && 875 count >= ourport->min_dma_size) { 876 int align = dma_get_cache_alignment() - 877 (tail & (dma_get_cache_alignment() - 1)); 878 if (count - align >= ourport->min_dma_size) { 879 dma_count = count - align; 880 count = align; 881 tail += align; 882 } 883 } 884 885 if (port->x_char) { 886 wr_reg(port, S3C2410_UTXH, port->x_char); 887 port->icount.tx++; 888 port->x_char = 0; 889 return; 890 } 891 892 /* if there isn't anything more to transmit, or the uart is now 893 * stopped, disable the uart and exit 894 */ 895 896 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) { 897 s3c24xx_serial_stop_tx(port); 898 return; 899 } 900 901 /* try and drain the buffer... */ 902 903 if (count > port->fifosize) { 904 count = port->fifosize; 905 dma_count = 0; 906 } 907 908 while (!(rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)) { 909 unsigned char ch; 910 911 if (!uart_fifo_get(port, &ch)) 912 break; 913 914 wr_reg(port, S3C2410_UTXH, ch); 915 count--; 916 } 917 918 if (!count && dma_count) { 919 s3c24xx_serial_start_tx_dma(ourport, dma_count, tail); 920 return; 921 } 922 923 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 924 uart_write_wakeup(port); 925 926 if (kfifo_is_empty(&tport->xmit_fifo)) 927 s3c24xx_serial_stop_tx(port); 928 } 929 930 static irqreturn_t s3c24xx_serial_tx_irq(struct s3c24xx_uart_port *ourport) 931 { 932 struct uart_port *port = &ourport->port; 933 934 uart_port_lock(port); 935 936 s3c24xx_serial_tx_chars(ourport); 937 938 uart_port_unlock(port); 939 return IRQ_HANDLED; 940 } 941 942 /* interrupt handler for s3c64xx and later SoC's.*/ 943 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id) 944 { 945 struct s3c24xx_uart_port *ourport = id; 946 const struct uart_port *port = &ourport->port; 947 u32 pend = rd_regl(port, S3C64XX_UINTP); 948 irqreturn_t ret = IRQ_HANDLED; 949 950 if (pend & S3C64XX_UINTM_RXD_MSK) { 951 ret = s3c24xx_serial_rx_irq(ourport); 952 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK); 953 } 954 if (pend & S3C64XX_UINTM_TXD_MSK) { 955 ret = s3c24xx_serial_tx_irq(ourport); 956 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK); 957 } 958 return ret; 959 } 960 961 /* interrupt handler for Apple SoC's.*/ 962 static irqreturn_t apple_serial_handle_irq(int irq, void *id) 963 { 964 struct s3c24xx_uart_port *ourport = id; 965 const struct uart_port *port = &ourport->port; 966 u32 pend = rd_regl(port, S3C2410_UTRSTAT); 967 irqreturn_t ret = IRQ_NONE; 968 969 if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO | 970 APPLE_S5L_UTRSTAT_RXTO_LEGACY)) { 971 wr_regl(port, S3C2410_UTRSTAT, 972 APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO | 973 APPLE_S5L_UTRSTAT_RXTO_LEGACY); 974 ret = s3c24xx_serial_rx_irq(ourport); 975 } 976 if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) { 977 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH); 978 ret = s3c24xx_serial_tx_irq(ourport); 979 } 980 981 return ret; 982 } 983 984 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) 985 { 986 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 987 u32 ufstat = rd_regl(port, S3C2410_UFSTAT); 988 u32 ufcon = rd_regl(port, S3C2410_UFCON); 989 990 if (ufcon & S3C2410_UFCON_FIFOMODE) { 991 if ((ufstat & info->tx_fifomask) || 992 (ufstat & info->tx_fifofull)) 993 return 0; 994 return TIOCSER_TEMT; 995 } 996 997 return s3c24xx_serial_txempty_nofifo(port) ? TIOCSER_TEMT : 0; 998 } 999 1000 /* no modem control lines */ 1001 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) 1002 { 1003 u32 umstat = rd_reg(port, S3C2410_UMSTAT); 1004 1005 if (umstat & S3C2410_UMSTAT_CTS) 1006 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 1007 else 1008 return TIOCM_CAR | TIOCM_DSR; 1009 } 1010 1011 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) 1012 { 1013 u32 umcon = rd_regl(port, S3C2410_UMCON); 1014 u32 ucon = rd_regl(port, S3C2410_UCON); 1015 1016 if (mctrl & TIOCM_RTS) 1017 umcon |= S3C2410_UMCOM_RTS_LOW; 1018 else 1019 umcon &= ~S3C2410_UMCOM_RTS_LOW; 1020 1021 wr_regl(port, S3C2410_UMCON, umcon); 1022 1023 if (mctrl & TIOCM_LOOP) 1024 ucon |= S3C2410_UCON_LOOPBACK; 1025 else 1026 ucon &= ~S3C2410_UCON_LOOPBACK; 1027 1028 wr_regl(port, S3C2410_UCON, ucon); 1029 } 1030 1031 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state) 1032 { 1033 unsigned long flags; 1034 u32 ucon; 1035 1036 uart_port_lock_irqsave(port, &flags); 1037 1038 ucon = rd_regl(port, S3C2410_UCON); 1039 1040 if (break_state) 1041 ucon |= S3C2410_UCON_SBREAK; 1042 else 1043 ucon &= ~S3C2410_UCON_SBREAK; 1044 1045 wr_regl(port, S3C2410_UCON, ucon); 1046 1047 uart_port_unlock_irqrestore(port, flags); 1048 } 1049 1050 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p) 1051 { 1052 struct s3c24xx_uart_dma *dma = p->dma; 1053 struct dma_slave_caps dma_caps; 1054 const char *reason = NULL; 1055 int ret; 1056 1057 /* Default slave configuration parameters */ 1058 dma->rx_conf.direction = DMA_DEV_TO_MEM; 1059 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1060 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH; 1061 dma->rx_conf.src_maxburst = 1; 1062 1063 dma->tx_conf.direction = DMA_MEM_TO_DEV; 1064 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1065 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH; 1066 dma->tx_conf.dst_maxburst = 1; 1067 1068 dma->rx_chan = dma_request_chan(p->port.dev, "rx"); 1069 1070 if (IS_ERR(dma->rx_chan)) { 1071 reason = "DMA RX channel request failed"; 1072 ret = PTR_ERR(dma->rx_chan); 1073 goto err_warn; 1074 } 1075 1076 ret = dma_get_slave_caps(dma->rx_chan, &dma_caps); 1077 if (ret < 0 || 1078 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { 1079 reason = "insufficient DMA RX engine capabilities"; 1080 ret = -EOPNOTSUPP; 1081 goto err_release_rx; 1082 } 1083 1084 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf); 1085 1086 dma->tx_chan = dma_request_chan(p->port.dev, "tx"); 1087 if (IS_ERR(dma->tx_chan)) { 1088 reason = "DMA TX channel request failed"; 1089 ret = PTR_ERR(dma->tx_chan); 1090 goto err_release_rx; 1091 } 1092 1093 ret = dma_get_slave_caps(dma->tx_chan, &dma_caps); 1094 if (ret < 0 || 1095 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { 1096 reason = "insufficient DMA TX engine capabilities"; 1097 ret = -EOPNOTSUPP; 1098 goto err_release_tx; 1099 } 1100 1101 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf); 1102 1103 /* RX buffer */ 1104 dma->rx_size = PAGE_SIZE; 1105 1106 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL); 1107 if (!dma->rx_buf) { 1108 ret = -ENOMEM; 1109 goto err_release_tx; 1110 } 1111 1112 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf, 1113 dma->rx_size, DMA_FROM_DEVICE); 1114 if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) { 1115 reason = "DMA mapping error for RX buffer"; 1116 ret = -EIO; 1117 goto err_free_rx; 1118 } 1119 1120 /* TX buffer */ 1121 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev, 1122 p->port.state->port.xmit_buf, 1123 UART_XMIT_SIZE, 1124 DMA_TO_DEVICE); 1125 if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) { 1126 reason = "DMA mapping error for TX buffer"; 1127 ret = -EIO; 1128 goto err_unmap_rx; 1129 } 1130 1131 return 0; 1132 1133 err_unmap_rx: 1134 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr, 1135 dma->rx_size, DMA_FROM_DEVICE); 1136 err_free_rx: 1137 kfree(dma->rx_buf); 1138 err_release_tx: 1139 dma_release_channel(dma->tx_chan); 1140 err_release_rx: 1141 dma_release_channel(dma->rx_chan); 1142 err_warn: 1143 if (reason) 1144 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason); 1145 return ret; 1146 } 1147 1148 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p) 1149 { 1150 struct s3c24xx_uart_dma *dma = p->dma; 1151 1152 if (dma->rx_chan) { 1153 dmaengine_terminate_all(dma->rx_chan); 1154 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr, 1155 dma->rx_size, DMA_FROM_DEVICE); 1156 kfree(dma->rx_buf); 1157 dma_release_channel(dma->rx_chan); 1158 dma->rx_chan = NULL; 1159 } 1160 1161 if (dma->tx_chan) { 1162 dmaengine_terminate_all(dma->tx_chan); 1163 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr, 1164 UART_XMIT_SIZE, DMA_TO_DEVICE); 1165 dma_release_channel(dma->tx_chan); 1166 dma->tx_chan = NULL; 1167 } 1168 } 1169 1170 static void s3c64xx_serial_shutdown(struct uart_port *port) 1171 { 1172 struct s3c24xx_uart_port *ourport = to_ourport(port); 1173 1174 ourport->tx_enabled = 0; 1175 ourport->tx_mode = 0; 1176 ourport->rx_enabled = 0; 1177 1178 free_irq(port->irq, ourport); 1179 1180 wr_regl(port, S3C64XX_UINTP, 0xf); 1181 wr_regl(port, S3C64XX_UINTM, 0xf); 1182 1183 if (ourport->dma) 1184 s3c24xx_serial_release_dma(ourport); 1185 1186 ourport->tx_in_progress = 0; 1187 } 1188 1189 static void apple_s5l_serial_shutdown(struct uart_port *port) 1190 { 1191 struct s3c24xx_uart_port *ourport = to_ourport(port); 1192 1193 u32 ucon; 1194 1195 ucon = rd_regl(port, S3C2410_UCON); 1196 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 1197 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 1198 APPLE_S5L_UCON_RXTO_ENA_MSK | 1199 APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK); 1200 wr_regl(port, S3C2410_UCON, ucon); 1201 1202 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 1203 1204 free_irq(port->irq, ourport); 1205 1206 ourport->tx_enabled = 0; 1207 ourport->tx_mode = 0; 1208 ourport->rx_enabled = 0; 1209 1210 if (ourport->dma) 1211 s3c24xx_serial_release_dma(ourport); 1212 1213 ourport->tx_in_progress = 0; 1214 } 1215 1216 static int s3c64xx_serial_startup(struct uart_port *port) 1217 { 1218 struct s3c24xx_uart_port *ourport = to_ourport(port); 1219 unsigned long flags; 1220 u32 ufcon; 1221 int ret; 1222 1223 wr_regl(port, S3C64XX_UINTM, 0xf); 1224 if (ourport->dma) { 1225 ret = s3c24xx_serial_request_dma(ourport); 1226 if (ret < 0) { 1227 devm_kfree(port->dev, ourport->dma); 1228 ourport->dma = NULL; 1229 } 1230 } 1231 1232 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED, 1233 s3c24xx_serial_portname(port), ourport); 1234 if (ret) { 1235 dev_err(port->dev, "cannot get irq %d\n", port->irq); 1236 return ret; 1237 } 1238 1239 /* For compatibility with s3c24xx Soc's */ 1240 ourport->rx_enabled = 1; 1241 ourport->tx_enabled = 0; 1242 1243 uart_port_lock_irqsave(port, &flags); 1244 1245 ufcon = rd_regl(port, S3C2410_UFCON); 1246 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; 1247 if (!uart_console(port)) 1248 ufcon |= S3C2410_UFCON_RESETTX; 1249 wr_regl(port, S3C2410_UFCON, ufcon); 1250 1251 enable_rx_pio(ourport); 1252 1253 uart_port_unlock_irqrestore(port, flags); 1254 1255 /* Enable Rx Interrupt */ 1256 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM); 1257 1258 return ret; 1259 } 1260 1261 static int apple_s5l_serial_startup(struct uart_port *port) 1262 { 1263 struct s3c24xx_uart_port *ourport = to_ourport(port); 1264 unsigned long flags; 1265 u32 ufcon; 1266 int ret; 1267 1268 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 1269 1270 ret = request_irq(port->irq, apple_serial_handle_irq, 0, 1271 s3c24xx_serial_portname(port), ourport); 1272 if (ret) { 1273 dev_err(port->dev, "cannot get irq %d\n", port->irq); 1274 return ret; 1275 } 1276 1277 /* For compatibility with s3c24xx Soc's */ 1278 ourport->rx_enabled = 1; 1279 ourport->tx_enabled = 0; 1280 1281 uart_port_lock_irqsave(port, &flags); 1282 1283 ufcon = rd_regl(port, S3C2410_UFCON); 1284 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; 1285 if (!uart_console(port)) 1286 ufcon |= S3C2410_UFCON_RESETTX; 1287 wr_regl(port, S3C2410_UFCON, ufcon); 1288 1289 enable_rx_pio(ourport); 1290 1291 uart_port_unlock_irqrestore(port, flags); 1292 1293 /* Enable Rx Interrupt */ 1294 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); 1295 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON); 1296 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_LEGACY_ENA, S3C2410_UCON); 1297 1298 return ret; 1299 } 1300 1301 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, 1302 unsigned int old) 1303 { 1304 struct s3c24xx_uart_port *ourport = to_ourport(port); 1305 int timeout = 10000; 1306 1307 ourport->pm_level = level; 1308 1309 switch (level) { 1310 case 3: 1311 while (--timeout && !s3c24xx_serial_txempty_nofifo(port)) 1312 udelay(100); 1313 1314 if (!IS_ERR(ourport->baudclk)) 1315 clk_disable_unprepare(ourport->baudclk); 1316 1317 clk_disable_unprepare(ourport->clk); 1318 break; 1319 1320 case 0: 1321 clk_prepare_enable(ourport->clk); 1322 1323 if (!IS_ERR(ourport->baudclk)) 1324 clk_prepare_enable(ourport->baudclk); 1325 break; 1326 default: 1327 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level); 1328 } 1329 } 1330 1331 /* baud rate calculation 1332 * 1333 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number 1334 * of different sources, including the peripheral clock ("pclk") and an 1335 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk") 1336 * with a programmable extra divisor. 1337 * 1338 * The following code goes through the clock sources, and calculates the 1339 * baud clocks (and the resultant actual baud rates) and then tries to 1340 * pick the closest one and select that. 1341 * 1342 */ 1343 1344 #define MAX_CLK_NAME_LENGTH 15 1345 1346 static inline u8 s3c24xx_serial_getsource(struct uart_port *port) 1347 { 1348 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1349 u32 ucon; 1350 1351 if (info->num_clks == 1) 1352 return 0; 1353 1354 ucon = rd_regl(port, S3C2410_UCON); 1355 ucon &= info->clksel_mask; 1356 return ucon >> info->clksel_shift; 1357 } 1358 1359 static void s3c24xx_serial_setsource(struct uart_port *port, u8 clk_sel) 1360 { 1361 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1362 u32 ucon; 1363 1364 if (info->num_clks == 1) 1365 return; 1366 1367 ucon = rd_regl(port, S3C2410_UCON); 1368 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel) 1369 return; 1370 1371 ucon &= ~info->clksel_mask; 1372 ucon |= clk_sel << info->clksel_shift; 1373 wr_regl(port, S3C2410_UCON, ucon); 1374 } 1375 1376 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport, 1377 unsigned int req_baud, struct clk **best_clk, 1378 u8 *clk_num) 1379 { 1380 const struct s3c24xx_uart_info *info = ourport->info; 1381 struct clk *clk; 1382 unsigned long rate; 1383 unsigned int baud, quot, best_quot = 0; 1384 char clkname[MAX_CLK_NAME_LENGTH]; 1385 int calc_deviation, deviation = (1 << 30) - 1; 1386 u8 cnt; 1387 1388 for (cnt = 0; cnt < info->num_clks; cnt++) { 1389 /* Keep selected clock if provided */ 1390 if (ourport->cfg->clk_sel && 1391 !(ourport->cfg->clk_sel & (1 << cnt))) 1392 continue; 1393 1394 sprintf(clkname, "clk_uart_baud%d", cnt); 1395 clk = clk_get(ourport->port.dev, clkname); 1396 if (IS_ERR(clk)) 1397 continue; 1398 1399 rate = clk_get_rate(clk); 1400 if (!rate) { 1401 dev_err(ourport->port.dev, 1402 "Failed to get clock rate for %s.\n", clkname); 1403 clk_put(clk); 1404 continue; 1405 } 1406 1407 if (ourport->info->has_divslot) { 1408 unsigned long div = rate / req_baud; 1409 1410 /* The UDIVSLOT register on the newer UARTs allows us to 1411 * get a divisor adjustment of 1/16th on the baud clock. 1412 * 1413 * We don't keep the UDIVSLOT value (the 16ths we 1414 * calculated by not multiplying the baud by 16) as it 1415 * is easy enough to recalculate. 1416 */ 1417 1418 quot = div / 16; 1419 baud = rate / div; 1420 } else { 1421 quot = (rate + (8 * req_baud)) / (16 * req_baud); 1422 baud = rate / (quot * 16); 1423 } 1424 quot--; 1425 1426 calc_deviation = abs(req_baud - baud); 1427 1428 if (calc_deviation < deviation) { 1429 /* 1430 * If we find a better clk, release the previous one, if 1431 * any. 1432 */ 1433 if (!IS_ERR(*best_clk)) 1434 clk_put(*best_clk); 1435 *best_clk = clk; 1436 best_quot = quot; 1437 *clk_num = cnt; 1438 deviation = calc_deviation; 1439 } else { 1440 clk_put(clk); 1441 } 1442 } 1443 1444 return best_quot; 1445 } 1446 1447 /* udivslot_table[] 1448 * 1449 * This table takes the fractional value of the baud divisor and gives 1450 * the recommended setting for the UDIVSLOT register. 1451 */ 1452 static const u16 udivslot_table[16] = { 1453 [0] = 0x0000, 1454 [1] = 0x0080, 1455 [2] = 0x0808, 1456 [3] = 0x0888, 1457 [4] = 0x2222, 1458 [5] = 0x4924, 1459 [6] = 0x4A52, 1460 [7] = 0x54AA, 1461 [8] = 0x5555, 1462 [9] = 0xD555, 1463 [10] = 0xD5D5, 1464 [11] = 0xDDD5, 1465 [12] = 0xDDDD, 1466 [13] = 0xDFDD, 1467 [14] = 0xDFDF, 1468 [15] = 0xFFDF, 1469 }; 1470 1471 static void s3c24xx_serial_set_termios(struct uart_port *port, 1472 struct ktermios *termios, 1473 const struct ktermios *old) 1474 { 1475 const struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); 1476 struct s3c24xx_uart_port *ourport = to_ourport(port); 1477 struct clk *clk = ERR_PTR(-EINVAL); 1478 unsigned long flags; 1479 unsigned int baud, quot; 1480 unsigned int udivslot = 0; 1481 u32 ulcon, umcon; 1482 u8 clk_sel = 0; 1483 1484 /* 1485 * We don't support modem control lines. 1486 */ 1487 termios->c_cflag &= ~(HUPCL | CMSPAR); 1488 termios->c_cflag |= CLOCAL; 1489 1490 /* 1491 * Ask the core to calculate the divisor for us. 1492 */ 1493 1494 baud = uart_get_baud_rate(port, termios, old, 0, 3000000); 1495 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel); 1496 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) 1497 quot = port->custom_divisor; 1498 if (IS_ERR(clk)) 1499 return; 1500 1501 /* check to see if we need to change clock source */ 1502 1503 if (ourport->baudclk != clk) { 1504 clk_prepare_enable(clk); 1505 1506 s3c24xx_serial_setsource(port, clk_sel); 1507 1508 if (!IS_ERR(ourport->baudclk)) { 1509 clk_disable_unprepare(ourport->baudclk); 1510 ourport->baudclk = ERR_PTR(-EINVAL); 1511 } 1512 1513 ourport->baudclk = clk; 1514 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0; 1515 } 1516 1517 if (ourport->info->has_divslot) { 1518 unsigned int div = ourport->baudclk_rate / baud; 1519 1520 if (cfg->has_fracval) { 1521 udivslot = (div & 15); 1522 dev_dbg(port->dev, "fracval = %04x\n", udivslot); 1523 } else { 1524 udivslot = udivslot_table[div & 15]; 1525 dev_dbg(port->dev, "udivslot = %04x (div %d)\n", 1526 udivslot, div & 15); 1527 } 1528 } 1529 1530 switch (termios->c_cflag & CSIZE) { 1531 case CS5: 1532 dev_dbg(port->dev, "config: 5bits/char\n"); 1533 ulcon = S3C2410_LCON_CS5; 1534 break; 1535 case CS6: 1536 dev_dbg(port->dev, "config: 6bits/char\n"); 1537 ulcon = S3C2410_LCON_CS6; 1538 break; 1539 case CS7: 1540 dev_dbg(port->dev, "config: 7bits/char\n"); 1541 ulcon = S3C2410_LCON_CS7; 1542 break; 1543 case CS8: 1544 default: 1545 dev_dbg(port->dev, "config: 8bits/char\n"); 1546 ulcon = S3C2410_LCON_CS8; 1547 break; 1548 } 1549 1550 /* preserve original lcon IR settings */ 1551 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM); 1552 1553 if (termios->c_cflag & CSTOPB) 1554 ulcon |= S3C2410_LCON_STOPB; 1555 1556 if (termios->c_cflag & PARENB) { 1557 if (termios->c_cflag & PARODD) 1558 ulcon |= S3C2410_LCON_PODD; 1559 else 1560 ulcon |= S3C2410_LCON_PEVEN; 1561 } else { 1562 ulcon |= S3C2410_LCON_PNONE; 1563 } 1564 1565 dev_dbg(port->dev, 1566 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n", 1567 ulcon, quot, udivslot); 1568 1569 uart_port_lock_irqsave(port, &flags); 1570 1571 wr_regl(port, S3C2410_ULCON, ulcon); 1572 wr_regl(port, S3C2410_UBRDIV, quot); 1573 1574 port->status &= ~UPSTAT_AUTOCTS; 1575 1576 umcon = rd_regl(port, S3C2410_UMCON); 1577 if (termios->c_cflag & CRTSCTS) { 1578 umcon |= S3C2410_UMCOM_AFC; 1579 /* Disable RTS when RX FIFO contains 63 bytes */ 1580 umcon &= ~S3C2412_UMCON_AFC_8; 1581 port->status = UPSTAT_AUTOCTS; 1582 } else { 1583 umcon &= ~S3C2410_UMCOM_AFC; 1584 } 1585 wr_regl(port, S3C2410_UMCON, umcon); 1586 1587 if (ourport->info->has_divslot) 1588 wr_regl(port, S3C2443_DIVSLOT, udivslot); 1589 1590 /* 1591 * Update the per-port timeout. 1592 */ 1593 uart_update_timeout(port, termios->c_cflag, baud); 1594 1595 /* 1596 * Which character status flags are we interested in? 1597 */ 1598 port->read_status_mask = S3C2410_UERSTAT_OVERRUN; 1599 if (termios->c_iflag & INPCK) 1600 port->read_status_mask |= S3C2410_UERSTAT_FRAME | 1601 S3C2410_UERSTAT_PARITY; 1602 /* 1603 * Which character status flags should we ignore? 1604 */ 1605 port->ignore_status_mask = 0; 1606 if (termios->c_iflag & IGNPAR) 1607 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN; 1608 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR) 1609 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME; 1610 1611 /* 1612 * Ignore all characters if CREAD is not set. 1613 */ 1614 if ((termios->c_cflag & CREAD) == 0) 1615 port->ignore_status_mask |= RXSTAT_DUMMY_READ; 1616 1617 uart_port_unlock_irqrestore(port, flags); 1618 } 1619 1620 static const char *s3c24xx_serial_type(struct uart_port *port) 1621 { 1622 const struct s3c24xx_uart_port *ourport = to_ourport(port); 1623 1624 switch (ourport->info->type) { 1625 case TYPE_S3C6400: 1626 return "S3C6400/10"; 1627 case TYPE_APPLE_S5L: 1628 return "APPLE S5L"; 1629 default: 1630 return NULL; 1631 } 1632 } 1633 1634 static void s3c24xx_serial_config_port(struct uart_port *port, int flags) 1635 { 1636 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1637 1638 if (flags & UART_CONFIG_TYPE) 1639 port->type = info->port_type; 1640 } 1641 1642 /* 1643 * verify the new serial_struct (for TIOCSSERIAL). 1644 */ 1645 static int 1646 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser) 1647 { 1648 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1649 1650 if (ser->type != PORT_UNKNOWN && ser->type != info->port_type) 1651 return -EINVAL; 1652 1653 return 0; 1654 } 1655 1656 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 1657 1658 static struct console s3c24xx_serial_console; 1659 1660 static void __init s3c24xx_serial_register_console(void) 1661 { 1662 register_console(&s3c24xx_serial_console); 1663 } 1664 1665 static void s3c24xx_serial_unregister_console(void) 1666 { 1667 if (console_is_registered(&s3c24xx_serial_console)) 1668 unregister_console(&s3c24xx_serial_console); 1669 } 1670 1671 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console 1672 #else 1673 static inline void s3c24xx_serial_register_console(void) { } 1674 static inline void s3c24xx_serial_unregister_console(void) { } 1675 #define S3C24XX_SERIAL_CONSOLE NULL 1676 #endif 1677 1678 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1679 static int s3c24xx_serial_get_poll_char(struct uart_port *port); 1680 static void s3c24xx_serial_put_poll_char(struct uart_port *port, 1681 unsigned char c); 1682 #endif 1683 1684 static const struct uart_ops s3c64xx_serial_ops = { 1685 .pm = s3c24xx_serial_pm, 1686 .tx_empty = s3c24xx_serial_tx_empty, 1687 .get_mctrl = s3c24xx_serial_get_mctrl, 1688 .set_mctrl = s3c24xx_serial_set_mctrl, 1689 .stop_tx = s3c24xx_serial_stop_tx, 1690 .start_tx = s3c24xx_serial_start_tx, 1691 .stop_rx = s3c24xx_serial_stop_rx, 1692 .break_ctl = s3c24xx_serial_break_ctl, 1693 .startup = s3c64xx_serial_startup, 1694 .shutdown = s3c64xx_serial_shutdown, 1695 .set_termios = s3c24xx_serial_set_termios, 1696 .type = s3c24xx_serial_type, 1697 .config_port = s3c24xx_serial_config_port, 1698 .verify_port = s3c24xx_serial_verify_port, 1699 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1700 .poll_get_char = s3c24xx_serial_get_poll_char, 1701 .poll_put_char = s3c24xx_serial_put_poll_char, 1702 #endif 1703 }; 1704 1705 static const struct uart_ops apple_s5l_serial_ops = { 1706 .pm = s3c24xx_serial_pm, 1707 .tx_empty = s3c24xx_serial_tx_empty, 1708 .get_mctrl = s3c24xx_serial_get_mctrl, 1709 .set_mctrl = s3c24xx_serial_set_mctrl, 1710 .stop_tx = s3c24xx_serial_stop_tx, 1711 .start_tx = s3c24xx_serial_start_tx, 1712 .stop_rx = s3c24xx_serial_stop_rx, 1713 .break_ctl = s3c24xx_serial_break_ctl, 1714 .startup = apple_s5l_serial_startup, 1715 .shutdown = apple_s5l_serial_shutdown, 1716 .set_termios = s3c24xx_serial_set_termios, 1717 .type = s3c24xx_serial_type, 1718 .config_port = s3c24xx_serial_config_port, 1719 .verify_port = s3c24xx_serial_verify_port, 1720 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1721 .poll_get_char = s3c24xx_serial_get_poll_char, 1722 .poll_put_char = s3c24xx_serial_put_poll_char, 1723 #endif 1724 }; 1725 1726 static struct uart_driver s3c24xx_uart_drv = { 1727 .owner = THIS_MODULE, 1728 .driver_name = "s3c2410_serial", 1729 .nr = UART_NR, 1730 .cons = S3C24XX_SERIAL_CONSOLE, 1731 .dev_name = S3C24XX_SERIAL_NAME, 1732 .major = S3C24XX_SERIAL_MAJOR, 1733 .minor = S3C24XX_SERIAL_MINOR, 1734 }; 1735 1736 static struct s3c24xx_uart_port s3c24xx_serial_ports[UART_NR]; 1737 1738 static void s3c24xx_serial_init_port_default(int index) 1739 { 1740 struct uart_port *port = &s3c24xx_serial_ports[index].port; 1741 1742 spin_lock_init(&port->lock); 1743 1744 port->uartclk = 0; 1745 port->fifosize = 16; 1746 port->flags = UPF_BOOT_AUTOCONF; 1747 port->line = index; 1748 } 1749 1750 /* s3c24xx_serial_resetport 1751 * 1752 * reset the fifos and other the settings. 1753 */ 1754 1755 static void s3c24xx_serial_resetport(struct uart_port *port, 1756 const struct s3c2410_uartcfg *cfg) 1757 { 1758 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1759 u32 ucon = rd_regl(port, S3C2410_UCON); 1760 1761 ucon &= (info->clksel_mask | info->ucon_mask); 1762 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); 1763 1764 /* reset both fifos */ 1765 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); 1766 wr_regl(port, S3C2410_UFCON, cfg->ufcon); 1767 1768 /* some delay is required after fifo reset */ 1769 udelay(1); 1770 } 1771 1772 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport) 1773 { 1774 struct device *dev = ourport->port.dev; 1775 const struct s3c24xx_uart_info *info = ourport->info; 1776 char clk_name[MAX_CLK_NAME_LENGTH]; 1777 struct clk *clk; 1778 int ret; 1779 u8 clk_sel, clk_num; 1780 1781 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel; 1782 for (clk_num = 0; clk_num < info->num_clks; clk_num++) { 1783 if (!(clk_sel & (1 << clk_num))) 1784 continue; 1785 1786 sprintf(clk_name, "clk_uart_baud%d", clk_num); 1787 clk = clk_get(dev, clk_name); 1788 if (IS_ERR(clk)) 1789 continue; 1790 1791 ret = clk_prepare_enable(clk); 1792 if (ret) { 1793 clk_put(clk); 1794 continue; 1795 } 1796 1797 ourport->baudclk = clk; 1798 ourport->baudclk_rate = clk_get_rate(clk); 1799 s3c24xx_serial_setsource(&ourport->port, clk_num); 1800 1801 return 0; 1802 } 1803 1804 return -EINVAL; 1805 } 1806 1807 /* s3c24xx_serial_init_port 1808 * 1809 * initialise a single serial port from the platform device given 1810 */ 1811 1812 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, 1813 struct platform_device *platdev) 1814 { 1815 struct uart_port *port = &ourport->port; 1816 const struct s3c2410_uartcfg *cfg = ourport->cfg; 1817 struct resource *res; 1818 int ret; 1819 1820 if (platdev == NULL) 1821 return -ENODEV; 1822 1823 if (port->mapbase != 0) 1824 return -EINVAL; 1825 1826 /* setup info for port */ 1827 port->dev = &platdev->dev; 1828 1829 port->uartclk = 1; 1830 1831 if (cfg->uart_flags & UPF_CONS_FLOW) { 1832 dev_dbg(port->dev, "enabling flow control\n"); 1833 port->flags |= UPF_CONS_FLOW; 1834 } 1835 1836 /* sort our the physical and virtual addresses for each UART */ 1837 1838 res = platform_get_resource(platdev, IORESOURCE_MEM, 0); 1839 if (res == NULL) { 1840 dev_err(port->dev, "failed to find memory resource for uart\n"); 1841 return -EINVAL; 1842 } 1843 1844 dev_dbg(port->dev, "resource %pR)\n", res); 1845 1846 port->membase = devm_ioremap_resource(port->dev, res); 1847 if (IS_ERR(port->membase)) { 1848 dev_err(port->dev, "failed to remap controller address\n"); 1849 return -EBUSY; 1850 } 1851 1852 port->mapbase = res->start; 1853 ret = platform_get_irq(platdev, 0); 1854 if (ret < 0) { 1855 port->irq = 0; 1856 } else { 1857 port->irq = ret; 1858 ourport->rx_irq = ret; 1859 ourport->tx_irq = ret + 1; 1860 } 1861 1862 /* 1863 * DMA is currently supported only on DT platforms, if DMA properties 1864 * are specified. 1865 */ 1866 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node, 1867 "dmas", NULL)) { 1868 ourport->dma = devm_kzalloc(port->dev, 1869 sizeof(*ourport->dma), 1870 GFP_KERNEL); 1871 if (!ourport->dma) { 1872 ret = -ENOMEM; 1873 goto err; 1874 } 1875 } 1876 1877 ourport->clk = clk_get(&platdev->dev, "uart"); 1878 if (IS_ERR(ourport->clk)) { 1879 pr_err("%s: Controller clock not found\n", 1880 dev_name(&platdev->dev)); 1881 ret = PTR_ERR(ourport->clk); 1882 goto err; 1883 } 1884 1885 ret = clk_prepare_enable(ourport->clk); 1886 if (ret) { 1887 pr_err("uart: clock failed to prepare+enable: %d\n", ret); 1888 clk_put(ourport->clk); 1889 goto err; 1890 } 1891 1892 ret = s3c24xx_serial_enable_baudclk(ourport); 1893 if (ret) 1894 pr_warn("uart: failed to enable baudclk\n"); 1895 1896 /* Keep all interrupts masked and cleared */ 1897 switch (ourport->info->type) { 1898 case TYPE_S3C6400: 1899 wr_regl(port, S3C64XX_UINTM, 0xf); 1900 wr_regl(port, S3C64XX_UINTP, 0xf); 1901 wr_regl(port, S3C64XX_UINTSP, 0xf); 1902 break; 1903 case TYPE_APPLE_S5L: { 1904 u32 ucon; 1905 1906 ucon = rd_regl(port, S3C2410_UCON); 1907 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 1908 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 1909 APPLE_S5L_UCON_RXTO_ENA_MSK); 1910 wr_regl(port, S3C2410_UCON, ucon); 1911 1912 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 1913 break; 1914 } 1915 default: 1916 break; 1917 } 1918 1919 dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n", 1920 &port->mapbase, port->membase, port->irq, 1921 ourport->rx_irq, ourport->tx_irq, port->uartclk); 1922 1923 /* reset the fifos (and setup the uart) */ 1924 s3c24xx_serial_resetport(port, cfg); 1925 1926 return 0; 1927 1928 err: 1929 port->mapbase = 0; 1930 return ret; 1931 } 1932 1933 /* Device driver serial port probe */ 1934 1935 static int probe_index; 1936 1937 static inline const struct s3c24xx_serial_drv_data * 1938 s3c24xx_get_driver_data(struct platform_device *pdev) 1939 { 1940 if (dev_of_node(&pdev->dev)) 1941 return of_device_get_match_data(&pdev->dev); 1942 1943 return (struct s3c24xx_serial_drv_data *) 1944 platform_get_device_id(pdev)->driver_data; 1945 } 1946 1947 static int s3c24xx_serial_probe(struct platform_device *pdev) 1948 { 1949 struct device_node *np = pdev->dev.of_node; 1950 struct s3c24xx_uart_port *ourport; 1951 int index = probe_index; 1952 int ret, prop = 0, fifosize_prop = 1; 1953 1954 if (np) { 1955 ret = of_alias_get_id(np, "serial"); 1956 if (ret >= 0) 1957 index = ret; 1958 } 1959 1960 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) { 1961 dev_err(&pdev->dev, "serial%d out of range\n", index); 1962 return -EINVAL; 1963 } 1964 ourport = &s3c24xx_serial_ports[index]; 1965 1966 s3c24xx_serial_init_port_default(index); 1967 1968 ourport->drv_data = s3c24xx_get_driver_data(pdev); 1969 if (!ourport->drv_data) { 1970 dev_err(&pdev->dev, "could not find driver data\n"); 1971 return -ENODEV; 1972 } 1973 1974 ourport->baudclk = ERR_PTR(-EINVAL); 1975 ourport->info = &ourport->drv_data->info; 1976 ourport->cfg = (dev_get_platdata(&pdev->dev)) ? 1977 dev_get_platdata(&pdev->dev) : 1978 &ourport->drv_data->def_cfg; 1979 1980 switch (ourport->info->type) { 1981 case TYPE_S3C6400: 1982 ourport->port.ops = &s3c64xx_serial_ops; 1983 break; 1984 case TYPE_APPLE_S5L: 1985 ourport->port.ops = &apple_s5l_serial_ops; 1986 break; 1987 } 1988 1989 ourport->port.iotype = ourport->info->iotype; 1990 1991 if (np) { 1992 fifosize_prop = of_property_read_u32(np, "samsung,uart-fifosize", 1993 &ourport->port.fifosize); 1994 1995 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { 1996 switch (prop) { 1997 case 1: 1998 ourport->port.iotype = UPIO_MEM; 1999 break; 2000 case 4: 2001 ourport->port.iotype = UPIO_MEM32; 2002 break; 2003 default: 2004 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n", 2005 prop); 2006 return -EINVAL; 2007 } 2008 } 2009 } 2010 2011 if (fifosize_prop) { 2012 if (ourport->drv_data->fifosize[index]) 2013 ourport->port.fifosize = ourport->drv_data->fifosize[index]; 2014 else if (ourport->info->fifosize) 2015 ourport->port.fifosize = ourport->info->fifosize; 2016 } 2017 2018 ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE); 2019 2020 /* 2021 * DMA transfers must be aligned at least to cache line size, 2022 * so find minimal transfer size suitable for DMA mode 2023 */ 2024 ourport->min_dma_size = max_t(int, ourport->port.fifosize, 2025 dma_get_cache_alignment()); 2026 2027 dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport); 2028 2029 ret = s3c24xx_serial_init_port(ourport, pdev); 2030 if (ret < 0) 2031 return ret; 2032 2033 if (!s3c24xx_uart_drv.state) { 2034 ret = uart_register_driver(&s3c24xx_uart_drv); 2035 if (ret < 0) { 2036 pr_err("Failed to register Samsung UART driver\n"); 2037 return ret; 2038 } 2039 } 2040 2041 dev_dbg(&pdev->dev, "%s: adding port\n", __func__); 2042 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port); 2043 platform_set_drvdata(pdev, &ourport->port); 2044 2045 /* 2046 * Deactivate the clock enabled in s3c24xx_serial_init_port here, 2047 * so that a potential re-enablement through the pm-callback overlaps 2048 * and keeps the clock enabled in this case. 2049 */ 2050 clk_disable_unprepare(ourport->clk); 2051 if (!IS_ERR(ourport->baudclk)) 2052 clk_disable_unprepare(ourport->baudclk); 2053 2054 probe_index++; 2055 2056 return 0; 2057 } 2058 2059 static void s3c24xx_serial_remove(struct platform_device *dev) 2060 { 2061 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); 2062 2063 if (port) 2064 uart_remove_one_port(&s3c24xx_uart_drv, port); 2065 2066 uart_unregister_driver(&s3c24xx_uart_drv); 2067 } 2068 2069 /* UART power management code */ 2070 #ifdef CONFIG_PM_SLEEP 2071 static int s3c24xx_serial_suspend(struct device *dev) 2072 { 2073 struct uart_port *port = s3c24xx_dev_to_port(dev); 2074 2075 if (port) 2076 uart_suspend_port(&s3c24xx_uart_drv, port); 2077 2078 return 0; 2079 } 2080 2081 static int s3c24xx_serial_resume(struct device *dev) 2082 { 2083 struct uart_port *port = s3c24xx_dev_to_port(dev); 2084 struct s3c24xx_uart_port *ourport = to_ourport(port); 2085 2086 if (port) { 2087 clk_prepare_enable(ourport->clk); 2088 if (!IS_ERR(ourport->baudclk)) 2089 clk_prepare_enable(ourport->baudclk); 2090 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port)); 2091 if (!IS_ERR(ourport->baudclk)) 2092 clk_disable_unprepare(ourport->baudclk); 2093 clk_disable_unprepare(ourport->clk); 2094 2095 uart_resume_port(&s3c24xx_uart_drv, port); 2096 } 2097 2098 return 0; 2099 } 2100 2101 static int s3c24xx_serial_resume_noirq(struct device *dev) 2102 { 2103 struct uart_port *port = s3c24xx_dev_to_port(dev); 2104 struct s3c24xx_uart_port *ourport = to_ourport(port); 2105 2106 if (port) { 2107 /* restore IRQ mask */ 2108 switch (ourport->info->type) { 2109 case TYPE_S3C6400: { 2110 u32 uintm = 0xf; 2111 2112 if (ourport->tx_enabled) 2113 uintm &= ~S3C64XX_UINTM_TXD_MSK; 2114 if (ourport->rx_enabled) 2115 uintm &= ~S3C64XX_UINTM_RXD_MSK; 2116 clk_prepare_enable(ourport->clk); 2117 if (!IS_ERR(ourport->baudclk)) 2118 clk_prepare_enable(ourport->baudclk); 2119 wr_regl(port, S3C64XX_UINTM, uintm); 2120 if (!IS_ERR(ourport->baudclk)) 2121 clk_disable_unprepare(ourport->baudclk); 2122 clk_disable_unprepare(ourport->clk); 2123 break; 2124 } 2125 case TYPE_APPLE_S5L: { 2126 u32 ucon; 2127 int ret; 2128 2129 ret = clk_prepare_enable(ourport->clk); 2130 if (ret) { 2131 dev_err(dev, "clk_enable clk failed: %d\n", ret); 2132 return ret; 2133 } 2134 if (!IS_ERR(ourport->baudclk)) { 2135 ret = clk_prepare_enable(ourport->baudclk); 2136 if (ret) { 2137 dev_err(dev, "clk_enable baudclk failed: %d\n", ret); 2138 clk_disable_unprepare(ourport->clk); 2139 return ret; 2140 } 2141 } 2142 2143 ucon = rd_regl(port, S3C2410_UCON); 2144 2145 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 2146 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2147 APPLE_S5L_UCON_RXTO_ENA_MSK | 2148 APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK); 2149 2150 if (ourport->tx_enabled) 2151 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK; 2152 if (ourport->rx_enabled) 2153 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2154 APPLE_S5L_UCON_RXTO_ENA_MSK | 2155 APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK; 2156 2157 wr_regl(port, S3C2410_UCON, ucon); 2158 2159 if (!IS_ERR(ourport->baudclk)) 2160 clk_disable_unprepare(ourport->baudclk); 2161 clk_disable_unprepare(ourport->clk); 2162 break; 2163 } 2164 default: 2165 break; 2166 } 2167 } 2168 2169 return 0; 2170 } 2171 2172 static const struct dev_pm_ops s3c24xx_serial_pm_ops = { 2173 SET_SYSTEM_SLEEP_PM_OPS(s3c24xx_serial_suspend, s3c24xx_serial_resume) 2174 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, s3c24xx_serial_resume_noirq) 2175 }; 2176 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops) 2177 2178 #else /* !CONFIG_PM_SLEEP */ 2179 2180 #define SERIAL_SAMSUNG_PM_OPS NULL 2181 #endif /* CONFIG_PM_SLEEP */ 2182 2183 /* Console code */ 2184 2185 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 2186 2187 static struct uart_port *cons_uart; 2188 2189 static bool 2190 s3c24xx_serial_console_txrdy(struct uart_port *port, u32 ufcon) 2191 { 2192 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 2193 u32 ufstat, utrstat; 2194 2195 if (ufcon & S3C2410_UFCON_FIFOMODE) { 2196 /* fifo mode - check amount of data in fifo registers... */ 2197 2198 ufstat = rd_regl(port, S3C2410_UFSTAT); 2199 return !(ufstat & info->tx_fifofull); 2200 } 2201 2202 /* in non-fifo mode, we go and use the tx buffer empty */ 2203 2204 utrstat = rd_regl(port, S3C2410_UTRSTAT); 2205 return utrstat & S3C2410_UTRSTAT_TXE; 2206 } 2207 2208 static bool 2209 s3c24xx_port_configured(u32 ucon) 2210 { 2211 /* consider the serial port configured if the tx/rx mode set */ 2212 return (ucon & 0xf) != 0; 2213 } 2214 2215 #ifdef CONFIG_CONSOLE_POLL 2216 /* 2217 * Console polling routines for writing and reading from the uart while 2218 * in an interrupt or debug context. 2219 */ 2220 2221 static int s3c24xx_serial_get_poll_char(struct uart_port *port) 2222 { 2223 const struct s3c24xx_uart_port *ourport = to_ourport(port); 2224 u32 ufstat; 2225 2226 ufstat = rd_regl(port, S3C2410_UFSTAT); 2227 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) 2228 return NO_POLL_CHAR; 2229 2230 return rd_reg(port, S3C2410_URXH); 2231 } 2232 2233 static void s3c24xx_serial_put_poll_char(struct uart_port *port, 2234 unsigned char c) 2235 { 2236 u32 ufcon = rd_regl(port, S3C2410_UFCON); 2237 u32 ucon = rd_regl(port, S3C2410_UCON); 2238 2239 /* not possible to xmit on unconfigured port */ 2240 if (!s3c24xx_port_configured(ucon)) 2241 return; 2242 2243 while (!s3c24xx_serial_console_txrdy(port, ufcon)) 2244 cpu_relax(); 2245 wr_reg(port, S3C2410_UTXH, c); 2246 } 2247 2248 #endif /* CONFIG_CONSOLE_POLL */ 2249 2250 static void 2251 s3c24xx_serial_console_putchar(struct uart_port *port, unsigned char ch) 2252 { 2253 u32 ufcon = rd_regl(port, S3C2410_UFCON); 2254 2255 while (!s3c24xx_serial_console_txrdy(port, ufcon)) 2256 cpu_relax(); 2257 wr_reg(port, S3C2410_UTXH, ch); 2258 } 2259 2260 static void 2261 s3c24xx_serial_console_write(struct console *co, const char *s, 2262 unsigned int count) 2263 { 2264 u32 ucon = rd_regl(cons_uart, S3C2410_UCON); 2265 unsigned long flags; 2266 bool locked = true; 2267 2268 /* not possible to xmit on unconfigured port */ 2269 if (!s3c24xx_port_configured(ucon)) 2270 return; 2271 2272 if (cons_uart->sysrq) 2273 locked = false; 2274 else if (oops_in_progress) 2275 locked = uart_port_trylock_irqsave(cons_uart, &flags); 2276 else 2277 uart_port_lock_irqsave(cons_uart, &flags); 2278 2279 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar); 2280 2281 if (locked) 2282 uart_port_unlock_irqrestore(cons_uart, flags); 2283 } 2284 2285 /* Shouldn't be __init, as it can be instantiated from other module */ 2286 static void 2287 s3c24xx_serial_get_options(struct uart_port *port, int *baud, 2288 int *parity, int *bits) 2289 { 2290 struct clk *clk; 2291 unsigned long rate; 2292 u32 ulcon, ucon, ubrdiv; 2293 char clk_name[MAX_CLK_NAME_LENGTH]; 2294 u8 clk_sel; 2295 2296 ulcon = rd_regl(port, S3C2410_ULCON); 2297 ucon = rd_regl(port, S3C2410_UCON); 2298 ubrdiv = rd_regl(port, S3C2410_UBRDIV); 2299 2300 if (s3c24xx_port_configured(ucon)) { 2301 switch (ulcon & S3C2410_LCON_CSMASK) { 2302 case S3C2410_LCON_CS5: 2303 *bits = 5; 2304 break; 2305 case S3C2410_LCON_CS6: 2306 *bits = 6; 2307 break; 2308 case S3C2410_LCON_CS7: 2309 *bits = 7; 2310 break; 2311 case S3C2410_LCON_CS8: 2312 default: 2313 *bits = 8; 2314 break; 2315 } 2316 2317 switch (ulcon & S3C2410_LCON_PMASK) { 2318 case S3C2410_LCON_PEVEN: 2319 *parity = 'e'; 2320 break; 2321 2322 case S3C2410_LCON_PODD: 2323 *parity = 'o'; 2324 break; 2325 2326 case S3C2410_LCON_PNONE: 2327 default: 2328 *parity = 'n'; 2329 } 2330 2331 /* now calculate the baud rate */ 2332 2333 clk_sel = s3c24xx_serial_getsource(port); 2334 sprintf(clk_name, "clk_uart_baud%d", clk_sel); 2335 2336 clk = clk_get(port->dev, clk_name); 2337 if (!IS_ERR(clk)) 2338 rate = clk_get_rate(clk); 2339 else 2340 rate = 1; 2341 2342 *baud = rate / (16 * (ubrdiv + 1)); 2343 dev_dbg(port->dev, "calculated baud %d\n", *baud); 2344 } 2345 } 2346 2347 /* Shouldn't be __init, as it can be instantiated from other module */ 2348 static int 2349 s3c24xx_serial_console_setup(struct console *co, char *options) 2350 { 2351 struct uart_port *port; 2352 int baud = 9600; 2353 int bits = 8; 2354 int parity = 'n'; 2355 int flow = 'n'; 2356 2357 /* is this a valid port */ 2358 2359 if (co->index == -1 || co->index >= UART_NR) 2360 co->index = 0; 2361 2362 port = &s3c24xx_serial_ports[co->index].port; 2363 2364 /* is the port configured? */ 2365 2366 if (port->mapbase == 0x0) 2367 return -ENODEV; 2368 2369 cons_uart = port; 2370 2371 /* 2372 * Check whether an invalid uart number has been specified, and 2373 * if so, search for the first available port that does have 2374 * console support. 2375 */ 2376 if (options) 2377 uart_parse_options(options, &baud, &parity, &bits, &flow); 2378 else 2379 s3c24xx_serial_get_options(port, &baud, &parity, &bits); 2380 2381 dev_dbg(port->dev, "baud %d\n", baud); 2382 2383 return uart_set_options(port, co, baud, parity, bits, flow); 2384 } 2385 2386 static struct console s3c24xx_serial_console = { 2387 .name = S3C24XX_SERIAL_NAME, 2388 .device = uart_console_device, 2389 .flags = CON_PRINTBUFFER, 2390 .index = -1, 2391 .write = s3c24xx_serial_console_write, 2392 .setup = s3c24xx_serial_console_setup, 2393 .data = &s3c24xx_uart_drv, 2394 }; 2395 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */ 2396 2397 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) 2398 static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = { 2399 .info = { 2400 .name = "Samsung S3C6400 UART", 2401 .type = TYPE_S3C6400, 2402 .port_type = PORT_S3C6400, 2403 .iotype = UPIO_MEM, 2404 .fifosize = 64, 2405 .has_divslot = true, 2406 .rx_fifomask = S3C2440_UFSTAT_RXMASK, 2407 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, 2408 .rx_fifofull = S3C2440_UFSTAT_RXFULL, 2409 .tx_fifofull = S3C2440_UFSTAT_TXFULL, 2410 .tx_fifomask = S3C2440_UFSTAT_TXMASK, 2411 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, 2412 .def_clk_sel = S3C2410_UCON_CLKSEL2, 2413 .num_clks = 4, 2414 .clksel_mask = S3C6400_UCON_CLKMASK, 2415 .clksel_shift = S3C6400_UCON_CLKSHIFT, 2416 }, 2417 .def_cfg = { 2418 .ucon = S3C2410_UCON_DEFAULT, 2419 .ufcon = S3C2410_UFCON_DEFAULT, 2420 }, 2421 }; 2422 #define S3C6400_SERIAL_DRV_DATA (&s3c6400_serial_drv_data) 2423 #else 2424 #define S3C6400_SERIAL_DRV_DATA NULL 2425 #endif 2426 2427 #ifdef CONFIG_CPU_S5PV210 2428 static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { 2429 .info = { 2430 .name = "Samsung S5PV210 UART", 2431 .type = TYPE_S3C6400, 2432 .port_type = PORT_S3C6400, 2433 .iotype = UPIO_MEM, 2434 .has_divslot = true, 2435 .rx_fifomask = S5PV210_UFSTAT_RXMASK, 2436 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, 2437 .rx_fifofull = S5PV210_UFSTAT_RXFULL, 2438 .tx_fifofull = S5PV210_UFSTAT_TXFULL, 2439 .tx_fifomask = S5PV210_UFSTAT_TXMASK, 2440 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, 2441 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2442 .num_clks = 2, 2443 .clksel_mask = S5PV210_UCON_CLKMASK, 2444 .clksel_shift = S5PV210_UCON_CLKSHIFT, 2445 }, 2446 .def_cfg = { 2447 .ucon = S5PV210_UCON_DEFAULT, 2448 .ufcon = S5PV210_UFCON_DEFAULT, 2449 }, 2450 .fifosize = { 256, 64, 16, 16 }, 2451 }; 2452 #define S5PV210_SERIAL_DRV_DATA (&s5pv210_serial_drv_data) 2453 #else 2454 #define S5PV210_SERIAL_DRV_DATA NULL 2455 #endif 2456 2457 #if defined(CONFIG_ARCH_EXYNOS) 2458 #define EXYNOS_COMMON_SERIAL_DRV_DATA \ 2459 .info = { \ 2460 .name = "Samsung Exynos UART", \ 2461 .type = TYPE_S3C6400, \ 2462 .port_type = PORT_S3C6400, \ 2463 .iotype = UPIO_MEM, \ 2464 .has_divslot = true, \ 2465 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ 2466 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ 2467 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \ 2468 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \ 2469 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \ 2470 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \ 2471 .def_clk_sel = S3C2410_UCON_CLKSEL0, \ 2472 .num_clks = 1, \ 2473 .clksel_mask = 0, \ 2474 .clksel_shift = 0, \ 2475 }, \ 2476 .def_cfg = { \ 2477 .ucon = S5PV210_UCON_DEFAULT, \ 2478 .ufcon = S5PV210_UFCON_DEFAULT, \ 2479 .has_fracval = 1, \ 2480 } \ 2481 2482 static const struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { 2483 EXYNOS_COMMON_SERIAL_DRV_DATA, 2484 .fifosize = { 256, 64, 16, 16 }, 2485 }; 2486 2487 static const struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { 2488 EXYNOS_COMMON_SERIAL_DRV_DATA, 2489 .fifosize = { 64, 256, 16, 256 }, 2490 }; 2491 2492 static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = { 2493 EXYNOS_COMMON_SERIAL_DRV_DATA, 2494 .fifosize = { 256, 64, 64, 64 }, 2495 }; 2496 2497 static const struct s3c24xx_serial_drv_data exynos8895_serial_drv_data = { 2498 EXYNOS_COMMON_SERIAL_DRV_DATA, 2499 /* samsung,uart-fifosize must be specified in the device tree. */ 2500 .fifosize = { 0 }, 2501 }; 2502 2503 static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = { 2504 .info = { 2505 .name = "Google GS101 UART", 2506 .type = TYPE_S3C6400, 2507 .port_type = PORT_S3C6400, 2508 .iotype = UPIO_MEM32, 2509 .has_divslot = true, 2510 .rx_fifomask = S5PV210_UFSTAT_RXMASK, 2511 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, 2512 .rx_fifofull = S5PV210_UFSTAT_RXFULL, 2513 .tx_fifofull = S5PV210_UFSTAT_TXFULL, 2514 .tx_fifomask = S5PV210_UFSTAT_TXMASK, 2515 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, 2516 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2517 .num_clks = 1, 2518 .clksel_mask = 0, 2519 .clksel_shift = 0, 2520 }, 2521 .def_cfg = { 2522 .ucon = S5PV210_UCON_DEFAULT, 2523 .ufcon = S5PV210_UFCON_DEFAULT, 2524 .has_fracval = 1, 2525 }, 2526 /* samsung,uart-fifosize must be specified in the device tree. */ 2527 .fifosize = { 0 }, 2528 }; 2529 2530 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data) 2531 #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data) 2532 #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data) 2533 #define EXYNOS8895_SERIAL_DRV_DATA (&exynos8895_serial_drv_data) 2534 #define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data) 2535 2536 #else 2537 #define EXYNOS4210_SERIAL_DRV_DATA NULL 2538 #define EXYNOS5433_SERIAL_DRV_DATA NULL 2539 #define EXYNOS850_SERIAL_DRV_DATA NULL 2540 #define EXYNOS8895_SERIAL_DRV_DATA NULL 2541 #define GS101_SERIAL_DRV_DATA NULL 2542 #endif 2543 2544 #ifdef CONFIG_ARCH_APPLE 2545 static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = { 2546 .info = { 2547 .name = "Apple S5L UART", 2548 .type = TYPE_APPLE_S5L, 2549 .port_type = PORT_8250, 2550 .iotype = UPIO_MEM32, 2551 .fifosize = 16, 2552 .rx_fifomask = S3C2410_UFSTAT_RXMASK, 2553 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, 2554 .rx_fifofull = S3C2410_UFSTAT_RXFULL, 2555 .tx_fifofull = S3C2410_UFSTAT_TXFULL, 2556 .tx_fifomask = S3C2410_UFSTAT_TXMASK, 2557 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT, 2558 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2559 .num_clks = 1, 2560 .clksel_mask = 0, 2561 .clksel_shift = 0, 2562 .ucon_mask = APPLE_S5L_UCON_MASK, 2563 }, 2564 .def_cfg = { 2565 .ucon = APPLE_S5L_UCON_DEFAULT, 2566 .ufcon = S3C2410_UFCON_DEFAULT, 2567 }, 2568 }; 2569 #define S5L_SERIAL_DRV_DATA (&s5l_serial_drv_data) 2570 #else 2571 #define S5L_SERIAL_DRV_DATA NULL 2572 #endif 2573 2574 #if defined(CONFIG_ARCH_ARTPEC) 2575 static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = { 2576 .info = { 2577 .name = "Axis ARTPEC-8 UART", 2578 .type = TYPE_S3C6400, 2579 .port_type = PORT_S3C6400, 2580 .iotype = UPIO_MEM, 2581 .fifosize = 64, 2582 .has_divslot = true, 2583 .rx_fifomask = S5PV210_UFSTAT_RXMASK, 2584 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, 2585 .rx_fifofull = S5PV210_UFSTAT_RXFULL, 2586 .tx_fifofull = S5PV210_UFSTAT_TXFULL, 2587 .tx_fifomask = S5PV210_UFSTAT_TXMASK, 2588 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, 2589 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2590 .num_clks = 1, 2591 .clksel_mask = 0, 2592 .clksel_shift = 0, 2593 }, 2594 .def_cfg = { 2595 .ucon = S5PV210_UCON_DEFAULT, 2596 .ufcon = S5PV210_UFCON_DEFAULT, 2597 .has_fracval = 1, 2598 } 2599 }; 2600 #define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data) 2601 #else 2602 #define ARTPEC8_SERIAL_DRV_DATA (NULL) 2603 #endif 2604 2605 static const struct platform_device_id s3c24xx_serial_driver_ids[] = { 2606 { 2607 .name = "s3c6400-uart", 2608 .driver_data = (kernel_ulong_t)S3C6400_SERIAL_DRV_DATA, 2609 }, { 2610 .name = "s5pv210-uart", 2611 .driver_data = (kernel_ulong_t)S5PV210_SERIAL_DRV_DATA, 2612 }, { 2613 .name = "exynos4210-uart", 2614 .driver_data = (kernel_ulong_t)EXYNOS4210_SERIAL_DRV_DATA, 2615 }, { 2616 .name = "exynos5433-uart", 2617 .driver_data = (kernel_ulong_t)EXYNOS5433_SERIAL_DRV_DATA, 2618 }, { 2619 .name = "s5l-uart", 2620 .driver_data = (kernel_ulong_t)S5L_SERIAL_DRV_DATA, 2621 }, { 2622 .name = "exynos850-uart", 2623 .driver_data = (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA, 2624 }, { 2625 .name = "artpec8-uart", 2626 .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA, 2627 }, { 2628 .name = "gs101-uart", 2629 .driver_data = (kernel_ulong_t)GS101_SERIAL_DRV_DATA, 2630 }, { 2631 .name = "exynos8895-uart", 2632 .driver_data = (kernel_ulong_t)EXYNOS8895_SERIAL_DRV_DATA, 2633 }, 2634 { }, 2635 }; 2636 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids); 2637 2638 #ifdef CONFIG_OF 2639 static const struct of_device_id s3c24xx_uart_dt_match[] = { 2640 { .compatible = "samsung,s3c6400-uart", 2641 .data = S3C6400_SERIAL_DRV_DATA }, 2642 { .compatible = "samsung,s5pv210-uart", 2643 .data = S5PV210_SERIAL_DRV_DATA }, 2644 { .compatible = "samsung,exynos4210-uart", 2645 .data = EXYNOS4210_SERIAL_DRV_DATA }, 2646 { .compatible = "samsung,exynos5433-uart", 2647 .data = EXYNOS5433_SERIAL_DRV_DATA }, 2648 { .compatible = "apple,s5l-uart", 2649 .data = S5L_SERIAL_DRV_DATA }, 2650 { .compatible = "samsung,exynos850-uart", 2651 .data = EXYNOS850_SERIAL_DRV_DATA }, 2652 { .compatible = "axis,artpec8-uart", 2653 .data = ARTPEC8_SERIAL_DRV_DATA }, 2654 { .compatible = "google,gs101-uart", 2655 .data = GS101_SERIAL_DRV_DATA }, 2656 { .compatible = "samsung,exynos8895-uart", 2657 .data = EXYNOS8895_SERIAL_DRV_DATA }, 2658 {}, 2659 }; 2660 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); 2661 #endif 2662 2663 static struct platform_driver samsung_serial_driver = { 2664 .probe = s3c24xx_serial_probe, 2665 .remove = s3c24xx_serial_remove, 2666 .id_table = s3c24xx_serial_driver_ids, 2667 .driver = { 2668 .name = "samsung-uart", 2669 .pm = SERIAL_SAMSUNG_PM_OPS, 2670 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match), 2671 }, 2672 }; 2673 2674 static int __init samsung_serial_init(void) 2675 { 2676 int ret; 2677 2678 s3c24xx_serial_register_console(); 2679 2680 ret = platform_driver_register(&samsung_serial_driver); 2681 if (ret) { 2682 s3c24xx_serial_unregister_console(); 2683 return ret; 2684 } 2685 2686 return 0; 2687 } 2688 2689 static void __exit samsung_serial_exit(void) 2690 { 2691 platform_driver_unregister(&samsung_serial_driver); 2692 s3c24xx_serial_unregister_console(); 2693 } 2694 2695 module_init(samsung_serial_init); 2696 module_exit(samsung_serial_exit); 2697 2698 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 2699 /* 2700 * Early console. 2701 */ 2702 2703 static void wr_reg_barrier(const struct uart_port *port, u32 reg, u32 val) 2704 { 2705 switch (port->iotype) { 2706 case UPIO_MEM: 2707 writeb(val, portaddr(port, reg)); 2708 break; 2709 case UPIO_MEM32: 2710 writel(val, portaddr(port, reg)); 2711 break; 2712 default: 2713 break; 2714 } 2715 } 2716 2717 struct samsung_early_console_data { 2718 u32 txfull_mask; 2719 u32 rxfifo_mask; 2720 }; 2721 2722 static void samsung_early_busyuart(const struct uart_port *port) 2723 { 2724 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE)) 2725 ; 2726 } 2727 2728 static void samsung_early_busyuart_fifo(const struct uart_port *port) 2729 { 2730 const struct samsung_early_console_data *data = port->private_data; 2731 2732 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask) 2733 ; 2734 } 2735 2736 static void samsung_early_putc(struct uart_port *port, unsigned char c) 2737 { 2738 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) 2739 samsung_early_busyuart_fifo(port); 2740 else 2741 samsung_early_busyuart(port); 2742 2743 wr_reg_barrier(port, S3C2410_UTXH, c); 2744 } 2745 2746 static void samsung_early_write(struct console *con, const char *s, 2747 unsigned int n) 2748 { 2749 struct earlycon_device *dev = con->data; 2750 2751 uart_console_write(&dev->port, s, n, samsung_early_putc); 2752 } 2753 2754 static int samsung_early_read(struct console *con, char *s, unsigned int n) 2755 { 2756 struct earlycon_device *dev = con->data; 2757 const struct samsung_early_console_data *data = dev->port.private_data; 2758 int num_read = 0; 2759 u32 ch, ufstat; 2760 2761 while (num_read < n) { 2762 ufstat = rd_regl(&dev->port, S3C2410_UFSTAT); 2763 if (!(ufstat & data->rxfifo_mask)) 2764 break; 2765 ch = rd_reg(&dev->port, S3C2410_URXH); 2766 if (ch == NO_POLL_CHAR) 2767 break; 2768 2769 s[num_read++] = ch; 2770 } 2771 2772 return num_read; 2773 } 2774 2775 static int __init samsung_early_console_setup(struct earlycon_device *device, 2776 const char *opt) 2777 { 2778 if (!device->port.membase) 2779 return -ENODEV; 2780 2781 device->con->write = samsung_early_write; 2782 device->con->read = samsung_early_read; 2783 return 0; 2784 } 2785 2786 /* S3C2410 */ 2787 static struct samsung_early_console_data s3c2410_early_console_data = { 2788 .txfull_mask = S3C2410_UFSTAT_TXFULL, 2789 .rxfifo_mask = S3C2410_UFSTAT_RXFULL | S3C2410_UFSTAT_RXMASK, 2790 }; 2791 2792 /* S3C64xx */ 2793 static struct samsung_early_console_data s3c2440_early_console_data = { 2794 .txfull_mask = S3C2440_UFSTAT_TXFULL, 2795 .rxfifo_mask = S3C2440_UFSTAT_RXFULL | S3C2440_UFSTAT_RXMASK, 2796 }; 2797 2798 static int __init s3c2440_early_console_setup(struct earlycon_device *device, 2799 const char *opt) 2800 { 2801 device->port.private_data = &s3c2440_early_console_data; 2802 return samsung_early_console_setup(device, opt); 2803 } 2804 2805 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart", 2806 s3c2440_early_console_setup); 2807 2808 /* S5PV210, Exynos */ 2809 static struct samsung_early_console_data s5pv210_early_console_data = { 2810 .txfull_mask = S5PV210_UFSTAT_TXFULL, 2811 .rxfifo_mask = S5PV210_UFSTAT_RXFULL | S5PV210_UFSTAT_RXMASK, 2812 }; 2813 2814 static int __init s5pv210_early_console_setup(struct earlycon_device *device, 2815 const char *opt) 2816 { 2817 device->port.private_data = &s5pv210_early_console_data; 2818 return samsung_early_console_setup(device, opt); 2819 } 2820 2821 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart", 2822 s5pv210_early_console_setup); 2823 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart", 2824 s5pv210_early_console_setup); 2825 OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart", 2826 s5pv210_early_console_setup); 2827 OF_EARLYCON_DECLARE(exynos850, "samsung,exynos850-uart", 2828 s5pv210_early_console_setup); 2829 2830 static int __init gs101_early_console_setup(struct earlycon_device *device, 2831 const char *opt) 2832 { 2833 /* gs101 always expects MMIO32 register accesses. */ 2834 device->port.iotype = UPIO_MEM32; 2835 2836 return s5pv210_early_console_setup(device, opt); 2837 } 2838 2839 OF_EARLYCON_DECLARE(gs101, "google,gs101-uart", gs101_early_console_setup); 2840 2841 /* Apple S5L */ 2842 static int __init apple_s5l_early_console_setup(struct earlycon_device *device, 2843 const char *opt) 2844 { 2845 /* Apple A7-A11 requires MMIO32 register accesses. */ 2846 device->port.iotype = UPIO_MEM32; 2847 2848 /* Close enough to S3C2410 for earlycon... */ 2849 device->port.private_data = &s3c2410_early_console_data; 2850 2851 #ifdef CONFIG_ARM64 2852 /* ... but we need to override the existing fixmap entry as nGnRnE */ 2853 __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase, 2854 __pgprot(PROT_DEVICE_nGnRnE)); 2855 #endif 2856 return samsung_early_console_setup(device, opt); 2857 } 2858 2859 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup); 2860 #endif 2861 2862 MODULE_ALIAS("platform:samsung-uart"); 2863 MODULE_DESCRIPTION("Samsung SoC Serial port driver"); 2864 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 2865 MODULE_LICENSE("GPL v2"); 2866