1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/slab.h> 6 #include <linux/platform_device.h> 7 #include <linux/device.h> 8 #include <linux/delay.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/kernel.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/component.h> 13 #include <sound/tlv.h> 14 #include <linux/of_gpio.h> 15 #include <linux/of.h> 16 #include <sound/jack.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <linux/regmap.h> 20 #include <sound/soc.h> 21 #include <sound/soc-dapm.h> 22 #include <linux/regulator/consumer.h> 23 24 #include "wcd-clsh-v2.h" 25 #include "wcd-mbhc-v2.h" 26 #include "wcd938x.h" 27 28 #define WCD938X_MAX_MICBIAS (4) 29 #define WCD938X_MAX_SUPPLY (4) 30 #define WCD938X_MBHC_MAX_BUTTONS (8) 31 #define TX_ADC_MAX (4) 32 #define WCD938X_TX_MAX_SWR_PORTS (5) 33 34 #define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 35 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 36 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 37 /* Fractional Rates */ 38 #define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 39 SNDRV_PCM_RATE_176400) 40 #define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 41 SNDRV_PCM_FMTBIT_S24_LE) 42 /* Convert from vout ctl to micbias voltage in mV */ 43 #define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50) 44 #define SWR_CLK_RATE_0P6MHZ (600000) 45 #define SWR_CLK_RATE_1P2MHZ (1200000) 46 #define SWR_CLK_RATE_2P4MHZ (2400000) 47 #define SWR_CLK_RATE_4P8MHZ (4800000) 48 #define SWR_CLK_RATE_9P6MHZ (9600000) 49 #define SWR_CLK_RATE_11P2896MHZ (1128960) 50 51 #define WCD938X_DRV_NAME "wcd938x_codec" 52 #define WCD938X_VERSION_1_0 (1) 53 #define EAR_RX_PATH_AUX (1) 54 55 #define ADC_MODE_VAL_HIFI 0x01 56 #define ADC_MODE_VAL_LO_HIF 0x02 57 #define ADC_MODE_VAL_NORMAL 0x03 58 #define ADC_MODE_VAL_LP 0x05 59 #define ADC_MODE_VAL_ULP1 0x09 60 #define ADC_MODE_VAL_ULP2 0x0B 61 62 /* Z value defined in milliohm */ 63 #define WCD938X_ZDET_VAL_32 (32000) 64 #define WCD938X_ZDET_VAL_400 (400000) 65 #define WCD938X_ZDET_VAL_1200 (1200000) 66 #define WCD938X_ZDET_VAL_100K (100000000) 67 /* Z floating defined in ohms */ 68 #define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 69 #define WCD938X_ZDET_NUM_MEASUREMENTS (900) 70 #define WCD938X_MBHC_GET_C1(c) ((c & 0xC000) >> 14) 71 #define WCD938X_MBHC_GET_X1(x) (x & 0x3FFF) 72 /* Z value compared in milliOhm */ 73 #define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000)) 74 #define WCD938X_MBHC_ZDET_CONST (86 * 16384) 75 #define WCD938X_MBHC_MOISTURE_RREF R_24_KOHM 76 #define WCD_MBHC_HS_V_MAX 1600 77 78 #define WCD938X_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \ 79 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 80 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 81 SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 82 .tlv.p = (tlv_array), \ 83 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ 84 .put = wcd938x_ear_pa_put_gain, \ 85 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) } 86 87 enum { 88 WCD9380 = 0, 89 WCD9385 = 5, 90 }; 91 92 enum { 93 TX_HDR12 = 0, 94 TX_HDR34, 95 TX_HDR_MAX, 96 }; 97 98 enum { 99 WCD_RX1, 100 WCD_RX2, 101 WCD_RX3 102 }; 103 104 enum { 105 /* INTR_CTRL_INT_MASK_0 */ 106 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0, 107 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 108 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 109 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 110 WCD938X_IRQ_MBHC_SW_DET, 111 WCD938X_IRQ_HPHR_OCP_INT, 112 WCD938X_IRQ_HPHR_CNP_INT, 113 WCD938X_IRQ_HPHL_OCP_INT, 114 115 /* INTR_CTRL_INT_MASK_1 */ 116 WCD938X_IRQ_HPHL_CNP_INT, 117 WCD938X_IRQ_EAR_CNP_INT, 118 WCD938X_IRQ_EAR_SCD_INT, 119 WCD938X_IRQ_AUX_CNP_INT, 120 WCD938X_IRQ_AUX_SCD_INT, 121 WCD938X_IRQ_HPHL_PDM_WD_INT, 122 WCD938X_IRQ_HPHR_PDM_WD_INT, 123 WCD938X_IRQ_AUX_PDM_WD_INT, 124 125 /* INTR_CTRL_INT_MASK_2 */ 126 WCD938X_IRQ_LDORT_SCD_INT, 127 WCD938X_IRQ_MBHC_MOISTURE_INT, 128 WCD938X_IRQ_HPHL_SURGE_DET_INT, 129 WCD938X_IRQ_HPHR_SURGE_DET_INT, 130 WCD938X_NUM_IRQS, 131 }; 132 133 enum { 134 WCD_ADC1 = 0, 135 WCD_ADC2, 136 WCD_ADC3, 137 WCD_ADC4, 138 ALLOW_BUCK_DISABLE, 139 HPH_COMP_DELAY, 140 HPH_PA_DELAY, 141 AMIC2_BCS_ENABLE, 142 WCD_SUPPLIES_LPM_MODE, 143 }; 144 145 enum { 146 ADC_MODE_INVALID = 0, 147 ADC_MODE_HIFI, 148 ADC_MODE_LO_HIF, 149 ADC_MODE_NORMAL, 150 ADC_MODE_LP, 151 ADC_MODE_ULP1, 152 ADC_MODE_ULP2, 153 }; 154 155 enum { 156 AIF1_PB = 0, 157 AIF1_CAP, 158 NUM_CODEC_DAIS, 159 }; 160 161 static u8 tx_mode_bit[] = { 162 [ADC_MODE_INVALID] = 0x00, 163 [ADC_MODE_HIFI] = 0x01, 164 [ADC_MODE_LO_HIF] = 0x02, 165 [ADC_MODE_NORMAL] = 0x04, 166 [ADC_MODE_LP] = 0x08, 167 [ADC_MODE_ULP1] = 0x10, 168 [ADC_MODE_ULP2] = 0x20, 169 }; 170 171 struct wcd938x_priv { 172 struct sdw_slave *tx_sdw_dev; 173 struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 174 struct device *txdev; 175 struct device *rxdev; 176 struct device_node *rxnode, *txnode; 177 struct regmap *regmap; 178 struct mutex micb_lock; 179 /* mbhc module */ 180 struct wcd_mbhc *wcd_mbhc; 181 struct wcd_mbhc_config mbhc_cfg; 182 struct wcd_mbhc_intr intr_ids; 183 struct wcd_clsh_ctrl *clsh_info; 184 struct irq_domain *virq; 185 struct regmap_irq_chip *wcd_regmap_irq_chip; 186 struct regmap_irq_chip_data *irq_chip; 187 struct regulator_bulk_data supplies[WCD938X_MAX_SUPPLY]; 188 struct snd_soc_jack *jack; 189 unsigned long status_mask; 190 s32 micb_ref[WCD938X_MAX_MICBIAS]; 191 s32 pullup_ref[WCD938X_MAX_MICBIAS]; 192 u32 hph_mode; 193 u32 tx_mode[TX_ADC_MAX]; 194 int flyback_cur_det_disable; 195 int ear_rx_path; 196 int variant; 197 int reset_gpio; 198 struct gpio_desc *us_euro_gpio; 199 u32 micb1_mv; 200 u32 micb2_mv; 201 u32 micb3_mv; 202 u32 micb4_mv; 203 int hphr_pdm_wd_int; 204 int hphl_pdm_wd_int; 205 int aux_pdm_wd_int; 206 bool comp1_enable; 207 bool comp2_enable; 208 bool ldoh; 209 }; 210 211 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 212 static const DECLARE_TLV_DB_SCALE(line_gain, -3000, 150, 0); 213 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000); 214 215 struct wcd938x_mbhc_zdet_param { 216 u16 ldo_ctl; 217 u16 noff; 218 u16 nshift; 219 u16 btn5; 220 u16 btn6; 221 u16 btn7; 222 }; 223 224 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 225 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD938X_ANA_MBHC_MECH, 0x80), 226 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD938X_ANA_MBHC_MECH, 0x40), 227 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD938X_ANA_MBHC_MECH, 0x20), 228 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 229 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD938X_ANA_MBHC_ELECT, 0x08), 230 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 231 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD938X_ANA_MBHC_MECH, 0x04), 232 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x10), 233 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x08), 234 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD938X_ANA_MBHC_MECH, 0x01), 235 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD938X_ANA_MBHC_ELECT, 0x06), 236 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD938X_ANA_MBHC_ELECT, 0x80), 237 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 238 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD938X_MBHC_NEW_CTL_1, 0x03), 239 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD938X_MBHC_NEW_CTL_2, 0x03), 240 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x08), 241 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD938X_ANA_MBHC_RESULT_3, 0x10), 242 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x20), 243 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x80), 244 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x40), 245 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD938X_HPH_OCP_CTL, 0x10), 246 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x07), 247 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD938X_ANA_MBHC_ELECT, 0x70), 248 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0xFF), 249 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD938X_ANA_MICB2, 0xC0), 250 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD938X_HPH_CNP_WG_TIME, 0xFF), 251 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD938X_ANA_HPH, 0x40), 252 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD938X_ANA_HPH, 0x80), 253 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD938X_ANA_HPH, 0xC0), 254 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD938X_ANA_MBHC_RESULT_3, 0x10), 255 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD938X_MBHC_CTL_BCS, 0x02), 256 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x01), 257 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD938X_MBHC_NEW_CTL_2, 0x70), 258 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x20), 259 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD938X_HPH_PA_CTL2, 0x40), 260 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD938X_HPH_PA_CTL2, 0x10), 261 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD938X_HPH_L_TEST, 0x01), 262 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD938X_HPH_R_TEST, 0x01), 263 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x80), 264 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x20), 265 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD938X_MBHC_NEW_CTL_1, 0x08), 266 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD938X_MBHC_NEW_FSM_STATUS, 0x40), 267 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD938X_MBHC_NEW_FSM_STATUS, 0x80), 268 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD938X_MBHC_NEW_ADC_RESULT, 0xFF), 269 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD938X_ANA_MICB2, 0x3F), 270 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD938X_MBHC_NEW_CTL_1, 0x10), 271 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD938X_MBHC_NEW_CTL_1, 0x04), 272 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02), 273 }; 274 275 static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = { 276 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01), 277 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02), 278 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04), 279 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08), 280 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10), 281 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20), 282 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40), 283 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80), 284 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01), 285 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02), 286 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04), 287 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08), 288 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10), 289 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20), 290 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40), 291 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80), 292 REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01), 293 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02), 294 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04), 295 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08), 296 }; 297 298 static struct regmap_irq_chip wcd938x_regmap_irq_chip = { 299 .name = "wcd938x", 300 .irqs = wcd938x_irqs, 301 .num_irqs = ARRAY_SIZE(wcd938x_irqs), 302 .num_regs = 3, 303 .status_base = WCD938X_DIGITAL_INTR_STATUS_0, 304 .mask_base = WCD938X_DIGITAL_INTR_MASK_0, 305 .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0, 306 .use_ack = 1, 307 .runtime_pm = true, 308 .irq_drv_data = NULL, 309 }; 310 311 static int wcd938x_get_clk_rate(int mode) 312 { 313 int rate; 314 315 switch (mode) { 316 case ADC_MODE_ULP2: 317 rate = SWR_CLK_RATE_0P6MHZ; 318 break; 319 case ADC_MODE_ULP1: 320 rate = SWR_CLK_RATE_1P2MHZ; 321 break; 322 case ADC_MODE_LP: 323 rate = SWR_CLK_RATE_4P8MHZ; 324 break; 325 case ADC_MODE_NORMAL: 326 case ADC_MODE_LO_HIF: 327 case ADC_MODE_HIFI: 328 case ADC_MODE_INVALID: 329 default: 330 rate = SWR_CLK_RATE_9P6MHZ; 331 break; 332 } 333 334 return rate; 335 } 336 337 static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank) 338 { 339 u8 mask = (bank ? 0xF0 : 0x0F); 340 u8 val = 0; 341 342 switch (rate) { 343 case SWR_CLK_RATE_0P6MHZ: 344 val = (bank ? 0x60 : 0x06); 345 break; 346 case SWR_CLK_RATE_1P2MHZ: 347 val = (bank ? 0x50 : 0x05); 348 break; 349 case SWR_CLK_RATE_2P4MHZ: 350 val = (bank ? 0x30 : 0x03); 351 break; 352 case SWR_CLK_RATE_4P8MHZ: 353 val = (bank ? 0x10 : 0x01); 354 break; 355 case SWR_CLK_RATE_9P6MHZ: 356 default: 357 val = 0x00; 358 break; 359 } 360 snd_soc_component_update_bits(component, WCD938X_DIGITAL_SWR_TX_CLK_RATE, 361 mask, val); 362 363 return 0; 364 } 365 366 static int wcd938x_io_init(struct wcd938x_priv *wcd938x) 367 { 368 struct regmap *rm = wcd938x->regmap; 369 370 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E); 371 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80); 372 /* 1 msec delay as per HW requirement */ 373 usleep_range(1000, 1010); 374 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40); 375 /* 1 msec delay as per HW requirement */ 376 usleep_range(1000, 1010); 377 regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00); 378 regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ, 379 0xF0, 0x80); 380 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80); 381 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40); 382 /* 10 msec delay as per HW requirement */ 383 usleep_range(10000, 10010); 384 385 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00); 386 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 387 0xF0, 0x00); 388 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 389 0x1F, 0x15); 390 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 391 0x1F, 0x15); 392 regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL, 393 0xC0, 0x80); 394 regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL, 395 0x02, 0x02); 396 397 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 398 0xFF, 0x14); 399 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 400 0x1F, 0x08); 401 402 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55); 403 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44); 404 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11); 405 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00); 406 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00); 407 408 /* Set Noise Filter Resistor value */ 409 regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0); 410 regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0); 411 regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0); 412 regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0); 413 414 regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00); 415 regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 416 417 return 0; 418 419 } 420 421 static int wcd938x_sdw_connect_port(const struct wcd938x_sdw_ch_info *ch_info, 422 struct sdw_port_config *port_config, 423 u8 enable) 424 { 425 u8 ch_mask, port_num; 426 427 port_num = ch_info->port_num; 428 ch_mask = ch_info->ch_mask; 429 430 port_config->num = port_num; 431 432 if (enable) 433 port_config->ch_mask |= ch_mask; 434 else 435 port_config->ch_mask &= ~ch_mask; 436 437 return 0; 438 } 439 440 static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 port_num, u8 ch_id, u8 enable) 441 { 442 return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id], 443 &wcd->port_config[port_num - 1], 444 enable); 445 } 446 447 static int wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget *w, 448 struct snd_kcontrol *kcontrol, 449 int event) 450 { 451 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 452 453 switch (event) { 454 case SND_SOC_DAPM_PRE_PMU: 455 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 456 WCD938X_ANA_RX_CLK_EN_MASK, 1); 457 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 458 WCD938X_RX_BIAS_EN_MASK, 1); 459 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX0_CTL, 460 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 461 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX1_CTL, 462 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 463 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX2_CTL, 464 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 465 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 466 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 1); 467 snd_soc_component_write_field(component, WCD938X_AUX_AUXPA, 468 WCD938X_AUXPA_CLK_EN_MASK, 1); 469 break; 470 case SND_SOC_DAPM_POST_PMD: 471 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 472 WCD938X_VNEG_EN_MASK, 0); 473 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 474 WCD938X_VPOS_EN_MASK, 0); 475 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 476 WCD938X_RX_BIAS_EN_MASK, 0); 477 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 478 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 0); 479 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 480 WCD938X_ANA_RX_CLK_EN_MASK, 0); 481 break; 482 } 483 return 0; 484 } 485 486 static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 487 struct snd_kcontrol *kcontrol, 488 int event) 489 { 490 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 491 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 492 493 switch (event) { 494 case SND_SOC_DAPM_PRE_PMU: 495 snd_soc_component_write_field(component, 496 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 497 WCD938X_RXD0_CLK_EN_MASK, 0x01); 498 snd_soc_component_write_field(component, 499 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 500 WCD938X_HPHL_RX_EN_MASK, 1); 501 snd_soc_component_write_field(component, 502 WCD938X_HPH_RDAC_CLK_CTL1, 503 WCD938X_CHOP_CLK_EN_MASK, 0); 504 break; 505 case SND_SOC_DAPM_POST_PMU: 506 snd_soc_component_write_field(component, 507 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 508 WCD938X_HPH_RES_DIV_MASK, 0x02); 509 if (wcd938x->comp1_enable) { 510 snd_soc_component_write_field(component, 511 WCD938X_DIGITAL_CDC_COMP_CTL_0, 512 WCD938X_HPHL_COMP_EN_MASK, 1); 513 /* 5msec compander delay as per HW requirement */ 514 if (!wcd938x->comp2_enable || (snd_soc_component_read(component, 515 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01)) 516 usleep_range(5000, 5010); 517 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 518 WCD938X_AUTOCHOP_TIMER_EN, 0); 519 } else { 520 snd_soc_component_write_field(component, 521 WCD938X_DIGITAL_CDC_COMP_CTL_0, 522 WCD938X_HPHL_COMP_EN_MASK, 0); 523 snd_soc_component_write_field(component, 524 WCD938X_HPH_L_EN, 525 WCD938X_GAIN_SRC_SEL_MASK, 526 WCD938X_GAIN_SRC_SEL_REGISTER); 527 528 } 529 break; 530 case SND_SOC_DAPM_POST_PMD: 531 snd_soc_component_write_field(component, 532 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 533 WCD938X_HPH_RES_DIV_MASK, 0x1); 534 break; 535 } 536 537 return 0; 538 } 539 540 static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 541 struct snd_kcontrol *kcontrol, 542 int event) 543 { 544 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 545 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 546 547 switch (event) { 548 case SND_SOC_DAPM_PRE_PMU: 549 snd_soc_component_write_field(component, 550 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 551 WCD938X_RXD1_CLK_EN_MASK, 1); 552 snd_soc_component_write_field(component, 553 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 554 WCD938X_HPHR_RX_EN_MASK, 1); 555 snd_soc_component_write_field(component, 556 WCD938X_HPH_RDAC_CLK_CTL1, 557 WCD938X_CHOP_CLK_EN_MASK, 0); 558 break; 559 case SND_SOC_DAPM_POST_PMU: 560 snd_soc_component_write_field(component, 561 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 562 WCD938X_HPH_RES_DIV_MASK, 0x02); 563 if (wcd938x->comp2_enable) { 564 snd_soc_component_write_field(component, 565 WCD938X_DIGITAL_CDC_COMP_CTL_0, 566 WCD938X_HPHR_COMP_EN_MASK, 1); 567 /* 5msec compander delay as per HW requirement */ 568 if (!wcd938x->comp1_enable || 569 (snd_soc_component_read(component, 570 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02)) 571 usleep_range(5000, 5010); 572 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 573 WCD938X_AUTOCHOP_TIMER_EN, 0); 574 } else { 575 snd_soc_component_write_field(component, 576 WCD938X_DIGITAL_CDC_COMP_CTL_0, 577 WCD938X_HPHR_COMP_EN_MASK, 0); 578 snd_soc_component_write_field(component, 579 WCD938X_HPH_R_EN, 580 WCD938X_GAIN_SRC_SEL_MASK, 581 WCD938X_GAIN_SRC_SEL_REGISTER); 582 } 583 break; 584 case SND_SOC_DAPM_POST_PMD: 585 snd_soc_component_write_field(component, 586 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 587 WCD938X_HPH_RES_DIV_MASK, 0x01); 588 break; 589 } 590 591 return 0; 592 } 593 594 static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 595 struct snd_kcontrol *kcontrol, 596 int event) 597 { 598 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 599 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 600 601 switch (event) { 602 case SND_SOC_DAPM_PRE_PMU: 603 wcd938x->ear_rx_path = 604 snd_soc_component_read( 605 component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL); 606 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) { 607 snd_soc_component_write_field(component, 608 WCD938X_EAR_EAR_DAC_CON, 609 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 0); 610 snd_soc_component_write_field(component, 611 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 612 WCD938X_AUX_EN_MASK, 1); 613 snd_soc_component_write_field(component, 614 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 615 WCD938X_RXD2_CLK_EN_MASK, 1); 616 snd_soc_component_write_field(component, 617 WCD938X_ANA_EAR_COMPANDER_CTL, 618 WCD938X_GAIN_OVRD_REG_MASK, 1); 619 } else { 620 snd_soc_component_write_field(component, 621 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 622 WCD938X_HPHL_RX_EN_MASK, 1); 623 snd_soc_component_write_field(component, 624 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 625 WCD938X_RXD0_CLK_EN_MASK, 1); 626 if (wcd938x->comp1_enable) 627 snd_soc_component_write_field(component, 628 WCD938X_DIGITAL_CDC_COMP_CTL_0, 629 WCD938X_HPHL_COMP_EN_MASK, 1); 630 } 631 /* 5 msec delay as per HW requirement */ 632 usleep_range(5000, 5010); 633 if (wcd938x->flyback_cur_det_disable == 0) 634 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 635 WCD938X_EN_CUR_DET_MASK, 0); 636 wcd938x->flyback_cur_det_disable++; 637 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 638 WCD_CLSH_EVENT_PRE_DAC, 639 WCD_CLSH_STATE_EAR, 640 wcd938x->hph_mode); 641 break; 642 case SND_SOC_DAPM_POST_PMD: 643 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) { 644 snd_soc_component_write_field(component, 645 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 646 WCD938X_AUX_EN_MASK, 0); 647 snd_soc_component_write_field(component, 648 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 649 WCD938X_RXD2_CLK_EN_MASK, 0); 650 } else { 651 snd_soc_component_write_field(component, 652 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 653 WCD938X_HPHL_RX_EN_MASK, 0); 654 snd_soc_component_write_field(component, 655 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 656 WCD938X_RXD0_CLK_EN_MASK, 0); 657 if (wcd938x->comp1_enable) 658 snd_soc_component_write_field(component, 659 WCD938X_DIGITAL_CDC_COMP_CTL_0, 660 WCD938X_HPHL_COMP_EN_MASK, 0); 661 } 662 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 663 WCD938X_GAIN_OVRD_REG_MASK, 0); 664 snd_soc_component_write_field(component, 665 WCD938X_EAR_EAR_DAC_CON, 666 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 1); 667 break; 668 } 669 return 0; 670 671 } 672 673 static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, 674 struct snd_kcontrol *kcontrol, 675 int event) 676 { 677 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 678 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 679 680 switch (event) { 681 case SND_SOC_DAPM_PRE_PMU: 682 snd_soc_component_write_field(component, 683 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 684 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 1); 685 snd_soc_component_write_field(component, 686 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 687 WCD938X_RXD2_CLK_EN_MASK, 1); 688 snd_soc_component_write_field(component, 689 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 690 WCD938X_AUX_EN_MASK, 1); 691 if (wcd938x->flyback_cur_det_disable == 0) 692 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 693 WCD938X_EN_CUR_DET_MASK, 0); 694 wcd938x->flyback_cur_det_disable++; 695 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 696 WCD_CLSH_EVENT_PRE_DAC, 697 WCD_CLSH_STATE_AUX, 698 wcd938x->hph_mode); 699 break; 700 case SND_SOC_DAPM_POST_PMD: 701 snd_soc_component_write_field(component, 702 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 703 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0); 704 break; 705 } 706 return 0; 707 708 } 709 710 static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 711 struct snd_kcontrol *kcontrol, int event) 712 { 713 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 714 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 715 int hph_mode = wcd938x->hph_mode; 716 717 switch (event) { 718 case SND_SOC_DAPM_PRE_PMU: 719 if (wcd938x->ldoh) 720 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 721 WCD938X_LDOH_EN_MASK, 1); 722 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 723 WCD_CLSH_STATE_HPHR, hph_mode); 724 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI); 725 726 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 727 hph_mode == CLS_H_ULP) { 728 snd_soc_component_write_field(component, 729 WCD938X_HPH_REFBUFF_LP_CTL, 730 WCD938X_PREREF_FLIT_BYPASS_MASK, 1); 731 } 732 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 733 WCD938X_HPHR_REF_EN_MASK, 1); 734 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode); 735 /* 100 usec delay as per HW requirement */ 736 usleep_range(100, 110); 737 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 738 snd_soc_component_write_field(component, 739 WCD938X_DIGITAL_PDM_WD_CTL1, 740 WCD938X_PDM_WD_EN_MASK, 0x3); 741 break; 742 case SND_SOC_DAPM_POST_PMU: 743 /* 744 * 7ms sleep is required if compander is enabled as per 745 * HW requirement. If compander is disabled, then 746 * 20ms delay is required. 747 */ 748 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 749 if (!wcd938x->comp2_enable) 750 usleep_range(20000, 20100); 751 else 752 usleep_range(7000, 7100); 753 754 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 755 hph_mode == CLS_H_ULP) 756 snd_soc_component_write_field(component, 757 WCD938X_HPH_REFBUFF_LP_CTL, 758 WCD938X_PREREF_FLIT_BYPASS_MASK, 0); 759 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 760 } 761 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 762 WCD938X_AUTOCHOP_TIMER_EN, 1); 763 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 764 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 765 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 766 WCD938X_REGULATOR_MODE_MASK, 767 WCD938X_REGULATOR_MODE_CLASS_AB); 768 enable_irq(wcd938x->hphr_pdm_wd_int); 769 break; 770 case SND_SOC_DAPM_PRE_PMD: 771 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); 772 /* 773 * 7ms sleep is required if compander is enabled as per 774 * HW requirement. If compander is disabled, then 775 * 20ms delay is required. 776 */ 777 if (!wcd938x->comp2_enable) 778 usleep_range(20000, 20100); 779 else 780 usleep_range(7000, 7100); 781 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 782 WCD938X_HPHR_EN_MASK, 0); 783 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 784 WCD_EVENT_PRE_HPHR_PA_OFF); 785 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 786 break; 787 case SND_SOC_DAPM_POST_PMD: 788 /* 789 * 7ms sleep is required if compander is enabled as per 790 * HW requirement. If compander is disabled, then 791 * 20ms delay is required. 792 */ 793 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 794 if (!wcd938x->comp2_enable) 795 usleep_range(20000, 20100); 796 else 797 usleep_range(7000, 7100); 798 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 799 } 800 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 801 WCD_EVENT_POST_HPHR_PA_OFF); 802 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 803 WCD938X_HPHR_REF_EN_MASK, 0); 804 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1, 805 WCD938X_PDM_WD_EN_MASK, 0); 806 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 807 WCD_CLSH_STATE_HPHR, hph_mode); 808 if (wcd938x->ldoh) 809 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 810 WCD938X_LDOH_EN_MASK, 0); 811 break; 812 } 813 814 return 0; 815 } 816 817 static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 818 struct snd_kcontrol *kcontrol, int event) 819 { 820 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 821 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 822 int hph_mode = wcd938x->hph_mode; 823 824 switch (event) { 825 case SND_SOC_DAPM_PRE_PMU: 826 if (wcd938x->ldoh) 827 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 828 WCD938X_LDOH_EN_MASK, 1); 829 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 830 WCD_CLSH_STATE_HPHL, hph_mode); 831 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI); 832 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 833 hph_mode == CLS_H_ULP) { 834 snd_soc_component_write_field(component, 835 WCD938X_HPH_REFBUFF_LP_CTL, 836 WCD938X_PREREF_FLIT_BYPASS_MASK, 1); 837 } 838 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 839 WCD938X_HPHL_REF_EN_MASK, 1); 840 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode); 841 /* 100 usec delay as per HW requirement */ 842 usleep_range(100, 110); 843 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 844 snd_soc_component_write_field(component, 845 WCD938X_DIGITAL_PDM_WD_CTL0, 846 WCD938X_PDM_WD_EN_MASK, 0x3); 847 break; 848 case SND_SOC_DAPM_POST_PMU: 849 /* 850 * 7ms sleep is required if compander is enabled as per 851 * HW requirement. If compander is disabled, then 852 * 20ms delay is required. 853 */ 854 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 855 if (!wcd938x->comp1_enable) 856 usleep_range(20000, 20100); 857 else 858 usleep_range(7000, 7100); 859 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 860 hph_mode == CLS_H_ULP) 861 snd_soc_component_write_field(component, 862 WCD938X_HPH_REFBUFF_LP_CTL, 863 WCD938X_PREREF_FLIT_BYPASS_MASK, 0); 864 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 865 } 866 867 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 868 WCD938X_AUTOCHOP_TIMER_EN, 1); 869 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 870 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 871 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 872 WCD938X_REGULATOR_MODE_MASK, 873 WCD938X_REGULATOR_MODE_CLASS_AB); 874 enable_irq(wcd938x->hphl_pdm_wd_int); 875 break; 876 case SND_SOC_DAPM_PRE_PMD: 877 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 878 /* 879 * 7ms sleep is required if compander is enabled as per 880 * HW requirement. If compander is disabled, then 881 * 20ms delay is required. 882 */ 883 if (!wcd938x->comp1_enable) 884 usleep_range(20000, 20100); 885 else 886 usleep_range(7000, 7100); 887 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 888 WCD938X_HPHL_EN_MASK, 0); 889 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 890 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 891 break; 892 case SND_SOC_DAPM_POST_PMD: 893 /* 894 * 7ms sleep is required if compander is enabled as per 895 * HW requirement. If compander is disabled, then 896 * 20ms delay is required. 897 */ 898 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 899 if (!wcd938x->comp1_enable) 900 usleep_range(21000, 21100); 901 else 902 usleep_range(7000, 7100); 903 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 904 } 905 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 906 WCD_EVENT_POST_HPHL_PA_OFF); 907 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 908 WCD938X_HPHL_REF_EN_MASK, 0); 909 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0, 910 WCD938X_PDM_WD_EN_MASK, 0); 911 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 912 WCD_CLSH_STATE_HPHL, hph_mode); 913 if (wcd938x->ldoh) 914 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 915 WCD938X_LDOH_EN_MASK, 0); 916 break; 917 } 918 919 return 0; 920 } 921 922 static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, 923 struct snd_kcontrol *kcontrol, int event) 924 { 925 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 926 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 927 int hph_mode = wcd938x->hph_mode; 928 929 switch (event) { 930 case SND_SOC_DAPM_PRE_PMU: 931 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 932 WCD938X_AUX_PDM_WD_EN_MASK, 1); 933 break; 934 case SND_SOC_DAPM_POST_PMU: 935 /* 1 msec delay as per HW requirement */ 936 usleep_range(1000, 1010); 937 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 938 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 939 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 940 WCD938X_REGULATOR_MODE_MASK, 941 WCD938X_REGULATOR_MODE_CLASS_AB); 942 enable_irq(wcd938x->aux_pdm_wd_int); 943 break; 944 case SND_SOC_DAPM_PRE_PMD: 945 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 946 break; 947 case SND_SOC_DAPM_POST_PMD: 948 /* 1 msec delay as per HW requirement */ 949 usleep_range(1000, 1010); 950 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 951 WCD938X_AUX_PDM_WD_EN_MASK, 0); 952 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 953 WCD_CLSH_EVENT_POST_PA, 954 WCD_CLSH_STATE_AUX, 955 hph_mode); 956 957 wcd938x->flyback_cur_det_disable--; 958 if (wcd938x->flyback_cur_det_disable == 0) 959 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 960 WCD938X_EN_CUR_DET_MASK, 1); 961 break; 962 } 963 return 0; 964 } 965 966 static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 967 struct snd_kcontrol *kcontrol, int event) 968 { 969 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 970 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 971 int hph_mode = wcd938x->hph_mode; 972 973 switch (event) { 974 case SND_SOC_DAPM_PRE_PMU: 975 /* 976 * Enable watchdog interrupt for HPHL or AUX 977 * depending on mux value 978 */ 979 wcd938x->ear_rx_path = snd_soc_component_read(component, 980 WCD938X_DIGITAL_CDC_EAR_PATH_CTL); 981 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 982 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 983 WCD938X_AUX_PDM_WD_EN_MASK, 1); 984 else 985 snd_soc_component_write_field(component, 986 WCD938X_DIGITAL_PDM_WD_CTL0, 987 WCD938X_PDM_WD_EN_MASK, 0x3); 988 if (!wcd938x->comp1_enable) 989 snd_soc_component_write_field(component, 990 WCD938X_ANA_EAR_COMPANDER_CTL, 991 WCD938X_GAIN_OVRD_REG_MASK, 1); 992 993 break; 994 case SND_SOC_DAPM_POST_PMU: 995 /* 6 msec delay as per HW requirement */ 996 usleep_range(6000, 6010); 997 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 998 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 999 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1000 WCD938X_REGULATOR_MODE_MASK, 1001 WCD938X_REGULATOR_MODE_CLASS_AB); 1002 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 1003 enable_irq(wcd938x->aux_pdm_wd_int); 1004 else 1005 enable_irq(wcd938x->hphl_pdm_wd_int); 1006 break; 1007 case SND_SOC_DAPM_PRE_PMD: 1008 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 1009 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 1010 else 1011 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 1012 break; 1013 case SND_SOC_DAPM_POST_PMD: 1014 if (!wcd938x->comp1_enable) 1015 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 1016 WCD938X_GAIN_OVRD_REG_MASK, 0); 1017 /* 7 msec delay as per HW requirement */ 1018 usleep_range(7000, 7010); 1019 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 1020 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 1021 WCD938X_AUX_PDM_WD_EN_MASK, 0); 1022 else 1023 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0, 1024 WCD938X_PDM_WD_EN_MASK, 0); 1025 1026 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 1027 WCD_CLSH_STATE_EAR, hph_mode); 1028 1029 wcd938x->flyback_cur_det_disable--; 1030 if (wcd938x->flyback_cur_det_disable == 0) 1031 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 1032 WCD938X_EN_CUR_DET_MASK, 1); 1033 break; 1034 } 1035 1036 return 0; 1037 } 1038 1039 static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 1040 struct snd_kcontrol *kcontrol, 1041 int event) 1042 { 1043 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1044 u16 dmic_clk_reg, dmic_clk_en_reg; 1045 u8 dmic_sel_mask, dmic_clk_mask; 1046 1047 switch (w->shift) { 1048 case 0: 1049 case 1: 1050 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2; 1051 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL; 1052 dmic_clk_mask = WCD938X_DMIC1_RATE_MASK; 1053 dmic_sel_mask = WCD938X_AMIC1_IN_SEL_MASK; 1054 break; 1055 case 2: 1056 case 3: 1057 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2; 1058 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL; 1059 dmic_clk_mask = WCD938X_DMIC2_RATE_MASK; 1060 dmic_sel_mask = WCD938X_AMIC3_IN_SEL_MASK; 1061 break; 1062 case 4: 1063 case 5: 1064 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4; 1065 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL; 1066 dmic_clk_mask = WCD938X_DMIC3_RATE_MASK; 1067 dmic_sel_mask = WCD938X_AMIC4_IN_SEL_MASK; 1068 break; 1069 case 6: 1070 case 7: 1071 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4; 1072 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL; 1073 dmic_clk_mask = WCD938X_DMIC4_RATE_MASK; 1074 dmic_sel_mask = WCD938X_AMIC5_IN_SEL_MASK; 1075 break; 1076 default: 1077 dev_err(component->dev, "%s: Invalid DMIC Selection\n", 1078 __func__); 1079 return -EINVAL; 1080 } 1081 1082 switch (event) { 1083 case SND_SOC_DAPM_PRE_PMU: 1084 snd_soc_component_write_field(component, 1085 WCD938X_DIGITAL_CDC_AMIC_CTL, 1086 dmic_sel_mask, 1087 WCD938X_AMIC1_IN_SEL_DMIC); 1088 /* 250us sleep as per HW requirement */ 1089 usleep_range(250, 260); 1090 /* Setting DMIC clock rate to 2.4MHz */ 1091 snd_soc_component_write_field(component, dmic_clk_reg, 1092 dmic_clk_mask, 1093 WCD938X_DMIC4_RATE_2P4MHZ); 1094 snd_soc_component_write_field(component, dmic_clk_en_reg, 1095 WCD938X_DMIC_CLK_EN_MASK, 1); 1096 /* enable clock scaling */ 1097 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_DMIC_CTL, 1098 WCD938X_DMIC_CLK_SCALING_EN_MASK, 0x3); 1099 break; 1100 case SND_SOC_DAPM_POST_PMD: 1101 snd_soc_component_write_field(component, 1102 WCD938X_DIGITAL_CDC_AMIC_CTL, 1103 dmic_sel_mask, WCD938X_AMIC1_IN_SEL_AMIC); 1104 snd_soc_component_write_field(component, dmic_clk_en_reg, 1105 WCD938X_DMIC_CLK_EN_MASK, 0); 1106 break; 1107 } 1108 return 0; 1109 } 1110 1111 static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 1112 struct snd_kcontrol *kcontrol, int event) 1113 { 1114 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1115 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1116 int bank; 1117 int rate; 1118 1119 bank = (wcd938x_swr_get_current_bank(wcd938x->sdw_priv[AIF1_CAP]->sdev)) ? 0 : 1; 1120 bank = bank ? 0 : 1; 1121 1122 switch (event) { 1123 case SND_SOC_DAPM_PRE_PMU: 1124 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 1125 int i = 0, mode = 0; 1126 1127 if (test_bit(WCD_ADC1, &wcd938x->status_mask)) 1128 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]]; 1129 if (test_bit(WCD_ADC2, &wcd938x->status_mask)) 1130 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]]; 1131 if (test_bit(WCD_ADC3, &wcd938x->status_mask)) 1132 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]]; 1133 if (test_bit(WCD_ADC4, &wcd938x->status_mask)) 1134 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]]; 1135 1136 if (mode != 0) { 1137 for (i = 0; i < ADC_MODE_ULP2; i++) { 1138 if (mode & (1 << i)) { 1139 i++; 1140 break; 1141 } 1142 } 1143 } 1144 rate = wcd938x_get_clk_rate(i); 1145 wcd938x_set_swr_clk_rate(component, rate, bank); 1146 /* Copy clk settings to active bank */ 1147 wcd938x_set_swr_clk_rate(component, rate, !bank); 1148 } 1149 break; 1150 case SND_SOC_DAPM_POST_PMD: 1151 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 1152 rate = wcd938x_get_clk_rate(ADC_MODE_INVALID); 1153 wcd938x_set_swr_clk_rate(component, rate, !bank); 1154 wcd938x_set_swr_clk_rate(component, rate, bank); 1155 } 1156 break; 1157 } 1158 1159 return 0; 1160 } 1161 1162 static int wcd938x_get_adc_mode(int val) 1163 { 1164 int ret = 0; 1165 1166 switch (val) { 1167 case ADC_MODE_INVALID: 1168 ret = ADC_MODE_VAL_NORMAL; 1169 break; 1170 case ADC_MODE_HIFI: 1171 ret = ADC_MODE_VAL_HIFI; 1172 break; 1173 case ADC_MODE_LO_HIF: 1174 ret = ADC_MODE_VAL_LO_HIF; 1175 break; 1176 case ADC_MODE_NORMAL: 1177 ret = ADC_MODE_VAL_NORMAL; 1178 break; 1179 case ADC_MODE_LP: 1180 ret = ADC_MODE_VAL_LP; 1181 break; 1182 case ADC_MODE_ULP1: 1183 ret = ADC_MODE_VAL_ULP1; 1184 break; 1185 case ADC_MODE_ULP2: 1186 ret = ADC_MODE_VAL_ULP2; 1187 break; 1188 default: 1189 ret = -EINVAL; 1190 break; 1191 } 1192 return ret; 1193 } 1194 1195 static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w, 1196 struct snd_kcontrol *kcontrol, int event) 1197 { 1198 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1199 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1200 1201 switch (event) { 1202 case SND_SOC_DAPM_PRE_PMU: 1203 snd_soc_component_write_field(component, 1204 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1205 WCD938X_ANA_TX_CLK_EN_MASK, 1); 1206 snd_soc_component_write_field(component, 1207 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1208 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1); 1209 set_bit(w->shift, &wcd938x->status_mask); 1210 break; 1211 case SND_SOC_DAPM_POST_PMD: 1212 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1213 WCD938X_ANA_TX_CLK_EN_MASK, 0); 1214 clear_bit(w->shift, &wcd938x->status_mask); 1215 break; 1216 } 1217 1218 return 0; 1219 } 1220 1221 static void wcd938x_tx_channel_config(struct snd_soc_component *component, 1222 int channel, int mode) 1223 { 1224 int reg, mask; 1225 1226 switch (channel) { 1227 case 0: 1228 reg = WCD938X_ANA_TX_CH2; 1229 mask = WCD938X_HPF1_INIT_MASK; 1230 break; 1231 case 1: 1232 reg = WCD938X_ANA_TX_CH2; 1233 mask = WCD938X_HPF2_INIT_MASK; 1234 break; 1235 case 2: 1236 reg = WCD938X_ANA_TX_CH4; 1237 mask = WCD938X_HPF3_INIT_MASK; 1238 break; 1239 case 3: 1240 reg = WCD938X_ANA_TX_CH4; 1241 mask = WCD938X_HPF4_INIT_MASK; 1242 break; 1243 default: 1244 return; 1245 } 1246 1247 snd_soc_component_write_field(component, reg, mask, mode); 1248 } 1249 1250 static int wcd938x_adc_enable_req(struct snd_soc_dapm_widget *w, 1251 struct snd_kcontrol *kcontrol, int event) 1252 { 1253 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1254 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1255 int mode; 1256 1257 switch (event) { 1258 case SND_SOC_DAPM_PRE_PMU: 1259 snd_soc_component_write_field(component, 1260 WCD938X_DIGITAL_CDC_REQ_CTL, 1261 WCD938X_FS_RATE_4P8_MASK, 1); 1262 snd_soc_component_write_field(component, 1263 WCD938X_DIGITAL_CDC_REQ_CTL, 1264 WCD938X_NO_NOTCH_MASK, 0); 1265 wcd938x_tx_channel_config(component, w->shift, 1); 1266 mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]); 1267 if (mode < 0) { 1268 dev_info(component->dev, "Invalid ADC mode\n"); 1269 return -EINVAL; 1270 } 1271 switch (w->shift) { 1272 case 0: 1273 snd_soc_component_write_field(component, 1274 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1275 WCD938X_TXD0_MODE_MASK, mode); 1276 snd_soc_component_write_field(component, 1277 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1278 WCD938X_TXD0_CLK_EN_MASK, 1); 1279 break; 1280 case 1: 1281 snd_soc_component_write_field(component, 1282 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1283 WCD938X_TXD1_MODE_MASK, mode); 1284 snd_soc_component_write_field(component, 1285 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1286 WCD938X_TXD1_CLK_EN_MASK, 1); 1287 break; 1288 case 2: 1289 snd_soc_component_write_field(component, 1290 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1291 WCD938X_TXD2_MODE_MASK, mode); 1292 snd_soc_component_write_field(component, 1293 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1294 WCD938X_TXD2_CLK_EN_MASK, 1); 1295 break; 1296 case 3: 1297 snd_soc_component_write_field(component, 1298 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1299 WCD938X_TXD3_MODE_MASK, mode); 1300 snd_soc_component_write_field(component, 1301 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1302 WCD938X_TXD3_CLK_EN_MASK, 1); 1303 break; 1304 default: 1305 break; 1306 } 1307 1308 wcd938x_tx_channel_config(component, w->shift, 0); 1309 break; 1310 case SND_SOC_DAPM_POST_PMD: 1311 switch (w->shift) { 1312 case 0: 1313 snd_soc_component_write_field(component, 1314 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1315 WCD938X_TXD0_MODE_MASK, 0); 1316 snd_soc_component_write_field(component, 1317 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1318 WCD938X_TXD0_CLK_EN_MASK, 0); 1319 break; 1320 case 1: 1321 snd_soc_component_write_field(component, 1322 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1323 WCD938X_TXD1_MODE_MASK, 0); 1324 snd_soc_component_write_field(component, 1325 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1326 WCD938X_TXD1_CLK_EN_MASK, 0); 1327 break; 1328 case 2: 1329 snd_soc_component_write_field(component, 1330 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1331 WCD938X_TXD2_MODE_MASK, 0); 1332 snd_soc_component_write_field(component, 1333 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1334 WCD938X_TXD2_CLK_EN_MASK, 0); 1335 break; 1336 case 3: 1337 snd_soc_component_write_field(component, 1338 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1339 WCD938X_TXD3_MODE_MASK, 0); 1340 snd_soc_component_write_field(component, 1341 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1342 WCD938X_TXD3_CLK_EN_MASK, 0); 1343 break; 1344 default: 1345 break; 1346 } 1347 snd_soc_component_write_field(component, 1348 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1349 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 0); 1350 break; 1351 } 1352 1353 return 0; 1354 } 1355 1356 static int wcd938x_micbias_control(struct snd_soc_component *component, 1357 int micb_num, int req, bool is_dapm) 1358 { 1359 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1360 int micb_index = micb_num - 1; 1361 u16 micb_reg; 1362 1363 switch (micb_num) { 1364 case MIC_BIAS_1: 1365 micb_reg = WCD938X_ANA_MICB1; 1366 break; 1367 case MIC_BIAS_2: 1368 micb_reg = WCD938X_ANA_MICB2; 1369 break; 1370 case MIC_BIAS_3: 1371 micb_reg = WCD938X_ANA_MICB3; 1372 break; 1373 case MIC_BIAS_4: 1374 micb_reg = WCD938X_ANA_MICB4; 1375 break; 1376 default: 1377 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 1378 __func__, micb_num); 1379 return -EINVAL; 1380 } 1381 1382 switch (req) { 1383 case MICB_PULLUP_ENABLE: 1384 wcd938x->pullup_ref[micb_index]++; 1385 if ((wcd938x->pullup_ref[micb_index] == 1) && 1386 (wcd938x->micb_ref[micb_index] == 0)) 1387 snd_soc_component_write_field(component, micb_reg, 1388 WCD938X_MICB_EN_MASK, 1389 WCD938X_MICB_PULL_UP); 1390 break; 1391 case MICB_PULLUP_DISABLE: 1392 if (wcd938x->pullup_ref[micb_index] > 0) 1393 wcd938x->pullup_ref[micb_index]--; 1394 1395 if ((wcd938x->pullup_ref[micb_index] == 0) && 1396 (wcd938x->micb_ref[micb_index] == 0)) 1397 snd_soc_component_write_field(component, micb_reg, 1398 WCD938X_MICB_EN_MASK, 0); 1399 break; 1400 case MICB_ENABLE: 1401 wcd938x->micb_ref[micb_index]++; 1402 if (wcd938x->micb_ref[micb_index] == 1) { 1403 snd_soc_component_write_field(component, 1404 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1405 WCD938X_TX_CLK_EN_MASK, 0xF); 1406 snd_soc_component_write_field(component, 1407 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1408 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1); 1409 snd_soc_component_write_field(component, 1410 WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 1411 WCD938X_TX_SC_CLK_EN_MASK, 1); 1412 1413 snd_soc_component_write_field(component, micb_reg, 1414 WCD938X_MICB_EN_MASK, 1415 WCD938X_MICB_ENABLE); 1416 if (micb_num == MIC_BIAS_2) 1417 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1418 WCD_EVENT_POST_MICBIAS_2_ON); 1419 } 1420 if (micb_num == MIC_BIAS_2 && is_dapm) 1421 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1422 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 1423 1424 1425 break; 1426 case MICB_DISABLE: 1427 if (wcd938x->micb_ref[micb_index] > 0) 1428 wcd938x->micb_ref[micb_index]--; 1429 1430 if ((wcd938x->micb_ref[micb_index] == 0) && 1431 (wcd938x->pullup_ref[micb_index] > 0)) 1432 snd_soc_component_write_field(component, micb_reg, 1433 WCD938X_MICB_EN_MASK, 1434 WCD938X_MICB_PULL_UP); 1435 else if ((wcd938x->micb_ref[micb_index] == 0) && 1436 (wcd938x->pullup_ref[micb_index] == 0)) { 1437 if (micb_num == MIC_BIAS_2) 1438 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1439 WCD_EVENT_PRE_MICBIAS_2_OFF); 1440 1441 snd_soc_component_write_field(component, micb_reg, 1442 WCD938X_MICB_EN_MASK, 0); 1443 if (micb_num == MIC_BIAS_2) 1444 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1445 WCD_EVENT_POST_MICBIAS_2_OFF); 1446 } 1447 if (is_dapm && micb_num == MIC_BIAS_2) 1448 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1449 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 1450 break; 1451 } 1452 1453 return 0; 1454 } 1455 1456 static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1457 struct snd_kcontrol *kcontrol, 1458 int event) 1459 { 1460 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1461 int micb_num = w->shift; 1462 1463 switch (event) { 1464 case SND_SOC_DAPM_PRE_PMU: 1465 wcd938x_micbias_control(component, micb_num, MICB_ENABLE, true); 1466 break; 1467 case SND_SOC_DAPM_POST_PMU: 1468 /* 1 msec delay as per HW requirement */ 1469 usleep_range(1000, 1100); 1470 break; 1471 case SND_SOC_DAPM_POST_PMD: 1472 wcd938x_micbias_control(component, micb_num, MICB_DISABLE, true); 1473 break; 1474 } 1475 1476 return 0; 1477 } 1478 1479 static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1480 struct snd_kcontrol *kcontrol, 1481 int event) 1482 { 1483 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1484 int micb_num = w->shift; 1485 1486 switch (event) { 1487 case SND_SOC_DAPM_PRE_PMU: 1488 wcd938x_micbias_control(component, micb_num, 1489 MICB_PULLUP_ENABLE, true); 1490 break; 1491 case SND_SOC_DAPM_POST_PMU: 1492 /* 1 msec delay as per HW requirement */ 1493 usleep_range(1000, 1100); 1494 break; 1495 case SND_SOC_DAPM_POST_PMD: 1496 wcd938x_micbias_control(component, micb_num, 1497 MICB_PULLUP_DISABLE, true); 1498 break; 1499 } 1500 1501 return 0; 1502 } 1503 1504 static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol, 1505 struct snd_ctl_elem_value *ucontrol) 1506 { 1507 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1508 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1509 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1510 int path = e->shift_l; 1511 1512 ucontrol->value.enumerated.item[0] = wcd938x->tx_mode[path]; 1513 1514 return 0; 1515 } 1516 1517 static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol, 1518 struct snd_ctl_elem_value *ucontrol) 1519 { 1520 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1521 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1522 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1523 int path = e->shift_l; 1524 1525 if (wcd938x->tx_mode[path] == ucontrol->value.enumerated.item[0]) 1526 return 0; 1527 1528 wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0]; 1529 1530 return 1; 1531 } 1532 1533 static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 1534 struct snd_ctl_elem_value *ucontrol) 1535 { 1536 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1537 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1538 1539 ucontrol->value.enumerated.item[0] = wcd938x->hph_mode; 1540 1541 return 0; 1542 } 1543 1544 static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 1545 struct snd_ctl_elem_value *ucontrol) 1546 { 1547 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1548 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1549 1550 if (wcd938x->hph_mode == ucontrol->value.enumerated.item[0]) 1551 return 0; 1552 1553 wcd938x->hph_mode = ucontrol->value.enumerated.item[0]; 1554 1555 return 1; 1556 } 1557 1558 static int wcd938x_ear_pa_put_gain(struct snd_kcontrol *kcontrol, 1559 struct snd_ctl_elem_value *ucontrol) 1560 { 1561 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1562 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1563 1564 if (wcd938x->comp1_enable) { 1565 dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n"); 1566 return -EINVAL; 1567 } 1568 1569 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 1570 WCD938X_EAR_GAIN_MASK, 1571 ucontrol->value.integer.value[0]); 1572 1573 return 1; 1574 } 1575 1576 static int wcd938x_get_compander(struct snd_kcontrol *kcontrol, 1577 struct snd_ctl_elem_value *ucontrol) 1578 { 1579 1580 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1581 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1582 struct soc_mixer_control *mc; 1583 bool hphr; 1584 1585 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1586 hphr = mc->shift; 1587 1588 if (hphr) 1589 ucontrol->value.integer.value[0] = wcd938x->comp2_enable; 1590 else 1591 ucontrol->value.integer.value[0] = wcd938x->comp1_enable; 1592 1593 return 0; 1594 } 1595 1596 static int wcd938x_set_compander(struct snd_kcontrol *kcontrol, 1597 struct snd_ctl_elem_value *ucontrol) 1598 { 1599 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1600 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1601 struct wcd938x_sdw_priv *wcd; 1602 int value = ucontrol->value.integer.value[0]; 1603 int portidx; 1604 struct soc_mixer_control *mc; 1605 bool hphr; 1606 1607 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1608 hphr = mc->shift; 1609 1610 wcd = wcd938x->sdw_priv[AIF1_PB]; 1611 1612 if (hphr) 1613 wcd938x->comp2_enable = value; 1614 else 1615 wcd938x->comp1_enable = value; 1616 1617 portidx = wcd->ch_info[mc->reg].port_num; 1618 1619 if (value) 1620 wcd938x_connect_port(wcd, portidx, mc->reg, true); 1621 else 1622 wcd938x_connect_port(wcd, portidx, mc->reg, false); 1623 1624 return 1; 1625 } 1626 1627 static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol, 1628 struct snd_ctl_elem_value *ucontrol) 1629 { 1630 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1631 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1632 1633 ucontrol->value.integer.value[0] = wcd938x->ldoh; 1634 1635 return 0; 1636 } 1637 1638 static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol, 1639 struct snd_ctl_elem_value *ucontrol) 1640 { 1641 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1642 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1643 1644 if (wcd938x->ldoh == ucontrol->value.integer.value[0]) 1645 return 0; 1646 1647 wcd938x->ldoh = ucontrol->value.integer.value[0]; 1648 1649 return 1; 1650 } 1651 1652 static const char * const tx_mode_mux_text_wcd9380[] = { 1653 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 1654 }; 1655 1656 static const char * const tx_mode_mux_text[] = { 1657 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 1658 "ADC_ULP1", "ADC_ULP2", 1659 }; 1660 1661 static const char * const rx_hph_mode_mux_text_wcd9380[] = { 1662 "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB", 1663 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP", 1664 "CLS_AB_LOHIFI", 1665 }; 1666 1667 static const char * const rx_hph_mode_mux_text[] = { 1668 "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI", 1669 "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI", 1670 }; 1671 1672 static const char * const adc2_mux_text[] = { 1673 "INP2", "INP3" 1674 }; 1675 1676 static const char * const adc3_mux_text[] = { 1677 "INP4", "INP6" 1678 }; 1679 1680 static const char * const adc4_mux_text[] = { 1681 "INP5", "INP7" 1682 }; 1683 1684 static const char * const rdac3_mux_text[] = { 1685 "RX1", "RX3" 1686 }; 1687 1688 static const char * const hdr12_mux_text[] = { 1689 "NO_HDR12", "HDR12" 1690 }; 1691 1692 static const char * const hdr34_mux_text[] = { 1693 "NO_HDR34", "HDR34" 1694 }; 1695 1696 static const struct soc_enum tx0_mode_enum_wcd9380 = 1697 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1698 tx_mode_mux_text_wcd9380); 1699 1700 static const struct soc_enum tx1_mode_enum_wcd9380 = 1701 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1702 tx_mode_mux_text_wcd9380); 1703 1704 static const struct soc_enum tx2_mode_enum_wcd9380 = 1705 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1706 tx_mode_mux_text_wcd9380); 1707 1708 static const struct soc_enum tx3_mode_enum_wcd9380 = 1709 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1710 tx_mode_mux_text_wcd9380); 1711 1712 static const struct soc_enum tx0_mode_enum_wcd9385 = 1713 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text), 1714 tx_mode_mux_text); 1715 1716 static const struct soc_enum tx1_mode_enum_wcd9385 = 1717 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text), 1718 tx_mode_mux_text); 1719 1720 static const struct soc_enum tx2_mode_enum_wcd9385 = 1721 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text), 1722 tx_mode_mux_text); 1723 1724 static const struct soc_enum tx3_mode_enum_wcd9385 = 1725 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text), 1726 tx_mode_mux_text); 1727 1728 static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 = 1729 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380), 1730 rx_hph_mode_mux_text_wcd9380); 1731 1732 static const struct soc_enum rx_hph_mode_mux_enum = 1733 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 1734 rx_hph_mode_mux_text); 1735 1736 static const struct soc_enum adc2_enum = 1737 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7, 1738 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 1739 1740 static const struct soc_enum adc3_enum = 1741 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6, 1742 ARRAY_SIZE(adc3_mux_text), adc3_mux_text); 1743 1744 static const struct soc_enum adc4_enum = 1745 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5, 1746 ARRAY_SIZE(adc4_mux_text), adc4_mux_text); 1747 1748 static const struct soc_enum hdr12_enum = 1749 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4, 1750 ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text); 1751 1752 static const struct soc_enum hdr34_enum = 1753 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3, 1754 ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text); 1755 1756 static const struct soc_enum rdac3_enum = 1757 SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0, 1758 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 1759 1760 static const struct snd_kcontrol_new adc1_switch[] = { 1761 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1762 }; 1763 1764 static const struct snd_kcontrol_new adc2_switch[] = { 1765 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1766 }; 1767 1768 static const struct snd_kcontrol_new adc3_switch[] = { 1769 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1770 }; 1771 1772 static const struct snd_kcontrol_new adc4_switch[] = { 1773 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1774 }; 1775 1776 static const struct snd_kcontrol_new dmic1_switch[] = { 1777 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1778 }; 1779 1780 static const struct snd_kcontrol_new dmic2_switch[] = { 1781 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1782 }; 1783 1784 static const struct snd_kcontrol_new dmic3_switch[] = { 1785 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1786 }; 1787 1788 static const struct snd_kcontrol_new dmic4_switch[] = { 1789 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1790 }; 1791 1792 static const struct snd_kcontrol_new dmic5_switch[] = { 1793 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1794 }; 1795 1796 static const struct snd_kcontrol_new dmic6_switch[] = { 1797 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1798 }; 1799 1800 static const struct snd_kcontrol_new dmic7_switch[] = { 1801 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1802 }; 1803 1804 static const struct snd_kcontrol_new dmic8_switch[] = { 1805 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1806 }; 1807 1808 static const struct snd_kcontrol_new ear_rdac_switch[] = { 1809 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1810 }; 1811 1812 static const struct snd_kcontrol_new aux_rdac_switch[] = { 1813 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1814 }; 1815 1816 static const struct snd_kcontrol_new hphl_rdac_switch[] = { 1817 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1818 }; 1819 1820 static const struct snd_kcontrol_new hphr_rdac_switch[] = { 1821 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1822 }; 1823 1824 static const struct snd_kcontrol_new tx_adc2_mux = 1825 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 1826 1827 static const struct snd_kcontrol_new tx_adc3_mux = 1828 SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum); 1829 1830 static const struct snd_kcontrol_new tx_adc4_mux = 1831 SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum); 1832 1833 static const struct snd_kcontrol_new tx_hdr12_mux = 1834 SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum); 1835 1836 static const struct snd_kcontrol_new tx_hdr34_mux = 1837 SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum); 1838 1839 static const struct snd_kcontrol_new rx_rdac3_mux = 1840 SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 1841 1842 static const struct snd_kcontrol_new wcd9380_snd_controls[] = { 1843 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380, 1844 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put), 1845 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9380, 1846 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1847 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9380, 1848 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1849 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9380, 1850 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1851 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9380, 1852 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1853 }; 1854 1855 static const struct snd_kcontrol_new wcd9385_snd_controls[] = { 1856 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 1857 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put), 1858 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9385, 1859 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1860 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9385, 1861 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1862 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9385, 1863 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1864 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9385, 1865 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1866 }; 1867 1868 static int wcd938x_get_swr_port(struct snd_kcontrol *kcontrol, 1869 struct snd_ctl_elem_value *ucontrol) 1870 { 1871 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1872 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp); 1873 struct wcd938x_sdw_priv *wcd; 1874 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1875 int dai_id = mixer->shift; 1876 int portidx, ch_idx = mixer->reg; 1877 1878 1879 wcd = wcd938x->sdw_priv[dai_id]; 1880 portidx = wcd->ch_info[ch_idx].port_num; 1881 1882 ucontrol->value.integer.value[0] = wcd->port_enable[portidx]; 1883 1884 return 0; 1885 } 1886 1887 static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol, 1888 struct snd_ctl_elem_value *ucontrol) 1889 { 1890 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1891 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp); 1892 struct wcd938x_sdw_priv *wcd; 1893 struct soc_mixer_control *mixer = 1894 (struct soc_mixer_control *)kcontrol->private_value; 1895 int ch_idx = mixer->reg; 1896 int portidx; 1897 int dai_id = mixer->shift; 1898 bool enable; 1899 1900 wcd = wcd938x->sdw_priv[dai_id]; 1901 1902 portidx = wcd->ch_info[ch_idx].port_num; 1903 if (ucontrol->value.integer.value[0]) 1904 enable = true; 1905 else 1906 enable = false; 1907 1908 wcd->port_enable[portidx] = enable; 1909 1910 wcd938x_connect_port(wcd, portidx, ch_idx, enable); 1911 1912 return 1; 1913 1914 } 1915 1916 /* MBHC related */ 1917 static void wcd938x_mbhc_clk_setup(struct snd_soc_component *component, 1918 bool enable) 1919 { 1920 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_1, 1921 WCD938X_MBHC_CTL_RCO_EN_MASK, enable); 1922 } 1923 1924 static void wcd938x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 1925 bool enable) 1926 { 1927 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_ELECT, 1928 WCD938X_ANA_MBHC_BIAS_EN, enable); 1929 } 1930 1931 static void wcd938x_mbhc_program_btn_thr(struct snd_soc_component *component, 1932 int *btn_low, int *btn_high, 1933 int num_btn, bool is_micbias) 1934 { 1935 int i, vth; 1936 1937 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 1938 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 1939 __func__, num_btn); 1940 return; 1941 } 1942 1943 for (i = 0; i < num_btn; i++) { 1944 vth = ((btn_high[i] * 2) / 25) & 0x3F; 1945 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_BTN0 + i, 1946 WCD938X_MBHC_BTN_VTH_MASK, vth); 1947 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n", 1948 __func__, i, btn_high[i], vth); 1949 } 1950 } 1951 1952 static bool wcd938x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 1953 { 1954 u8 val; 1955 1956 if (micb_num == MIC_BIAS_2) { 1957 val = snd_soc_component_read_field(component, 1958 WCD938X_ANA_MICB2, 1959 WCD938X_MICB_EN_MASK); 1960 if (val == WCD938X_MICB_ENABLE) 1961 return true; 1962 } 1963 return false; 1964 } 1965 1966 static void wcd938x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 1967 int pull_up_cur) 1968 { 1969 /* Default pull up current to 2uA */ 1970 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA) 1971 pull_up_cur = HS_PULLUP_I_2P0_UA; 1972 1973 snd_soc_component_write_field(component, 1974 WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 1975 WCD938X_HSDET_PULLUP_C_MASK, pull_up_cur); 1976 } 1977 1978 static int wcd938x_mbhc_request_micbias(struct snd_soc_component *component, 1979 int micb_num, int req) 1980 { 1981 return wcd938x_micbias_control(component, micb_num, req, false); 1982 } 1983 1984 static void wcd938x_mbhc_micb_ramp_control(struct snd_soc_component *component, 1985 bool enable) 1986 { 1987 if (enable) { 1988 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1989 WCD938X_RAMP_SHIFT_CTRL_MASK, 0x0C); 1990 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1991 WCD938X_RAMP_EN_MASK, 1); 1992 } else { 1993 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1994 WCD938X_RAMP_EN_MASK, 0); 1995 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1996 WCD938X_RAMP_SHIFT_CTRL_MASK, 0); 1997 } 1998 } 1999 2000 static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv) 2001 { 2002 /* min micbias voltage is 1V and maximum is 2.85V */ 2003 if (micb_mv < 1000 || micb_mv > 2850) 2004 return -EINVAL; 2005 2006 return (micb_mv - 1000) / 50; 2007 } 2008 2009 static int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 2010 int req_volt, int micb_num) 2011 { 2012 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2013 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 2014 2015 switch (micb_num) { 2016 case MIC_BIAS_1: 2017 micb_reg = WCD938X_ANA_MICB1; 2018 break; 2019 case MIC_BIAS_2: 2020 micb_reg = WCD938X_ANA_MICB2; 2021 break; 2022 case MIC_BIAS_3: 2023 micb_reg = WCD938X_ANA_MICB3; 2024 break; 2025 case MIC_BIAS_4: 2026 micb_reg = WCD938X_ANA_MICB4; 2027 break; 2028 default: 2029 return -EINVAL; 2030 } 2031 mutex_lock(&wcd938x->micb_lock); 2032 /* 2033 * If requested micbias voltage is same as current micbias 2034 * voltage, then just return. Otherwise, adjust voltage as 2035 * per requested value. If micbias is already enabled, then 2036 * to avoid slow micbias ramp-up or down enable pull-up 2037 * momentarily, change the micbias value and then re-enable 2038 * micbias. 2039 */ 2040 micb_en = snd_soc_component_read_field(component, micb_reg, 2041 WCD938X_MICB_EN_MASK); 2042 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 2043 WCD938X_MICB_VOUT_MASK); 2044 2045 req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt); 2046 if (req_vout_ctl < 0) { 2047 ret = -EINVAL; 2048 goto exit; 2049 } 2050 2051 if (cur_vout_ctl == req_vout_ctl) { 2052 ret = 0; 2053 goto exit; 2054 } 2055 2056 if (micb_en == WCD938X_MICB_ENABLE) 2057 snd_soc_component_write_field(component, micb_reg, 2058 WCD938X_MICB_EN_MASK, 2059 WCD938X_MICB_PULL_UP); 2060 2061 snd_soc_component_write_field(component, micb_reg, 2062 WCD938X_MICB_VOUT_MASK, 2063 req_vout_ctl); 2064 2065 if (micb_en == WCD938X_MICB_ENABLE) { 2066 snd_soc_component_write_field(component, micb_reg, 2067 WCD938X_MICB_EN_MASK, 2068 WCD938X_MICB_ENABLE); 2069 /* 2070 * Add 2ms delay as per HW requirement after enabling 2071 * micbias 2072 */ 2073 usleep_range(2000, 2100); 2074 } 2075 exit: 2076 mutex_unlock(&wcd938x->micb_lock); 2077 return ret; 2078 } 2079 2080 static int wcd938x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 2081 int micb_num, bool req_en) 2082 { 2083 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2084 int micb_mv; 2085 2086 if (micb_num != MIC_BIAS_2) 2087 return -EINVAL; 2088 /* 2089 * If device tree micbias level is already above the minimum 2090 * voltage needed to detect threshold microphone, then do 2091 * not change the micbias, just return. 2092 */ 2093 if (wcd938x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 2094 return 0; 2095 2096 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd938x->micb2_mv; 2097 2098 return wcd938x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 2099 } 2100 2101 static void wcd938x_mbhc_get_result_params(struct snd_soc_component *component, 2102 s16 *d1_a, u16 noff, 2103 int32_t *zdet) 2104 { 2105 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2106 int i; 2107 int val, val1; 2108 s16 c1; 2109 s32 x1, d1; 2110 int32_t denom; 2111 static const int minCode_param[] = { 2112 3277, 1639, 820, 410, 205, 103, 52, 26 2113 }; 2114 2115 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x20); 2116 for (i = 0; i < WCD938X_ZDET_NUM_MEASUREMENTS; i++) { 2117 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_2, &val); 2118 if (val & 0x80) 2119 break; 2120 } 2121 val = val << 0x8; 2122 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_1, &val1); 2123 val |= val1; 2124 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x00); 2125 x1 = WCD938X_MBHC_GET_X1(val); 2126 c1 = WCD938X_MBHC_GET_C1(val); 2127 /* If ramp is not complete, give additional 5ms */ 2128 if ((c1 < 2) && x1) 2129 usleep_range(5000, 5050); 2130 2131 if (!c1 || !x1) { 2132 dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n", 2133 c1, x1); 2134 goto ramp_down; 2135 } 2136 d1 = d1_a[c1]; 2137 denom = (x1 * d1) - (1 << (14 - noff)); 2138 if (denom > 0) 2139 *zdet = (WCD938X_MBHC_ZDET_CONST * 1000) / denom; 2140 else if (x1 < minCode_param[noff]) 2141 *zdet = WCD938X_ZDET_FLOATING_IMPEDANCE; 2142 2143 dev_dbg(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n", 2144 __func__, d1, c1, x1, *zdet); 2145 ramp_down: 2146 i = 0; 2147 while (x1) { 2148 regmap_read(wcd938x->regmap, 2149 WCD938X_ANA_MBHC_RESULT_1, &val); 2150 regmap_read(wcd938x->regmap, 2151 WCD938X_ANA_MBHC_RESULT_2, &val1); 2152 val = val << 0x08; 2153 val |= val1; 2154 x1 = WCD938X_MBHC_GET_X1(val); 2155 i++; 2156 if (i == WCD938X_ZDET_NUM_MEASUREMENTS) 2157 break; 2158 } 2159 } 2160 2161 static void wcd938x_mbhc_zdet_ramp(struct snd_soc_component *component, 2162 struct wcd938x_mbhc_zdet_param *zdet_param, 2163 int32_t *zl, int32_t *zr, s16 *d1_a) 2164 { 2165 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2166 int32_t zdet = 0; 2167 2168 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, 2169 WCD938X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 2170 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN5, 2171 WCD938X_VTH_MASK, zdet_param->btn5); 2172 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN6, 2173 WCD938X_VTH_MASK, zdet_param->btn6); 2174 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN7, 2175 WCD938X_VTH_MASK, zdet_param->btn7); 2176 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, 2177 WCD938X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 2178 snd_soc_component_update_bits(component, WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 2179 0x0F, zdet_param->nshift); 2180 2181 if (!zl) 2182 goto z_right; 2183 /* Start impedance measurement for HPH_L */ 2184 regmap_update_bits(wcd938x->regmap, 2185 WCD938X_ANA_MBHC_ZDET, 0x80, 0x80); 2186 dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n", 2187 __func__, zdet_param->noff); 2188 wcd938x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 2189 regmap_update_bits(wcd938x->regmap, 2190 WCD938X_ANA_MBHC_ZDET, 0x80, 0x00); 2191 2192 *zl = zdet; 2193 2194 z_right: 2195 if (!zr) 2196 return; 2197 /* Start impedance measurement for HPH_R */ 2198 regmap_update_bits(wcd938x->regmap, 2199 WCD938X_ANA_MBHC_ZDET, 0x40, 0x40); 2200 dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n", 2201 __func__, zdet_param->noff); 2202 wcd938x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 2203 regmap_update_bits(wcd938x->regmap, 2204 WCD938X_ANA_MBHC_ZDET, 0x40, 0x00); 2205 2206 *zr = zdet; 2207 } 2208 2209 static void wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2210 int32_t *z_val, int flag_l_r) 2211 { 2212 s16 q1; 2213 int q1_cal; 2214 2215 if (*z_val < (WCD938X_ZDET_VAL_400/1000)) 2216 q1 = snd_soc_component_read(component, 2217 WCD938X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r)); 2218 else 2219 q1 = snd_soc_component_read(component, 2220 WCD938X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r)); 2221 if (q1 & 0x80) 2222 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 2223 else 2224 q1_cal = (10000 + (q1 * 25)); 2225 if (q1_cal > 0) 2226 *z_val = ((*z_val) * 10000) / q1_cal; 2227 } 2228 2229 static void wcd938x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 2230 uint32_t *zl, uint32_t *zr) 2231 { 2232 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2233 s16 reg0, reg1, reg2, reg3, reg4; 2234 int32_t z1L, z1R, z1Ls; 2235 int zMono, z_diff1, z_diff2; 2236 bool is_fsm_disable = false; 2237 struct wcd938x_mbhc_zdet_param zdet_param[] = { 2238 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 2239 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 2240 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 2241 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 2242 }; 2243 struct wcd938x_mbhc_zdet_param *zdet_param_ptr = NULL; 2244 s16 d1_a[][4] = { 2245 {0, 30, 90, 30}, 2246 {0, 30, 30, 5}, 2247 {0, 30, 30, 5}, 2248 {0, 30, 30, 5}, 2249 }; 2250 s16 *d1 = NULL; 2251 2252 reg0 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN5); 2253 reg1 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN6); 2254 reg2 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN7); 2255 reg3 = snd_soc_component_read(component, WCD938X_MBHC_CTL_CLK); 2256 reg4 = snd_soc_component_read(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL); 2257 2258 if (snd_soc_component_read(component, WCD938X_ANA_MBHC_ELECT) & 0x80) { 2259 is_fsm_disable = true; 2260 regmap_update_bits(wcd938x->regmap, 2261 WCD938X_ANA_MBHC_ELECT, 0x80, 0x00); 2262 } 2263 2264 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 2265 if (wcd938x->mbhc_cfg.hphl_swh) 2266 regmap_update_bits(wcd938x->regmap, 2267 WCD938X_ANA_MBHC_MECH, 0x80, 0x00); 2268 2269 /* Turn off 100k pull down on HPHL */ 2270 regmap_update_bits(wcd938x->regmap, 2271 WCD938X_ANA_MBHC_MECH, 0x01, 0x00); 2272 2273 /* Disable surge protection before impedance detection. 2274 * This is done to give correct value for high impedance. 2275 */ 2276 regmap_update_bits(wcd938x->regmap, 2277 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00); 2278 /* 1ms delay needed after disable surge protection */ 2279 usleep_range(1000, 1010); 2280 2281 /* First get impedance on Left */ 2282 d1 = d1_a[1]; 2283 zdet_param_ptr = &zdet_param[1]; 2284 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2285 2286 if (!WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L)) 2287 goto left_ch_impedance; 2288 2289 /* Second ramp for left ch */ 2290 if (z1L < WCD938X_ZDET_VAL_32) { 2291 zdet_param_ptr = &zdet_param[0]; 2292 d1 = d1_a[0]; 2293 } else if ((z1L > WCD938X_ZDET_VAL_400) && 2294 (z1L <= WCD938X_ZDET_VAL_1200)) { 2295 zdet_param_ptr = &zdet_param[2]; 2296 d1 = d1_a[2]; 2297 } else if (z1L > WCD938X_ZDET_VAL_1200) { 2298 zdet_param_ptr = &zdet_param[3]; 2299 d1 = d1_a[3]; 2300 } 2301 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2302 2303 left_ch_impedance: 2304 if ((z1L == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2305 (z1L > WCD938X_ZDET_VAL_100K)) { 2306 *zl = WCD938X_ZDET_FLOATING_IMPEDANCE; 2307 zdet_param_ptr = &zdet_param[1]; 2308 d1 = d1_a[1]; 2309 } else { 2310 *zl = z1L/1000; 2311 wcd938x_wcd_mbhc_qfuse_cal(component, zl, 0); 2312 } 2313 dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 2314 __func__, *zl); 2315 2316 /* Start of right impedance ramp and calculation */ 2317 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2318 if (WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) { 2319 if (((z1R > WCD938X_ZDET_VAL_1200) && 2320 (zdet_param_ptr->noff == 0x6)) || 2321 ((*zl) != WCD938X_ZDET_FLOATING_IMPEDANCE)) 2322 goto right_ch_impedance; 2323 /* Second ramp for right ch */ 2324 if (z1R < WCD938X_ZDET_VAL_32) { 2325 zdet_param_ptr = &zdet_param[0]; 2326 d1 = d1_a[0]; 2327 } else if ((z1R > WCD938X_ZDET_VAL_400) && 2328 (z1R <= WCD938X_ZDET_VAL_1200)) { 2329 zdet_param_ptr = &zdet_param[2]; 2330 d1 = d1_a[2]; 2331 } else if (z1R > WCD938X_ZDET_VAL_1200) { 2332 zdet_param_ptr = &zdet_param[3]; 2333 d1 = d1_a[3]; 2334 } 2335 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2336 } 2337 right_ch_impedance: 2338 if ((z1R == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2339 (z1R > WCD938X_ZDET_VAL_100K)) { 2340 *zr = WCD938X_ZDET_FLOATING_IMPEDANCE; 2341 } else { 2342 *zr = z1R/1000; 2343 wcd938x_wcd_mbhc_qfuse_cal(component, zr, 1); 2344 } 2345 dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 2346 __func__, *zr); 2347 2348 /* Mono/stereo detection */ 2349 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) && 2350 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE)) { 2351 dev_dbg(component->dev, 2352 "%s: plug type is invalid or extension cable\n", 2353 __func__); 2354 goto zdet_complete; 2355 } 2356 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2357 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2358 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 2359 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 2360 dev_dbg(component->dev, 2361 "%s: Mono plug type with one ch floating or shorted to GND\n", 2362 __func__); 2363 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO); 2364 goto zdet_complete; 2365 } 2366 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST, 2367 WCD938X_HPHPA_GND_OVR_MASK, 1); 2368 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2369 WCD938X_HPHPA_GND_R_MASK, 1); 2370 if (*zl < (WCD938X_ZDET_VAL_32/1000)) 2371 wcd938x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1); 2372 else 2373 wcd938x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1); 2374 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2375 WCD938X_HPHPA_GND_R_MASK, 0); 2376 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST, 2377 WCD938X_HPHPA_GND_OVR_MASK, 0); 2378 z1Ls /= 1000; 2379 wcd938x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0); 2380 /* Parallel of left Z and 9 ohm pull down resistor */ 2381 zMono = ((*zl) * 9) / ((*zl) + 9); 2382 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls); 2383 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl)); 2384 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) { 2385 dev_dbg(component->dev, "%s: stereo plug type detected\n", 2386 __func__); 2387 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 2388 } else { 2389 dev_dbg(component->dev, "%s: MONO plug type detected\n", 2390 __func__); 2391 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO); 2392 } 2393 2394 /* Enable surge protection again after impedance detection */ 2395 regmap_update_bits(wcd938x->regmap, 2396 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 2397 zdet_complete: 2398 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN5, reg0); 2399 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN6, reg1); 2400 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN7, reg2); 2401 /* Turn on 100k pull down on HPHL */ 2402 regmap_update_bits(wcd938x->regmap, 2403 WCD938X_ANA_MBHC_MECH, 0x01, 0x01); 2404 2405 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 2406 if (wcd938x->mbhc_cfg.hphl_swh) 2407 regmap_update_bits(wcd938x->regmap, 2408 WCD938X_ANA_MBHC_MECH, 0x80, 0x80); 2409 2410 snd_soc_component_write(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, reg4); 2411 snd_soc_component_write(component, WCD938X_MBHC_CTL_CLK, reg3); 2412 if (is_fsm_disable) 2413 regmap_update_bits(wcd938x->regmap, 2414 WCD938X_ANA_MBHC_ELECT, 0x80, 0x80); 2415 } 2416 2417 static void wcd938x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 2418 bool enable) 2419 { 2420 if (enable) { 2421 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2422 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 1); 2423 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2424 WCD938X_MBHC_GND_DET_EN_MASK, 1); 2425 } else { 2426 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2427 WCD938X_MBHC_GND_DET_EN_MASK, 0); 2428 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2429 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 0); 2430 } 2431 } 2432 2433 static void wcd938x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 2434 bool enable) 2435 { 2436 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2437 WCD938X_HPHPA_GND_R_MASK, enable); 2438 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2439 WCD938X_HPHPA_GND_L_MASK, enable); 2440 } 2441 2442 static void wcd938x_mbhc_moisture_config(struct snd_soc_component *component) 2443 { 2444 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2445 2446 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) { 2447 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2448 WCD938X_M_RTH_CTL_MASK, R_OFF); 2449 return; 2450 } 2451 2452 /* Do not enable moisture detection if jack type is NC */ 2453 if (!wcd938x->mbhc_cfg.hphl_swh) { 2454 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 2455 __func__); 2456 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2457 WCD938X_M_RTH_CTL_MASK, R_OFF); 2458 return; 2459 } 2460 2461 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2462 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref); 2463 } 2464 2465 static void wcd938x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 2466 { 2467 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2468 2469 if (enable) 2470 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2471 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref); 2472 else 2473 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2474 WCD938X_M_RTH_CTL_MASK, R_OFF); 2475 } 2476 2477 static bool wcd938x_mbhc_get_moisture_status(struct snd_soc_component *component) 2478 { 2479 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2480 bool ret = false; 2481 2482 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) { 2483 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2484 WCD938X_M_RTH_CTL_MASK, R_OFF); 2485 goto done; 2486 } 2487 2488 /* Do not enable moisture detection if jack type is NC */ 2489 if (!wcd938x->mbhc_cfg.hphl_swh) { 2490 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 2491 __func__); 2492 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2493 WCD938X_M_RTH_CTL_MASK, R_OFF); 2494 goto done; 2495 } 2496 2497 /* 2498 * If moisture_en is already enabled, then skip to plug type 2499 * detection. 2500 */ 2501 if (snd_soc_component_read_field(component, WCD938X_MBHC_NEW_CTL_2, WCD938X_M_RTH_CTL_MASK)) 2502 goto done; 2503 2504 wcd938x_mbhc_moisture_detect_en(component, true); 2505 /* Read moisture comparator status */ 2506 ret = ((snd_soc_component_read(component, WCD938X_MBHC_NEW_FSM_STATUS) 2507 & 0x20) ? 0 : 1); 2508 2509 done: 2510 return ret; 2511 2512 } 2513 2514 static void wcd938x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 2515 bool enable) 2516 { 2517 snd_soc_component_write_field(component, 2518 WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 2519 WCD938X_MOISTURE_EN_POLLING_MASK, enable); 2520 } 2521 2522 static const struct wcd_mbhc_cb mbhc_cb = { 2523 .clk_setup = wcd938x_mbhc_clk_setup, 2524 .mbhc_bias = wcd938x_mbhc_mbhc_bias_control, 2525 .set_btn_thr = wcd938x_mbhc_program_btn_thr, 2526 .micbias_enable_status = wcd938x_mbhc_micb_en_status, 2527 .hph_pull_up_control_v2 = wcd938x_mbhc_hph_l_pull_up_control, 2528 .mbhc_micbias_control = wcd938x_mbhc_request_micbias, 2529 .mbhc_micb_ramp_control = wcd938x_mbhc_micb_ramp_control, 2530 .mbhc_micb_ctrl_thr_mic = wcd938x_mbhc_micb_ctrl_threshold_mic, 2531 .compute_impedance = wcd938x_wcd_mbhc_calc_impedance, 2532 .mbhc_gnd_det_ctrl = wcd938x_mbhc_gnd_det_ctrl, 2533 .hph_pull_down_ctrl = wcd938x_mbhc_hph_pull_down_ctrl, 2534 .mbhc_moisture_config = wcd938x_mbhc_moisture_config, 2535 .mbhc_get_moisture_status = wcd938x_mbhc_get_moisture_status, 2536 .mbhc_moisture_polling_ctrl = wcd938x_mbhc_moisture_polling_ctrl, 2537 .mbhc_moisture_detect_en = wcd938x_mbhc_moisture_detect_en, 2538 }; 2539 2540 static int wcd938x_get_hph_type(struct snd_kcontrol *kcontrol, 2541 struct snd_ctl_elem_value *ucontrol) 2542 { 2543 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2544 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2545 2546 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd938x->wcd_mbhc); 2547 2548 return 0; 2549 } 2550 2551 static int wcd938x_hph_impedance_get(struct snd_kcontrol *kcontrol, 2552 struct snd_ctl_elem_value *ucontrol) 2553 { 2554 uint32_t zl, zr; 2555 bool hphr; 2556 struct soc_mixer_control *mc; 2557 struct snd_soc_component *component = 2558 snd_soc_kcontrol_component(kcontrol); 2559 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2560 2561 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2562 hphr = mc->shift; 2563 wcd_mbhc_get_impedance(wcd938x->wcd_mbhc, &zl, &zr); 2564 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 2565 ucontrol->value.integer.value[0] = hphr ? zr : zl; 2566 2567 return 0; 2568 } 2569 2570 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 2571 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 2572 wcd938x_get_hph_type, NULL), 2573 }; 2574 2575 static const struct snd_kcontrol_new impedance_detect_controls[] = { 2576 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 2577 wcd938x_hph_impedance_get, NULL), 2578 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 2579 wcd938x_hph_impedance_get, NULL), 2580 }; 2581 2582 static int wcd938x_mbhc_init(struct snd_soc_component *component) 2583 { 2584 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2585 struct wcd_mbhc_intr *intr_ids = &wcd938x->intr_ids; 2586 2587 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2588 WCD938X_IRQ_MBHC_SW_DET); 2589 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2590 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET); 2591 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2592 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET); 2593 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2594 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 2595 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2596 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET); 2597 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd938x->irq_chip, 2598 WCD938X_IRQ_HPHL_OCP_INT); 2599 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd938x->irq_chip, 2600 WCD938X_IRQ_HPHR_OCP_INT); 2601 2602 wcd938x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2603 if (IS_ERR(wcd938x->wcd_mbhc)) 2604 return PTR_ERR(wcd938x->wcd_mbhc); 2605 2606 snd_soc_add_component_controls(component, impedance_detect_controls, 2607 ARRAY_SIZE(impedance_detect_controls)); 2608 snd_soc_add_component_controls(component, hph_type_detect_controls, 2609 ARRAY_SIZE(hph_type_detect_controls)); 2610 2611 return 0; 2612 } 2613 2614 static void wcd938x_mbhc_deinit(struct snd_soc_component *component) 2615 { 2616 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2617 2618 wcd_mbhc_deinit(wcd938x->wcd_mbhc); 2619 } 2620 2621 /* END MBHC */ 2622 2623 static const struct snd_kcontrol_new wcd938x_snd_controls[] = { 2624 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0, 2625 wcd938x_get_compander, wcd938x_set_compander), 2626 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD938X_COMP_R, 1, 1, 0, 2627 wcd938x_get_compander, wcd938x_set_compander), 2628 SOC_SINGLE_EXT("HPHL Switch", WCD938X_HPH_L, 0, 1, 0, 2629 wcd938x_get_swr_port, wcd938x_set_swr_port), 2630 SOC_SINGLE_EXT("HPHR Switch", WCD938X_HPH_R, 0, 1, 0, 2631 wcd938x_get_swr_port, wcd938x_set_swr_port), 2632 SOC_SINGLE_EXT("CLSH Switch", WCD938X_CLSH, 0, 1, 0, 2633 wcd938x_get_swr_port, wcd938x_set_swr_port), 2634 SOC_SINGLE_EXT("LO Switch", WCD938X_LO, 0, 1, 0, 2635 wcd938x_get_swr_port, wcd938x_set_swr_port), 2636 SOC_SINGLE_EXT("DSD_L Switch", WCD938X_DSD_L, 0, 1, 0, 2637 wcd938x_get_swr_port, wcd938x_set_swr_port), 2638 SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0, 2639 wcd938x_get_swr_port, wcd938x_set_swr_port), 2640 SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 1, line_gain), 2641 SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 1, line_gain), 2642 WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL, 2643 2, 0x10, 0, ear_pa_gain), 2644 SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0, 2645 wcd938x_get_swr_port, wcd938x_set_swr_port), 2646 SOC_SINGLE_EXT("ADC2 Switch", WCD938X_ADC2, 1, 1, 0, 2647 wcd938x_get_swr_port, wcd938x_set_swr_port), 2648 SOC_SINGLE_EXT("ADC3 Switch", WCD938X_ADC3, 1, 1, 0, 2649 wcd938x_get_swr_port, wcd938x_set_swr_port), 2650 SOC_SINGLE_EXT("ADC4 Switch", WCD938X_ADC4, 1, 1, 0, 2651 wcd938x_get_swr_port, wcd938x_set_swr_port), 2652 SOC_SINGLE_EXT("DMIC0 Switch", WCD938X_DMIC0, 1, 1, 0, 2653 wcd938x_get_swr_port, wcd938x_set_swr_port), 2654 SOC_SINGLE_EXT("DMIC1 Switch", WCD938X_DMIC1, 1, 1, 0, 2655 wcd938x_get_swr_port, wcd938x_set_swr_port), 2656 SOC_SINGLE_EXT("MBHC Switch", WCD938X_MBHC, 1, 1, 0, 2657 wcd938x_get_swr_port, wcd938x_set_swr_port), 2658 SOC_SINGLE_EXT("DMIC2 Switch", WCD938X_DMIC2, 1, 1, 0, 2659 wcd938x_get_swr_port, wcd938x_set_swr_port), 2660 SOC_SINGLE_EXT("DMIC3 Switch", WCD938X_DMIC3, 1, 1, 0, 2661 wcd938x_get_swr_port, wcd938x_set_swr_port), 2662 SOC_SINGLE_EXT("DMIC4 Switch", WCD938X_DMIC4, 1, 1, 0, 2663 wcd938x_get_swr_port, wcd938x_set_swr_port), 2664 SOC_SINGLE_EXT("DMIC5 Switch", WCD938X_DMIC5, 1, 1, 0, 2665 wcd938x_get_swr_port, wcd938x_set_swr_port), 2666 SOC_SINGLE_EXT("DMIC6 Switch", WCD938X_DMIC6, 1, 1, 0, 2667 wcd938x_get_swr_port, wcd938x_set_swr_port), 2668 SOC_SINGLE_EXT("DMIC7 Switch", WCD938X_DMIC7, 1, 1, 0, 2669 wcd938x_get_swr_port, wcd938x_set_swr_port), 2670 SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0, 2671 wcd938x_ldoh_get, wcd938x_ldoh_put), 2672 2673 SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0, analog_gain), 2674 SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0, analog_gain), 2675 SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0, analog_gain), 2676 SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0, analog_gain), 2677 }; 2678 2679 static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = { 2680 2681 /*input widgets*/ 2682 SND_SOC_DAPM_INPUT("AMIC1"), 2683 SND_SOC_DAPM_INPUT("AMIC2"), 2684 SND_SOC_DAPM_INPUT("AMIC3"), 2685 SND_SOC_DAPM_INPUT("AMIC4"), 2686 SND_SOC_DAPM_INPUT("AMIC5"), 2687 SND_SOC_DAPM_INPUT("AMIC6"), 2688 SND_SOC_DAPM_INPUT("AMIC7"), 2689 SND_SOC_DAPM_MIC("Analog Mic1", NULL), 2690 SND_SOC_DAPM_MIC("Analog Mic2", NULL), 2691 SND_SOC_DAPM_MIC("Analog Mic3", NULL), 2692 SND_SOC_DAPM_MIC("Analog Mic4", NULL), 2693 SND_SOC_DAPM_MIC("Analog Mic5", NULL), 2694 2695 /*tx widgets*/ 2696 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 2697 wcd938x_codec_enable_adc, 2698 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2699 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 2700 wcd938x_codec_enable_adc, 2701 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2702 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 2703 wcd938x_codec_enable_adc, 2704 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2705 SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0, 2706 wcd938x_codec_enable_adc, 2707 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2708 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 2709 wcd938x_codec_enable_dmic, 2710 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2711 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 2712 wcd938x_codec_enable_dmic, 2713 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2714 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 2715 wcd938x_codec_enable_dmic, 2716 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2717 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 2718 wcd938x_codec_enable_dmic, 2719 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2720 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 2721 wcd938x_codec_enable_dmic, 2722 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2723 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 2724 wcd938x_codec_enable_dmic, 2725 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2726 SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0, 2727 wcd938x_codec_enable_dmic, 2728 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2729 SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0, 2730 wcd938x_codec_enable_dmic, 2731 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2732 2733 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, 2734 NULL, 0, wcd938x_adc_enable_req, 2735 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2736 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0, 2737 NULL, 0, wcd938x_adc_enable_req, 2738 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2739 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0, 2740 NULL, 0, wcd938x_adc_enable_req, 2741 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2742 SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0, 2743 wcd938x_adc_enable_req, 2744 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2745 2746 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 2747 SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux), 2748 SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux), 2749 SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr12_mux), 2750 SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr34_mux), 2751 2752 /*tx mixers*/ 2753 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, adc1_switch, 2754 ARRAY_SIZE(adc1_switch), wcd938x_tx_swr_ctrl, 2755 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2756 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, adc2_switch, 2757 ARRAY_SIZE(adc2_switch), wcd938x_tx_swr_ctrl, 2758 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2759 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch, 2760 ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl, 2761 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2762 SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch, 2763 ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl, 2764 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2765 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, dmic1_switch, 2766 ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl, 2767 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2768 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, dmic2_switch, 2769 ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl, 2770 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2771 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, dmic3_switch, 2772 ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl, 2773 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2774 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, dmic4_switch, 2775 ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl, 2776 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2777 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, dmic5_switch, 2778 ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl, 2779 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2780 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, dmic6_switch, 2781 ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl, 2782 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2783 SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, dmic7_switch, 2784 ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl, 2785 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2786 SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, dmic8_switch, 2787 ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl, 2788 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2789 /* micbias widgets*/ 2790 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2791 wcd938x_codec_enable_micbias, 2792 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2793 SND_SOC_DAPM_POST_PMD), 2794 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2795 wcd938x_codec_enable_micbias, 2796 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2797 SND_SOC_DAPM_POST_PMD), 2798 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2799 wcd938x_codec_enable_micbias, 2800 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2801 SND_SOC_DAPM_POST_PMD), 2802 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 2803 wcd938x_codec_enable_micbias, 2804 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2805 SND_SOC_DAPM_POST_PMD), 2806 2807 /* micbias pull up widgets*/ 2808 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2809 wcd938x_codec_enable_micbias_pullup, 2810 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2811 SND_SOC_DAPM_POST_PMD), 2812 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2813 wcd938x_codec_enable_micbias_pullup, 2814 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2815 SND_SOC_DAPM_POST_PMD), 2816 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2817 wcd938x_codec_enable_micbias_pullup, 2818 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2819 SND_SOC_DAPM_POST_PMD), 2820 SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 2821 wcd938x_codec_enable_micbias_pullup, 2822 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2823 SND_SOC_DAPM_POST_PMD), 2824 2825 /*output widgets tx*/ 2826 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 2827 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 2828 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 2829 SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"), 2830 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 2831 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 2832 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 2833 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 2834 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 2835 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 2836 SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"), 2837 SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"), 2838 2839 SND_SOC_DAPM_INPUT("IN1_HPHL"), 2840 SND_SOC_DAPM_INPUT("IN2_HPHR"), 2841 SND_SOC_DAPM_INPUT("IN3_AUX"), 2842 2843 /*rx widgets*/ 2844 SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0, 2845 wcd938x_codec_enable_ear_pa, 2846 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2847 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2848 SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0, 2849 wcd938x_codec_enable_aux_pa, 2850 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2851 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2852 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0, 2853 wcd938x_codec_enable_hphl_pa, 2854 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2855 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2856 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0, 2857 wcd938x_codec_enable_hphr_pa, 2858 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2859 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2860 2861 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 2862 wcd938x_codec_hphl_dac_event, 2863 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2864 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2865 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 2866 wcd938x_codec_hphr_dac_event, 2867 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2868 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2869 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 2870 wcd938x_codec_ear_dac_event, 2871 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2872 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2873 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0, 2874 wcd938x_codec_aux_dac_event, 2875 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2876 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2877 2878 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 2879 2880 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0), 2881 SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0, 2882 wcd938x_codec_enable_rxclk, 2883 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2884 SND_SOC_DAPM_POST_PMD), 2885 2886 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 2887 2888 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2889 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2890 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2891 2892 /* rx mixer widgets*/ 2893 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 2894 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 2895 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0, 2896 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)), 2897 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 2898 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 2899 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 2900 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 2901 2902 /*output widgets rx*/ 2903 SND_SOC_DAPM_OUTPUT("EAR"), 2904 SND_SOC_DAPM_OUTPUT("AUX"), 2905 SND_SOC_DAPM_OUTPUT("HPHL"), 2906 SND_SOC_DAPM_OUTPUT("HPHR"), 2907 2908 }; 2909 2910 static const struct snd_soc_dapm_route wcd938x_audio_map[] = { 2911 {"ADC1_OUTPUT", NULL, "ADC1_MIXER"}, 2912 {"ADC1_MIXER", "Switch", "ADC1 REQ"}, 2913 {"ADC1 REQ", NULL, "ADC1"}, 2914 {"ADC1", NULL, "AMIC1"}, 2915 2916 {"ADC2_OUTPUT", NULL, "ADC2_MIXER"}, 2917 {"ADC2_MIXER", "Switch", "ADC2 REQ"}, 2918 {"ADC2 REQ", NULL, "ADC2"}, 2919 {"ADC2", NULL, "HDR12 MUX"}, 2920 {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"}, 2921 {"HDR12 MUX", "HDR12", "AMIC1"}, 2922 {"ADC2 MUX", "INP3", "AMIC3"}, 2923 {"ADC2 MUX", "INP2", "AMIC2"}, 2924 2925 {"ADC3_OUTPUT", NULL, "ADC3_MIXER"}, 2926 {"ADC3_MIXER", "Switch", "ADC3 REQ"}, 2927 {"ADC3 REQ", NULL, "ADC3"}, 2928 {"ADC3", NULL, "HDR34 MUX"}, 2929 {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"}, 2930 {"HDR34 MUX", "HDR34", "AMIC5"}, 2931 {"ADC3 MUX", "INP4", "AMIC4"}, 2932 {"ADC3 MUX", "INP6", "AMIC6"}, 2933 2934 {"ADC4_OUTPUT", NULL, "ADC4_MIXER"}, 2935 {"ADC4_MIXER", "Switch", "ADC4 REQ"}, 2936 {"ADC4 REQ", NULL, "ADC4"}, 2937 {"ADC4", NULL, "ADC4 MUX"}, 2938 {"ADC4 MUX", "INP5", "AMIC5"}, 2939 {"ADC4 MUX", "INP7", "AMIC7"}, 2940 2941 {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"}, 2942 {"DMIC1_MIXER", "Switch", "DMIC1"}, 2943 2944 {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"}, 2945 {"DMIC2_MIXER", "Switch", "DMIC2"}, 2946 2947 {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"}, 2948 {"DMIC3_MIXER", "Switch", "DMIC3"}, 2949 2950 {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"}, 2951 {"DMIC4_MIXER", "Switch", "DMIC4"}, 2952 2953 {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"}, 2954 {"DMIC5_MIXER", "Switch", "DMIC5"}, 2955 2956 {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"}, 2957 {"DMIC6_MIXER", "Switch", "DMIC6"}, 2958 2959 {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"}, 2960 {"DMIC7_MIXER", "Switch", "DMIC7"}, 2961 2962 {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"}, 2963 {"DMIC8_MIXER", "Switch", "DMIC8"}, 2964 2965 {"IN1_HPHL", NULL, "VDD_BUCK"}, 2966 {"IN1_HPHL", NULL, "CLS_H_PORT"}, 2967 2968 {"RX1", NULL, "IN1_HPHL"}, 2969 {"RX1", NULL, "RXCLK"}, 2970 {"RDAC1", NULL, "RX1"}, 2971 {"HPHL_RDAC", "Switch", "RDAC1"}, 2972 {"HPHL PGA", NULL, "HPHL_RDAC"}, 2973 {"HPHL", NULL, "HPHL PGA"}, 2974 2975 {"IN2_HPHR", NULL, "VDD_BUCK"}, 2976 {"IN2_HPHR", NULL, "CLS_H_PORT"}, 2977 {"RX2", NULL, "IN2_HPHR"}, 2978 {"RDAC2", NULL, "RX2"}, 2979 {"RX2", NULL, "RXCLK"}, 2980 {"HPHR_RDAC", "Switch", "RDAC2"}, 2981 {"HPHR PGA", NULL, "HPHR_RDAC"}, 2982 {"HPHR", NULL, "HPHR PGA"}, 2983 2984 {"IN3_AUX", NULL, "VDD_BUCK"}, 2985 {"IN3_AUX", NULL, "CLS_H_PORT"}, 2986 {"RX3", NULL, "IN3_AUX"}, 2987 {"RDAC4", NULL, "RX3"}, 2988 {"RX3", NULL, "RXCLK"}, 2989 {"AUX_RDAC", "Switch", "RDAC4"}, 2990 {"AUX PGA", NULL, "AUX_RDAC"}, 2991 {"AUX", NULL, "AUX PGA"}, 2992 2993 {"RDAC3_MUX", "RX3", "RX3"}, 2994 {"RDAC3_MUX", "RX1", "RX1"}, 2995 {"RDAC3", NULL, "RDAC3_MUX"}, 2996 {"EAR_RDAC", "Switch", "RDAC3"}, 2997 {"EAR PGA", NULL, "EAR_RDAC"}, 2998 {"EAR", NULL, "EAR PGA"}, 2999 }; 3000 3001 static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x) 3002 { 3003 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4; 3004 3005 /* set micbias voltage */ 3006 vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb1_mv); 3007 vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb2_mv); 3008 vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb3_mv); 3009 vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb4_mv); 3010 if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0) 3011 return -EINVAL; 3012 3013 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 3014 WCD938X_MICB_VOUT_MASK, vout_ctl_1); 3015 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 3016 WCD938X_MICB_VOUT_MASK, vout_ctl_2); 3017 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 3018 WCD938X_MICB_VOUT_MASK, vout_ctl_3); 3019 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 3020 WCD938X_MICB_VOUT_MASK, vout_ctl_4); 3021 3022 return 0; 3023 } 3024 3025 static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data) 3026 { 3027 return IRQ_HANDLED; 3028 } 3029 3030 static const struct irq_chip wcd_irq_chip = { 3031 .name = "WCD938x", 3032 }; 3033 3034 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 3035 irq_hw_number_t hw) 3036 { 3037 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 3038 irq_set_nested_thread(virq, 1); 3039 irq_set_noprobe(virq); 3040 3041 return 0; 3042 } 3043 3044 static const struct irq_domain_ops wcd_domain_ops = { 3045 .map = wcd_irq_chip_map, 3046 }; 3047 3048 static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev) 3049 { 3050 3051 wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL); 3052 if (!(wcd->virq)) { 3053 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 3054 return -EINVAL; 3055 } 3056 3057 return devm_regmap_add_irq_chip(dev, wcd->regmap, 3058 irq_create_mapping(wcd->virq, 0), 3059 IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip, 3060 &wcd->irq_chip); 3061 } 3062 3063 static int wcd938x_soc_codec_probe(struct snd_soc_component *component) 3064 { 3065 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3066 struct sdw_slave *tx_sdw_dev = wcd938x->tx_sdw_dev; 3067 struct device *dev = component->dev; 3068 unsigned long time_left; 3069 int ret, i; 3070 3071 time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete, 3072 msecs_to_jiffies(2000)); 3073 if (!time_left) { 3074 dev_err(dev, "soundwire device init timeout\n"); 3075 return -ETIMEDOUT; 3076 } 3077 3078 snd_soc_component_init_regmap(component, wcd938x->regmap); 3079 3080 ret = pm_runtime_resume_and_get(dev); 3081 if (ret < 0) 3082 return ret; 3083 3084 wcd938x->variant = snd_soc_component_read_field(component, 3085 WCD938X_DIGITAL_EFUSE_REG_0, 3086 WCD938X_ID_MASK); 3087 3088 wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X); 3089 if (IS_ERR(wcd938x->clsh_info)) { 3090 pm_runtime_put(dev); 3091 return PTR_ERR(wcd938x->clsh_info); 3092 } 3093 3094 wcd938x_io_init(wcd938x); 3095 /* Set all interrupts as edge triggered */ 3096 for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) { 3097 regmap_write(wcd938x->regmap, 3098 (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0); 3099 } 3100 3101 pm_runtime_put(dev); 3102 3103 wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 3104 WCD938X_IRQ_HPHR_PDM_WD_INT); 3105 wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 3106 WCD938X_IRQ_HPHL_PDM_WD_INT); 3107 wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 3108 WCD938X_IRQ_AUX_PDM_WD_INT); 3109 3110 /* Request for watchdog interrupt */ 3111 ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3112 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3113 "HPHR PDM WD INT", wcd938x); 3114 if (ret) { 3115 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret); 3116 goto err_free_clsh_ctrl; 3117 } 3118 3119 ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3120 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3121 "HPHL PDM WD INT", wcd938x); 3122 if (ret) { 3123 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret); 3124 goto err_free_hphr_pdm_wd_int; 3125 } 3126 3127 ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3128 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3129 "AUX PDM WD INT", wcd938x); 3130 if (ret) { 3131 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret); 3132 goto err_free_hphl_pdm_wd_int; 3133 } 3134 3135 /* Disable watchdog interrupt for HPH and AUX */ 3136 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); 3137 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 3138 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 3139 3140 switch (wcd938x->variant) { 3141 case WCD9380: 3142 ret = snd_soc_add_component_controls(component, wcd9380_snd_controls, 3143 ARRAY_SIZE(wcd9380_snd_controls)); 3144 if (ret < 0) { 3145 dev_err(component->dev, 3146 "%s: Failed to add snd ctrls for variant: %d\n", 3147 __func__, wcd938x->variant); 3148 goto err_free_aux_pdm_wd_int; 3149 } 3150 break; 3151 case WCD9385: 3152 ret = snd_soc_add_component_controls(component, wcd9385_snd_controls, 3153 ARRAY_SIZE(wcd9385_snd_controls)); 3154 if (ret < 0) { 3155 dev_err(component->dev, 3156 "%s: Failed to add snd ctrls for variant: %d\n", 3157 __func__, wcd938x->variant); 3158 goto err_free_aux_pdm_wd_int; 3159 } 3160 break; 3161 default: 3162 break; 3163 } 3164 3165 ret = wcd938x_mbhc_init(component); 3166 if (ret) { 3167 dev_err(component->dev, "mbhc initialization failed\n"); 3168 goto err_free_aux_pdm_wd_int; 3169 } 3170 3171 return 0; 3172 3173 err_free_aux_pdm_wd_int: 3174 free_irq(wcd938x->aux_pdm_wd_int, wcd938x); 3175 err_free_hphl_pdm_wd_int: 3176 free_irq(wcd938x->hphl_pdm_wd_int, wcd938x); 3177 err_free_hphr_pdm_wd_int: 3178 free_irq(wcd938x->hphr_pdm_wd_int, wcd938x); 3179 err_free_clsh_ctrl: 3180 wcd_clsh_ctrl_free(wcd938x->clsh_info); 3181 3182 return ret; 3183 } 3184 3185 static void wcd938x_soc_codec_remove(struct snd_soc_component *component) 3186 { 3187 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3188 3189 wcd938x_mbhc_deinit(component); 3190 3191 free_irq(wcd938x->aux_pdm_wd_int, wcd938x); 3192 free_irq(wcd938x->hphl_pdm_wd_int, wcd938x); 3193 free_irq(wcd938x->hphr_pdm_wd_int, wcd938x); 3194 3195 wcd_clsh_ctrl_free(wcd938x->clsh_info); 3196 } 3197 3198 static int wcd938x_codec_set_jack(struct snd_soc_component *comp, 3199 struct snd_soc_jack *jack, void *data) 3200 { 3201 struct wcd938x_priv *wcd = dev_get_drvdata(comp->dev); 3202 3203 if (jack) 3204 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 3205 else 3206 wcd_mbhc_stop(wcd->wcd_mbhc); 3207 3208 return 0; 3209 } 3210 3211 static const struct snd_soc_component_driver soc_codec_dev_wcd938x = { 3212 .name = "wcd938x_codec", 3213 .probe = wcd938x_soc_codec_probe, 3214 .remove = wcd938x_soc_codec_remove, 3215 .controls = wcd938x_snd_controls, 3216 .num_controls = ARRAY_SIZE(wcd938x_snd_controls), 3217 .dapm_widgets = wcd938x_dapm_widgets, 3218 .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets), 3219 .dapm_routes = wcd938x_audio_map, 3220 .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map), 3221 .set_jack = wcd938x_codec_set_jack, 3222 .endianness = 1, 3223 }; 3224 3225 static void wcd938x_dt_parse_micbias_info(struct device *dev, struct wcd938x_priv *wcd) 3226 { 3227 struct device_node *np = dev->of_node; 3228 u32 prop_val = 0; 3229 int rc = 0; 3230 3231 rc = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val); 3232 if (!rc) 3233 wcd->micb1_mv = prop_val/1000; 3234 else 3235 dev_info(dev, "%s: Micbias1 DT property not found\n", __func__); 3236 3237 rc = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val); 3238 if (!rc) 3239 wcd->micb2_mv = prop_val/1000; 3240 else 3241 dev_info(dev, "%s: Micbias2 DT property not found\n", __func__); 3242 3243 rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val); 3244 if (!rc) 3245 wcd->micb3_mv = prop_val/1000; 3246 else 3247 dev_info(dev, "%s: Micbias3 DT property not found\n", __func__); 3248 3249 rc = of_property_read_u32(np, "qcom,micbias4-microvolt", &prop_val); 3250 if (!rc) 3251 wcd->micb4_mv = prop_val/1000; 3252 else 3253 dev_info(dev, "%s: Micbias4 DT property not found\n", __func__); 3254 } 3255 3256 static bool wcd938x_swap_gnd_mic(struct snd_soc_component *component, bool active) 3257 { 3258 int value; 3259 3260 struct wcd938x_priv *wcd938x; 3261 3262 wcd938x = snd_soc_component_get_drvdata(component); 3263 3264 value = gpiod_get_value(wcd938x->us_euro_gpio); 3265 3266 gpiod_set_value(wcd938x->us_euro_gpio, !value); 3267 3268 return true; 3269 } 3270 3271 3272 static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev) 3273 { 3274 struct wcd_mbhc_config *cfg = &wcd938x->mbhc_cfg; 3275 int ret; 3276 3277 wcd938x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0); 3278 if (wcd938x->reset_gpio < 0) 3279 return dev_err_probe(dev, wcd938x->reset_gpio, 3280 "Failed to get reset gpio\n"); 3281 3282 wcd938x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", 3283 GPIOD_OUT_LOW); 3284 if (IS_ERR(wcd938x->us_euro_gpio)) 3285 return dev_err_probe(dev, PTR_ERR(wcd938x->us_euro_gpio), 3286 "us-euro swap Control GPIO not found\n"); 3287 3288 cfg->swap_gnd_mic = wcd938x_swap_gnd_mic; 3289 3290 wcd938x->supplies[0].supply = "vdd-rxtx"; 3291 wcd938x->supplies[1].supply = "vdd-io"; 3292 wcd938x->supplies[2].supply = "vdd-buck"; 3293 wcd938x->supplies[3].supply = "vdd-mic-bias"; 3294 3295 ret = regulator_bulk_get(dev, WCD938X_MAX_SUPPLY, wcd938x->supplies); 3296 if (ret) 3297 return dev_err_probe(dev, ret, "Failed to get supplies\n"); 3298 3299 ret = regulator_bulk_enable(WCD938X_MAX_SUPPLY, wcd938x->supplies); 3300 if (ret) { 3301 regulator_bulk_free(WCD938X_MAX_SUPPLY, wcd938x->supplies); 3302 return dev_err_probe(dev, ret, "Failed to enable supplies\n"); 3303 } 3304 3305 wcd938x_dt_parse_micbias_info(dev, wcd938x); 3306 3307 cfg->mbhc_micbias = MIC_BIAS_2; 3308 cfg->anc_micbias = MIC_BIAS_2; 3309 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 3310 cfg->num_btn = WCD938X_MBHC_MAX_BUTTONS; 3311 cfg->micb_mv = wcd938x->micb2_mv; 3312 cfg->linein_th = 5000; 3313 cfg->hs_thr = 1700; 3314 cfg->hph_thr = 50; 3315 3316 wcd_dt_parse_mbhc_data(dev, cfg); 3317 3318 return 0; 3319 } 3320 3321 static int wcd938x_reset(struct wcd938x_priv *wcd938x) 3322 { 3323 gpio_direction_output(wcd938x->reset_gpio, 0); 3324 /* 20us sleep required after pulling the reset gpio to LOW */ 3325 usleep_range(20, 30); 3326 gpio_set_value(wcd938x->reset_gpio, 1); 3327 /* 20us sleep required after pulling the reset gpio to HIGH */ 3328 usleep_range(20, 30); 3329 3330 return 0; 3331 } 3332 3333 static int wcd938x_codec_hw_params(struct snd_pcm_substream *substream, 3334 struct snd_pcm_hw_params *params, 3335 struct snd_soc_dai *dai) 3336 { 3337 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 3338 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 3339 3340 return wcd938x_sdw_hw_params(wcd, substream, params, dai); 3341 } 3342 3343 static int wcd938x_codec_free(struct snd_pcm_substream *substream, 3344 struct snd_soc_dai *dai) 3345 { 3346 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 3347 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 3348 3349 return wcd938x_sdw_free(wcd, substream, dai); 3350 } 3351 3352 static int wcd938x_codec_set_sdw_stream(struct snd_soc_dai *dai, 3353 void *stream, int direction) 3354 { 3355 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 3356 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 3357 3358 return wcd938x_sdw_set_sdw_stream(wcd, dai, stream, direction); 3359 3360 } 3361 3362 static const struct snd_soc_dai_ops wcd938x_sdw_dai_ops = { 3363 .hw_params = wcd938x_codec_hw_params, 3364 .hw_free = wcd938x_codec_free, 3365 .set_stream = wcd938x_codec_set_sdw_stream, 3366 }; 3367 3368 static struct snd_soc_dai_driver wcd938x_dais[] = { 3369 [AIF1_PB] = { 3370 .name = "wcd938x-sdw-rx", 3371 .playback = { 3372 .stream_name = "WCD AIF1 Playback", 3373 .rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK, 3374 .formats = WCD938X_FORMATS_S16_S24_LE, 3375 .rate_max = 192000, 3376 .rate_min = 8000, 3377 .channels_min = 1, 3378 .channels_max = 2, 3379 }, 3380 .ops = &wcd938x_sdw_dai_ops, 3381 }, 3382 [AIF1_CAP] = { 3383 .name = "wcd938x-sdw-tx", 3384 .capture = { 3385 .stream_name = "WCD AIF1 Capture", 3386 .rates = WCD938X_RATES_MASK, 3387 .formats = SNDRV_PCM_FMTBIT_S16_LE, 3388 .rate_min = 8000, 3389 .rate_max = 192000, 3390 .channels_min = 1, 3391 .channels_max = 4, 3392 }, 3393 .ops = &wcd938x_sdw_dai_ops, 3394 }, 3395 }; 3396 3397 static int wcd938x_bind(struct device *dev) 3398 { 3399 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 3400 int ret; 3401 3402 ret = component_bind_all(dev, wcd938x); 3403 if (ret) { 3404 dev_err(dev, "%s: Slave bind failed, ret = %d\n", 3405 __func__, ret); 3406 return ret; 3407 } 3408 3409 wcd938x->rxdev = wcd938x_sdw_device_get(wcd938x->rxnode); 3410 if (!wcd938x->rxdev) { 3411 dev_err(dev, "could not find slave with matching of node\n"); 3412 ret = -EINVAL; 3413 goto err_unbind; 3414 } 3415 wcd938x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd938x->rxdev); 3416 wcd938x->sdw_priv[AIF1_PB]->wcd938x = wcd938x; 3417 3418 wcd938x->txdev = wcd938x_sdw_device_get(wcd938x->txnode); 3419 if (!wcd938x->txdev) { 3420 dev_err(dev, "could not find txslave with matching of node\n"); 3421 ret = -EINVAL; 3422 goto err_put_rxdev; 3423 } 3424 wcd938x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd938x->txdev); 3425 wcd938x->sdw_priv[AIF1_CAP]->wcd938x = wcd938x; 3426 wcd938x->tx_sdw_dev = dev_to_sdw_dev(wcd938x->txdev); 3427 3428 /* As TX is main CSR reg interface, which should not be suspended first. 3429 * expicilty add the dependency link */ 3430 if (!device_link_add(wcd938x->rxdev, wcd938x->txdev, DL_FLAG_STATELESS | 3431 DL_FLAG_PM_RUNTIME)) { 3432 dev_err(dev, "could not devlink tx and rx\n"); 3433 ret = -EINVAL; 3434 goto err_put_txdev; 3435 } 3436 3437 if (!device_link_add(dev, wcd938x->txdev, DL_FLAG_STATELESS | 3438 DL_FLAG_PM_RUNTIME)) { 3439 dev_err(dev, "could not devlink wcd and tx\n"); 3440 ret = -EINVAL; 3441 goto err_remove_rxtx_link; 3442 } 3443 3444 if (!device_link_add(dev, wcd938x->rxdev, DL_FLAG_STATELESS | 3445 DL_FLAG_PM_RUNTIME)) { 3446 dev_err(dev, "could not devlink wcd and rx\n"); 3447 ret = -EINVAL; 3448 goto err_remove_tx_link; 3449 } 3450 3451 wcd938x->regmap = dev_get_regmap(&wcd938x->tx_sdw_dev->dev, NULL); 3452 if (!wcd938x->regmap) { 3453 dev_err(dev, "could not get TX device regmap\n"); 3454 ret = -EINVAL; 3455 goto err_remove_rx_link; 3456 } 3457 3458 ret = wcd938x_irq_init(wcd938x, dev); 3459 if (ret) { 3460 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret); 3461 goto err_remove_rx_link; 3462 } 3463 3464 wcd938x->sdw_priv[AIF1_PB]->slave_irq = wcd938x->virq; 3465 wcd938x->sdw_priv[AIF1_CAP]->slave_irq = wcd938x->virq; 3466 3467 ret = wcd938x_set_micbias_data(wcd938x); 3468 if (ret < 0) { 3469 dev_err(dev, "%s: bad micbias pdata\n", __func__); 3470 goto err_remove_rx_link; 3471 } 3472 3473 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x, 3474 wcd938x_dais, ARRAY_SIZE(wcd938x_dais)); 3475 if (ret) { 3476 dev_err(dev, "%s: Codec registration failed\n", 3477 __func__); 3478 goto err_remove_rx_link; 3479 } 3480 3481 return 0; 3482 3483 err_remove_rx_link: 3484 device_link_remove(dev, wcd938x->rxdev); 3485 err_remove_tx_link: 3486 device_link_remove(dev, wcd938x->txdev); 3487 err_remove_rxtx_link: 3488 device_link_remove(wcd938x->rxdev, wcd938x->txdev); 3489 err_put_txdev: 3490 put_device(wcd938x->txdev); 3491 err_put_rxdev: 3492 put_device(wcd938x->rxdev); 3493 err_unbind: 3494 component_unbind_all(dev, wcd938x); 3495 3496 return ret; 3497 } 3498 3499 static void wcd938x_unbind(struct device *dev) 3500 { 3501 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 3502 3503 snd_soc_unregister_component(dev); 3504 device_link_remove(dev, wcd938x->txdev); 3505 device_link_remove(dev, wcd938x->rxdev); 3506 device_link_remove(wcd938x->rxdev, wcd938x->txdev); 3507 put_device(wcd938x->txdev); 3508 put_device(wcd938x->rxdev); 3509 component_unbind_all(dev, wcd938x); 3510 } 3511 3512 static const struct component_master_ops wcd938x_comp_ops = { 3513 .bind = wcd938x_bind, 3514 .unbind = wcd938x_unbind, 3515 }; 3516 3517 static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x, 3518 struct device *dev, 3519 struct component_match **matchptr) 3520 { 3521 struct device_node *np; 3522 3523 np = dev->of_node; 3524 3525 wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 3526 if (!wcd938x->rxnode) { 3527 dev_err(dev, "%s: Rx-device node not defined\n", __func__); 3528 return -ENODEV; 3529 } 3530 3531 of_node_get(wcd938x->rxnode); 3532 component_match_add_release(dev, matchptr, component_release_of, 3533 component_compare_of, wcd938x->rxnode); 3534 3535 wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 3536 if (!wcd938x->txnode) { 3537 dev_err(dev, "%s: Tx-device node not defined\n", __func__); 3538 return -ENODEV; 3539 } 3540 of_node_get(wcd938x->txnode); 3541 component_match_add_release(dev, matchptr, component_release_of, 3542 component_compare_of, wcd938x->txnode); 3543 return 0; 3544 } 3545 3546 static int wcd938x_probe(struct platform_device *pdev) 3547 { 3548 struct component_match *match = NULL; 3549 struct wcd938x_priv *wcd938x = NULL; 3550 struct device *dev = &pdev->dev; 3551 int ret; 3552 3553 wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv), 3554 GFP_KERNEL); 3555 if (!wcd938x) 3556 return -ENOMEM; 3557 3558 dev_set_drvdata(dev, wcd938x); 3559 mutex_init(&wcd938x->micb_lock); 3560 3561 ret = wcd938x_populate_dt_data(wcd938x, dev); 3562 if (ret) 3563 return ret; 3564 3565 ret = wcd938x_add_slave_components(wcd938x, dev, &match); 3566 if (ret) 3567 goto err_disable_regulators; 3568 3569 wcd938x_reset(wcd938x); 3570 3571 ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match); 3572 if (ret) 3573 goto err_disable_regulators; 3574 3575 pm_runtime_set_autosuspend_delay(dev, 1000); 3576 pm_runtime_use_autosuspend(dev); 3577 pm_runtime_mark_last_busy(dev); 3578 pm_runtime_set_active(dev); 3579 pm_runtime_enable(dev); 3580 pm_runtime_idle(dev); 3581 3582 return 0; 3583 3584 err_disable_regulators: 3585 regulator_bulk_disable(WCD938X_MAX_SUPPLY, wcd938x->supplies); 3586 regulator_bulk_free(WCD938X_MAX_SUPPLY, wcd938x->supplies); 3587 3588 return ret; 3589 } 3590 3591 static void wcd938x_remove(struct platform_device *pdev) 3592 { 3593 struct device *dev = &pdev->dev; 3594 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 3595 3596 component_master_del(dev, &wcd938x_comp_ops); 3597 3598 pm_runtime_disable(dev); 3599 pm_runtime_set_suspended(dev); 3600 pm_runtime_dont_use_autosuspend(dev); 3601 3602 regulator_bulk_disable(WCD938X_MAX_SUPPLY, wcd938x->supplies); 3603 regulator_bulk_free(WCD938X_MAX_SUPPLY, wcd938x->supplies); 3604 } 3605 3606 #if defined(CONFIG_OF) 3607 static const struct of_device_id wcd938x_dt_match[] = { 3608 { .compatible = "qcom,wcd9380-codec" }, 3609 { .compatible = "qcom,wcd9385-codec" }, 3610 {} 3611 }; 3612 MODULE_DEVICE_TABLE(of, wcd938x_dt_match); 3613 #endif 3614 3615 static struct platform_driver wcd938x_codec_driver = { 3616 .probe = wcd938x_probe, 3617 .remove_new = wcd938x_remove, 3618 .driver = { 3619 .name = "wcd938x_codec", 3620 .of_match_table = of_match_ptr(wcd938x_dt_match), 3621 .suppress_bind_attrs = true, 3622 }, 3623 }; 3624 3625 module_platform_driver(wcd938x_codec_driver); 3626 MODULE_DESCRIPTION("WCD938X Codec driver"); 3627 MODULE_LICENSE("GPL"); 3628