1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 7 #ifndef AIROHA_ETH_H 8 #define AIROHA_ETH_H 9 10 #include <linux/debugfs.h> 11 #include <linux/etherdevice.h> 12 #include <linux/iopoll.h> 13 #include <linux/kernel.h> 14 #include <linux/netdevice.h> 15 #include <linux/reset.h> 16 #include <linux/soc/airoha/airoha_offload.h> 17 #include <net/dsa.h> 18 19 #define AIROHA_MAX_NUM_GDM_PORTS 4 20 #define AIROHA_MAX_NUM_GDM_DEVS 2 21 #define AIROHA_MAX_NUM_QDMA 2 22 #define AIROHA_MAX_NUM_IRQ_BANKS 4 23 #define AIROHA_MAX_DSA_PORTS 7 24 #define AIROHA_MAX_NUM_RSTS 3 25 #define AIROHA_MAX_MTU 9220 26 #define AIROHA_MAX_RX_SIZE 16128 27 #define AIROHA_MAX_PACKET_SIZE 2048 28 #define AIROHA_NUM_QOS_CHANNELS 4 29 #define AIROHA_NUM_QOS_QUEUES 8 30 #define AIROHA_NUM_TX_RING 32 31 #define AIROHA_NUM_RX_RING 32 32 #define AIROHA_NUM_NETDEV_TX_RINGS (AIROHA_NUM_TX_RING + \ 33 AIROHA_NUM_QOS_CHANNELS) 34 #define AIROHA_FE_MC_MAX_VLAN_TABLE 64 35 #define AIROHA_FE_MC_MAX_VLAN_PORT 16 36 #define AIROHA_NUM_TX_IRQ 2 37 #define AIROHA_RX_HEADROOM (NET_SKB_PAD + NET_IP_ALIGN) 38 #define AIROHA_RX_LEN(_n) ((_n) - AIROHA_RX_HEADROOM) 39 #define HW_DSCP_NUM 2048 40 #define IRQ_QUEUE_LEN(_n) ((_n) ? 1024 : 2048) 41 #define TX_DSCP_NUM 1024 42 #define RX_DSCP_NUM(_n) \ 43 ((_n) == 2 ? 128 : \ 44 (_n) == 11 ? 128 : \ 45 (_n) == 15 ? 128 : \ 46 (_n) == 0 ? 1024 : 16) 47 48 #define PSE_RSV_PAGES 128 49 #define PSE_QUEUE_RSV_PAGES 64 50 51 #define QDMA_METER_IDX(_n) ((_n) & 0xff) 52 #define QDMA_METER_GROUP(_n) (((_n) >> 8) & 0x3) 53 54 #define PPE_SRAM_NUM_ENTRIES (8 * 1024) 55 #define PPE_STATS_NUM_ENTRIES (4 * 1024) 56 #define PPE_DRAM_NUM_ENTRIES (16 * 1024) 57 #define PPE_ENTRY_SIZE 80 58 #define PPE_RAM_NUM_ENTRIES_SHIFT(_n) (__ffs((_n) >> 10)) 59 60 #define MTK_HDR_LEN 4 61 #define MTK_HDR_XMIT_TAGGED_TPID_8100 1 62 #define MTK_HDR_XMIT_TAGGED_TPID_88A8 2 63 64 enum { 65 QDMA_INT_REG_IDX0, 66 QDMA_INT_REG_IDX1, 67 QDMA_INT_REG_IDX2, 68 QDMA_INT_REG_IDX3, 69 QDMA_INT_REG_IDX4, 70 QDMA_INT_REG_MAX 71 }; 72 73 enum { 74 HSGMII_LAN_7581_PCIE0_SRCPORT = 0x16, 75 HSGMII_LAN_7581_PCIE1_SRCPORT, 76 HSGMII_LAN_7581_ETH_SRCPORT, 77 HSGMII_LAN_7581_USB_SRCPORT, 78 }; 79 80 enum { 81 HSGMII_LAN_7583_ETH_SRCPORT = 0x16, 82 HSGMII_LAN_7583_PCIE_SRCPORT = 0x18, 83 HSGMII_LAN_7583_USB_SRCPORT, 84 }; 85 86 enum { 87 XSI_PCIE0_VIP_PORT_MASK = BIT(22), 88 XSI_PCIE1_VIP_PORT_MASK = BIT(23), 89 XSI_USB_VIP_PORT_MASK = BIT(25), 90 XSI_ETH_VIP_PORT_MASK = BIT(24), 91 }; 92 93 enum { 94 DEV_STATE_INITIALIZED, 95 DEV_STATE_REGISTERED, 96 }; 97 98 enum { 99 CDM_CRSN_QSEL_Q1 = 1, 100 CDM_CRSN_QSEL_Q5 = 5, 101 CDM_CRSN_QSEL_Q6 = 6, 102 CDM_CRSN_QSEL_Q15 = 15, 103 }; 104 105 enum { 106 CRSN_08 = 0x8, 107 CRSN_21 = 0x15, /* KA */ 108 CRSN_22 = 0x16, /* hit bind and force route to CPU */ 109 CRSN_24 = 0x18, 110 CRSN_25 = 0x19, 111 }; 112 113 enum airoha_gdm_index { 114 AIROHA_GDM1_IDX = 1, 115 AIROHA_GDM2_IDX = 2, 116 AIROHA_GDM3_IDX = 3, 117 AIROHA_GDM4_IDX = 4, 118 }; 119 120 enum { 121 FE_PSE_PORT_CDM1, 122 FE_PSE_PORT_GDM1, 123 FE_PSE_PORT_GDM2, 124 FE_PSE_PORT_GDM3, 125 FE_PSE_PORT_PPE1, 126 FE_PSE_PORT_CDM2, 127 FE_PSE_PORT_CDM3, 128 FE_PSE_PORT_CDM4, 129 FE_PSE_PORT_PPE2, 130 FE_PSE_PORT_GDM4, 131 FE_PSE_PORT_CDM5, 132 FE_PSE_PORT_DROP = 0xf, 133 }; 134 135 enum tx_sched_mode { 136 TC_SCH_WRR8, 137 TC_SCH_SP, 138 TC_SCH_WRR7, 139 TC_SCH_WRR6, 140 TC_SCH_WRR5, 141 TC_SCH_WRR4, 142 TC_SCH_WRR3, 143 TC_SCH_WRR2, 144 }; 145 146 enum trtcm_unit_type { 147 TRTCM_BYTE_UNIT, 148 TRTCM_PACKET_UNIT, 149 }; 150 151 enum trtcm_param_type { 152 TRTCM_MISC_MODE, /* meter_en, pps_mode, tick_sel */ 153 TRTCM_TOKEN_RATE_MODE, 154 TRTCM_BUCKETSIZE_SHIFT_MODE, 155 TRTCM_BUCKET_COUNTER_MODE, 156 }; 157 158 enum trtcm_mode_type { 159 TRTCM_COMMIT_MODE, 160 TRTCM_PEAK_MODE, 161 }; 162 163 enum trtcm_param { 164 TRTCM_TICK_SEL = BIT(0), 165 TRTCM_PKT_MODE = BIT(1), 166 TRTCM_METER_MODE = BIT(2), 167 }; 168 169 #define MIN_TOKEN_SIZE 4096 170 #define MAX_TOKEN_SIZE_OFFSET 17 171 #define TRTCM_TOKEN_RATE_MASK GENMASK(23, 6) 172 #define TRTCM_TOKEN_RATE_FRACTION_MASK GENMASK(5, 0) 173 174 enum airoha_dma_map_type { 175 AIROHA_DMA_UNMAPPED, 176 AIROHA_DMA_MAP_SINGLE, 177 AIROHA_DMA_MAP_PAGE, 178 }; 179 180 struct airoha_queue_entry { 181 union { 182 void *buf; 183 struct { 184 struct list_head list; 185 struct sk_buff *skb; 186 enum airoha_dma_map_type dma_type; 187 }; 188 }; 189 dma_addr_t dma_addr; 190 u16 dma_len; 191 }; 192 193 struct airoha_queue { 194 struct airoha_qdma *qdma; 195 196 /* protect concurrent queue accesses */ 197 spinlock_t lock; 198 struct airoha_queue_entry *entry; 199 struct airoha_qdma_desc *desc; 200 u16 head; 201 u16 tail; 202 203 int queued; 204 int ndesc; 205 int free_thr; 206 int buf_size; 207 bool txq_stopped; 208 bool flushing; 209 210 struct napi_struct napi; 211 struct page_pool *page_pool; 212 struct sk_buff *skb; 213 214 struct list_head tx_list; 215 }; 216 217 struct airoha_tx_irq_queue { 218 struct airoha_qdma *qdma; 219 220 struct napi_struct napi; 221 222 int size; 223 u32 *q; 224 }; 225 226 struct airoha_hw_stats { 227 struct u64_stats_sync syncp; 228 229 /* get_stats64 */ 230 u64 rx_ok_pkts; 231 u64 tx_ok_pkts; 232 u64 rx_ok_bytes; 233 u64 tx_ok_bytes; 234 u64 rx_multicast; 235 u64 rx_errors; 236 u64 rx_drops; 237 u64 tx_drops; 238 u64 rx_crc_error; 239 u64 rx_over_errors; 240 /* ethtool stats */ 241 u64 tx_broadcast; 242 u64 tx_multicast; 243 u64 tx_len[7]; 244 u64 rx_broadcast; 245 u64 rx_fragment; 246 u64 rx_jabber; 247 u64 rx_len[7]; 248 249 struct { 250 /* Previous HW register values for 32-bit counter delta 251 * tracking. Storing the last seen value and accumulating 252 * (u32)(curr - prev) into the 64-bit software counter 253 * handles wrap-around transparently via unsigned arithmetic. 254 * tx_runt64/rx_runt64 hold the running sum of runt deltas. 255 * These fields are never reported to userspace. 256 */ 257 u32 tx_drops; 258 u32 tx_broadcast; 259 u32 tx_multicast; 260 u32 tx_runt; 261 u32 tx_long; 262 u64 tx_runt64; 263 u32 rx_drops; 264 u32 rx_broadcast; 265 u32 rx_multicast; 266 u32 rx_errors; 267 u32 rx_crc_error; 268 u32 rx_over_errors; 269 u32 rx_fragment; 270 u32 rx_jabber; 271 u32 rx_runt; 272 u32 rx_long; 273 u64 rx_runt64; 274 } mib_prev; 275 }; 276 277 enum { 278 AIROHA_FOE_STATE_INVALID, 279 AIROHA_FOE_STATE_UNBIND, 280 AIROHA_FOE_STATE_BIND, 281 AIROHA_FOE_STATE_FIN 282 }; 283 284 enum { 285 PPE_PKT_TYPE_IPV4_HNAPT = 0, 286 PPE_PKT_TYPE_IPV4_ROUTE = 1, 287 PPE_PKT_TYPE_BRIDGE = 2, 288 PPE_PKT_TYPE_IPV4_DSLITE = 3, 289 PPE_PKT_TYPE_IPV6_ROUTE_3T = 4, 290 PPE_PKT_TYPE_IPV6_ROUTE_5T = 5, 291 PPE_PKT_TYPE_IPV6_6RD = 7, 292 }; 293 294 #define AIROHA_FOE_MAC_SMAC_ID GENMASK(20, 16) 295 #define AIROHA_FOE_MAC_PPPOE_ID GENMASK(15, 0) 296 297 #define AIROHA_FOE_MAC_WDMA_QOS GENMASK(15, 12) 298 #define AIROHA_FOE_MAC_WDMA_BAND BIT(11) 299 #define AIROHA_FOE_MAC_WDMA_WCID GENMASK(10, 0) 300 301 struct airoha_foe_mac_info_common { 302 u16 vlan1; 303 u16 etype; 304 305 u32 dest_mac_hi; 306 307 u16 vlan2; 308 u16 dest_mac_lo; 309 310 u32 src_mac_hi; 311 }; 312 313 struct airoha_foe_mac_info { 314 struct airoha_foe_mac_info_common common; 315 316 u16 pppoe_id; 317 u16 src_mac_lo; 318 319 u32 meter; 320 }; 321 322 #define AIROHA_FOE_IB1_UNBIND_PREBIND BIT(24) 323 #define AIROHA_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8) 324 #define AIROHA_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0) 325 326 #define AIROHA_FOE_IB1_BIND_STATIC BIT(31) 327 #define AIROHA_FOE_IB1_BIND_UDP BIT(30) 328 #define AIROHA_FOE_IB1_BIND_STATE GENMASK(29, 28) 329 #define AIROHA_FOE_IB1_BIND_PACKET_TYPE GENMASK(27, 25) 330 #define AIROHA_FOE_IB1_BIND_TTL BIT(24) 331 #define AIROHA_FOE_IB1_BIND_TUNNEL_DECAP BIT(23) 332 #define AIROHA_FOE_IB1_BIND_PPPOE BIT(22) 333 #define AIROHA_FOE_IB1_BIND_VPM GENMASK(21, 20) 334 #define AIROHA_FOE_IB1_BIND_VLAN_LAYER GENMASK(19, 16) 335 #define AIROHA_FOE_IB1_BIND_KEEPALIVE BIT(15) 336 #define AIROHA_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0) 337 338 #define AIROHA_FOE_IB2_DSCP GENMASK(31, 24) 339 #define AIROHA_FOE_IB2_PORT_AG GENMASK(23, 13) 340 #define AIROHA_FOE_IB2_PCP BIT(12) 341 #define AIROHA_FOE_IB2_MULTICAST BIT(11) 342 #define AIROHA_FOE_IB2_FAST_PATH BIT(10) 343 #define AIROHA_FOE_IB2_PSE_QOS BIT(9) 344 #define AIROHA_FOE_IB2_PSE_PORT GENMASK(8, 5) 345 #define AIROHA_FOE_IB2_NBQ GENMASK(4, 0) 346 347 #define AIROHA_FOE_ACTDP GENMASK(31, 24) 348 #define AIROHA_FOE_SHAPER_ID GENMASK(23, 16) 349 #define AIROHA_FOE_CHANNEL GENMASK(15, 11) 350 #define AIROHA_FOE_QID GENMASK(10, 8) 351 #define AIROHA_FOE_DPI BIT(7) 352 #define AIROHA_FOE_TUNNEL BIT(6) 353 #define AIROHA_FOE_TUNNEL_ID GENMASK(5, 0) 354 355 #define AIROHA_FOE_TUNNEL_MTU GENMASK(31, 16) 356 #define AIROHA_FOE_ACNT_GRP3 GENMASK(15, 9) 357 #define AIROHA_FOE_METER_GRP3 GENMASK(8, 5) 358 #define AIROHA_FOE_METER_GRP2 GENMASK(4, 0) 359 360 struct airoha_foe_bridge { 361 u32 dest_mac_hi; 362 363 u16 src_mac_hi; 364 u16 dest_mac_lo; 365 366 u32 src_mac_lo; 367 368 u32 ib2; 369 370 u32 rsv[5]; 371 372 u32 data; 373 374 struct airoha_foe_mac_info l2; 375 }; 376 377 struct airoha_foe_ipv4_tuple { 378 u32 src_ip; 379 u32 dest_ip; 380 union { 381 struct { 382 u16 dest_port; 383 u16 src_port; 384 }; 385 struct { 386 u8 protocol; 387 u8 _pad[3]; /* fill with 0xa5a5a5 */ 388 }; 389 u32 ports; 390 }; 391 }; 392 393 struct airoha_foe_ipv4 { 394 struct airoha_foe_ipv4_tuple orig_tuple; 395 396 u32 ib2; 397 398 struct airoha_foe_ipv4_tuple new_tuple; 399 400 u32 rsv[2]; 401 402 u32 data; 403 404 struct airoha_foe_mac_info l2; 405 }; 406 407 struct airoha_foe_ipv4_dslite { 408 struct airoha_foe_ipv4_tuple ip4; 409 410 u32 ib2; 411 412 u8 flow_label[3]; 413 u8 priority; 414 415 u32 rsv[4]; 416 417 u32 data; 418 419 struct airoha_foe_mac_info l2; 420 }; 421 422 struct airoha_foe_ipv6 { 423 u32 src_ip[4]; 424 u32 dest_ip[4]; 425 426 union { 427 struct { 428 u16 dest_port; 429 u16 src_port; 430 }; 431 struct { 432 u8 protocol; 433 u8 pad[3]; 434 }; 435 u32 ports; 436 }; 437 438 u32 data; 439 440 u32 ib2; 441 442 struct airoha_foe_mac_info_common l2; 443 444 u32 meter; 445 }; 446 447 struct airoha_foe_entry { 448 union { 449 struct { 450 u32 ib1; 451 union { 452 struct airoha_foe_bridge bridge; 453 struct airoha_foe_ipv4 ipv4; 454 struct airoha_foe_ipv4_dslite dslite; 455 struct airoha_foe_ipv6 ipv6; 456 DECLARE_FLEX_ARRAY(u32, d); 457 }; 458 }; 459 u8 data[PPE_ENTRY_SIZE]; 460 }; 461 }; 462 463 struct airoha_foe_stats { 464 u32 bytes; 465 u32 packets; 466 }; 467 468 struct airoha_foe_stats64 { 469 u64 bytes; 470 u64 packets; 471 }; 472 473 struct airoha_flow_data { 474 struct ethhdr eth; 475 476 union { 477 struct { 478 __be32 src_addr; 479 __be32 dst_addr; 480 } v4; 481 482 struct { 483 struct in6_addr src_addr; 484 struct in6_addr dst_addr; 485 } v6; 486 }; 487 488 __be16 src_port; 489 __be16 dst_port; 490 491 struct { 492 struct { 493 u16 id; 494 __be16 proto; 495 } hdr[2]; 496 u8 num; 497 } vlan; 498 struct { 499 u16 sid; 500 u8 num; 501 } pppoe; 502 }; 503 504 enum airoha_flow_entry_type { 505 FLOW_TYPE_L4, 506 FLOW_TYPE_L2, 507 FLOW_TYPE_L2_SUBFLOW, 508 }; 509 510 struct airoha_flow_table_entry { 511 union { 512 struct hlist_node list; /* PPE L3 flow entry */ 513 struct { 514 struct rhash_head l2_node; /* L2 flow entry */ 515 struct hlist_head l2_flows; /* PPE L2 subflows list */ 516 }; 517 }; 518 519 struct hlist_node l2_subflow_node; /* PPE L2 subflow entry */ 520 u32 hash; 521 522 struct airoha_foe_stats64 stats; 523 enum airoha_flow_entry_type type; 524 525 struct rhash_head node; 526 unsigned long cookie; 527 528 /* Must be last --ends in a flexible-array member. */ 529 struct airoha_foe_entry data; 530 }; 531 532 struct airoha_wdma_info { 533 u8 idx; 534 u8 queue; 535 u16 wcid; 536 u8 bss; 537 }; 538 539 /* RX queue to IRQ mapping: BIT(q) in IRQ(n) */ 540 #define RX_IRQ0_BANK_PIN_MASK 0x839f 541 #define RX_IRQ1_BANK_PIN_MASK 0xffe00000 542 #define RX_IRQ2_BANK_PIN_MASK 0x20 543 #define RX_IRQ3_BANK_PIN_MASK 0x40 544 #define RX_IRQ_BANK_PIN_MASK(_n) \ 545 (((_n) == 3) ? RX_IRQ3_BANK_PIN_MASK : \ 546 ((_n) == 2) ? RX_IRQ2_BANK_PIN_MASK : \ 547 ((_n) == 1) ? RX_IRQ1_BANK_PIN_MASK : \ 548 RX_IRQ0_BANK_PIN_MASK) 549 550 struct airoha_irq_bank { 551 struct airoha_qdma *qdma; 552 553 /* protect concurrent irqmask accesses */ 554 spinlock_t irq_lock; 555 u32 irqmask[QDMA_INT_REG_MAX]; 556 int irq; 557 }; 558 559 struct airoha_qdma { 560 struct airoha_eth *eth; 561 void __iomem *regs; 562 563 struct airoha_irq_bank irq_banks[AIROHA_MAX_NUM_IRQ_BANKS]; 564 565 struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ]; 566 567 struct airoha_queue q_tx[AIROHA_NUM_TX_RING]; 568 struct airoha_queue q_rx[AIROHA_NUM_RX_RING]; 569 570 DECLARE_BITMAP(qos_channel_map, AIROHA_NUM_QOS_CHANNELS); 571 }; 572 573 enum airoha_dev_flags { 574 AIROHA_DEV_F_WAN, 575 AIROHA_DEV_F_TX_QOS, 576 }; 577 578 struct airoha_gdm_dev { 579 struct airoha_qdma __rcu *qdma; 580 struct airoha_gdm_port *port; 581 struct airoha_eth *eth; 582 583 DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS); 584 struct { 585 u32 cpu_tx_packets; 586 u32 fwd_tx_packets; 587 } qos_stats[AIROHA_NUM_QOS_CHANNELS]; 588 589 unsigned long flags; 590 int nbq; 591 592 struct airoha_hw_stats stats; 593 594 /* Serialize netdev_tx_completed_queue() calls per TX queue during 595 * QDMA migration. 596 */ 597 spinlock_t txq_lock[AIROHA_NUM_NETDEV_TX_RINGS]; 598 }; 599 600 struct airoha_gdm_port { 601 struct airoha_gdm_dev *devs[AIROHA_MAX_NUM_GDM_DEVS]; 602 int id; 603 int users; 604 605 /* protect concurrent hw_stats accesses */ 606 spinlock_t stats_lock; 607 608 struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS]; 609 }; 610 611 #define AIROHA_RXD4_PPE_CPU_REASON GENMASK(20, 16) 612 #define AIROHA_RXD4_FOE_ENTRY GENMASK(15, 0) 613 614 struct airoha_ppe { 615 struct airoha_ppe_dev dev; 616 struct airoha_eth *eth; 617 618 void *foe; 619 dma_addr_t foe_dma; 620 621 struct rhashtable l2_flows; 622 623 struct hlist_head *foe_flow; 624 u16 *foe_check_time; 625 626 struct airoha_foe_stats *foe_stats; 627 dma_addr_t foe_stats_dma; 628 629 struct dentry *debugfs_dir; 630 }; 631 632 struct airoha_eth_soc_data { 633 u16 version; 634 const char * const *xsi_rsts_names; 635 int num_xsi_rsts; 636 int num_ppe; 637 struct { 638 int (*get_sport)(struct airoha_gdm_port *port, int nbq); 639 u32 (*get_vip_port)(struct airoha_gdm_port *port, int nbq); 640 int (*get_dev_from_sport)(struct airoha_qdma_desc *desc, 641 u16 *port, u16 *dev); 642 } ops; 643 }; 644 645 struct airoha_eth { 646 struct device *dev; 647 648 const struct airoha_eth_soc_data *soc; 649 650 unsigned long state; 651 void __iomem *fe_regs; 652 653 struct airoha_npu __rcu *npu; 654 655 struct airoha_ppe *ppe; 656 struct rhashtable flow_table; 657 658 struct reset_control_bulk_data rsts[AIROHA_MAX_NUM_RSTS]; 659 struct reset_control_bulk_data *xsi_rsts; 660 661 struct net_device *napi_dev; 662 663 struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA]; 664 struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS]; 665 }; 666 667 u32 airoha_rr(void __iomem *base, u32 offset); 668 void airoha_wr(void __iomem *base, u32 offset, u32 val); 669 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val); 670 671 #define airoha_fe_rr(eth, offset) \ 672 airoha_rr((eth)->fe_regs, (offset)) 673 #define airoha_fe_wr(eth, offset, val) \ 674 airoha_wr((eth)->fe_regs, (offset), (val)) 675 #define airoha_fe_rmw(eth, offset, mask, val) \ 676 airoha_rmw((eth)->fe_regs, (offset), (mask), (val)) 677 #define airoha_fe_set(eth, offset, val) \ 678 airoha_rmw((eth)->fe_regs, (offset), 0, (val)) 679 #define airoha_fe_clear(eth, offset, val) \ 680 airoha_rmw((eth)->fe_regs, (offset), (val), 0) 681 #define airoha_fe_get(eth, offset, mask) \ 682 FIELD_GET((mask), airoha_fe_rr((eth), (offset))) 683 684 #define airoha_qdma_rr(qdma, offset) \ 685 airoha_rr((qdma)->regs, (offset)) 686 #define airoha_qdma_wr(qdma, offset, val) \ 687 airoha_wr((qdma)->regs, (offset), (val)) 688 #define airoha_qdma_rmw(qdma, offset, mask, val) \ 689 airoha_rmw((qdma)->regs, (offset), (mask), (val)) 690 #define airoha_qdma_set(qdma, offset, val) \ 691 airoha_rmw((qdma)->regs, (offset), 0, (val)) 692 #define airoha_qdma_clear(qdma, offset, val) \ 693 airoha_rmw((qdma)->regs, (offset), (val), 0) 694 #define airoha_qdma_get(qdma, offset, mask) \ 695 FIELD_GET((mask), airoha_qdma_rr((qdma), (offset))) 696 697 static inline u16 airoha_qdma_get_txq(struct airoha_qdma *qdma, u16 qid) 698 { 699 return qid % ARRAY_SIZE(qdma->q_tx); 700 } 701 702 static inline bool airoha_is_lan_gdm_dev(struct airoha_gdm_dev *dev) 703 { 704 return !test_bit(AIROHA_DEV_F_WAN, &dev->flags); 705 } 706 707 static inline bool airoha_is_7581(struct airoha_eth *eth) 708 { 709 return eth->soc->version == 0x7581; 710 } 711 712 static inline bool airoha_is_7583(struct airoha_eth *eth) 713 { 714 return eth->soc->version == 0x7583; 715 } 716 717 int airoha_get_fe_port(struct airoha_gdm_dev *dev); 718 bool airoha_is_valid_gdm_dev(struct airoha_eth *eth, 719 struct airoha_gdm_dev *dev); 720 721 extern struct mutex flow_offload_mutex; 722 723 static inline struct airoha_qdma * 724 airoha_qdma_deref(struct airoha_gdm_dev *dev) 725 { 726 return rcu_dereference_protected(dev->qdma, 727 lockdep_rtnl_is_held() || 728 lockdep_is_held(&flow_offload_mutex)); 729 } 730 731 void airoha_ppe_set_xmit_frame_size(struct airoha_gdm_dev *dev); 732 void airoha_ppe_set_cpu_port(struct airoha_gdm_dev *dev, u8 ppe_id, u8 fport); 733 bool airoha_ppe_is_enabled(struct airoha_eth *eth, int index); 734 void airoha_ppe_check_skb(struct airoha_ppe_dev *dev, struct sk_buff *skb, 735 u16 hash, bool rx_wlan); 736 int airoha_ppe_setup_tc_block_cb(struct airoha_ppe_dev *dev, void *type_data); 737 int airoha_ppe_init(struct airoha_eth *eth); 738 void airoha_ppe_deinit(struct airoha_eth *eth); 739 void airoha_ppe_init_upd_mem(struct airoha_gdm_dev *dev, const u8 *addr); 740 u32 airoha_ppe_get_total_num_entries(struct airoha_ppe *ppe); 741 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe, 742 u32 hash); 743 void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash, 744 struct airoha_foe_stats64 *stats); 745 746 #ifdef CONFIG_DEBUG_FS 747 int airoha_ppe_debugfs_init(struct airoha_ppe *ppe); 748 #else 749 static inline int airoha_ppe_debugfs_init(struct airoha_ppe *ppe) 750 { 751 return 0; 752 } 753 #endif 754 755 #endif /* AIROHA_ETH_H */ 756