1 /* SPDX-License-Identifier: GPL-2.0-or-later 2 * 3 * Copyright (C) 2005 David Brownell 4 */ 5 6 #ifndef __LINUX_SPI_H 7 #define __LINUX_SPI_H 8 9 #include <linux/acpi.h> 10 #include <linux/bits.h> 11 #include <linux/completion.h> 12 #include <linux/device.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/kthread.h> 15 #include <linux/device-id/acpi.h> 16 #include <linux/device-id/of.h> 17 #include <linux/device-id/spi.h> 18 #include <linux/overflow.h> 19 #include <linux/scatterlist.h> 20 #include <linux/slab.h> 21 #include <linux/u64_stats_sync.h> 22 23 #include <uapi/linux/spi/spi.h> 24 25 /* Max no. of CS supported per spi device */ 26 #define SPI_DEVICE_CS_CNT_MAX 4 27 28 /* Max no. of data lanes supported per spi device */ 29 #define SPI_DEVICE_DATA_LANE_CNT_MAX 8 30 31 struct dma_chan; 32 struct software_node; 33 struct ptp_system_timestamp; 34 struct spi_controller; 35 struct spi_transfer; 36 struct spi_controller_mem_ops; 37 struct spi_controller_mem_caps; 38 struct spi_message; 39 struct spi_offload; 40 struct spi_offload_config; 41 42 /* 43 * INTERFACES between SPI controller-side drivers and SPI target protocol handlers, 44 * and SPI infrastructure. 45 */ 46 extern const struct bus_type spi_bus_type; 47 48 /** 49 * struct spi_statistics - statistics for spi transfers 50 * @syncp: seqcount to protect members in this struct for per-cpu update 51 * on 32-bit systems 52 * 53 * @messages: number of spi-messages handled 54 * @transfers: number of spi_transfers handled 55 * @errors: number of errors during spi_transfer 56 * @timedout: number of timeouts during spi_transfer 57 * 58 * @spi_sync: number of times spi_sync is used 59 * @spi_sync_immediate: 60 * number of times spi_sync is executed immediately 61 * in calling context without queuing and scheduling 62 * @spi_async: number of times spi_async is used 63 * 64 * @bytes: number of bytes transferred to/from device 65 * @bytes_tx: number of bytes sent to device 66 * @bytes_rx: number of bytes received from device 67 * 68 * @transfer_bytes_histo: 69 * transfer bytes histogram 70 * 71 * @transfers_split_maxsize: 72 * number of transfers that have been split because of 73 * maxsize limit 74 */ 75 struct spi_statistics { 76 struct u64_stats_sync syncp; 77 78 u64_stats_t messages; 79 u64_stats_t transfers; 80 u64_stats_t errors; 81 u64_stats_t timedout; 82 83 u64_stats_t spi_sync; 84 u64_stats_t spi_sync_immediate; 85 u64_stats_t spi_async; 86 87 u64_stats_t bytes; 88 u64_stats_t bytes_rx; 89 u64_stats_t bytes_tx; 90 91 #define SPI_STATISTICS_HISTO_SIZE 17 92 u64_stats_t transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE]; 93 94 u64_stats_t transfers_split_maxsize; 95 }; 96 97 #define SPI_STATISTICS_ADD_TO_FIELD(pcpu_stats, field, count) \ 98 do { \ 99 struct spi_statistics *__lstats; \ 100 get_cpu(); \ 101 __lstats = this_cpu_ptr(pcpu_stats); \ 102 u64_stats_update_begin(&__lstats->syncp); \ 103 u64_stats_add(&__lstats->field, count); \ 104 u64_stats_update_end(&__lstats->syncp); \ 105 put_cpu(); \ 106 } while (0) 107 108 #define SPI_STATISTICS_INCREMENT_FIELD(pcpu_stats, field) \ 109 do { \ 110 struct spi_statistics *__lstats; \ 111 get_cpu(); \ 112 __lstats = this_cpu_ptr(pcpu_stats); \ 113 u64_stats_update_begin(&__lstats->syncp); \ 114 u64_stats_inc(&__lstats->field); \ 115 u64_stats_update_end(&__lstats->syncp); \ 116 put_cpu(); \ 117 } while (0) 118 119 /** 120 * struct spi_delay - SPI delay information 121 * @value: Value for the delay 122 * @unit: Unit for the delay 123 */ 124 struct spi_delay { 125 #define SPI_DELAY_UNIT_USECS 0 126 #define SPI_DELAY_UNIT_NSECS 1 127 #define SPI_DELAY_UNIT_SCK 2 128 u16 value; 129 u8 unit; 130 }; 131 132 extern int spi_delay_to_ns(struct spi_delay *_delay, struct spi_transfer *xfer); 133 extern int spi_delay_exec(struct spi_delay *_delay, struct spi_transfer *xfer); 134 extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg, 135 struct spi_transfer *xfer); 136 137 /** 138 * struct spi_device - Controller side proxy for an SPI target device 139 * @dev: Driver model representation of the device. 140 * @controller: SPI controller used with the device. 141 * @max_speed_hz: Maximum clock rate to be used with this chip 142 * (on this board); may be changed by the device's driver. 143 * The spi_transfer.speed_hz can override this for each transfer. 144 * @bits_per_word: Data transfers involve one or more words; word sizes 145 * like eight or 12 bits are common. In-memory wordsizes are 146 * powers of two bytes (e.g. 20 bit samples use 32 bits). 147 * This may be changed by the device's driver, or left at the 148 * default (0) indicating protocol words are eight bit bytes. 149 * The spi_transfer.bits_per_word can override this for each transfer. 150 * @rt: Make the pump thread real time priority. 151 * @mode: The spi mode defines how data is clocked out and in. 152 * This may be changed by the device's driver. 153 * The "active low" default for chipselect mode can be overridden 154 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for 155 * each word in a transfer (by specifying SPI_LSB_FIRST). 156 * @irq: Negative, or the number passed to request_irq() to receive 157 * interrupts from this device. 158 * @controller_state: Controller's runtime state 159 * @controller_data: Board-specific definitions for controller, such as 160 * FIFO initialization parameters; from board_info.controller_data 161 * @modalias: Name of the driver to use with this device, or an alias 162 * for that name. This appears in the sysfs "modalias" attribute 163 * for driver coldplugging, and in uevents used for hotplugging 164 * @pcpu_statistics: statistics for the spi_device 165 * @word_delay: delay to be inserted between consecutive 166 * words of a transfer 167 * @cs_setup: delay to be introduced by the controller after CS is asserted 168 * @cs_hold: delay to be introduced by the controller before CS is deasserted 169 * @cs_inactive: delay to be introduced by the controller after CS is 170 * deasserted. If @cs_change_delay is used from @spi_transfer, then the 171 * two delays will be added up. 172 * @rx_sample_delay_ns: Delay in nanoseconds by which the controller should 173 * postpone sampling the incoming data, relative to the sampling point it 174 * uses by default. Describes the board rather than the device, namely the 175 * flight time of the clock and data signals between controller and 176 * device, and comes from the "rx-sample-delay-ns" property. Zero when the 177 * property is absent. 178 * @chip_select: Array of physical chipselect, spi->chipselect[i] gives 179 * the corresponding physical CS for logical CS i. 180 * @num_chipselect: Number of physical chipselects used. 181 * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array 182 * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect lines 183 * (optional, NULL when not using a GPIO line) 184 * @tx_lane_map: Map of peripheral lanes (index) to controller lanes (value). 185 * @num_tx_lanes: Number of transmit lanes wired up. 186 * @rx_lane_map: Map of peripheral lanes (index) to controller lanes (value). 187 * @num_rx_lanes: Number of receive lanes wired up. 188 * @userspace_node: entry on the parent controller's userspace_clients list 189 * when this device was instantiated via the sysfs new_device interface 190 * 191 * A @spi_device is used to interchange data between an SPI target device 192 * (usually a discrete chip) and CPU memory. 193 * 194 * In @dev, the platform_data is used to hold information about this 195 * device that's meaningful to the device's protocol driver, but not 196 * to its controller. One example might be an identifier for a chip 197 * variant with slightly different functionality; another might be 198 * information about how this particular board wires the chip's pins. 199 */ 200 struct spi_device { 201 struct device dev; 202 struct spi_controller *controller; 203 u32 max_speed_hz; 204 u8 bits_per_word; 205 bool rt; 206 #define SPI_NO_TX BIT(31) /* No transmit wire */ 207 #define SPI_NO_RX BIT(30) /* No receive wire */ 208 /* 209 * TPM specification defines flow control over SPI. Client device 210 * can insert a wait state on MISO when address is transmitted by 211 * controller on MOSI. Detecting the wait state in software is only 212 * possible for full duplex controllers. For controllers that support 213 * only half-duplex, the wait state detection needs to be implemented 214 * in hardware. TPM devices would set this flag when hardware flow 215 * control is expected from SPI controller. 216 */ 217 #define SPI_TPM_HW_FLOW BIT(29) /* TPM HW flow control */ 218 /* 219 * All bits defined above should be covered by SPI_MODE_KERNEL_MASK. 220 * The SPI_MODE_KERNEL_MASK has the SPI_MODE_USER_MASK counterpart, 221 * which is defined in 'include/uapi/linux/spi/spi.h'. 222 * The bits defined here are from bit 31 downwards, while in 223 * SPI_MODE_USER_MASK are from 0 upwards. 224 * These bits must not overlap. A static assert check should make sure of that. 225 * If adding extra bits, make sure to decrease the bit index below as well. 226 */ 227 #define SPI_MODE_KERNEL_MASK (~(BIT(29) - 1)) 228 u32 mode; 229 int irq; 230 void *controller_state; 231 void *controller_data; 232 char modalias[SPI_NAME_SIZE]; 233 234 /* The statistics */ 235 struct spi_statistics __percpu *pcpu_statistics; 236 237 struct spi_delay word_delay; /* Inter-word delay */ 238 239 /* CS delays */ 240 struct spi_delay cs_setup; 241 struct spi_delay cs_hold; 242 struct spi_delay cs_inactive; 243 244 /* Additional delay before the incoming data is sampled, in ns */ 245 u32 rx_sample_delay_ns; 246 247 u8 chip_select[SPI_DEVICE_CS_CNT_MAX]; 248 u8 num_chipselect; 249 250 /* 251 * Bit mask of the chipselect(s) that the driver need to use from 252 * the chipselect array. When the controller is capable to handle 253 * multiple chip selects & memories are connected in parallel 254 * then more than one bit need to be set in cs_index_mask. 255 */ 256 u32 cs_index_mask : SPI_DEVICE_CS_CNT_MAX; 257 258 struct gpio_desc *cs_gpiod[SPI_DEVICE_CS_CNT_MAX]; /* Chip select gpio desc */ 259 260 /* Multi-lane SPI controller support. */ 261 u8 tx_lane_map[SPI_DEVICE_DATA_LANE_CNT_MAX]; 262 u8 num_tx_lanes; 263 u8 rx_lane_map[SPI_DEVICE_DATA_LANE_CNT_MAX]; 264 u8 num_rx_lanes; 265 266 #if IS_ENABLED(CONFIG_SPI_DYNAMIC) 267 struct list_head userspace_node; 268 #endif 269 270 /* 271 * Likely need more hooks for more protocol options affecting how 272 * the controller talks to each chip, like: 273 * - memory packing (12 bit samples into low bits, others zeroed) 274 * - priority 275 * - chipselect delays 276 * - ... 277 */ 278 }; 279 280 /* Make sure that SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK don't overlap */ 281 static_assert((SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK) == 0, 282 "SPI_MODE_USER_MASK & SPI_MODE_KERNEL_MASK must not overlap"); 283 284 #define to_spi_device(__dev) container_of_const(__dev, struct spi_device, dev) 285 286 /* Most drivers won't need to care about device refcounting */ 287 static inline struct spi_device *spi_dev_get(struct spi_device *spi) 288 { 289 return (spi && get_device(&spi->dev)) ? spi : NULL; 290 } 291 292 static inline void spi_dev_put(struct spi_device *spi) 293 { 294 if (spi) 295 put_device(&spi->dev); 296 } 297 298 /* ctldata is for the bus_controller driver's runtime state */ 299 static inline void *spi_get_ctldata(const struct spi_device *spi) 300 { 301 return spi->controller_state; 302 } 303 304 static inline void spi_set_ctldata(struct spi_device *spi, void *state) 305 { 306 spi->controller_state = state; 307 } 308 309 /* Device driver data */ 310 311 static inline void spi_set_drvdata(struct spi_device *spi, void *data) 312 { 313 dev_set_drvdata(&spi->dev, data); 314 } 315 316 static inline void *spi_get_drvdata(const struct spi_device *spi) 317 { 318 return dev_get_drvdata(&spi->dev); 319 } 320 321 static inline u8 spi_get_chipselect(const struct spi_device *spi, u8 idx) 322 { 323 return spi->chip_select[idx]; 324 } 325 326 static inline void spi_set_chipselect(struct spi_device *spi, u8 idx, u8 chipselect) 327 { 328 spi->chip_select[idx] = chipselect; 329 } 330 331 static inline struct gpio_desc *spi_get_csgpiod(const struct spi_device *spi, u8 idx) 332 { 333 return spi->cs_gpiod[idx]; 334 } 335 336 static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx, struct gpio_desc *csgpiod) 337 { 338 spi->cs_gpiod[idx] = csgpiod; 339 } 340 341 static inline bool spi_is_csgpiod(struct spi_device *spi) 342 { 343 u8 idx; 344 345 for (idx = 0; idx < spi->num_chipselect; idx++) { 346 if (spi_get_csgpiod(spi, idx)) 347 return true; 348 } 349 return false; 350 } 351 352 /** 353 * struct spi_driver - Host side "protocol" driver 354 * @id_table: List of SPI devices supported by this driver 355 * @probe: Binds this driver to the SPI device. Drivers can verify 356 * that the device is actually present, and may need to configure 357 * characteristics (such as bits_per_word) which weren't needed for 358 * the initial configuration done during system setup. 359 * @remove: Unbinds this driver from the SPI device 360 * @shutdown: Standard shutdown callback used during system state 361 * transitions such as powerdown/halt and kexec 362 * @driver: SPI device drivers should initialize the name and owner 363 * field of this structure. 364 * 365 * This represents the kind of device driver that uses SPI messages to 366 * interact with the hardware at the other end of a SPI link. It's called 367 * a "protocol" driver because it works through messages rather than talking 368 * directly to SPI hardware (which is what the underlying SPI controller 369 * driver does to pass those messages). These protocols are defined in the 370 * specification for the device(s) supported by the driver. 371 * 372 * As a rule, those device protocols represent the lowest level interface 373 * supported by a driver, and it will support upper level interfaces too. 374 * Examples of such upper levels include frameworks like MTD, networking, 375 * MMC, RTC, filesystem character device nodes, and hardware monitoring. 376 */ 377 struct spi_driver { 378 const struct spi_device_id *id_table; 379 int (*probe)(struct spi_device *spi); 380 void (*remove)(struct spi_device *spi); 381 void (*shutdown)(struct spi_device *spi); 382 struct device_driver driver; 383 }; 384 385 #define to_spi_driver(__drv) \ 386 ( __drv ? container_of_const(__drv, struct spi_driver, driver) : NULL ) 387 388 extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv); 389 390 /** 391 * spi_unregister_driver - reverse effect of spi_register_driver 392 * @sdrv: the driver to unregister 393 * Context: can sleep 394 */ 395 static inline void spi_unregister_driver(struct spi_driver *sdrv) 396 { 397 if (sdrv) 398 driver_unregister(&sdrv->driver); 399 } 400 401 extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 chip_select); 402 extern struct spi_device *devm_spi_new_ancillary_device(struct spi_device *spi, u8 chip_select); 403 404 /* Use a define to avoid include chaining to get THIS_MODULE */ 405 #define spi_register_driver(driver) \ 406 __spi_register_driver(THIS_MODULE, driver) 407 408 /** 409 * module_spi_driver() - Helper macro for registering a SPI driver 410 * @__spi_driver: spi_driver struct 411 * 412 * Helper macro for SPI drivers which do not do anything special in module 413 * init/exit. This eliminates a lot of boilerplate. Each module may only 414 * use this macro once, and calling it replaces module_init() and module_exit() 415 */ 416 #define module_spi_driver(__spi_driver) \ 417 module_driver(__spi_driver, spi_register_driver, \ 418 spi_unregister_driver) 419 420 /** 421 * struct spi_controller - interface to SPI host or target controller 422 * @dev: device interface to this driver 423 * @list: link with the global spi_controller list 424 * @bus_num: board-specific (and often SOC-specific) identifier for a 425 * given SPI controller. 426 * @num_chipselect: chipselects are used to distinguish individual 427 * SPI targets, and are numbered from zero to num_chipselects. 428 * each target has a chipselect signal, but it's common that not 429 * every chipselect is connected to a target. 430 * @num_data_lanes: Number of data lanes supported by this controller. Default is 1. 431 * @dma_alignment: SPI controller constraint on DMA buffers alignment. 432 * @mode_bits: flags understood by this controller driver 433 * @buswidth_override_bits: flags to override for this controller driver 434 * @bits_per_word_mask: A mask indicating which values of bits_per_word are 435 * supported by the driver. Bit n indicates that a bits_per_word n+1 is 436 * supported. If set, the SPI core will reject any transfer with an 437 * unsupported bits_per_word. If not set, this value is simply ignored, 438 * and it's up to the individual driver to perform any validation. 439 * @min_speed_hz: Lowest supported transfer speed 440 * @max_speed_hz: Highest supported transfer speed 441 * @flags: other constraints relevant to this driver 442 * @slave: indicates that this is an SPI slave controller 443 * @target: indicates that this is an SPI target controller 444 * @max_transfer_size: function that returns the max transfer size for 445 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 446 * @max_message_size: function that returns the max message size for 447 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 448 * @io_mutex: mutex for physical bus access 449 * @add_lock: mutex to avoid adding devices to the same chipselect 450 * @bus_lock_spinlock: spinlock for SPI bus locking 451 * @bus_lock_mutex: mutex for exclusion of multiple callers 452 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use 453 * @setup: updates the device mode and clocking records used by a 454 * device's SPI controller; protocol code may call this. This 455 * must fail if an unrecognized or unsupported mode is requested. 456 * It's always safe to call this unless transfers are pending on 457 * the device whose settings are being modified. 458 * @set_cs_timing: optional hook for SPI devices to request SPI 459 * controller for configuring specific CS setup time, hold time and inactive 460 * delay in terms of clock counts 461 * @transfer: adds a message to the controller's transfer queue. 462 * @cleanup: frees controller-specific state 463 * @can_dma: determine whether this controller supports DMA 464 * @dma_map_dev: device which can be used for DMA mapping 465 * @cur_rx_dma_dev: device which is currently used for RX DMA mapping 466 * @cur_tx_dma_dev: device which is currently used for TX DMA mapping 467 * @queued: whether this controller is providing an internal message queue 468 * @kworker: pointer to thread struct for message pump 469 * @pump_messages: work struct for scheduling work to the message pump 470 * @queue_lock: spinlock to synchronise access to message queue 471 * @queue: message queue 472 * @cur_msg: the currently in-flight message 473 * @cur_msg_completion: a completion for the current in-flight message 474 * @cur_msg_incomplete: Flag used internally to opportunistically skip 475 * the @cur_msg_completion. This flag is used to check if the driver has 476 * already called spi_finalize_current_message(). 477 * @cur_msg_need_completion: Flag used internally to opportunistically skip 478 * the @cur_msg_completion. This flag is used to signal the context that 479 * is running spi_finalize_current_message() that it needs to complete() 480 * @fallback: fallback to PIO if DMA transfer return failure with 481 * SPI_TRANS_FAIL_NO_START. 482 * @last_cs_mode_high: was (mode & SPI_CS_HIGH) true on the last call to set_cs. 483 * @last_cs: the last chip_select that is recorded by set_cs, -1 on non chip 484 * selected 485 * @last_cs_index_mask: bit mask the last chip selects that were used 486 * @xfer_completion: used by core transfer_one_message() 487 * @busy: message pump is busy 488 * @running: message pump is running 489 * @rt: whether this queue is set to run as a realtime task 490 * @auto_runtime_pm: the core should ensure a runtime PM reference is held 491 * while the hardware is prepared, using the parent 492 * device for the spidev 493 * @max_dma_len: Maximum length of a DMA transfer for the device. 494 * @prepare_transfer_hardware: a message will soon arrive from the queue 495 * so the subsystem requests the driver to prepare the transfer hardware 496 * by issuing this call 497 * @transfer_one_message: the subsystem calls the driver to transfer a single 498 * message while queuing transfers that arrive in the meantime. When the 499 * driver is finished with this message, it must call 500 * spi_finalize_current_message() so the subsystem can issue the next 501 * message 502 * @unprepare_transfer_hardware: there are currently no more messages on the 503 * queue so the subsystem notifies the driver that it may relax the 504 * hardware by issuing this call 505 * 506 * @set_cs: set the logic level of the chip select line. May be called 507 * from interrupt context. 508 * @optimize_message: optimize the message for reuse 509 * @unoptimize_message: release resources allocated by optimize_message 510 * @prepare_message: set up the controller to transfer a single message, 511 * for example doing DMA mapping. Called from threaded 512 * context. 513 * @transfer_one: transfer a single spi_transfer. 514 * 515 * - return 0 if the transfer is finished, 516 * - return 1 if the transfer is still in progress. When 517 * the driver is finished with this transfer it must 518 * call spi_finalize_current_transfer() so the subsystem 519 * can issue the next transfer. If the transfer fails, the 520 * driver must set the flag SPI_TRANS_FAIL_IO to 521 * spi_transfer->error first, before calling 522 * spi_finalize_current_transfer(). 523 * Note: transfer_one and transfer_one_message are mutually 524 * exclusive; when both are set, the generic subsystem does 525 * not call your transfer_one callback. 526 * @handle_err: the subsystem calls the driver to handle an error that occurs 527 * in the generic implementation of transfer_one_message(). 528 * @mem_ops: optimized/dedicated operations for interactions with SPI memory. 529 * This field is optional and should only be implemented if the 530 * controller has native support for memory like operations. 531 * @get_offload: callback for controllers with offload support to get matching 532 * offload instance. Implementations should return -ENODEV if no match is 533 * found. 534 * @put_offload: release the offload instance acquired by @get_offload. 535 * @mem_caps: controller capabilities for the handling of memory operations. 536 * @dtr_caps: true if controller has dtr(single/dual transfer rate) capability. 537 * QSPI based controller should fill this based on controller's capability. 538 * @unprepare_message: undo any work done by prepare_message(). 539 * @target_abort: abort the ongoing transfer request on an SPI target controller 540 * @cs_gpiods: Array of GPIO descriptors to use as chip select lines; one per CS 541 * number. Any individual value may be NULL for CS lines that 542 * are not GPIOs (driven by the SPI controller itself). 543 * @use_gpio_descriptors: Turns on the code in the SPI core to parse and grab 544 * GPIO descriptors. This will fill in @cs_gpiods and SPI devices will have 545 * the cs_gpiod assigned if a GPIO line is found for the chipselect. 546 * @unused_native_cs: When cs_gpiods is used, spi_register_controller() will 547 * fill in this field with the first unused native CS, to be used by SPI 548 * controller drivers that need to drive a native CS when using GPIO CS. 549 * @max_native_cs: When cs_gpiods is used, and this field is filled in, 550 * spi_register_controller() will validate all native CS (including the 551 * unused native CS) against this value. 552 * @pcpu_statistics: statistics for the spi_controller 553 * @dma_tx: DMA transmit channel 554 * @dma_rx: DMA receive channel 555 * @dummy_rx: dummy receive buffer for full-duplex devices 556 * @dummy_tx: dummy transmit buffer for full-duplex devices 557 * @fw_translate_cs: If the boot firmware uses different numbering scheme 558 * what Linux expects, this optional hook can be used to translate 559 * between the two. 560 * @ptp_sts_supported: If the driver sets this to true, it must provide a 561 * time snapshot in @spi_transfer->ptp_sts as close as possible to the 562 * moment in time when @spi_transfer->ptp_sts_word_pre and 563 * @spi_transfer->ptp_sts_word_post were transmitted. 564 * If the driver does not set this, the SPI core takes the snapshot as 565 * close to the driver hand-over as possible. 566 * @irq_flags: Interrupt enable state during PTP system timestamping 567 * @queue_empty: signal green light for opportunistically skipping the queue 568 * for spi_sync transfers. 569 * @must_async: disable all fast paths in the core 570 * @defer_optimize_message: set to true if controller cannot pre-optimize messages 571 * and needs to defer the optimization step until the message is actually 572 * being transferred 573 * @userspace_clients: list of SPI devices instantiated from userspace via 574 * the sysfs new_device interface; protected by @add_lock 575 * @userspace_registered: true once the new_device/delete_device sysfs 576 * group has been added by spi_register_controller(); used by 577 * spi_unregister_controller() to know whether to remove it 578 * 579 * Each SPI controller can communicate with one or more @spi_device 580 * children. These make a small bus, sharing MOSI, MISO and SCK signals 581 * but not chip select signals. Each device may be configured to use a 582 * different clock rate, since those shared signals are ignored unless 583 * the chip is selected. 584 * 585 * The driver for an SPI controller manages access to those devices through 586 * a queue of spi_message transactions, copying data between CPU memory and 587 * an SPI target device. For each such message it queues, it calls the 588 * message's completion function when the transaction completes. 589 */ 590 struct spi_controller { 591 struct device dev; 592 593 struct list_head list; 594 595 /* 596 * Other than negative (== assign one dynamically), bus_num is fully 597 * board-specific. Usually that simplifies to being SoC-specific. 598 * example: one SoC has three SPI controllers, numbered 0..2, 599 * and one board's schematics might show it using SPI-2. Software 600 * would normally use bus_num=2 for that controller. 601 */ 602 s16 bus_num; 603 604 /* 605 * Chipselects will be integral to many controllers; some others 606 * might use board-specific GPIOs. 607 */ 608 u16 num_chipselect; 609 610 /* 611 * Some specialized SPI controllers can have more than one physical 612 * data lane interface per controller (each having it's own serializer). 613 * This specifies the number of data lanes in that case. Other 614 * controllers do not need to set this (defaults to 1). 615 */ 616 u16 num_data_lanes; 617 618 /* Some SPI controllers pose alignment requirements on DMAable 619 * buffers; let protocol drivers know about these requirements. 620 */ 621 u16 dma_alignment; 622 623 /* spi_device.mode flags understood by this controller driver */ 624 u32 mode_bits; 625 626 /* spi_device.mode flags override flags for this controller */ 627 u32 buswidth_override_bits; 628 629 /* Bitmask of supported bits_per_word for transfers */ 630 u32 bits_per_word_mask; 631 #define SPI_BPW_MASK(bits) BIT((bits) - 1) 632 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1) 633 634 /* Limits on transfer speed */ 635 u32 min_speed_hz; 636 u32 max_speed_hz; 637 638 /* Other constraints relevant to this driver */ 639 u16 flags; 640 #define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* Can't do full duplex */ 641 #define SPI_CONTROLLER_NO_RX BIT(1) /* Can't do buffer read */ 642 #define SPI_CONTROLLER_NO_TX BIT(2) /* Can't do buffer write */ 643 #define SPI_CONTROLLER_MUST_RX BIT(3) /* Requires rx */ 644 #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx */ 645 #define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS must select target device */ 646 #define SPI_CONTROLLER_SUSPENDED BIT(6) /* Currently suspended */ 647 /* 648 * The spi-controller has multi chip select capability and can 649 * assert/de-assert more than one chip select at once. 650 */ 651 #define SPI_CONTROLLER_MULTI_CS BIT(7) 652 653 union { 654 /* Flag indicating this is an SPI slave controller */ 655 bool slave; 656 /* Flag indicating this is an SPI target controller */ 657 bool target; 658 }; 659 660 /* 661 * On some hardware transfer / message size may be constrained 662 * the limit may depend on device transfer settings. 663 */ 664 size_t (*max_transfer_size)(struct spi_device *spi); 665 size_t (*max_message_size)(struct spi_device *spi); 666 667 /* I/O mutex */ 668 struct mutex io_mutex; 669 670 /* Used to avoid adding the same CS twice */ 671 struct mutex add_lock; 672 673 /* Lock and mutex for SPI bus locking */ 674 spinlock_t bus_lock_spinlock; 675 struct mutex bus_lock_mutex; 676 677 /* Flag indicating that the SPI bus is locked for exclusive use */ 678 bool bus_lock_flag; 679 680 /* 681 * Setup mode and clock, etc (SPI driver may call many times). 682 * 683 * IMPORTANT: this may be called when transfers to another 684 * device are active. DO NOT UPDATE SHARED REGISTERS in ways 685 * which could break those transfers. 686 */ 687 int (*setup)(struct spi_device *spi); 688 689 /* 690 * set_cs_timing() method is for SPI controllers that supports 691 * configuring CS timing. 692 * 693 * This hook allows SPI client drivers to request SPI controllers 694 * to configure specific CS timing through spi_set_cs_timing() after 695 * spi_setup(). 696 */ 697 int (*set_cs_timing)(struct spi_device *spi); 698 699 /* 700 * Bidirectional bulk transfers 701 * 702 * + The transfer() method may not sleep; its main role is 703 * just to add the message to the queue. 704 * + For now there's no remove-from-queue operation, or 705 * any other request management 706 * + To a given spi_device, message queueing is pure FIFO 707 * 708 * + The controller's main job is to process its message queue, 709 * selecting a chip (for controllers), then transferring data 710 * + If there are multiple spi_device children, the i/o queue 711 * arbitration algorithm is unspecified (round robin, FIFO, 712 * priority, reservations, preemption, etc) 713 * 714 * + Chipselect stays active during the entire message 715 * (unless modified by spi_transfer.cs_change != 0). 716 * + The message transfers use clock and SPI mode parameters 717 * previously established by setup() for this device 718 */ 719 int (*transfer)(struct spi_device *spi, 720 struct spi_message *mesg); 721 722 /* Called on deregistration to free memory provided by spi_controller */ 723 void (*cleanup)(struct spi_device *spi); 724 725 /* 726 * Used to enable core support for DMA handling, if can_dma() 727 * exists and returns true then the transfer will be mapped 728 * prior to transfer_one() being called. The driver should 729 * not modify or store xfer and dma_tx and dma_rx must be set 730 * while the device is prepared. 731 */ 732 bool (*can_dma)(struct spi_controller *ctlr, 733 struct spi_device *spi, 734 struct spi_transfer *xfer); 735 struct device *dma_map_dev; 736 struct device *cur_rx_dma_dev; 737 struct device *cur_tx_dma_dev; 738 739 /* 740 * These hooks are for drivers that want to use the generic 741 * controller transfer queueing mechanism. If these are used, the 742 * transfer() function above must NOT be specified by the driver. 743 * Over time we expect SPI drivers to be phased over to this API. 744 */ 745 bool queued; 746 struct kthread_worker *kworker; 747 struct kthread_work pump_messages; 748 spinlock_t queue_lock; 749 struct list_head queue; 750 struct spi_message *cur_msg; 751 struct completion cur_msg_completion; 752 bool cur_msg_incomplete; 753 bool cur_msg_need_completion; 754 bool busy; 755 bool running; 756 bool rt; 757 bool auto_runtime_pm; 758 bool fallback; 759 bool last_cs_mode_high; 760 s8 last_cs[SPI_DEVICE_CS_CNT_MAX]; 761 u32 last_cs_index_mask : SPI_DEVICE_CS_CNT_MAX; 762 struct completion xfer_completion; 763 size_t max_dma_len; 764 765 int (*optimize_message)(struct spi_message *msg); 766 int (*unoptimize_message)(struct spi_message *msg); 767 int (*prepare_transfer_hardware)(struct spi_controller *ctlr); 768 int (*transfer_one_message)(struct spi_controller *ctlr, 769 struct spi_message *mesg); 770 int (*unprepare_transfer_hardware)(struct spi_controller *ctlr); 771 int (*prepare_message)(struct spi_controller *ctlr, 772 struct spi_message *message); 773 int (*unprepare_message)(struct spi_controller *ctlr, 774 struct spi_message *message); 775 int (*target_abort)(struct spi_controller *ctlr); 776 777 /* 778 * These hooks are for drivers that use a generic implementation 779 * of transfer_one_message() provided by the core. 780 */ 781 void (*set_cs)(struct spi_device *spi, bool enable); 782 int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi, 783 struct spi_transfer *transfer); 784 void (*handle_err)(struct spi_controller *ctlr, 785 struct spi_message *message); 786 787 /* Optimized handlers for SPI memory-like operations. */ 788 const struct spi_controller_mem_ops *mem_ops; 789 const struct spi_controller_mem_caps *mem_caps; 790 791 /* SPI or QSPI controller can set to true if supports SDR/DDR transfer rate */ 792 bool dtr_caps; 793 794 struct spi_offload *(*get_offload)(struct spi_device *spi, 795 const struct spi_offload_config *config); 796 void (*put_offload)(struct spi_offload *offload); 797 798 /* GPIO chip select */ 799 struct gpio_desc **cs_gpiods; 800 bool use_gpio_descriptors; 801 s8 unused_native_cs; 802 s8 max_native_cs; 803 804 /* Statistics */ 805 struct spi_statistics __percpu *pcpu_statistics; 806 807 /* DMA channels for use with core dmaengine helpers */ 808 struct dma_chan *dma_tx; 809 struct dma_chan *dma_rx; 810 811 /* Dummy data for full duplex devices */ 812 void *dummy_rx; 813 void *dummy_tx; 814 815 int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); 816 817 /* 818 * Driver sets this field to indicate it is able to snapshot SPI 819 * transfers (needed e.g. for reading the time of POSIX clocks) 820 */ 821 bool ptp_sts_supported; 822 823 /* Interrupt enable state during PTP system timestamping */ 824 unsigned long irq_flags; 825 826 /* Flag for enabling opportunistic skipping of the queue in spi_sync */ 827 bool queue_empty; 828 bool must_async; 829 bool defer_optimize_message; 830 831 #if IS_ENABLED(CONFIG_SPI_DYNAMIC) 832 /* List of userspace-instantiated devices; protected by @add_lock */ 833 struct list_head userspace_clients; 834 /* True after new_device/delete_device sysfs group is created */ 835 bool userspace_registered; 836 #endif 837 }; 838 839 static inline void *spi_controller_get_devdata(struct spi_controller *ctlr) 840 { 841 return dev_get_drvdata(&ctlr->dev); 842 } 843 844 static inline void spi_controller_set_devdata(struct spi_controller *ctlr, 845 void *data) 846 { 847 dev_set_drvdata(&ctlr->dev, data); 848 } 849 850 static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr) 851 { 852 if (!ctlr || !get_device(&ctlr->dev)) 853 return NULL; 854 return ctlr; 855 } 856 857 static inline void spi_controller_put(struct spi_controller *ctlr) 858 { 859 if (ctlr) 860 put_device(&ctlr->dev); 861 } 862 863 static inline bool spi_controller_is_target(struct spi_controller *ctlr) 864 { 865 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->target; 866 } 867 868 /* PM calls that need to be issued by the driver */ 869 extern int spi_controller_suspend(struct spi_controller *ctlr); 870 extern int spi_controller_resume(struct spi_controller *ctlr); 871 872 /* Calls the driver make to interact with the message queue */ 873 extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr); 874 extern void spi_finalize_current_message(struct spi_controller *ctlr); 875 extern void spi_finalize_current_transfer(struct spi_controller *ctlr); 876 877 /* Helper calls for driver to timestamp transfer */ 878 void spi_take_timestamp_pre(struct spi_controller *ctlr, 879 struct spi_transfer *xfer, 880 size_t progress, bool irqs_off); 881 void spi_take_timestamp_post(struct spi_controller *ctlr, 882 struct spi_transfer *xfer, 883 size_t progress, bool irqs_off); 884 885 /* The SPI driver core manages memory for the spi_controller classdev */ 886 extern struct spi_controller *__spi_alloc_controller(struct device *host, 887 unsigned int size, bool target); 888 889 static inline struct spi_controller *spi_alloc_host(struct device *dev, 890 unsigned int size) 891 { 892 return __spi_alloc_controller(dev, size, false); 893 } 894 895 static inline struct spi_controller *spi_alloc_target(struct device *dev, 896 unsigned int size) 897 { 898 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 899 return NULL; 900 901 return __spi_alloc_controller(dev, size, true); 902 } 903 904 struct spi_controller *__devm_spi_alloc_controller(struct device *dev, 905 unsigned int size, 906 bool target); 907 908 static inline struct spi_controller *devm_spi_alloc_host(struct device *dev, 909 unsigned int size) 910 { 911 return __devm_spi_alloc_controller(dev, size, false); 912 } 913 914 static inline struct spi_controller *devm_spi_alloc_target(struct device *dev, 915 unsigned int size) 916 { 917 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 918 return NULL; 919 920 return __devm_spi_alloc_controller(dev, size, true); 921 } 922 923 extern int spi_register_controller(struct spi_controller *ctlr); 924 extern int devm_spi_register_controller(struct device *dev, 925 struct spi_controller *ctlr); 926 extern void spi_unregister_controller(struct spi_controller *ctlr); 927 928 #if IS_ENABLED(CONFIG_OF) 929 extern struct spi_controller *of_find_spi_controller_by_node(struct device_node *node); 930 #else 931 static inline struct spi_controller *of_find_spi_controller_by_node(struct device_node *node) 932 { 933 return NULL; 934 } 935 #endif 936 937 #if IS_ENABLED(CONFIG_ACPI) && IS_ENABLED(CONFIG_SPI_MASTER) 938 extern struct spi_controller *acpi_spi_find_controller_by_adev(struct acpi_device *adev); 939 extern struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr, 940 struct acpi_device *adev, 941 int index); 942 int acpi_spi_count_resources(struct acpi_device *adev); 943 #else 944 static inline struct spi_controller *acpi_spi_find_controller_by_adev(struct acpi_device *adev) 945 { 946 return NULL; 947 } 948 949 static inline struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr, 950 struct acpi_device *adev, 951 int index) 952 { 953 return ERR_PTR(-ENODEV); 954 } 955 956 static inline int acpi_spi_count_resources(struct acpi_device *adev) 957 { 958 return 0; 959 } 960 #endif 961 962 /* 963 * SPI resource management while processing a SPI message 964 */ 965 966 typedef void (*spi_res_release_t)(struct spi_controller *ctlr, 967 struct spi_message *msg, 968 void *res); 969 970 /** 971 * struct spi_res - SPI resource management structure 972 * @entry: list entry 973 * @release: release code called prior to freeing this resource 974 * @data: extra data allocated for the specific use-case 975 * 976 * This is based on ideas from devres, but focused on life-cycle 977 * management during spi_message processing. 978 */ 979 struct spi_res { 980 struct list_head entry; 981 spi_res_release_t release; 982 unsigned long long data[]; /* Guarantee ull alignment */ 983 }; 984 985 /*---------------------------------------------------------------------------*/ 986 987 /* 988 * I/O INTERFACE between SPI controller and protocol drivers 989 * 990 * Protocol drivers use a queue of spi_messages, each transferring data 991 * between the controller and memory buffers. 992 * 993 * The spi_messages themselves consist of a series of read+write transfer 994 * segments. Those segments always read the same number of bits as they 995 * write; but one or the other is easily ignored by passing a NULL buffer 996 * pointer. (This is unlike most types of I/O API, because SPI hardware 997 * is full duplex.) 998 * 999 * NOTE: Allocation of spi_transfer and spi_message memory is entirely 1000 * up to the protocol driver, which guarantees the integrity of both (as 1001 * well as the data buffers) for as long as the message is queued. 1002 */ 1003 1004 /** 1005 * struct spi_transfer - a read/write buffer pair 1006 * @tx_buf: data to be written (DMA-safe memory), or NULL 1007 * @rx_buf: data to be read (DMA-safe memory), or NULL 1008 * @tx_dma: DMA address of tx_buf, currently not for client use 1009 * @rx_dma: DMA address of rx_buf, currently not for client use 1010 * @tx_nbits: number of bits used for writing. If 0 the default 1011 * (SPI_NBITS_SINGLE) is used. 1012 * @rx_nbits: number of bits used for reading. If 0 the default 1013 * (SPI_NBITS_SINGLE) is used. 1014 * @multi_lane_mode: How to serialize data on multiple lanes. One of the 1015 * SPI_MULTI_LANE_MODE_* values. 1016 * @len: size of rx and tx buffers (in bytes) 1017 * @speed_hz: Select a speed other than the device default for this 1018 * transfer. If 0 the default (from @spi_device) is used. 1019 * @bits_per_word: select a bits_per_word other than the device default 1020 * for this transfer. If 0 the default (from @spi_device) is used. 1021 * @dummy_data: indicates transfer is dummy bytes transfer. 1022 * @cs_off: performs the transfer with chipselect off. 1023 * @cs_change: affects chipselect after this transfer completes 1024 * @cs_change_delay: delay between cs deassert and assert when 1025 * @cs_change is set and @spi_transfer is not the last in @spi_message 1026 * @delay: delay to be introduced after this transfer before 1027 * (optionally) changing the chipselect status, then starting 1028 * the next transfer or completing this @spi_message. 1029 * @word_delay: inter word delay to be introduced after each word size 1030 * (set by bits_per_word) transmission. 1031 * @effective_speed_hz: the effective SCK-speed that was used to 1032 * transfer this transfer. Set to 0 if the SPI bus driver does 1033 * not support it. 1034 * @transfer_list: transfers are sequenced through @spi_message.transfers 1035 * @tx_sg_mapped: If true, the @tx_sg is mapped for DMA 1036 * @rx_sg_mapped: If true, the @rx_sg is mapped for DMA 1037 * @tx_sg: Scatterlist for transmit, currently not for client use 1038 * @rx_sg: Scatterlist for receive, currently not for client use 1039 * @offload_flags: Flags that are only applicable to specialized SPI offload 1040 * transfers. See %SPI_OFFLOAD_XFER_* in spi-offload.h. 1041 * @ptp_sts_word_pre: The word (subject to bits_per_word semantics) offset 1042 * within @tx_buf for which the SPI device is requesting that the time 1043 * snapshot for this transfer begins. Upon completing the SPI transfer, 1044 * this value may have changed compared to what was requested, depending 1045 * on the available snapshotting resolution (DMA transfer, 1046 * @ptp_sts_supported is false, etc). 1047 * @ptp_sts_word_post: See @ptp_sts_word_pre. The two can be equal (meaning 1048 * that a single byte should be snapshotted). 1049 * If the core takes care of the timestamp (if @ptp_sts_supported is false 1050 * for this controller), it will set @ptp_sts_word_pre to 0, and 1051 * @ptp_sts_word_post to the length of the transfer. This is done 1052 * purposefully (instead of setting to spi_transfer->len - 1) to denote 1053 * that a transfer-level snapshot taken from within the driver may still 1054 * be of higher quality. 1055 * @ptp_sts: Pointer to a memory location held by the SPI target device where a 1056 * PTP system timestamp structure may lie. If drivers use PIO or their 1057 * hardware has some sort of assist for retrieving exact transfer timing, 1058 * they can (and should) assert @ptp_sts_supported and populate this 1059 * structure using the ptp_read_system_*ts helper functions. 1060 * The timestamp must represent the time at which the SPI target device has 1061 * processed the word, i.e. the "pre" timestamp should be taken before 1062 * transmitting the "pre" word, and the "post" timestamp after receiving 1063 * transmit confirmation from the controller for the "post" word. 1064 * @dtr_mode: true if supports double transfer rate. 1065 * @timestamped: true if the transfer has been timestamped 1066 * @error: Error status logged by SPI controller driver. 1067 * 1068 * SPI transfers always write the same number of bytes as they read. 1069 * Protocol drivers should always provide @rx_buf and/or @tx_buf. 1070 * In some cases, they may also want to provide DMA addresses for 1071 * the data being transferred; that may reduce overhead, when the 1072 * underlying driver uses DMA. 1073 * 1074 * If the transmit buffer is NULL, zeroes will be shifted out 1075 * while filling @rx_buf. If the receive buffer is NULL, the data 1076 * shifted in will be discarded. Only "len" bytes shift out (or in). 1077 * It's an error to try to shift out a partial word. (For example, by 1078 * shifting out three bytes with word size of sixteen or twenty bits; 1079 * the former uses two bytes per word, the latter uses four bytes.) 1080 * 1081 * In-memory data values are always in native CPU byte order, translated 1082 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So 1083 * for example when bits_per_word is sixteen, buffers are 2N bytes long 1084 * (@len = 2N) and hold N sixteen bit words in CPU byte order. 1085 * 1086 * When the word size of the SPI transfer is not a power-of-two multiple 1087 * of eight bits, those in-memory words include extra bits. In-memory 1088 * words are always seen by protocol drivers as right-justified, so the 1089 * undefined (rx) or unused (tx) bits are always the most significant bits. 1090 * 1091 * All SPI transfers start with the relevant chipselect active. Normally 1092 * it stays selected until after the last transfer in a message. Drivers 1093 * can affect the chipselect signal using cs_change. 1094 * 1095 * (i) If the transfer isn't the last one in the message, this flag is 1096 * used to make the chipselect briefly go inactive in the middle of the 1097 * message. Toggling chipselect in this way may be needed to terminate 1098 * a chip command, letting a single spi_message perform all of group of 1099 * chip transactions together. 1100 * 1101 * (ii) When the transfer is the last one in the message, the chip may 1102 * stay selected until the next transfer. On multi-device SPI busses 1103 * with nothing blocking messages going to other devices, this is just 1104 * a performance hint; starting a message to another device deselects 1105 * this one. But in other cases, this can be used to ensure correctness. 1106 * Some devices need protocol transactions to be built from a series of 1107 * spi_message submissions, where the content of one message is determined 1108 * by the results of previous messages and where the whole transaction 1109 * ends when the chipselect goes inactive. 1110 * 1111 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information 1112 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these 1113 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x) 1114 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer. 1115 * 1116 * User may also set dtr_mode to true to use dual transfer mode if desired. if 1117 * not, default considered as single transfer mode. 1118 * 1119 * The code that submits an spi_message (and its spi_transfers) 1120 * to the lower layers is responsible for managing its memory. 1121 * Zero-initialize every field you don't set up explicitly, to 1122 * insulate against future API updates. After you submit a message 1123 * and its transfers, ignore them until its completion callback. 1124 */ 1125 struct spi_transfer { 1126 /* 1127 * It's okay if tx_buf == rx_buf (right?). 1128 * For MicroWire, one buffer must be NULL. 1129 * Buffers must work with dma_*map_single() calls. 1130 */ 1131 const void *tx_buf; 1132 void *rx_buf; 1133 unsigned len; 1134 1135 #define SPI_TRANS_FAIL_NO_START BIT(0) 1136 #define SPI_TRANS_FAIL_IO BIT(1) 1137 u16 error; 1138 1139 bool tx_sg_mapped; 1140 bool rx_sg_mapped; 1141 1142 struct sg_table tx_sg; 1143 struct sg_table rx_sg; 1144 dma_addr_t tx_dma; 1145 dma_addr_t rx_dma; 1146 1147 unsigned dummy_data:1; 1148 unsigned cs_off:1; 1149 unsigned cs_change:1; 1150 unsigned tx_nbits:4; 1151 unsigned rx_nbits:4; 1152 1153 #define SPI_MULTI_LANE_MODE_SINGLE 0 /* only use single lane */ 1154 #define SPI_MULTI_LANE_MODE_STRIPE 1 /* one data word per lane */ 1155 #define SPI_MULTI_LANE_MODE_MIRROR 2 /* same word sent on all lanes */ 1156 unsigned multi_lane_mode: 2; 1157 1158 unsigned timestamped:1; 1159 bool dtr_mode; 1160 #define SPI_NBITS_SINGLE 0x01 /* 1-bit transfer */ 1161 #define SPI_NBITS_DUAL 0x02 /* 2-bit transfer */ 1162 #define SPI_NBITS_QUAD 0x04 /* 4-bit transfer */ 1163 #define SPI_NBITS_OCTAL 0x08 /* 8-bit transfer */ 1164 u8 bits_per_word; 1165 struct spi_delay delay; 1166 struct spi_delay cs_change_delay; 1167 struct spi_delay word_delay; 1168 u32 speed_hz; 1169 1170 u32 effective_speed_hz; 1171 1172 /* Use %SPI_OFFLOAD_XFER_* from spi-offload.h */ 1173 unsigned int offload_flags; 1174 1175 unsigned int ptp_sts_word_pre; 1176 unsigned int ptp_sts_word_post; 1177 1178 struct ptp_system_timestamp *ptp_sts; 1179 1180 struct list_head transfer_list; 1181 }; 1182 1183 /** 1184 * struct spi_message - one multi-segment SPI transaction 1185 * @transfers: list of transfer segments in this transaction 1186 * @spi: SPI device to which the transaction is queued 1187 * @pre_optimized: peripheral driver pre-optimized the message 1188 * @optimized: the message is in the optimized state 1189 * @prepared: spi_prepare_message was called for the this message 1190 * @status: zero for success, else negative errno 1191 * @complete: called to report transaction completions 1192 * @context: the argument to complete() when it's called 1193 * @frame_length: the total number of bytes in the message 1194 * @actual_length: the total number of bytes that were transferred in all 1195 * successful segments 1196 * @queue: for use by whichever driver currently owns the message 1197 * @state: for use by whichever driver currently owns the message 1198 * @opt_state: for use by whichever driver currently owns the message 1199 * @resources: for resource management when the SPI message is processed 1200 * @offload: (optional) offload instance used by this message 1201 * 1202 * A @spi_message is used to execute an atomic sequence of data transfers, 1203 * each represented by a struct spi_transfer. The sequence is "atomic" 1204 * in the sense that no other spi_message may use that SPI bus until that 1205 * sequence completes. On some systems, many such sequences can execute as 1206 * a single programmed DMA transfer. On all systems, these messages are 1207 * queued, and might complete after transactions to other devices. Messages 1208 * sent to a given spi_device are always executed in FIFO order. 1209 * 1210 * The code that submits an spi_message (and its spi_transfers) 1211 * to the lower layers is responsible for managing its memory. 1212 * Zero-initialize every field you don't set up explicitly, to 1213 * insulate against future API updates. After you submit a message 1214 * and its transfers, ignore them until its completion callback. 1215 */ 1216 struct spi_message { 1217 struct list_head transfers; 1218 1219 struct spi_device *spi; 1220 1221 /* spi_optimize_message() was called for this message */ 1222 bool pre_optimized; 1223 /* __spi_optimize_message() was called for this message */ 1224 bool optimized; 1225 1226 /* spi_prepare_message() was called for this message */ 1227 bool prepared; 1228 1229 /* 1230 * REVISIT: we might want a flag affecting the behavior of the 1231 * last transfer ... allowing things like "read 16 bit length L" 1232 * immediately followed by "read L bytes". Basically imposing 1233 * a specific message scheduling algorithm. 1234 * 1235 * Some controller drivers (message-at-a-time queue processing) 1236 * could provide that as their default scheduling algorithm. But 1237 * others (with multi-message pipelines) could need a flag to 1238 * tell them about such special cases. 1239 */ 1240 1241 /* Completion is reported through a callback */ 1242 int status; 1243 void (*complete)(void *context); 1244 void *context; 1245 unsigned frame_length; 1246 unsigned actual_length; 1247 1248 /* 1249 * For optional use by whatever driver currently owns the 1250 * spi_message ... between calls to spi_async and then later 1251 * complete(), that's the spi_controller controller driver. 1252 */ 1253 struct list_head queue; 1254 void *state; 1255 /* 1256 * Optional state for use by controller driver between calls to 1257 * __spi_optimize_message() and __spi_unoptimize_message(). 1258 */ 1259 void *opt_state; 1260 1261 /* 1262 * Optional offload instance used by this message. This must be set 1263 * by the peripheral driver before calling spi_optimize_message(). 1264 */ 1265 struct spi_offload *offload; 1266 1267 /* List of spi_res resources when the SPI message is processed */ 1268 struct list_head resources; 1269 }; 1270 1271 static inline void spi_message_init_no_memset(struct spi_message *m) 1272 { 1273 INIT_LIST_HEAD(&m->transfers); 1274 INIT_LIST_HEAD(&m->resources); 1275 } 1276 1277 static inline void spi_message_init(struct spi_message *m) 1278 { 1279 memset(m, 0, sizeof *m); 1280 spi_message_init_no_memset(m); 1281 } 1282 1283 static inline void 1284 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m) 1285 { 1286 list_add_tail(&t->transfer_list, &m->transfers); 1287 } 1288 1289 static inline void 1290 spi_transfer_del(struct spi_transfer *t) 1291 { 1292 list_del(&t->transfer_list); 1293 } 1294 1295 static inline int 1296 spi_transfer_delay_exec(struct spi_transfer *t) 1297 { 1298 return spi_delay_exec(&t->delay, t); 1299 } 1300 1301 /** 1302 * spi_message_init_with_transfers - Initialize spi_message and append transfers 1303 * @m: spi_message to be initialized 1304 * @xfers: An array of SPI transfers 1305 * @num_xfers: Number of items in the xfer array 1306 * 1307 * This function initializes the given spi_message and adds each spi_transfer in 1308 * the given array to the message. 1309 */ 1310 static inline void 1311 spi_message_init_with_transfers(struct spi_message *m, 1312 struct spi_transfer *xfers, unsigned int num_xfers) 1313 { 1314 unsigned int i; 1315 1316 spi_message_init(m); 1317 for (i = 0; i < num_xfers; ++i) 1318 spi_message_add_tail(&xfers[i], m); 1319 } 1320 1321 /* 1322 * It's fine to embed message and transaction structures in other data 1323 * structures so long as you don't free them while they're in use. 1324 */ 1325 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags) 1326 { 1327 struct spi_message_with_transfers { 1328 struct spi_message m; 1329 struct spi_transfer t[]; 1330 } *mwt; 1331 unsigned i; 1332 1333 mwt = kzalloc_flex(*mwt, t, ntrans, flags); 1334 if (!mwt) 1335 return NULL; 1336 1337 spi_message_init_no_memset(&mwt->m); 1338 for (i = 0; i < ntrans; i++) 1339 spi_message_add_tail(&mwt->t[i], &mwt->m); 1340 1341 return &mwt->m; 1342 } 1343 1344 static inline void spi_message_free(struct spi_message *m) 1345 { 1346 kfree(m); 1347 } 1348 1349 extern int spi_optimize_message(struct spi_device *spi, struct spi_message *msg); 1350 extern void spi_unoptimize_message(struct spi_message *msg); 1351 extern int devm_spi_optimize_message(struct device *dev, struct spi_device *spi, 1352 struct spi_message *msg); 1353 1354 extern int spi_setup(struct spi_device *spi); 1355 extern int spi_async(struct spi_device *spi, struct spi_message *message); 1356 extern int spi_target_abort(struct spi_device *spi); 1357 1358 static inline size_t 1359 spi_max_message_size(struct spi_device *spi) 1360 { 1361 struct spi_controller *ctlr = spi->controller; 1362 1363 if (!ctlr->max_message_size) 1364 return SIZE_MAX; 1365 return ctlr->max_message_size(spi); 1366 } 1367 1368 static inline size_t 1369 spi_max_transfer_size(struct spi_device *spi) 1370 { 1371 struct spi_controller *ctlr = spi->controller; 1372 size_t tr_max = SIZE_MAX; 1373 size_t msg_max = spi_max_message_size(spi); 1374 1375 if (ctlr->max_transfer_size) 1376 tr_max = ctlr->max_transfer_size(spi); 1377 1378 /* Transfer size limit must not be greater than message size limit */ 1379 return min(tr_max, msg_max); 1380 } 1381 1382 /** 1383 * spi_is_bpw_supported - Check if bits per word is supported 1384 * @spi: SPI device 1385 * @bpw: Bits per word 1386 * 1387 * This function checks to see if the SPI controller supports @bpw. 1388 * 1389 * Returns: 1390 * True if @bpw is supported, false otherwise. 1391 */ 1392 static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw) 1393 { 1394 u32 bpw_mask = spi->controller->bits_per_word_mask; 1395 1396 if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw))) 1397 return true; 1398 1399 return false; 1400 } 1401 1402 /** 1403 * spi_bpw_to_bytes - Covert bits per word to bytes 1404 * @bpw: Bits per word 1405 * 1406 * This function converts the given @bpw to bytes. The result is always 1407 * power-of-two, e.g., 1408 * 1409 * =============== ================= 1410 * Input (in bits) Output (in bytes) 1411 * =============== ================= 1412 * 5 1 1413 * 9 2 1414 * 21 4 1415 * 37 8 1416 * =============== ================= 1417 * 1418 * It will return 0 for the 0 input. 1419 * 1420 * Returns: 1421 * Bytes for the given @bpw. 1422 */ 1423 static inline u32 spi_bpw_to_bytes(u32 bpw) 1424 { 1425 return roundup_pow_of_two(BITS_TO_BYTES(bpw)); 1426 } 1427 1428 /** 1429 * spi_controller_xfer_timeout - Compute a suitable timeout value 1430 * @ctlr: SPI device 1431 * @xfer: Transfer descriptor 1432 * 1433 * Compute a relevant timeout value for the given transfer. We derive the time 1434 * that it would take on a single data line and take twice this amount of time 1435 * with a minimum of 500ms to avoid false positives on loaded systems. 1436 * 1437 * Returns: Transfer timeout value in milliseconds. 1438 */ 1439 static inline unsigned int spi_controller_xfer_timeout(struct spi_controller *ctlr, 1440 struct spi_transfer *xfer) 1441 { 1442 return max(xfer->len * 8 * 2 / (xfer->speed_hz / 1000), 500U); 1443 } 1444 1445 /*---------------------------------------------------------------------------*/ 1446 1447 /* SPI transfer replacement methods which make use of spi_res */ 1448 1449 struct spi_replaced_transfers; 1450 typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr, 1451 struct spi_message *msg, 1452 struct spi_replaced_transfers *res); 1453 /** 1454 * struct spi_replaced_transfers - structure describing the spi_transfer 1455 * replacements that have occurred 1456 * so that they can get reverted 1457 * @release: some extra release code to get executed prior to 1458 * releasing this structure 1459 * @extradata: pointer to some extra data if requested or NULL 1460 * @replaced_transfers: transfers that have been replaced and which need 1461 * to get restored 1462 * @replaced_after: the transfer after which the @replaced_transfers 1463 * are to get re-inserted 1464 * @inserted: number of transfers inserted 1465 * @inserted_transfers: array of spi_transfers of array-size @inserted, 1466 * that have been replacing replaced_transfers 1467 * 1468 * Note: that @extradata will point to @inserted_transfers[@inserted] 1469 * if some extra allocation is requested, so alignment will be the same 1470 * as for spi_transfers. 1471 */ 1472 struct spi_replaced_transfers { 1473 spi_replaced_release_t release; 1474 void *extradata; 1475 struct list_head replaced_transfers; 1476 struct list_head *replaced_after; 1477 size_t inserted; 1478 struct spi_transfer inserted_transfers[]; 1479 }; 1480 1481 /*---------------------------------------------------------------------------*/ 1482 1483 /* SPI transfer transformation methods */ 1484 1485 extern int spi_split_transfers_maxsize(struct spi_controller *ctlr, 1486 struct spi_message *msg, 1487 size_t maxsize); 1488 extern int spi_split_transfers_maxwords(struct spi_controller *ctlr, 1489 struct spi_message *msg, 1490 size_t maxwords); 1491 1492 /*---------------------------------------------------------------------------*/ 1493 1494 /* 1495 * All these synchronous SPI transfer routines are utilities layered 1496 * over the core async transfer primitive. Here, "synchronous" means 1497 * they will sleep uninterruptibly until the async transfer completes. 1498 */ 1499 1500 extern int spi_sync(struct spi_device *spi, struct spi_message *message); 1501 extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message); 1502 extern int spi_bus_lock(struct spi_controller *ctlr); 1503 extern int spi_bus_unlock(struct spi_controller *ctlr); 1504 1505 /** 1506 * spi_sync_transfer - synchronous SPI data transfer 1507 * @spi: device with which data will be exchanged 1508 * @xfers: An array of spi_transfers 1509 * @num_xfers: Number of items in the xfer array 1510 * Context: can sleep 1511 * 1512 * Does a synchronous SPI data transfer of the given spi_transfer array. 1513 * 1514 * For more specific semantics see spi_sync(). 1515 * 1516 * Return: zero on success, else a negative error code. 1517 */ 1518 static inline int 1519 spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers, 1520 unsigned int num_xfers) 1521 { 1522 struct spi_message msg; 1523 1524 spi_message_init_with_transfers(&msg, xfers, num_xfers); 1525 1526 return spi_sync(spi, &msg); 1527 } 1528 1529 /** 1530 * spi_write - SPI synchronous write 1531 * @spi: device to which data will be written 1532 * @buf: data buffer 1533 * @len: data buffer size 1534 * Context: can sleep 1535 * 1536 * This function writes the buffer @buf. 1537 * Callable only from contexts that can sleep. 1538 * 1539 * Return: zero on success, else a negative error code. 1540 */ 1541 static inline int 1542 spi_write(struct spi_device *spi, const void *buf, size_t len) 1543 { 1544 struct spi_transfer t = { 1545 .tx_buf = buf, 1546 .len = len, 1547 }; 1548 1549 return spi_sync_transfer(spi, &t, 1); 1550 } 1551 1552 /** 1553 * spi_read - SPI synchronous read 1554 * @spi: device from which data will be read 1555 * @buf: data buffer 1556 * @len: data buffer size 1557 * Context: can sleep 1558 * 1559 * This function reads the buffer @buf. 1560 * Callable only from contexts that can sleep. 1561 * 1562 * Return: zero on success, else a negative error code. 1563 */ 1564 static inline int 1565 spi_read(struct spi_device *spi, void *buf, size_t len) 1566 { 1567 struct spi_transfer t = { 1568 .rx_buf = buf, 1569 .len = len, 1570 }; 1571 1572 return spi_sync_transfer(spi, &t, 1); 1573 } 1574 1575 /* This copies txbuf and rxbuf data; for small transfers only! */ 1576 extern int spi_write_then_read(struct spi_device *spi, 1577 const void *txbuf, unsigned n_tx, 1578 void *rxbuf, unsigned n_rx); 1579 1580 /** 1581 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read 1582 * @spi: device with which data will be exchanged 1583 * @cmd: command to be written before data is read back 1584 * Context: can sleep 1585 * 1586 * Callable only from contexts that can sleep. 1587 * 1588 * Return: the (unsigned) eight bit number returned by the 1589 * device, or else a negative error code. 1590 */ 1591 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd) 1592 { 1593 ssize_t status; 1594 u8 result; 1595 1596 status = spi_write_then_read(spi, &cmd, 1, &result, 1); 1597 1598 /* Return negative errno or unsigned value */ 1599 return (status < 0) ? status : result; 1600 } 1601 1602 /** 1603 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read 1604 * @spi: device with which data will be exchanged 1605 * @cmd: command to be written before data is read back 1606 * Context: can sleep 1607 * 1608 * The number is returned in wire-order, which is at least sometimes 1609 * big-endian. 1610 * 1611 * Callable only from contexts that can sleep. 1612 * 1613 * Return: the (unsigned) sixteen bit number returned by the 1614 * device, or else a negative error code. 1615 */ 1616 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) 1617 { 1618 ssize_t status; 1619 u16 result; 1620 1621 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1622 1623 /* Return negative errno or unsigned value */ 1624 return (status < 0) ? status : result; 1625 } 1626 1627 /** 1628 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read 1629 * @spi: device with which data will be exchanged 1630 * @cmd: command to be written before data is read back 1631 * Context: can sleep 1632 * 1633 * This function is similar to spi_w8r16, with the exception that it will 1634 * convert the read 16 bit data word from big-endian to native endianness. 1635 * 1636 * Callable only from contexts that can sleep. 1637 * 1638 * Return: the (unsigned) sixteen bit number returned by the device in CPU 1639 * endianness, or else a negative error code. 1640 */ 1641 static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd) 1642 1643 { 1644 ssize_t status; 1645 __be16 result; 1646 1647 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1648 if (status < 0) 1649 return status; 1650 1651 return be16_to_cpu(result); 1652 } 1653 1654 /*---------------------------------------------------------------------------*/ 1655 1656 /* 1657 * INTERFACE between board init code and SPI infrastructure. 1658 * 1659 * No SPI driver ever sees these SPI device table segments, but 1660 * it's how the SPI core (or adapters that get hotplugged) grows 1661 * the driver model tree. 1662 * 1663 * As a rule, SPI devices can't be probed. Instead, board init code 1664 * provides a table listing the devices which are present, with enough 1665 * information to bind and set up the device's driver. There's basic 1666 * support for non-static configurations too; enough to handle adding 1667 * parport adapters, or microcontrollers acting as USB-to-SPI bridges. 1668 */ 1669 1670 /** 1671 * struct spi_board_info - board-specific template for a SPI device 1672 * @modalias: Initializes spi_device.modalias; identifies the driver. 1673 * @platform_data: Initializes spi_device.platform_data; the particular 1674 * data stored there is driver-specific. 1675 * @swnode: Software node for the device. 1676 * @controller_data: Initializes spi_device.controller_data; some 1677 * controllers need hints about hardware setup, e.g. for DMA. 1678 * @irq: Initializes spi_device.irq; depends on how the board is wired. 1679 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits 1680 * from the chip datasheet and board-specific signal quality issues. 1681 * @bus_num: Identifies which spi_controller parents the spi_device; unused 1682 * by spi_new_device(), and otherwise depends on board wiring. 1683 * @chip_select: Initializes spi_device.chip_select; depends on how 1684 * the board is wired. 1685 * @mode: Initializes spi_device.mode; based on the chip datasheet, board 1686 * wiring (some devices support both 3WIRE and standard modes), and 1687 * possibly presence of an inverter in the chipselect path. 1688 * 1689 * When adding new SPI devices to the device tree, these structures serve 1690 * as a partial device template. They hold information which can't always 1691 * be determined by drivers. Information that probe() can establish (such 1692 * as the default transfer wordsize) is not included here. 1693 * 1694 * These structures are used in two places. Their primary role is to 1695 * be stored in tables of board-specific device descriptors, which are 1696 * declared early in board initialization and then used (much later) to 1697 * populate a controller's device tree after the that controller's driver 1698 * initializes. A secondary (and atypical) role is as a parameter to 1699 * spi_new_device() call, which happens after those controller drivers 1700 * are active in some dynamic board configuration models. 1701 */ 1702 struct spi_board_info { 1703 /* 1704 * The device name and module name are coupled, like platform_bus; 1705 * "modalias" is normally the driver name. 1706 * 1707 * platform_data goes to spi_device.dev.platform_data, 1708 * controller_data goes to spi_device.controller_data, 1709 * IRQ is copied too. 1710 */ 1711 char modalias[SPI_NAME_SIZE]; 1712 const void *platform_data; 1713 const struct software_node *swnode; 1714 void *controller_data; 1715 int irq; 1716 1717 /* Slower signaling on noisy or low voltage boards */ 1718 u32 max_speed_hz; 1719 1720 1721 /* 1722 * bus_num is board specific and matches the bus_num of some 1723 * spi_controller that will probably be registered later. 1724 * 1725 * chip_select reflects how this chip is wired to that controller; 1726 * it's less than num_chipselect. 1727 */ 1728 u16 bus_num; 1729 u16 chip_select; 1730 1731 /* 1732 * mode becomes spi_device.mode, and is essential for chips 1733 * where the default of SPI_CS_HIGH = 0 is wrong. 1734 */ 1735 u32 mode; 1736 1737 /* 1738 * ... may need additional spi_device chip config data here. 1739 * avoid stuff protocol drivers can set; but include stuff 1740 * needed to behave without being bound to a driver: 1741 * - quirks like clock rate mattering when not selected 1742 */ 1743 }; 1744 1745 #ifdef CONFIG_SPI 1746 extern int 1747 spi_register_board_info(struct spi_board_info const *info, unsigned n); 1748 #else 1749 /* Board init code may ignore whether SPI is configured or not */ 1750 static inline int 1751 spi_register_board_info(struct spi_board_info const *info, unsigned n) 1752 { return 0; } 1753 #endif 1754 1755 /* 1756 * If you're hotplugging an adapter with devices (parport, USB, etc) 1757 * use spi_new_device() to describe each device. You can also call 1758 * spi_unregister_device() to start making that device vanish, but 1759 * normally that would be handled by spi_unregister_controller(). 1760 * 1761 * You can also use spi_alloc_device() and spi_add_device() to use a two 1762 * stage registration sequence for each spi_device. This gives the caller 1763 * some more control over the spi_device structure before it is registered, 1764 * but requires that caller to initialize fields that would otherwise 1765 * be defined using the board info. 1766 */ 1767 extern struct spi_device * 1768 spi_alloc_device(struct spi_controller *ctlr); 1769 1770 extern int 1771 spi_add_device(struct spi_device *spi); 1772 1773 extern struct spi_device * 1774 spi_new_device(struct spi_controller *, struct spi_board_info *); 1775 1776 extern void spi_unregister_device(struct spi_device *spi); 1777 1778 extern const struct spi_device_id * 1779 spi_get_device_id(const struct spi_device *sdev); 1780 1781 extern const void * 1782 spi_get_device_match_data(const struct spi_device *sdev); 1783 1784 static inline bool 1785 spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer) 1786 { 1787 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers); 1788 } 1789 1790 #endif /* __LINUX_SPI_H */ 1791