1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ 8 #define __DISABLE_TRACE_MMIO__ 9 10 #include <linux/clk.h> 11 #include <linux/console.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/irq.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/pm_domain.h> 18 #include <linux/pm_opp.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/pm_wakeirq.h> 22 #include <linux/soc/qcom/geni-se.h> 23 #include <linux/serial.h> 24 #include <linux/serial_core.h> 25 #include <linux/slab.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <dt-bindings/interconnect/qcom,icc.h> 29 30 /* UART specific GENI registers */ 31 #define SE_UART_LOOPBACK_CFG 0x22c 32 #define SE_UART_IO_MACRO_CTRL 0x240 33 #define SE_UART_TX_TRANS_CFG 0x25c 34 #define SE_UART_TX_WORD_LEN 0x268 35 #define SE_UART_TX_STOP_BIT_LEN 0x26c 36 #define SE_UART_TX_TRANS_LEN 0x270 37 #define SE_UART_RX_TRANS_CFG 0x280 38 #define SE_UART_RX_WORD_LEN 0x28c 39 #define SE_UART_RX_STALE_CNT 0x294 40 #define SE_UART_TX_PARITY_CFG 0x2a4 41 #define SE_UART_RX_PARITY_CFG 0x2a8 42 #define SE_UART_MANUAL_RFR 0x2ac 43 44 /* SE_UART_TRANS_CFG */ 45 #define UART_TX_PAR_EN BIT(0) 46 #define UART_CTS_MASK BIT(1) 47 48 /* SE_UART_TX_STOP_BIT_LEN */ 49 #define TX_STOP_BIT_LEN_1 0 50 #define TX_STOP_BIT_LEN_2 2 51 52 /* SE_UART_RX_TRANS_CFG */ 53 #define UART_RX_PAR_EN BIT(4) 54 55 /* SE_UART_RX_WORD_LEN */ 56 #define RX_WORD_LEN_MASK GENMASK(9, 0) 57 58 /* SE_UART_RX_STALE_CNT */ 59 #define RX_STALE_CNT GENMASK(23, 0) 60 61 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ 62 #define PAR_CALC_EN BIT(0) 63 #define PAR_EVEN 0x00 64 #define PAR_ODD 0x01 65 #define PAR_SPACE 0x10 66 67 /* SE_UART_MANUAL_RFR register fields */ 68 #define UART_MANUAL_RFR_EN BIT(31) 69 #define UART_RFR_NOT_READY BIT(1) 70 #define UART_RFR_READY BIT(0) 71 72 /* UART M_CMD OP codes */ 73 #define UART_START_TX 0x1 74 /* UART S_CMD OP codes */ 75 #define UART_START_READ 0x1 76 #define UART_PARAM 0x1 77 #define UART_PARAM_RFR_OPEN BIT(7) 78 79 #define UART_OVERSAMPLING 32 80 #define STALE_TIMEOUT 16 81 #define DEFAULT_BITS_PER_CHAR 10 82 #define GENI_UART_CONS_PORTS 1 83 #define DEF_FIFO_DEPTH_WORDS 16 84 #define DEF_TX_WM 2 85 #define DEF_FIFO_WIDTH_BITS 32 86 #define UART_RX_WM 2 87 88 /* SE_UART_LOOPBACK_CFG */ 89 #define RX_TX_SORTED BIT(0) 90 #define CTS_RTS_SORTED BIT(1) 91 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) 92 93 /* UART pin swap value */ 94 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) 95 #define IO_MACRO_IO0_SEL 0x3 96 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) 97 #define IO_MACRO_IO2_IO3_SWAP 0x4640 98 99 /* We always configure 4 bytes per FIFO word */ 100 #define BYTES_PER_FIFO_WORD 4U 101 102 #define DMA_RX_BUF_SIZE 2048 103 104 static DEFINE_IDA(port_ida); 105 #define DOMAIN_IDX_POWER 0 106 #define DOMAIN_IDX_PERF 1 107 108 struct qcom_geni_device_data { 109 bool console; 110 enum geni_se_xfer_mode mode; 111 struct dev_pm_domain_attach_data pd_data; 112 int (*resources_init)(struct uart_port *uport); 113 int (*set_rate)(struct uart_port *uport, unsigned int baud); 114 int (*power_state)(struct uart_port *uport, bool state); 115 }; 116 117 struct qcom_geni_private_data { 118 /* NOTE: earlycon port will have NULL here */ 119 struct uart_driver *drv; 120 121 u32 poll_cached_bytes; 122 unsigned int poll_cached_bytes_cnt; 123 124 u32 write_cached_bytes; 125 unsigned int write_cached_bytes_cnt; 126 }; 127 128 struct qcom_geni_serial_port { 129 struct uart_port uport; 130 struct geni_se se; 131 const char *name; 132 u32 tx_fifo_depth; 133 u32 tx_fifo_width; 134 u32 rx_fifo_depth; 135 dma_addr_t tx_dma_addr; 136 dma_addr_t rx_dma_addr; 137 bool setup; 138 unsigned long poll_timeout_us; 139 unsigned long clk_rate; 140 void *rx_buf; 141 u32 loopback; 142 bool brk; 143 144 unsigned int tx_remaining; 145 unsigned int tx_queued; 146 int wakeup_irq; 147 bool rx_tx_swap; 148 bool cts_rts_swap; 149 bool manual_flow; 150 151 struct qcom_geni_private_data private_data; 152 const struct qcom_geni_device_data *dev_data; 153 struct dev_pm_domain_list *pd_list; 154 }; 155 156 static const struct uart_ops qcom_geni_console_pops; 157 static const struct uart_ops qcom_geni_uart_pops; 158 static struct uart_driver qcom_geni_console_driver; 159 static struct uart_driver qcom_geni_uart_driver; 160 161 static void __qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport); 162 static void qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport); 163 static int qcom_geni_serial_port_setup(struct uart_port *uport); 164 165 static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport) 166 { 167 return container_of(uport, struct qcom_geni_serial_port, uport); 168 } 169 170 static struct qcom_geni_serial_port qcom_geni_console_port = { 171 .uport = { 172 .iotype = UPIO_MEM, 173 .ops = &qcom_geni_console_pops, 174 .flags = UPF_BOOT_AUTOCONF, 175 .line = 0, 176 }, 177 }; 178 179 static const struct serial_rs485 qcom_geni_rs485_supported = { 180 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND | SER_RS485_RTS_ON_SEND, 181 }; 182 183 /** 184 * qcom_geni_set_rs485_mode - Set RTS pin state for RS485 mode 185 * @uport: UART port 186 * @flag: RS485 flag to determine RTS polarity 187 * 188 * Enables manual RTS control for RS485. Sets RTS to READY or NOT_READY 189 * based on the specified flag if RS485 mode is enabled. 190 */ 191 static void qcom_geni_set_rs485_mode(struct uart_port *uport, u32 flag) 192 { 193 if (!(uport->rs485.flags & SER_RS485_ENABLED)) 194 return; 195 196 u32 rfr = UART_MANUAL_RFR_EN; 197 198 if (uport->rs485.flags & flag) 199 rfr |= UART_RFR_NOT_READY; 200 else 201 rfr |= UART_RFR_READY; 202 203 writel(rfr, uport->membase + SE_UART_MANUAL_RFR); 204 } 205 206 static int qcom_geni_serial_request_port(struct uart_port *uport) 207 { 208 struct platform_device *pdev = to_platform_device(uport->dev); 209 struct qcom_geni_serial_port *port = to_dev_port(uport); 210 211 uport->membase = devm_platform_ioremap_resource(pdev, 0); 212 if (IS_ERR(uport->membase)) 213 return PTR_ERR(uport->membase); 214 port->se.base = uport->membase; 215 return 0; 216 } 217 218 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) 219 { 220 if (cfg_flags & UART_CONFIG_TYPE) { 221 uport->type = PORT_MSM; 222 qcom_geni_serial_request_port(uport); 223 } 224 } 225 226 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) 227 { 228 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; 229 u32 geni_ios; 230 231 if (uart_console(uport)) { 232 mctrl |= TIOCM_CTS; 233 } else { 234 geni_ios = readl(uport->membase + SE_GENI_IOS); 235 if (!(geni_ios & IO2_DATA_IN)) 236 mctrl |= TIOCM_CTS; 237 } 238 239 return mctrl; 240 } 241 242 static void qcom_geni_serial_set_mctrl(struct uart_port *uport, 243 unsigned int mctrl) 244 { 245 u32 uart_manual_rfr = 0; 246 struct qcom_geni_serial_port *port = to_dev_port(uport); 247 248 if (uart_console(uport)) 249 return; 250 251 if (mctrl & TIOCM_LOOP) 252 port->loopback = RX_TX_CTS_RTS_SORTED; 253 254 if (port->manual_flow && !(mctrl & TIOCM_RTS) && !uport->suspended) 255 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; 256 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); 257 } 258 259 static const char *qcom_geni_serial_get_type(struct uart_port *uport) 260 { 261 return "MSM"; 262 } 263 264 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console, struct device *dev) 265 { 266 struct qcom_geni_serial_port *port; 267 int nr_ports = console ? GENI_UART_CONS_PORTS : CONFIG_SERIAL_QCOM_GENI_UART_PORTS; 268 269 if (console) { 270 if (line < 0 || line >= nr_ports) 271 return ERR_PTR(-ENXIO); 272 273 port = &qcom_geni_console_port; 274 } else { 275 int max_alias_num = of_alias_get_highest_id("serial"); 276 277 if (line < 0 || line >= nr_ports) 278 line = ida_alloc_range(&port_ida, max_alias_num + 1, 279 nr_ports - 1, GFP_KERNEL); 280 else 281 line = ida_alloc_range(&port_ida, line, 282 nr_ports - 1, GFP_KERNEL); 283 284 if (line < 0) 285 return ERR_PTR(-ENXIO); 286 287 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 288 if (!port) 289 return ERR_PTR(-ENOMEM); 290 291 port->uport.iotype = UPIO_MEM; 292 port->uport.ops = &qcom_geni_uart_pops; 293 port->uport.flags = UPF_BOOT_AUTOCONF; 294 port->uport.line = line; 295 } 296 return port; 297 } 298 299 static bool qcom_geni_serial_main_active(struct uart_port *uport) 300 { 301 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; 302 } 303 304 static bool qcom_geni_serial_secondary_active(struct uart_port *uport) 305 { 306 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; 307 } 308 309 static bool qcom_geni_serial_poll_bitfield(struct uart_port *uport, 310 unsigned int offset, u32 field, u32 val) 311 { 312 u32 reg; 313 struct qcom_geni_serial_port *port; 314 unsigned long timeout_us = 20000; 315 struct qcom_geni_private_data *private_data = uport->private_data; 316 317 if (private_data->drv) { 318 port = to_dev_port(uport); 319 if (port->poll_timeout_us) 320 timeout_us = port->poll_timeout_us; 321 } 322 323 /* 324 * Use custom implementation instead of readl_poll_atomic since ktimer 325 * is not ready at the time of early console. 326 */ 327 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 328 while (timeout_us) { 329 reg = readl(uport->membase + offset); 330 if ((reg & field) == val) 331 return true; 332 udelay(10); 333 timeout_us -= 10; 334 } 335 return false; 336 } 337 338 static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 339 unsigned int offset, u32 field, bool set) 340 { 341 return qcom_geni_serial_poll_bitfield(uport, offset, field, set ? field : 0); 342 } 343 344 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) 345 { 346 u32 m_cmd; 347 348 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); 349 m_cmd = UART_START_TX << M_OPCODE_SHFT; 350 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); 351 } 352 353 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) 354 { 355 int done; 356 357 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 358 M_CMD_DONE_EN, true); 359 if (!done) { 360 writel(M_GENI_CMD_ABORT, uport->membase + 361 SE_GENI_M_CMD_CTRL_REG); 362 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 363 M_CMD_ABORT_EN, true); 364 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 365 } 366 } 367 368 static void qcom_geni_serial_abort_rx(struct uart_port *uport) 369 { 370 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; 371 372 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); 373 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 374 S_GENI_CMD_ABORT, false); 375 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 376 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); 377 } 378 379 #ifdef CONFIG_CONSOLE_POLL 380 static int qcom_geni_serial_get_char(struct uart_port *uport) 381 { 382 struct qcom_geni_private_data *private_data = uport->private_data; 383 u32 status; 384 u32 word_cnt; 385 int ret; 386 387 if (!private_data->poll_cached_bytes_cnt) { 388 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 389 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); 390 391 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 392 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); 393 394 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 395 word_cnt = status & RX_FIFO_WC_MSK; 396 if (!word_cnt) 397 return NO_POLL_CHAR; 398 399 if (word_cnt == 1 && (status & RX_LAST)) 400 /* 401 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be 402 * treated as if it was BYTES_PER_FIFO_WORD. 403 */ 404 private_data->poll_cached_bytes_cnt = 405 (status & RX_LAST_BYTE_VALID_MSK) >> 406 RX_LAST_BYTE_VALID_SHFT; 407 408 if (private_data->poll_cached_bytes_cnt == 0) 409 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; 410 411 private_data->poll_cached_bytes = 412 readl(uport->membase + SE_GENI_RX_FIFOn); 413 } 414 415 private_data->poll_cached_bytes_cnt--; 416 ret = private_data->poll_cached_bytes & 0xff; 417 private_data->poll_cached_bytes >>= 8; 418 419 return ret; 420 } 421 422 static void qcom_geni_serial_poll_put_char(struct uart_port *uport, 423 unsigned char c) 424 { 425 if (qcom_geni_serial_main_active(uport)) { 426 qcom_geni_serial_poll_tx_done(uport); 427 __qcom_geni_serial_cancel_tx_cmd(uport); 428 } 429 430 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 431 qcom_geni_serial_setup_tx(uport, 1); 432 writel(c, uport->membase + SE_GENI_TX_FIFOn); 433 qcom_geni_serial_poll_tx_done(uport); 434 } 435 436 static int qcom_geni_serial_poll_init(struct uart_port *uport) 437 { 438 struct qcom_geni_serial_port *port = to_dev_port(uport); 439 int ret; 440 441 if (!port->setup) { 442 ret = qcom_geni_serial_port_setup(uport); 443 if (ret) 444 return ret; 445 } 446 447 if (!qcom_geni_serial_secondary_active(uport)) 448 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 449 450 return 0; 451 } 452 #endif 453 454 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 455 static void qcom_geni_serial_drain_fifo(struct uart_port *uport) 456 { 457 struct qcom_geni_serial_port *port = to_dev_port(uport); 458 459 qcom_geni_serial_poll_bitfield(uport, SE_GENI_M_GP_LENGTH, GP_LENGTH, 460 port->tx_queued); 461 } 462 463 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch) 464 { 465 struct qcom_geni_private_data *private_data = uport->private_data; 466 467 private_data->write_cached_bytes = 468 (private_data->write_cached_bytes >> 8) | (ch << 24); 469 private_data->write_cached_bytes_cnt++; 470 471 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { 472 writel(private_data->write_cached_bytes, 473 uport->membase + SE_GENI_TX_FIFOn); 474 private_data->write_cached_bytes_cnt = 0; 475 } 476 } 477 478 static void 479 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, 480 unsigned int count) 481 { 482 struct qcom_geni_private_data *private_data = uport->private_data; 483 484 int i; 485 u32 bytes_to_send = count; 486 487 for (i = 0; i < count; i++) { 488 /* 489 * uart_console_write() adds a carriage return for each newline. 490 * Account for additional bytes to be written. 491 */ 492 if (s[i] == '\n') 493 bytes_to_send++; 494 } 495 496 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 497 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 498 qcom_geni_serial_setup_tx(uport, bytes_to_send); 499 for (i = 0; i < count; ) { 500 size_t chars_to_write = 0; 501 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; 502 503 /* 504 * If the WM bit never set, then the Tx state machine is not 505 * in a valid state, so break, cancel/abort any existing 506 * command. Unfortunately the current data being written is 507 * lost. 508 */ 509 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 510 M_TX_FIFO_WATERMARK_EN, true)) 511 break; 512 chars_to_write = min_t(size_t, count - i, avail / 2); 513 uart_console_write(uport, s + i, chars_to_write, 514 qcom_geni_serial_wr_char); 515 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + 516 SE_GENI_M_IRQ_CLEAR); 517 i += chars_to_write; 518 } 519 520 if (private_data->write_cached_bytes_cnt) { 521 private_data->write_cached_bytes >>= BITS_PER_BYTE * 522 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); 523 writel(private_data->write_cached_bytes, 524 uport->membase + SE_GENI_TX_FIFOn); 525 private_data->write_cached_bytes_cnt = 0; 526 } 527 528 qcom_geni_serial_poll_tx_done(uport); 529 } 530 531 static void qcom_geni_serial_console_write(struct console *co, const char *s, 532 unsigned int count) 533 { 534 struct uart_port *uport; 535 struct qcom_geni_serial_port *port; 536 u32 m_irq_en, s_irq_en; 537 bool locked = true; 538 unsigned long flags; 539 540 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); 541 542 port = get_port_from_line(co->index, true, NULL); 543 if (IS_ERR(port)) 544 return; 545 546 uport = &port->uport; 547 if (oops_in_progress) 548 locked = uart_port_trylock_irqsave(uport, &flags); 549 else 550 uart_port_lock_irqsave(uport, &flags); 551 552 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 553 s_irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 554 writel(0, uport->membase + SE_GENI_M_IRQ_EN); 555 writel(0, uport->membase + SE_GENI_S_IRQ_EN); 556 557 if (qcom_geni_serial_main_active(uport)) { 558 /* Wait for completion or drain FIFO */ 559 if (!locked || port->tx_remaining == 0) 560 qcom_geni_serial_poll_tx_done(uport); 561 else 562 qcom_geni_serial_drain_fifo(uport); 563 564 qcom_geni_serial_cancel_tx_cmd(uport); 565 } 566 567 __qcom_geni_serial_console_write(uport, s, count); 568 569 writel(m_irq_en, uport->membase + SE_GENI_M_IRQ_EN); 570 writel(s_irq_en, uport->membase + SE_GENI_S_IRQ_EN); 571 572 if (locked) 573 uart_port_unlock_irqrestore(uport, flags); 574 } 575 576 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 577 { 578 u32 i; 579 unsigned char buf[sizeof(u32)]; 580 struct tty_port *tport; 581 struct qcom_geni_serial_port *port = to_dev_port(uport); 582 583 tport = &uport->state->port; 584 for (i = 0; i < bytes; ) { 585 int c; 586 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); 587 588 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); 589 i += chunk; 590 if (drop) 591 continue; 592 593 for (c = 0; c < chunk; c++) { 594 int sysrq; 595 596 uport->icount.rx++; 597 if (port->brk && buf[c] == 0) { 598 port->brk = false; 599 if (uart_handle_break(uport)) 600 continue; 601 } 602 603 sysrq = uart_prepare_sysrq_char(uport, buf[c]); 604 605 if (!sysrq) 606 tty_insert_flip_char(tport, buf[c], TTY_NORMAL); 607 } 608 } 609 if (!drop) 610 tty_flip_buffer_push(tport); 611 } 612 #else 613 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 614 { 615 616 } 617 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 618 619 static void handle_rx_uart(struct uart_port *uport, u32 bytes) 620 { 621 struct qcom_geni_serial_port *port = to_dev_port(uport); 622 struct tty_port *tport = &uport->state->port; 623 int ret; 624 625 ret = tty_insert_flip_string(tport, port->rx_buf, bytes); 626 if (ret != bytes) { 627 dev_err_ratelimited(uport->dev, "failed to push data (%d < %u)\n", 628 ret, bytes); 629 } 630 uport->icount.rx += ret; 631 tty_flip_buffer_push(tport); 632 } 633 634 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) 635 { 636 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 637 } 638 639 static void qcom_geni_serial_stop_tx_dma(struct uart_port *uport) 640 { 641 struct qcom_geni_serial_port *port = to_dev_port(uport); 642 bool done; 643 644 if (!qcom_geni_serial_main_active(uport)) 645 return; 646 647 if (port->tx_dma_addr) { 648 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, 649 port->tx_remaining); 650 port->tx_dma_addr = 0; 651 port->tx_remaining = 0; 652 } 653 654 geni_se_cancel_m_cmd(&port->se); 655 656 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 657 M_CMD_CANCEL_EN, true); 658 if (!done) { 659 geni_se_abort_m_cmd(&port->se); 660 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 661 M_CMD_ABORT_EN, true); 662 if (!done) 663 dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set"); 664 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 665 } 666 667 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 668 } 669 670 static void qcom_geni_serial_start_tx_dma(struct uart_port *uport) 671 { 672 struct qcom_geni_serial_port *port = to_dev_port(uport); 673 struct tty_port *tport = &uport->state->port; 674 unsigned int xmit_size; 675 u8 *tail; 676 int ret; 677 678 if (port->tx_dma_addr) 679 return; 680 681 if (kfifo_is_empty(&tport->xmit_fifo)) 682 return; 683 684 xmit_size = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, 685 UART_XMIT_SIZE); 686 687 qcom_geni_set_rs485_mode(uport, SER_RS485_RTS_ON_SEND); 688 689 qcom_geni_serial_setup_tx(uport, xmit_size); 690 691 ret = geni_se_tx_dma_prep(&port->se, tail, xmit_size, 692 &port->tx_dma_addr); 693 if (ret) { 694 dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret); 695 qcom_geni_serial_stop_tx_dma(uport); 696 return; 697 } 698 699 port->tx_remaining = xmit_size; 700 } 701 702 static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport) 703 { 704 unsigned char c; 705 u32 irq_en; 706 707 /* 708 * Start a new transfer in case the previous command was cancelled and 709 * left data in the FIFO which may prevent the watermark interrupt 710 * from triggering. Note that the stale data is discarded. 711 */ 712 if (!qcom_geni_serial_main_active(uport) && 713 !qcom_geni_serial_tx_empty(uport)) { 714 if (uart_fifo_out(uport, &c, 1) == 1) { 715 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 716 qcom_geni_serial_setup_tx(uport, 1); 717 writel(c, uport->membase + SE_GENI_TX_FIFOn); 718 } 719 } 720 721 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 722 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; 723 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 724 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 725 } 726 727 static void qcom_geni_serial_stop_tx_fifo(struct uart_port *uport) 728 { 729 u32 irq_en; 730 731 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 732 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 733 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); 734 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 735 } 736 737 static void __qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport) 738 { 739 struct qcom_geni_serial_port *port = to_dev_port(uport); 740 741 geni_se_cancel_m_cmd(&port->se); 742 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 743 M_CMD_CANCEL_EN, true)) { 744 geni_se_abort_m_cmd(&port->se); 745 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 746 M_CMD_ABORT_EN, true); 747 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 748 } 749 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 750 } 751 752 static void qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport) 753 { 754 struct qcom_geni_serial_port *port = to_dev_port(uport); 755 756 if (!qcom_geni_serial_main_active(uport)) 757 return; 758 759 __qcom_geni_serial_cancel_tx_cmd(uport); 760 761 port->tx_remaining = 0; 762 port->tx_queued = 0; 763 } 764 765 static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop) 766 { 767 u32 status; 768 u32 word_cnt; 769 u32 last_word_byte_cnt; 770 u32 last_word_partial; 771 u32 total_bytes; 772 773 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 774 word_cnt = status & RX_FIFO_WC_MSK; 775 last_word_partial = status & RX_LAST; 776 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> 777 RX_LAST_BYTE_VALID_SHFT; 778 779 if (!word_cnt) 780 return; 781 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); 782 if (last_word_partial && last_word_byte_cnt) 783 total_bytes += last_word_byte_cnt; 784 else 785 total_bytes += BYTES_PER_FIFO_WORD; 786 handle_rx_console(uport, total_bytes, drop); 787 } 788 789 static void qcom_geni_serial_stop_rx_fifo(struct uart_port *uport) 790 { 791 u32 irq_en; 792 struct qcom_geni_serial_port *port = to_dev_port(uport); 793 u32 s_irq_status; 794 795 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 796 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 797 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 798 799 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 800 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 801 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 802 803 if (!qcom_geni_serial_secondary_active(uport)) 804 return; 805 806 geni_se_cancel_s_cmd(&port->se); 807 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 808 S_CMD_CANCEL_EN, true); 809 /* 810 * If timeout occurs secondary engine remains active 811 * and Abort sequence is executed. 812 */ 813 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 814 /* Flush the Rx buffer */ 815 if (s_irq_status & S_RX_FIFO_LAST_EN) 816 qcom_geni_serial_handle_rx_fifo(uport, true); 817 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 818 819 if (qcom_geni_serial_secondary_active(uport)) 820 qcom_geni_serial_abort_rx(uport); 821 } 822 823 static void qcom_geni_serial_start_rx_fifo(struct uart_port *uport) 824 { 825 u32 irq_en; 826 struct qcom_geni_serial_port *port = to_dev_port(uport); 827 828 if (qcom_geni_serial_secondary_active(uport)) 829 qcom_geni_serial_stop_rx_fifo(uport); 830 831 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 832 833 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 834 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; 835 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 836 837 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 838 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 839 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 840 } 841 842 static void qcom_geni_serial_stop_rx_dma(struct uart_port *uport) 843 { 844 struct qcom_geni_serial_port *port = to_dev_port(uport); 845 bool done; 846 847 if (!qcom_geni_serial_secondary_active(uport)) 848 return; 849 850 geni_se_cancel_s_cmd(&port->se); 851 done = qcom_geni_serial_poll_bit(uport, SE_DMA_RX_IRQ_STAT, 852 RX_EOT, true); 853 if (done) { 854 writel(RX_EOT | RX_DMA_DONE, 855 uport->membase + SE_DMA_RX_IRQ_CLR); 856 } else { 857 qcom_geni_serial_abort_rx(uport); 858 859 writel(1, uport->membase + SE_DMA_RX_FSM_RST); 860 qcom_geni_serial_poll_bit(uport, SE_DMA_RX_IRQ_STAT, 861 RX_RESET_DONE, true); 862 writel(RX_RESET_DONE | RX_DMA_DONE, 863 uport->membase + SE_DMA_RX_IRQ_CLR); 864 } 865 866 if (port->rx_dma_addr) { 867 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, 868 DMA_RX_BUF_SIZE); 869 port->rx_dma_addr = 0; 870 } 871 } 872 873 static void qcom_geni_serial_start_rx_dma(struct uart_port *uport) 874 { 875 struct qcom_geni_serial_port *port = to_dev_port(uport); 876 int ret; 877 878 if (qcom_geni_serial_secondary_active(uport)) 879 qcom_geni_serial_stop_rx_dma(uport); 880 881 geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN); 882 883 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 884 DMA_RX_BUF_SIZE, 885 &port->rx_dma_addr); 886 if (ret) { 887 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); 888 qcom_geni_serial_stop_rx_dma(uport); 889 } 890 } 891 892 static void qcom_geni_serial_handle_rx_dma(struct uart_port *uport, bool drop) 893 { 894 struct qcom_geni_serial_port *port = to_dev_port(uport); 895 u32 rx_in; 896 int ret; 897 898 if (!qcom_geni_serial_secondary_active(uport)) 899 return; 900 901 if (!port->rx_dma_addr) 902 return; 903 904 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE); 905 port->rx_dma_addr = 0; 906 907 rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN); 908 if (!rx_in) 909 dev_warn_ratelimited(uport->dev, "serial engine reports 0 RX bytes in!\n"); 910 else if (!drop) 911 handle_rx_uart(uport, rx_in); 912 913 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 914 DMA_RX_BUF_SIZE, 915 &port->rx_dma_addr); 916 if (ret) { 917 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); 918 qcom_geni_serial_stop_rx_dma(uport); 919 } 920 } 921 922 static void qcom_geni_serial_start_rx(struct uart_port *uport) 923 { 924 uport->ops->start_rx(uport); 925 } 926 927 static void qcom_geni_serial_stop_rx(struct uart_port *uport) 928 { 929 uport->ops->stop_rx(uport); 930 } 931 932 static void qcom_geni_serial_stop_tx(struct uart_port *uport) 933 { 934 uport->ops->stop_tx(uport); 935 } 936 937 static void qcom_geni_serial_send_chunk_fifo(struct uart_port *uport, 938 unsigned int chunk) 939 { 940 struct qcom_geni_serial_port *port = to_dev_port(uport); 941 unsigned int tx_bytes, remaining = chunk; 942 u8 buf[BYTES_PER_FIFO_WORD]; 943 944 while (remaining) { 945 memset(buf, 0, sizeof(buf)); 946 tx_bytes = min(remaining, BYTES_PER_FIFO_WORD); 947 948 uart_fifo_out(uport, buf, tx_bytes); 949 950 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); 951 952 remaining -= tx_bytes; 953 port->tx_remaining -= tx_bytes; 954 } 955 } 956 957 static void qcom_geni_serial_handle_tx_fifo(struct uart_port *uport, 958 bool done, bool active) 959 { 960 struct qcom_geni_serial_port *port = to_dev_port(uport); 961 struct tty_port *tport = &uport->state->port; 962 size_t avail; 963 size_t pending; 964 u32 status; 965 u32 irq_en; 966 unsigned int chunk; 967 968 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 969 970 /* Complete the current tx command before taking newly added data */ 971 if (active) 972 pending = port->tx_remaining; 973 else 974 pending = kfifo_len(&tport->xmit_fifo); 975 976 /* All data has been transmitted or command has been cancelled */ 977 if (!pending && done) { 978 qcom_geni_serial_stop_tx_fifo(uport); 979 goto out_write_wakeup; 980 } 981 982 if (active) 983 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); 984 else 985 avail = port->tx_fifo_depth; 986 987 avail *= BYTES_PER_FIFO_WORD; 988 989 chunk = min(avail, pending); 990 if (!chunk) 991 goto out_write_wakeup; 992 993 if (!active) { 994 qcom_geni_serial_setup_tx(uport, pending); 995 port->tx_remaining = pending; 996 port->tx_queued = 0; 997 998 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 999 if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) 1000 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 1001 uport->membase + SE_GENI_M_IRQ_EN); 1002 } 1003 1004 qcom_geni_serial_send_chunk_fifo(uport, chunk); 1005 port->tx_queued += chunk; 1006 1007 /* 1008 * The tx fifo watermark is level triggered and latched. Though we had 1009 * cleared it in qcom_geni_serial_isr it will have already reasserted 1010 * so we must clear it again here after our writes. 1011 */ 1012 writel(M_TX_FIFO_WATERMARK_EN, 1013 uport->membase + SE_GENI_M_IRQ_CLEAR); 1014 1015 out_write_wakeup: 1016 if (!port->tx_remaining) { 1017 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 1018 if (irq_en & M_TX_FIFO_WATERMARK_EN) 1019 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN, 1020 uport->membase + SE_GENI_M_IRQ_EN); 1021 } 1022 1023 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1024 uart_write_wakeup(uport); 1025 } 1026 1027 static void qcom_geni_serial_handle_tx_dma(struct uart_port *uport) 1028 { 1029 struct qcom_geni_serial_port *port = to_dev_port(uport); 1030 struct tty_port *tport = &uport->state->port; 1031 unsigned int fifo_len = kfifo_len(&tport->xmit_fifo); 1032 1033 /* 1034 * Only advance the kfifo if it still contains the bytes that were 1035 * transferred. uart_flush_buffer() may have run before this IRQ 1036 * fired: it calls kfifo_reset() under the port lock, making 1037 * fifo_len = 0 while tx_remaining remains non-zero. Calling 1038 * uart_xmit_advance() in that case would underflow kfifo->out past 1039 * kfifo->in, making kfifo_len() wrap to UART_XMIT_SIZE - tx_remaining 1040 * and triggering a spurious large DMA transfer of stale data. 1041 */ 1042 if (fifo_len >= port->tx_remaining) 1043 uart_xmit_advance(uport, port->tx_remaining); 1044 1045 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining); 1046 port->tx_dma_addr = 0; 1047 port->tx_remaining = 0; 1048 1049 if (!kfifo_is_empty(&tport->xmit_fifo)) 1050 qcom_geni_serial_start_tx_dma(uport); 1051 1052 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1053 uart_write_wakeup(uport); 1054 } 1055 1056 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) 1057 { 1058 u32 m_irq_en; 1059 u32 m_irq_status; 1060 u32 s_irq_status; 1061 u32 geni_status; 1062 u32 dma; 1063 u32 dma_tx_status; 1064 u32 dma_rx_status; 1065 struct uart_port *uport = dev; 1066 bool drop_rx = false; 1067 struct tty_port *tport = &uport->state->port; 1068 struct qcom_geni_serial_port *port = to_dev_port(uport); 1069 1070 if (uport->suspended) 1071 return IRQ_NONE; 1072 1073 uart_port_lock(uport); 1074 1075 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 1076 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 1077 dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT); 1078 dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT); 1079 geni_status = readl(uport->membase + SE_GENI_STATUS); 1080 dma = readl(uport->membase + SE_GENI_DMA_MODE_EN); 1081 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 1082 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); 1083 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 1084 writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR); 1085 writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR); 1086 1087 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) 1088 goto out_unlock; 1089 1090 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { 1091 uport->icount.overrun++; 1092 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1093 } 1094 1095 if (s_irq_status & (S_GP_IRQ_0_EN | S_GP_IRQ_1_EN)) { 1096 if (s_irq_status & S_GP_IRQ_0_EN) 1097 uport->icount.parity++; 1098 drop_rx = true; 1099 } else if (s_irq_status & (S_GP_IRQ_2_EN | S_GP_IRQ_3_EN)) { 1100 uport->icount.brk++; 1101 port->brk = true; 1102 } 1103 1104 if (dma) { 1105 if (dma_tx_status & TX_DMA_DONE) { 1106 qcom_geni_serial_handle_tx_dma(uport); 1107 qcom_geni_set_rs485_mode(uport, SER_RS485_RTS_AFTER_SEND); 1108 } 1109 1110 if (dma_rx_status) { 1111 if (dma_rx_status & RX_RESET_DONE) 1112 goto out_unlock; 1113 1114 if (dma_rx_status & RX_DMA_PARITY_ERR) { 1115 uport->icount.parity++; 1116 drop_rx = true; 1117 } 1118 1119 if (dma_rx_status & RX_DMA_BREAK) 1120 uport->icount.brk++; 1121 1122 if (dma_rx_status & (RX_DMA_DONE | RX_EOT)) 1123 qcom_geni_serial_handle_rx_dma(uport, drop_rx); 1124 } 1125 } else { 1126 if (m_irq_status & m_irq_en & 1127 (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) 1128 qcom_geni_serial_handle_tx_fifo(uport, 1129 m_irq_status & M_CMD_DONE_EN, 1130 geni_status & M_GENI_CMD_ACTIVE); 1131 1132 if (s_irq_status & (S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN)) 1133 qcom_geni_serial_handle_rx_fifo(uport, drop_rx); 1134 } 1135 1136 out_unlock: 1137 uart_unlock_and_check_sysrq(uport); 1138 1139 return IRQ_HANDLED; 1140 } 1141 1142 static int setup_fifos(struct qcom_geni_serial_port *port) 1143 { 1144 struct uart_port *uport; 1145 u32 old_rx_fifo_depth = port->rx_fifo_depth; 1146 1147 uport = &port->uport; 1148 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); 1149 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); 1150 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); 1151 uport->fifosize = 1152 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; 1153 1154 if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) { 1155 /* 1156 * Use krealloc rather than krealloc_array because rx_buf is 1157 * accessed as 1 byte entries as well as 4 byte entries so it's 1158 * not necessarily an array. 1159 */ 1160 port->rx_buf = devm_krealloc(uport->dev, port->rx_buf, 1161 port->rx_fifo_depth * sizeof(u32), 1162 GFP_KERNEL); 1163 if (!port->rx_buf) 1164 return -ENOMEM; 1165 } 1166 1167 return 0; 1168 } 1169 1170 1171 static void qcom_geni_serial_shutdown(struct uart_port *uport) 1172 { 1173 disable_irq(uport->irq); 1174 1175 uart_port_lock_irq(uport); 1176 qcom_geni_serial_stop_tx(uport); 1177 qcom_geni_serial_stop_rx(uport); 1178 1179 qcom_geni_serial_cancel_tx_cmd(uport); 1180 uart_port_unlock_irq(uport); 1181 } 1182 1183 static void qcom_geni_serial_flush_buffer(struct uart_port *uport) 1184 { 1185 qcom_geni_serial_cancel_tx_cmd(uport); 1186 } 1187 1188 static int qcom_geni_serial_port_setup(struct uart_port *uport) 1189 { 1190 struct qcom_geni_serial_port *port = to_dev_port(uport); 1191 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; 1192 u32 proto; 1193 u32 pin_swap; 1194 int ret; 1195 1196 proto = geni_se_read_proto(&port->se); 1197 if (proto == GENI_SE_INVALID_PROTO) { 1198 ret = geni_load_se_firmware(&port->se, GENI_SE_UART); 1199 if (ret) { 1200 dev_err(uport->dev, "UART firmware load failed ret: %d\n", ret); 1201 return ret; 1202 } 1203 } else if (proto != GENI_SE_UART) { 1204 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); 1205 return -ENXIO; 1206 } 1207 1208 qcom_geni_serial_stop_rx(uport); 1209 1210 ret = setup_fifos(port); 1211 if (ret) 1212 return ret; 1213 1214 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); 1215 1216 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); 1217 if (port->rx_tx_swap) { 1218 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK; 1219 pin_swap |= IO_MACRO_IO2_IO3_SWAP; 1220 } 1221 if (port->cts_rts_swap) { 1222 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK; 1223 pin_swap |= IO_MACRO_IO0_SEL; 1224 } 1225 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ 1226 if (port->rx_tx_swap || port->cts_rts_swap) 1227 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); 1228 1229 /* 1230 * Make an unconditional cancel on the main sequencer to reset 1231 * it else we could end up in data loss scenarios. 1232 */ 1233 if (uart_console(uport)) 1234 qcom_geni_serial_poll_tx_done(uport); 1235 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1236 false, true, true); 1237 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); 1238 geni_se_select_mode(&port->se, port->dev_data->mode); 1239 port->setup = true; 1240 1241 return 0; 1242 } 1243 1244 static int qcom_geni_serial_startup(struct uart_port *uport) 1245 { 1246 int ret; 1247 struct qcom_geni_serial_port *port = to_dev_port(uport); 1248 1249 if (!port->setup) { 1250 ret = qcom_geni_serial_port_setup(uport); 1251 if (ret) 1252 return ret; 1253 } 1254 1255 uart_port_lock_irq(uport); 1256 qcom_geni_serial_start_rx(uport); 1257 uart_port_unlock_irq(uport); 1258 1259 enable_irq(uport->irq); 1260 1261 return 0; 1262 } 1263 1264 static int geni_serial_set_rate(struct uart_port *uport, unsigned int baud) 1265 { 1266 struct qcom_geni_serial_port *port = to_dev_port(uport); 1267 unsigned long clk_rate; 1268 unsigned int avg_bw_core, clk_idx; 1269 unsigned int clk_div; 1270 u32 ver, sampling_rate; 1271 u32 ser_clk_cfg; 1272 int ret; 1273 1274 sampling_rate = UART_OVERSAMPLING; 1275 /* Sampling rate is halved for IP versions >= 2.5 */ 1276 ver = geni_se_get_qup_hw_version(&port->se); 1277 if (ver >= QUP_SE_VERSION_2_5) 1278 sampling_rate /= 2; 1279 1280 ret = geni_se_clk_freq_match(&port->se, baud * sampling_rate, &clk_idx, &clk_rate, false); 1281 if (ret) { 1282 dev_err(port->se.dev, "Failed to find src clk for baud rate: %d ret: %d\n", 1283 baud, ret); 1284 return ret; 1285 } 1286 1287 clk_div = DIV_ROUND_UP(clk_rate, baud * sampling_rate); 1288 /* Check if calculated divider exceeds maximum allowed value */ 1289 if (clk_div > (CLK_DIV_MSK >> CLK_DIV_SHFT)) { 1290 dev_err(port->se.dev, "Calculated clock divider %u exceeds maximum\n", clk_div); 1291 return -EINVAL; 1292 } 1293 1294 dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u, clk_idx = %u\n", 1295 baud * sampling_rate, clk_rate, clk_div, clk_idx); 1296 1297 uport->uartclk = clk_rate; 1298 port->clk_rate = clk_rate; 1299 dev_pm_opp_set_rate(uport->dev, clk_rate); 1300 ser_clk_cfg = SER_CLK_EN; 1301 ser_clk_cfg |= clk_div << CLK_DIV_SHFT; 1302 1303 /* 1304 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode 1305 * only. 1306 */ 1307 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ) 1308 : GENI_DEFAULT_BW; 1309 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; 1310 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); 1311 geni_icc_set_bw(&port->se); 1312 1313 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); 1314 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); 1315 /* Configure clock selection register with the selected clock index */ 1316 writel(clk_idx & CLK_SEL_MSK, uport->membase + SE_GENI_CLK_SEL); 1317 return 0; 1318 } 1319 1320 static int geni_serial_set_level(struct uart_port *uport, unsigned int baud) 1321 { 1322 struct qcom_geni_serial_port *port = to_dev_port(uport); 1323 struct device *perf_dev = port->pd_list->pd_devs[DOMAIN_IDX_PERF]; 1324 1325 /* 1326 * The performance protocol sets UART communication 1327 * speeds by selecting different performance levels 1328 * through the OPP framework. 1329 * 1330 * Supported perf levels for baudrates in firmware are below 1331 * +---------------------+--------------------+ 1332 * | Perf level value | Baudrate values | 1333 * +---------------------+--------------------+ 1334 * | 300 | 300 | 1335 * | 1200 | 1200 | 1336 * | 2400 | 2400 | 1337 * | 4800 | 4800 | 1338 * | 9600 | 9600 | 1339 * | 19200 | 19200 | 1340 * | 38400 | 38400 | 1341 * | 57600 | 57600 | 1342 * | 115200 | 115200 | 1343 * | 230400 | 230400 | 1344 * | 460800 | 460800 | 1345 * | 921600 | 921600 | 1346 * | 2000000 | 2000000 | 1347 * | 3000000 | 3000000 | 1348 * | 3200000 | 3200000 | 1349 * | 4000000 | 4000000 | 1350 * +---------------------+--------------------+ 1351 */ 1352 1353 return dev_pm_opp_set_level(perf_dev, baud); 1354 } 1355 1356 static void qcom_geni_serial_set_termios(struct uart_port *uport, 1357 struct ktermios *termios, 1358 const struct ktermios *old) 1359 { 1360 struct qcom_geni_serial_port *port = to_dev_port(uport); 1361 unsigned int baud; 1362 unsigned long timeout; 1363 u32 bits_per_char; 1364 u32 tx_trans_cfg; 1365 u32 tx_parity_cfg; 1366 u32 rx_trans_cfg; 1367 u32 rx_parity_cfg; 1368 u32 stop_bit_len; 1369 int ret = 0; 1370 1371 /* baud rate */ 1372 baud = uart_get_baud_rate(uport, termios, old, 300, 8000000); 1373 1374 ret = port->dev_data->set_rate(uport, baud); 1375 if (ret) 1376 return; 1377 1378 /* parity */ 1379 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); 1380 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); 1381 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); 1382 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); 1383 if (termios->c_cflag & PARENB) { 1384 tx_trans_cfg |= UART_TX_PAR_EN; 1385 rx_trans_cfg |= UART_RX_PAR_EN; 1386 tx_parity_cfg |= PAR_CALC_EN; 1387 rx_parity_cfg |= PAR_CALC_EN; 1388 if (termios->c_cflag & PARODD) { 1389 tx_parity_cfg |= PAR_ODD; 1390 rx_parity_cfg |= PAR_ODD; 1391 } else if (termios->c_cflag & CMSPAR) { 1392 tx_parity_cfg |= PAR_SPACE; 1393 rx_parity_cfg |= PAR_SPACE; 1394 } else { 1395 tx_parity_cfg |= PAR_EVEN; 1396 rx_parity_cfg |= PAR_EVEN; 1397 } 1398 } else { 1399 tx_trans_cfg &= ~UART_TX_PAR_EN; 1400 rx_trans_cfg &= ~UART_RX_PAR_EN; 1401 tx_parity_cfg &= ~PAR_CALC_EN; 1402 rx_parity_cfg &= ~PAR_CALC_EN; 1403 } 1404 1405 /* bits per char */ 1406 bits_per_char = tty_get_char_size(termios->c_cflag); 1407 1408 /* stop bits */ 1409 if (termios->c_cflag & CSTOPB) 1410 stop_bit_len = TX_STOP_BIT_LEN_2; 1411 else 1412 stop_bit_len = TX_STOP_BIT_LEN_1; 1413 1414 /* Configure flow control based on CRTSCTS flag. 1415 * When CRTSCTS is set, use HW/auto flow control mode, where HW 1416 * controls the RTS/CTS pin based FIFO state. 1417 * When CRTSCTS is clear, the CTS pin value is ignored for TX 1418 * path and RTS pin can be set/cleared using registers, for RX 1419 * path. 1420 */ 1421 1422 if (termios->c_cflag & CRTSCTS) { 1423 tx_trans_cfg &= ~UART_CTS_MASK; 1424 port->manual_flow = false; 1425 } else { 1426 tx_trans_cfg |= UART_CTS_MASK; 1427 port->manual_flow = true; 1428 } 1429 1430 if (baud) { 1431 uart_update_timeout(uport, termios->c_cflag, baud); 1432 1433 /* 1434 * Make sure that qcom_geni_serial_poll_bitfield() waits for 1435 * the FIFO, two-word intermediate transfer register and shift 1436 * register to clear. 1437 * 1438 * Note that uart_fifo_timeout() also adds a 20 ms margin. 1439 */ 1440 timeout = jiffies_to_usecs(uart_fifo_timeout(uport)); 1441 timeout += 3 * timeout / port->tx_fifo_depth; 1442 WRITE_ONCE(port->poll_timeout_us, timeout); 1443 } 1444 1445 if (!uart_console(uport)) 1446 writel(port->loopback, 1447 uport->membase + SE_UART_LOOPBACK_CFG); 1448 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1449 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1450 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1451 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1452 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1453 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1454 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1455 } 1456 1457 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 1458 static int qcom_geni_console_setup(struct console *co, char *options) 1459 { 1460 struct uart_port *uport; 1461 struct qcom_geni_serial_port *port; 1462 int baud = 115200; 1463 int bits = 8; 1464 int parity = 'n'; 1465 int flow = 'n'; 1466 int ret; 1467 1468 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) 1469 return -ENXIO; 1470 1471 port = get_port_from_line(co->index, true, NULL); 1472 if (IS_ERR(port)) { 1473 pr_err("Invalid line %d\n", co->index); 1474 return PTR_ERR(port); 1475 } 1476 1477 uport = &port->uport; 1478 1479 if (unlikely(!uport->membase)) 1480 return -ENXIO; 1481 1482 if (!port->setup) { 1483 ret = qcom_geni_serial_port_setup(uport); 1484 if (ret) 1485 return ret; 1486 } 1487 1488 if (options) 1489 uart_parse_options(options, &baud, &parity, &bits, &flow); 1490 1491 return uart_set_options(uport, co, baud, parity, bits, flow); 1492 } 1493 1494 static void qcom_geni_serial_earlycon_write(struct console *con, 1495 const char *s, unsigned int n) 1496 { 1497 struct earlycon_device *dev = con->data; 1498 1499 __qcom_geni_serial_console_write(&dev->port, s, n); 1500 } 1501 1502 #ifdef CONFIG_CONSOLE_POLL 1503 static int qcom_geni_serial_earlycon_read(struct console *con, 1504 char *s, unsigned int n) 1505 { 1506 struct earlycon_device *dev = con->data; 1507 struct uart_port *uport = &dev->port; 1508 int num_read = 0; 1509 int ch; 1510 1511 while (num_read < n) { 1512 ch = qcom_geni_serial_get_char(uport); 1513 if (ch == NO_POLL_CHAR) 1514 break; 1515 s[num_read++] = ch; 1516 } 1517 1518 return num_read; 1519 } 1520 1521 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se, 1522 struct console *con) 1523 { 1524 geni_se_setup_s_cmd(se, UART_START_READ, 0); 1525 con->read = qcom_geni_serial_earlycon_read; 1526 } 1527 #else 1528 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se, 1529 struct console *con) { } 1530 #endif 1531 1532 static struct qcom_geni_private_data earlycon_private_data; 1533 1534 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, 1535 const char *opt) 1536 { 1537 struct uart_port *uport = &dev->port; 1538 u32 tx_trans_cfg; 1539 u32 tx_parity_cfg = 0; /* Disable Tx Parity */ 1540 u32 rx_trans_cfg = 0; 1541 u32 rx_parity_cfg = 0; /* Disable Rx Parity */ 1542 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ 1543 u32 bits_per_char; 1544 struct geni_se se; 1545 1546 if (!uport->membase) 1547 return -EINVAL; 1548 1549 uport->private_data = &earlycon_private_data; 1550 1551 memset(&se, 0, sizeof(se)); 1552 se.base = uport->membase; 1553 if (geni_se_read_proto(&se) != GENI_SE_UART) 1554 return -ENXIO; 1555 /* 1556 * Ignore Flow control. 1557 * n = 8. 1558 */ 1559 tx_trans_cfg = UART_CTS_MASK; 1560 bits_per_char = BITS_PER_BYTE; 1561 1562 /* 1563 * Make an unconditional cancel on the main sequencer to reset 1564 * it else we could end up in data loss scenarios. 1565 */ 1566 qcom_geni_serial_poll_tx_done(uport); 1567 qcom_geni_serial_abort_rx(uport); 1568 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1569 false, true, true); 1570 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); 1571 geni_se_select_mode(&se, GENI_SE_FIFO); 1572 1573 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1574 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1575 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1576 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1577 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1578 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1579 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1580 1581 dev->con->write = qcom_geni_serial_earlycon_write; 1582 dev->con->setup = NULL; 1583 qcom_geni_serial_enable_early_read(&se, dev->con); 1584 1585 return 0; 1586 } 1587 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", 1588 qcom_geni_serial_earlycon_setup); 1589 1590 static int __init console_register(struct uart_driver *drv) 1591 { 1592 return uart_register_driver(drv); 1593 } 1594 1595 static void console_unregister(struct uart_driver *drv) 1596 { 1597 uart_unregister_driver(drv); 1598 } 1599 1600 static struct console cons_ops = { 1601 .name = "ttyMSM", 1602 .write = qcom_geni_serial_console_write, 1603 .device = uart_console_device, 1604 .setup = qcom_geni_console_setup, 1605 .flags = CON_PRINTBUFFER, 1606 .index = -1, 1607 .data = &qcom_geni_console_driver, 1608 }; 1609 1610 static struct uart_driver qcom_geni_console_driver = { 1611 .owner = THIS_MODULE, 1612 .driver_name = "qcom_geni_console", 1613 .dev_name = "ttyMSM", 1614 .nr = GENI_UART_CONS_PORTS, 1615 .cons = &cons_ops, 1616 }; 1617 #else 1618 static int console_register(struct uart_driver *drv) 1619 { 1620 return 0; 1621 } 1622 1623 static void console_unregister(struct uart_driver *drv) 1624 { 1625 } 1626 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 1627 1628 static struct uart_driver qcom_geni_uart_driver = { 1629 .owner = THIS_MODULE, 1630 .driver_name = "qcom_geni_uart", 1631 .dev_name = "ttyHS", 1632 .nr = CONFIG_SERIAL_QCOM_GENI_UART_PORTS, 1633 }; 1634 1635 static int geni_serial_resources_on(struct uart_port *uport) 1636 { 1637 struct qcom_geni_serial_port *port = to_dev_port(uport); 1638 int ret; 1639 1640 ret = geni_icc_enable(&port->se); 1641 if (ret) 1642 return ret; 1643 1644 ret = geni_se_resources_on(&port->se); 1645 if (ret) { 1646 geni_icc_disable(&port->se); 1647 return ret; 1648 } 1649 1650 if (port->clk_rate) 1651 dev_pm_opp_set_rate(uport->dev, port->clk_rate); 1652 1653 return 0; 1654 } 1655 1656 static int geni_serial_resources_off(struct uart_port *uport) 1657 { 1658 struct qcom_geni_serial_port *port = to_dev_port(uport); 1659 int ret; 1660 1661 dev_pm_opp_set_rate(uport->dev, 0); 1662 ret = geni_se_resources_off(&port->se); 1663 if (ret) 1664 return ret; 1665 1666 geni_icc_disable(&port->se); 1667 1668 return 0; 1669 } 1670 1671 static int geni_serial_resource_state(struct uart_port *uport, bool power_on) 1672 { 1673 return power_on ? geni_serial_resources_on(uport) : geni_serial_resources_off(uport); 1674 } 1675 1676 static int geni_serial_pwr_init(struct uart_port *uport) 1677 { 1678 struct qcom_geni_serial_port *port = to_dev_port(uport); 1679 int ret; 1680 1681 ret = dev_pm_domain_attach_list(port->se.dev, 1682 &port->dev_data->pd_data, &port->pd_list); 1683 if (ret <= 0) 1684 return -EINVAL; 1685 1686 return 0; 1687 } 1688 1689 static int geni_serial_resource_init(struct uart_port *uport) 1690 { 1691 struct qcom_geni_serial_port *port = to_dev_port(uport); 1692 int ret; 1693 1694 port->se.clk = devm_clk_get(port->se.dev, "se"); 1695 if (IS_ERR(port->se.clk)) { 1696 ret = PTR_ERR(port->se.clk); 1697 dev_err(port->se.dev, "Err getting SE Core clk %d\n", ret); 1698 return ret; 1699 } 1700 1701 ret = geni_icc_get(&port->se, NULL); 1702 if (ret) 1703 return ret; 1704 1705 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; 1706 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1707 1708 /* Set BW for register access */ 1709 ret = geni_icc_set_bw(&port->se); 1710 if (ret) 1711 return ret; 1712 1713 ret = devm_pm_opp_set_clkname(port->se.dev, "se"); 1714 if (ret) 1715 return ret; 1716 1717 /* OPP table is optional */ 1718 ret = devm_pm_opp_of_add_table(port->se.dev); 1719 if (ret && ret != -ENODEV) { 1720 dev_err(port->se.dev, "invalid OPP table in device tree\n"); 1721 return ret; 1722 } 1723 1724 return 0; 1725 } 1726 1727 static void qcom_geni_serial_pm(struct uart_port *uport, 1728 unsigned int new_state, unsigned int old_state) 1729 { 1730 1731 /* If we've never been called, treat it as off */ 1732 if (old_state == UART_PM_STATE_UNDEFINED) 1733 old_state = UART_PM_STATE_OFF; 1734 1735 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) 1736 pm_runtime_resume_and_get(uport->dev); 1737 else if (new_state == UART_PM_STATE_OFF && 1738 old_state == UART_PM_STATE_ON) 1739 pm_runtime_put_sync(uport->dev); 1740 1741 } 1742 1743 /** 1744 * qcom_geni_rs485_config - Configure RS485 settings for the UART port 1745 * @uport: Pointer to the UART port structure 1746 * @termios: Pointer to the termios structure 1747 * @rs485: Pointer to the RS485 configuration structure 1748 * This function configures the RTS (Request to Send) pin behavior for RS485 mode. 1749 * When RS485 mode is enabled, the RTS pin is kept in default ACTIVE HIGH state. 1750 * Return: Always returns 0. 1751 */ 1752 1753 static int qcom_geni_rs485_config(struct uart_port *uport, 1754 struct ktermios *termios, struct serial_rs485 *rs485) 1755 { 1756 qcom_geni_set_rs485_mode(uport, SER_RS485_ENABLED); 1757 1758 return 0; 1759 } 1760 1761 static const struct uart_ops qcom_geni_console_pops = { 1762 .tx_empty = qcom_geni_serial_tx_empty, 1763 .stop_tx = qcom_geni_serial_stop_tx_fifo, 1764 .start_tx = qcom_geni_serial_start_tx_fifo, 1765 .stop_rx = qcom_geni_serial_stop_rx_fifo, 1766 .start_rx = qcom_geni_serial_start_rx_fifo, 1767 .set_termios = qcom_geni_serial_set_termios, 1768 .startup = qcom_geni_serial_startup, 1769 .request_port = qcom_geni_serial_request_port, 1770 .config_port = qcom_geni_serial_config_port, 1771 .shutdown = qcom_geni_serial_shutdown, 1772 .flush_buffer = qcom_geni_serial_flush_buffer, 1773 .type = qcom_geni_serial_get_type, 1774 .set_mctrl = qcom_geni_serial_set_mctrl, 1775 .get_mctrl = qcom_geni_serial_get_mctrl, 1776 #ifdef CONFIG_CONSOLE_POLL 1777 .poll_get_char = qcom_geni_serial_get_char, 1778 .poll_put_char = qcom_geni_serial_poll_put_char, 1779 .poll_init = qcom_geni_serial_poll_init, 1780 #endif 1781 .pm = qcom_geni_serial_pm, 1782 }; 1783 1784 static const struct uart_ops qcom_geni_uart_pops = { 1785 .tx_empty = qcom_geni_serial_tx_empty, 1786 .stop_tx = qcom_geni_serial_stop_tx_dma, 1787 .start_tx = qcom_geni_serial_start_tx_dma, 1788 .start_rx = qcom_geni_serial_start_rx_dma, 1789 .stop_rx = qcom_geni_serial_stop_rx_dma, 1790 .set_termios = qcom_geni_serial_set_termios, 1791 .startup = qcom_geni_serial_startup, 1792 .request_port = qcom_geni_serial_request_port, 1793 .config_port = qcom_geni_serial_config_port, 1794 .shutdown = qcom_geni_serial_shutdown, 1795 .type = qcom_geni_serial_get_type, 1796 .set_mctrl = qcom_geni_serial_set_mctrl, 1797 .get_mctrl = qcom_geni_serial_get_mctrl, 1798 .pm = qcom_geni_serial_pm, 1799 }; 1800 1801 static int qcom_geni_serial_probe(struct platform_device *pdev) 1802 { 1803 int ret = 0; 1804 int line; 1805 struct qcom_geni_serial_port *port; 1806 struct uart_port *uport; 1807 struct resource *res; 1808 int irq; 1809 struct uart_driver *drv; 1810 const struct qcom_geni_device_data *data; 1811 1812 data = of_device_get_match_data(&pdev->dev); 1813 if (!data) 1814 return -EINVAL; 1815 1816 if (data->console) { 1817 drv = &qcom_geni_console_driver; 1818 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1819 } else { 1820 drv = &qcom_geni_uart_driver; 1821 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1822 if (line == -ENODEV) /* compat with non-standard aliases */ 1823 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); 1824 } 1825 1826 port = get_port_from_line(line, data->console, &pdev->dev); 1827 if (IS_ERR(port)) { 1828 dev_err(&pdev->dev, "Invalid line %d\n", line); 1829 return PTR_ERR(port); 1830 } 1831 1832 uport = &port->uport; 1833 /* Don't allow 2 drivers to access the same port */ 1834 if (uport->private_data) 1835 return -ENODEV; 1836 1837 uport->dev = &pdev->dev; 1838 port->dev_data = data; 1839 port->se.dev = &pdev->dev; 1840 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); 1841 1842 ret = port->dev_data->resources_init(uport); 1843 if (ret) 1844 return ret; 1845 1846 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1847 if (!res) { 1848 ret = -EINVAL; 1849 goto error; 1850 } 1851 1852 uport->mapbase = res->start; 1853 1854 uport->rs485_config = qcom_geni_rs485_config; 1855 uport->rs485_supported = qcom_geni_rs485_supported; 1856 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1857 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1858 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; 1859 1860 if (!data->console) { 1861 port->rx_buf = devm_kzalloc(uport->dev, 1862 DMA_RX_BUF_SIZE, GFP_KERNEL); 1863 if (!port->rx_buf) { 1864 ret = -ENOMEM; 1865 goto error; 1866 } 1867 } 1868 1869 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, 1870 "qcom_geni_serial_%s%d", 1871 uart_console(uport) ? "console" : "uart", uport->line); 1872 if (!port->name) { 1873 ret = -ENOMEM; 1874 goto error; 1875 } 1876 1877 irq = platform_get_irq(pdev, 0); 1878 if (irq < 0) { 1879 ret = irq; 1880 goto error; 1881 } 1882 1883 uport->irq = irq; 1884 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); 1885 1886 if (!data->console) 1887 port->wakeup_irq = platform_get_irq_optional(pdev, 1); 1888 1889 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) 1890 port->rx_tx_swap = true; 1891 1892 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) 1893 port->cts_rts_swap = true; 1894 1895 port->private_data.drv = drv; 1896 uport->private_data = &port->private_data; 1897 platform_set_drvdata(pdev, port); 1898 1899 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); 1900 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, 1901 IRQF_TRIGGER_HIGH, port->name, uport); 1902 if (ret) { 1903 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); 1904 goto error; 1905 } 1906 1907 ret = uart_get_rs485_mode(uport); 1908 if (ret) 1909 goto error; 1910 1911 if (port->wakeup_irq > 0) { 1912 device_init_wakeup(&pdev->dev, true); 1913 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1914 port->wakeup_irq); 1915 if (ret) { 1916 device_init_wakeup(&pdev->dev, false); 1917 ida_free(&port_ida, uport->line); 1918 goto error; 1919 } 1920 } 1921 1922 devm_pm_runtime_enable(port->se.dev); 1923 1924 ret = uart_add_one_port(drv, uport); 1925 if (ret) 1926 goto error; 1927 1928 return 0; 1929 1930 error: 1931 dev_pm_domain_detach_list(port->pd_list); 1932 return ret; 1933 } 1934 1935 static void qcom_geni_serial_remove(struct platform_device *pdev) 1936 { 1937 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 1938 struct uart_port *uport = &port->uport; 1939 struct uart_driver *drv = port->private_data.drv; 1940 1941 dev_pm_clear_wake_irq(&pdev->dev); 1942 device_init_wakeup(&pdev->dev, false); 1943 ida_free(&port_ida, uport->line); 1944 uart_remove_one_port(drv, &port->uport); 1945 dev_pm_domain_detach_list(port->pd_list); 1946 } 1947 1948 static int __maybe_unused qcom_geni_serial_runtime_suspend(struct device *dev) 1949 { 1950 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1951 struct uart_port *uport = &port->uport; 1952 int ret = 0; 1953 1954 if (port->dev_data->power_state) 1955 ret = port->dev_data->power_state(uport, false); 1956 1957 return ret; 1958 } 1959 1960 static int __maybe_unused qcom_geni_serial_runtime_resume(struct device *dev) 1961 { 1962 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1963 struct uart_port *uport = &port->uport; 1964 int ret = 0; 1965 1966 if (port->dev_data->power_state) 1967 ret = port->dev_data->power_state(uport, true); 1968 1969 return ret; 1970 } 1971 1972 static int qcom_geni_serial_suspend(struct device *dev) 1973 { 1974 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1975 struct uart_port *uport = &port->uport; 1976 struct qcom_geni_private_data *private_data = uport->private_data; 1977 1978 /* 1979 * This is done so we can hit the lowest possible state in suspend 1980 * even with no_console_suspend 1981 */ 1982 if (uart_console(uport)) { 1983 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); 1984 geni_icc_set_bw(&port->se); 1985 } 1986 return uart_suspend_port(private_data->drv, uport); 1987 } 1988 1989 static int qcom_geni_serial_resume(struct device *dev) 1990 { 1991 int ret; 1992 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1993 struct uart_port *uport = &port->uport; 1994 struct qcom_geni_private_data *private_data = uport->private_data; 1995 1996 ret = uart_resume_port(private_data->drv, uport); 1997 if (uart_console(uport)) { 1998 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); 1999 geni_icc_set_bw(&port->se); 2000 } 2001 return ret; 2002 } 2003 2004 #if IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE) 2005 static const struct qcom_geni_device_data qcom_geni_console_data = { 2006 .console = true, 2007 .mode = GENI_SE_FIFO, 2008 .resources_init = geni_serial_resource_init, 2009 .set_rate = geni_serial_set_rate, 2010 .power_state = geni_serial_resource_state, 2011 }; 2012 2013 static const struct qcom_geni_device_data sa8255p_qcom_geni_console_data = { 2014 .console = true, 2015 .mode = GENI_SE_FIFO, 2016 .pd_data = { 2017 .pd_flags = PD_FLAG_DEV_LINK_ON, 2018 .pd_names = (const char*[]) { "power", "perf" }, 2019 .num_pd_names = 2, 2020 }, 2021 .resources_init = geni_serial_pwr_init, 2022 .set_rate = geni_serial_set_level, 2023 }; 2024 #endif 2025 2026 static const struct qcom_geni_device_data qcom_geni_uart_data = { 2027 .console = false, 2028 .mode = GENI_SE_DMA, 2029 .resources_init = geni_serial_resource_init, 2030 .set_rate = geni_serial_set_rate, 2031 .power_state = geni_serial_resource_state, 2032 }; 2033 2034 static const struct qcom_geni_device_data sa8255p_qcom_geni_uart_data = { 2035 .console = false, 2036 .mode = GENI_SE_DMA, 2037 .pd_data = { 2038 .pd_flags = PD_FLAG_DEV_LINK_ON, 2039 .pd_names = (const char*[]) { "power", "perf" }, 2040 .num_pd_names = 2, 2041 }, 2042 .resources_init = geni_serial_pwr_init, 2043 .set_rate = geni_serial_set_level, 2044 }; 2045 2046 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 2047 SET_RUNTIME_PM_OPS(qcom_geni_serial_runtime_suspend, 2048 qcom_geni_serial_runtime_resume, NULL) 2049 SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_suspend, qcom_geni_serial_resume) 2050 }; 2051 2052 static const struct of_device_id qcom_geni_serial_match_table[] = { 2053 #if IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE) 2054 { 2055 .compatible = "qcom,geni-debug-uart", 2056 .data = &qcom_geni_console_data, 2057 }, 2058 { 2059 .compatible = "qcom,sa8255p-geni-debug-uart", 2060 .data = &sa8255p_qcom_geni_console_data, 2061 }, 2062 #endif 2063 { 2064 .compatible = "qcom,geni-uart", 2065 .data = &qcom_geni_uart_data, 2066 }, 2067 { 2068 .compatible = "qcom,sa8255p-geni-uart", 2069 .data = &sa8255p_qcom_geni_uart_data, 2070 }, 2071 {} 2072 }; 2073 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); 2074 2075 static struct platform_driver qcom_geni_serial_platform_driver = { 2076 .remove = qcom_geni_serial_remove, 2077 .probe = qcom_geni_serial_probe, 2078 .driver = { 2079 .name = "qcom_geni_serial", 2080 .of_match_table = qcom_geni_serial_match_table, 2081 .pm = &qcom_geni_serial_pm_ops, 2082 }, 2083 }; 2084 2085 static int __init qcom_geni_serial_init(void) 2086 { 2087 int ret; 2088 2089 ret = console_register(&qcom_geni_console_driver); 2090 if (ret) 2091 return ret; 2092 2093 ret = uart_register_driver(&qcom_geni_uart_driver); 2094 if (ret) { 2095 console_unregister(&qcom_geni_console_driver); 2096 return ret; 2097 } 2098 2099 ret = platform_driver_register(&qcom_geni_serial_platform_driver); 2100 if (ret) { 2101 console_unregister(&qcom_geni_console_driver); 2102 uart_unregister_driver(&qcom_geni_uart_driver); 2103 } 2104 return ret; 2105 } 2106 module_init(qcom_geni_serial_init); 2107 2108 static void __exit qcom_geni_serial_exit(void) 2109 { 2110 platform_driver_unregister(&qcom_geni_serial_platform_driver); 2111 console_unregister(&qcom_geni_console_driver); 2112 uart_unregister_driver(&qcom_geni_uart_driver); 2113 } 2114 module_exit(qcom_geni_serial_exit); 2115 2116 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); 2117 MODULE_LICENSE("GPL v2"); 2118