1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
5 * Copyright (c) 2023, Linaro Limited
6 */
7
8 #include <linux/module.h>
9 #include <linux/slab.h>
10 #include <linux/platform_device.h>
11 #include <linux/device.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/kernel.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/component.h>
17 #include <sound/tlv.h>
18 #include <linux/of_graph.h>
19 #include <linux/of.h>
20 #include <sound/jack.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <linux/regmap.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/usb/typec_mux.h>
28 #include <linux/usb/typec_altmode.h>
29
30 #include "wcd-clsh-v2.h"
31 #include "wcd-common.h"
32 #include "wcd-mbhc-v2.h"
33 #include "wcd939x.h"
34
35 #define WCD939X_MAX_MICBIAS (4)
36 #define WCD939X_MBHC_MAX_BUTTONS (8)
37 #define TX_ADC_MAX (4)
38 #define WCD_MBHC_HS_V_MAX 1600
39
40 #define CHIPID_WCD9390 0x0
41 #define CHIPID_WCD9395 0x5
42
43 /* Version major: 1.x */
44 #define CHIPID_WCD939X_VER_MAJOR_1 0x0
45 /* Version minor: x.1 */
46 #define CHIPID_WCD939X_VER_MINOR_1 0x3
47
48 enum {
49 WCD939X_VERSION_1_0 = 0,
50 WCD939X_VERSION_1_1,
51 WCD939X_VERSION_2_0,
52 };
53
54 #define WCD939X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
55 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
56 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
57 SNDRV_PCM_RATE_384000)
58 /* Fractional Rates */
59 #define WCD939X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
60 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
61 #define WCD939X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
62 SNDRV_PCM_FMTBIT_S24_LE |\
63 SNDRV_PCM_FMTBIT_S24_3LE |\
64 SNDRV_PCM_FMTBIT_S32_LE)
65
66 /* Convert from vout ctl to micbias voltage in mV */
67 #define WCD_VOUT_CTL_TO_MICB(v) (1000 + (v) * 50)
68 #define SWR_CLK_RATE_0P6MHZ (600000)
69 #define SWR_CLK_RATE_1P2MHZ (1200000)
70 #define SWR_CLK_RATE_2P4MHZ (2400000)
71 #define SWR_CLK_RATE_4P8MHZ (4800000)
72 #define SWR_CLK_RATE_9P6MHZ (9600000)
73 #define SWR_CLK_RATE_11P2896MHZ (1128960)
74
75 #define ADC_MODE_VAL_HIFI 0x01
76 #define ADC_MODE_VAL_LO_HIF 0x02
77 #define ADC_MODE_VAL_NORMAL 0x03
78 #define ADC_MODE_VAL_LP 0x05
79 #define ADC_MODE_VAL_ULP1 0x09
80 #define ADC_MODE_VAL_ULP2 0x0B
81
82 /* Z value defined in milliohm */
83 #define WCD939X_ZDET_VAL_32 (32000)
84 #define WCD939X_ZDET_VAL_400 (400000)
85 #define WCD939X_ZDET_VAL_1200 (1200000)
86 #define WCD939X_ZDET_VAL_100K (100000000)
87
88 /* Z floating defined in ohms */
89 #define WCD939X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE)
90 #define WCD939X_ZDET_NUM_MEASUREMENTS (900)
91 #define WCD939X_MBHC_GET_C1(c) (((c) & 0xC000) >> 14)
92 #define WCD939X_MBHC_GET_X1(x) ((x) & 0x3FFF)
93
94 /* Z value compared in milliOhm */
95 #define WCD939X_ANA_MBHC_ZDET_CONST (1018 * 1024)
96
97 enum {
98 /* INTR_CTRL_INT_MASK_0 */
99 WCD939X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
100 WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET,
101 WCD939X_IRQ_MBHC_ELECT_INS_REM_DET,
102 WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
103 WCD939X_IRQ_MBHC_SW_DET,
104 WCD939X_IRQ_HPHR_OCP_INT,
105 WCD939X_IRQ_HPHR_CNP_INT,
106 WCD939X_IRQ_HPHL_OCP_INT,
107
108 /* INTR_CTRL_INT_MASK_1 */
109 WCD939X_IRQ_HPHL_CNP_INT,
110 WCD939X_IRQ_EAR_CNP_INT,
111 WCD939X_IRQ_EAR_SCD_INT,
112 WCD939X_IRQ_HPHL_PDM_WD_INT,
113 WCD939X_IRQ_HPHR_PDM_WD_INT,
114 WCD939X_IRQ_EAR_PDM_WD_INT,
115
116 /* INTR_CTRL_INT_MASK_2 */
117 WCD939X_IRQ_MBHC_MOISTURE_INT,
118 WCD939X_IRQ_HPHL_SURGE_DET_INT,
119 WCD939X_IRQ_HPHR_SURGE_DET_INT,
120 WCD939X_NUM_IRQS,
121 };
122
123 enum {
124 MICB_BIAS_DISABLE = 0,
125 MICB_BIAS_ENABLE,
126 MICB_BIAS_PULL_UP,
127 MICB_BIAS_PULL_DOWN,
128 };
129
130 enum {
131 WCD_ADC1 = 0,
132 WCD_ADC2,
133 WCD_ADC3,
134 WCD_ADC4,
135 HPH_PA_DELAY,
136 };
137
138 enum {
139 ADC_MODE_INVALID = 0,
140 ADC_MODE_HIFI,
141 ADC_MODE_LO_HIF,
142 ADC_MODE_NORMAL,
143 ADC_MODE_LP,
144 ADC_MODE_ULP1,
145 ADC_MODE_ULP2,
146 };
147
148 enum {
149 AIF1_PB = 0,
150 AIF1_CAP,
151 NUM_CODEC_DAIS,
152 };
153
154 static u8 tx_mode_bit[] = {
155 [ADC_MODE_INVALID] = 0x00,
156 [ADC_MODE_HIFI] = 0x01,
157 [ADC_MODE_LO_HIF] = 0x02,
158 [ADC_MODE_NORMAL] = 0x04,
159 [ADC_MODE_LP] = 0x08,
160 [ADC_MODE_ULP1] = 0x10,
161 [ADC_MODE_ULP2] = 0x20,
162 };
163
164 struct zdet_param {
165 u16 ldo_ctl;
166 u16 noff;
167 u16 nshift;
168 u16 btn5;
169 u16 btn6;
170 u16 btn7;
171 };
172
173 struct wcd939x_priv {
174 struct sdw_slave *tx_sdw_dev;
175 struct wcd939x_sdw_priv *sdw_priv[NUM_CODEC_DAIS];
176 struct device *txdev;
177 struct device *rxdev;
178 struct device_node *rxnode, *txnode;
179 struct regmap *regmap;
180 struct snd_soc_component *component;
181 /* micb setup lock */
182 struct mutex micb_lock;
183 /* typec handling */
184 bool typec_analog_mux;
185 #if IS_ENABLED(CONFIG_TYPEC)
186 enum typec_orientation typec_orientation;
187 unsigned long typec_mode;
188 struct typec_switch *typec_switch;
189 #endif /* CONFIG_TYPEC */
190 /* mbhc module */
191 struct wcd_mbhc *wcd_mbhc;
192 struct wcd_mbhc_config mbhc_cfg;
193 struct wcd_mbhc_intr intr_ids;
194 struct wcd_clsh_ctrl *clsh_info;
195 struct wcd_common common;
196 struct irq_domain *virq;
197 struct regmap_irq_chip_data *irq_chip;
198 struct snd_soc_jack *jack;
199 unsigned long status_mask;
200 s32 micb_ref[WCD939X_MAX_MICBIAS];
201 s32 pullup_ref[WCD939X_MAX_MICBIAS];
202 u32 hph_mode;
203 u32 tx_mode[TX_ADC_MAX];
204 int variant;
205 struct gpio_desc *reset_gpio;
206 int hphr_pdm_wd_int;
207 int hphl_pdm_wd_int;
208 int ear_pdm_wd_int;
209 bool comp1_enable;
210 bool comp2_enable;
211 bool ldoh;
212 };
213
214 static const char * const wcd939x_supplies[] = {
215 "vdd-rxtx", "vdd-io", "vdd-buck", "vdd-mic-bias", "vdd-px",
216 };
217
218 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
219 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
220 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
221
222 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
223 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD939X_ANA_MBHC_MECH, 0x80),
224 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD939X_ANA_MBHC_MECH, 0x40),
225 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD939X_ANA_MBHC_MECH, 0x20),
226 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD939X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
227 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD939X_ANA_MBHC_ELECT, 0x08),
228 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD939X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F),
229 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD939X_ANA_MBHC_MECH, 0x04),
230 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD939X_ANA_MBHC_MECH, 0x10),
231 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD939X_ANA_MBHC_MECH, 0x08),
232 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD939X_ANA_MBHC_MECH, 0x01),
233 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD939X_ANA_MBHC_ELECT, 0x06),
234 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD939X_ANA_MBHC_ELECT, 0x80),
235 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD939X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
236 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD939X_MBHC_NEW_CTL_1, 0x03),
237 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD939X_MBHC_NEW_CTL_2, 0x03),
238 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x08),
239 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD939X_ANA_MBHC_RESULT_3, 0x10),
240 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x20),
241 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x80),
242 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x40),
243 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD939X_HPH_OCP_CTL, 0x10),
244 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x07),
245 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD939X_ANA_MBHC_ELECT, 0x70),
246 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0xFF),
247 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD939X_ANA_MICB2, 0xC0),
248 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD939X_HPH_CNP_WG_TIME, 0xFF),
249 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD939X_ANA_HPH, 0x40),
250 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD939X_ANA_HPH, 0x80),
251 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD939X_ANA_HPH, 0xC0),
252 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD939X_ANA_MBHC_RESULT_3, 0x10),
253 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD939X_MBHC_CTL_BCS, 0x02),
254 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD939X_MBHC_NEW_FSM_STATUS, 0x01),
255 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD939X_MBHC_NEW_CTL_2, 0x70),
256 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD939X_MBHC_NEW_FSM_STATUS, 0x20),
257 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD939X_HPH_PA_CTL2, 0x40),
258 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD939X_HPH_PA_CTL2, 0x10),
259 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD939X_HPH_L_TEST, 0x01),
260 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD939X_HPH_R_TEST, 0x01),
261 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD939X_DIGITAL_INTR_STATUS_0, 0x80),
262 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD939X_DIGITAL_INTR_STATUS_0, 0x20),
263 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD939X_MBHC_NEW_CTL_1, 0x08),
264 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD939X_MBHC_NEW_FSM_STATUS, 0x40),
265 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD939X_MBHC_NEW_FSM_STATUS, 0x80),
266 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD939X_MBHC_NEW_ADC_RESULT, 0xFF),
267 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD939X_ANA_MICB2, 0x3F),
268 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD939X_MBHC_NEW_CTL_1, 0x10),
269 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD939X_MBHC_NEW_CTL_1, 0x04),
270 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD939X_ANA_MBHC_ZDET, 0x02),
271 };
272
273 static const struct regmap_irq wcd939x_irqs[WCD939X_NUM_IRQS] = {
274 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
275 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
276 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
277 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
278 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_SW_DET, 0, 0x10),
279 REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_OCP_INT, 0, 0x20),
280 REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_CNP_INT, 0, 0x40),
281 REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_OCP_INT, 0, 0x80),
282 REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_CNP_INT, 1, 0x01),
283 REGMAP_IRQ_REG(WCD939X_IRQ_EAR_CNP_INT, 1, 0x02),
284 REGMAP_IRQ_REG(WCD939X_IRQ_EAR_SCD_INT, 1, 0x04),
285 REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
286 REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
287 REGMAP_IRQ_REG(WCD939X_IRQ_EAR_PDM_WD_INT, 1, 0x80),
288 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
289 REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
290 REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
291 };
292
293 static const struct regmap_irq_chip wcd939x_regmap_irq_chip = {
294 .name = "wcd939x",
295 .irqs = wcd939x_irqs,
296 .num_irqs = ARRAY_SIZE(wcd939x_irqs),
297 .num_regs = 3,
298 .status_base = WCD939X_DIGITAL_INTR_STATUS_0,
299 .mask_base = WCD939X_DIGITAL_INTR_MASK_0,
300 .ack_base = WCD939X_DIGITAL_INTR_CLEAR_0,
301 .use_ack = 1,
302 .runtime_pm = true,
303 .irq_drv_data = NULL,
304 };
305
wcd939x_get_clk_rate(int mode)306 static int wcd939x_get_clk_rate(int mode)
307 {
308 int rate;
309
310 switch (mode) {
311 case ADC_MODE_ULP2:
312 rate = SWR_CLK_RATE_0P6MHZ;
313 break;
314 case ADC_MODE_ULP1:
315 rate = SWR_CLK_RATE_1P2MHZ;
316 break;
317 case ADC_MODE_LP:
318 rate = SWR_CLK_RATE_4P8MHZ;
319 break;
320 case ADC_MODE_NORMAL:
321 case ADC_MODE_LO_HIF:
322 case ADC_MODE_HIFI:
323 case ADC_MODE_INVALID:
324 default:
325 rate = SWR_CLK_RATE_9P6MHZ;
326 break;
327 }
328
329 return rate;
330 }
331
wcd939x_set_swr_clk_rate(struct snd_soc_component * component,int rate,int bank)332 static int wcd939x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank)
333 {
334 u8 mask = (bank ? 0xF0 : 0x0F);
335 u8 val = 0;
336
337 switch (rate) {
338 case SWR_CLK_RATE_0P6MHZ:
339 val = 6;
340 break;
341 case SWR_CLK_RATE_1P2MHZ:
342 val = 5;
343 break;
344 case SWR_CLK_RATE_2P4MHZ:
345 val = 3;
346 break;
347 case SWR_CLK_RATE_4P8MHZ:
348 val = 1;
349 break;
350 case SWR_CLK_RATE_9P6MHZ:
351 default:
352 val = 0;
353 break;
354 }
355
356 snd_soc_component_write_field(component, WCD939X_DIGITAL_SWR_TX_CLK_RATE, mask, val);
357
358 return 0;
359 }
360
wcd939x_io_init(struct snd_soc_component * component)361 static int wcd939x_io_init(struct snd_soc_component *component)
362 {
363 snd_soc_component_write_field(component, WCD939X_ANA_BIAS,
364 WCD939X_BIAS_ANALOG_BIAS_EN, true);
365 snd_soc_component_write_field(component, WCD939X_ANA_BIAS,
366 WCD939X_BIAS_PRECHRG_EN, true);
367
368 /* 10 msec delay as per HW requirement */
369 usleep_range(10000, 10010);
370 snd_soc_component_write_field(component, WCD939X_ANA_BIAS,
371 WCD939X_BIAS_PRECHRG_EN, false);
372
373 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L,
374 WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 0x15);
375 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R,
376 WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 0x15);
377 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL,
378 WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN, true);
379
380 snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2CASC_ULP,
381 WCD939X_FE_ICTRL_STG2CASC_ULP_ICTRL_SCBIAS_ULP0P6M, 1);
382 snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2CASC_ULP,
383 WCD939X_FE_ICTRL_STG2CASC_ULP_VALUE, 4);
384
385 snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2MAIN_ULP,
386 WCD939X_FE_ICTRL_STG2MAIN_ULP_VALUE, 8);
387
388 snd_soc_component_write_field(component, WCD939X_MICB1_TEST_CTL_1,
389 WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7);
390 snd_soc_component_write_field(component, WCD939X_MICB2_TEST_CTL_1,
391 WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7);
392 snd_soc_component_write_field(component, WCD939X_MICB3_TEST_CTL_1,
393 WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7);
394 snd_soc_component_write_field(component, WCD939X_MICB4_TEST_CTL_1,
395 WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7);
396 snd_soc_component_write_field(component, WCD939X_TX_3_4_TEST_BLK_EN2,
397 WCD939X_TEST_BLK_EN2_TXFE2_MBHC_CLKRST_EN, false);
398
399 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
400 WCD939X_EN_EN_SURGE_PROTECTION_HPHL, false);
401 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
402 WCD939X_EN_EN_SURGE_PROTECTION_HPHR, false);
403
404 snd_soc_component_write_field(component, WCD939X_HPH_OCP_CTL,
405 WCD939X_OCP_CTL_OCP_FSM_EN, true);
406 snd_soc_component_write_field(component, WCD939X_HPH_OCP_CTL,
407 WCD939X_OCP_CTL_SCD_OP_EN, true);
408
409 snd_soc_component_write(component, WCD939X_E_CFG0,
410 WCD939X_CFG0_IDLE_STEREO |
411 WCD939X_CFG0_AUTO_DISABLE_ANC);
412
413 return 0;
414 }
415
wcd939x_sdw_connect_port(const struct wcd_sdw_ch_info * ch_info,struct sdw_port_config * port_config,u8 enable)416 static int wcd939x_sdw_connect_port(const struct wcd_sdw_ch_info *ch_info,
417 struct sdw_port_config *port_config,
418 u8 enable)
419 {
420 u8 ch_mask, port_num;
421
422 port_num = ch_info->port_num;
423 ch_mask = ch_info->ch_mask;
424
425 port_config->num = port_num;
426
427 if (enable)
428 port_config->ch_mask |= ch_mask;
429 else
430 port_config->ch_mask &= ~ch_mask;
431
432 return 0;
433 }
434
wcd939x_connect_port(struct wcd939x_sdw_priv * wcd,u8 port_num,u8 ch_id,u8 enable)435 static int wcd939x_connect_port(struct wcd939x_sdw_priv *wcd, u8 port_num, u8 ch_id, u8 enable)
436 {
437 return wcd939x_sdw_connect_port(&wcd->ch_info[ch_id],
438 &wcd->port_config[port_num - 1],
439 enable);
440 }
441
wcd939x_codec_enable_rxclk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)442 static int wcd939x_codec_enable_rxclk(struct snd_soc_dapm_widget *w,
443 struct snd_kcontrol *kcontrol,
444 int event)
445 {
446 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
447
448 switch (event) {
449 case SND_SOC_DAPM_PRE_PMU:
450 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
451 WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE, true);
452
453 /* Analog path clock controls */
454 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
455 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN, true);
456 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
457 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN,
458 true);
459 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
460 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN,
461 true);
462
463 /* Digital path clock controls */
464 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
465 WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN, true);
466 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
467 WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN, true);
468 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
469 WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN, true);
470 break;
471 case SND_SOC_DAPM_POST_PMD:
472 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
473 WCD939X_RX_SUPPLIES_VNEG_EN, false);
474 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
475 WCD939X_RX_SUPPLIES_VPOS_EN, false);
476
477 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
478 WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN, false);
479 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
480 WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN, false);
481 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
482 WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN, false);
483
484 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
485 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN,
486 false);
487 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
488 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN,
489 false);
490 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
491 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN, false);
492
493 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
494 WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE, false);
495
496 break;
497 }
498
499 return 0;
500 }
501
wcd939x_codec_hphl_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)502 static int wcd939x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
503 struct snd_kcontrol *kcontrol,
504 int event)
505 {
506 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
507 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
508
509 switch (event) {
510 case SND_SOC_DAPM_PRE_PMU:
511 snd_soc_component_write_field(component, WCD939X_HPH_RDAC_CLK_CTL1,
512 WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN,
513 false);
514
515 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL,
516 WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN, true);
517 break;
518 case SND_SOC_DAPM_POST_PMU:
519 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L,
520 WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 0x1d);
521 if (wcd939x->comp1_enable) {
522 snd_soc_component_write_field(component,
523 WCD939X_DIGITAL_CDC_COMP_CTL_0,
524 WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN,
525 true);
526 /* 5msec compander delay as per HW requirement */
527 if (!wcd939x->comp2_enable ||
528 snd_soc_component_read_field(component,
529 WCD939X_DIGITAL_CDC_COMP_CTL_0,
530 WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN))
531 usleep_range(5000, 5010);
532
533 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1,
534 WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN,
535 false);
536 } else {
537 snd_soc_component_write_field(component,
538 WCD939X_DIGITAL_CDC_COMP_CTL_0,
539 WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN,
540 false);
541 snd_soc_component_write_field(component, WCD939X_HPH_L_EN,
542 WCD939X_L_EN_GAIN_SOURCE_SEL, true);
543 }
544 break;
545 case SND_SOC_DAPM_POST_PMD:
546 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L,
547 WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 1);
548 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL,
549 WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN, false);
550 break;
551 }
552
553 return 0;
554 }
555
wcd939x_codec_hphr_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)556 static int wcd939x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
557 struct snd_kcontrol *kcontrol,
558 int event)
559 {
560 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
561 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
562
563 dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
564 w->name, event);
565
566 switch (event) {
567 case SND_SOC_DAPM_PRE_PMU:
568 snd_soc_component_write_field(component, WCD939X_HPH_RDAC_CLK_CTL1,
569 WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN,
570 false);
571
572 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL,
573 WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN, true);
574 break;
575 case SND_SOC_DAPM_POST_PMU:
576 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R,
577 WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 0x1d);
578 if (wcd939x->comp2_enable) {
579 snd_soc_component_write_field(component,
580 WCD939X_DIGITAL_CDC_COMP_CTL_0,
581 WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN,
582 true);
583 /* 5msec compander delay as per HW requirement */
584 if (!wcd939x->comp1_enable ||
585 snd_soc_component_read_field(component,
586 WCD939X_DIGITAL_CDC_COMP_CTL_0,
587 WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN))
588 usleep_range(5000, 5010);
589 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1,
590 WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN,
591 false);
592 } else {
593 snd_soc_component_write_field(component,
594 WCD939X_DIGITAL_CDC_COMP_CTL_0,
595 WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN,
596 false);
597 snd_soc_component_write_field(component, WCD939X_HPH_R_EN,
598 WCD939X_R_EN_GAIN_SOURCE_SEL, true);
599 }
600 break;
601 case SND_SOC_DAPM_POST_PMD:
602 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R,
603 WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 1);
604 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL,
605 WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN, false);
606 break;
607 }
608
609 return 0;
610 }
611
wcd939x_codec_ear_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)612 static int wcd939x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
613 struct snd_kcontrol *kcontrol,
614 int event)
615 {
616 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
617 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
618
619 switch (event) {
620 case SND_SOC_DAPM_PRE_PMU:
621 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_EAR_GAIN_CTL,
622 WCD939X_CDC_EAR_GAIN_CTL_EAR_EN, true);
623
624 snd_soc_component_write_field(component, WCD939X_EAR_DAC_CON,
625 WCD939X_DAC_CON_DAC_SAMPLE_EDGE_SEL, false);
626
627 /* 5 msec delay as per HW requirement */
628 usleep_range(5000, 5010);
629 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
630 WCD_CLSH_STATE_EAR, CLS_AB_HIFI);
631
632 snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4,
633 WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd);
634 break;
635 case SND_SOC_DAPM_POST_PMD:
636 snd_soc_component_write_field(component, WCD939X_EAR_DAC_CON,
637 WCD939X_DAC_CON_DAC_SAMPLE_EDGE_SEL, true);
638 break;
639 }
640
641 return 0;
642 }
643
wcd939x_codec_enable_hphr_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)644 static int wcd939x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
645 struct snd_kcontrol *kcontrol,
646 int event)
647 {
648 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
649 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
650 int hph_mode = wcd939x->hph_mode;
651
652 switch (event) {
653 case SND_SOC_DAPM_PRE_PMU:
654 if (wcd939x->ldoh)
655 snd_soc_component_write_field(component, WCD939X_LDOH_MODE,
656 WCD939X_MODE_LDOH_EN, true);
657
658 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
659 WCD_CLSH_STATE_HPHR, hph_mode);
660 wcd_clsh_set_hph_mode(wcd939x->clsh_info, CLS_H_HIFI);
661
662 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || hph_mode == CLS_H_ULP)
663 snd_soc_component_write_field(component,
664 WCD939X_HPH_REFBUFF_LP_CTL,
665 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS, true);
666 if (hph_mode == CLS_H_LOHIFI)
667 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
668 WCD939X_HPH_PWR_LEVEL, 0);
669
670 snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4,
671 WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd);
672 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
673 WCD939X_HPH_HPHR_REF_ENABLE, true);
674
675 if (snd_soc_component_read_field(component, WCD939X_ANA_HPH,
676 WCD939X_HPH_HPHL_REF_ENABLE))
677 usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */
678
679 set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
680 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL1,
681 WCD939X_PDM_WD_CTL1_PDM_WD_EN, 3);
682 break;
683 case SND_SOC_DAPM_POST_PMU:
684 /*
685 * 7ms sleep is required if compander is enabled as per
686 * HW requirement. If compander is disabled, then
687 * 20ms delay is required.
688 */
689 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
690 if (!wcd939x->comp2_enable)
691 usleep_range(20000, 20100);
692 else
693 usleep_range(7000, 7100);
694
695 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
696 hph_mode == CLS_H_ULP)
697 snd_soc_component_write_field(component,
698 WCD939X_HPH_REFBUFF_LP_CTL,
699 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS,
700 false);
701 clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
702 }
703 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1,
704 WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN, true);
705 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
706 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
707 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
708 WCD939X_RX_SUPPLIES_REGULATOR_MODE,
709 true);
710
711 enable_irq(wcd939x->hphr_pdm_wd_int);
712 break;
713 case SND_SOC_DAPM_PRE_PMD:
714 disable_irq_nosync(wcd939x->hphr_pdm_wd_int);
715 /*
716 * 7ms sleep is required if compander is enabled as per
717 * HW requirement. If compander is disabled, then
718 * 20ms delay is required.
719 */
720 if (!wcd939x->comp2_enable)
721 usleep_range(20000, 20100);
722 else
723 usleep_range(7000, 7100);
724
725 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
726 WCD939X_HPH_HPHR_ENABLE, false);
727
728 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
729 WCD_EVENT_PRE_HPHR_PA_OFF);
730 set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
731 break;
732 case SND_SOC_DAPM_POST_PMD:
733 /*
734 * 7ms sleep is required if compander is enabled as per
735 * HW requirement. If compander is disabled, then
736 * 20ms delay is required.
737 */
738 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
739 if (!wcd939x->comp2_enable)
740 usleep_range(20000, 20100);
741 else
742 usleep_range(7000, 7100);
743 clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
744 }
745 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
746 WCD_EVENT_POST_HPHR_PA_OFF);
747
748 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
749 WCD939X_HPH_HPHR_REF_ENABLE, false);
750 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL1,
751 WCD939X_PDM_WD_CTL1_PDM_WD_EN, 0);
752
753 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA,
754 WCD_CLSH_STATE_HPHR, hph_mode);
755 if (wcd939x->ldoh)
756 snd_soc_component_write_field(component, WCD939X_LDOH_MODE,
757 WCD939X_MODE_LDOH_EN, false);
758 break;
759 }
760
761 return 0;
762 }
763
wcd939x_codec_enable_hphl_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)764 static int wcd939x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
765 struct snd_kcontrol *kcontrol,
766 int event)
767 {
768 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
769 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
770 int hph_mode = wcd939x->hph_mode;
771
772 dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
773 w->name, event);
774
775 switch (event) {
776 case SND_SOC_DAPM_PRE_PMU:
777 if (wcd939x->ldoh)
778 snd_soc_component_write_field(component, WCD939X_LDOH_MODE,
779 WCD939X_MODE_LDOH_EN, true);
780 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
781 WCD_CLSH_STATE_HPHL, hph_mode);
782 wcd_clsh_set_hph_mode(wcd939x->clsh_info, CLS_H_HIFI);
783
784 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || hph_mode == CLS_H_ULP)
785 snd_soc_component_write_field(component,
786 WCD939X_HPH_REFBUFF_LP_CTL,
787 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS,
788 true);
789 if (hph_mode == CLS_H_LOHIFI)
790 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
791 WCD939X_HPH_PWR_LEVEL, 0);
792
793 snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4,
794 WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd);
795 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
796 WCD939X_HPH_HPHL_REF_ENABLE, true);
797
798 if (snd_soc_component_read_field(component, WCD939X_ANA_HPH,
799 WCD939X_HPH_HPHR_REF_ENABLE))
800 usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */
801
802 set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
803 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0,
804 WCD939X_PDM_WD_CTL0_PDM_WD_EN, 3);
805 break;
806 case SND_SOC_DAPM_POST_PMU:
807 /*
808 * 7ms sleep is required if compander is enabled as per
809 * HW requirement. If compander is disabled, then
810 * 20ms delay is required.
811 */
812 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
813 if (!wcd939x->comp1_enable)
814 usleep_range(20000, 20100);
815 else
816 usleep_range(7000, 7100);
817 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
818 hph_mode == CLS_H_ULP)
819 snd_soc_component_write_field(component,
820 WCD939X_HPH_REFBUFF_LP_CTL,
821 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS,
822 false);
823 clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
824 }
825 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1,
826 WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN, true);
827 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
828 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
829 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
830 WCD939X_RX_SUPPLIES_REGULATOR_MODE,
831 true);
832 enable_irq(wcd939x->hphl_pdm_wd_int);
833 break;
834 case SND_SOC_DAPM_PRE_PMD:
835 disable_irq_nosync(wcd939x->hphl_pdm_wd_int);
836 /*
837 * 7ms sleep is required if compander is enabled as per
838 * HW requirement. If compander is disabled, then
839 * 20ms delay is required.
840 */
841 if (!wcd939x->comp1_enable)
842 usleep_range(20000, 20100);
843 else
844 usleep_range(7000, 7100);
845
846 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
847 WCD939X_HPH_HPHL_ENABLE, false);
848
849 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF);
850 set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
851 break;
852 case SND_SOC_DAPM_POST_PMD:
853 /*
854 * 7ms sleep is required if compander is enabled as per
855 * HW requirement. If compander is disabled, then
856 * 20ms delay is required.
857 */
858 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
859 if (!wcd939x->comp1_enable)
860 usleep_range(21000, 21100);
861 else
862 usleep_range(7000, 7100);
863 clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
864 }
865 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
866 WCD_EVENT_POST_HPHL_PA_OFF);
867 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
868 WCD939X_HPH_HPHL_REF_ENABLE, false);
869 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0,
870 WCD939X_PDM_WD_CTL0_PDM_WD_EN, 0);
871 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA,
872 WCD_CLSH_STATE_HPHL, hph_mode);
873 if (wcd939x->ldoh)
874 snd_soc_component_write_field(component, WCD939X_LDOH_MODE,
875 WCD939X_MODE_LDOH_EN, false);
876 break;
877 }
878
879 return 0;
880 }
881
wcd939x_codec_enable_ear_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)882 static int wcd939x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
883 struct snd_kcontrol *kcontrol, int event)
884 {
885 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
886 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
887
888 switch (event) {
889 case SND_SOC_DAPM_PRE_PMU:
890 /* Enable watchdog interrupt for HPHL */
891 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0,
892 WCD939X_PDM_WD_CTL0_PDM_WD_EN, 3);
893 /* For EAR, use CLASS_AB regulator mode */
894 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
895 WCD939X_RX_SUPPLIES_REGULATOR_MODE, true);
896 snd_soc_component_write_field(component, WCD939X_ANA_EAR_COMPANDER_CTL,
897 WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG, true);
898 break;
899 case SND_SOC_DAPM_POST_PMU:
900 /* 6 msec delay as per HW requirement */
901 usleep_range(6000, 6010);
902 enable_irq(wcd939x->ear_pdm_wd_int);
903 break;
904 case SND_SOC_DAPM_PRE_PMD:
905 disable_irq_nosync(wcd939x->ear_pdm_wd_int);
906 break;
907 case SND_SOC_DAPM_POST_PMD:
908 snd_soc_component_write_field(component, WCD939X_ANA_EAR_COMPANDER_CTL,
909 WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG,
910 false);
911 /* 7 msec delay as per HW requirement */
912 usleep_range(7000, 7010);
913 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0,
914 WCD939X_PDM_WD_CTL0_PDM_WD_EN, 0);
915 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA,
916 WCD_CLSH_STATE_EAR, CLS_AB_HIFI);
917 break;
918 }
919
920 return 0;
921 }
922
923 /* TX Controls */
924
wcd939x_codec_enable_dmic(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)925 static int wcd939x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
926 struct snd_kcontrol *kcontrol,
927 int event)
928 {
929 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
930 u16 dmic_clk_reg, dmic_clk_en_reg;
931 u8 dmic_clk_en_mask;
932 u8 dmic_ctl_mask;
933 u8 dmic_clk_mask;
934
935 switch (w->shift) {
936 case 0:
937 case 1:
938 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_1_2;
939 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC1_CTL;
940 dmic_clk_en_mask = WCD939X_CDC_DMIC1_CTL_DMIC_CLK_EN;
941 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_1_2_DMIC1_RATE;
942 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC1_IN_SEL;
943 break;
944 case 2:
945 case 3:
946 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_1_2;
947 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC2_CTL;
948 dmic_clk_en_mask = WCD939X_CDC_DMIC2_CTL_DMIC_CLK_EN;
949 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_1_2_DMIC2_RATE;
950 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC3_IN_SEL;
951 break;
952 case 4:
953 case 5:
954 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_3_4;
955 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC3_CTL;
956 dmic_clk_en_mask = WCD939X_CDC_DMIC3_CTL_DMIC_CLK_EN;
957 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_3_4_DMIC3_RATE;
958 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC4_IN_SEL;
959 break;
960 case 6:
961 case 7:
962 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_3_4;
963 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC4_CTL;
964 dmic_clk_en_mask = WCD939X_CDC_DMIC4_CTL_DMIC_CLK_EN;
965 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_3_4_DMIC4_RATE;
966 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC5_IN_SEL;
967 break;
968 default:
969 dev_err(component->dev, "%s: Invalid DMIC Selection\n", __func__);
970 return -EINVAL;
971 }
972
973 switch (event) {
974 case SND_SOC_DAPM_PRE_PMU:
975 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_AMIC_CTL,
976 dmic_ctl_mask, false);
977 /* 250us sleep as per HW requirement */
978 usleep_range(250, 260);
979 if (w->shift == 2)
980 snd_soc_component_write_field(component,
981 WCD939X_DIGITAL_CDC_DMIC2_CTL,
982 WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN,
983 true);
984 /* Setting DMIC clock rate to 2.4MHz */
985 snd_soc_component_write_field(component, dmic_clk_reg,
986 dmic_clk_mask, 3);
987 snd_soc_component_write_field(component, dmic_clk_en_reg,
988 dmic_clk_en_mask, true);
989 /* enable clock scaling */
990 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL,
991 WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN, true);
992 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL,
993 WCD939X_CDC_DMIC_CTL_DMIC_DIV_BAK_EN, true);
994 break;
995 case SND_SOC_DAPM_POST_PMD:
996 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_AMIC_CTL,
997 dmic_ctl_mask, 1);
998 if (w->shift == 2)
999 snd_soc_component_write_field(component,
1000 WCD939X_DIGITAL_CDC_DMIC2_CTL,
1001 WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN,
1002 false);
1003 snd_soc_component_write_field(component, dmic_clk_en_reg,
1004 dmic_clk_en_mask, 0);
1005 break;
1006 }
1007 return 0;
1008 }
1009
wcd939x_tx_swr_ctrl(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1010 static int wcd939x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
1011 struct snd_kcontrol *kcontrol, int event)
1012 {
1013 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1014 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1015 int bank;
1016 int rate;
1017
1018 bank = sdw_slave_get_current_bank(wcd939x->sdw_priv[AIF1_CAP]->sdev);
1019
1020 switch (event) {
1021 case SND_SOC_DAPM_PRE_PMU:
1022 if (strnstr(w->name, "ADC", sizeof("ADC"))) {
1023 int mode = 0;
1024
1025 if (test_bit(WCD_ADC1, &wcd939x->status_mask))
1026 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC1]];
1027 if (test_bit(WCD_ADC2, &wcd939x->status_mask))
1028 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC2]];
1029 if (test_bit(WCD_ADC3, &wcd939x->status_mask))
1030 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC3]];
1031 if (test_bit(WCD_ADC4, &wcd939x->status_mask))
1032 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC4]];
1033
1034 if (mode)
1035 rate = wcd939x_get_clk_rate(ffs(mode) - 1);
1036 else
1037 rate = wcd939x_get_clk_rate(ADC_MODE_INVALID);
1038 wcd939x_set_swr_clk_rate(component, rate, bank);
1039 wcd939x_set_swr_clk_rate(component, rate, !bank);
1040 }
1041 break;
1042 case SND_SOC_DAPM_POST_PMD:
1043 if (strnstr(w->name, "ADC", sizeof("ADC"))) {
1044 rate = wcd939x_get_clk_rate(ADC_MODE_INVALID);
1045 wcd939x_set_swr_clk_rate(component, rate, !bank);
1046 wcd939x_set_swr_clk_rate(component, rate, bank);
1047 }
1048 break;
1049 }
1050
1051 return 0;
1052 }
1053
wcd939x_get_adc_mode(int val)1054 static int wcd939x_get_adc_mode(int val)
1055 {
1056 int ret = 0;
1057
1058 switch (val) {
1059 case ADC_MODE_INVALID:
1060 ret = ADC_MODE_VAL_NORMAL;
1061 break;
1062 case ADC_MODE_HIFI:
1063 ret = ADC_MODE_VAL_HIFI;
1064 break;
1065 case ADC_MODE_LO_HIF:
1066 ret = ADC_MODE_VAL_LO_HIF;
1067 break;
1068 case ADC_MODE_NORMAL:
1069 ret = ADC_MODE_VAL_NORMAL;
1070 break;
1071 case ADC_MODE_LP:
1072 ret = ADC_MODE_VAL_LP;
1073 break;
1074 case ADC_MODE_ULP1:
1075 ret = ADC_MODE_VAL_ULP1;
1076 break;
1077 case ADC_MODE_ULP2:
1078 ret = ADC_MODE_VAL_ULP2;
1079 break;
1080 default:
1081 ret = -EINVAL;
1082 break;
1083 }
1084 return ret;
1085 }
1086
wcd939x_codec_enable_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1087 static int wcd939x_codec_enable_adc(struct snd_soc_dapm_widget *w,
1088 struct snd_kcontrol *kcontrol, int event)
1089 {
1090 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1091 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1092
1093 switch (event) {
1094 case SND_SOC_DAPM_PRE_PMU:
1095 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1096 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN, true);
1097 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1098 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN,
1099 true);
1100 set_bit(w->shift, &wcd939x->status_mask);
1101 break;
1102 case SND_SOC_DAPM_POST_PMD:
1103 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1104 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN,
1105 false);
1106 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1107 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN,
1108 false);
1109 clear_bit(w->shift, &wcd939x->status_mask);
1110 break;
1111 }
1112
1113 return 0;
1114 }
1115
wcd939x_tx_channel_config(struct snd_soc_component * component,int channel,bool init)1116 static void wcd939x_tx_channel_config(struct snd_soc_component *component,
1117 int channel, bool init)
1118 {
1119 int reg, mask;
1120
1121 switch (channel) {
1122 case 0:
1123 reg = WCD939X_ANA_TX_CH2;
1124 mask = WCD939X_TX_CH2_HPF1_INIT;
1125 break;
1126 case 1:
1127 reg = WCD939X_ANA_TX_CH2;
1128 mask = WCD939X_TX_CH2_HPF2_INIT;
1129 break;
1130 case 2:
1131 reg = WCD939X_ANA_TX_CH4;
1132 mask = WCD939X_TX_CH4_HPF3_INIT;
1133 break;
1134 case 3:
1135 reg = WCD939X_ANA_TX_CH4;
1136 mask = WCD939X_TX_CH4_HPF4_INIT;
1137 break;
1138 default:
1139 return;
1140 }
1141
1142 snd_soc_component_write_field(component, reg, mask, init);
1143 }
1144
wcd939x_adc_enable_req(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1145 static int wcd939x_adc_enable_req(struct snd_soc_dapm_widget *w,
1146 struct snd_kcontrol *kcontrol, int event)
1147 {
1148 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1149 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1150 int mode;
1151
1152 switch (event) {
1153 case SND_SOC_DAPM_PRE_PMU:
1154 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_REQ_CTL,
1155 WCD939X_CDC_REQ_CTL_FS_RATE_4P8, true);
1156 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_REQ_CTL,
1157 WCD939X_CDC_REQ_CTL_NO_NOTCH, false);
1158
1159 wcd939x_tx_channel_config(component, w->shift, true);
1160 mode = wcd939x_get_adc_mode(wcd939x->tx_mode[w->shift]);
1161 if (mode < 0) {
1162 dev_info(component->dev, "Invalid ADC mode\n");
1163 return -EINVAL;
1164 }
1165
1166 switch (w->shift) {
1167 case 0:
1168 snd_soc_component_write_field(component,
1169 WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1170 WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE,
1171 mode);
1172 snd_soc_component_write_field(component,
1173 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1174 WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN,
1175 true);
1176 break;
1177 case 1:
1178 snd_soc_component_write_field(component,
1179 WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1180 WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE,
1181 mode);
1182 snd_soc_component_write_field(component,
1183 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1184 WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN,
1185 true);
1186 break;
1187 case 2:
1188 snd_soc_component_write_field(component,
1189 WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1190 WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE,
1191 mode);
1192 snd_soc_component_write_field(component,
1193 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1194 WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN,
1195 true);
1196 break;
1197 case 3:
1198 snd_soc_component_write_field(component,
1199 WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1200 WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE,
1201 mode);
1202 snd_soc_component_write_field(component,
1203 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1204 WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN,
1205 true);
1206 break;
1207 default:
1208 break;
1209 }
1210
1211 wcd939x_tx_channel_config(component, w->shift, false);
1212 break;
1213 case SND_SOC_DAPM_POST_PMD:
1214 switch (w->shift) {
1215 case 0:
1216 snd_soc_component_write_field(component,
1217 WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1218 WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE,
1219 false);
1220 snd_soc_component_write_field(component,
1221 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1222 WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN,
1223 false);
1224 break;
1225 case 1:
1226 snd_soc_component_write_field(component,
1227 WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1228 WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE,
1229 false);
1230 snd_soc_component_write_field(component,
1231 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1232 WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN,
1233 false);
1234 break;
1235 case 2:
1236 snd_soc_component_write_field(component,
1237 WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1238 WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE,
1239 false);
1240 snd_soc_component_write_field(component,
1241 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1242 WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN,
1243 false);
1244 break;
1245 case 3:
1246 snd_soc_component_write_field(component,
1247 WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1248 WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE,
1249 false);
1250 snd_soc_component_write_field(component,
1251 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1252 WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN,
1253 false);
1254 break;
1255 default:
1256 break;
1257 }
1258 break;
1259 }
1260
1261 return 0;
1262 }
1263
wcd939x_micbias_control(struct snd_soc_component * component,int micb_num,int req,bool is_dapm)1264 static int wcd939x_micbias_control(struct snd_soc_component *component,
1265 int micb_num, int req, bool is_dapm)
1266 {
1267 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1268 int micb_index = micb_num - 1;
1269 u16 micb_reg;
1270
1271 switch (micb_num) {
1272 case MIC_BIAS_1:
1273 micb_reg = WCD939X_ANA_MICB1;
1274 break;
1275 case MIC_BIAS_2:
1276 micb_reg = WCD939X_ANA_MICB2;
1277 break;
1278 case MIC_BIAS_3:
1279 micb_reg = WCD939X_ANA_MICB3;
1280 break;
1281 case MIC_BIAS_4:
1282 micb_reg = WCD939X_ANA_MICB4;
1283 break;
1284 default:
1285 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
1286 __func__, micb_num);
1287 return -EINVAL;
1288 }
1289
1290 switch (req) {
1291 case MICB_PULLUP_ENABLE:
1292 wcd939x->pullup_ref[micb_index]++;
1293 if (wcd939x->pullup_ref[micb_index] == 1 &&
1294 wcd939x->micb_ref[micb_index] == 0)
1295 snd_soc_component_write_field(component, micb_reg,
1296 WCD939X_MICB_ENABLE,
1297 MICB_BIAS_PULL_UP);
1298 break;
1299 case MICB_PULLUP_DISABLE:
1300 if (wcd939x->pullup_ref[micb_index] > 0)
1301 wcd939x->pullup_ref[micb_index]--;
1302 if (wcd939x->pullup_ref[micb_index] == 0 &&
1303 wcd939x->micb_ref[micb_index] == 0)
1304 snd_soc_component_write_field(component, micb_reg,
1305 WCD939X_MICB_ENABLE,
1306 MICB_BIAS_DISABLE);
1307 break;
1308 case MICB_ENABLE:
1309 wcd939x->micb_ref[micb_index]++;
1310 if (wcd939x->micb_ref[micb_index] == 1) {
1311 snd_soc_component_write_field(component,
1312 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1313 WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN, true);
1314 snd_soc_component_write_field(component,
1315 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1316 WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN, true);
1317 snd_soc_component_write_field(component,
1318 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1319 WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN, true);
1320 snd_soc_component_write_field(component,
1321 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1322 WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN, true);
1323 snd_soc_component_write_field(component,
1324 WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1325 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN,
1326 true);
1327 snd_soc_component_write_field(component,
1328 WCD939X_DIGITAL_CDC_ANA_TX_CLK_CTL,
1329 WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TXSCBIAS_CLK_EN,
1330 true);
1331 snd_soc_component_write_field(component,
1332 WCD939X_MICB1_TEST_CTL_2,
1333 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true);
1334 snd_soc_component_write_field(component,
1335 WCD939X_MICB2_TEST_CTL_2,
1336 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true);
1337 snd_soc_component_write_field(component,
1338 WCD939X_MICB3_TEST_CTL_2,
1339 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true);
1340 snd_soc_component_write_field(component,
1341 WCD939X_MICB4_TEST_CTL_2,
1342 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true);
1343 snd_soc_component_write_field(component, micb_reg,
1344 WCD939X_MICB_ENABLE,
1345 MICB_BIAS_ENABLE);
1346 if (micb_num == MIC_BIAS_2)
1347 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1348 WCD_EVENT_POST_MICBIAS_2_ON);
1349 }
1350 if (micb_num == MIC_BIAS_2 && is_dapm)
1351 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1352 WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
1353 break;
1354 case MICB_DISABLE:
1355 if (wcd939x->micb_ref[micb_index] > 0)
1356 wcd939x->micb_ref[micb_index]--;
1357
1358 if (wcd939x->micb_ref[micb_index] == 0 &&
1359 wcd939x->pullup_ref[micb_index] > 0)
1360 snd_soc_component_write_field(component, micb_reg,
1361 WCD939X_MICB_ENABLE,
1362 MICB_BIAS_PULL_UP);
1363 else if (wcd939x->micb_ref[micb_index] == 0 &&
1364 wcd939x->pullup_ref[micb_index] == 0) {
1365 if (micb_num == MIC_BIAS_2)
1366 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1367 WCD_EVENT_PRE_MICBIAS_2_OFF);
1368
1369 snd_soc_component_write_field(component, micb_reg,
1370 WCD939X_MICB_ENABLE,
1371 MICB_BIAS_DISABLE);
1372 if (micb_num == MIC_BIAS_2)
1373 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1374 WCD_EVENT_POST_MICBIAS_2_OFF);
1375 }
1376 if (is_dapm && micb_num == MIC_BIAS_2)
1377 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1378 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
1379 break;
1380 }
1381
1382 return 0;
1383 }
1384
wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1385 static int wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
1386 struct snd_kcontrol *kcontrol,
1387 int event)
1388 {
1389 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1390 int micb_num = w->shift;
1391
1392 switch (event) {
1393 case SND_SOC_DAPM_PRE_PMU:
1394 wcd939x_micbias_control(component, micb_num, MICB_ENABLE, true);
1395 break;
1396 case SND_SOC_DAPM_POST_PMU:
1397 /* 1 msec delay as per HW requirement */
1398 usleep_range(1000, 1100);
1399 break;
1400 case SND_SOC_DAPM_POST_PMD:
1401 wcd939x_micbias_control(component, micb_num, MICB_DISABLE, true);
1402 break;
1403 }
1404
1405 return 0;
1406 }
1407
wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1408 static int wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
1409 struct snd_kcontrol *kcontrol,
1410 int event)
1411 {
1412 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1413 int micb_num = w->shift;
1414
1415 switch (event) {
1416 case SND_SOC_DAPM_PRE_PMU:
1417 wcd939x_micbias_control(component, micb_num,
1418 MICB_PULLUP_ENABLE, true);
1419 break;
1420 case SND_SOC_DAPM_POST_PMU:
1421 /* 1 msec delay as per HW requirement */
1422 usleep_range(1000, 1100);
1423 break;
1424 case SND_SOC_DAPM_POST_PMD:
1425 wcd939x_micbias_control(component, micb_num,
1426 MICB_PULLUP_DISABLE, true);
1427 break;
1428 }
1429
1430 return 0;
1431 }
1432
wcd939x_tx_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1433 static int wcd939x_tx_mode_get(struct snd_kcontrol *kcontrol,
1434 struct snd_ctl_elem_value *ucontrol)
1435 {
1436 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1437 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1438 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1439 int path = e->shift_l;
1440
1441 ucontrol->value.enumerated.item[0] = wcd939x->tx_mode[path];
1442
1443 return 0;
1444 }
1445
wcd939x_tx_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1446 static int wcd939x_tx_mode_put(struct snd_kcontrol *kcontrol,
1447 struct snd_ctl_elem_value *ucontrol)
1448 {
1449 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1450 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1451 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1452 int path = e->shift_l;
1453
1454 if (wcd939x->tx_mode[path] == ucontrol->value.enumerated.item[0])
1455 return 0;
1456
1457 wcd939x->tx_mode[path] = ucontrol->value.enumerated.item[0];
1458
1459 return 1;
1460 }
1461
1462 /* RX Controls */
1463
wcd939x_rx_hph_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1464 static int wcd939x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
1465 struct snd_ctl_elem_value *ucontrol)
1466 {
1467 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1468 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1469
1470 ucontrol->value.integer.value[0] = wcd939x->hph_mode;
1471
1472 return 0;
1473 }
1474
wcd939x_rx_hph_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1475 static int wcd939x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
1476 struct snd_ctl_elem_value *ucontrol)
1477 {
1478 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1479 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1480 u32 mode_val;
1481
1482 mode_val = ucontrol->value.enumerated.item[0];
1483
1484 if (mode_val == wcd939x->hph_mode)
1485 return 0;
1486
1487 if (wcd939x->variant == CHIPID_WCD9390) {
1488 switch (mode_val) {
1489 case CLS_H_NORMAL:
1490 case CLS_H_LP:
1491 case CLS_AB:
1492 case CLS_H_LOHIFI:
1493 case CLS_H_ULP:
1494 case CLS_AB_LP:
1495 case CLS_AB_LOHIFI:
1496 wcd939x->hph_mode = mode_val;
1497 return 1;
1498 }
1499 } else {
1500 switch (mode_val) {
1501 case CLS_H_NORMAL:
1502 case CLS_H_HIFI:
1503 case CLS_H_LP:
1504 case CLS_AB:
1505 case CLS_H_LOHIFI:
1506 case CLS_H_ULP:
1507 case CLS_AB_HIFI:
1508 case CLS_AB_LP:
1509 case CLS_AB_LOHIFI:
1510 wcd939x->hph_mode = mode_val;
1511 return 1;
1512 }
1513 }
1514
1515 dev_dbg(component->dev, "%s: Invalid HPH Mode\n", __func__);
1516 return -EINVAL;
1517 }
1518
wcd939x_get_compander(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1519 static int wcd939x_get_compander(struct snd_kcontrol *kcontrol,
1520 struct snd_ctl_elem_value *ucontrol)
1521 {
1522 struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value);
1523 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1524 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1525
1526 if (mc->shift)
1527 ucontrol->value.integer.value[0] = wcd939x->comp2_enable ? 1 : 0;
1528 else
1529 ucontrol->value.integer.value[0] = wcd939x->comp1_enable ? 1 : 0;
1530
1531 return 0;
1532 }
1533
wcd939x_set_compander(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1534 static int wcd939x_set_compander(struct snd_kcontrol *kcontrol,
1535 struct snd_ctl_elem_value *ucontrol)
1536 {
1537 struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value);
1538 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1539 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1540 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[AIF1_PB];
1541 bool value = !!ucontrol->value.integer.value[0];
1542 int portidx = wcd->ch_info[mc->reg].port_num;
1543
1544 if (mc->shift)
1545 wcd939x->comp2_enable = value;
1546 else
1547 wcd939x->comp1_enable = value;
1548
1549 if (value)
1550 wcd939x_connect_port(wcd, portidx, mc->reg, true);
1551 else
1552 wcd939x_connect_port(wcd, portidx, mc->reg, false);
1553
1554 return 1;
1555 }
1556
wcd939x_ldoh_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1557 static int wcd939x_ldoh_get(struct snd_kcontrol *kcontrol,
1558 struct snd_ctl_elem_value *ucontrol)
1559 {
1560 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1561 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1562
1563 ucontrol->value.integer.value[0] = wcd939x->ldoh ? 1 : 0;
1564
1565 return 0;
1566 }
1567
wcd939x_ldoh_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1568 static int wcd939x_ldoh_put(struct snd_kcontrol *kcontrol,
1569 struct snd_ctl_elem_value *ucontrol)
1570 {
1571 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1572 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1573
1574 if (wcd939x->ldoh == !!ucontrol->value.integer.value[0])
1575 return 0;
1576
1577 wcd939x->ldoh = !!ucontrol->value.integer.value[0];
1578
1579 return 1;
1580 }
1581
1582 static const char * const tx_mode_mux_text_wcd9390[] = {
1583 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
1584 };
1585
1586 static const struct soc_enum tx0_mode_mux_enum_wcd9390 =
1587 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9390),
1588 tx_mode_mux_text_wcd9390);
1589
1590 static const struct soc_enum tx1_mode_mux_enum_wcd9390 =
1591 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9390),
1592 tx_mode_mux_text_wcd9390);
1593
1594 static const struct soc_enum tx2_mode_mux_enum_wcd9390 =
1595 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9390),
1596 tx_mode_mux_text_wcd9390);
1597
1598 static const struct soc_enum tx3_mode_mux_enum_wcd9390 =
1599 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9390),
1600 tx_mode_mux_text_wcd9390);
1601
1602 static const char * const tx_mode_mux_text[] = {
1603 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
1604 "ADC_ULP1", "ADC_ULP2",
1605 };
1606
1607 static const struct soc_enum tx0_mode_mux_enum =
1608 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text),
1609 tx_mode_mux_text);
1610
1611 static const struct soc_enum tx1_mode_mux_enum =
1612 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text),
1613 tx_mode_mux_text);
1614
1615 static const struct soc_enum tx2_mode_mux_enum =
1616 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text),
1617 tx_mode_mux_text);
1618
1619 static const struct soc_enum tx3_mode_mux_enum =
1620 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text),
1621 tx_mode_mux_text);
1622
1623 static const char * const rx_hph_mode_mux_text_wcd9390[] = {
1624 "CLS_H_NORMAL", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
1625 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
1626 "CLS_AB_LOHIFI",
1627 };
1628
1629 static const struct soc_enum rx_hph_mode_mux_enum_wcd9390 =
1630 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9390),
1631 rx_hph_mode_mux_text_wcd9390);
1632
1633 static const char * const rx_hph_mode_mux_text[] = {
1634 "CLS_H_NORMAL", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
1635 "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
1636 };
1637
1638 static const struct soc_enum rx_hph_mode_mux_enum =
1639 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
1640 rx_hph_mode_mux_text);
1641
1642 static const struct snd_kcontrol_new wcd9390_snd_controls[] = {
1643 SOC_SINGLE_TLV("EAR_PA Volume", WCD939X_ANA_EAR_COMPANDER_CTL,
1644 2, 0x10, 0, ear_pa_gain),
1645
1646 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9390,
1647 wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
1648
1649 SOC_ENUM_EXT("TX0 MODE", tx0_mode_mux_enum_wcd9390,
1650 wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1651 SOC_ENUM_EXT("TX1 MODE", tx1_mode_mux_enum_wcd9390,
1652 wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1653 SOC_ENUM_EXT("TX2 MODE", tx2_mode_mux_enum_wcd9390,
1654 wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1655 SOC_ENUM_EXT("TX3 MODE", tx3_mode_mux_enum_wcd9390,
1656 wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1657 };
1658
1659 static const struct snd_kcontrol_new wcd9395_snd_controls[] = {
1660 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
1661 wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
1662
1663 SOC_ENUM_EXT("TX0 MODE", tx0_mode_mux_enum,
1664 wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1665 SOC_ENUM_EXT("TX1 MODE", tx1_mode_mux_enum,
1666 wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1667 SOC_ENUM_EXT("TX2 MODE", tx2_mode_mux_enum,
1668 wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1669 SOC_ENUM_EXT("TX3 MODE", tx3_mode_mux_enum,
1670 wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1671 };
1672
1673 static const struct snd_kcontrol_new adc1_switch[] = {
1674 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1675 };
1676
1677 static const struct snd_kcontrol_new adc2_switch[] = {
1678 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1679 };
1680
1681 static const struct snd_kcontrol_new adc3_switch[] = {
1682 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1683 };
1684
1685 static const struct snd_kcontrol_new adc4_switch[] = {
1686 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1687 };
1688
1689 static const struct snd_kcontrol_new dmic1_switch[] = {
1690 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1691 };
1692
1693 static const struct snd_kcontrol_new dmic2_switch[] = {
1694 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1695 };
1696
1697 static const struct snd_kcontrol_new dmic3_switch[] = {
1698 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1699 };
1700
1701 static const struct snd_kcontrol_new dmic4_switch[] = {
1702 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1703 };
1704
1705 static const struct snd_kcontrol_new dmic5_switch[] = {
1706 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1707 };
1708
1709 static const struct snd_kcontrol_new dmic6_switch[] = {
1710 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1711 };
1712
1713 static const struct snd_kcontrol_new dmic7_switch[] = {
1714 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1715 };
1716
1717 static const struct snd_kcontrol_new dmic8_switch[] = {
1718 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1719 };
1720
1721 static const struct snd_kcontrol_new ear_rdac_switch[] = {
1722 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1723 };
1724
1725 static const struct snd_kcontrol_new hphl_rdac_switch[] = {
1726 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1727 };
1728
1729 static const struct snd_kcontrol_new hphr_rdac_switch[] = {
1730 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1731 };
1732
1733 static const char * const adc1_mux_text[] = {
1734 "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4", "CH1_AMIC5"
1735 };
1736
1737 static const struct soc_enum adc1_enum =
1738 SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH12_MUX, 0,
1739 ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
1740
1741 static const struct snd_kcontrol_new tx_adc1_mux =
1742 SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
1743
1744 static const char * const adc2_mux_text[] = {
1745 "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4", "CH2_AMIC5"
1746 };
1747
1748 static const struct soc_enum adc2_enum =
1749 SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH12_MUX, 3,
1750 ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
1751
1752 static const struct snd_kcontrol_new tx_adc2_mux =
1753 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
1754
1755 static const char * const adc3_mux_text[] = {
1756 "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC3", "CH3_AMIC4", "CH3_AMIC5"
1757 };
1758
1759 static const struct soc_enum adc3_enum =
1760 SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH34_MUX, 0,
1761 ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
1762
1763 static const struct snd_kcontrol_new tx_adc3_mux =
1764 SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
1765
1766 static const char * const adc4_mux_text[] = {
1767 "CH4_AMIC_DISABLE", "CH4_AMIC1", "CH4_AMIC3", "CH4_AMIC4", "CH4_AMIC5"
1768 };
1769
1770 static const struct soc_enum adc4_enum =
1771 SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH34_MUX, 3,
1772 ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
1773
1774 static const struct snd_kcontrol_new tx_adc4_mux =
1775 SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
1776
1777 static const char * const rdac3_mux_text[] = {
1778 "RX3", "RX1"
1779 };
1780
1781 static const struct soc_enum rdac3_enum =
1782 SOC_ENUM_SINGLE(WCD939X_DIGITAL_CDC_EAR_PATH_CTL, 0,
1783 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
1784
1785 static const struct snd_kcontrol_new rx_rdac3_mux =
1786 SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
1787
wcd939x_get_swr_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1788 static int wcd939x_get_swr_port(struct snd_kcontrol *kcontrol,
1789 struct snd_ctl_elem_value *ucontrol)
1790 {
1791 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1792 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
1793 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(comp);
1794 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[mixer->shift];
1795 unsigned int portidx = wcd->ch_info[mixer->reg].port_num;
1796
1797 ucontrol->value.integer.value[0] = wcd->port_enable[portidx] ? 1 : 0;
1798
1799 return 0;
1800 }
1801
version_to_str(u32 version)1802 static const char *version_to_str(u32 version)
1803 {
1804 switch (version) {
1805 case WCD939X_VERSION_1_0:
1806 return __stringify(WCD939X_1_0);
1807 case WCD939X_VERSION_1_1:
1808 return __stringify(WCD939X_1_1);
1809 case WCD939X_VERSION_2_0:
1810 return __stringify(WCD939X_2_0);
1811 }
1812 return NULL;
1813 }
1814
wcd939x_set_swr_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1815 static int wcd939x_set_swr_port(struct snd_kcontrol *kcontrol,
1816 struct snd_ctl_elem_value *ucontrol)
1817 {
1818 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1819 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
1820 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(comp);
1821 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[mixer->shift];
1822 unsigned int portidx = wcd->ch_info[mixer->reg].port_num;
1823
1824 wcd->port_enable[portidx] = !!ucontrol->value.integer.value[0];
1825
1826 wcd939x_connect_port(wcd, portidx, mixer->reg, wcd->port_enable[portidx]);
1827
1828 return 1;
1829 }
1830
1831 /* MBHC Related */
1832
wcd939x_mbhc_clk_setup(struct snd_soc_component * component,bool enable)1833 static void wcd939x_mbhc_clk_setup(struct snd_soc_component *component,
1834 bool enable)
1835 {
1836 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_1,
1837 WCD939X_CTL_1_RCO_EN, enable);
1838 }
1839
wcd939x_mbhc_mbhc_bias_control(struct snd_soc_component * component,bool enable)1840 static void wcd939x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
1841 bool enable)
1842 {
1843 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT,
1844 WCD939X_MBHC_ELECT_BIAS_EN, enable);
1845 }
1846
wcd939x_mbhc_program_btn_thr(struct snd_soc_component * component,int * btn_low,int * btn_high,int num_btn,bool is_micbias)1847 static void wcd939x_mbhc_program_btn_thr(struct snd_soc_component *component,
1848 int *btn_low, int *btn_high,
1849 int num_btn, bool is_micbias)
1850 {
1851 int i, vth;
1852
1853 if (num_btn > WCD_MBHC_DEF_BUTTONS) {
1854 dev_err(component->dev, "%s: invalid number of buttons: %d\n",
1855 __func__, num_btn);
1856 return;
1857 }
1858
1859 for (i = 0; i < num_btn; i++) {
1860 vth = (btn_high[i] * 2) / 25;
1861 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_BTN0 + i,
1862 WCD939X_MBHC_BTN0_VTH, vth);
1863 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n",
1864 __func__, i, btn_high[i], vth);
1865 }
1866 }
1867
wcd939x_mbhc_micb_en_status(struct snd_soc_component * component,int micb_num)1868 static bool wcd939x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
1869 {
1870 if (micb_num == MIC_BIAS_2) {
1871 u8 val;
1872
1873 val = FIELD_GET(WCD939X_MICB_ENABLE,
1874 snd_soc_component_read(component, WCD939X_ANA_MICB2));
1875 if (val == MICB_BIAS_ENABLE)
1876 return true;
1877 }
1878
1879 return false;
1880 }
1881
wcd939x_mbhc_hph_l_pull_up_control(struct snd_soc_component * component,int pull_up_cur)1882 static void wcd939x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
1883 int pull_up_cur)
1884 {
1885 /* Default pull up current to 2uA */
1886 if (pull_up_cur > HS_PULLUP_I_OFF ||
1887 pull_up_cur < HS_PULLUP_I_3P0_UA ||
1888 pull_up_cur == HS_PULLUP_I_DEFAULT)
1889 pull_up_cur = HS_PULLUP_I_2P0_UA;
1890
1891 dev_dbg(component->dev, "%s: HS pull up current:%d\n",
1892 __func__, pull_up_cur);
1893
1894 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_INT_MECH_DET_CURRENT,
1895 WCD939X_MECH_DET_CURRENT_HSDET_PULLUP_CTL, pull_up_cur);
1896 }
1897
wcd939x_mbhc_request_micbias(struct snd_soc_component * component,int micb_num,int req)1898 static int wcd939x_mbhc_request_micbias(struct snd_soc_component *component,
1899 int micb_num, int req)
1900 {
1901 return wcd939x_micbias_control(component, micb_num, req, false);
1902 }
1903
wcd939x_mbhc_micb_ramp_control(struct snd_soc_component * component,bool enable)1904 static void wcd939x_mbhc_micb_ramp_control(struct snd_soc_component *component,
1905 bool enable)
1906 {
1907 if (enable) {
1908 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP,
1909 WCD939X_MICB2_RAMP_SHIFT_CTL, 3);
1910 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP,
1911 WCD939X_MICB2_RAMP_RAMP_ENABLE, true);
1912 } else {
1913 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP,
1914 WCD939X_MICB2_RAMP_RAMP_ENABLE, false);
1915 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP,
1916 WCD939X_MICB2_RAMP_SHIFT_CTL, 0);
1917 }
1918 }
1919
wcd939x_mbhc_micb_adjust_voltage(struct snd_soc_component * component,int req_volt,int micb_num)1920 static int wcd939x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
1921 int req_volt, int micb_num)
1922 {
1923 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1924 unsigned int micb_reg, cur_vout_ctl, micb_en;
1925 int req_vout_ctl;
1926 int ret = 0;
1927
1928 switch (micb_num) {
1929 case MIC_BIAS_1:
1930 micb_reg = WCD939X_ANA_MICB1;
1931 break;
1932 case MIC_BIAS_2:
1933 micb_reg = WCD939X_ANA_MICB2;
1934 break;
1935 case MIC_BIAS_3:
1936 micb_reg = WCD939X_ANA_MICB3;
1937 break;
1938 case MIC_BIAS_4:
1939 micb_reg = WCD939X_ANA_MICB4;
1940 break;
1941 default:
1942 return -EINVAL;
1943 }
1944 mutex_lock(&wcd939x->micb_lock);
1945
1946 /*
1947 * If requested micbias voltage is same as current micbias
1948 * voltage, then just return. Otherwise, adjust voltage as
1949 * per requested value. If micbias is already enabled, then
1950 * to avoid slow micbias ramp-up or down enable pull-up
1951 * momentarily, change the micbias value and then re-enable
1952 * micbias.
1953 */
1954 micb_en = snd_soc_component_read_field(component, micb_reg,
1955 WCD939X_MICB_ENABLE);
1956 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
1957 WCD939X_MICB_VOUT_CTL);
1958
1959 req_vout_ctl = wcd_get_micb_vout_ctl_val(component->dev, req_volt);
1960 if (req_vout_ctl < 0) {
1961 ret = req_vout_ctl;
1962 goto exit;
1963 }
1964
1965 if (cur_vout_ctl == req_vout_ctl) {
1966 ret = 0;
1967 goto exit;
1968 }
1969
1970 dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
1971 __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
1972 req_volt, micb_en);
1973
1974 if (micb_en == MICB_BIAS_ENABLE)
1975 snd_soc_component_write_field(component, micb_reg,
1976 WCD939X_MICB_ENABLE,
1977 MICB_BIAS_PULL_DOWN);
1978
1979 snd_soc_component_write_field(component, micb_reg,
1980 WCD939X_MICB_VOUT_CTL, req_vout_ctl);
1981
1982 if (micb_en == MICB_BIAS_ENABLE) {
1983 snd_soc_component_write_field(component, micb_reg,
1984 WCD939X_MICB_ENABLE,
1985 MICB_BIAS_ENABLE);
1986 /*
1987 * Add 2ms delay as per HW requirement after enabling
1988 * micbias
1989 */
1990 usleep_range(2000, 2100);
1991 }
1992
1993 exit:
1994 mutex_unlock(&wcd939x->micb_lock);
1995 return ret;
1996 }
1997
wcd939x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component * component,int micb_num,bool req_en)1998 static int wcd939x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
1999 int micb_num, bool req_en)
2000 {
2001 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2002 int micb_mv;
2003
2004 if (micb_num != MIC_BIAS_2)
2005 return -EINVAL;
2006 /*
2007 * If device tree micbias level is already above the minimum
2008 * voltage needed to detect threshold microphone, then do
2009 * not change the micbias, just return.
2010 */
2011 if (wcd939x->common.micb_mv[1] >= WCD_MBHC_THR_HS_MICB_MV)
2012 return 0;
2013
2014 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd939x->common.micb_mv[1];
2015
2016 return wcd939x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
2017 }
2018
2019 /* Selected by WCD939X_MBHC_GET_C1() */
2020 static const s16 wcd939x_wcd_mbhc_d1_a[4] = {
2021 0, 30, 30, 6
2022 };
2023
2024 /* Selected by zdet_param.noff */
2025 static const int wcd939x_mbhc_mincode_param[] = {
2026 3277, 1639, 820, 410, 205, 103, 52, 26
2027 };
2028
2029 static const struct zdet_param wcd939x_mbhc_zdet_param = {
2030 .ldo_ctl = 4,
2031 .noff = 0,
2032 .nshift = 6,
2033 .btn5 = 0x18,
2034 .btn6 = 0x60,
2035 .btn7 = 0x78,
2036 };
2037
wcd939x_mbhc_get_result_params(struct snd_soc_component * component,int32_t * zdet)2038 static void wcd939x_mbhc_get_result_params(struct snd_soc_component *component,
2039 int32_t *zdet)
2040 {
2041 const struct zdet_param *zdet_param = &wcd939x_mbhc_zdet_param;
2042 s32 x1, d1, denom;
2043 int val;
2044 s16 c1;
2045 int i;
2046
2047 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2048 WCD939X_MBHC_ZDET_ZDET_CHG_EN, true);
2049 for (i = 0; i < WCD939X_ZDET_NUM_MEASUREMENTS; i++) {
2050 val = snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_2,
2051 WCD939X_MBHC_RESULT_2_Z_RESULT_MSB);
2052 if (val & BIT(7))
2053 break;
2054 }
2055 val = val << 8;
2056 val |= snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_1,
2057 WCD939X_MBHC_RESULT_1_Z_RESULT_LSB);
2058 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2059 WCD939X_MBHC_ZDET_ZDET_CHG_EN, false);
2060 x1 = WCD939X_MBHC_GET_X1(val);
2061 c1 = WCD939X_MBHC_GET_C1(val);
2062
2063 /* If ramp is not complete, give additional 5ms */
2064 if (c1 < 2 && x1)
2065 mdelay(5);
2066
2067 if (!c1 || !x1) {
2068 dev_dbg(component->dev,
2069 "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
2070 __func__, c1, x1);
2071 goto ramp_down;
2072 }
2073
2074 d1 = wcd939x_wcd_mbhc_d1_a[c1];
2075 denom = (x1 * d1) - (1 << (14 - zdet_param->noff));
2076 if (denom > 0)
2077 *zdet = (WCD939X_ANA_MBHC_ZDET_CONST * 1000) / denom;
2078 else if (x1 < wcd939x_mbhc_mincode_param[zdet_param->noff])
2079 *zdet = WCD939X_ZDET_FLOATING_IMPEDANCE;
2080
2081 dev_dbg(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n",
2082 __func__, d1, c1, x1, *zdet);
2083 ramp_down:
2084 i = 0;
2085 while (x1) {
2086 val = snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_1,
2087 WCD939X_MBHC_RESULT_1_Z_RESULT_LSB) << 8;
2088 val |= snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_2,
2089 WCD939X_MBHC_RESULT_2_Z_RESULT_MSB);
2090 x1 = WCD939X_MBHC_GET_X1(val);
2091 i++;
2092 if (i == WCD939X_ZDET_NUM_MEASUREMENTS)
2093 break;
2094 }
2095 }
2096
wcd939x_mbhc_zdet_ramp(struct snd_soc_component * component,s32 * zl,int32_t * zr)2097 static void wcd939x_mbhc_zdet_ramp(struct snd_soc_component *component,
2098 s32 *zl, int32_t *zr)
2099 {
2100 const struct zdet_param *zdet_param = &wcd939x_mbhc_zdet_param;
2101 s32 zdet = 0;
2102
2103 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL,
2104 WCD939X_ZDET_ANA_CTL_MAXV_CTL, zdet_param->ldo_ctl);
2105 snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN5, WCD939X_MBHC_BTN5_VTH,
2106 zdet_param->btn5);
2107 snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN6, WCD939X_MBHC_BTN6_VTH,
2108 zdet_param->btn6);
2109 snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN7, WCD939X_MBHC_BTN7_VTH,
2110 zdet_param->btn7);
2111 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL,
2112 WCD939X_ZDET_ANA_CTL_RANGE_CTL, zdet_param->noff);
2113 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_RAMP_CTL,
2114 WCD939X_ZDET_RAMP_CTL_TIME_CTL, zdet_param->nshift);
2115 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_RAMP_CTL,
2116 WCD939X_ZDET_RAMP_CTL_ACC1_MIN_CTL, 6); /*acc1_min_63 */
2117
2118 if (!zl)
2119 goto z_right;
2120
2121 /* Start impedance measurement for HPH_L */
2122 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2123 WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN, true);
2124 dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n",
2125 __func__, zdet_param->noff);
2126 wcd939x_mbhc_get_result_params(component, &zdet);
2127 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2128 WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN, false);
2129
2130 *zl = zdet;
2131
2132 z_right:
2133 if (!zr)
2134 return;
2135
2136 /* Start impedance measurement for HPH_R */
2137 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2138 WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN, true);
2139 dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n",
2140 __func__, zdet_param->noff);
2141 wcd939x_mbhc_get_result_params(component, &zdet);
2142 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2143 WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN, false);
2144
2145 *zr = zdet;
2146 }
2147
wcd939x_wcd_mbhc_qfuse_cal(struct snd_soc_component * component,s32 * z_val,int flag_l_r)2148 static void wcd939x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
2149 s32 *z_val, int flag_l_r)
2150 {
2151 int q1_cal;
2152 s16 q1;
2153
2154 q1 = snd_soc_component_read(component, WCD939X_DIGITAL_EFUSE_REG_21 + flag_l_r);
2155 if (q1 & BIT(7))
2156 q1_cal = (10000 - ((q1 & GENMASK(6, 0)) * 10));
2157 else
2158 q1_cal = (10000 + (q1 * 10));
2159
2160 if (q1_cal > 0)
2161 *z_val = ((*z_val) * 10000) / q1_cal;
2162 }
2163
wcd939x_wcd_mbhc_calc_impedance(struct snd_soc_component * component,u32 * zl,uint32_t * zr)2164 static void wcd939x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
2165 u32 *zl, uint32_t *zr)
2166 {
2167 struct wcd939x_priv *wcd939x = dev_get_drvdata(component->dev);
2168 unsigned int reg0, reg1, reg2, reg3, reg4;
2169 int z_mono, z_diff1, z_diff2;
2170 bool is_fsm_disable = false;
2171 s32 z1l, z1r, z1ls;
2172
2173 reg0 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN5);
2174 reg1 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN6);
2175 reg2 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN7);
2176 reg3 = snd_soc_component_read(component, WCD939X_MBHC_CTL_CLK);
2177 reg4 = snd_soc_component_read(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL);
2178
2179 if (snd_soc_component_read_field(component, WCD939X_ANA_MBHC_ELECT,
2180 WCD939X_MBHC_ELECT_FSM_EN)) {
2181 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT,
2182 WCD939X_MBHC_ELECT_FSM_EN, false);
2183 is_fsm_disable = true;
2184 }
2185
2186 /* For NO-jack, disable L_DET_EN before Z-det measurements */
2187 if (wcd939x->mbhc_cfg.hphl_swh)
2188 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2189 WCD939X_MBHC_MECH_L_DET_EN, false);
2190
2191 /* Turn off 100k pull down on HPHL */
2192 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2193 WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND,
2194 false);
2195
2196 /*
2197 * Disable surge protection before impedance detection.
2198 * This is done to give correct value for high impedance.
2199 */
2200 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
2201 WCD939X_EN_EN_SURGE_PROTECTION_HPHR, false);
2202 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
2203 WCD939X_EN_EN_SURGE_PROTECTION_HPHL, false);
2204
2205 /* 1ms delay needed after disable surge protection */
2206 usleep_range(1000, 1010);
2207
2208 /* First get impedance on Left */
2209 wcd939x_mbhc_zdet_ramp(component, &z1l, NULL);
2210 if (z1l == WCD939X_ZDET_FLOATING_IMPEDANCE || z1l > WCD939X_ZDET_VAL_100K) {
2211 *zl = WCD939X_ZDET_FLOATING_IMPEDANCE;
2212 } else {
2213 *zl = z1l / 1000;
2214 wcd939x_wcd_mbhc_qfuse_cal(component, zl, 0);
2215 }
2216 dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
2217 __func__, *zl);
2218
2219 /* Start of right impedance ramp and calculation */
2220 wcd939x_mbhc_zdet_ramp(component, NULL, &z1r);
2221 if (z1r == WCD939X_ZDET_FLOATING_IMPEDANCE || z1r > WCD939X_ZDET_VAL_100K) {
2222 *zr = WCD939X_ZDET_FLOATING_IMPEDANCE;
2223 } else {
2224 *zr = z1r / 1000;
2225 wcd939x_wcd_mbhc_qfuse_cal(component, zr, 1);
2226 }
2227 dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
2228 __func__, *zr);
2229
2230 /* Mono/stereo detection */
2231 if (*zl == WCD939X_ZDET_FLOATING_IMPEDANCE &&
2232 *zr == WCD939X_ZDET_FLOATING_IMPEDANCE) {
2233 dev_dbg(component->dev,
2234 "%s: plug type is invalid or extension cable\n",
2235 __func__);
2236 goto zdet_complete;
2237 }
2238
2239 if (*zl == WCD939X_ZDET_FLOATING_IMPEDANCE ||
2240 *zr == WCD939X_ZDET_FLOATING_IMPEDANCE ||
2241 (*zl < WCD_MONO_HS_MIN_THR && *zr > WCD_MONO_HS_MIN_THR) ||
2242 (*zl > WCD_MONO_HS_MIN_THR && *zr < WCD_MONO_HS_MIN_THR)) {
2243 dev_dbg(component->dev,
2244 "%s: Mono plug type with one ch floating or shorted to GND\n",
2245 __func__);
2246 wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_MONO);
2247 goto zdet_complete;
2248 }
2249
2250 snd_soc_component_write_field(component, WCD939X_HPH_R_ATEST,
2251 WCD939X_R_ATEST_HPH_GND_OVR, true);
2252 snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2,
2253 WCD939X_PA_CTL2_HPHPA_GND_R, true);
2254 wcd939x_mbhc_zdet_ramp(component, &z1ls, NULL);
2255 snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2,
2256 WCD939X_PA_CTL2_HPHPA_GND_R, false);
2257 snd_soc_component_write_field(component, WCD939X_HPH_R_ATEST,
2258 WCD939X_R_ATEST_HPH_GND_OVR, false);
2259
2260 z1ls /= 1000;
2261 wcd939x_wcd_mbhc_qfuse_cal(component, &z1ls, 0);
2262
2263 /* Parallel of left Z and 9 ohm pull down resistor */
2264 z_mono = (*zl * 9) / (*zl + 9);
2265 z_diff1 = z1ls > z_mono ? z1ls - z_mono : z_mono - z1ls;
2266 z_diff2 = *zl > z1ls ? *zl - z1ls : z1ls - *zl;
2267 if ((z_diff1 * (*zl + z1ls)) > (z_diff2 * (z1ls + z_mono))) {
2268 dev_dbg(component->dev, "%s: stereo plug type detected\n",
2269 __func__);
2270 wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_STEREO);
2271 } else {
2272 dev_dbg(component->dev, "%s: MONO plug type detected\n",
2273 __func__);
2274 wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_MONO);
2275 }
2276
2277 /* Enable surge protection again after impedance detection */
2278 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
2279 WCD939X_EN_EN_SURGE_PROTECTION_HPHR, true);
2280 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
2281 WCD939X_EN_EN_SURGE_PROTECTION_HPHL, true);
2282
2283 zdet_complete:
2284 snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN5, reg0);
2285 snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN6, reg1);
2286 snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN7, reg2);
2287
2288 /* Turn on 100k pull down on HPHL */
2289 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2290 WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND, true);
2291
2292 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */
2293 if (wcd939x->mbhc_cfg.hphl_swh)
2294 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2295 WCD939X_MBHC_MECH_L_DET_EN, true);
2296
2297 snd_soc_component_write(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL, reg4);
2298 snd_soc_component_write(component, WCD939X_MBHC_CTL_CLK, reg3);
2299
2300 if (is_fsm_disable)
2301 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT,
2302 WCD939X_MBHC_ELECT_FSM_EN, true);
2303 }
2304
wcd939x_mbhc_gnd_det_ctrl(struct snd_soc_component * component,bool enable)2305 static void wcd939x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
2306 bool enable)
2307 {
2308 if (enable) {
2309 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2310 WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN,
2311 true);
2312 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2313 WCD939X_MBHC_MECH_GND_DET_EN, true);
2314 } else {
2315 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2316 WCD939X_MBHC_MECH_GND_DET_EN, false);
2317 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2318 WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN,
2319 false);
2320 }
2321 }
2322
wcd939x_mbhc_hph_pull_down_ctrl(struct snd_soc_component * component,bool enable)2323 static void wcd939x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
2324 bool enable)
2325 {
2326 snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2,
2327 WCD939X_PA_CTL2_HPHPA_GND_R, enable);
2328 snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2,
2329 WCD939X_PA_CTL2_HPHPA_GND_L, enable);
2330 }
2331
wcd939x_mbhc_moisture_config(struct snd_soc_component * component)2332 static void wcd939x_mbhc_moisture_config(struct snd_soc_component *component)
2333 {
2334 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2335
2336 if (wcd939x->mbhc_cfg.moist_rref == R_OFF || wcd939x->typec_analog_mux) {
2337 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2338 WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2339 return;
2340 }
2341
2342 /* Do not enable moisture detection if jack type is NC */
2343 if (!wcd939x->mbhc_cfg.hphl_swh) {
2344 dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
2345 __func__);
2346 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2347 WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2348 return;
2349 }
2350
2351 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2352 WCD939X_CTL_2_M_RTH_CTL, wcd939x->mbhc_cfg.moist_rref);
2353 }
2354
wcd939x_mbhc_moisture_detect_en(struct snd_soc_component * component,bool enable)2355 static void wcd939x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable)
2356 {
2357 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2358
2359 if (enable)
2360 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2361 WCD939X_CTL_2_M_RTH_CTL,
2362 wcd939x->mbhc_cfg.moist_rref);
2363 else
2364 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2365 WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2366 }
2367
wcd939x_mbhc_get_moisture_status(struct snd_soc_component * component)2368 static bool wcd939x_mbhc_get_moisture_status(struct snd_soc_component *component)
2369 {
2370 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2371 bool ret = false;
2372
2373 if (wcd939x->mbhc_cfg.moist_rref == R_OFF || wcd939x->typec_analog_mux) {
2374 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2375 WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2376 goto done;
2377 }
2378
2379 /* Do not enable moisture detection if jack type is NC */
2380 if (!wcd939x->mbhc_cfg.hphl_swh) {
2381 dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
2382 __func__);
2383 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2384 WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2385 goto done;
2386 }
2387
2388 /*
2389 * If moisture_en is already enabled, then skip to plug type
2390 * detection.
2391 */
2392 if (snd_soc_component_read_field(component, WCD939X_MBHC_NEW_CTL_2,
2393 WCD939X_CTL_2_M_RTH_CTL))
2394 goto done;
2395
2396 wcd939x_mbhc_moisture_detect_en(component, true);
2397
2398 /* Read moisture comparator status, invert of status bit */
2399 ret = !snd_soc_component_read_field(component, WCD939X_MBHC_NEW_FSM_STATUS,
2400 WCD939X_FSM_STATUS_HS_M_COMP_STATUS);
2401 done:
2402 return ret;
2403 }
2404
wcd939x_mbhc_moisture_polling_ctrl(struct snd_soc_component * component,bool enable)2405 static void wcd939x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component,
2406 bool enable)
2407 {
2408 snd_soc_component_write_field(component,
2409 WCD939X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,
2410 WCD939X_MOISTURE_DET_POLLING_CTRL_MOIST_EN_POLLING,
2411 enable);
2412 }
2413
2414 static const struct wcd_mbhc_cb mbhc_cb = {
2415 .clk_setup = wcd939x_mbhc_clk_setup,
2416 .mbhc_bias = wcd939x_mbhc_mbhc_bias_control,
2417 .set_btn_thr = wcd939x_mbhc_program_btn_thr,
2418 .micbias_enable_status = wcd939x_mbhc_micb_en_status,
2419 .hph_pull_up_control_v2 = wcd939x_mbhc_hph_l_pull_up_control,
2420 .mbhc_micbias_control = wcd939x_mbhc_request_micbias,
2421 .mbhc_micb_ramp_control = wcd939x_mbhc_micb_ramp_control,
2422 .mbhc_micb_ctrl_thr_mic = wcd939x_mbhc_micb_ctrl_threshold_mic,
2423 .compute_impedance = wcd939x_wcd_mbhc_calc_impedance,
2424 .mbhc_gnd_det_ctrl = wcd939x_mbhc_gnd_det_ctrl,
2425 .hph_pull_down_ctrl = wcd939x_mbhc_hph_pull_down_ctrl,
2426 .mbhc_moisture_config = wcd939x_mbhc_moisture_config,
2427 .mbhc_get_moisture_status = wcd939x_mbhc_get_moisture_status,
2428 .mbhc_moisture_polling_ctrl = wcd939x_mbhc_moisture_polling_ctrl,
2429 .mbhc_moisture_detect_en = wcd939x_mbhc_moisture_detect_en,
2430 };
2431
wcd939x_get_hph_type(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2432 static int wcd939x_get_hph_type(struct snd_kcontrol *kcontrol,
2433 struct snd_ctl_elem_value *ucontrol)
2434 {
2435 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2436 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2437
2438 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd939x->wcd_mbhc);
2439
2440 return 0;
2441 }
2442
wcd939x_hph_impedance_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2443 static int wcd939x_hph_impedance_get(struct snd_kcontrol *kcontrol,
2444 struct snd_ctl_elem_value *ucontrol)
2445 {
2446 struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value);
2447 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2448 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2449 bool hphr = mc->shift;
2450 u32 zl, zr;
2451
2452 wcd_mbhc_get_impedance(wcd939x->wcd_mbhc, &zl, &zr);
2453 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
2454 ucontrol->value.integer.value[0] = hphr ? zr : zl;
2455
2456 return 0;
2457 }
2458
2459 static const struct snd_kcontrol_new hph_type_detect_controls[] = {
2460 SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0,
2461 wcd939x_get_hph_type, NULL),
2462 };
2463
2464 static const struct snd_kcontrol_new impedance_detect_controls[] = {
2465 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0,
2466 wcd939x_hph_impedance_get, NULL),
2467 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0,
2468 wcd939x_hph_impedance_get, NULL),
2469 };
2470
wcd939x_mbhc_init(struct snd_soc_component * component)2471 static int wcd939x_mbhc_init(struct snd_soc_component *component)
2472 {
2473 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2474 struct wcd_mbhc_intr *intr_ids = &wcd939x->intr_ids;
2475
2476 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2477 WCD939X_IRQ_MBHC_SW_DET);
2478 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2479 WCD939X_IRQ_MBHC_BUTTON_PRESS_DET);
2480 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2481 WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET);
2482 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2483 WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
2484 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2485 WCD939X_IRQ_MBHC_ELECT_INS_REM_DET);
2486 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd939x->irq_chip,
2487 WCD939X_IRQ_HPHL_OCP_INT);
2488 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd939x->irq_chip,
2489 WCD939X_IRQ_HPHR_OCP_INT);
2490
2491 wcd939x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
2492 if (IS_ERR(wcd939x->wcd_mbhc))
2493 return PTR_ERR(wcd939x->wcd_mbhc);
2494
2495 snd_soc_add_component_controls(component, impedance_detect_controls,
2496 ARRAY_SIZE(impedance_detect_controls));
2497 snd_soc_add_component_controls(component, hph_type_detect_controls,
2498 ARRAY_SIZE(hph_type_detect_controls));
2499
2500 return 0;
2501 }
2502
wcd939x_mbhc_deinit(struct snd_soc_component * component)2503 static void wcd939x_mbhc_deinit(struct snd_soc_component *component)
2504 {
2505 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2506
2507 wcd_mbhc_deinit(wcd939x->wcd_mbhc);
2508 }
2509
2510 /* END MBHC */
2511
2512 static const struct snd_kcontrol_new wcd939x_snd_controls[] = {
2513 /* RX Path */
2514 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD939X_COMP_L, 0, 1, 0,
2515 wcd939x_get_compander, wcd939x_set_compander),
2516 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD939X_COMP_R, 1, 1, 0,
2517 wcd939x_get_compander, wcd939x_set_compander),
2518 SOC_SINGLE_EXT("HPHL Switch", WCD939X_HPH_L, 0, 1, 0,
2519 wcd939x_get_swr_port, wcd939x_set_swr_port),
2520 SOC_SINGLE_EXT("HPHR Switch", WCD939X_HPH_R, 0, 1, 0,
2521 wcd939x_get_swr_port, wcd939x_set_swr_port),
2522 SOC_SINGLE_EXT("CLSH Switch", WCD939X_CLSH, 0, 1, 0,
2523 wcd939x_get_swr_port, wcd939x_set_swr_port),
2524 SOC_SINGLE_EXT("LO Switch", WCD939X_LO, 0, 1, 0,
2525 wcd939x_get_swr_port, wcd939x_set_swr_port),
2526 SOC_SINGLE_EXT("DSD_L Switch", WCD939X_DSD_L, 0, 1, 0,
2527 wcd939x_get_swr_port, wcd939x_set_swr_port),
2528 SOC_SINGLE_EXT("DSD_R Switch", WCD939X_DSD_R, 0, 1, 0,
2529 wcd939x_get_swr_port, wcd939x_set_swr_port),
2530 SOC_SINGLE_TLV("HPHL Volume", WCD939X_HPH_L_EN, 0, 20, 1, line_gain),
2531 SOC_SINGLE_TLV("HPHR Volume", WCD939X_HPH_R_EN, 0, 20, 1, line_gain),
2532 SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0,
2533 wcd939x_ldoh_get, wcd939x_ldoh_put),
2534
2535 /* TX Path */
2536 SOC_SINGLE_EXT("ADC1 Switch", WCD939X_ADC1, 1, 1, 0,
2537 wcd939x_get_swr_port, wcd939x_set_swr_port),
2538 SOC_SINGLE_EXT("ADC2 Switch", WCD939X_ADC2, 1, 1, 0,
2539 wcd939x_get_swr_port, wcd939x_set_swr_port),
2540 SOC_SINGLE_EXT("ADC3 Switch", WCD939X_ADC3, 1, 1, 0,
2541 wcd939x_get_swr_port, wcd939x_set_swr_port),
2542 SOC_SINGLE_EXT("ADC4 Switch", WCD939X_ADC4, 1, 1, 0,
2543 wcd939x_get_swr_port, wcd939x_set_swr_port),
2544 SOC_SINGLE_EXT("DMIC0 Switch", WCD939X_DMIC0, 1, 1, 0,
2545 wcd939x_get_swr_port, wcd939x_set_swr_port),
2546 SOC_SINGLE_EXT("DMIC1 Switch", WCD939X_DMIC1, 1, 1, 0,
2547 wcd939x_get_swr_port, wcd939x_set_swr_port),
2548 SOC_SINGLE_EXT("MBHC Switch", WCD939X_MBHC, 1, 1, 0,
2549 wcd939x_get_swr_port, wcd939x_set_swr_port),
2550 SOC_SINGLE_EXT("DMIC2 Switch", WCD939X_DMIC2, 1, 1, 0,
2551 wcd939x_get_swr_port, wcd939x_set_swr_port),
2552 SOC_SINGLE_EXT("DMIC3 Switch", WCD939X_DMIC3, 1, 1, 0,
2553 wcd939x_get_swr_port, wcd939x_set_swr_port),
2554 SOC_SINGLE_EXT("DMIC4 Switch", WCD939X_DMIC4, 1, 1, 0,
2555 wcd939x_get_swr_port, wcd939x_set_swr_port),
2556 SOC_SINGLE_EXT("DMIC5 Switch", WCD939X_DMIC5, 1, 1, 0,
2557 wcd939x_get_swr_port, wcd939x_set_swr_port),
2558 SOC_SINGLE_EXT("DMIC6 Switch", WCD939X_DMIC6, 1, 1, 0,
2559 wcd939x_get_swr_port, wcd939x_set_swr_port),
2560 SOC_SINGLE_EXT("DMIC7 Switch", WCD939X_DMIC7, 1, 1, 0,
2561 wcd939x_get_swr_port, wcd939x_set_swr_port),
2562 SOC_SINGLE_TLV("ADC1 Volume", WCD939X_ANA_TX_CH1, 0, 20, 0,
2563 analog_gain),
2564 SOC_SINGLE_TLV("ADC2 Volume", WCD939X_ANA_TX_CH2, 0, 20, 0,
2565 analog_gain),
2566 SOC_SINGLE_TLV("ADC3 Volume", WCD939X_ANA_TX_CH3, 0, 20, 0,
2567 analog_gain),
2568 SOC_SINGLE_TLV("ADC4 Volume", WCD939X_ANA_TX_CH4, 0, 20, 0,
2569 analog_gain),
2570 };
2571
2572 static const struct snd_soc_dapm_widget wcd939x_dapm_widgets[] = {
2573 /*input widgets*/
2574 SND_SOC_DAPM_INPUT("AMIC1"),
2575 SND_SOC_DAPM_INPUT("AMIC2"),
2576 SND_SOC_DAPM_INPUT("AMIC3"),
2577 SND_SOC_DAPM_INPUT("AMIC4"),
2578 SND_SOC_DAPM_INPUT("AMIC5"),
2579
2580 SND_SOC_DAPM_MIC("Analog Mic1", NULL),
2581 SND_SOC_DAPM_MIC("Analog Mic2", NULL),
2582 SND_SOC_DAPM_MIC("Analog Mic3", NULL),
2583 SND_SOC_DAPM_MIC("Analog Mic4", NULL),
2584 SND_SOC_DAPM_MIC("Analog Mic5", NULL),
2585
2586 /* TX widgets */
2587 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
2588 wcd939x_codec_enable_adc,
2589 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2590 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
2591 wcd939x_codec_enable_adc,
2592 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2593 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
2594 wcd939x_codec_enable_adc,
2595 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2596 SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
2597 wcd939x_codec_enable_adc,
2598 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2599 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
2600 wcd939x_codec_enable_dmic,
2601 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2602 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
2603 wcd939x_codec_enable_dmic,
2604 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2605 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
2606 wcd939x_codec_enable_dmic,
2607 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2608 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
2609 wcd939x_codec_enable_dmic,
2610 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2611 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
2612 wcd939x_codec_enable_dmic,
2613 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2614 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
2615 wcd939x_codec_enable_dmic,
2616 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2617 SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
2618 wcd939x_codec_enable_dmic,
2619 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2620 SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
2621 wcd939x_codec_enable_dmic,
2622 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2623
2624 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, NULL, 0,
2625 wcd939x_adc_enable_req,
2626 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2627 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0, NULL, 0,
2628 wcd939x_adc_enable_req,
2629 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2630 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0, NULL, 0,
2631 wcd939x_adc_enable_req,
2632 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2633 SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0,
2634 wcd939x_adc_enable_req,
2635 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2636
2637 SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0, &tx_adc1_mux),
2638 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
2639 SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux),
2640 SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux),
2641
2642 /* tx mixers */
2643 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
2644 adc1_switch, ARRAY_SIZE(adc1_switch), wcd939x_tx_swr_ctrl,
2645 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2646 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
2647 adc2_switch, ARRAY_SIZE(adc2_switch), wcd939x_tx_swr_ctrl,
2648 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2649 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0,
2650 adc3_switch, ARRAY_SIZE(adc3_switch), wcd939x_tx_swr_ctrl,
2651 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2652 SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0,
2653 adc4_switch, ARRAY_SIZE(adc4_switch), wcd939x_tx_swr_ctrl,
2654 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2655 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0,
2656 dmic1_switch, ARRAY_SIZE(dmic1_switch), wcd939x_tx_swr_ctrl,
2657 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2658 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0,
2659 dmic2_switch, ARRAY_SIZE(dmic2_switch), wcd939x_tx_swr_ctrl,
2660 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2661 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0,
2662 dmic3_switch, ARRAY_SIZE(dmic3_switch), wcd939x_tx_swr_ctrl,
2663 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2664 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0,
2665 dmic4_switch, ARRAY_SIZE(dmic4_switch), wcd939x_tx_swr_ctrl,
2666 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2667 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0,
2668 dmic5_switch, ARRAY_SIZE(dmic5_switch), wcd939x_tx_swr_ctrl,
2669 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2670 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0,
2671 dmic6_switch, ARRAY_SIZE(dmic6_switch), wcd939x_tx_swr_ctrl,
2672 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2673 SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0,
2674 dmic7_switch, ARRAY_SIZE(dmic7_switch), wcd939x_tx_swr_ctrl,
2675 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2676 SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0,
2677 dmic8_switch, ARRAY_SIZE(dmic8_switch), wcd939x_tx_swr_ctrl,
2678 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2679
2680 /* micbias widgets */
2681 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
2682 wcd939x_codec_enable_micbias,
2683 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2684 SND_SOC_DAPM_POST_PMD),
2685 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
2686 wcd939x_codec_enable_micbias,
2687 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2688 SND_SOC_DAPM_POST_PMD),
2689 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
2690 wcd939x_codec_enable_micbias,
2691 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2692 SND_SOC_DAPM_POST_PMD),
2693 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
2694 wcd939x_codec_enable_micbias,
2695 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2696 SND_SOC_DAPM_POST_PMD),
2697
2698 /* micbias pull up widgets */
2699 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
2700 wcd939x_codec_enable_micbias_pullup,
2701 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2702 SND_SOC_DAPM_POST_PMD),
2703 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
2704 wcd939x_codec_enable_micbias_pullup,
2705 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2706 SND_SOC_DAPM_POST_PMD),
2707 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
2708 wcd939x_codec_enable_micbias_pullup,
2709 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2710 SND_SOC_DAPM_POST_PMD),
2711 SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
2712 wcd939x_codec_enable_micbias_pullup,
2713 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2714 SND_SOC_DAPM_POST_PMD),
2715
2716 /* output widgets tx */
2717 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
2718 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
2719 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
2720 SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
2721 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
2722 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
2723 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
2724 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
2725 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
2726 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
2727 SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
2728 SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
2729
2730 SND_SOC_DAPM_INPUT("IN1_HPHL"),
2731 SND_SOC_DAPM_INPUT("IN2_HPHR"),
2732 SND_SOC_DAPM_INPUT("IN3_EAR"),
2733
2734 /* rx widgets */
2735 SND_SOC_DAPM_PGA_E("EAR PGA", WCD939X_ANA_EAR, 7, 0, NULL, 0,
2736 wcd939x_codec_enable_ear_pa,
2737 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2738 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2739 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD939X_ANA_HPH, 7, 0, NULL, 0,
2740 wcd939x_codec_enable_hphl_pa,
2741 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2742 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2743 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD939X_ANA_HPH, 6, 0, NULL, 0,
2744 wcd939x_codec_enable_hphr_pa,
2745 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2746 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2747
2748 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
2749 wcd939x_codec_hphl_dac_event,
2750 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2751 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2752 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
2753 wcd939x_codec_hphr_dac_event,
2754 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2755 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2756 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
2757 wcd939x_codec_ear_dac_event,
2758 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2759 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2760
2761 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
2762
2763 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0),
2764 SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0,
2765 wcd939x_codec_enable_rxclk,
2766 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2767 SND_SOC_DAPM_POST_PMD),
2768
2769 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0),
2770
2771 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2772 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2773 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2774
2775 /* rx mixer widgets */
2776 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
2777 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
2778 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
2779 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
2780 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
2781 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
2782
2783 /* output widgets rx */
2784 SND_SOC_DAPM_OUTPUT("EAR"),
2785 SND_SOC_DAPM_OUTPUT("HPHL"),
2786 SND_SOC_DAPM_OUTPUT("HPHR"),
2787 };
2788
2789 static const struct snd_soc_dapm_route wcd939x_audio_map[] = {
2790 /* TX Path */
2791 {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
2792 {"ADC1_MIXER", "Switch", "ADC1 REQ"},
2793 {"ADC1 REQ", NULL, "ADC1"},
2794 {"ADC1", NULL, "ADC1 MUX"},
2795 {"ADC1 MUX", "CH1_AMIC1", "AMIC1"},
2796 {"ADC1 MUX", "CH1_AMIC2", "AMIC2"},
2797 {"ADC1 MUX", "CH1_AMIC3", "AMIC3"},
2798 {"ADC1 MUX", "CH1_AMIC4", "AMIC4"},
2799 {"ADC1 MUX", "CH1_AMIC5", "AMIC5"},
2800
2801 {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
2802 {"ADC2_MIXER", "Switch", "ADC2 REQ"},
2803 {"ADC2 REQ", NULL, "ADC2"},
2804 {"ADC2", NULL, "ADC2 MUX"},
2805 {"ADC2 MUX", "CH2_AMIC1", "AMIC1"},
2806 {"ADC2 MUX", "CH2_AMIC2", "AMIC2"},
2807 {"ADC2 MUX", "CH2_AMIC3", "AMIC3"},
2808 {"ADC2 MUX", "CH2_AMIC4", "AMIC4"},
2809 {"ADC2 MUX", "CH2_AMIC5", "AMIC5"},
2810
2811 {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
2812 {"ADC3_MIXER", "Switch", "ADC3 REQ"},
2813 {"ADC3 REQ", NULL, "ADC3"},
2814 {"ADC3", NULL, "ADC3 MUX"},
2815 {"ADC3 MUX", "CH3_AMIC1", "AMIC1"},
2816 {"ADC3 MUX", "CH3_AMIC3", "AMIC3"},
2817 {"ADC3 MUX", "CH3_AMIC4", "AMIC4"},
2818 {"ADC3 MUX", "CH3_AMIC5", "AMIC5"},
2819
2820 {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
2821 {"ADC4_MIXER", "Switch", "ADC4 REQ"},
2822 {"ADC4 REQ", NULL, "ADC4"},
2823 {"ADC4", NULL, "ADC4 MUX"},
2824 {"ADC4 MUX", "CH4_AMIC1", "AMIC1"},
2825 {"ADC4 MUX", "CH4_AMIC3", "AMIC3"},
2826 {"ADC4 MUX", "CH4_AMIC4", "AMIC4"},
2827 {"ADC4 MUX", "CH4_AMIC5", "AMIC5"},
2828
2829 {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
2830 {"DMIC1_MIXER", "Switch", "DMIC1"},
2831
2832 {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
2833 {"DMIC2_MIXER", "Switch", "DMIC2"},
2834
2835 {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
2836 {"DMIC3_MIXER", "Switch", "DMIC3"},
2837
2838 {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
2839 {"DMIC4_MIXER", "Switch", "DMIC4"},
2840
2841 {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
2842 {"DMIC5_MIXER", "Switch", "DMIC5"},
2843
2844 {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
2845 {"DMIC6_MIXER", "Switch", "DMIC6"},
2846
2847 {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
2848 {"DMIC7_MIXER", "Switch", "DMIC7"},
2849
2850 {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
2851 {"DMIC8_MIXER", "Switch", "DMIC8"},
2852
2853 /* RX Path */
2854 {"IN1_HPHL", NULL, "VDD_BUCK"},
2855 {"IN1_HPHL", NULL, "CLS_H_PORT"},
2856
2857 {"RX1", NULL, "IN1_HPHL"},
2858 {"RX1", NULL, "RXCLK"},
2859 {"RDAC1", NULL, "RX1"},
2860 {"HPHL_RDAC", "Switch", "RDAC1"},
2861 {"HPHL PGA", NULL, "HPHL_RDAC"},
2862 {"HPHL", NULL, "HPHL PGA"},
2863
2864 {"IN2_HPHR", NULL, "VDD_BUCK"},
2865 {"IN2_HPHR", NULL, "CLS_H_PORT"},
2866 {"RX2", NULL, "IN2_HPHR"},
2867 {"RDAC2", NULL, "RX2"},
2868 {"RX2", NULL, "RXCLK"},
2869 {"HPHR_RDAC", "Switch", "RDAC2"},
2870 {"HPHR PGA", NULL, "HPHR_RDAC"},
2871 {"HPHR", NULL, "HPHR PGA"},
2872
2873 {"IN3_EAR", NULL, "VDD_BUCK"},
2874 {"RX3", NULL, "IN3_EAR"},
2875 {"RX3", NULL, "RXCLK"},
2876
2877 {"RDAC3_MUX", "RX3", "RX3"},
2878 {"RDAC3_MUX", "RX1", "RX1"},
2879 {"RDAC3", NULL, "RDAC3_MUX"},
2880 {"EAR_RDAC", "Switch", "RDAC3"},
2881 {"EAR PGA", NULL, "EAR_RDAC"},
2882 {"EAR", NULL, "EAR PGA"},
2883 };
2884
wcd939x_set_micbias_data(struct device * dev,struct wcd939x_priv * wcd939x)2885 static void wcd939x_set_micbias_data(struct device *dev, struct wcd939x_priv *wcd939x)
2886 {
2887 regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB1,
2888 WCD939X_MICB_VOUT_CTL, wcd939x->common.micb_vout[0]);
2889 regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB2,
2890 WCD939X_MICB_VOUT_CTL, wcd939x->common.micb_vout[1]);
2891 regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB3,
2892 WCD939X_MICB_VOUT_CTL, wcd939x->common.micb_vout[2]);
2893 regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB4,
2894 WCD939X_MICB_VOUT_CTL, wcd939x->common.micb_vout[3]);
2895 }
2896
wcd939x_wd_handle_irq(int irq,void * data)2897 static irqreturn_t wcd939x_wd_handle_irq(int irq, void *data)
2898 {
2899 /*
2900 * HPHR/HPHL/EAR Watchdog interrupt threaded handler
2901 *
2902 * Watchdog interrupts are expected to be enabled when switching
2903 * on the HPHL/R and EAR RX PGA in order to make sure the interrupts
2904 * are acked by the regmap_irq handler to allow PDM sync.
2905 * We could leave those interrupts masked but we would not have
2906 * any valid way to enable/disable them without violating irq layers.
2907 *
2908 * The HPHR/HPHL/EAR Watchdog interrupts are handled
2909 * by regmap_irq, so requesting a threaded handler is the
2910 * safest way to be able to ack those interrupts without
2911 * colliding with the regmap_irq setup.
2912 */
2913
2914 return IRQ_HANDLED;
2915 }
2916
2917 /*
2918 * Setup a virtual interrupt domain to hook regmap_irq
2919 * The root domain will have a single interrupt which mapping
2920 * will trigger the regmap_irq handler.
2921 *
2922 * root:
2923 * wcd_irq_chip
2924 * [0] wcd939x_regmap_irq_chip
2925 * [0] MBHC_BUTTON_PRESS_DET
2926 * [1] MBHC_BUTTON_RELEASE_DET
2927 * ...
2928 * [16] HPHR_SURGE_DET_INT
2929 *
2930 * Interrupt trigger:
2931 * soundwire_interrupt_callback()
2932 * \-handle_nested_irq(0)
2933 * \- regmap_irq_thread()
2934 * \- handle_nested_irq(i)
2935 */
2936 static const struct irq_chip wcd_irq_chip = {
2937 .name = "WCD939x",
2938 };
2939
wcd_irq_chip_map(struct irq_domain * irqd,unsigned int virq,irq_hw_number_t hw)2940 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq,
2941 irq_hw_number_t hw)
2942 {
2943 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq);
2944 irq_set_nested_thread(virq, 1);
2945 irq_set_noprobe(virq);
2946
2947 return 0;
2948 }
2949
2950 static const struct irq_domain_ops wcd_domain_ops = {
2951 .map = wcd_irq_chip_map,
2952 };
2953
wcd939x_irq_init(struct wcd939x_priv * wcd,struct device * dev)2954 static int wcd939x_irq_init(struct wcd939x_priv *wcd, struct device *dev)
2955 {
2956 wcd->virq = irq_domain_create_linear(NULL, 1, &wcd_domain_ops, NULL);
2957 if (!(wcd->virq)) {
2958 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__);
2959 return -EINVAL;
2960 }
2961
2962 return devm_regmap_add_irq_chip(dev, wcd->regmap,
2963 irq_create_mapping(wcd->virq, 0),
2964 IRQF_ONESHOT, 0, &wcd939x_regmap_irq_chip,
2965 &wcd->irq_chip);
2966 }
2967
wcd939x_soc_codec_probe(struct snd_soc_component * component)2968 static int wcd939x_soc_codec_probe(struct snd_soc_component *component)
2969 {
2970 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2971 struct sdw_slave *tx_sdw_dev = wcd939x->tx_sdw_dev;
2972 struct device *dev = component->dev;
2973 unsigned long time_left;
2974 int ret, i;
2975
2976 time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete,
2977 msecs_to_jiffies(2000));
2978 if (!time_left) {
2979 dev_err(dev, "soundwire device init timeout\n");
2980 return -ETIMEDOUT;
2981 }
2982
2983 snd_soc_component_init_regmap(component, wcd939x->regmap);
2984
2985 ret = pm_runtime_resume_and_get(dev);
2986 if (ret < 0)
2987 return ret;
2988
2989 wcd939x->variant = snd_soc_component_read_field(component,
2990 WCD939X_DIGITAL_EFUSE_REG_0,
2991 WCD939X_EFUSE_REG_0_WCD939X_ID);
2992
2993 wcd939x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD939X);
2994 if (IS_ERR(wcd939x->clsh_info)) {
2995 pm_runtime_put(dev);
2996 return PTR_ERR(wcd939x->clsh_info);
2997 }
2998
2999 wcd939x_io_init(component);
3000
3001 /* Set all interrupts as edge triggered */
3002 for (i = 0; i < wcd939x_regmap_irq_chip.num_regs; i++)
3003 regmap_write(wcd939x->regmap,
3004 (WCD939X_DIGITAL_INTR_LEVEL_0 + i), 0);
3005
3006 pm_runtime_put(dev);
3007
3008 /* Request for watchdog interrupt */
3009 wcd939x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip,
3010 WCD939X_IRQ_HPHR_PDM_WD_INT);
3011 wcd939x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip,
3012 WCD939X_IRQ_HPHL_PDM_WD_INT);
3013 wcd939x->ear_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip,
3014 WCD939X_IRQ_EAR_PDM_WD_INT);
3015
3016 ret = request_threaded_irq(wcd939x->hphr_pdm_wd_int, NULL, wcd939x_wd_handle_irq,
3017 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3018 "HPHR PDM WD INT", wcd939x);
3019 if (ret) {
3020 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret);
3021 goto err_free_clsh_ctrl;
3022 }
3023
3024 ret = request_threaded_irq(wcd939x->hphl_pdm_wd_int, NULL, wcd939x_wd_handle_irq,
3025 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3026 "HPHL PDM WD INT", wcd939x);
3027 if (ret) {
3028 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret);
3029 goto err_free_hphr_pdm_wd_int;
3030 }
3031
3032 ret = request_threaded_irq(wcd939x->ear_pdm_wd_int, NULL, wcd939x_wd_handle_irq,
3033 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3034 "AUX PDM WD INT", wcd939x);
3035 if (ret) {
3036 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret);
3037 goto err_free_hphl_pdm_wd_int;
3038 }
3039
3040 /* Disable watchdog interrupt for HPH and AUX */
3041 disable_irq_nosync(wcd939x->hphr_pdm_wd_int);
3042 disable_irq_nosync(wcd939x->hphl_pdm_wd_int);
3043 disable_irq_nosync(wcd939x->ear_pdm_wd_int);
3044
3045 switch (wcd939x->variant) {
3046 case CHIPID_WCD9390:
3047 ret = snd_soc_add_component_controls(component, wcd9390_snd_controls,
3048 ARRAY_SIZE(wcd9390_snd_controls));
3049 if (ret < 0) {
3050 dev_err(component->dev,
3051 "%s: Failed to add snd ctrls for variant: %d\n",
3052 __func__, wcd939x->variant);
3053 goto err_free_ear_pdm_wd_int;
3054 }
3055 break;
3056 case CHIPID_WCD9395:
3057 ret = snd_soc_add_component_controls(component, wcd9395_snd_controls,
3058 ARRAY_SIZE(wcd9395_snd_controls));
3059 if (ret < 0) {
3060 dev_err(component->dev,
3061 "%s: Failed to add snd ctrls for variant: %d\n",
3062 __func__, wcd939x->variant);
3063 goto err_free_ear_pdm_wd_int;
3064 }
3065 break;
3066 default:
3067 break;
3068 }
3069
3070 ret = wcd939x_mbhc_init(component);
3071 if (ret) {
3072 dev_err(component->dev, "mbhc initialization failed\n");
3073 goto err_free_ear_pdm_wd_int;
3074 }
3075
3076 return 0;
3077
3078 err_free_ear_pdm_wd_int:
3079 free_irq(wcd939x->ear_pdm_wd_int, wcd939x);
3080 err_free_hphl_pdm_wd_int:
3081 free_irq(wcd939x->hphl_pdm_wd_int, wcd939x);
3082 err_free_hphr_pdm_wd_int:
3083 free_irq(wcd939x->hphr_pdm_wd_int, wcd939x);
3084 err_free_clsh_ctrl:
3085 wcd_clsh_ctrl_free(wcd939x->clsh_info);
3086
3087 return ret;
3088 }
3089
wcd939x_soc_codec_remove(struct snd_soc_component * component)3090 static void wcd939x_soc_codec_remove(struct snd_soc_component *component)
3091 {
3092 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
3093
3094 wcd939x_mbhc_deinit(component);
3095
3096 free_irq(wcd939x->ear_pdm_wd_int, wcd939x);
3097 free_irq(wcd939x->hphl_pdm_wd_int, wcd939x);
3098 free_irq(wcd939x->hphr_pdm_wd_int, wcd939x);
3099
3100 wcd_clsh_ctrl_free(wcd939x->clsh_info);
3101 }
3102
wcd939x_codec_set_jack(struct snd_soc_component * comp,struct snd_soc_jack * jack,void * data)3103 static int wcd939x_codec_set_jack(struct snd_soc_component *comp,
3104 struct snd_soc_jack *jack, void *data)
3105 {
3106 struct wcd939x_priv *wcd = dev_get_drvdata(comp->dev);
3107
3108 if (jack)
3109 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack);
3110
3111 wcd_mbhc_stop(wcd->wcd_mbhc);
3112
3113 return 0;
3114 }
3115
3116 static const struct snd_soc_component_driver soc_codec_dev_wcd939x = {
3117 .name = "wcd939x_codec",
3118 .probe = wcd939x_soc_codec_probe,
3119 .remove = wcd939x_soc_codec_remove,
3120 .controls = wcd939x_snd_controls,
3121 .num_controls = ARRAY_SIZE(wcd939x_snd_controls),
3122 .dapm_widgets = wcd939x_dapm_widgets,
3123 .num_dapm_widgets = ARRAY_SIZE(wcd939x_dapm_widgets),
3124 .dapm_routes = wcd939x_audio_map,
3125 .num_dapm_routes = ARRAY_SIZE(wcd939x_audio_map),
3126 .set_jack = wcd939x_codec_set_jack,
3127 .endianness = 1,
3128 };
3129
3130 #if IS_ENABLED(CONFIG_TYPEC)
3131 /* Get USB-C plug orientation to provide swap event for MBHC */
wcd939x_typec_switch_set(struct typec_switch_dev * sw,enum typec_orientation orientation)3132 static int wcd939x_typec_switch_set(struct typec_switch_dev *sw,
3133 enum typec_orientation orientation)
3134 {
3135 struct wcd939x_priv *wcd939x = typec_switch_get_drvdata(sw);
3136
3137 wcd939x->typec_orientation = orientation;
3138
3139 return 0;
3140 }
3141
wcd939x_typec_mux_set(struct typec_mux_dev * mux,struct typec_mux_state * state)3142 static int wcd939x_typec_mux_set(struct typec_mux_dev *mux,
3143 struct typec_mux_state *state)
3144 {
3145 struct wcd939x_priv *wcd939x = typec_mux_get_drvdata(mux);
3146 unsigned int previous_mode = wcd939x->typec_mode;
3147
3148 if (!wcd939x->wcd_mbhc)
3149 return -EINVAL;
3150
3151 if (wcd939x->typec_mode != state->mode) {
3152 wcd939x->typec_mode = state->mode;
3153
3154 if (wcd939x->typec_mode == TYPEC_MODE_AUDIO)
3155 return wcd_mbhc_typec_report_plug(wcd939x->wcd_mbhc);
3156 else if (previous_mode == TYPEC_MODE_AUDIO)
3157 return wcd_mbhc_typec_report_unplug(wcd939x->wcd_mbhc);
3158 }
3159
3160 return 0;
3161 }
3162 #endif /* CONFIG_TYPEC */
3163
3164 #if IS_ENABLED(CONFIG_TYPEC)
wcd939x_swap_gnd_mic(struct snd_soc_component * component)3165 static bool wcd939x_swap_gnd_mic(struct snd_soc_component *component)
3166 {
3167 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
3168
3169 if (!wcd939x->typec_analog_mux || !wcd939x->typec_switch)
3170 return false;
3171
3172 /* Report inversion via Type Switch of USBSS */
3173 typec_switch_set(wcd939x->typec_switch,
3174 wcd939x->typec_orientation == TYPEC_ORIENTATION_REVERSE ?
3175 TYPEC_ORIENTATION_NORMAL : TYPEC_ORIENTATION_REVERSE);
3176
3177 return true;
3178 }
3179 #endif /* CONFIG_TYPEC */
3180
wcd939x_populate_dt_data(struct wcd939x_priv * wcd939x,struct device * dev)3181 static int wcd939x_populate_dt_data(struct wcd939x_priv *wcd939x, struct device *dev)
3182 {
3183 struct wcd_mbhc_config *cfg = &wcd939x->mbhc_cfg;
3184 #if IS_ENABLED(CONFIG_TYPEC)
3185 struct device_node *np;
3186 #endif /* CONFIG_TYPEC */
3187 int ret;
3188
3189 wcd939x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
3190 if (IS_ERR(wcd939x->reset_gpio))
3191 return dev_err_probe(dev, PTR_ERR(wcd939x->reset_gpio),
3192 "Failed to get reset gpio\n");
3193
3194 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(wcd939x_supplies),
3195 wcd939x_supplies);
3196 if (ret)
3197 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n");
3198
3199 ret = wcd_dt_parse_micbias_info(&wcd939x->common);
3200 if (ret)
3201 return dev_err_probe(dev, ret, "Failed to get micbias\n");
3202
3203 cfg->mbhc_micbias = MIC_BIAS_2;
3204 cfg->anc_micbias = MIC_BIAS_2;
3205 cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
3206 cfg->num_btn = WCD939X_MBHC_MAX_BUTTONS;
3207 cfg->micb_mv = wcd939x->common.micb_mv[1];
3208 cfg->linein_th = 5000;
3209 cfg->hs_thr = 1700;
3210 cfg->hph_thr = 50;
3211
3212 wcd_dt_parse_mbhc_data(dev, cfg);
3213
3214 #if IS_ENABLED(CONFIG_TYPEC)
3215 /*
3216 * Is node has a port and a valid remote endpoint
3217 * consider HP lines are connected to the USBSS part
3218 */
3219 np = of_graph_get_remote_node(dev->of_node, 0, 0);
3220 if (np) {
3221 wcd939x->typec_analog_mux = true;
3222 cfg->typec_analog_mux = true;
3223 cfg->swap_gnd_mic = wcd939x_swap_gnd_mic;
3224 }
3225 #endif /* CONFIG_TYPEC */
3226
3227 return 0;
3228 }
3229
wcd939x_reset(struct wcd939x_priv * wcd939x)3230 static int wcd939x_reset(struct wcd939x_priv *wcd939x)
3231 {
3232 gpiod_set_value(wcd939x->reset_gpio, 1);
3233 /* 20us sleep required after pulling the reset gpio to LOW */
3234 usleep_range(20, 30);
3235 gpiod_set_value(wcd939x->reset_gpio, 0);
3236 /* 20us sleep required after pulling the reset gpio to HIGH */
3237 usleep_range(20, 30);
3238
3239 return 0;
3240 }
3241
wcd939x_codec_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)3242 static int wcd939x_codec_hw_params(struct snd_pcm_substream *substream,
3243 struct snd_pcm_hw_params *params,
3244 struct snd_soc_dai *dai)
3245 {
3246 struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev);
3247 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id];
3248
3249 return wcd939x_sdw_hw_params(wcd, substream, params, dai);
3250 }
3251
wcd939x_codec_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)3252 static int wcd939x_codec_free(struct snd_pcm_substream *substream,
3253 struct snd_soc_dai *dai)
3254 {
3255 struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev);
3256 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id];
3257
3258 return wcd939x_sdw_free(wcd, substream, dai);
3259 }
3260
wcd939x_codec_set_sdw_stream(struct snd_soc_dai * dai,void * stream,int direction)3261 static int wcd939x_codec_set_sdw_stream(struct snd_soc_dai *dai,
3262 void *stream, int direction)
3263 {
3264 struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev);
3265 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id];
3266
3267 return wcd939x_sdw_set_sdw_stream(wcd, dai, stream, direction);
3268 }
3269
3270 static const struct snd_soc_dai_ops wcd939x_sdw_dai_ops = {
3271 .hw_params = wcd939x_codec_hw_params,
3272 .hw_free = wcd939x_codec_free,
3273 .set_stream = wcd939x_codec_set_sdw_stream,
3274 };
3275
3276 static struct snd_soc_dai_driver wcd939x_dais[] = {
3277 [0] = {
3278 .name = "wcd939x-sdw-rx",
3279 .playback = {
3280 .stream_name = "WCD AIF1 Playback",
3281 .rates = WCD939X_RATES_MASK | WCD939X_FRAC_RATES_MASK,
3282 .formats = WCD939X_FORMATS,
3283 .rate_max = 384000,
3284 .rate_min = 8000,
3285 .channels_min = 1,
3286 .channels_max = 2,
3287 },
3288 .ops = &wcd939x_sdw_dai_ops,
3289 },
3290 [1] = {
3291 .name = "wcd939x-sdw-tx",
3292 .capture = {
3293 .stream_name = "WCD AIF1 Capture",
3294 .rates = WCD939X_RATES_MASK | WCD939X_FRAC_RATES_MASK,
3295 .formats = WCD939X_FORMATS,
3296 .rate_min = 8000,
3297 .rate_max = 384000,
3298 .channels_min = 1,
3299 .channels_max = 4,
3300 },
3301 .ops = &wcd939x_sdw_dai_ops,
3302 },
3303 };
3304
wcd939x_bind(struct device * dev)3305 static int wcd939x_bind(struct device *dev)
3306 {
3307 struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
3308 unsigned int version, id1, status1;
3309 int ret;
3310
3311 #if IS_ENABLED(CONFIG_TYPEC)
3312 /*
3313 * Get USBSS type-c switch to send gnd/mic swap events
3314 * typec_switch is fetched now to avoid a probe deadlock since
3315 * the USBSS depends on the typec_mux register in wcd939x_probe()
3316 */
3317 if (wcd939x->typec_analog_mux) {
3318 wcd939x->typec_switch = fwnode_typec_switch_get(dev->fwnode);
3319 if (IS_ERR(wcd939x->typec_switch))
3320 return dev_err_probe(dev, PTR_ERR(wcd939x->typec_switch),
3321 "failed to acquire orientation-switch\n");
3322 }
3323 #endif /* CONFIG_TYPEC */
3324
3325 ret = component_bind_all(dev, wcd939x);
3326 if (ret) {
3327 dev_err(dev, "%s: Slave bind failed, ret = %d\n",
3328 __func__, ret);
3329 goto err_put_typec_switch;
3330 }
3331
3332 wcd939x->rxdev = of_sdw_find_device_by_node(wcd939x->rxnode);
3333 if (!wcd939x->rxdev) {
3334 dev_err(dev, "could not find slave with matching of node\n");
3335 ret = -EINVAL;
3336 goto err_unbind;
3337 }
3338 wcd939x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd939x->rxdev);
3339 wcd939x->sdw_priv[AIF1_PB]->wcd939x = wcd939x;
3340
3341 wcd939x->txdev = of_sdw_find_device_by_node(wcd939x->txnode);
3342 if (!wcd939x->txdev) {
3343 dev_err(dev, "could not find txslave with matching of node\n");
3344 ret = -EINVAL;
3345 goto err_put_rxdev;
3346 }
3347 wcd939x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd939x->txdev);
3348 wcd939x->sdw_priv[AIF1_CAP]->wcd939x = wcd939x;
3349 wcd939x->tx_sdw_dev = dev_to_sdw_dev(wcd939x->txdev);
3350
3351 /*
3352 * As TX is main CSR reg interface, which should not be suspended first.
3353 * explicitly add the dependency link
3354 */
3355 if (!device_link_add(wcd939x->rxdev, wcd939x->txdev, DL_FLAG_STATELESS |
3356 DL_FLAG_PM_RUNTIME)) {
3357 dev_err(dev, "could not devlink tx and rx\n");
3358 ret = -EINVAL;
3359 goto err_put_txdev;
3360 }
3361
3362 if (!device_link_add(dev, wcd939x->txdev, DL_FLAG_STATELESS |
3363 DL_FLAG_PM_RUNTIME)) {
3364 dev_err(dev, "could not devlink wcd and tx\n");
3365 ret = -EINVAL;
3366 goto err_remove_rxtx_link;
3367 }
3368
3369 if (!device_link_add(dev, wcd939x->rxdev, DL_FLAG_STATELESS |
3370 DL_FLAG_PM_RUNTIME)) {
3371 dev_err(dev, "could not devlink wcd and rx\n");
3372 ret = -EINVAL;
3373 goto err_remove_tx_link;
3374 }
3375
3376 /* Get regmap from TX SoundWire device */
3377 wcd939x->regmap = wcd939x->sdw_priv[AIF1_CAP]->regmap;
3378 if (!wcd939x->regmap) {
3379 dev_err(dev, "could not get TX device regmap\n");
3380 ret = -ENODEV;
3381 goto err_remove_rx_link;
3382 }
3383
3384 ret = wcd939x_irq_init(wcd939x, dev);
3385 if (ret) {
3386 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret);
3387 goto err_remove_rx_link;
3388 }
3389
3390 wcd939x->sdw_priv[AIF1_PB]->slave_irq = wcd939x->virq;
3391 wcd939x->sdw_priv[AIF1_CAP]->slave_irq = wcd939x->virq;
3392
3393 wcd939x_set_micbias_data(dev, wcd939x);
3394
3395 /* Check WCD9395 version */
3396 regmap_read(wcd939x->regmap, WCD939X_DIGITAL_CHIP_ID1, &id1);
3397 regmap_read(wcd939x->regmap, WCD939X_EAR_STATUS_REG_1, &status1);
3398
3399 if (id1 == CHIPID_WCD939X_VER_MAJOR_1)
3400 version = ((status1 & CHIPID_WCD939X_VER_MINOR_1) ? WCD939X_VERSION_1_1 : WCD939X_VERSION_1_0);
3401 else
3402 version = WCD939X_VERSION_2_0;
3403
3404 dev_dbg(dev, "wcd939x version: %s\n", version_to_str(version));
3405
3406 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd939x,
3407 wcd939x_dais, ARRAY_SIZE(wcd939x_dais));
3408 if (ret) {
3409 dev_err(dev, "%s: Codec registration failed\n",
3410 __func__);
3411 goto err_remove_rx_link;
3412 }
3413
3414 return 0;
3415
3416 err_remove_rx_link:
3417 device_link_remove(dev, wcd939x->rxdev);
3418 err_remove_tx_link:
3419 device_link_remove(dev, wcd939x->txdev);
3420 err_remove_rxtx_link:
3421 device_link_remove(wcd939x->rxdev, wcd939x->txdev);
3422 err_put_txdev:
3423 put_device(wcd939x->txdev);
3424 err_put_rxdev:
3425 put_device(wcd939x->rxdev);
3426 err_unbind:
3427 component_unbind_all(dev, wcd939x);
3428 err_put_typec_switch:
3429 #if IS_ENABLED(CONFIG_TYPEC)
3430 if (wcd939x->typec_analog_mux)
3431 typec_switch_put(wcd939x->typec_switch);
3432 #endif /* CONFIG_TYPEC */
3433
3434 return ret;
3435 }
3436
wcd939x_unbind(struct device * dev)3437 static void wcd939x_unbind(struct device *dev)
3438 {
3439 struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
3440
3441 snd_soc_unregister_component(dev);
3442 device_link_remove(dev, wcd939x->txdev);
3443 device_link_remove(dev, wcd939x->rxdev);
3444 device_link_remove(wcd939x->rxdev, wcd939x->txdev);
3445 put_device(wcd939x->txdev);
3446 put_device(wcd939x->rxdev);
3447 component_unbind_all(dev, wcd939x);
3448 }
3449
3450 static const struct component_master_ops wcd939x_comp_ops = {
3451 .bind = wcd939x_bind,
3452 .unbind = wcd939x_unbind,
3453 };
3454
wcd939x_typec_mux_unregister(void * data)3455 static void __maybe_unused wcd939x_typec_mux_unregister(void *data)
3456 {
3457 struct typec_mux_dev *typec_mux = data;
3458
3459 typec_mux_unregister(typec_mux);
3460 }
3461
wcd939x_typec_switch_unregister(void * data)3462 static void __maybe_unused wcd939x_typec_switch_unregister(void *data)
3463 {
3464 struct typec_switch_dev *typec_sw = data;
3465
3466 typec_switch_unregister(typec_sw);
3467 }
3468
wcd939x_add_typec(struct wcd939x_priv * wcd939x,struct device * dev)3469 static int wcd939x_add_typec(struct wcd939x_priv *wcd939x, struct device *dev)
3470 {
3471 #if IS_ENABLED(CONFIG_TYPEC)
3472 int ret;
3473 struct typec_mux_dev *typec_mux;
3474 struct typec_switch_dev *typec_sw;
3475 struct typec_mux_desc mux_desc = {
3476 .drvdata = wcd939x,
3477 .fwnode = dev_fwnode(dev),
3478 .set = wcd939x_typec_mux_set,
3479 };
3480 struct typec_switch_desc sw_desc = {
3481 .drvdata = wcd939x,
3482 .fwnode = dev_fwnode(dev),
3483 .set = wcd939x_typec_switch_set,
3484 };
3485
3486 /*
3487 * Is USBSS is used to mux analog lines,
3488 * register a typec mux/switch to get typec events
3489 */
3490 if (!wcd939x->typec_analog_mux)
3491 return 0;
3492
3493 typec_mux = typec_mux_register(dev, &mux_desc);
3494 if (IS_ERR(typec_mux))
3495 return dev_err_probe(dev, PTR_ERR(typec_mux),
3496 "failed to register typec mux\n");
3497
3498 ret = devm_add_action_or_reset(dev, wcd939x_typec_mux_unregister,
3499 typec_mux);
3500 if (ret)
3501 return ret;
3502
3503 typec_sw = typec_switch_register(dev, &sw_desc);
3504 if (IS_ERR(typec_sw))
3505 return dev_err_probe(dev, PTR_ERR(typec_sw),
3506 "failed to register typec switch\n");
3507
3508 ret = devm_add_action_or_reset(dev, wcd939x_typec_switch_unregister,
3509 typec_sw);
3510 if (ret)
3511 return ret;
3512 #endif
3513
3514 return 0;
3515 }
3516
wcd939x_add_slave_components(struct wcd939x_priv * wcd939x,struct device * dev,struct component_match ** matchptr)3517 static int wcd939x_add_slave_components(struct wcd939x_priv *wcd939x,
3518 struct device *dev,
3519 struct component_match **matchptr)
3520 {
3521 struct device_node *np = dev->of_node;
3522
3523 wcd939x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0);
3524 if (!wcd939x->rxnode) {
3525 dev_err(dev, "%s: Rx-device node not defined\n", __func__);
3526 return -ENODEV;
3527 }
3528
3529 component_match_add_release(dev, matchptr, component_release_of,
3530 component_compare_of, wcd939x->rxnode);
3531
3532 wcd939x->txnode = of_parse_phandle(np, "qcom,tx-device", 0);
3533 if (!wcd939x->txnode) {
3534 dev_err(dev, "%s: Tx-device node not defined\n", __func__);
3535 return -ENODEV;
3536 }
3537
3538 component_match_add_release(dev, matchptr, component_release_of,
3539 component_compare_of, wcd939x->txnode);
3540 return 0;
3541 }
3542
wcd939x_probe(struct platform_device * pdev)3543 static int wcd939x_probe(struct platform_device *pdev)
3544 {
3545 struct component_match *match = NULL;
3546 struct wcd939x_priv *wcd939x = NULL;
3547 struct device *dev = &pdev->dev;
3548 int ret;
3549
3550 wcd939x = devm_kzalloc(dev, sizeof(struct wcd939x_priv),
3551 GFP_KERNEL);
3552 if (!wcd939x)
3553 return -ENOMEM;
3554
3555 dev_set_drvdata(dev, wcd939x);
3556 mutex_init(&wcd939x->micb_lock);
3557 wcd939x->common.dev = dev;
3558 wcd939x->common.max_bias = 4;
3559
3560 ret = wcd939x_populate_dt_data(wcd939x, dev);
3561 if (ret) {
3562 dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
3563 return -EINVAL;
3564 }
3565
3566 ret = wcd939x_add_typec(wcd939x, dev);
3567 if (ret)
3568 return ret;
3569
3570 ret = wcd939x_add_slave_components(wcd939x, dev, &match);
3571 if (ret)
3572 return ret;
3573
3574 wcd939x_reset(wcd939x);
3575
3576 ret = component_master_add_with_match(dev, &wcd939x_comp_ops, match);
3577 if (ret)
3578 return ret;
3579
3580 pm_runtime_set_autosuspend_delay(dev, 1000);
3581 pm_runtime_use_autosuspend(dev);
3582 pm_runtime_mark_last_busy(dev);
3583 pm_runtime_set_active(dev);
3584 pm_runtime_enable(dev);
3585 pm_runtime_idle(dev);
3586
3587 return 0;
3588 }
3589
wcd939x_remove(struct platform_device * pdev)3590 static void wcd939x_remove(struct platform_device *pdev)
3591 {
3592 struct device *dev = &pdev->dev;
3593
3594 component_master_del(dev, &wcd939x_comp_ops);
3595
3596 pm_runtime_disable(dev);
3597 pm_runtime_set_suspended(dev);
3598 pm_runtime_dont_use_autosuspend(dev);
3599 }
3600
3601 #if defined(CONFIG_OF)
3602 static const struct of_device_id wcd939x_dt_match[] = {
3603 { .compatible = "qcom,wcd9390-codec" },
3604 { .compatible = "qcom,wcd9395-codec" },
3605 {}
3606 };
3607 MODULE_DEVICE_TABLE(of, wcd939x_dt_match);
3608 #endif
3609
3610 static struct platform_driver wcd939x_codec_driver = {
3611 .probe = wcd939x_probe,
3612 .remove = wcd939x_remove,
3613 .driver = {
3614 .name = "wcd939x_codec",
3615 .of_match_table = of_match_ptr(wcd939x_dt_match),
3616 .suppress_bind_attrs = true,
3617 },
3618 };
3619
3620 module_platform_driver(wcd939x_codec_driver);
3621 MODULE_DESCRIPTION("WCD939X Codec driver");
3622 MODULE_LICENSE("GPL");
3623