1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/reset.h> 13 #include <linux/timer.h> 14 15 #include <drm/drm_print.h> 16 17 #include "vc4_drv.h" 18 #include "vc4_regs.h" 19 20 static const struct debugfs_reg32 v3d_regs[] = { 21 VC4_REG32(V3D_IDENT0), 22 VC4_REG32(V3D_IDENT1), 23 VC4_REG32(V3D_IDENT2), 24 VC4_REG32(V3D_SCRATCH), 25 VC4_REG32(V3D_L2CACTL), 26 VC4_REG32(V3D_SLCACTL), 27 VC4_REG32(V3D_INTCTL), 28 VC4_REG32(V3D_INTENA), 29 VC4_REG32(V3D_INTDIS), 30 VC4_REG32(V3D_CT0CS), 31 VC4_REG32(V3D_CT1CS), 32 VC4_REG32(V3D_CT0EA), 33 VC4_REG32(V3D_CT1EA), 34 VC4_REG32(V3D_CT0CA), 35 VC4_REG32(V3D_CT1CA), 36 VC4_REG32(V3D_CT00RA0), 37 VC4_REG32(V3D_CT01RA0), 38 VC4_REG32(V3D_CT0LC), 39 VC4_REG32(V3D_CT1LC), 40 VC4_REG32(V3D_CT0PC), 41 VC4_REG32(V3D_CT1PC), 42 VC4_REG32(V3D_PCS), 43 VC4_REG32(V3D_BFC), 44 VC4_REG32(V3D_RFC), 45 VC4_REG32(V3D_BPCA), 46 VC4_REG32(V3D_BPCS), 47 VC4_REG32(V3D_BPOA), 48 VC4_REG32(V3D_BPOS), 49 VC4_REG32(V3D_BXCF), 50 VC4_REG32(V3D_SQRSV0), 51 VC4_REG32(V3D_SQRSV1), 52 VC4_REG32(V3D_SQCNTL), 53 VC4_REG32(V3D_SRQPC), 54 VC4_REG32(V3D_SRQUA), 55 VC4_REG32(V3D_SRQUL), 56 VC4_REG32(V3D_SRQCS), 57 VC4_REG32(V3D_VPACNTL), 58 VC4_REG32(V3D_VPMBASE), 59 VC4_REG32(V3D_PCTRC), 60 VC4_REG32(V3D_PCTRE), 61 VC4_REG32(V3D_PCTR(0)), 62 VC4_REG32(V3D_PCTRS(0)), 63 VC4_REG32(V3D_PCTR(1)), 64 VC4_REG32(V3D_PCTRS(1)), 65 VC4_REG32(V3D_PCTR(2)), 66 VC4_REG32(V3D_PCTRS(2)), 67 VC4_REG32(V3D_PCTR(3)), 68 VC4_REG32(V3D_PCTRS(3)), 69 VC4_REG32(V3D_PCTR(4)), 70 VC4_REG32(V3D_PCTRS(4)), 71 VC4_REG32(V3D_PCTR(5)), 72 VC4_REG32(V3D_PCTRS(5)), 73 VC4_REG32(V3D_PCTR(6)), 74 VC4_REG32(V3D_PCTRS(6)), 75 VC4_REG32(V3D_PCTR(7)), 76 VC4_REG32(V3D_PCTRS(7)), 77 VC4_REG32(V3D_PCTR(8)), 78 VC4_REG32(V3D_PCTRS(8)), 79 VC4_REG32(V3D_PCTR(9)), 80 VC4_REG32(V3D_PCTRS(9)), 81 VC4_REG32(V3D_PCTR(10)), 82 VC4_REG32(V3D_PCTRS(10)), 83 VC4_REG32(V3D_PCTR(11)), 84 VC4_REG32(V3D_PCTRS(11)), 85 VC4_REG32(V3D_PCTR(12)), 86 VC4_REG32(V3D_PCTRS(12)), 87 VC4_REG32(V3D_PCTR(13)), 88 VC4_REG32(V3D_PCTRS(13)), 89 VC4_REG32(V3D_PCTR(14)), 90 VC4_REG32(V3D_PCTRS(14)), 91 VC4_REG32(V3D_PCTR(15)), 92 VC4_REG32(V3D_PCTRS(15)), 93 VC4_REG32(V3D_DBGE), 94 VC4_REG32(V3D_FDBGO), 95 VC4_REG32(V3D_FDBGB), 96 VC4_REG32(V3D_FDBGR), 97 VC4_REG32(V3D_FDBGS), 98 VC4_REG32(V3D_ERRSTAT), 99 }; 100 101 static int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused) 102 { 103 struct drm_debugfs_entry *entry = m->private; 104 struct drm_device *dev = entry->dev; 105 struct vc4_dev *vc4 = to_vc4_dev(dev); 106 int ret = vc4_v3d_pm_get(vc4); 107 108 if (ret == 0) { 109 uint32_t ident1 = V3D_READ(V3D_IDENT1); 110 uint32_t nslc = VC4_GET_FIELD(ident1, V3D_IDENT1_NSLC); 111 uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS); 112 uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS); 113 114 seq_printf(m, "Revision: %d\n", 115 VC4_GET_FIELD(ident1, V3D_IDENT1_REV)); 116 seq_printf(m, "Slices: %d\n", nslc); 117 seq_printf(m, "TMUs: %d\n", nslc * tups); 118 seq_printf(m, "QPUs: %d\n", nslc * qups); 119 seq_printf(m, "Semaphores: %d\n", 120 VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM)); 121 vc4_v3d_pm_put(vc4); 122 } 123 124 return 0; 125 } 126 127 int 128 vc4_v3d_pm_get(struct vc4_dev *vc4) 129 { 130 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) 131 return -ENODEV; 132 133 return pm_runtime_resume_and_get(&vc4->v3d->pdev->dev); 134 } 135 136 void 137 vc4_v3d_pm_put(struct vc4_dev *vc4) 138 { 139 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) 140 return; 141 142 pm_runtime_put_autosuspend(&vc4->v3d->pdev->dev); 143 } 144 145 void vc4_v3d_init_hw(struct drm_device *dev) 146 { 147 struct vc4_dev *vc4 = to_vc4_dev(dev); 148 149 /* Take all the memory that would have been reserved for user 150 * QPU programs, since we don't have an interface for running 151 * them, anyway. 152 */ 153 V3D_WRITE(V3D_VPMBASE, 0); 154 } 155 156 static int bin_slot_try_alloc(struct vc4_dev *vc4) 157 { 158 int slot; 159 160 guard(spinlock_irqsave)(&vc4->job_lock); 161 162 slot = ffs(~vc4->bin_alloc_used); 163 if (slot != 0) { 164 /* Switch from ffs() bit index to a 0-based index. */ 165 slot--; 166 vc4->bin_alloc_used |= BIT(slot); 167 } else { 168 slot = -ENOMEM; 169 } 170 171 return slot; 172 } 173 174 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4, long timeout) 175 { 176 int slot; 177 long ret; 178 179 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) 180 return -ENODEV; 181 182 /* If the pool is full, wait for a job to release its slots. */ 183 ret = wait_event_interruptible_timeout(vc4->job_wait_queue, 184 (slot = bin_slot_try_alloc(vc4)) >= 0, 185 timeout); 186 if (ret < 0) 187 return ret; 188 if (ret == 0) 189 return -ENOMEM; 190 191 return slot; 192 } 193 194 /* 195 * bin_bo_alloc() - allocates the memory that will be used for 196 * tile binning. 197 * 198 * The binner has a limitation that the addresses in the tile state 199 * buffer that point into the tile alloc buffer or binner overflow 200 * memory only have 28 bits (256MB), and the top 4 on the bus for 201 * tile alloc references end up coming from the tile state buffer's 202 * address. 203 * 204 * To work around this, we allocate a single large buffer while V3D is 205 * in use, make sure that it has the top 4 bits constant across its 206 * entire extent, and then put the tile state, tile alloc, and binner 207 * overflow memory inside that buffer. 208 * 209 * This creates a limitation where we may not be able to execute a job 210 * if it doesn't fit within the buffer that we allocated up front. 211 * However, it turns out that 16MB is "enough for anybody", and 212 * real-world applications run into allocation failures from the 213 * overall DMA pool before they make scenes complicated enough to run 214 * out of bin space. 215 */ 216 static int bin_bo_alloc(struct vc4_dev *vc4) 217 { 218 struct vc4_v3d *v3d = vc4->v3d; 219 uint32_t size = 16 * 1024 * 1024; 220 int ret = 0; 221 struct list_head list; 222 223 if (!v3d) 224 return -ENODEV; 225 226 /* We may need to try allocating more than once to get a BO 227 * that doesn't cross 256MB. Track the ones we've allocated 228 * that failed so far, so that we can free them when we've got 229 * one that succeeded (if we freed them right away, our next 230 * allocation would probably be the same chunk of memory). 231 */ 232 INIT_LIST_HEAD(&list); 233 234 while (true) { 235 struct vc4_bo *bo = vc4_bo_create(&vc4->base, size, true, 236 VC4_BO_TYPE_BIN); 237 238 if (IS_ERR(bo)) { 239 ret = PTR_ERR(bo); 240 241 dev_err(&v3d->pdev->dev, 242 "Failed to allocate memory for tile binning: " 243 "%d. You may need to enable DMA or give it " 244 "more memory.", 245 ret); 246 break; 247 } 248 249 /* Check if this BO won't trigger the addressing bug. */ 250 if ((bo->base.dma_addr & 0xf0000000) == 251 ((bo->base.dma_addr + bo->base.base.size - 1) & 0xf0000000)) { 252 vc4->bin_bo = bo; 253 254 /* Set up for allocating 512KB chunks of 255 * binner memory. The biggest allocation we 256 * need to do is for the initial tile alloc + 257 * tile state buffer. We can render to a 258 * maximum of ((2048*2048) / (32*32) = 4096 259 * tiles in a frame (until we do floating 260 * point rendering, at which point it would be 261 * 8192). Tile state is 48b/tile (rounded to 262 * a page), and tile alloc is 32b/tile 263 * (rounded to a page), plus a page of extra, 264 * for a total of 320kb for our worst-case. 265 * We choose 512kb so that it divides evenly 266 * into our 16MB, and the rest of the 512kb 267 * will be used as storage for the overflow 268 * from the initial 32b CL per bin. 269 */ 270 vc4->bin_alloc_size = 512 * 1024; 271 vc4->bin_alloc_used = 0; 272 vc4->bin_alloc_overflow = 0; 273 WARN_ON_ONCE(sizeof(vc4->bin_alloc_used) * 8 != 274 bo->base.base.size / vc4->bin_alloc_size); 275 276 kref_init(&vc4->bin_bo_kref); 277 278 /* Enable the out-of-memory interrupt to set our 279 * newly-allocated binner BO, potentially from an 280 * already-pending-but-masked interrupt. 281 */ 282 V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM); 283 284 break; 285 } 286 287 /* Put it on the list to free later, and try again. */ 288 list_add(&bo->unref_head, &list); 289 } 290 291 /* Free all the BOs we allocated but didn't choose. */ 292 while (!list_empty(&list)) { 293 struct vc4_bo *bo = list_last_entry(&list, 294 struct vc4_bo, unref_head); 295 296 list_del(&bo->unref_head); 297 drm_gem_object_put(&bo->base.base); 298 } 299 300 return ret; 301 } 302 303 int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used) 304 { 305 int ret = 0; 306 307 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) 308 return -ENODEV; 309 310 mutex_lock(&vc4->bin_bo_lock); 311 312 if (used && *used) 313 goto complete; 314 315 if (vc4->bin_bo) 316 kref_get(&vc4->bin_bo_kref); 317 else 318 ret = bin_bo_alloc(vc4); 319 320 if (ret == 0 && used) 321 *used = true; 322 323 complete: 324 mutex_unlock(&vc4->bin_bo_lock); 325 326 return ret; 327 } 328 329 static void bin_bo_release(struct kref *ref) 330 { 331 struct vc4_dev *vc4 = container_of(ref, struct vc4_dev, bin_bo_kref); 332 333 if (WARN_ON_ONCE(!vc4->bin_bo)) 334 return; 335 336 drm_gem_object_put(&vc4->bin_bo->base.base); 337 vc4->bin_bo = NULL; 338 } 339 340 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4) 341 { 342 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) 343 return; 344 345 mutex_lock(&vc4->bin_bo_lock); 346 kref_put(&vc4->bin_bo_kref, bin_bo_release); 347 mutex_unlock(&vc4->bin_bo_lock); 348 } 349 350 #ifdef CONFIG_PM 351 static int vc4_v3d_runtime_suspend(struct device *dev) 352 { 353 struct vc4_v3d *v3d = dev_get_drvdata(dev); 354 struct vc4_dev *vc4 = v3d->vc4; 355 356 vc4_irq_disable(&vc4->base); 357 358 clk_disable_unprepare(v3d->clk); 359 360 return 0; 361 } 362 363 static int vc4_v3d_runtime_resume(struct device *dev) 364 { 365 struct vc4_v3d *v3d = dev_get_drvdata(dev); 366 struct vc4_dev *vc4 = v3d->vc4; 367 int ret; 368 369 ret = clk_prepare_enable(v3d->clk); 370 if (ret != 0) 371 return ret; 372 373 vc4_v3d_init_hw(&vc4->base); 374 375 vc4_irq_enable(&vc4->base); 376 enable_irq(vc4->irq); 377 378 return 0; 379 } 380 #endif 381 382 int vc4_v3d_debugfs_init(struct drm_minor *minor) 383 { 384 struct drm_device *drm = minor->dev; 385 struct vc4_dev *vc4 = to_vc4_dev(drm); 386 struct vc4_v3d *v3d = vc4->v3d; 387 388 if (!vc4->v3d) 389 return -ENODEV; 390 391 drm_debugfs_add_file(drm, "v3d_ident", vc4_v3d_debugfs_ident, NULL); 392 393 vc4_debugfs_add_regset32(drm, "v3d_regs", &v3d->regset); 394 395 return 0; 396 } 397 398 static int vc4_v3d_bind(struct device *dev, struct device *master, void *data) 399 { 400 struct platform_device *pdev = to_platform_device(dev); 401 struct drm_device *drm = dev_get_drvdata(master); 402 struct vc4_dev *vc4 = to_vc4_dev(drm); 403 struct vc4_v3d *v3d = NULL; 404 int ret; 405 406 v3d = devm_kzalloc(&pdev->dev, sizeof(*v3d), GFP_KERNEL); 407 if (!v3d) 408 return -ENOMEM; 409 410 dev_set_drvdata(dev, v3d); 411 412 v3d->pdev = pdev; 413 414 v3d->regs = vc4_ioremap_regs(pdev, 0); 415 if (IS_ERR(v3d->regs)) 416 return PTR_ERR(v3d->regs); 417 v3d->regset.base = v3d->regs; 418 v3d->regset.regs = v3d_regs; 419 v3d->regset.nregs = ARRAY_SIZE(v3d_regs); 420 421 vc4->v3d = v3d; 422 v3d->vc4 = vc4; 423 424 /* 425 * In headless setups where HVS is absent, use V3D as the fallback 426 * DMA controller for buffer allocations. 427 */ 428 if (drm_dev_dma_dev(drm) == drm->dev) 429 drm_dev_set_dma_dev(drm, dev); 430 431 v3d->clk = devm_clk_get_optional(dev, NULL); 432 if (IS_ERR(v3d->clk)) 433 return dev_err_probe(dev, PTR_ERR(v3d->clk), "Failed to get V3D clock\n"); 434 435 v3d->reset = devm_reset_control_get_optional_exclusive(dev, NULL); 436 if (IS_ERR(v3d->reset)) 437 return dev_err_probe(dev, PTR_ERR(v3d->reset), 438 "Failed to get reset control\n"); 439 440 if (!v3d->reset) 441 drm_warn(drm, "No V3D reset line in the device tree"); 442 443 ret = platform_get_irq(pdev, 0); 444 if (ret < 0) 445 return ret; 446 vc4->irq = ret; 447 448 ret = vc4_irq_install(drm, vc4->irq); 449 if (ret) { 450 drm_err(drm, "Failed to install IRQ handler\n"); 451 return ret; 452 } 453 454 ret = devm_pm_runtime_enable(dev); 455 if (ret) 456 return ret; 457 458 ret = pm_runtime_resume_and_get(dev); 459 if (ret) 460 return ret; 461 462 if (V3D_READ(V3D_IDENT0) != V3D_EXPECTED_IDENT0) { 463 drm_err(drm, "V3D_IDENT0 read 0x%08x instead of 0x%08x\n", 464 V3D_READ(V3D_IDENT0), V3D_EXPECTED_IDENT0); 465 ret = -EINVAL; 466 goto err_put_runtime_pm; 467 } 468 469 /* Reset the binner overflow address/size at setup, to be sure 470 * we don't reuse an old one. 471 */ 472 V3D_WRITE(V3D_BPOA, 0); 473 V3D_WRITE(V3D_BPOS, 0); 474 475 pm_runtime_use_autosuspend(dev); 476 pm_runtime_set_autosuspend_delay(dev, 40); /* a little over 2 frames. */ 477 pm_runtime_put_autosuspend(dev); 478 479 return 0; 480 481 err_put_runtime_pm: 482 pm_runtime_put(dev); 483 484 return ret; 485 } 486 487 static void vc4_v3d_unbind(struct device *dev, struct device *master, 488 void *data) 489 { 490 struct drm_device *drm = data; 491 struct vc4_dev *vc4 = to_vc4_dev(drm); 492 493 /* A straggler vc4_reset() re-enables the interrupt. */ 494 timer_shutdown_sync(&vc4->hangcheck.timer); 495 cancel_work_sync(&vc4->hangcheck.reset_work); 496 497 vc4_irq_uninstall(drm); 498 499 /* Flush rather than cancel, so queued completions release their jobs. */ 500 flush_work(&vc4->job_done_work); 501 502 /* Disable the binner's overflow memory address, so the next 503 * driver probe (if any) doesn't try to reuse our old 504 * allocation. 505 */ 506 V3D_WRITE(V3D_BPOA, 0); 507 V3D_WRITE(V3D_BPOS, 0); 508 509 vc4->v3d = NULL; 510 } 511 512 static const struct dev_pm_ops vc4_v3d_pm_ops = { 513 SET_RUNTIME_PM_OPS(vc4_v3d_runtime_suspend, vc4_v3d_runtime_resume, NULL) 514 }; 515 516 static const struct component_ops vc4_v3d_ops = { 517 .bind = vc4_v3d_bind, 518 .unbind = vc4_v3d_unbind, 519 }; 520 521 static int vc4_v3d_dev_probe(struct platform_device *pdev) 522 { 523 return component_add(&pdev->dev, &vc4_v3d_ops); 524 } 525 526 static void vc4_v3d_dev_remove(struct platform_device *pdev) 527 { 528 component_del(&pdev->dev, &vc4_v3d_ops); 529 } 530 531 const struct of_device_id vc4_v3d_dt_match[] = { 532 { .compatible = "brcm,bcm2835-v3d" }, 533 { .compatible = "brcm,cygnus-v3d" }, 534 {} 535 }; 536 537 struct platform_driver vc4_v3d_driver = { 538 .probe = vc4_v3d_dev_probe, 539 .remove = vc4_v3d_dev_remove, 540 .driver = { 541 .name = "vc4_v3d", 542 .of_match_table = vc4_v3d_dt_match, 543 .pm = &vc4_v3d_pm_ops, 544 }, 545 }; 546